Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins

KAUST Repository

Diab, Amer El Hajj

2014-12-01

We report the temperature dependence of the core electrical parameters and transport characteristics of a flexible version of fin field-effect transistor (FinFET) on silicon-on-insulator (SOI) with sub-20-nm wide fins and high-k/metal gate-stacks. For the first time, we characterize them from room to high temperature (150 °C) to show the impact of temperature variation on drain current, gate leakage current, and transconductance. Variation of extracted parameters, such as low-field mobility, subthreshold swing, threshold voltage, and ON-OFF current characteristics, is reported too. Direct comparison is made to a rigid version of the SOI FinFETs. The mobility degradation with temperature is mainly caused by phonon scattering mechanism. The overall excellent devices performance at high temperature after release is outlined proving the suitability of truly high-performance flexible inorganic electronics with such advanced architecture.

High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

International Nuclear Information System (INIS)

Caër, Charles; Le Roux, Xavier; Cassan, Eric

2013-01-01

We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

International Nuclear Information System (INIS)

Fu Qiang; Zhang Wan-Rong; Jin Dong-Yue; Zhao Yan-Xiao; Wang Xiao

2016-01-01

The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness ( T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer

An SEU resistant 256K SOI SRAM

Science.gov (United States)

Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

1992-12-01

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

Worst-Case Bias During Total Dose Irradiation of SOI Transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

2000-01-01

The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

Science.gov (United States)

Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

2016-12-01

The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

Conventional P-ω/Q-V Droop Control in Highly Resistive Line of Low-Voltage Converter-Based AC Microgrid

DEFF Research Database (Denmark)

Hou, Xiaochao; Sun, Yao; Yuan, Wenbin

2016-01-01

-ω/Q-V droop control is adopted in the low-voltage AC microgrid. As a result, the active power sharing among the distributed generators (DGs) is easily obtained without communication. More importantly, this study clears up the previous misunderstanding that conventional P-ω/Q-V droop control is only applicable...... to microgrids with highly inductive lines, and lays a foundation for the application of conventional droop control under different line impedances. Moreover, in order to guarantee the accurate reactive power sharing, a guide for designing Q-V droop gains is given, and virtual resistance is adopted to shape......In low-voltage converter-based alternating current (AC) microgrids with resistive distribution lines, the P-V droop with Q-f boost (VPD/FQB) is the most common method for load sharing. However, it cannot achieve the active power sharing proportionally. To overcome this drawback, the conventional P...

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

Science.gov (United States)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

Science.gov (United States)

Saramekala, G. K.; Santra, Abirmoya; Dubey, Sarvesh; Jit, Satyabrata; Tiwari, Pramod Kumar

2013-08-01

In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

Conventional P-ω/Q-V Droop Control in Highly Resistive Line of Low-Voltage Converter-Based AC Microgrid

Directory of Open Access Journals (Sweden)

Xiaochao Hou

2016-11-01

Full Text Available In low-voltage converter-based alternating current (AC microgrids with resistive distribution lines, the P-V droop with Q-f boost (VPD/FQB is the most common method for load sharing. However, it cannot achieve the active power sharing proportionally. To overcome this drawback, the conventional P-ω/Q-V droop control is adopted in the low-voltage AC microgrid. As a result, the active power sharing among the distributed generators (DGs is easily obtained without communication. More importantly, this study clears up the previous misunderstanding that conventional P-ω/Q-V droop control is only applicable to microgrids with highly inductive lines, and lays a foundation for the application of conventional droop control under different line impedances. Moreover, in order to guarantee the accurate reactive power sharing, a guide for designing Q-V droop gains is given, and virtual resistance is adopted to shape the desired output impedance. Finally, the effects of power sharing and transient response are verified through simulations and experiments in converter-based AC Microgrid.

A novel SOI pressure sensor for high temperature application

International Nuclear Information System (INIS)

Li Sainan; Liang Ting; Wang Wei; Hong Yingping; Zheng Tingli; Xiong Jijun

2015-01-01

The silicon on insulator (SOI) high temperature pressure sensor is a novel pressure sensor with high-performance and high-quality. A structure of a SOI high-temperature pressure sensor is presented in this paper. The key factors including doping concentration and power are analyzed. The process of the sensor is designed with the critical process parameters set appropriately. The test result at room temperature and high temperature shows that nonlinear error below is 0.1%, and hysteresis is less than 0.5%. High temperature measuring results show that the sensor can be used for from room temperature to 350 °C in harsh environments. It offers a reference for the development of high temperature piezoresistive pressure sensors. (semiconductor devices)

SOI MESFETs on high-resistivity, trap-rich substrates

Science.gov (United States)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

Science.gov (United States)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

International Nuclear Information System (INIS)

Zhang Wen-Tong; Wu Li-Juan; Qiao Ming; Luo Xiao-Rong; Zhang Bo; Li Zhao-Ji

2012-01-01

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and −587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

New Role of P/Q-type Voltage-gated Calcium Channels

DEFF Research Database (Denmark)

Hansen, Pernille B L

2015-01-01

Voltage-gated calcium channels are important for the depolarization-evoked contraction of vascular smooth muscle cells (SMCs), with L-type channels being the classical channel involved in this mechanism. However, it has been demonstrated that the CaV2.1 subunit, which encodes a neuronal isoform...... of the voltage-gated calcium channels (P/Q-type), is also expressed and contributes functionally to contraction of renal blood vessels in both mice and humans. Furthermore, preglomerular vascular SMCs and aortic SMCs coexpress L-, P-, and Q-type calcium channels within the same cell. Calcium channel blockers...... are widely used as pharmacological treatments. However, calcium channel antagonists vary in their selectivity for the various calcium channel subtypes, and the functional contribution from P/Q-type channels as compared with L-type should be considered. Confirming the presence of P/Q-type voltage...

Total dose radiation effects of pressure sensors fabricated on uni-bond-SOI materials

International Nuclear Information System (INIS)

Zhu Shiyang; Huang Yiping; Wang Jin; Li Anzhen; Shen Shaoqun; Bao Minhang

2001-01-01

Piezoresistive pressure sensors with a twin-island structure were successfully fabricated using high quality Uni-bond-SOI (On Insulator) materials. Since the piezoresistors were structured by the single crystalline silicon overlayer of the SOI wafer and were totally isolated by the buried SiO 2 , the sensors are radiation-hard. The sensitivity and the linearity of the pressure sensors keep their original values after being irradiated by 60 Co γ-rays up to 2.3 x 10 4 Gy(H 2 O). However, the offset voltage of the sensor has a slight drift, increasing with the radiation dose. The absolute value of the offset voltage deviation depends on the pressure sensor itself. For comparison, corresponding polysilicon pressure sensors were fabricated using the similar process and irradiated at the same condition

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

Science.gov (United States)

Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

2000-08-01

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

Formation of SIMOX–SOI structure by high-temperature oxygen implantation

International Nuclear Information System (INIS)

Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

2015-01-01

We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 10"1"7–10"1"8 ions/cm"2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO_2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO_2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

Compact Si-based asymmetric MZI waveguide on SOI as a thermo-optical switch

Science.gov (United States)

Rizal, C. S.; Niraula, B.

2018-03-01

A compact low power consuming asymmetric MZI based optical modulator with fast response time has been proposed on SOI platform. The geometrical and performance characteristics were analyzed in depth and optimized using coupled mode analysis and FDTD simulation tools, respectively. It was tested with and without implementation of thermo-optic (TO) effect. The device showed good frequency modulating characteristics when tested without the implementation of the TO effect. The fabricated device showed quality factor, Q ≈ 10,000, and this value is comparable to the Q of the device simulated with 25% transmission loss, showing FSR of 0.195 nm, FWHM ≈ 0.16 nm, and ER of 13 dB. With TO effect, it showed temperature sensitivity of 0.01 nm/°C and FSR of 0.19 nm. With the heater length of 4.18 mm, the device required 0.26 mW per π shift power with a switching voltage of 0.309 V, response time of 10 μ, and figure-of-merit of 2.6 mW μs. All of these characteristics make this device highly attractive for use in integrated Si photonics network as optical switch and wavelength modulator.

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

Science.gov (United States)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Total dose induced latch in short channel NMOS/SOI transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

1998-01-01

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

Research on SOI-based micro-resonator devices

Science.gov (United States)

Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

2010-10-01

SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6 - 1 V)

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Musseau, O.; Leray, J.L.; Faynot, O.; Raynaud, C.; Pelloie, J.L.

1999-01-01

In this paper, we presented two DTMOS architectures processed with a partially depleted SOI technology. The first architecture, DTMOS without limiting transistor, is dedicated to ultra-low voltage applications, at 0.6 V. For 1V applications, the second architecture, DTMOS with limiting transistor, needs an additional transistor to limit the body-source diode current. The total dose irradiation of both DTMOS architectures induces no change of the drain current, but an increase of the body-source diode current. Total dose induced trapped charge in the buried oxide increases the body potential of the DTMOS transistor. It induces an increase of the current flow at the back interface of the silicon film. Irradiation of complex circuits using DTMOS transistors would lead to a degradation of the stand-by consumption. (authors)

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Science.gov (United States)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

Science.gov (United States)

Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

2007-01-01

We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

Directory of Open Access Journals (Sweden)

Saeid Marjani

2016-09-01

Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

Science.gov (United States)

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

A graphene spin diode based on Rashba SOI

International Nuclear Information System (INIS)

Mohammadpour, Hakimeh

2015-01-01

In this paper a graphene-based two-terminal electronic device is modeled for application in spintronics. It is based on a gapped armchair graphene nanoribbon (GNR). The electron transport is considered through a scattering or channel region which is sandwiched between two lateral semi-infinite ferromagnetic leads. The two ferromagnetic leads, being half-metallic, are supposed to be in either parallel or anti-parallel magnetization. Meanwhile, the central channel region is a normal layer under the influence of the Rashba SOI, induced e.g., by the substrate. The device operation is based on modulating the (spin-) current by tuning the strength of the RSOI. The resultant current, being spin-polarized, is controlled by the RSOI in mutual interplay with the channel length. Inverting alternating bias voltage to a fully rectified spin-current is the main achievement of this paper. - Highlights: • Graphene-based electronic device is modeled with ferromagnetic leads. • The device operation is based on modulating the (spin-) current by Rashba SOI. • Inverting alternating bias voltage to rectified spin-current is the main achievement

A MEMS SOI-based piezoresistive fluid flow sensor

Science.gov (United States)

Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

2018-02-01

In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

Evaluation of the probability of arrester failure in a high-voltage transmission line using a Q learning artificial neural network model

International Nuclear Information System (INIS)

Ekonomou, L; Karampelas, P; Vita, V; Chatzarakis, G E

2011-01-01

One of the most popular methods of protecting high voltage transmission lines against lightning strikes and internal overvoltages is the use of arresters. The installation of arresters in high voltage transmission lines can prevent or even reduce the lines' failure rate. Several studies based on simulation tools have been presented in order to estimate the critical currents that exceed the arresters' rated energy stress and to specify the arresters' installation interval. In this work artificial intelligence, and more specifically a Q-learning artificial neural network (ANN) model, is addressed for evaluating the arresters' failure probability. The aims of the paper are to describe in detail the developed Q-learning ANN model and to compare the results obtained by its application in operating 150 kV Greek transmission lines with those produced using a simulation tool. The satisfactory and accurate results of the proposed ANN model can make it a valuable tool for designers of electrical power systems seeking more effective lightning protection, reducing operational costs and better continuity of service

Evaluation of the probability of arrester failure in a high-voltage transmission line using a Q learning artificial neural network model

Science.gov (United States)

Ekonomou, L.; Karampelas, P.; Vita, V.; Chatzarakis, G. E.

2011-04-01

One of the most popular methods of protecting high voltage transmission lines against lightning strikes and internal overvoltages is the use of arresters. The installation of arresters in high voltage transmission lines can prevent or even reduce the lines' failure rate. Several studies based on simulation tools have been presented in order to estimate the critical currents that exceed the arresters' rated energy stress and to specify the arresters' installation interval. In this work artificial intelligence, and more specifically a Q-learning artificial neural network (ANN) model, is addressed for evaluating the arresters' failure probability. The aims of the paper are to describe in detail the developed Q-learning ANN model and to compare the results obtained by its application in operating 150 kV Greek transmission lines with those produced using a simulation tool. The satisfactory and accurate results of the proposed ANN model can make it a valuable tool for designers of electrical power systems seeking more effective lightning protection, reducing operational costs and better continuity of service.

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Comparative study of SOI/Si hybrid substrates fabricated using high-dose and low-dose oxygen implantation

International Nuclear Information System (INIS)

Dong Yemin; Chen Meng; Chen Jing; Wang Xiang; Wang Xi

2004-01-01

Hybrid substrates comprising both silicon-on-insulator (SOI) and bulk Si regions have been fabricated using the technique of patterned separation by implantation of oxygen (SIMOX) with high-dose (1.5 x 10 18 cm -2 ) and low-dose ((1.5-3.5) x 10 17 cm -2 ) oxygen ions, respectively. Cross-sectional transmission electron microscopy (XTEM) was employed to examine the microstructures of the resulting materials. Experimental results indicate that the SOI/Si hybrid substrate fabricated using high-dose SIMOX is of inferior quality with very large surface height step and heavily damaged transitions between the SOI and bulk regions. However, the quality of the SOI/Si hybrid substrate is enhanced dramatically by reducing the implant dose. The defect density in transitions is reduced considerably. Moreover, the expected surface height difference does not exist and the surface is exceptionally flat. The possible mechanisms responsible for the improvements in quality are discussed

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

International Nuclear Information System (INIS)

Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

2011-01-01

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

Electronics and Sensor Study with the OKI SOI process

CERN Document Server

Arai, Yasuo

2007-01-01

While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Science.gov (United States)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

IBM-PC based high voltage controller [Paper No.: L7

International Nuclear Information System (INIS)

Mondal, N.K.; Kalmani, S.D.

1993-01-01

A simple IBM-PC/XT based high voltage controller is designed for C.A.E.N. high voltage supply unit, which is being used for testing the prototype detector for future accelerator experiment. The high voltage output of the supply unit can be remotely programmed. The V-set Lemo connectors at the rear panel provides the remote control facility. Similarly V-mon and I-mon can be used for remotely monitoring the voltage set and the current drawn from the supply unit. The controller described here sets the high voltage through V-set and monitors the voltage set, through V-mon at a pre-determined time interval. The monitoring is a background job and is done as an interrupt service routine of IRQ3. A simple menu driven software package used is written in Q-Basic and MASM. (author). 1 fig

Automotive SOI-BCD Technology Using Bonded Wafers

International Nuclear Information System (INIS)

Himi, H.; Fujino, S.

2008-01-01

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Ultrabroadband Hybrid III-V/SOI Grating Reflector for On-chip Lasers

DEFF Research Database (Denmark)

Park, Gyeong Cheol; Taghizadeh, Alireza; Chung, Il-Sug

2016-01-01

We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability.......We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability....

Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

International Nuclear Information System (INIS)

Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

2005-01-01

This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

International Nuclear Information System (INIS)

Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

2011-01-01

An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

Science.gov (United States)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications

Directory of Open Access Journals (Sweden)

Jader A. De Lima

2002-01-01

Full Text Available A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 μm single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm2. Measured resolution of encoding parameter α is better than 10% at 6 MHz and VDD = 3.3 V. Idle-mode consumption is 340 μW. Pulses of frequencies up to15 MHz and α =10% can be discriminated for 2.3 V ≤ VDD ≤ 3.3 V. Such an excellent immunity to VDD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2016-10-01

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

Science.gov (United States)

Diaz Llorente, C.; Le Royer, C.; Batude, P.; Fenouillet-Beranger, C.; Martinie, S.; Lu, C.-M. V.; Allain, F.; Colinge, J.-P.; Cristoloveanu, S.; Ghibaudo, G.; Vinet, M.

2018-06-01

This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

Characterizing SOI Wafers By Use Of AOTF-PHI

Science.gov (United States)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

VCSELs and silicon light sources exploiting SOI grating mirrors

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2012-01-01

In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

Science.gov (United States)

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Gate Engineering in SOI LDMOS for Device Reliability

Directory of Open Access Journals (Sweden)

Aanand

2016-01-01

Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

Heterojunction fully depleted SOI-TFET with oxide/source overlap

Science.gov (United States)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Impact of technology scaling in SOI back-channel total dose tolerance. A 2-D numerical study using a self-consistent oxide code; Effet du facteur d'echelle sur la tolerance en dose de rayonnement dans le cas du courant de fuite arriere des transistors MOS/SOI. Une etude d'un oxyde utilise un code auto coherent en deux dimensions

Energy Technology Data Exchange (ETDEWEB)

Leray, J.L.; Paillet, Ph.; Ferlet-Cavrois, V. [CEA Bruyeres le Chatel DRIF, 91 (France); Tavernier, C.; Belhaddad, K. [ISE Integrated System Engineering AG (Switzerland); Penzin, O. [ISE Integrated System Engineering Inc., San Jose (United States)

1999-07-01

A new 2-D and 3-D self-consistent code has been developed and is applied to understanding the charge trapping in SOI buried oxide causing back-channel MOS leakage in SOI transistors. Clear indications on scaling trends are obtained with respect to supply voltage and oxide thickness. (authors)

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Propriété de soi et indifférence morale du rapport à soi

Directory of Open Access Journals (Sweden)

Nathalie Maillard Romagnoli

2011-05-01

Full Text Available Je m’interroge dans cet article sur les implications du principe libertarien de la pleine propriété de soi sur la question du rapport moral à soi-même. À travers le principe de la pleine propriété de soi, les libertariens défendent la liberté entière de chacun de vivre comme il l���entend, pourvu que les droits des autres soient respectés. Apparemment, ce principe n’a pas grand-chose à nous dire sur ce que nous sommes moralement autorisés à nous faire à nous-mêmes ou non. Certains libertariens, comme Vallentyne, soutiennent toutefois que le principe de la pleine propriété de soi est incompatible avec l’existence de devoirs envers soi. La pleine propriété de soi impliquerait l’indifférence morale du rapport à soi. Je soutiens dans cet article que le principe de la pleine propriété de soi n’implique pas que ce que nous nous faisons à nous-mêmes soit moralement indifférent. Je veux aussi montrer que même si les libertariens, et en particulier Vallentyne, soutiennent la thèse de l’indifférence morale du rapport à soi, celle-ci n’est pas liée à la thèse de la pleine propriété de soi, mais bien plutôt à leur subjectivisme moral.ABSTRACTI ask in this article what the libertarian principle of full self-ownership has to say about volontary actions directed towards oneself. Through the principle of full self-ownership, libertarians defend the persons’ individual liberty to live as they choose to do, as long as they don’t infringe on the rights of others. Apparently, this principle doesn’t have much to say about what we are morally allowed to do to ourselves or not. Some libertarians, however, like Vallentyne, maintain that, if we have duties or obligations to ourselves, then we cannot be full self-owner. In this perspective, full self-ownership would imply that what we do to ourselves is morally indifferent. I want to show in this article that full self-ownership is compatible with the

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

International Nuclear Information System (INIS)

Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

2012-01-01

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

International Nuclear Information System (INIS)

Wang Zhongjian; Cheng Xinhong; Xia Chao; Xu Dawei; Cao Duo; Song Zhaorui; Yu Yuehui; Shen Dashen

2012-01-01

A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an 'oxidation-etch-oxidation' process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm 2 . (semiconductor devices)

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

International Nuclear Information System (INIS)

Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

2014-01-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

Science.gov (United States)

Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

2014-12-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

High voltage systems

International Nuclear Information System (INIS)

Martin, M.

1991-01-01

Industrial processes usually require electrical power. This power is used to drive motors, to heat materials, or in electrochemical processes. Often the power requirements of a plant require the electric power to be delivered at high voltage. In this paper high voltage is considered any voltage over 600 V. This voltage could be as high as 138,000 V for some very large facilities. The characteristics of this voltage and the enormous amounts of power being transmitted necessitate special safety considerations. Safety must be considered during the four activities associated with a high voltage electrical system. These activities are: Design; Installation; Operation; and Maintenance

Technology development for SOI monolithic pixel detectors

International Nuclear Information System (INIS)

Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

2006-01-01

A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

A high efficiency lateral light emitting device on SOI

NARCIS (Netherlands)

Hoang, T.; Le Minh, P.; Holleman, J.; Zieren, V.; Goossens, M.J.; Schmitz, Jurriaan

2005-01-01

The infrared light emission of lateral p/sup +/-p-n/sup +/ diodes realized on SIMOX-SOI (separation by implantation of oxygen - silicon on insulator) substrates has been studied. The confinement of the free carriers in one dimension due to the buried oxide was suggested to be a key point to increase

Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

International Nuclear Information System (INIS)

Kumar, V Vinoth; Dasgupta, A; Bhat, K N; KNatarajan

2006-01-01

In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process

Analyses of the radiation-caused characteristics change in SOI MOSFETs using field shield isolation

International Nuclear Information System (INIS)

Hirano, Yuuichi; Maeda, Shigeru; Fernandez, Warren; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Maegawa, Shigeto; Nishimura, Tadashi

1999-01-01

Reliability against radiation ia an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long regime channel. In transistors with a channel length of 0.18μm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0μm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment. (author)

Supplementary High-Input Impedance Voltage-Mode Universal Biquadratic Filter Using DVCCs

Directory of Open Access Journals (Sweden)

Jitendra Mohan

2012-01-01

Full Text Available To further extend the existing knowledge on voltage-mode universal biquadratic filter, in this paper, a new biquadratic filter circuit with single input and multiple outputs is proposed, employing three differential voltage current conveyors (DVCCs, three resistors, and two grounded capacitors. The proposed circuit realizes all the standard filter functions, that is, high-pass, band-pass, low-pass, notch, and all-pass filters simultaneously. The circuit enjoys the feature of high-input impedance, orthogonal control of resonance angular frequency (o, and quality factor (Q via grounded resistor and the use of grounded capacitors which is ideal for IC implementation.

Method to improve commercial bonded SOI material

Science.gov (United States)

Maris, Humphrey John; Sadana, Devendra Kumar

2000-07-11

A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

High voltage engineering

CERN Document Server

Rizk, Farouk AM

2014-01-01

Inspired by a new revival of worldwide interest in extra-high-voltage (EHV) and ultra-high-voltage (UHV) transmission, High Voltage Engineering merges the latest research with the extensive experience of the best in the field to deliver a comprehensive treatment of electrical insulation systems for the next generation of utility engineers and electric power professionals. The book offers extensive coverage of the physical basis of high-voltage engineering, from insulation stress and strength to lightning attachment and protection and beyond. Presenting information critical to the design, selec

A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

International Nuclear Information System (INIS)

Guo Yufeng; Wang Zhigong; Sheu Gene

2009-01-01

This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N + N and P + N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications. (semiconductor devices)

Determination of High-Frequency d- and q-axis Inductances for Surface-Mounted Permanent-Magnet Synchronous Machines

DEFF Research Database (Denmark)

Lu, Kaiyuan; Vetuschi, M.; Rasmussen, Peter Omand

2010-01-01

This paper presents a reliable method for the experimental determination of high-frequency d- and q -axis inductances for surface-mounted permanent-magnet synchronous machines (SMPMSMs). Knowledge of the high-frequency d- and q-axis inductances plays an important role in the efficient design...... of sensorless controllers using high-frequency signal injection techniques. The proposed method employs a static locked-rotor test using an ac +dc power supply. By injecting a high-frequency rotating voltage vector into the machine, the d- and q-axis inductances may simultaneously be determined with no need...

Performance analysis of SOI MOSFET with rectangular recessed channel

Science.gov (United States)

Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

2016-03-01

In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Science.gov (United States)

Patterson, Richard L.; Hammoud, Almad

2009-01-01

high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Technological Aspects: High Voltage

CERN Document Server

Faircloth, D.C.

2013-12-16

This paper covers the theory and technological aspects of high-voltage design for ion sources. Electric field strengths are critical to understanding high-voltage breakdown. The equations governing electric fields and the techniques to solve them are discussed. The fundamental physics of high-voltage breakdown and electrical discharges are outlined. Different types of electrical discharges are catalogued and their behaviour in environments ranging from air to vacuum are detailed. The importance of surfaces is discussed. The principles of designing electrodes and insulators are introduced. The use of high-voltage platforms and their relation to system design are discussed. The use of commercially available high-voltage technology such as connectors, feedthroughs and cables are considered. Different power supply technologies and their procurement are briefly outlined. High-voltage safety, electric shocks and system design rules are covered.

Performance analysis of SOI MOSFET with rectangular recessed channel

International Nuclear Information System (INIS)

Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

2016-01-01

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

Technological Aspects: High Voltage

International Nuclear Information System (INIS)

Faircloth, D C

2013-01-01

This paper covers the theory and technological aspects of high-voltage design for ion sources. Electric field strengths are critical to understanding high-voltage breakdown. The equations governing electric fields and the techniques to solve them are discussed. The fundamental physics of high-voltage breakdown and electrical discharges are outlined. Different types of electrical discharges are catalogued and their behaviour in environments ranging from air to vacuum are detailed. The importance of surfaces is discussed. The principles of designing electrodes and insulators are introduced. The use of high-voltage platforms and their relation to system design are discussed. The use of commercially available high-voltage technology such as connectors, feedthroughs and cables are considered. Different power supply technologies and their procurement are briefly outlined. High-voltage safety, electric shocks and system design rules are covered. (author)

Assessment of the operating conditions of coordinated Q-V controller within secondary voltage control system

Directory of Open Access Journals (Sweden)

Arnautović Dušan

2014-01-01

Full Text Available The paper, discusses the possibility to use coordinated Q-V controller (CQVC to perform secondary voltage control at the power plant level. The CQVC performs the coordination of the synchronous generators' (SG reactive power outputs in order to maintain the same total reactive power delivered by the steam power plant (SPP, while at the same time maintaining a constant voltage with programmed reactive droop characteristic at the SPP HV busbar. This busbar is the natural pilot node for secondary voltage control at HV level as the node with maximum power production and maximum power consumption. In addition to voltage control, the CQVC maintains the uniform allocation of reactive power reserves at all SGs in the power plant. This is accomplished by setting the reactive power of each SG at given operating point in accordance to the available reactive power of the same SG at that point. Different limitations imposed by unit's and plant equipment are superimposed on original SG operating chart (provided by the manufacturer in order to establish realistic limits of SG operation at given operating point. The CQVC facilitates: i practical implementation of secondary voltage control in power system, as it is capable of ensuring delivery of reactive power as requested by regional/voltage control while maintaining voltage at system pilot node, ii the full deployment of available reactive power of SGs which in turn contributes to system stability, iii assessment of the reactive power impact/contribution of each generator in providing voltage control as ancillary service. Furthermore, it is also possible to use CQVC to pricing reactive power production cost at each SG involved and to design reactive power bidding structure for transmission network devices by using recorded data. Practical exploitation experience acquired during CQVC continuous operation for over two years enabled implementation of the optimal setting of reference voltage and droop on daily

BUSFET -- A radiation-hardened SOI transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

1999-01-01

A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

Science.gov (United States)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

Science.gov (United States)

Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

2016-03-01

In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

Suppressing voltage transients in high voltage power supplies

International Nuclear Information System (INIS)

Lickel, K.F.; Stonebank, R.

1979-01-01

A high voltage power supply for an X-ray tubes includes voltage adjusting means, a high voltage transformer, switch means connected to make and interrupt the primary current of the transformer, and over-voltage suppression means to suppress the voltage transient produced when the current is switched on. In order to reduce the power losses in the suppression means, an impedance is connected in the transformer primary circuit on operation of the switch means and is subsequently short-circuited by a switch controlled by a timer after a period which is automatically adjusted to the duration of the transient overvoltage. (U.K.)

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

International Nuclear Information System (INIS)

Yuan, Yang; Yong, Gao; Peng-Liang, Gong

2008-01-01

A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

Development of Electromechanical Architectures for AC Voltage Metrology

Directory of Open Access Journals (Sweden)

Alexandre BOUNOUH

2010-12-01

Full Text Available This paper presents results of work undertaken for exploring MEMS capabilities to fabricate AC voltage references for electrical metrology and high precision instrumentation through the mechanical-electrical coupling in MEMS. From first MEMS test structures previously realized, a second set of devices with improved characteristics has been developed and fabricated with Silicon on Insulator (SOI Surface Micromachining process. These MEMS exhibit pull-in voltages of 5 V and 10 V to match with the best performance of the read-out electronics developed for driving the MEMS. Deep Level Transient Spectroscopy measurements carried out on the new design show resonance frequencies of about only some kHz, and the stability of the MEMS output voltage measured at 100 kHz has been found very promising for the best samples where the relative deviation from the mean value over almost 12 hours showed a standard deviation of about 6.3 ppm.

High voltage test techniques

CERN Document Server

Kind, Dieter

2001-01-01

The second edition of High Voltage Test Techniques has been completely revised. The present revision takes into account the latest international developments in High Voltage and Measurement technology, making it an essential reference for engineers in the testing field.High Voltage Technology belongs to the traditional area of Electrical Engineering. However, this is not to say that the area has stood still. New insulating materials, computing methods and voltage levels repeatedly pose new problems or open up methods of solution; electromagnetic compatibility (EMC) or components and systems al

Fully On-chip High Q Inductors Based on Microtechnologies

Directory of Open Access Journals (Sweden)

Kriyang SHAH

2010-04-01

Full Text Available Wireless biosensor networks (WBSNs collect information about biological responses and process it using scattered battery-power sensor nodes. Such nodes demand ultra low-power consumption for longer operating time. Ultra Wide Band (UWB is a potential solution for WBSNs due to its advantage in low power consumption at reasonable data rate. However, such UBW technology requires high quality (Q factor passive components. This paper presents detailed analysis, design and optimization of physical parameters of silicon-on-sapphire (SOS and micro-electro-mechanical-systems (MEMS inductors for application in UWB transceivers. Results showed that the 1.5 nH SOS inductor achieved Q factor of 111 and MEMS inductor achieved Q factor of 45 at 4 GHz frequency. The voltage controlled oscillator (VCO designed with SOS inductor achieved more than 10 dBc/Hz reduction in phase noise and consumed half the power compared to VCO with MEMS inductor. Such low power VCO will improve battery life of a UWB wireless sensor node.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

International Nuclear Information System (INIS)

Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

2013-01-01

A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

Energy Technology Data Exchange (ETDEWEB)

Zerrouk, D.

1997-07-18

Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

International Nuclear Information System (INIS)

Patil, Ganesh C; Qureshi, S

2011-01-01

In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

Temperature and Voltage Offsets in High-ZT Thermoelectrics

Science.gov (United States)

Levy, George S.

2017-10-01

Thermodynamic temperature can take on different meanings. Kinetic temperature is an expectation value and a function of the kinetic energy distribution. Statistical temperature is a parameter of the distribution. Kinetic temperature and statistical temperature, identical in Maxwell-Boltzmann statistics, can differ in other statistics such as those of Fermi-Dirac or Bose-Einstein when a field is present. Thermal equilibrium corresponds to zero statistical temperature gradient, not zero kinetic temperature gradient. Since heat carriers in thermoelectrics are fermions, the difference between these two temperatures may explain voltage and temperature offsets observed during meticulous Seebeck measurements in which the temperature-voltage curve does not go through the origin. In conventional semiconductors, temperature offsets produced by fermionic electrical carriers are not observable because they are shorted by heat phonons in the lattice. In high-ZT materials, however, these offsets have been detected but attributed to faulty laboratory procedures. Additional supporting evidence for spontaneous voltages and temperature gradients includes data collected in epistatic experiments and in the plasma Q-machine. Device fabrication guidelines for testing the hypothesis are suggested including using unipolar junctions stacked in a superlattice, alternating n/n + and p/p + junctions, selecting appropriate dimensions, doping, and loading.

Temperature and Voltage Offsets in High- ZT Thermoelectrics

Science.gov (United States)

Levy, George S.

2018-06-01

Thermodynamic temperature can take on different meanings. Kinetic temperature is an expectation value and a function of the kinetic energy distribution. Statistical temperature is a parameter of the distribution. Kinetic temperature and statistical temperature, identical in Maxwell-Boltzmann statistics, can differ in other statistics such as those of Fermi-Dirac or Bose-Einstein when a field is present. Thermal equilibrium corresponds to zero statistical temperature gradient, not zero kinetic temperature gradient. Since heat carriers in thermoelectrics are fermions, the difference between these two temperatures may explain voltage and temperature offsets observed during meticulous Seebeck measurements in which the temperature-voltage curve does not go through the origin. In conventional semiconductors, temperature offsets produced by fermionic electrical carriers are not observable because they are shorted by heat phonons in the lattice. In high- ZT materials, however, these offsets have been detected but attributed to faulty laboratory procedures. Additional supporting evidence for spontaneous voltages and temperature gradients includes data collected in epistatic experiments and in the plasma Q-machine. Device fabrication guidelines for testing the hypothesis are suggested including using unipolar junctions stacked in a superlattice, alternating n/ n + and p/ p + junctions, selecting appropriate dimensions, doping, and loading.

Reliability of supply of switchgear for auxiliary low voltage in substations extra high voltage to high voltage

Directory of Open Access Journals (Sweden)

Perić Dragoslav M.

2015-01-01

Full Text Available Switchgear for auxiliary low voltage in substations (SS of extra high voltages (EHV to high voltage (HV - SS EHV/HV kV/kV is of special interest for the functioning of these important SS, as it provides a supply for system of protection and other vital functions of SS. The article addresses several characteristic examples involving MV lines with varying degrees of independence of their supply, and the possible application of direct transformation EHV/LV through special voltage transformers. Auxiliary sources such as inverters and diesel generators, which have limited power and expensive energy, are also used for the supply of switchgear for auxiliary low voltage. Corresponding reliability indices are calculated for all examples including mean expected annual engagement of diesel generators. The applicability of certain solutions of switchgear for auxiliary low voltage SS EHV/HV, taking into account their reliability, feasibility and cost-effectiveness is analyzed too. In particular, the analysis of applications of direct transformation EHV/LV for supply of switchgear for auxiliary low voltage, for both new and existing SS EHV/HV.

Le soi et l’estime de soi chez l’enfant: Une revue systématique de la littérature

OpenAIRE

Pinto, Alexandra Maria Pereira Inácio Sequeira; Gatinho, Ana Rita dos Santos; Tereno, Susana; Veríssimo, Manuela

2016-01-01

Cette étude vise : a) à analyser les différentes méthodes utilisées pour l’étude du Soi et chez les enfants, en ce que concerne sa qualité et son potentiel et b) à synthétiser les résultats déjà obtenus en termes de Soi/d’estime de soi/d’autoconcept, pour les enfants en âge préscolaire. Après avoir établi des critères rigoureux d’inclusion et d’exclusion, 33 articles ont été sélectionnés, dans plusieurs bases de données, nationales et international...

DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

Directory of Open Access Journals (Sweden)

D. SINDHANAISELVI

2017-07-01

Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Science.gov (United States)

Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

2016-03-01

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

Voltage-driven versus current-driven spin torque in anisotropic tunneling junctions

KAUST Repository

Manchon, Aurelien

2011-01-01

Nonequilibrium spin transport in a magnetic tunnel junction comprising a single magnetic layer in the presence of interfacial spin-orbit interaction (SOI) is studied theoretically. The interfacial SOI generates a spin torque of the form T=T∥ M×(z× M)+T⊥ z× M, even in the absence of an external spin polarizer. For thick and large tunnel barriers, the torque reduces to the perpendicular component T⊥, which can be electrically tuned by applying a voltage across the insulator. In the limit of thin and low tunnel barriers, the in-plane torque T∥ emerges, proportional to the tunneling current density. Experimental implications on magnetic devices are discussed. © 2011 IEEE.

Voltage-driven versus current-driven spin torque in anisotropic tunneling junctions

KAUST Repository

Manchon, Aurelien

2011-10-01

Nonequilibrium spin transport in a magnetic tunnel junction comprising a single magnetic layer in the presence of interfacial spin-orbit interaction (SOI) is studied theoretically. The interfacial SOI generates a spin torque of the form T=T∥ M×(z× M)+T⊥ z× M, even in the absence of an external spin polarizer. For thick and large tunnel barriers, the torque reduces to the perpendicular component T⊥, which can be electrically tuned by applying a voltage across the insulator. In the limit of thin and low tunnel barriers, the in-plane torque T∥ emerges, proportional to the tunneling current density. Experimental implications on magnetic devices are discussed. © 2011 IEEE.

A high-voltage equipment (high voltage supply, high voltage pulse generators, resonant charging inductance, synchro-instruments for gyrotron frequency measurements) for plasma applications

International Nuclear Information System (INIS)

Spassov, Velin

1996-01-01

This document reports my activities as visitor-professor at the Gyrotron Project - INPE Plasma Laboratory. The main objective of my activities was designing, construction and testing a suitable high-voltage pulse generator for plasma applications, and efforts were concentrated on the following points: Design of high-voltage resonant power supply with tunable output (0 - 50 kV) for line-type high voltage pulse generator; design of line-type pulse generator (4 microseconds pulse duration, 0 - 25 kV tunable voltage) for non linear loads such as a gyrotron and P III reactor; design of resonant charging inductance for resonant line-type pulse generator, and design of high resolution synchro instrument for gyrotron frequency measurement. (author)

Performance study of double SOI image sensors

Science.gov (United States)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Croire en soi, croire en l'autre

Directory of Open Access Journals (Sweden)

Eugène Enriquez

2014-04-01

Full Text Available La croyance aux Dieux ou en un Dieu unique c'est-à-dire à l'incroyable est fort répandue et semble normale comme avoir confiance en soi et en l'autre. Mais croire en soi et en l'autre apparaît étonnant car ce serait se mettre sur le même rang que Dieu. Effectivement l'homme essaie de ressembler à Dieu. Mais à Dieu blessé, faillible, s'interrogeant constamment. Ce Dieu nouveau est un "sujet amoureux" amoureux de soi, de l'autre et de la vie. Il se conduit comme un "Dichter" assumant une responsabilité morale. Il est difficile, voire souvent impossible de se situer comme un "Dichter". C'est pourtant la tâche à laquelle l'homme contemporain est confronté.

Change in high field Q-slope by baking and anodizing

Energy Technology Data Exchange (ETDEWEB)

Eremeev, G. [LEPP, Cornell University, Ithaca, NY 14853 (United States); Padamsee, H. [LEPP, Cornell University, Ithaca, NY 14853 (United States)

2006-07-15

Low temperature RF performance of two niobium cavities that underwent different chemical treatments was measured after they were heat treated at 100 deg, C for 48 h. After heat treatment cavities were anodized in ammonia hydroxide solution for sequentially increasing voltage until baking effect was gone. The thickness of niobium finally consumed is estimated to be 20 nm. The results are discussed in view of one of the current models for the baking effect on the high field Q-slope.

High-voltage, high-current, solid-state closing switch

Science.gov (United States)

Focia, Ronald Jeffrey

2017-08-22

A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications.

CMOS-compatible high-voltage integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Parpia, Z

1988-01-01

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

Test-beam results of a SOI pixel detector prototype

CERN Document Server

Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

2018-01-01

This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

High-voltage picoamperemeter

Energy Technology Data Exchange (ETDEWEB)

Bugl, Andrea; Ball, Markus; Boehmer, Michael; Doerheim, Sverre; Hoenle, Andreas; Konorov, Igor [Technische Universitaet Muenchen, Garching (Germany); Ketzer, Bernhard [Technische Universitaet Muenchen, Garching (Germany); Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany)

2014-07-01

Current measurements in the nano- and picoampere region on high voltage are an important tool to understand charge transfer processes in micropattern gas detectors like the Gas Electron Multiplier (GEM). They are currently used to e.g. optimize the field configuration in a multi-GEM stack to be used in the ALICE TPC after the upgrade of the experiment during the 2nd long shutdown of the LHC. Devices which allow measurements down to 1pA at high voltage up to 6 kV have been developed at TU Muenchen. They are based on analog current measurements via the voltage drop over a switchable shunt. A microcontroller collects 128 digital ADC values and calculates their mean and standard deviation. This information is sent with a wireless transmitting unit to a computer and stored in a root file. A nearly unlimited number of devices can be operated simultaneously and read out by a single receiver. The results can also be displayed on a LCD directly at the device. Battery operation and the wireless readout are important to protect the user from any contact to high voltage. The principle of the device is explained, and systematic studies of their properties are shown.

Hybrid III-V/SOI Resonant Cavity Photodetector

DEFF Research Database (Denmark)

Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

2016-01-01

A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization.......A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization....

Scaling limits and reliability of SOI CMOS technology

International Nuclear Information System (INIS)

Ioannou, D E

2005-01-01

As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

Temporary over voltages in the high voltage networks

International Nuclear Information System (INIS)

Vukelja, Petar; Naumov, Radomir; Mrvic, Jovan; Minovski, Risto

2001-01-01

The paper treats the temporary over voltages that may arise in the high voltage networks as a result of: ground faults, loss of load, loss of one or two phases and switching operation. Based on the analysis, the measures for their limitation are proposed. (Original)

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

Directory of Open Access Journals (Sweden)

Ha-Duong Ngo

2015-08-01

Full Text Available In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load with an accuracy of 0.25% Full Scale Output (FSO. A push rod (mounted onto the steel membrane transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process. A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

Science.gov (United States)

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Transient voltage sharing in series-coupled high voltage switches

Directory of Open Access Journals (Sweden)

Editorial Office

1992-07-01

Full Text Available For switching voltages in excess of the maximum blocking voltage of a switching element (for example, thyristor, MOSFET or bipolar transistor such elements are often coupled in series - and additional circuitry has to be provided to ensure equal voltage sharing. Between each such series element and system ground there is a certain parasitic capacitance that may draw a significant current during high-speed voltage transients. The "open" switch is modelled as a ladder network. Analy­sis reveals an exponential progression in the distribution of the applied voltage across the elements. Overstressing thus oc­curs in some of the elements at levels of the total voltage that are significantly below the design value. This difficulty is overcome by grading the voltage sharing circuitry, coupled in parallel with each element, in a prescribed manner, as set out here.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Prediction of breakdown voltages in novel gases for high voltage insulation

International Nuclear Information System (INIS)

Koch, M.

2015-01-01

This thesis submitted to the Swiss Federal Institute of Technology ETH in Zurich examines the use of sulphur hexafluoride (SF_6) and similar gases as important insulation media for high voltage equipment. Due to its superior insulation properties, SF_6 is widely used in gas-insulated switchgear. However, the gas also has a very high global warming potential and the content of SF_6 in the atmosphere is constantly increasing. The search for new insulation gases using classical breakdown experiments is discussed. A model for SF_6 based on the stepped leader model is described. This calculates the breakdown voltages in arbitrary electrode configurations and under standard voltage waveforms. Thus, the thesis provides a method for the prediction of breakdown voltages of arbitrary field configurations under standard voltage waveforms for gases with electron-attaching properties. With this, further gases can be characterized for usage as high voltage insulation media

Prediction of breakdown voltages in novel gases for high voltage insulation

Energy Technology Data Exchange (ETDEWEB)

Koch, M.

2015-07-01

This thesis submitted to the Swiss Federal Institute of Technology ETH in Zurich examines the use of sulphur hexafluoride (SF{sub 6}) and similar gases as important insulation media for high voltage equipment. Due to its superior insulation properties, SF{sub 6} is widely used in gas-insulated switchgear. However, the gas also has a very high global warming potential and the content of SF{sub 6} in the atmosphere is constantly increasing. The search for new insulation gases using classical breakdown experiments is discussed. A model for SF{sub 6} based on the stepped leader model is described. This calculates the breakdown voltages in arbitrary electrode configurations and under standard voltage waveforms. Thus, the thesis provides a method for the prediction of breakdown voltages of arbitrary field configurations under standard voltage waveforms for gases with electron-attaching properties. With this, further gases can be characterized for usage as high voltage insulation media.

Electron mobility in the inversion layers of fully depleted SOI films

Energy Technology Data Exchange (ETDEWEB)

Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

2017-04-15

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

Group Delay of High Q Antennas

DEFF Research Database (Denmark)

Bahramzy, Pevand; Pedersen, Gert Frølund

2013-01-01

Group Delay variations versus frequency is an essential factor which can cause distortion and degradation in the signals. Usually this is an issue in wideband communication systems, such as satellite communication systems, which are used for transmitting wideband data. However, group delay can also...... become an issue, when working with high Q antennas, because of the steep phase shift over the frequency. In this paper, it is measured how large group delay variations can become, when going from a low Q antenna to a high Q antenna. The group delay of a low Q antenna is shown to be around 1.3 ns, whereas...... a high Q antenna has group delay of around 22 ns. It is due to this huge group delay variation characteristics of high Q antennas, that signal distortion might occur in the radio system with high Q antennas....

LED-Based High-Voltage Lines Warning System

Directory of Open Access Journals (Sweden)

Eldar MUSA

2013-04-01

Full Text Available LED-based system, running with the current of high-voltage lines and converting the current flowing through the line into the light by using a toroid transformer, has been developed. The transformer’s primary winding is constituted by the high voltage power line. Toroidal core consists of two equal parts and the secondary windings are evenly placed on these two parts. The system is mounted on the high-voltage lines as a clamp. The secondary winding ends are connected in series by the connector on the clamp. LEDs are supplied by the voltage at the ends of secondary. Current flowing through highvoltage transmission lines is converted to voltage by the toroidal transformer and the light emitting LEDs are supplied with this voltage. The theory of the conversion of the current flowing through the line into the light is given. The system, running with the current of the line and converting the current into the light, has been developed. System has many application areas such as warning high voltage lines (warning winches to not hinder the high-voltage lines when working under the lines, warning planes to not touch the high-voltage lines, remote measurement of high-voltage line currents, and local illumination of the line area

Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

International Nuclear Information System (INIS)

Liao, Shu-Hui; Chang, Shu-Tong

2010-01-01

This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

International Nuclear Information System (INIS)

Dehzangi, Arash; Larki, Farhad; Naseri, Mahmud G.; Navasery, Manizheh; Majlis, Burhanuddin Y.; Razip Wee, Mohd F.; Halimah, M.K.; Islam, Md. Shabiul; Md Ali, Sawal H.; Saion, Elias

2015-01-01

Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated

Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

Energy Technology Data Exchange (ETDEWEB)

Dehzangi, Arash, E-mail: arashd53@hotmail.com [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Larki, Farhad [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Naseri, Mahmud G. [Department of Physics, Faculty of Science, Malayer University, Malayer, Hamedan (Iran, Islamic Republic of); Navasery, Manizheh [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Majlis, Burhanuddin Y.; Razip Wee, Mohd F. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Halimah, M.K. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Islam, Md. Shabiul; Md Ali, Sawal H. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Saion, Elias [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia)

2015-04-15

Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

Science.gov (United States)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

76 FR 70721 - Voltage Coordination on High Voltage Grids; Notice of Staff Workshop

Science.gov (United States)

2011-11-15

... DEPARTMENT OF ENERGY Federal Energy Regulatory Commission [Docket No. AD12-5-000] Voltage Coordination on High Voltage Grids; Notice of Staff Workshop Take notice that the Federal Energy Regulatory Commission will hold a Workshop on Voltage Coordination on High Voltage Grids on Thursday, December 1, 2011...

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

Reduced nonlinearities in 100-nm high SOI waveguides

Science.gov (United States)

Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

2016-03-01

Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

Performance of the INTPIX6 SOI pixel detector

International Nuclear Information System (INIS)

Arai, Y.; Miyoshi, T.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Turala, M.; Kucewicz, W.

2017-01-01

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ  m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241 Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e − . The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e − . The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

Performance of the INTPIX6 SOI pixel detector

Science.gov (United States)

Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

2017-01-01

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

Science.gov (United States)

Stock, William A.; DiSalvo, Pamela M.

The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

Deep sub-micron FD-SOI for front-end application

International Nuclear Information System (INIS)

Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

2007-01-01

In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

Micromachined thin-film sensors for SOI-CMOS co-integration

CERN Document Server

Laconte, Jean; Raskin, Jean-Pierre

2006-01-01

Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

First results of a Double-SOI pixel chip for X-ray imaging

Energy Technology Data Exchange (ETDEWEB)

Lu, Yunpeng, E-mail: yplu@ihep.ac.cn [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Ouyang, Qun [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Arai, Yasuo [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801 (Japan); Liu, Yi; Wu, Zhigang; Zhou, Yang [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China)

2016-09-21

Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I–V curve. An s-curve fitting resulted in a sigma of 153 e{sup −} among which equivalent noise charge (ENC) contributed 113 e{sup −}. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

On-site voltage measurement with capacitive sensors on high voltage systems

NARCIS (Netherlands)

Wu, L.; Wouters, P.A.A.F.; Heesch, van E.J.M.; Steennis, E.F.

2011-01-01

In Extra/High-Voltage (EHV/HV) power systems, over-voltages occur e.g. due to transients or resonances. At places where no conventional voltage measurement devices can be installed, on-site measurement of these occurrences requires preferably non intrusive sensors, which can be installed with little

A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

CERN Multimedia

2002-01-01

% RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

Ionization smoke detectors - the high-voltage issues

International Nuclear Information System (INIS)

Anon.

1992-01-01

Production of high-voltage ionization smoke detectors ceased in 1978 following the development of lower voltage models which used much smaller amounts of radioactive material. Despite this fact, thousands of high-voltage detectors are still in use today in many large UK companies. The major users argue that there is no reason to stop using their detectors if they are still fit for their purpose - many could last for another 15 to 20 years if properly maintained. But pressure has been mounting on businesses to replace all their high-voltage detectors with new low-voltage models within the next couple of years. This could place a huge financial burden on the companies concerned, with costs possibly running into millions of pounds. Traditionally, the major detector installers offered cleaning and maintenance services for high-voltage detectors to their customers but these have now been withdrawn. The installers give no clear reasons for this decision except that the detectors are outmoded and should be disposed of as soon as possible. Most users would agree that conversion to low-voltage types is inevitable but their main worry is the financial strain of replacing all their detectors - and associated equipment - in one go. They would prefer to phase out their high-voltage detectors in stages over a number of years to spread the costs of conversion. The problems of maintenance is discussed. A dual voltage fire alarm panel which allows the high-voltage detectors to be phased out is mentioned. (Author)

High-frequency high-voltage high-power DC-to-DC converters

Science.gov (United States)

Wilson, T. G.; Owen, H. A.; Wilson, P. M.

1982-09-01

A simple analysis of the current and voltage waveshapes associated with the power transistor and the power diode in an example current-or-voltage step-up (buck-boost) converter is presented. The purpose of the analysis is to provide an overview of the problems and design trade-offs which must be addressed as high-power high-voltage converters are operated at switching frequencies in the range of 100 kHz and beyond. Although the analysis focuses on the current-or-voltage step-up converter as the vehicle for discussion, the basic principles presented are applicable to other converter topologies as well.

Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

Science.gov (United States)

Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

2018-05-01

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

High voltage engineering fundamentals

CERN Document Server

Kuffel, E; Hammond, P

1984-01-01

Provides a comprehensive treatment of high voltage engineering fundamentals at the introductory and intermediate levels. It covers: techniques used for generation and measurement of high direct, alternating and surge voltages for general application in industrial testing and selected special examples found in basic research; analytical and numerical calculation of electrostatic fields in simple practical insulation system; basic ionisation and decay processes in gases and breakdown mechanisms of gaseous, liquid and solid dielectrics; partial discharges and modern discharge detectors; and over

30 CFR 75.804 - Underground high-voltage cables.

Science.gov (United States)

2010-07-01

... AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Underground High-Voltage Distribution § 75.804 Underground high-voltage cables. (a) Underground high-voltage cables used in resistance... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Underground high-voltage cables. 75.804 Section...

High-voltage engineering and testing

CERN Document Server

Ryan, Hugh M

2013-01-01

This 3rd edition of High Voltage Engineering Testing describes strategic developments in the field and reflects on how they can best be managed. All the key components of high voltage and distribution systems are covered including electric power networks, UHV and HV. Distribution systems including HVDC and power electronic systems are also considered.

Modular high voltage power supply for chemical analysis

Science.gov (United States)

Stamps, James F [Livermore, CA; Yee, Daniel D [Dublin, CA

2008-07-15

A high voltage power supply for use in a system such as a microfluidics system, uses a DC-DC converter in parallel with a voltage-controlled resistor. A feedback circuit provides a control signal for the DC-DC converter and voltage-controlled resistor so as to regulate the output voltage of the high voltage power supply, as well as, to sink or source current from the high voltage supply.

High voltage designing of 300.000 Volt

International Nuclear Information System (INIS)

Hutapea, Sumihar.

1978-01-01

Some methods of designing a.c and d.c high voltage supplies are discussed. A high voltage supply for the Gama Research Centre accelerator is designed using transistor pulse generators. High voltage transformers being made using radio transistor ferrits as a core are also discussed. (author)

30 CFR 75.813 - High-voltage longwalls; scope.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage longwalls; scope. 75.813 Section... AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Underground High-Voltage Distribution High-Voltage Longwalls § 75.813 High-voltage longwalls; scope. Sections 75.814 through 75.822 of this...

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

Science.gov (United States)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

International Nuclear Information System (INIS)

Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

2014-01-01

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

Science.gov (United States)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Numerical and Experimental Study of the Q Factor of High-Q Micropillar Cavities

DEFF Research Database (Denmark)

Gregersen, Niels; Reitzenstein, S.; Kistner, C.

2010-01-01

Micropillar cavities are potential candidates for high-efficiency single-photon sources and are testbeds for cavity quantum electrodynamics experiments. In both applications a high quality (Q) factor is desired. It was recently shown that the Q of high-Q semiconductor micropillar cavities exhibit...

Free-energy relationships in ion channels activated by voltage and ligand

Science.gov (United States)

Chowdhury, Sandipan

2013-01-01

Many ion channels are modulated by multiple stimuli, which allow them to integrate a variety of cellular signals and precisely respond to physiological needs. Understanding how these different signaling pathways interact has been a challenge in part because of the complexity of underlying models. In this study, we analyzed the energetic relationships in polymodal ion channels using linkage principles. We first show that in proteins dually modulated by voltage and ligand, the net free-energy change can be obtained by measuring the charge-voltage (Q-V) relationship in zero ligand condition and the ligand binding curve at highly depolarizing membrane voltages. Next, we show that the voltage-dependent changes in ligand occupancy of the protein can be directly obtained by measuring the Q-V curves at multiple ligand concentrations. When a single reference ligand binding curve is available, this relationship allows us to reconstruct ligand binding curves at different voltages. More significantly, we establish that the shift of the Q-V curve between zero and saturating ligand concentration is a direct estimate of the interaction energy between the ligand- and voltage-dependent pathway. These free-energy relationships were tested by numerical simulations of a detailed gating model of the BK channel. Furthermore, as a proof of principle, we estimate the interaction energy between the ligand binding and voltage-dependent pathways for HCN2 channels whose ligand binding curves at various voltages are available. These emerging principles will be useful for high-throughput mutagenesis studies aimed at identifying interaction pathways between various regulatory domains in a polymodal ion channel. PMID:23250866

Computer controlled high voltage system

Energy Technology Data Exchange (ETDEWEB)

Kunov, B; Georgiev, G; Dimitrov, L [and others

1996-12-31

A multichannel computer controlled high-voltage power supply system is developed. The basic technical parameters of the system are: output voltage -100-3000 V, output current - 0-3 mA, maximum number of channels in one crate - 78. 3 refs.

High voltage distributions in RPCs

International Nuclear Information System (INIS)

Inoue, Y.; Muranishi, Y.; Nakamura, M.; Nakano, E.; Takahashi, T.; Teramoto, Y.

1996-01-01

High voltage distributions on the inner surfaces of RPCs electrodes were calculated by using a two-dimensional resistor network model. The calculated result shows that the surface resistivity of the electrodes should be high, compared to their volume resistivity, to get a uniform high voltage over the surface. Our model predicts that the rate capabilities of RPCs should be inversely proportional to the thickness of the electrodes if the ratio of surface-to-volume resistivity is low. (orig.)

High-voltage CMOS detectors

International Nuclear Information System (INIS)

Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

2016-01-01

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High-voltage CMOS detectors

Energy Technology Data Exchange (ETDEWEB)

Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

2016-07-11

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

L’estime de soi : un cas particulier d’estime sociale ?

OpenAIRE

Santarelli, Matteo

2016-01-01

Un des traits plus originaux de la théorie intersubjective de la reconnaissance d’Axel Honneth, consiste dans la façon dont elle discute la relation entre estime sociale et estime de soi. En particulier, Honneth présente l’estime de soi comme un reflet de l’estime sociale au niveau individuel. Dans cet article, je discute cette conception, en posant la question suivante : l’estime de soi est-elle un cas particulier de l’estime sociale ? Pour ce faire, je me concentre sur deux problèmes crucia...

Electrophysiological characteristics of a SCN5A voltage sensors mutation R1629Q associated with Brugada syndrome.

Directory of Open Access Journals (Sweden)

Zhipeng Zeng

Full Text Available Brugada syndrome (BrS is an inherited arrhythmogenic syndrome leading to sudden cardiac death, partially associated with autosomal dominant mutations in SCN5A, which encodes the cardiac sodium channel alpha-subunit (Nav1.5. To date some SCN5A mutations related with BrS have been identified in voltage sensor of Nav1.5. Here, we describe a dominant missense mutation (R1629Q localized in the fourth segment of domain IV region (DIV-S4 in a Chinese Han family. The mutation was identified by direct sequencing of SCN5A from the proband's DNA. Co-expression of Wild-type (WT or R1629Q Nav1.5 channel and hβ1 subunit were achieved in human embryonic kidney cells by transient transfection. Sodium currents were recorded using whole cell patch-clamp protocols. No significant changes between WT and R1629Q currents were observed in current density or steady-state activation. However, hyperpolarized shift of steady-state inactivation curve was identified in cells expressing R1629Q channel (WT: V1/2 = -81.1 ± 1.3 mV, n = 13; R1629Q: V1/2 = -101.7 ± 1.2 mV, n = 18. Moreover, R1629Q channel showed enhanced intermediate inactivation and prolonged recovery time from inactivation. In summary, this study reveals that R1629Q mutation causes a distinct loss-of-function of the channel due to alter its electrophysiological characteristics, and facilitates our understanding of biophysical mechanisms of BrS.

High voltage high brightness electron accelerators with MITL voltage adder coupled to foilless diodes

International Nuclear Information System (INIS)

Mazarakis, M.G.; Poukey, J.W.; Frost, C.A.; Shope, S.L.; Halbleib, J.A.; Turman, B.N.

1993-01-01

During the last ten years the authors have extensively studied the physics and operation of magnetically-immersed electron foilless diodes. Most of these sources were utilized as injectors to high current, high energy linear induction accelerators such as those of the RADLAC family. Recently they have experimentally and theoretically demonstrated that foilless diodes can be successfully coupled to self-magnetically insulated transmission line voltage adders to produce very small high brightness, high definition (no halo) electron beams. The RADLAC/SMILE experience opened the path to a new approach in high brightness, high energy induction accelerators. There is no beam drifting through the device. The voltage addition occurs in a center conductor, and the beam is created at the high voltage end in an applied magnetic field diode. This work was motivated by the remarkable success of the HERMES-III accelerator and the need to produce small radius, high energy, high current electron beams for air propagation studies and flash x-ray radiography. In this paper they present experimental results compared with analytical and numerical simulations in addition to design examples of devices that can produce multikiloamp electron beams of as high as 100 MV energies and radii as small as 1 mm

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

Characterization of silicon-on-insulator wafers

Science.gov (United States)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Advances in high voltage power switching with GTOs

International Nuclear Information System (INIS)

Podlesak, T.F.

1990-01-01

The control of high voltage at high power, particularly opening switches, has been difficult in the past. Using gate turnoff thyristors (GTOs) arranged in series enables large currents to be switched at high voltage. The authors report a high voltage opening switch has been successfully demonstrated. This switch uses GTOs in series and successfully operates at voltages higher than the rated voltage of the individual devices. It is believed that this is the first time this has been successfully demonstrated, in that GTOs have been operated in series before, but always in a manner as to not exceed the voltage capability of the individual devices. In short, the devices have not worked together, sharing the voltage, but one device has been operated using several backup devices. Of particular interest is how well the individual devices share the voltage applied to them. Equal voltage sharing between devices is absolutely essential, in order to not exceed the voltage rating of any of the devices in the series chain. This is accomplished at high (microsecond) switching speeds. Thus, the system is useful for high frequency applications as well as high power, making for a flexible circuit system element. This demonstration system is rated at 5 KV and uses 1 KV devices. A larger 24 KV system is under design and will use 4.5 KV devices. In order to design the 24 KV switch, the safe operating area of the large devices must be known thoroughly

Electro-optic control of a PPLN-unpoled LiNbO3 boundary for low-voltage Q switching of an intracavity frequency-doubled Nd3+:YVO4 laser.

Science.gov (United States)

Torregrosa, A J; Maestre, H; Fernández-Pousa, C R; Pereda, J A; Capmany, J

2009-08-01

We present a simple technique to integrate an electro-optic Q switch in a periodically poled bulk lithium niobate crystal bounded by two unpoled (monodomain) regions. The technique exploits the high sensitivity to low applied electric fields of the total internal reflection condition in the periodic poled-unpoled boundary for the small grazing incidence angles associated with the diffraction of a focused Gaussian beam that propagates in the periodically poled region with its axis parallel to the boundary. When the arrangement is placed intracavity to a 1064 nm diode-pumped Nd(3+):YVO(4) laser, it performs simultaneously as a Q switch and as a second-harmonic generator, with Q switching starting at applied voltages as low as 1 V over a 500 microm thickness and with no additional optical elements.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

Science.gov (United States)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

High frequency relay protection channels on super high voltage lines

Energy Technology Data Exchange (ETDEWEB)

Mikutskii, G V

1964-08-01

General aspects of high voltage transmission line design are discussed. The relationships between line voltage and length and line dimensions and power losses are explained. Electrical interference in the line is classified under three headings: interference under normal operating conditions, interference due to insulation faults, and interference due to variations in operating conditions of the high-voltage network.

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

High Efficiency Power Converter for Low Voltage High Power Applications

DEFF Research Database (Denmark)

Nymand, Morten

The topic of this thesis is the design of high efficiency power electronic dc-to-dc converters for high-power, low-input-voltage to high-output-voltage applications. These converters are increasingly required for emerging sustainable energy systems such as fuel cell, battery or photo voltaic based......, and remote power generation for light towers, camper vans, boats, beacons, and buoys etc. A review of current state-of-the-art is presented. The best performing converters achieve moderately high peak efficiencies at high input voltage and medium power level. However, system dimensioning and cost are often...

Vivitron 1995, transient voltage simulation, high voltage insulator tests, electric field calculation

International Nuclear Information System (INIS)

Frick, G.; Osswald, F.; Heusch, B.

1996-01-01

Preliminary investigations showed clearly that, because of the discrete electrode structure of the Vivitron, important overvoltage leading to insulator damage can appear in case of a spark. The first high voltage tests showed damage connected with such events. This fact leads to a severe voltage limitation. This work describes, at first, studies made to understand the effects of transients and the associated over-voltage appearing in the Vivitron. Then we present the high voltage tests made with full size Vivitron components using the CN 6 MV machine as a pilot machine. Extensive field calculations were made. These involve simulations of static stresses and transient overvoltages, on insulating boards and electrodes. This work gave us the solutions for arrangements and modifications in the machine. After application, the Vivitron runs now without any sparks and damage at 20 MV. In the same manner, we tested column insulators of a new design and so we will find out how to get to higher voltages. Electric field calculation around the tie bars connecting the discrete electrodes together showed field enhancements when the voltages applied on the discrete electrodes are not equally distributed. This fact is one of the sources of discharges and voltage limitations. A scenario of a spark event is described and indications are given how to proceed towards higher voltages, in the 30 MV range. (orig.)

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

International Nuclear Information System (INIS)

Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

2014-01-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

A 600kV 15mA Cockcroft-Walton high-voltage power supply with high stability and low-ripple voltage

International Nuclear Information System (INIS)

Su Tongling; Zhang Yimin; Chen Shangwen; Liu Yantong; Lv Huiyi; Liu Jiangtao

2006-01-01

A Cockcroft-Walton high-voltage power supply with high stability and low-ripple voltage has been developed. This power supply has been operated in a ns pulse neutron generator. The maximum non-load voltage is 600kV while the working voltage and load current are 550kV and 15mA, respectively. The tested results indicate that when the power supply is operated at 300kV, 6.7mA and the input voltage varies +/-10%, the long-term stability of the output voltage is S=(0.300-1.006)x10 -3 . The ripple voltage is δU P-P =6.2V at 300kV, 6.8-8.3mA and the ratio of δU P-P to the output voltage V H is δU P-P /V H =2.1x10 -5

High voltage electricity installations a planning perspective

CERN Document Server

Jay, Stephen Andrew

2006-01-01

The presence of high voltage power lines has provoked widespread concern for many years. High Voltage Electricity Installations presents an in-depth study of policy surrounding the planning of high voltage installations, discussing the manner in which they are percieved by the public, and the associated environmental issues. An analysis of these concerns, along with the geographical, environmental and political influences that shape their expression, is presented. Investigates local planning policy in an area of the energy sector that is of highly topical environmental and public concern Cover

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Science.gov (United States)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

High Efficiency Power Converter for Low Voltage High Power Applications

DEFF Research Database (Denmark)

Nymand, Morten

The topic of this thesis is the design of high efficiency power electronic dc-to-dc converters for high-power, low-input-voltage to high-output-voltage applications. These converters are increasingly required for emerging sustainable energy systems such as fuel cell, battery or photo voltaic based...

High Voltage Seismic Generator

Science.gov (United States)

Bogacz, Adrian; Pala, Damian; Knafel, Marcin

2015-04-01

This contribution describes the preliminary result of annual cooperation of three student research groups from AGH UST in Krakow, Poland. The aim of this cooperation was to develop and construct a high voltage seismic wave generator. Constructed device uses a high-energy electrical discharge to generate seismic wave in ground. This type of device can be applied in several different methods of seismic measurement, but because of its limited power it is mainly dedicated for engineering geophysics. The source operates on a basic physical principles. The energy is stored in capacitor bank, which is charged by two stage low to high voltage converter. Stored energy is then released in very short time through high voltage thyristor in spark gap. The whole appliance is powered from li-ion battery and controlled by ATmega microcontroller. It is possible to construct larger and more powerful device. In this contribution the structure of device with technical specifications is resented. As a part of the investigation the prototype was built and series of experiments conducted. System parameter was measured, on this basis specification of elements for the final device were chosen. First stage of the project was successful. It was possible to efficiently generate seismic waves with constructed device. Then the field test was conducted. Spark gap wasplaced in shallowborehole(0.5 m) filled with salt water. Geophones were placed on the ground in straight line. The comparison of signal registered with hammer source and sparker source was made. The results of the test measurements are presented and discussed. Analysis of the collected data shows that characteristic of generated seismic signal is very promising, thus confirms possibility of practical application of the new high voltage generator. The biggest advantage of presented device after signal characteristics is its size which is 0.5 x 0.25 x 0.2 m and weight approximately 7 kg. This features with small li-ion battery makes

Voltage generators of high voltage high power accelerators

International Nuclear Information System (INIS)

Svinin, M.P.

1981-01-01

High voltage electron accelerators are widely used in modern radiation installations for industrial purposes. In the near future further increasing of their power may be effected, which enables to raise the efficiency of the radiation processes known and to master new power-consuming production in industry. Improvement of HV generators by increasing their power and efficiency is one of many scientific and engineering aspects the successful solution of which provides further development of these accelerators and their technical parameters. The subject is discussed in detail. (author)

Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

Directory of Open Access Journals (Sweden)

A. Daghighi

2013-09-01

Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

Special Issue: Planar Fully-Depleted SOI technology

Science.gov (United States)

Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

2016-03-01

We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

Physicochemical assessment criteria for high-voltage pulse capacitors

Energy Technology Data Exchange (ETDEWEB)

Darian, L. A., E-mail: LDarian@rambler.ru; Lam, L. Kh. [National Research University, Moscow Power Engineering Institute (Russian Federation)

2016-12-15

In the paper, the applicability of decomposition products of internal insulation of high-voltage pulse capacitors is considered (aging is the reason for decomposition products of internal insulation). Decomposition products of internal insulation of high-voltage pulse capacitors can be used to evaluate their quality when in operation and in service. There have been three generations of markers of aging of insulation as in the case with power transformers. The area of applicability of markers of aging of insulation for power transformers has been studied and the area can be extended to high-voltage pulse capacitors. The research reveals that there is a correlation between the components and quantities of markers of aging of the first generation (gaseous decomposition products of insulation) dissolved in insulating liquid and the remaining life of high-voltage pulse capacitors. The application of markers of aging to evaluate the remaining service life of high-voltage pulse capacitor is a promising direction of research, because the design of high-voltage pulse capacitors keeps stability of markers of aging of insulation in high-voltage pulse capacitors. It is necessary to continue gathering statistical data concerning development of markers of aging of the first generation. One should also carry out research aimed at estimation of the remaining life of capacitors using markers of the second and the third generation.

Physicochemical assessment criteria for high-voltage pulse capacitors

International Nuclear Information System (INIS)

Darian, L. A.; Lam, L. Kh.

2016-01-01

In the paper, the applicability of decomposition products of internal insulation of high-voltage pulse capacitors is considered (aging is the reason for decomposition products of internal insulation). Decomposition products of internal insulation of high-voltage pulse capacitors can be used to evaluate their quality when in operation and in service. There have been three generations of markers of aging of insulation as in the case with power transformers. The area of applicability of markers of aging of insulation for power transformers has been studied and the area can be extended to high-voltage pulse capacitors. The research reveals that there is a correlation between the components and quantities of markers of aging of the first generation (gaseous decomposition products of insulation) dissolved in insulating liquid and the remaining life of high-voltage pulse capacitors. The application of markers of aging to evaluate the remaining service life of high-voltage pulse capacitor is a promising direction of research, because the design of high-voltage pulse capacitors keeps stability of markers of aging of insulation in high-voltage pulse capacitors. It is necessary to continue gathering statistical data concerning development of markers of aging of the first generation. One should also carry out research aimed at estimation of the remaining life of capacitors using markers of the second and the third generation.

Time isolation high-voltage impulse generator

International Nuclear Information System (INIS)

Chodorow, A.M.

1975-01-01

Lewis' high-voltage impulse generator is analyzed in greater detail, demonstrating that voltage between adjacent nodes can be equalized by proper selection of parasitic impedances. This permits improved TEM mode propagation to a matched load, with more faithful source waveform preservation

SOI MESFETs for Extreme Environment Electronics, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — We are proposing a new extreme environment electronics (EEE) technology based on silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs)....

Thermal Loss in High-Q Antennas

DEFF Research Database (Denmark)

Barrio, Samantha Caporal Del; Bahramzy, Pevand; Svendsen, Simon

2014-01-01

Tunable antennas are very promising for future generations of mobile communications, where antennas are required to cover a wide range operating bands. This letter aims at characterizing the loss mechanism of tunable antennas. Tunable antennas typically exhibit a high Quality factor (Q), which ca...... lead to thermal loss due to the conductivity of the metal. The investigation shows that copper loss is non-negligible for high Q values. In the proposed design the copper loss is 2 dB, for a Q of 260 at 700 MHz....

Detecting Faults In High-Voltage Transformers

Science.gov (United States)

Blow, Raymond K.

1988-01-01

Simple fixture quickly shows whether high-voltage transformer has excessive voids in dielectric materials and whether high-voltage lead wires too close to transformer case. Fixture is "go/no-go" indicator; corona appears if transformer contains such faults. Nests in wire mesh supported by cap of clear epoxy. If transformer has defects, blue glow of corona appears in mesh and is seen through cap.

Nested high voltage generator/particle accelerator

International Nuclear Information System (INIS)

Adler, R.J.

1992-01-01

This patent describes a modular high voltage particle accelerator having an emission axis and an emission end, the accelerator. It comprises: a plurality of high voltage generators in nested adjacency to form a nested stack, each the generator comprising a cup-like housing having a base and a tubular sleeve extending from the base, a primary transformer winding encircling the nested stack; a secondary transformer winding between each adjacent pair of housings, magnetically linked to the primary transformer winding through the gaps; a power supply respective to each of the secondary windings converting alternating voltage from its respective secondary winding to d.c. voltage, the housings at the emission end forming a hollow throat for particle acceleration, a vacuum seal at the emission end of the throat which enables the throat to be evacuated; a particle source in the thrond power means to energize the primary transformer winding

Discussion - a high voltage DC generator

International Nuclear Information System (INIS)

Bhagwat, P.V.; Singh, Jagir; Hattangadi, V.A.

1993-01-01

One of the requirements for a high power ion source is a high voltage, high current DC generator. The high voltage, high current generator, DISCATRON, presently under development in our laboratory is a rotating disc type electrostatic generator similar in design to the one reported by A. Isoya et al. (1985). It is compact and rugged electrostatic DC generator based on the principle of induction charging by pellet chains used in the pelletron accelerator. It is, basically, a constant-current device with little stored energy, so that, in case of a breakdown, damage to the equipment connected to the output terminals is minimal. Since the present generator is only a proto-type, meant for a study of the practical difficulties that would be encountered in its manufacture, the output voltage and current specified has been kept quite modest viz., 300 kV at 500 μA, maximum. Some results of the preliminary tests carried out with this generator are described. (author). 4 figs

High voltage investigations for ITER coils

International Nuclear Information System (INIS)

Fink, S.; Fietz, W.H.

2006-01-01

The superconducting ITER magnets will be excited with high voltage during operation and fast discharge. Because the coils are complex systems the internal voltage distribution can differ to a large extent from the ideal linear voltage distribution. In case of fast excitations internal voltages between conductor and radial plate of a TF coil can be even higher than the terminal voltage of 3.5 kV to ground which appears during a fast discharge without a fault. Hence the determination of the transient voltage distribution is important for a proper insulation co-ordination and will provide a necessary basis for the verification of the individual insulation design and the choice of test voltages and waveforms. Especially the extent of internal overvoltages in case of failures, e. g. malfunction of discharge units and / or arcing is of special interest. Transient calculations for the ITER TF coil system have been performed for fast discharge and fault scenarios to define test voltages for ITER TF. The conductor and radial plate insulation of the ITER TF Model Coil were exposed at room temperature to test voltages derived from the results from these calculations. Breakdown appeared during the highest AC voltage step. A fault scenario for the TF fast discharge system is presented where one fault triggers a second fault, leading to considerable voltage stress. In addition a FEM model of Poloidal Field Coil 3 for the determination of the parameters of a detailed network model is presented in order to prepare detailed investigations of the transient voltage behaviour of the PF coils. (author)

Superconducting nanowire single-photon detectors (SNSPDs) on SOI for near-infrared range

Energy Technology Data Exchange (ETDEWEB)

Trojan, Philipp; Il' in, Konstantin; Henrich, Dagmar; Hofherr, Matthias; Doerner, Steffen; Siegel, Michael [Institut fuer Mikro- und Nanoelektronische Systeme (IMS), Karlsruher Institut fuer Technologie (KIT) (Germany); Semenov, Alexey [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Huebers, Heinz-Wilhelm [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Institut fuer Optik und Atomare Physik, Technische Universitaet Berlin (Germany)

2013-07-01

Superconducting nanowire single-photon detectors are promising devices for photon detectors with high count rates, low dark count rates and low dead times. At wavelengths beyond the visible range, the detection efficiency of today's SNSPDs drops significantly. Moreover, the low absorption in ultra-thin detector films is a limiting factor over the entire spectral range. Solving this problem requires approaches for an enhancement of the absorption range in feeding the light to the detector element. A possibility to obtain a better absorption is the use of multilayer substrate materials for photonic waveguide structures. We present results on development of superconducting nanowire single-photon detectors made from niobium nitride on silicon-on-insulator (SOI) multilayer substrates. Optical and superconducting properties of SNSPDs on SOI will be discussed and compared with the characteristics of detectors on common substrates.

High-Q microsphere resonators for angular velocity sensing in gyroscopes

International Nuclear Information System (INIS)

An, Panlong; Zheng, Yongqiu; Yan, Shubin; Xue, Chenyang; Liu, Jun; Wang, Wanjun

2015-01-01

A resonator gyroscope based on the Sagnac effect is proposed using a core unit that is generated by water-hydrogen flame melting. The relationship between the quality factor Q and diameter D is revealed. The Q factor of the spectral lines of the microsphere cavity coupling system, which uses tapered fibers, is found to be 10 6 or more before packaging with a low refractive curable ultraviolet polymer, although it drops to approximately 10 5 after packaging. In addition, a rotating test platform is built, and the transmission spectrum and discriminator curves of a microsphere cavity with Q of 3.22×10 6 are measured using a semiconductor laser (linewidth less than 1 kHz) and a real-time proportional-integral circuit tracking and feedback technique. Equations fitting the relation between the voltage and angular rotation rate are obtained. According to the experimentally measured parameters, the sensitivity of the microsphere-coupled system can reach 0.095 ∘ /s

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

Science.gov (United States)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

High Voltage in Noble Liquids for High Energy Physics

Energy Technology Data Exchange (ETDEWEB)

Rebel, B. [Fermilab; Bernard, E. [Yale U.; Faham, C. H. [LBL, Berkeley; Ito, T. M. [Los Alamos; Lundberg, B. [Maryland U.; Messina, M. [Columbia U.; Monrabal, F. [Valencia U., IFIC; Pereverzev, S. P. [LLNL, Livermore; Resnati, F. [Zurich, ETH; Rowson, P. C. [SLAC; Soderberg, M. [Fermilab; Strauss, T. [Bern U.; Tomas, A. [Imperial Coll., London; Va' vra, J. [SLAC; Wang, H. [UCLA

2014-08-22

A workshop was held at Fermilab November 8-9, 2013 to discuss the challenges of using high voltage in noble liquids. The participants spanned the fields of neutrino, dark matter, and electric dipole moment physics. All presentations at the workshop were made in plenary sessions. This document summarizes the experiences and lessons learned from experiments in these fields at developing high voltage systems in noble liquids.

Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

International Nuclear Information System (INIS)

Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

2006-01-01

A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

High voltage dc-dc converter with dynamic voltage regulation and decoupling during load-generated arcs

Science.gov (United States)

Shimer, Daniel W.; Lange, Arnold C.

1995-01-01

A high-power power supply produces a controllable, constant high voltage output under varying and arcing loads. The power supply includes a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, an output rectifier for producing a dc voltage at the output of each module, and a current sensor for sensing output current. The power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle and circuitry is provided for sensing incipient arc currents at the output of the power supply to simultaneously decouple the power supply circuitry from the arcing load. The power supply includes a plurality of discrete switching type dc--dc converter modules.

High voltage dc--dc converter with dynamic voltage regulation and decoupling during load-generated arcs

Science.gov (United States)

Shimer, D.W.; Lange, A.C.

1995-05-23

A high-power power supply produces a controllable, constant high voltage output under varying and arcing loads. The power supply includes a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, an output rectifier for producing a dc voltage at the output of each module, and a current sensor for sensing output current. The power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle and circuitry is provided for sensing incipient arc currents at the output of the power supply to simultaneously decouple the power supply circuitry from the arcing load. The power supply includes a plurality of discrete switching type dc--dc converter modules. 5 Figs.

Hybrid III-V/SOI resonant cavity enhanced photodetector

DEFF Research Database (Denmark)

Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

2016-01-01

A hybrid III–V/SOI resonant-cavity-enhanced photodetector (RCE-PD) structure comprising a high-contrast grating (HCG) reflector, a hybrid grating (HG) reflector, and an air cavity between them, has been proposed and investigated. In the proposed structure, a light absorbing material is integrated...... as part of the HG reflector, enabling a very compact vertical cavity. Numerical investigations show that a quantum efficiency close to 100 % and a detection linewidth of about 1 nm can be achieved, which are desirable for wavelength division multiplexing applications. Based on these results, a hybrid RCE...

High voltage pulse generator. [Patent application

Science.gov (United States)

Fasching, G.E.

1975-06-12

An improved high-voltage pulse generator is described which is especially useful in ultrasonic testing of rock core samples. An N number of capacitors are charged in parallel to V volts and at the proper instance are coupled in series to produce a high-voltage pulse of N times V volts. Rapid switching of the capacitors from the paralleled charging configuration to the series discharging configuration is accomplished by using silicon-controlled rectifiers which are chain self-triggered following the initial triggering of the first rectifier connected between the first and second capacitors. A timing and triggering circuit is provided to properly synchronize triggering pulses to the first SCR at a time when the charging voltage is not being applied to the parallel-connected charging capacitors. The output voltage can be readily increased by adding additional charging networks. The circuit allows the peak level of the output to be easily varied over a wide range by using a variable autotransformer in the charging circuit.

Simulation of dual-gate SOI MOSFET with different dielectric layers

Science.gov (United States)

Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

2016-04-01

The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Science.gov (United States)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

SOI silicon on glass for optical MEMS

DEFF Research Database (Denmark)

Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

2003-01-01

and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

76 FR 72203 - Voltage Coordination on High Voltage Grids; Notice of Reliability Workshop Agenda

Science.gov (United States)

2011-11-22

... DEPARTMENT OF ENERGY Federal Energy Regulatory Commission [Docket No. AD12-5-000] Voltage Coordination on High Voltage Grids; Notice of Reliability Workshop Agenda As announced in the Notice of Staff..., from 9 a.m. to 4:30 p.m. to explore the interaction between voltage control, reliability, and economic...

Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

2017-02-11

We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

High Voltage Homemade Capacitor Charger for Plasma Focus System

International Nuclear Information System (INIS)

Abdul Halim Baijan; Azaman Ahmad; Rokiah Mohd Sabri; Siti Aiasah Hashim; Mohd Rizal Md Chulan; Wah, L.K.; Azhar Ahmad; Rosli Che Ros; Mohd Faiz Mohd Zin

2015-01-01

A high voltage capacitor charger has been designed and built to replace a high voltage charger type General Atomics CCDs Power Supply which was damaged. The fabrication design was using materials which were easily available in the local market. Among the main components of the high-voltage charger is a transformer for neon lights, variable transformer rated 0 - 240 V 1 KVA, and 240 V transformer isolator. The results of experiments that have been conducted shows that a homemade capacitor charger was able to charge high voltage capacitors up to the required voltage of which was 12 kV. However the time taken for charging is quite long, up to more than 6 minutes. (author)

30 CFR 77.704-1 - Work on high-voltage lines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Work on high-voltage lines. 77.704-1 Section 77... MINES Grounding § 77.704-1 Work on high-voltage lines. (a) No high-voltage line shall be regarded as... provided in § 77.103) that such high-voltage line has been deenergized and grounded. Such qualified person...

Novel Interleaved Converter with Extra-High Voltage Gain to Process Low-Voltage Renewable-Energy Generation

Directory of Open Access Journals (Sweden)

Chih-Lung Shen

2016-10-01

Full Text Available This paper presents a novel interleaved converter (NIC with extra-high voltage gain to process the power of low-voltage renewable-energy generators such as photovoltaic (PV panel, wind turbine, and fuel cells. The NIC can boost a low input voltage to a much higher voltage level to inject renewable energy to DC bus for grid applications. Since the NIC has two circuit branches in parallel at frond end to share input current, it is suitable for high power applications. In addition, the NIC is controlled in an interleaving pattern, which has the advantages that the NIC has lower input current ripple, and the frequency of the ripple is twice the switching frequency. Two coupled inductors and two switched capacitors are incorporated to achieve a much higher voltage gain than conventional high step-up converters. The proposed NIC has intrinsic features such as leakage energy totally recycling and low voltage stress on power semiconductor. Thorough theoretical analysis and key parameter design are presented in this paper. A prototype is built for practical measurements to validate the proposed NIC.

Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

International Nuclear Information System (INIS)

Barchuk, I.P.; Kilchitskaya, V.I.; Lysenko, V.S.

1997-01-01

In this work SOI structures with buried SiO 2 -Si 3 N 4 -SiO 2 layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO 2 layers produced by either the ZMR or the SIMOX technique

Complete low power controller for high voltage power systems

International Nuclear Information System (INIS)

Sumner, R.; Blanar, G.

1997-01-01

The MHV100 is a custom CMOS integrated circuit, developed for the AMS experiment. It provides complete control for a single channel high voltage (HV) generator and integrates all the required digital communications, D to A and A to D converters, the analog feedback loop and output drivers. This chip has been designed for use in both distributed high voltage systems or for low cost single channel high voltage systems. The output voltage and current range is determined by the external components

E-beam high voltage switching power supply

Science.gov (United States)

Shimer, Daniel W.; Lange, Arnold C.

1997-01-01

A high power, solid state power supply is described for producing a controllable, constant high voltage output under varying and arcing loads suitable for powering an electron beam gun or other ion source. The present power supply is most useful for outputs in a range of about 100-400 kW or more. The power supply is comprised of a plurality of discrete switching type dc-dc converter modules, each comprising a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, and an output rectifier for producing a dc voltage at the output of each module. The inputs to the converter modules are fed from a common dc rectifier/filter and are linked together in parallel through decoupling networks to suppress high frequency input interactions. The outputs of the converter modules are linked together in series and connected to the input of the transmission line to the load through a decoupling and line matching network. The dc-dc converter modules are phase activated such that for n modules, each module is activated equally 360.degree./n out of phase with respect to a successive module. The phased activation of the converter modules, combined with the square current waveforms out of the step up transformers, allows the power supply to operate with greatly reduced output capacitance values which minimizes the stored energy available for discharge into an electron beam gun or the like during arcing. The present power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle using simulated voltage feedback signals and voltage feedback loops. Circuitry is also provided for sensing incipient arc currents reflected at the output of the power supply and for simultaneously decoupling the power supply circuitry from the arcing load.

E-beam high voltage switching power supply

International Nuclear Information System (INIS)

Shimer, D.W.; Lange, A.C.

1997-01-01

A high power, solid state power supply is described for producing a controllable, constant high voltage output under varying and arcing loads suitable for powering an electron beam gun or other ion source. The present power supply is most useful for outputs in a range of about 100-400 kW or more. The power supply is comprised of a plurality of discrete switching type dc-dc converter modules, each comprising a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, and an output rectifier for producing a dc voltage at the output of each module. The inputs to the converter modules are fed from a common dc rectifier/filter and are linked together in parallel through decoupling networks to suppress high frequency input interactions. The outputs of the converter modules are linked together in series and connected to the input of the transmission line to the load through a decoupling and line matching network. The dc-dc converter modules are phase activated such that for n modules, each module is activated equally 360 degree/n out of phase with respect to a successive module. The phased activation of the converter modules, combined with the square current waveforms out of the step up transformers, allows the power supply to operate with greatly reduced output capacitance values which minimizes the stored energy available for discharge into an electron beam gun or the like during arcing. The present power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle using simulated voltage feedback signals and voltage feedback loops. Circuitry is also provided for sensing incipient arc currents reflected at the output of the power supply and for simultaneously decoupling the power supply circuitry from the arcing load. 7 figs

PC-based control of a high-voltage injector

International Nuclear Information System (INIS)

Constantin, F.

1998-01-01

The stability of high voltage injectors is one of the major problems in any accelerator system. Most of the troubles encountered in the normal operation of an accelerator are connected with the ion source and associated high voltage platforms, regardless of the source or high voltage generator type. The quality of the ion beam injected in the accelerator strongly depends on the power supplies used in the injector and on the ability to control the non-electrical parameters (gas-flow, temperature, etc.). A wide used method in controlling is based on optical links between high-voltage platform and computer, the adjustments being more or less automated. Although the method mentioned above can be still useful in injector control, a different approach is presented in this work, i.e., the computer itself is placed inside the high-voltage terminal. Only one optical link is still necessary to connect this computer with an user-friendly host at ground potential. Requirements: - varying and monitoring the filament current; - gas flow control in the ion source; - reading the vacuum values; - current and voltage control for the anodic, magnet, extraction, suppression and lens' sources. Even in the high voltage terminal there are compartments with different voltages regardless the floating ground. In our injector the extraction voltage is applied on the top of the ion source including the filament and the anodic voltage. The extraction voltage is of maximum 30 kV. In this situation a second optical link is required to transfer the control for the anodic and magnet source power supply assuming the dedicated computer on the floating ground. One PC is placed inside the high voltage terminal and one PC outside the injector. The optical link (more precisely two optical wires) connects the serial ports. The inside computer is equipped with two multipurpose ADC/DAC and digital I/O card. They permit to read or output DC levels ranging between 0 to 10 volts or TTL signals. The filament

High voltage generator circuit with low power and high efficiency applied in EEPROM

International Nuclear Information System (INIS)

Liu Yan; Zhang Shilin; Zhao Yiqiang

2012-01-01

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

Suppression of the high-frequency disturbances in low-voltage circuits caused by disconnector operation in high-voltage open-air substations

Energy Technology Data Exchange (ETDEWEB)

Savic, M.S.

1986-07-01

The switching off and on of small capacitive currents charging busbar capacitances, connection conductors and open circuit breakers with disconnectors causes high-frequency transients in high-voltage networks. In low voltage circuits, these transient processes induce dangerous overvoltages for the electronic equipment in the substation. A modified construction of the disconnector with a damping resistor was investigated. Digital simulation of the transient process in a high-voltage network during the arcing period between the disconnector contacts with and without damping resistor were performed. A significant decrease of the arcing duration and the decrease of the electromagnetic field magnitude in the vicinity of the operating disconnector were noticed. In the low voltage circuit protected with the surge arrester, the overvoltage magnitude was not affected by the damping resistor due to the arrester protection effect.

Experimental validation of prototype high voltage bushing

Science.gov (United States)

Shah, Sejal; Tyagi, H.; Sharma, D.; Parmar, D.; M. N., Vishnudev; Joshi, K.; Patel, K.; Yadav, A.; Patel, R.; Bandyopadhyay, M.; Rotti, C.; Chakraborty, A.

2017-08-01

Prototype High voltage bushing (PHVB) is a scaled down configuration of DNB High Voltage Bushing (HVB) of ITER. It is designed for operation at 50 kV DC to ensure operational performance and thereby confirming the design configuration of DNB HVB. Two concentric insulators viz. Ceramic and Fiber reinforced polymer (FRP) rings are used as double layered vacuum boundary for 50 kV isolation between grounded and high voltage flanges. Stress shields are designed for smooth electric field distribution. During ceramic to Kovar brazing, spilling cannot be controlled which may lead to high localized electrostatic stress. To understand spilling phenomenon and precise stress calculation, quantitative analysis was performed using Scanning Electron Microscopy (SEM) of brazed sample and similar configuration modeled while performing the Finite Element (FE) analysis. FE analysis of PHVB is performed to find out electrical stresses on different areas of PHVB and are maintained similar to DNB HV Bushing. With this configuration, the experiment is performed considering ITER like vacuum and electrical parameters. Initial HV test is performed by temporary vacuum sealing arrangements using gaskets/O-rings at both ends in order to achieve desired vacuum and keep the system maintainable. During validation test, 50 kV voltage withstand is performed for one hour. Voltage withstand test for 60 kV DC (20% higher rated voltage) have also been performed without any breakdown. Successful operation of PHVB confirms the design of DNB HV Bushing. In this paper, configuration of PHVB with experimental validation data is presented.

30 CFR 75.811 - High-voltage underground equipment; grounding.

Science.gov (United States)

2010-07-01

...-voltage equipment supplying power to such equipment receiving power from resistance grounded systems shall... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage underground equipment; grounding... COAL MINE SAFETY AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Underground High-Voltage...

Investigations of a voltage-biased microwave cavity for quantum measurements of nanomechanical resonators

Science.gov (United States)

Rouxinol, Francisco; Hao, Hugo; Lahaye, Matt

2015-03-01

Quantum electromechanical systems incorporating superconducting qubits have received extensive interest in recent years due to their promising prospects for studying fundamental topics of quantum mechanics such as quantum measurement, entanglement and decoherence in new macroscopic limits, also for their potential as elements in technological applications in quantum information network and weak force detector, to name a few. In this presentation we will discuss ours efforts toward to devise an electromechanical circuit to strongly couple a nanomechanical resonator to a superconductor qubit, where a high voltage dc-bias is required, to study quantum behavior of a mechanical resonator. Preliminary results of our latest generation of devices integrating a superconductor qubit into a high-Q voltage biased microwave cavities are presented. Developments in the circuit design to couple a mechanical resonator to a qubit in the high-Q voltage bias CPW cavity is discussed as well prospects of achieving single-phonon measurement resolution. National Science Foundation under Grant No. DMR-1056423 and Grant No. DMR-1312421.

Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

International Nuclear Information System (INIS)

Hamilton, J.J.; Collart, E.J.H.; Colombeau, B.; Jeynes, C.; Bersani, M.; Giubertoni, D.; Sharp, J.A.; Cowern, N.E.B.; Kirkby, K.J.

2005-01-01

The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface

High-voltage nanosecond pulse shaper

International Nuclear Information System (INIS)

Kapishnikov, N.K.; Muratov, V.M.; Shatanov, A.A.

1987-01-01

A high-voltage pulse shaper with an output of up to 250 kV, a base duration of ∼ 10 nsec, and a repetition frequency of 50 pulses/sec is described. The described high-voltage nanosecond pulse shaper is designed for one-orbit extraction of an electron beam from a betatron. A diagram of the pulse shaper, which employs a single-stage generator is shown. The shaping element is a low-inductance capacitor bank of series-parallel KVI-3 (2200 pF at 10 kV) or K15-10 (4700 pF at 31.5 kV) disk ceramic capacitors. Four capacitors are connected in parallel and up to 25 are connected in series

High temperature piezoresistive {beta}-SiC-on-SOI pressure sensor for combustion engines

Energy Technology Data Exchange (ETDEWEB)

Berg, J. von; Ziermann, R.; Reichert, W.; Obermeier, E. [Tech. Univ. Berlin (Germany). Microsensor and Actuator Technol. Center; Eickhoff, M.; Kroetz, G. [Daimler Benz AG, Munich (Germany); Thoma, U.; Boltshauser, T.; Cavalloni, C. [Kistler Instrumente AG, Winterthur (Switzerland); Nendza, J.P. [TRW Deutschland GmbH, Barsinghausen (Germany)

1998-08-01

For measuring the cylinder pressure in combustion engines of automobiles a high temperature pressure sensor has been developed. The sensor is made of a membrane based piezoresistive {beta}-SiC-on-SOI (SiCOI) sensor chip and a specially designed housing. The SiCOI sensor was characterized under static pressures of up to 200 bar in the temperature range between room temperature and 300 C. The sensitivity of the sensor at room temperature is approximately 0.19 mV/bar and decreases to about 0.12 mV/bar at 300 C. For monitoring the dynamic cylinder pressure the sensor was placed into the combustion chamber of a gasoline engine. The measurements were performed at 1500 rpm under different loads, and for comparison a quartz pressure transducer from Kistler AG was used as a reference. The maximum pressure at partial load operation amounts to about 15 bar. The difference between the calibrated SiCOI sensor and the reference sensor is significantly less than 1 bar during the whole operation. (orig.) 8 refs.

High voltage performance of BARC-TIFR Pelletron Accelerator

Energy Technology Data Exchange (ETDEWEB)

Surendran, P.; Ansari, Q.N.; Nair, J.P., E-mail: surendra@tifr.res.in [Nuclear Physics Division, Bhabha Atomic Research Centre, Mumbai (India); and others

2014-07-01

The 14 UD Pelletron Accelerator at TIFR, Mumbai is operational since its inception in 1988. It was decided to impart enough time for high voltage conditioning to achieve higher operational voltage. Prior to this, comprehensive works such as replacing all the sputter ion pumps and Titanium sublimation pumps across the accelerator tube with new or refurbished ones and replacement of Alumina balls in the SF{sub 6} drier with fresh balls were carried out. High voltage conditioning of each module was done. Further conditioning of two modules at a time in overlapping mode improved the terminal voltage. As a result of this rigorous conditioning Terminal voltage of 12.6 MV was achieved and beam has been delivered to users at 12 MV terminal. Details of this effort will be presented in this paper. (author)

High voltage performance of BARC-TIFR Pelletron Accelerator

International Nuclear Information System (INIS)

Surendran, P.; Ansari, Q.N.; Nair, J.P.

2014-01-01

The 14 UD Pelletron Accelerator at TIFR, Mumbai is operational since its inception in 1988. It was decided to impart enough time for high voltage conditioning to achieve higher operational voltage. Prior to this, comprehensive works such as replacing all the sputter ion pumps and Titanium sublimation pumps across the accelerator tube with new or refurbished ones and replacement of Alumina balls in the SF_6 drier with fresh balls were carried out. High voltage conditioning of each module was done. Further conditioning of two modules at a time in overlapping mode improved the terminal voltage. As a result of this rigorous conditioning Terminal voltage of 12.6 MV was achieved and beam has been delivered to users at 12 MV terminal. Details of this effort will be presented in this paper. (author)

PV source based high voltage gain current fed converter

Science.gov (United States)

Saha, Soumya; Poddar, Sahityika; Chimonyo, Kudzai B.; Arunkumar, G.; Elangovan, D.

2017-11-01

This work involves designing and simulation of a PV source based high voltage gain, current fed converter. It deals with an isolated DC-DC converter which utilizes boost converter topology. The proposed converter is capable of high voltage gain and above all have very high efficiency levels as proved by the simulation results. The project intends to produce an output of 800 V dc from a 48 V dc input. The simulation results obtained from PSIM application interface were used to analyze the performance of the proposed converter. Transformer used in the circuit steps up the voltage as well as to provide electrical isolation between the low voltage and high voltage side. Since the converter involves high switching frequency of 100 kHz, ultrafast recovery diodes are employed in the circuitry. The major application of the project is for future modeling of solar powered electric hybrid cars.

30 CFR 77.804 - High-voltage trailing cables; minimum design requirements.

Science.gov (United States)

2010-07-01

... OF UNDERGROUND COAL MINES Surface High-Voltage Distribution § 77.804 High-voltage trailing cables; minimum design requirements. (a) High-voltage trailing cables used in resistance grounded systems shall be... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage trailing cables; minimum design...

Towards Polarization Diversity on the SOI Platform With Simple Fabrication Process

DEFF Research Database (Denmark)

Ding, Yunhong; Liu, Liu; Peucheret, Christophe

2011-01-01

We present a polarization diversity circuit built on the silicon-on-insulator (SOI) platform, which can be fabricated by a simple process. The polarization diversity is based on two identical air-clad asymmetrical directional couplers, which simultaneously play the roles of polarization splitter...... and rotator. A silicon polarization diversity circuit with a single microring resonator is fabricated on the SOI platform. Only ${1-dB polarization-dependent loss is demonstrated. A significant improvement of the polarization dependence is obtained for 20-Gb/s nonreturn-to-zero differential phase-shift keying...

Characterization of ultrathin SOI film and application to short channel MOSFETs.

Science.gov (United States)

Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

2008-04-23

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

The high voltage homopolar generator

Science.gov (United States)

Price, J. H.; Gully, J. H.; Driga, M. D.

1986-11-01

System and component design features of proposed high voltage homopolar generator (HVHPG) are described. The system is to have an open circuit voltage of 500 V, a peak output current of 500 kA, 3.25 MJ of stored inertial energy and possess an average magnetic-flux density of 5 T. Stator assembly components are discussed, including the stator, mount structure, hydrostatic bearings, main and motoring brushgears and rotor. Planned operational procedures such as monitoring the rotor to full speed and operation with a superconducting field coil are delineated.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

Science.gov (United States)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Voltage Balancing Method on Expert System for 51-Level MMC in High Voltage Direct Current Transmission

Directory of Open Access Journals (Sweden)

Yong Chen

2016-01-01

Full Text Available The Modular Multilevel Converters (MMC have been a spotlight for the high voltage and high power transmission systems. In the VSC-HVDC (High Voltage Direct Current based on Voltage Source Converter transmission system, the energy of DC link is stored in the distributed capacitors, and the difference of capacitors in parameters and charge rates causes capacitor voltage balance which affects the safety and stability of HVDC system. A method of MMC based on the expert system for reducing the frequency of the submodules (SMs of the IGBT switching frequency is proposed. Firstly, MMC with 51 levels for HVDC is designed. Secondly, the nearest level control (NLC for 51-level MMC is introduced. Thirdly, a modified capacitor voltage balancing method based on expert system for MMC-based HVDC transmission system is proposed. Finally, a simulation platform for 51-level Modular Multilevel Converter is constructed by using MATLAB/SIMULINK. The results indicate that the strategy proposed reduces the switching frequency on the premise of keeping submodule voltage basically identical, which greatly reduces the power losses for MMC-HVDC system.

An analysis of radiation effects on electronics and soi-mos devices as an alternative

International Nuclear Information System (INIS)

Ikraiam, F. A.

2013-01-01

The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

Solid-state high voltage modulator and its application to rf source high voltage power supplies

International Nuclear Information System (INIS)

Tooker, J.F.; Huynh, P.; Street, R.W.

2009-01-01

A solid-state high voltage modulator is described in which series-connected insulated-gate bipolar transistors (IGBTs) are switched at a fixed frequency by a pulse width modulation (PWM) regulator, that adjusts the pulse width to control the voltage out of an inductor-capacitor filter network. General Atomics proposed the HV power supply (HVPS) topology of multiple IGBT modulators connected to a common HVdc source for the large number of 1 MW klystrons in the linear accelerator of the Accelerator Production of Tritium project. The switching of 24 IGBTs to obtain 20 kVdc at 20 A for short pulses was successfully demonstrated. This effort was incorporated into the design of a -70 kV, 80 A, IGBT modulator, and in a short-pulse test 12 IGBTs regulated -5 kV at 50 A under PWM control. These two tests confirm the practicality of solid-state IGBT modulators to regulate high voltage at reasonable currents. Tokamaks such as ITER require large rf heating and current drive systems with multiple rf sources. A HVPS topology is presented that readily adapts to the three rf heating systems on ITER. To take advantage of the known economy of scale for power conversion equipment, a single HVdc source feeds multiple rf sources. The large power conversion equipment, which is located outside, converts the incoming utility line voltage directly to the HVdc needed for the class of rf sources connected to it, to further reduce cost. The HVdc feeds a set of IGBT modulators, one for each rf source, to independently control the voltage applied to each source, maximizing operational flexibility. Only the modulators are indoors, close to the rf sources, minimizing the use of costly near-tokamak floor space.

High voltage capacitor design and the determination of solid dielectric voltage breakdown

International Nuclear Information System (INIS)

Hutapea, S.

1976-01-01

The value of the external field intensity serves as an electrical insulating material and is a physical characteristic of the substance. Capacitor discharge in the dielectric medium are experimentally investigated. The high voltage power supply and other instrument needed are briefly discussed. Capacitors with working voltage of 30.000 volt and the plastic being used for dielectrics in the capacitors are also discussed. (author)

Generation and confinement of mobile charges in buried oxide of SOI substrates; Generation et confinement de charges mobiles dans les oxydes enterres de substrats SOI

Energy Technology Data Exchange (ETDEWEB)

Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A. [CEA Bruyeres-le-Chatel, DIF, 91 (France)

1999-07-01

We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO{sub 2} interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

Development of a broadband reflective T-filter for voltage biasing high-Q superconducting microwave cavities

International Nuclear Information System (INIS)

Hao, Yu; Rouxinol, Francisco; LaHaye, M. D.

2014-01-01

We present the design of a reflective stop-band filter based on quasi-lumped elements that can be utilized to introduce large dc and low-frequency voltage biases into a low-loss superconducting coplanar waveguide (CPW) cavity. Transmission measurements of the filter are seen to be in good agreement with simulations and demonstrate insertion losses greater than 20 dB in the range of 3–10 GHz. Moreover, transmission measurements of the CPW's fundamental mode demonstrate that loaded quality factors exceeding 10 5 can be achieved with this design for dc voltages as large as 20 V and for the cavity operated in the single-photon regime. This makes the design suitable for use in a number of applications including qubit-coupled mechanical systems and circuit QED

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Directory of Open Access Journals (Sweden)

A. Karsenty

2013-01-01

Full Text Available Ultrathin body (UTB and nanoscale body (NSB SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

Charge collection mechanisms in MOS/SOI transistors irradiated by energetic heavy ions

International Nuclear Information System (INIS)

Musseau, O.; Leray, J.L.; Ferlet, V.; Umbert, A.; Coic, Y.M.; Hesto, P.

1991-01-01

We have investigated with both experimental and numerical methods (Monte Carlo and drift-diffusion models) various charge collection mechanisms in NMOS/SOI transistors irradiated by single energetic heavy ions. Our physical interpretations of data emphasize the influence of various parasitic structures of the device. Two charge collection mechanisms are detailed: substrate funneling in buried MOS capacitor and latching of the parasitic bipolar transistor. Based on carrier transport and charge collection, the sensitivity of future scaled down CMOS/SOI technologies is finally discussed

30 CFR 77.807-1 - High-voltage powerlines; clearances above ground.

Science.gov (United States)

2010-07-01

... OF UNDERGROUND COAL MINES Surface High-Voltage Distribution § 77.807-1 High-voltage powerlines; clearances above ground. High-voltage powerlines located above driveways, haulageways, and railroad tracks...

Design and Implementation of a High Efficiency, Low Component Voltage Stress, Single-Switch High Step-Up Voltage Converter for Vehicular Green Energy Systems

Directory of Open Access Journals (Sweden)

Yu-En Wu

2016-09-01

Full Text Available In this study, a novel, non-isolated, cascade-type, single-switch, high step-up DC/DC converter was developed for green energy systems. An integrated coupled inductor and voltage lift circuit were applied to simplify the converter structure and satisfy the requirements of high efficiency and high voltage gain ratios. In addition, the proposed structure is controllable with a single switch, which effectively reduces the circuit cost and simplifies the control circuit. With the leakage inductor energy recovery function and active voltage clamp characteristics being present, the circuit yields optimizable conversion efficiency and low component voltage stress. After the operating principles of the proposed structure and characteristics of a steady-state circuit were analyzed, a converter prototype with 450 W, 40 V of input voltage, 400 V of output voltage, and 95% operating efficiency was fabricated. The Renesas MCU RX62T was employed to control the circuits. Experimental results were analyzed to validate the feasibility and effectiveness of the proposed system.

High-voltage test and measuring techniques

CERN Document Server

Hauschild, Wolfgang

2014-01-01

It is the intent of this book to combine high-voltage (HV) engineering with HV testing technique and HV measuring technique. Based on long-term experience gained by the authors as lecturer and researcher as well as member in international organizations, such as IEC and CIGRE, the book will reflect the state of the art as well as the future trends in testing and diagnostics of HV equipment to ensure a reliable generation, transmission and distribution of electrical energy. The book is intended not only for experts but also for students in electrical engineering and high-voltage engineering.

Design and Implementation of a High-Voltage Generator with Output Voltage Control for Vehicle ER Shock-Absorber Applications

Directory of Open Access Journals (Sweden)

Chih-Lung Shen

2013-01-01

Full Text Available A self-oscillating high-voltage generator is proposed to supply voltage for a suspension system in order to control the damping force of an electrorheological (ER fluid shock absorber. By controlling the output voltage level of the generator, the damping force in the ER fluid shock absorber can be adjusted immediately. The shock absorber is part of the suspension system. The high-voltage generator drives a power transistor based on self-excited oscillation, which converts dc to ac. A high-frequency transformer with high turns ratio is used to increase the voltage. In addition, the system uses the car battery as dc power supply. By regulating the duty cycle of the main switch in the buck converter, the output voltage of the buck converter can be linearly adjusted so as to obtain a specific high voltage for ER. The driving system is self-excited; that is, no additional external driving circuit is required. Thus, it reduces cost and simplifies system structure. A prototype version of the actual product is studied to measure and evaluate the key waveforms. The feasibility of the proposed system is verified based on experimental results.

Optical control system for high-voltage terminals

International Nuclear Information System (INIS)

Bicek, J.J.

1978-01-01

An optical control system for the control of devices in the terminal of an electrostatic accelerator includes a laser that is modulated by a series of preselected codes produced by an encoder. A photodiode receiver is placed in the laser beam at the high-voltage terminal of an electrostatic accelerator. A decoder connected to the photodiode decodes the signals to provide control impulses for a plurality of devices at the high voltage of the terminal

Ultra compact triplexing filters based on SOI nanowire AWGs

Science.gov (United States)

Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

2011-04-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

High-voltage pulse generator for electron gun power supply

International Nuclear Information System (INIS)

Korenev, S.A.; Enchevich, I.B.; Mikhov, M.K.

1987-01-01

High-voltage pulse generator with combined capacitive and inductive energy storages for electron gun power supply is described. Hydrogen thyratron set in a short magnetic lense is a current breaker. Times of current interruption in thyratrons are in the range from 100 to 300 ns. With 1 kV charging voltage of capacitive energy storage 25 kV voltage pulse is obtained in the load. The given high-voltage pulse generator was used for supply of an electron gun generating 10-30 keV low-energy electron beam

21 CFR 892.1700 - Diagnostic x-ray high voltage generator.

Science.gov (United States)

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Diagnostic x-ray high voltage generator. 892.1700... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1700 Diagnostic x-ray high voltage generator. (a) Identification. A diagnostic x-ray high voltage generator is a device that is intended to...

30 CFR 75.705-1 - Work on high-voltage lines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Work on high-voltage lines. 75.705-1 Section 75... AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Grounding § 75.705-1 Work on high-voltage lines. (a) Section 75.705 specifically prohibits work on energized high-voltage lines underground; (b...

Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

2012-01-01

Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

High Voltage Charge Pump

KAUST Repository

Emira, Ahmed A.; Abdelghany, Mohamed A.; Elsayed, Mohannad Yomn; Elshurafa, Amro M; Salama, Khaled N.

2014-01-01

Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

High Voltage Charge Pump

KAUST Repository

Emira, Ahmed A.

2014-10-09

Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

Coordinated voltage control in offshore HVDC connected cluster of wind power plants

DEFF Research Database (Denmark)

Sakamuri, Jayachandra Naidu; Rather, Zakir Hussain; Rimez, Johan

This paper presents a coordinated voltage control scheme (CVCS) for a cluster of offshore wind power plants connected to a voltage-source converter-based high-voltage direct current system. The primary control point of the proposed voltage control scheme is the introduced Pilot bus, which is having...... by dispatching reactive power references to each wind turbine (WT) in the wind power plant cluster based on their available reactive power margin and network sensitivity-based participation factors, which are derived from the dV/dQ sensitivity of a WT bus w.r.t. the Pilot bus. This method leads...

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

2012-01-01

The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

Science.gov (United States)

Duclaux, Benjamin; De Caunes, Jean; Perrier, Robin; Gatefait, Maxime; Le Gratiet, Bertrand; Chapon, Jean-Damien; Monget, Cédric

2018-03-01

Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the "more than Moore" path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or "virtual overlay" could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

Modular High Voltage Power Supply

Energy Technology Data Exchange (ETDEWEB)

Newell, Matthew R. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

2017-05-18

The goal of this project is to develop a modular high voltage power supply that will meet the needs of safeguards applications and provide a modular plug and play supply for use with standard electronic racks.

A compact 100 kV high voltage glycol capacitor.

Science.gov (United States)

Wang, Langning; Liu, Jinliang; Feng, Jiahuai

2015-01-01

A high voltage capacitor is described in this paper. The capacitor uses glycerol as energy storage medium, has a large capacitance close to 1 nF, can hold off voltages of up to 100 kV for μs charging time. Allowing for low inductance, the capacitor electrode is designed as coaxial structure, which is different from the common structure of the ceramic capacitor. With a steady capacitance at different frequencies and a high hold-off voltage of up to 100 kV, the glycol capacitor design provides a potential substitute for the ceramic capacitors in pulse-forming network modulator to generate high voltage pulses with a width longer than 100 ns.

Transmission of power at high voltages

Energy Technology Data Exchange (ETDEWEB)

Lane, F J

1963-01-01

High voltage transmission is considered to be concerned with circuits and systems operating at or above 132 kV. While the general examination is concerned with ac transmission, dc systems are also included. The choice of voltage for a system will usually involve hazardous assessments of the future requirements of industry, commerce and a changing population. Experience suggests that, if the estimated economic difference between two voltages is not significant, there is good reason to choose the higher voltage, as this will make the better provision for unexpected future expansion. Two principal functions served by transmission circuits in a supply system are: (a) the transportation of energy in bulk from the generator to the reception point in the distribution system; and (b) the interconnection and integration of the generating plant and associated loads. These functions are considered and various types of system are discussed in terms of practicability, viability, quality and continuity of supply. Future developments requiring transmission voltages up to 750 kV will raise many problems which are in the main empirical. Examples are given of the type of problem envisaged and it is suggested that these can only be partially solved by theory and model operation.

Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

International Nuclear Information System (INIS)

Naumova, O V; Fomin, B I; Ilnitsky, M A; Popov, V P

2012-01-01

In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 10 5 –5 × 10 7 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO 2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to k i ln D. The coefficients k i for as-fabricated and ion-implanted Si/buried SiO 2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO 2 interface. (paper)

30 CFR 77.704-2 - Repairs to energized high-voltage lines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Repairs to energized high-voltage lines. 77.704... UNDERGROUND COAL MINES Grounding § 77.704-2 Repairs to energized high-voltage lines. An energized high-voltage... repairs will be performed on power circuits with a phase-to-phase nominal voltage no greater than 15,000...

Multiple High Voltage Pulse Stressing of Polymer Thick Film Resistors

Directory of Open Access Journals (Sweden)

Busi Rambabu

2014-01-01

Full Text Available The purpose of this paper is to study high voltage interactions in polymer thick film resistors, namely, polyvinyl chloride- (PVC- graphite thick film resistors, and their applications in universal trimming of these resistors. High voltages in the form of impulses for various pulse durations and with different amplitudes have been applied to polymer thick film resistors and we observed the variation of resistance of these resistors with high voltages. It has been found that the resistance of polymer thick film resistors decreases in the case of higher resistivity materials and the resistance of polymer thick film resistor increases in the case of lower resistivity materials when high voltage impulses are applied to them. It has been also found that multiple high voltage pulse (MHVP stressing can be used to trim the polymer thick film resistors either upwards or downwards.

Low cost photomultiplier high-voltage readout system

International Nuclear Information System (INIS)

Oxoby, G.J.; Kunz, P.F.

1976-10-01

The Large Aperture Solenoid Spectrometer (LASS) at Stanford Linear Accelerator Center (SLAC) requires monitoring over 300 voltages. This data is recorded on magnetic tapes along with the event data. It must also be displayed so that operators can easily monitor and adjust the voltages. A low-cost high-voltage readout system has been implemented to offer stand-alone digital readout capability as well as fast data transfer to a host computer. The system is flexible enough to permit use of a DVM or ADC and commercially available analogue multiplexers

Design & Fabrication of a High-Voltage Photovoltaic Cell

Energy Technology Data Exchange (ETDEWEB)

Felder, Jennifer; /North Carolina State U. /SLAC

2012-09-05

Silicon photovoltaic (PV) cells are alternative energy sources that are important in sustainable power generation. Currently, applications of PV cells are limited by the low output voltage and somewhat low efficiency of such devices. In light of this fact, this project investigates the possibility of fabricating high-voltage PV cells on float-zone silicon wafers having output voltages ranging from 50 V to 2000 V. Three designs with different geometries of diffusion layers were simulated and compared in terms of metal coverage, recombination, built-in potential, and conduction current density. One design was then chosen and optimized to be implemented in the final device design. The results of the simulation serve as a feasibility test for the design concept and provide supportive evidence of the effectiveness of silicon PV cells as high-voltage power supplies.

Detuning effect study of High-Q Mobile Phone Antennas

DEFF Research Database (Denmark)

Bahramzy, Pevand; Pedersen, Gert F.

2015-01-01

Number of frequency bands that have to be covered by smart phones, are ever increasing. This broadband coverage can be obtained either by using a low-Q antenna or a high-Q tunable antenna. This study investigates high-Q antennas performance when placed in proximity of the user. This study...

Micro controller application as x-ray machine's high voltage controller

International Nuclear Information System (INIS)

Wiranto Budi Santoso; Beny Syawaludin

2010-01-01

The micro controller application as x-ray machine's high voltage controller has been carried out. The purpose of this micro controller application is to give an accurate high voltage supply to the x-ray tube so that the x ray machine could produce the result as expected. The micro controller based X-ray machine's high voltage controller receives an input voltage from the keypad. This input value is displayed in the LCD (Liquid Crystal Display) screen. Then micro controller uses this input data to drive the stepper motor. The stepper motor adjusts the high voltage auto transformer's output according to the input value. The micro controller is programmed using BASCOM-B051 compiler. The test results show that the stepper motor could rotate according to an input value. (author)

Integrated differential high-voltage transmitting circuit for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

2015-01-01

In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

High-voltage pulse generator synchronous with LINAC

International Nuclear Information System (INIS)

Muto, M.; Hiratsuka, Yoshio; Niimura, Nobuo

1974-01-01

High-voltage pulse generator (H.V. Flip-Flop) No.2, an improved type of No.1, is described, which is used in the structural analysis of transient phenomena in materials through the neutron TOF with a Linac. The method of producing positive and negative high-voltage pulses synchronous with the Linac is identical with that in No.1. However, No.2 has outstanding features as follows: (1) The rise time of output pulses is reduced to 0.3 msec, due to the improvement of switching circuit and the winding of a step-up transformer; (2) The widths of positive and negative pulses are variable up to maximum 8 and 16 frames, respectively (One frame = 10 msec); (3) The distribution of TOF signals from a BF 3 counter to a time analyzer is possible even in the negative voltage duration. The panel is provided with the switches for choosing pulse width and the frame for analysis, as well as the dials for setting positive/negative pulse voltage values and the respective indicating meters. (Mori, K)

30 CFR 18.54 - High-voltage continuous mining machines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage continuous mining machines. 18.54... and Design Requirements § 18.54 High-voltage continuous mining machines. (a) Separation of high... ground. (e) Onboard ungrounded, three-phase power circuit. A continuous mining machine designed with an...

Ultra compact triplexing filters based on SOI nanowire AWGs

Energy Technology Data Exchange (ETDEWEB)

Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei, E-mail: junming@red.semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2011-04-15

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

Ultra compact triplexing filters based on SOI nanowire AWGs

International Nuclear Information System (INIS)

Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei

2011-01-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

SOI Digital Accelerometer Based on Pull-in Time Configuration

NARCIS (Netherlands)

Pakula, L.S.; Rajaraman, V.; French, P.J.

2009-01-01

The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The

Fully-etched apodized fiber-to-chip grating coupler on the SOI platform with -0.78 dB coupling efficiency using photonic crystals and bonded Al mirror

DEFF Research Database (Denmark)

Ding, Yunhong; Ou, Haiyan; Peucheret, Christophe

2014-01-01

We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated.......We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated....

High-Voltage, Low-Power BNC Feedthrough Terminator

Science.gov (United States)

Bearden, Douglas

2012-01-01

This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

High-Capacity Cathode Material with High Voltage for Li-Ion Batteries.

Science.gov (United States)

Shi, Ji-Lei; Xiao, Dong-Dong; Ge, Mingyuan; Yu, Xiqian; Chu, Yong; Huang, Xiaojing; Zhang, Xu-Dong; Yin, Ya-Xia; Yang, Xiao-Qing; Guo, Yu-Guo; Gu, Lin; Wan, Li-Jun

2018-03-01

Electrochemical energy storage devices with a high energy density are an important technology in modern society, especially for electric vehicles. The most effective approach to improve the energy density of batteries is to search for high-capacity electrode materials. According to the concept of energy quality, a high-voltage battery delivers a highly useful energy, thus providing a new insight to improve energy density. Based on this concept, a novel and successful strategy to increase the energy density and energy quality by increasing the discharge voltage of cathode materials and preserving high capacity is proposed. The proposal is realized in high-capacity Li-rich cathode materials. The average discharge voltage is increased from 3.5 to 3.8 V by increasing the nickel content and applying a simple after-treatment, and the specific energy is improved from 912 to 1033 Wh kg -1 . The current work provides an insightful universal principle for developing, designing, and screening electrode materials for high energy density and energy quality. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

First high-voltage measurements using Ca{sup +} ions at the ALIVE experiment

Energy Technology Data Exchange (ETDEWEB)

König, K., E-mail: kkoenig@ikp.tu-darmstadt.de [Technische Universität Darmstadt, Institut für Kernphysik (Germany); Geppert, Ch. [Universität Mainz, Institut für Kernchemie (Germany); Krämer, J.; Maaß, B. [Technische Universität Darmstadt, Institut für Kernphysik (Germany); Otten, E. W. [Universität Mainz, Institut für Physik (Germany); Ratajczyk, T.; Nörtershäuser, W. [Technische Universität Darmstadt, Institut für Kernphysik (Germany)

2017-11-15

Many physics experiments depend on accurate high-voltage measurements to determine for example the exact retardation potential of an electron spectrometer as in the KATRIN experiment or the acceleration voltage of the ions at ISOL facilities. Until now only precision high-voltage dividers can be used to measure voltages up to 65 kV with an accuracy of 1 ppm. However, these dividers need frequent calibration and cross-checking and the direct traceability is not given. In this article we will describe the status of an experiment which aims to measure high voltages using collinear laser spectroscopy and which has the potential to provide a high-voltage standard and hence, a calibration source for precision high-voltage dividers on the 1 ppm level.

High voltage holding in the negative ion sources with cesium deposition

Energy Technology Data Exchange (ETDEWEB)

Belchenko, Yu.; Abdrashitov, G.; Ivanov, A.; Sanin, A.; Sotnikov, O., E-mail: O.Z.Sotnikov@inp.nsk.su [Budker Institute of Nuclear Physics, Siberian Branch of Russian Academy of Sciences, Novosibirsk (Russian Federation)

2016-02-15

High voltage holding of the large surface-plasma negative ion source with cesium deposition was studied. It was found that heating of ion-optical system electrodes to temperature >100 °C facilitates the source conditioning by high voltage pulses in vacuum and by beam shots. The procedure of electrode conditioning and the data on high-voltage holding in the negative ion source with small cesium seed are described. The mechanism of high voltage holding improvement by depletion of cesium coverage is discussed.

Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

Science.gov (United States)

Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

2009-03-01

The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

High voltage switches having one or more floating conductor layers

Science.gov (United States)

Werne, Roger W.; Sampayan, Stephen; Harris, John Richardson

2015-11-24

This patent document discloses high voltage switches that include one or more electrically floating conductor layers that are isolated from one another in the dielectric medium between the top and bottom switch electrodes. The presence of the one or more electrically floating conductor layers between the top and bottom switch electrodes allow the dielectric medium between the top and bottom switch electrodes to exhibit a higher breakdown voltage than the breakdown voltage when the one or more electrically floating conductor layers are not present between the top and bottom switch electrodes. This increased breakdown voltage in the presence of one or more electrically floating conductor layers in a dielectric medium enables the switch to supply a higher voltage for various high voltage circuits and electric systems.

HiQ - A high-Q diffractometer for PDF measurements

International Nuclear Information System (INIS)

Brunelli, M.; Fischer, H.E.; Gaehler, R.; Chatterji, T.

2011-01-01

The local structure of many important functional materials is often different from the average structure, as revealed by diffraction, due to, e.g. doping, mixed site occupancy, or formation of time-dependent local distortions. To get information on both the average and the local structures one needs to perform a joint Rietveld and PDF (Pair Distribution Function) analysis of the total scattering, for which we need data to Q = 30 - 35 Angstroms with Δd/d ∼ 3*10 -3 . Here, we describe how the hot-source diffractometer D4 can be adapted to achieve this capability, and outline one possible design of a dedicated high-Q diffractometer at the ILL (Laue Langevin Institute), using the vacant inclined hot-neutron beam IH2. (authors)

Active filter for INDUS-2 Q4 and Q5 power supplies

International Nuclear Information System (INIS)

Singh, Y.P.; Thakurta, A.C.; Kotaiah, S.

2003-01-01

Q4 and Q5 power supplies are SCR based power supplies wherein the rectified voltage is fed to a passive filter to reduce the ripple voltage. The output of the passive filter still contains some ripple particularly on the low frequency side. Attenuation of this ripple with passive filter necessitates increase in size of L and C and leads to sluggishness of the system. The design and the test results of an active filter module have been discussed wherein the low frequency attenuation can be very effectively taken care of by, allowing this to be absorbed in a coupling transformer put after the passive filter. Considerable size reduction has been achieved by using switching techniques. Low frequency attenuation has been made quite a simple task. This filter also helps in handling transients from input. (author)

Beam induced rf cavity transient voltage

International Nuclear Information System (INIS)

Kramer, S.L.; Wang, J.M.

1998-10-01

The authors calculate the transient voltage induced in a radio frequency cavity by the injection of a relativistic bunched beam into a circular accelerator. A simplified model of the beam induced voltage, using a single tone current signal, is generated and compared with the voltage induced by a more realistic model of a point-like bunched beam. The high Q limit of the bunched beam model is shown to be related simply to the simplified model. Both models are shown to induce voltages at the resonant frequency ω r of the cavity and at an integer multiple of the bunch revolution frequency (i.e. the accelerating frequency for powered cavity operation) hω ο . The presence of two nearby frequencies in the cavity leads to a modulation of the carrier wave exp(hω ο t). A special emphasis is placed in this paper on studying the modulation function. These models prove useful for computing the transient voltage induced in superconducting rf cavities, which was the motivation behind this research. The modulation of the transient cavity voltage discussed in this paper is the physical basis of the recently observed and explained new kinds of longitudinal rigid dipole mode which differs from the conventional Robinson mode

A compact, all solid-state LC high voltage generator.

Science.gov (United States)

Fan, Xuliang; Liu, Jinliang

2013-06-01

LC generator is widely applied in the field of high voltage generation technology. A compact and all solid-state LC high voltage generator based on saturable pulse transformer is proposed in this paper. First, working principle of the generator is presented. Theoretical analysis and circuit simulation are used to verify the design of the generator. Experimental studies of the proposed LC generator with two-stage main energy storage capacitors are carried out. And the results show that the proposed LC generator operates as expected. When the isolation inductance is 27 μH, the output voltage is 1.9 times larger than the charging voltage on single capacitor. The multiplication of voltages is achieved. On the condition that the primary energy storage capacitor is charged to 857 V, the output voltage of the generator can reach to 59.5 kV. The step-up ratio is nearly 69. When self breakdown gas gap switch is used as main switch, the rise time of the voltage pulse on load resistor is 8.7 ns. It means that the series-wound inductance in the discharging circuit is very small in this system. This generator can be employed in two different applications.

Recycling potential for low voltage and high voltage high rupturing capacity fuse links.

Science.gov (United States)

Psomopoulos, Constantinos S; Barkas, Dimitrios A; Kaminaris, Stavros D; Ioannidis, George C; Karagiannopoulos, Panagiotis

2017-12-01

Low voltage and high voltage high-rupturing-capacity fuse links are used in LV and HV installations respectively, protecting mainly the LV and HV electricity distribution and transportation networks. The Waste Electrical and Electronic Equipment Directive (2002/96/EC) for "Waste of electrical and electronic equipment" is the main related legislation and as it concerns electrical and electronic equipment, it includes electric fuses. Although, the fuse links consist of recyclable materials, only small scale actions have been implemented for their recycling around Europe. This work presents the possibilities for material recovery from this specialized industrial waste for which there are only limited volume data. Furthermore, in order to present the huge possibilities and environmental benefits, it presents the potential for recycling of HRC fuses used by the Public Power Corporation of Greece, which is the major consumer for the country, but one of the smallest ones in Europe and globally, emphasizing in this way in the issue. According to the obtained results, fuse recycling could contribute to the effort for minimize the impacts on the environment through materials recovery and reduction of the wastes' volume disposed of in landfills. Copyright © 2017 Elsevier Ltd. All rights reserved.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

International Nuclear Information System (INIS)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

1998-01-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

30 CFR 18.53 - High-voltage longwall mining systems.

Science.gov (United States)

2010-07-01

...-starter enclosure, with the exception of a controller on a high-voltage shearer, the disconnect device...) shielding between the primary and secondary windings. The shielding must be connected to equipment ground by... with a disconnect device installed to deenergize all high-voltage power conductors extending from the...

Square-Wave Voltage Injection Algorithm for PMSM Position Sensorless Control With High Robustness to Voltage Errors

DEFF Research Database (Denmark)

Ni, Ronggang; Xu, Dianguo; Blaabjerg, Frede

2017-01-01

relationship with the magnetic field distortion. Position estimation errors caused by higher order harmonic inductances and voltage harmonics generated by the SVPWM are also discussed. Both simulations and experiments are carried out based on a commercial PMSM to verify the superiority of the proposed method......Rotor position estimated with high-frequency (HF) voltage injection methods can be distorted by voltage errors due to inverter nonlinearities, motor resistance, and rotational voltage drops, etc. This paper proposes an improved HF square-wave voltage injection algorithm, which is robust to voltage...... errors without any compensations meanwhile has less fluctuation in the position estimation error. The average position estimation error is investigated based on the analysis of phase harmonic inductances, and deduced in the form of the phase shift of the second-order harmonic inductances to derive its...

30 CFR 75.705-2 - Repairs to energized surface high-voltage lines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Repairs to energized surface high-voltage lines... Repairs to energized surface high-voltage lines. An energized high-voltage surface line may be repaired... on power circuits with a phase-to-phase nominal voltage no greater than 15,000 volts; (3) Such...

Planning aspects of ac extra high voltage lines

Energy Technology Data Exchange (ETDEWEB)

Engelhardt, H

1964-01-01

The technical points arising in any project for application of higher voltages on power grids in Europe are discussed. The cost aspects of two alternative ways of extending the voltage level of existing systems are discussed in detail. The short-circuit current in a high-power system with isolated or grounded neutral point and its relation to the mode of grounding is examined. For a transmission distance of 200 kVm, operating cost for each kWh transmitted are shown on curves for voltages of 220, 380 and 700 kV against transmitted energy. This shows that for any rated voltage there is a range of energy values which can be transmitted economically. Factors to be considered in maintaining, selecting or rejecting transformers and switchgear of other systems for higher voltage purposes are mentioned.

Insulation co-ordination in high-voltage electric power systems

CERN Document Server

Diesendorf, W

2015-01-01

Insulation Co-ordination in High-Voltage Electric Power Systems deals with the methods of insulation needed in different circumstances. The book covers topics such as overvoltages and lightning surges; disruptive discharge and withstand voltages; self-restoring and non-self-restoring insulation; lightning overvoltages on transmission lines; and the attenuation and distortion of lightning surges. Also covered in the book are topics such as the switching surge designs of transmission lines, as well as the insulation coordination of high-voltage stations. The text is recommended for electrical en

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

Directory of Open Access Journals (Sweden)

Bo Xie

2015-09-01

Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

Optimized expression and purification of NavAb provide the structural insight into the voltage dependence.

Science.gov (United States)

Irie, Katsumasa; Haga, Yukari; Shimomura, Takushi; Fujiyoshi, Yoshinori

2018-01-01

Voltage-gated sodium channels are crucial for electro-signalling in living systems. Analysis of the molecular mechanism requires both fine electrophysiological evaluation and high-resolution channel structures. Here, we optimized a dual expression system of NavAb, which is a well-established standard of prokaryotic voltage-gated sodium channels, for E. coli and insect cells using a single plasmid vector to analyse high-resolution protein structures and measure large ionic currents. Using this expression system, we evaluated the voltage dependence and determined the crystal structures of NavAb wild-type and two mutants, E32Q and N49K, whose voltage dependence were positively shifted and essential interactions were lost in voltage sensor domain. The structural and functional comparison elucidated the molecular mechanisms of the voltage dependence of prokaryotic voltage-gated sodium channels. © 2017 Federation of European Biochemical Societies.

A high-order q-difference equation for q-Hahn multiple orthogonal polynomials

DEFF Research Database (Denmark)

Arvesú, J.; Esposito, Chiara

2012-01-01

A high-order linear q-difference equation with polynomial coefficients having q-Hahn multiple orthogonal polynomials as eigenfunctions is given. The order of the equation coincides with the number of orthogonality conditions that these polynomials satisfy. Some limiting situations when are studie....... Indeed, the difference equation for Hahn multiple orthogonal polynomials given in Lee [J. Approx. Theory (2007), ), doi: 10.1016/j.jat.2007.06.002] is obtained as a limiting case....

Analysis of transistor and snubber turn-off dynamics in high-frequency high-voltage high-power converters

Science.gov (United States)

Wilson, P. M.; Wilson, T. G.; Owen, H. A., Jr.

Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.

High Input Voltage, Silicon Carbide Power Processing Unit Performance Demonstration

Science.gov (United States)

Bozak, Karin E.; Pinero, Luis R.; Scheidegger, Robert J.; Aulisio, Michael V.; Gonzalez, Marcelo C.; Birchenough, Arthur G.

2015-01-01

A silicon carbide brassboard power processing unit has been developed by the NASA Glenn Research Center in Cleveland, Ohio. The power processing unit operates from two sources: a nominal 300 Volt high voltage input bus and a nominal 28 Volt low voltage input bus. The design of the power processing unit includes four low voltage, low power auxiliary supplies, and two parallel 7.5 kilowatt (kW) discharge power supplies that are capable of providing up to 15 kilowatts of total power at 300 to 500 Volts (V) to the thruster. Additionally, the unit contains a housekeeping supply, high voltage input filter, low voltage input filter, and master control board, such that the complete brassboard unit is capable of operating a 12.5 kilowatt Hall effect thruster. The performance of the unit was characterized under both ambient and thermal vacuum test conditions, and the results demonstrate exceptional performance with full power efficiencies exceeding 97%. The unit was also tested with a 12.5kW Hall effect thruster to verify compatibility and output filter specifications. With space-qualified silicon carbide or similar high voltage, high efficiency power devices, this would provide a design solution to address the need for high power electric propulsion systems.

A low knee voltage and high breakdown voltage of 4H-SiC TSBS employing poly-Si/Ni Schottky scheme

Science.gov (United States)

Kim, Dong Young; Seok, Ogyun; Park, Himchan; Bahng, Wook; Kim, Hyoung Woo; Park, Ki Cheol

2018-02-01

We report a low knee voltage and high breakdown voltage 4H-SiC TSBS employing poly-Si/Ni dual Schottky contacts. A knee voltage was significantly improved from 0.75 to 0.48 V by utilizing an alternative low work-function material of poly-Si as an anode electrode. Also, reverse breakdown voltage was successfully improved from 901 to 1154 V due to a shrunk low-work-function Schottky region by a proposed self-align etching process between poly-Si and SiC. SiC TSBS with poly-Si/Ni dual Schottky scheme is a suitable structure for high-efficiency rectification and high-voltage blocking operation.

Application of high voltage electric field (HVEF) drying technology in potato chips

International Nuclear Information System (INIS)

Bai, Yaxiang; Shi, Hua; Yang, Yaxin

2013-01-01

In order to improve the drying efficiency and qualities of vegetable by high voltage electric field (HVEF), potato chips as a representative of vegetable was dried using a high voltage electric drying systems at 20°C. The shrinkage rate, water absorption and rehydration ratio of dried potato chips were measured. The results indicated that the drying rate of potato chips was significantly improved in the high voltage electric drying systems. The shrinkage rate of potato chips dried by high voltage electric field was 1.1% lower than that by oven drying method. And the rehydration rate of high voltage electric field was 24.6% higher than that by oven drying method. High voltage electric field drying is very advantageous and can be used as a substitute for traditional drying method.

X-ray spectral meter of high voltages for X-ray apparatuses

International Nuclear Information System (INIS)

Zubkov, I.P.; Larchikov, Yu.V.

1993-01-01

Design of the X-ray spectral meter of high voltages (XRSMHV) for medical X-ray apparatuses permitting to conduct the voltage measurements without connection to current circuits. The XRSMHV consists of two main units: the detector unit based on semiconductor detector and the LP4900B multichannel analyzer (Afora, Finland). The XRSMYV was tested using the pilot plant based on RUM-20 X-ray diagnostic apparatus with high-voltage regulator. It was shown that the developed XRSMHV could be certify in the range of high constant voltages form 40 up to 120 kV with the basic relative error limits ±0.15%. The XRSMHV is used at present as the reference means for calibration of high-voltage medical X-ray equipment

Symmetry-Breaking Charge Transfer in a Zinc Chlorodipyrrin Acceptor for High Open Circuit Voltage Organic Photovoltaics

KAUST Repository

Bartynski, Andrew N.

2015-04-29

© 2015 American Chemical Society. Low open-circuit voltages significantly limit the power conversion efficiency of organic photovoltaic devices. Typical strategies to enhance the open-circuit voltage involve tuning the HOMO and LUMO positions of the donor (D) and acceptor (A), respectively, to increase the interfacial energy gap or to tailor the donor or acceptor structure at the D/A interface. Here, we present an alternative approach to improve the open-circuit voltage through the use of a zinc chlorodipyrrin, ZCl [bis(dodecachloro-5-mesityldipyrrinato)zinc], as an acceptor, which undergoes symmetry-breaking charge transfer (CT) at the donor/acceptor interface. DBP/ZCl cells exhibit open-circuit voltages of 1.33 V compared to 0.88 V for analogous tetraphenyldibenzoperyflanthrene (DBP)/C60-based devices. Charge transfer state energies measured by Fourier-transform photocurrent spectroscopy and electroluminescence show that C60 forms a CT state of 1.45 ± 0.05 eV in a DBP/C60-based organic photovoltaic device, while ZCl as acceptor gives a CT state energy of 1.70 ± 0.05 eV in the corresponding device structure. In the ZCl device this results in an energetic loss between ECT and qVOC of 0.37 eV, substantially less than the 0.6 eV typically observed for organic systems and equal to the recombination losses seen in high-efficiency Si and GaAs devices. The substantial increase in open-circuit voltage and reduction in recombination losses for devices utilizing ZCl demonstrate the great promise of symmetry-breaking charge transfer in organic photovoltaic devices.

An implantable neurostimulator with an integrated high-voltage inductive power-recovery frontend

International Nuclear Information System (INIS)

Wang Yuan; Zhang Xu; Liu Ming; Li Peng; Chen Hongda

2014-01-01

This paper present a highly-integrated neurostimulator with an on-chip inductive power-recovery frontend and high-voltage stimulus generator. In particular, the power-recovery frontend includes a high-voltage full-wave rectifier (up to 100 V AC input), high-voltage series regulators (24/5 V outputs) and a linear regulator (1.8/3.3 V output) with bandgap voltage reference. With the high voltage output of the series regulator, the proposed neurostimulator could deliver a considerably large current in high electrode-tissue contact impedance. This neurostimulator has been fabricated in a CSMC 1 μm 5/40/700 V BCD process and the total silicon area including pads is 5.8 mm 2 . Preliminary tests are successful as the neurostimulator shows good stability under a 13.56 MHz AC supply. Compared to previously reported works, our design has advantages of a wide induced voltage range (26–100 V), high output voltage (up to 24 V) and high-level integration, which are suitable for implantable neurostimulators. (semiconductor integrated circuits)

High voltage diagnostics on electrical insulation of supersonducting magnets

International Nuclear Information System (INIS)

Irmisch, M.

1995-12-01

The high voltage (HV) performance of superconducting magnets of large dimensions, e.g. as needed in fusion reactors, is a challange in the field of high voltage technology, i.e. especially in the field of cryogenic high voltage components and with respect to questions of HV insulation diagnostics at low temperature. By using the development of POLO - a superconducting prototype coil of a tokamak poloidal field coil - as an example, this work deals with special problems of how to get use of conventional HV test techniques for diagnostics under special cryogenic boundary conditions. As a first approach to gain experience in the field of phase resolved partial discharge (PRPD) measurements during operation of a superconductive coil, the POLO coil was subject to several high voltage tests. Compared with DC insulation resistance measurements and capacitive impulse voltage discharges to the coil, the AC PD measurements have been the only way to observe special characteristics of the electrical insulation with respect to the cooling down of the coil from 300 K to 4.2 K. The PRPD measurement technique thereby has proofed as a suitable diagnostic tool. This work can serve as basic data to be comparable within further projects of electrical insulation diagnostics at cryogenic temperatures. (orig.)

Precision High-Voltage DC Dividers and Their Calibration

Czech Academy of Sciences Publication Activity Database

Dragounová, Naděžda

2005-01-01

Roč. 54, č. 5 (2005), s. 1911-1915 ISSN 0018-9456 R&D Projects: GA AV ČR KSK1048102; GA ČR GA202/03/0889 Keywords : calibration * dc voltage * high voltage (HV) Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering Impact factor: 0.665, year: 2005

High Q-factor tunable superconducting HF circuit

CERN Document Server

Vopilkin, E A; Pavlov, S A; Ponomarev, L I; Ganitsev, A Y; Zhukov, A S; Vladimirov, V V; Letyago, A G; Parshikov, V V

2001-01-01

Feasibility of constructing a high Q-factor (Q approx 10 sup 5) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz

High Q-factor tunable superconducting HF circuit

International Nuclear Information System (INIS)

Vopilkin, E.A.; Parafin, A.E.; Pavlov, S.A.; Ponomarev, L.I.; Ganitsev, A.Yu.; Zhukov, A.S.; Vladimirov, V.V.; Letyago, A.G.; Parshikov, V.V.

2001-01-01

Feasibility of constructing a high Q-factor (Q ∼ 10 5 ) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz [ru

Process engineering of high voltage alginate encapsulation of mesenchymal stem cells

International Nuclear Information System (INIS)

Gryshkov, Oleksandr; Pogozhykh, Denys; Zernetsch, Holger; Hofmann, Nicola; Mueller, Thomas; Glasmacher, Birgit

2014-01-01

Encapsulation of stem cells in alginate beads is promising as a sophisticated drug delivery system in treatment of a wide range of acute and chronic diseases. However, common use of air flow encapsulation of cells in alginate beads fails to produce beads with narrow size distribution, intact spherical structure and controllable sizes that can be scaled up. Here we show that high voltage encapsulation (≥ 15 kV) can be used to reproducibly generate spherical alginate beads (200–400 μm) with narrow size distribution (± 5–7%) in a controlled manner under optimized process parameters. Flow rate of alginate solution ranged from 0.5 to 10 ml/h allowed producing alginate beads with a size of 320 and 350 μm respectively, suggesting that this approach can be scaled up. Moreover, we found that applied voltages (15–25 kV) did not alter the viability and proliferation of encapsulated mesenchymal stem cells post-encapsulation and cryopreservation as compared to air flow. We are the first who employed a comparative analysis of electro-spraying and air flow encapsulation to study the effect of high voltage on alginate encapsulated cells. This report provides background in application of high voltage to encapsulate living cells for further medical purposes. Long-term comparison and work on alginate–cell interaction within these structures will be forthcoming. - Highlights: • High voltage alginate encapsulation of mesenchymal stem cells (MSCs) was designed. • Reproducible and spherical alginate beads were generated via high voltage. • Air flow encapsulation was utilized as a comparative approach to high voltage. • High voltage did not alter the viability and proliferation of encapsulated MSCs. • High voltage encapsulation can be scaled up and applied in cell-based therapy

High voltage power network construction

CERN Document Server

Harker, Keith

2018-01-01

This book examines the key requirements, considerations, complexities and constraints relevant to the task of high voltage power network construction, from design, finance, contracts and project management to installation and commissioning, with the aim of providing an overview of the holistic end to end construction task in a single volume.

High Bandwidth Zero Voltage Injection Method for Sensorless Control of PMSM

DEFF Research Database (Denmark)

Ge, Xie; Lu, Kaiyuan; Kumar, Dwivedi Sanjeet

2014-01-01

High frequency signal injection is widely used in PMSM sensorless control system for low speed operations. The conventional voltage injection method often needs filters to obtain particular harmonic component in order to estimate the rotor position; or it requires several voltage pulses to be inj......High frequency signal injection is widely used in PMSM sensorless control system for low speed operations. The conventional voltage injection method often needs filters to obtain particular harmonic component in order to estimate the rotor position; or it requires several voltage pulses...... in a fast current regulation performance. Injection of zero voltage also minimizes the inverter voltage error effects caused by the dead-time....

Characteristics and Breakdown Behaviors of Polysilicon Resistors for High Voltage Applications

Directory of Open Access Journals (Sweden)

Xiao-Yu Tang

2015-01-01

Full Text Available With the rapid development of the power integrated circuit technology, polysilicon resistors have been widely used not only in traditional CMOS circuits, but also in the high voltage applications. However, there have been few detailed reports about the polysilicon resistors’ characteristics, like voltage and temperature coefficients and breakdown behaviors which are critical parameters of high voltage applications. In this study, we experimentally find that the resistance of the polysilicon resistor with a relatively low doping concentration shows negative voltage and temperature coefficients, while that of the polysilicon resistor with a high doping concentration has positive voltage and temperature coefficients. Moreover, from the experimental results of breakdown voltages of the polysilicon resistors, it could be deduced that the breakdown of polysilicon resistors is thermally rather than electrically induced. We also proposed to add an N-type well underneath the oxide to increase the breakdown voltage in the vertical direction when the substrate is P-type doped.

Generation and confinement of mobile charges in buried oxide of SOI substrates

International Nuclear Information System (INIS)

Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A.

1999-01-01

We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO 2 interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

30 CFR 75.802 - Protection of high-voltage circuits extending underground.

Science.gov (United States)

2010-07-01

...-Voltage Distribution § 75.802 Protection of high-voltage circuits extending underground. (a) Except as... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Protection of high-voltage circuits extending... which shall be grounded through a suitable resistor at the source transformers, and a grounding circuit...

Development of high voltage PEEK wire with radiation-resistance and cryogenic characteristics

International Nuclear Information System (INIS)

Fujita, T.; Hirata, T.; Araki, S.; Ohara, H.; Nishimura, H.

1989-01-01

High voltage electric wires insulated with highly-refined polyetheretherketone (PEEK) have been developed for the wiring in fusion reactors, where the wire is required to withstand high voltage under high vacuum up to 10 -5 Torr. The PEEK wires having the advantages of PEEK resin including superior radiation resistance and cryogenic characteristics are usable over a wide range of temperature and in radiation fields. The results of withstand voltage tests proved that the PEEK wires exceeding 0.8 mm in insulation thickness withstand such specified high voltage conditions as 24 kV for 1 minutes by 10 times and 6.6 kV for 110 hours. The results also revealed that the withstand voltage is improved by providing a jacket layer over the insulation and decreased by periodical voltage charge, by bending of the specimen and by water in the conductor. This paper deal with the withstand voltage test results under varied conditions of the PEEK wires. (author)

Copper wire theft and high voltage electrical burns

OpenAIRE

Francis, Eamon C; Shelley, Odhran P

2014-01-01

High voltage electrical burns are uncommon. However in the midst of our economic recession we are noticing an increasing number of these injuries. Copper wire is a valuable commodity with physical properties as an excellent conductor of electricity making it both ubiquitous in society and prized on the black market. We present two consecutive cases referred to the National Burns Unit who sustained life threatening injuries from the alleged theft of high voltage copper wire and its omnipresenc...

Compact high voltage, high peak power, high frequency transformer for converter type modulator applications.

Science.gov (United States)

Reghu, T; Mandloi, V; Shrivastava, Purushottam

2016-04-01

The design and development of a compact high voltage, high peak power, high frequency transformer for a converter type modulator of klystron amplifiers is presented. The transformer has been designed to operate at a frequency of 20 kHz and at a flux swing of ±0.6 T. Iron (Fe) based nanocrystalline material has been selected as a core for the construction of the transformer. The transformer employs a specially designed solid Teflon bobbin having 120 kV insulation for winding the high voltage secondary windings. The flux swing of the core has been experimentally found by plotting the hysteresis loop at actual operating conditions. Based on the design, a prototype transformer has been built which is per se a unique combination of high voltage, high frequency, and peak power specifications. The transformer was able to provide 58 kV (pk-pk) at the secondary with a peak power handling capability of 700 kVA. The transformation ratio was 1:17. The performance of the transformer is also presented and discussed.

Jean-Pierre Famose et Jean Bertsch, L’estime de soi : une controverse éducative, Paris, PUF, 2009, 192 p

OpenAIRE

Benamar, Aïcha

2015-01-01

L’ouvrage porte sur l’estime de soi, dans la sphère sociale en général et le monde éducatif en particulier. L’estime de soi est au cœur du comportement individuel, apportant confiance et assurance, permettant de progresser et in fine de réussir. Une faible estime de soi est fréquemment à l’origine de difficultés pour un individu : doutes, hésitations, ou à l’inverse vanité et arrogance. Un bon niveau d’estime de soi confère à la personnalité : capacité à s’affirmer et respect des autres. Cent...

An Integrated Chip High-Voltage Power Receiver for Wireless Biomedical Implants

Directory of Open Access Journals (Sweden)

Vijith Vijayakumaran Nair

2015-06-01

Full Text Available In near-field wireless-powered biomedical implants, the receiver voltage largely overrides the compliance of low-voltage power receiver systems. To limit the induced voltage, generally, low-voltage topologies utilize limiter circuits, voltage clippers or shunt regulators, which are power-inefficient methods. In order to overcome the voltage limitation and improve power efficiency, we propose an integrated chip high-voltage power receiver based on the step down approach. The topology accommodates voltages as high as 30 V and comprises a high-voltage semi-active rectifier, a voltage reference generator and a series regulator. Further, a battery management circuit that enables safe and reliable implant battery charging based on analog control is proposed and realized. The power receiver is fabricated in 0.35-μm high-voltage Bipolar-CMOS-DMOStechnology based on the LOCOS0.35-μm CMOS process. Measurement results indicate 83.5% power conversion efficiency for a rectifier at 2.1 mA load current. The low drop-out regulator based on the current buffer compensation and buffer impedance attenuation scheme operates with low quiescent current, reduces the power consumption and provides good stability. The topology also provides good power supply rejection, which is adequate for the design application. Measurement results indicate regulator output of 4 ± 0.03 V for input from 5 to 30 V and 10 ± 0.05 V output for input from 11 to 30 V with load current 0.01–100 mA. The charger circuit manages the charging of the Li-ion battery through all if the typical stages of the Li-ion battery charging profile.

Design and development of high voltage and high frequency center tapped transformer for HVDC test generator

International Nuclear Information System (INIS)

Thaker, Urmil; Saurabh Kumar; Amal, S.; Baruah, U.K.; Bhatt, Animesh

2015-01-01

A High Voltage center tapped transformer for high frequency application had been designed, fabricated, and tested. It was designed as a part of 200 kV HVDC Test Generator. The High Frequency operation of transformer increases power density. Therefore it is possible to reduce power supply volume. The step up ratio in High Voltage transformer is limited due to stray capacitance and leakage inductance. The limit was overcome by winding multi secondary outputs. Switching frequency of transformer was 15.8 kHz. Input and output voltages of transformer were 270V and 16.5kV-0V-16.5kV respectively. Power rating of transformer is 7kVA. High Voltage transformer with various winding and core arrangement was fabricated to check variation in electrical characteristics. The transformer used a ferrite core (E Type) and nylon insulated primary and secondary bobbins. Two set of E-E geometry cores had been stacked in order to achieve the estimated core volume. Compared with traditional high voltage transformer, this transformer had good thermal behavior, good line insulation properties and a high power density. In this poster, design procedures, development stages and test results of high voltage and high frequency transformer are presented. Results of various parameters such as transformer loss, temperature rise, insulation properties, impedance of primary and secondary winding, and voltage regulation are discussed. (author)

Innovation of High Voltage Supply Adjustment Device on Diagnostic X-Ray Machine

International Nuclear Information System (INIS)

Sujatno; Wiranto Budi Santoso

2010-01-01

Innovation of high voltage supply adjustment device on diagnostic x-ray machine has been carried out. The innovation is conducted by utilizing an electronic circuit as a high voltage adjustment device. Usually a diagnostic x-ray machine utilizes a transformer or an auto-transformer as a high voltage supply adjustment device. A high power diagnostic x-ray machine needs a high power transformer which has big physical dimension. Therefore a box control where the transformer is located has to have big physical dimension. Besides, the price of the transformer is expensive and hardly found in local markets. In this innovation, the transformer is replaced by an electronic circuit. The main component of the electronic circuit is Triac BTA-40. As adjustment device, the triac is controlled by a variable resistor which is coupled by a stepper motor. A step movement of stepper motor varies a value of resistor. The resistor value determines the triac gate voltage. Furthermore the triac will open according to the value of electrical current flowing to the gate. When the gate is open, electrical voltage and current will flow from cathode to anode of the triac. The value of these electrical voltage and current depend on gate open condition. Then this triac output voltage is feed to diagnostic x-ray machine high voltage supply. Therefore the high voltage value of diagnostic x-ray machine is adjusted by the output voltage of the electronic circuit. By using this electronic circuit, the physical dimension of diagnostic x-ray machine box control and the price of the equipment can be reduced. (author)

High rates of de novo 15q11q13 inversions in human spermatozoa

Directory of Open Access Journals (Sweden)

Molina Òscar

2012-02-01

Full Text Available Abstract Low-Copy Repeats predispose the 15q11-q13 region to non-allelic homologous recombination. We have already demonstrated that a significant percentage of Prader-Willi syndrome (PWS fathers have an increased susceptibility to generate 15q11q13 deletions in spermatozoa, suggesting the participation of intrachromatid exchanges. This work has been focused on assessing the incidence of de novo 15q11q13 inversions in spermatozoa of control donors and PWS fathers in order to determine the basal rates of inversions and to confirm the intrachromatid mechanism as the main cause of 15q11q13 anomalies. Semen samples from 10 control donors and 16 PWS fathers were processed and analyzed by triple-color FISH. Three differentially labeled BAC-clones were used: one proximal and two distal of the 15q11-q13 region. Signal associations allowed the discrimination between normal and inverted haplotypes, which were confirmed by laser-scanning confocal microscopy. Two types of inversions were detected which correspond to the segments involved in Class I and II PWS deletions. No significant differences were observed in the mean frequencies of inversions between controls and PWS fathers (3.59% ± 0.46 and 9.51% ± 0.87 vs 3.06% ± 0.33 and 10.07% ± 0.74. Individual comparisons showed significant increases of inversions in four PWS fathers (P Results suggest that the incidence of heterozygous inversion carriers in the general population could reach significant values. This situation could have important implications, as they have been described as predisposing haplotypes for genomic disorders. As a whole, results confirm the high instability of the 15q11-q13 region, which is prone to different types of de novo reorganizations by intrachromatid NAHR.

A Four-Phase High Voltage Conversion Ratio Bidirectional DC-DC Converter for Battery Applications

Directory of Open Access Journals (Sweden)

Li-Kun Xue

2015-06-01

Full Text Available This study presents a four-phase interleaved high voltage conversion ratio bidirectional DC-DC converter circuit based on coupled inductors and switched capacitors, which can eliminate the defects of conventional high voltage conversion ratio bidirectional DC-DC converters in terms of high-voltage/current stress, less efficiency and low-power limitation. Parallel channels are used to reduce current stress at the low-voltage side and series connected switched capacitors are used to enlarge voltage conversion ratio, reduce voltage stress and achieve auto current sharing. This paper proposes the operation principle, feature analysis and optimization design considerations. On this basis the objectives of high voltage conversion ratio, low voltage/current stress, high power density, high efficiency and high-power applications can be achieved. Some experimental results based on a 500 W prototype converter (24 V to 48 V at low-voltage side, 400 V at high-voltage side are given to verify the theoretical analysis and the effectiveness of the proposed converter.

Advanced High Voltage Power Device Concepts

CERN Document Server

Baliga, B Jayant

2012-01-01

Advanced High Voltage Power Device Concepts describes devices utilized in power transmission and distribution equipment, and for very high power motor control in electric trains and steel-mills. Since these devices must be capable of supporting more than 5000-volts in the blocking mode, this books covers operation of devices rated at 5,000-V, 10,000-V and 20,000-V. Advanced concepts (the MCT, the BRT, and the EST) that enable MOS-gated control of power thyristor structures are described and analyzed in detail. In addition, detailed analyses of the silicon IGBT, as well as the silicon carbide MOSFET and IGBT, are provided for comparison purposes. Throughout the book, analytical models are generated to give a better understanding of the physics of operation for all the structures. This book provides readers with: The first comprehensive treatment of high voltage (over 5000-volts) power devices suitable for the power distribution, traction, and motor-control markets;  Analytical formulations for all the device ...

Reactive power and voltage control strategy based on dynamic and adaptive segment for DG inverter

Science.gov (United States)

Zhai, Jianwei; Lin, Xiaoming; Zhang, Yongjun

2018-03-01

The inverter of distributed generation (DG) can support reactive power to help solve the problem of out-of-limit voltage in active distribution network (ADN). Therefore, a reactive voltage control strategy based on dynamic and adaptive segment for DG inverter is put forward to actively control voltage in this paper. The proposed strategy adjusts the segmented voltage threshold of Q(U) droop curve dynamically and adaptively according to the voltage of grid-connected point and the power direction of adjacent downstream line. And then the reactive power reference of DG inverter can be got through modified Q(U) control strategy. The reactive power of inverter is controlled to trace the reference value. The proposed control strategy can not only control the local voltage of grid-connected point but also help to maintain voltage within qualified range considering the terminal voltage of distribution feeder and the reactive support for adjacent downstream DG. The scheme using the proposed strategy is compared with the scheme without the reactive support of DG inverter and the scheme using the Q(U) control strategy with constant segmented voltage threshold. The simulation results suggest that the proposed method has a significant improvement on solving the problem of out-of-limit voltage, restraining voltage variation and improving voltage quality.

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

Copper wire theft and high voltage electrical burns.

Science.gov (United States)

Francis, Eamon C; Shelley, Odhran P

2014-01-01

High voltage electrical burns are uncommon. However in the midst of our economic recession we are noticing an increasing number of these injuries. Copper wire is a valuable commodity with physical properties as an excellent conductor of electricity making it both ubiquitous in society and prized on the black market. We present two consecutive cases referred to the National Burns Unit who sustained life threatening injuries from the alleged theft of high voltage copper wire and its omnipresence on an international scale.

MOSFET-based high voltage short pulse generator for ultrasonic transducer excitation

Science.gov (United States)

Hidayat, Darmawan; Setianto, Syafei, Nendi Suhendi; Wibawa, Bambang Mukti

2018-02-01

This paper presents the generation of a high-voltage short pulse for the excitation of high frequency ultrasonic transducers. This is highly required in the purpose of various ultrasonic-based evaluations, particularly when high resolution measurement is necessary. A high voltage (+760 V) DC voltage source was pulsated by an ultrafast switching MOSFET which was driven by a pulse generator circuit consisting of an astable multivibrator, a one-shot multivibrator with Schmitt trigger input and a high current MOSFET driver. The generated pulses excited a 200-kHz and a 1-MHz ultrasonic transducers and tested in the transmission mode propagation to evaluate the performances of the generated pulse. The test results showed the generator were able to produce negative spike pulses up to -760 V voltage with the shortest time-width of 107.1 nanosecond. The transmission-received ultrasonic waves show frequency oscillation at 200 and 961 kHz and their amplitudes varied with the voltage of excitation pulse. These results conclude that the developed pulse generator is applicable to excite transducer for the generation of high frequency ultrasonic waves.

Temperature Stabilized Characterization of High Voltage Power Supplies

CERN Document Server

Krarup, Ole

2017-01-01

High precision measurements of the masses of nuclear ions in the ISOLTRAP experiment relies on an MR-ToF. A major source of noise and drift is the instability of the high voltage power supplies employed. Electrical noise and temperature changes can broaden peaks in time-of-flight spectra and shift the position of peaks between runs. In this report we investigate how the noise and drift of high-voltage power supplies can be characterized. Results indicate that analog power supplies generally have better relative stability than digitally controlled ones, and that the high temperature coefficients of all power supplies merit efforts to stabilize them.

A High Voltage Swing 1.9 GHz PA in Standard CMOS

NARCIS (Netherlands)

Aartsen, W.A.J.; Annema, Anne J.; Nauta, Bram

2002-01-01

A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nominal supply voltage is presented. To achieve this high-voltage tolerance the circuit implements switched-cascode transistors that yield reliable operation for voltages up to 7V at RF frequencies in a

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca

2015-09-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

2015-01-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

High voltage series protection of neutral injectors with crossed-field tubes

International Nuclear Information System (INIS)

Hofmann, G.A.; Thomas, D.G.

1976-01-01

High voltage neutral beam injectors for fusion machines require either parallel or series protection schemes to limit fault currents in case of arcing to safe levels. The protection device is usually located between the high voltage supply and beam injector and either crowbars (parallel protection) or disconnects (series protection) the high voltage supply when a fault occurs. Because of its isolating property, series protection is preferred. The Hughes crossed-field tube is uniquely suited for series protection schemes. The tube can conduct 40 A continuously upon application of voltage (approximately 300 V) and a static magnetic field (approximately 100 G). It is also capable of interrupting currents of 1000 A within 10 μs and withstand voltage of more than 120 kV. Experiments were performed to simulate the duty of a crossed-field tube as a series protection element in a neutral injector circuit under fault conditions. Results of on-switching tests under high and low voltage and interruption of fault currents are presented. An example of a possible protection circuit with crossed-field tubes is discussed

High-voltage pixel sensors for ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Perić, I., E-mail: ivan.peric@ziti.uni-heidelberg.de [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Kreidl, C.; Fischer, P. [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M. [CPPM, Marseille (France); Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B. [CERN, Geneve (Switzerland); Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A. [University of Geneve (Switzerland); and others

2014-11-21

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

High mechanical Q-factor measurements on silicon bulk material

Energy Technology Data Exchange (ETDEWEB)

Schwarz, Christian; Nawrodt, Ronny; Heinert, Daniel; Schroeter, Anja; Neubert, Ralf; Thuerk, Matthias; Vodel, Wolfgang; Seidel, Paul [Institut fuer Festkoerperphysik, Helmholtzweg 5, D-07743 Jena (Germany); Tuennermann, Andreas [Institut fuer Angewandte Physik, Albert-Einstein-Strasse 15, D-07745 Jena (Germany)

2008-07-01

The direct observation of gravitational waves is one of the biggest challenges in science. Current detectors are limited by different kinds of noise. One of the fundamental noise sources is thermal noise arising from the optical components. One of the most promising attempts to reduce the thermal noise contribution in future detectors will be the use of high Q-factor materials at cryogenic temperatures. Silicon seems to be the most interesting material due to its excellent optical and thermal properties. We present high Q-factor measurements on bulk samples of high purity silicon in a temperature range from 5 to 300 K. The sample dimensions vary between 76.2 mm x 12..75 mm. The Q-factor exceeds 4.10{sup 8} at 6 K. The influence of the crystal orientation, doping and the sample preparation on the Q-factor is discussed.

Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

Science.gov (United States)

Dogan, Numan S.

2003-01-01

The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

High-voltage short-fall pulse generator

International Nuclear Information System (INIS)

Dolbilov, G.V.; Fateev, A.A.; Petrov, V.A.

1986-01-01

Powerful high-voltage pulses with short fall times and relatively low afterpulse amplitude are required for the deflection systems of accelerators. A generator is described that provides, into a 75-ohm load, a voltage pulse of up to 100 kV with a fall time of less than 1 nsec and a relative afterpulse amplitude of less than or equal to 15%. The generator employs a short-circuited ferrite-filled line in which shock waves are formed. A magnetic section is used to increase power. The switch is a TGI1-2500/50 thyratron. The main causes of afterpulses and methods for reducing their amplitude are examined

Copper wire theft and high voltage electrical burns

Science.gov (United States)

Francis, Eamon C; Shelley, Odhran P

2014-01-01

High voltage electrical burns are uncommon. However in the midst of our economic recession we are noticing an increasing number of these injuries. Copper wire is a valuable commodity with physical properties as an excellent conductor of electricity making it both ubiquitous in society and prized on the black market. We present two consecutive cases referred to the National Burns Unit who sustained life threatening injuries from the alleged theft of high voltage copper wire and its omnipresence on an international scale. PMID:25356371

Microparticles in high-voltage accelerator tubes

International Nuclear Information System (INIS)

Griffith, G.L.; Eastham, D.A.

1979-01-01

Microparticles with radii greater than 2 μm have been observed in a high voltage vacuum accelerator tube. The charge acquired by most of the particles is similar to the contact charging of a conducting sphere on a plane. (author)

High voltage and high specific capacity dual intercalating electrode Li-ion batteries

Science.gov (United States)

West, William C. (Inventor); Blanco, Mario (Inventor)

2010-01-01

The present invention provides high capacity and high voltage Li-ion batteries that have a carbonaceous cathode and a nonaqueous electrolyte solution comprising LiF salt and an anion receptor that binds the fluoride ion. The batteries can comprise dual intercalating electrode Li ion batteries. Methods of the present invention use a cathode and electrode pair, wherein each of the electrodes reversibly intercalate ions provided by a LiF salt to make a high voltage and high specific capacity dual intercalating electrode Li-ion battery. The present methods and systems provide high-capacity batteries particularly useful in powering devices where minimizing battery mass is important.

An inverted-geometry, high voltage polarized electron gun with UHV load lock

International Nuclear Information System (INIS)

Breidenbach, M.; Foss, M.; Hodgson, J.; Kulikov, A.; Odian, A.; Putallaz, G.; Rogers, H.; Schindler, R.; Skarpaas, K.; Zolotorev, M.

1994-01-01

The design of a high voltage electron source with a GaAs photocathode and a load lock system is described. The inverted high voltage structure of the gun permits a compact and simple design. Test results demonstrate that the load lock system provides a reliable way to achieve high quantum efficiency of the photocathode in a high voltage device. ((orig.))

Integrated reconfigurable high-voltage transmitting circuit for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

2015-01-01

In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

The research of high voltage switchgear detecting unit

Science.gov (United States)

Ji, Tong; Xie, Wei; Wang, Xiaoqing; Zhang, Jinbo

2017-07-01

In order to understand the status of the high voltage switch in the whole life circle, you must monitor the mechanical and electrical parameters that affect device health. So this paper gives a new high voltage switchgear detecting unit based on ARM technology. It can measure closing-opening mechanical wave, storage motor current wave and contactor temperature to judge the device’s health status. When something goes wrong, it can be on alert and give some advice. The practice showed that it can meet the requirements of circuit breaker mechanical properties temperature online detection.

High-voltage direct-current circuit breakers

International Nuclear Information System (INIS)

Yoshioka, Y.; Hirasawa, K.

1991-01-01

This paper reports that in 1954 the first high-voltage direct-current (HVDC) transmission system was put into operation between Gotland and the mainland of Sweden. Its system voltage and capacity were 100 kV and 20 MW, respectively. Since then many HVDC transmission systems have been planned, constructed, or commissioned in more than 30 places worldwide, and their total capacity is close to 40 GW. Most systems commissioned to date are two-terminal schemes, and HVDC breakers are not yet used in the high-potential main circuit of those systems, because the system is expected to perform well using only converter/inverter control even at a fault stage of the transmission line. However, even in a two-terminal scheme there are not a few merits in using an HVDC breaker when the system has two parallel transmission lines, that is, when it is a double-circuit system

Statistical characteristics of transient enclosure voltage in ultra-high-voltage gas-insulated switchgear

Science.gov (United States)

Cai, Yuanji; Guan, Yonggang; Liu, Weidong

2017-06-01

Transient enclosure voltage (TEV), which is a phenomenon induced by the inner dielectric breakdown of SF6 during disconnector operations in a gas-insulated switchgear (GIS), may cause issues relating to shock hazard and electromagnetic interference to secondary equipment. This is a critical factor regarding the electromagnetic compatibility of ultra-high-voltage (UHV) substations. In this paper, the statistical characteristics of TEV at UHV level are collected from field experiments, and are analyzed and compared to those from a repeated strike process. The TEV waveforms during disconnector operations are recorded by a self-developed measurement system first. Then, statistical characteristics, such as the pulse number, duration of pulses, frequency components, magnitude and single pulse duration, are extracted. The transmission line theory is introduced to analyze the TEV and is validated by the experimental results. Finally, the relationship between the TEV and the repeated strike process is analyzed. This proves that the pulse voltage of the TEV is proportional to the corresponding breakdown voltage. The results contribute to the definition of the standard testing waveform of the TEV, and can aid the protection of electronic devices in substations by minimizing the threat of this phenomenon.

Design of auto-control high-voltage control system of pulsed neutron generator

International Nuclear Information System (INIS)

Lv Juntao

2008-01-01

It is difficult to produce multiple anode controlling time sequences under different logging mode for the high-voltage control system of the conventional pulsed neutron generator. It is also difficult realize sequential control among anode high-voltage, filament power supply and target voltage to make neutron yield stable. To these problems, an auto-control high-voltage system of neutron pulsed generator was designed. It not only can achieve anode high-voltage double blast time sequences, which can measure multiple neutron blast time sequences such as Σ, activated spectrum, etc. under inelastic scattering mode, but also can realize neutron generator real-time measurement of multi-state parameters and auto-control such as target voltage pulse width modulation (PWM), filament current, anode current, etc., there by it can produce stable neutron yield and realize stable and accurate measurement of the pulsed neutron full spectral loging tool. (authors)

High voltage switch triggered by a laser-photocathode subsystem

Science.gov (United States)

Chen, Ping; Lundquist, Martin L.; Yu, David U. L.

2013-01-08

A spark gap switch for controlling the output of a high voltage pulse from a high voltage source, for example, a capacitor bank or a pulse forming network, to an external load such as a high gradient electron gun, laser, pulsed power accelerator or wide band radar. The combination of a UV laser and a high vacuum quartz cell, in which a photocathode and an anode are installed, is utilized as triggering devices to switch the spark gap from a non-conducting state to a conducting state with low delay and low jitter.

The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology

NARCIS (Netherlands)

Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, Domine M.W.; Nauta, Bram

2008-01-01

Abstract—This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a

Analysis of the rectangular resonator with butterfly MMI coupler using SOI

Science.gov (United States)

Kim, Sun-Ho; Park, Jun-Hee; Kim, Eudum; Jeon, Su-Jin; Kim, Ji-Hoon; Choi, Young-Wan

2018-02-01

We propose a rectangular resonator sensor structure with butterfly MMI coupler using SOI. It consists of the rectangular resonator, total internal reflection (TIR) mirror, and the butterfly MMI coupler. The rectangular resonator is expected to be used as bio and chemical sensors because of the advantages of using MMI coupler and the absence of bending loss unlike ring resonators. The butterfly MMI coupler can miniaturize the device compared to conventional MMI by using a linear butterfly shape instead of a square in the MMI part. The width, height, and slab height of the rib type waveguide are designed to be 1.5 μm, 1.5 μm, and 0.9 μm, respectively. This structure is designed as a single mode. When designing a TIR mirror, we considered the Goos-Hänchen shift and critical angle. We designed 3:1 MMI coupler because rectangular resonator has no bending loss. The width of MMI is designed to be 4.5 μm and we optimize the length of the butterfly MMI coupler using finite-difference time-domain (FDTD) method for higher Q-factor. It has the equal performance with conventional MMI even though the length is reduced by 1/3. As a result of the simulation, Qfactor of rectangular resonator can be obtained as 7381.

BEHAVIOUR OF BACKFILL MATERIALS FOR ELECTRICAL GROUNDING SYSTEMS UNDER HIGH VOLTAGE CONDITIONS

Directory of Open Access Journals (Sweden)

S. C. LIM

2015-06-01

Full Text Available Backfill materials like Bentonite and cement are effective in lowering grounding resistance of electrodes for a considerable period. During lightning, switching impulses and earth fault occurrences in medium and high voltage networks, the grounding system needs to handle extremely high currents either for a short duration or prolonged period respectively. This paper investigates the behaviour of bentonite, cement and sand under impulse and alternating high voltage (50Hz conditions. Fulguritic-formation was observed in all materials under alternating high voltage. The findings reveal that performance of grounding systems under high voltage conditions may significantly change from the outcomes anticipated at design stage.

Effects of q and high beta on tokamak stability

International Nuclear Information System (INIS)

Brickhouse, N.S.; Callen, J.D.; Dexter, R.N.

1984-08-01

In the Columbia University Torus II tokamak plasmas have been studied with volume averaged toroidal beta values as high as 15%. Experimental equilibria have been compared with a 2D free boundary MHD equilibrium code PSEC. The stability of these equilibria has been computed using PEST, the predictions of which are compatible with an observed instability in Torus II which may be characterized as a high toroidal mode number ballooning fluctuation. In the University of Wisconsin Tokapole II tokamak disruptive instability behavior is investigated, with plasma able to be confined on closed magnetic surfaces in the scrape-off region, as the cylindrical edge safety factor is varied from q approx. 3 to q approx. 0.5. It is observed that at q/sub a/ approx. 3 major disruption activity occurs without current terminations, at q/sub a/ less than or equal to 2 well-confined plasmas are obtained without major disruption, and at q/sub a/ approx. 0.5 only partial reconnection accompanies minor disruptions

High frequency breakdown voltage

International Nuclear Information System (INIS)

Chu, Thanh Duy.

1992-03-01

This report contains information about the effect of frequency on the breakdown voltage of an air gap at standard pressure and temperature, 76 mm Hg and O degrees C, respectively. The frequencies of interest are 47 MHz and 60 MHz. Additionally, the breakdown in vacuum is briefly considered. The breakdown mechanism is explained on the basis of collision and ionization. The presence of the positive ions produced by ionization enhances the field in the gap, and thus determines the breakdown. When a low-frequency voltage is applied across the gap, the breakdown mechanism is the same as that caused by the DC or static voltage. However, when the frequency exceeds the first critical value f c , the positive ions are trapped in the gap, increasing the field considerably. This makes the breakdown occur earlier; in other words, the breakdown voltage is lowered. As the frequency increases two decades or more, the second critical frequency, f ce , is reached. This time the electrons start being trapped in the gap. Those electrons that travel multiple times across the gap before reaching the positive electrode result in an enormous number of electrons and positive ions being present in the gap. The result is a further decrease of the breakdown voltage. However, increasing the frequency does not decrease the breakdown voltage correspondingly. In fact, the associated breakdown field intensity is almost constant (about 29 kV/cm).The reason is that the recombination rate increases and counterbalances the production rate, thus reducing the effect of the positive ions' concentration in the gap. The theory of collision and ionization does not apply to the breakdown in vacuum. It seems that the breakdown in vacuum is primarily determined by the irregularities on the surfaces of the electrodes. Therefore, the effect of frequency on the breakdown, if any, is of secondary importance

High voltage calibration of the TANSY-KM5 neutron detectors

International Nuclear Information System (INIS)

Grosshoeg, G.; Belle, P. van; Wilson, D.

1996-11-01

We have developed a procedure for the high voltage calibration of the TANSY neutron detectors. The procedure is based on the work done during the construction of the spectrometer. A program is written for the measurement of the sensitivity of the neutron detectors as a function of the high voltage. The data are transferred to a PC for evaluation. We use a Cobalt source for the calibration. With the PC the voltage corresponding to the effective Compton edge is found. The voltage settings for the neutron detectors are calculated and stored in a file suitable for input to a program that is used to control the instrument. A measurement is reported that shows that the reproducibility of the measurement is good. 4 refs

Lithium-Ion Electrolytes with Improved Safety Tolerance to High Voltage Systems

Science.gov (United States)

Smart, Marshall C. (Inventor); Bugga, Ratnakumar V. (Inventor); Prakash, Surya G. (Inventor); Krause, Frederick C. (Inventor)

2015-01-01

The invention discloses various embodiments of electrolytes for use in lithium-ion batteries, the electrolytes having improved safety and the ability to operate with high capacity anodes and high voltage cathodes. In one embodiment there is provided an electrolyte for use in a lithium-ion battery comprising an anode and a high voltage cathode. The electrolyte has a mixture of a cyclic carbonate of ethylene carbonate (EC) or mono-fluoroethylene carbonate (FEC) co-solvent, ethyl methyl carbonate (EMC), a flame retardant additive, a lithium salt, and an electrolyte additive that improves compatibility and performance of the lithium-ion battery with a high voltage cathode. The lithium-ion battery is charged to a voltage in a range of from about 2.0 V (Volts) to about 5.0 V (Volts).

A microcontroller application as X-ray machine's high voltage controller

International Nuclear Information System (INIS)

Wiranto Budi Santoso; Beny Syawaludin

2010-01-01

A micro controller application as x-ray machine's high voltage controller has been carried out. The purpose of this micro controller application is to give an accurate high voltage supply to the x-ray tube so that the x-ray machine could produce the result as expected. The micro controller based X-ray machine's high voltage controller receives an input voltage from the keypad. This input value is displayed in the LCD (Liquid Crystal Display) screen. Then micro controller uses this input data to drive a stepper motor. The stepper motor adjusts the high voltage auto transformer's output according to the input value. The micro controller is programmed using BASCOM-8051 compiler. The test results show that the stepper motor could rotate according to an input value (author)

Advances in high voltage engineering

CERN Document Server

Haddad, A

2005-01-01

This book addresses the very latest research and development issues in high voltage technology and is intended as a reference source for researchers and students in the field, specifically covering developments throughout the past decade. This unique blend of expert authors and comprehensive subject coverage means that this book is ideally suited as a reference source for engineers and academics in the field for years to come.

Compact, Lightweight, High Voltage Propellant Isolators, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — TA&T, Inc. proposes an enabling fabrication process for high voltage isolators required in high power solar electric and nuclear electric propulsion (SEP and...

Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

DEFF Research Database (Denmark)

Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

2014-01-01

We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

Report on achievements in fiscal 1998. Development on an immediately effective and innovative energy and environment technology (Research and development of an information terminal LSI requiring very low power consumption); 1998 nendo sokkoteki kakushinteki energy kankyo gijutsu kaihatsu seika hokokusho. Gokuteidenryoku joho tanmatsuyo LSI no kenkyu kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1999-09-01

It is intended that the technology for SOI expected of consuming very small power and operating at high speed be realized as an information terminal LSI for the coming 21st century. Therefore, research and development is made on the fundamental technology for LSI which operates in CMOS devices at high speed even with as very low voltage as about 0.5V by applying the optimized digital and analog circuit technology. Specifically, the aim is placed on enhancement of drive capability of transistors over that in the present devices, reduction of load capacity, and a very thin film complete depletion type SOI device that can be most expected of reduction of area as the main subjects. It is also intended to establish a method to realize very low power consuming LSI by using a CMOS circuit (a multi threshold value type CMOS circuit) that uses transistors with different threshold voltages and is optimized for the above SOI device. The achievements in this fiscal year include: a prototype 256kbSRAM was fabricated by using different design rules and wafer sizes, and the performance evaluation thereon was obtained; investigations were carried out on selection of SOI models for circuit simulation and on a high accuracy complete depletion type SOI models; and design criteria required for LSI design were put in order for comprehensive trial fabrication. (NEDO)

Calibration of the ISOLDE acceleration voltage using a high-precision voltage divider and applying collinear fast beam laser spectroscopy

Energy Technology Data Exchange (ETDEWEB)

Krieger, A., E-mail: kriegea@uni-mainz.d [Institut fuer Kernchemie, Johannes Gutenberg, Universitaet Mainz, Fritz-Strassmann-Weg 2, 55128 Mainz (Germany); Geppert, Ch. [Institut fuer Kernchemie, Johannes Gutenberg, Universitaet Mainz, Fritz-Strassmann-Weg 2, 55128 Mainz (Germany); GSI Helmholtzzentrum fuer Schwerionenforschung, 64291 Darmstadt (Germany); Catherall, R. [CERN, CH-1211 Geneve 23 (Switzerland); Hochschulz, F. [Institut fuer Kernphysik, Universitaet Muenster, 48149 Muenster (Germany); Kraemer, J.; Neugart, R. [Institut fuer Kernchemie, Johannes Gutenberg, Universitaet Mainz, Fritz-Strassmann-Weg 2, 55128 Mainz (Germany); Rosendahl, S. [Institut fuer Kernphysik, Universitaet Muenster, 48149 Muenster (Germany); Schipper, J.; Siesling, E. [CERN, CH-1211 Geneve 23 (Switzerland); Weinheimer, Ch. [Institut fuer Kernphysik, Universitaet Muenster, 48149 Muenster (Germany); Yordanov, D.T. [Max-Planck-Institut fuer Kernphysik, 69117 Heidelberg (Germany); Noertershaeuser, W. [Institut fuer Kernchemie, Johannes Gutenberg, Universitaet Mainz, Fritz-Strassmann-Weg 2, 55128 Mainz (Germany); GSI Helmholtzzentrum fuer Schwerionenforschung, 64291 Darmstadt (Germany)

2011-03-11

A high-voltage divider with accuracy at the ppm level and collinear laser spectroscopy were used to calibrate the high-voltage installation at the radioactive ion beam facility ISOLDE at CERN. The accurate knowledge of this voltage is particularly important for collinear laser spectroscopy measurements. Beam velocity measurements using frequency-comb based collinear laser spectroscopy agree with the new calibration. Applying this, one obtains consistent results for isotope shifts of stable magnesium isotopes measured using collinear spectroscopy and laser spectroscopy on laser-cooled ions in a trap. The long-term stability and the transient behavior during recovery from a voltage dropout were investigated for the different power supplies currently applied at ISOLDE.

A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

Science.gov (United States)

Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

2012-12-01

A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

Fast response double series resonant high-voltage DC-DC converter

International Nuclear Information System (INIS)

Lee, S S; Iqbal, S; Kamarol, M

2012-01-01

In this paper, a novel double series resonant high-voltage dc-dc converter with dual-mode pulse frequency modulation (PFM) control scheme is proposed. The proposed topology consists of two series resonant tanks and hence two resonant currents flow in each switching period. Moreover, it consists of two high-voltage transformer with the leakage inductances are absorbed as resonant inductor in the series resonant tanks. The secondary output of both transformers are rectified and mixed before supplying to load. In the resonant mode operation, the series resonant tanks are energized alternately by controlling two Insulated Gate Bipolar Transistor (IGBT) switches with pulse frequency modulation (PFM). This topology operates in discontinuous conduction mode (DCM) with all IGBT switches operating in zero current switching (ZCS) condition and hence no switching loss occurs. To achieve fast rise in output voltage, a dual-mode PFM control during start-up of the converter is proposed. In this operation, the inverter is started at a high switching frequency and as the output voltage reaches 90% of the target value, the switching frequency is reduced to a value which corresponds to the target output voltage. This can effectively reduce the rise time of the output voltage and prevent overshoot. Experimental results collected from a 100-W laboratory prototype are presented to verify the effectiveness of the proposed system.

Advances in high voltage insulation and arc interruption in SF6 and vacuum

CERN Document Server

Maller, V N

1982-01-01

Advances in High Voltage Insulation and Arc Interruption in SF6 and Vacuum deals with high voltage breakdown and arc extinction in sulfur hexafluoride (SF6) and high vacuum, with special emphasis on the application of these insulating media in high voltage power apparatus and devices. The design and developmental aspects of various high voltage power apparatus using SF6 and high vacuum are highlighted. This book is comprised of eight chapters and opens with a discussion on electrical discharges in SF6 and high vacuum, along with the properties and handling of SF6 gas. The following chapters fo

High-Q plasmonic bottle microresonator

Science.gov (United States)

Mohd Nasir, M. Narizee; Ding, Ming; Murugan, G. Senthil; Zervas, Michalis N.

2014-03-01

In this paper, we demonstrate a hybrid plasmonic bottle microresonator (PBMR) which supports whispering gallery modes (WGMs) along with surface plasmon waves (SPWs) for high performance optical sensor applications. The BMR was fabricated through "soften-and-compress" technique with a thin gold layer deposited on top of the resonator. A polarization-resolved measurement was set-up in order to fully characterize the fabricated PBMR. Initially, the uncoated BMR with waist diameter of 181 μm, stem diameter of 125 μm and length of 400 μm was fabricated and then gold film was deposited on the surface. Due to surface curvature, the gold film covering half of the BMR had a characteristic meniscus shape and maximum thickness of 30 nm. The meniscus provides appropriately tapered edges which facilitate the adiabatic transformation of BMR WGMs to SPWs and vice versa. This results in low transition losses, which combined with partially-metal-coated resonator, can result in high hybrid-PBMR Q's. The transmission spectra of the hybrid PBMR are dramatically different to the original uncoated BMR. Under TE(TM) excitation, the PBMR showed composite resonances with Q of ~2100(850) and almost identical ~ 3 nm FSR. We have accurately fitted the observed transmission resonances with Lorentzian-shaped curves and showed that the TE and TM excitations are actually composite resonances comprise of two and three partially overlapping resonances with Q's in excess of 2900 and 2500, respectively. To the best of our knowledge these are the highest Qs observed in plasmonic microcavities.

Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

Science.gov (United States)

Adell, Philippe C.; Mojarradi, Mohammad; DelCastillo, Linda Y.; Vo, Tuan A.

2011-01-01

A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

System for high-voltage control detectors with large number photomultipliers

International Nuclear Information System (INIS)

Donskov, S.V.; Kachanov, V.A.; Mikhajlov, Yu.V.

1985-01-01

A simple and inexpensive on-line system for hihg-voltage control which is designed for detectors with a large number of photomultipliers is developed and manufactured. It has been developed for the GAMC type hodoscopic electromagnetic calorimeters, comprising up to 4 thousand photomultipliers. High voltage variation is performed by a high-speed potentiometer which is rotated by a microengine. Block-diagrams of computer control electronics are presented. The high-voltage control system has been used for five years in the IHEP and CERN accelerator experiments. The operation experience has shown that it is quite simple and convenient in operation. In case of about 6 thousand controlled channels in both experiments no potentiometer and microengines failures were observed

Design and realization of high voltage disconnector condition monitoring system

Science.gov (United States)

Shi, Jinrui; Xu, Tianyang; Yang, Shuixian; Li, Buoyang

2017-08-01

The operation status of the high voltage disconnector directly affects the safe and stable operation of the power system. This article uses the wireless frequency hopping communication technology of the communication module to achieve the temperature acquisition of the switch contacts and high voltage bus, to introduce the current value of the loop in ECS, and judge the operation status of the disconnector by considering the ambient temperature, calculating the temperature rise; And through the acquisition of the current of drive motor in the process of switch closing and opening, and fault diagnosis of the disconnector by analyzing the change rule of the drive motor current, the condition monitoring of the high voltage disconnector is realized.

Self-aligned photolithography for the fabrication of fully transparent high-voltage devices

Science.gov (United States)

Zhang, Yonghui; Mei, Zengxia; Huo, Wenxing; Wang, Tao; Liang, Huili; Du, Xiaolong

2018-05-01

High-voltage devices, working in the range of hundreds of volts, are indispensable elements in the driving or readout circuits for various kinds of displays, integrated microelectromechanical systems and x-ray imaging sensors. However, the device performances are found hardly uniform or repeatable due to the misalignment issue, which are extremely common for offset drain high-voltage devices. To resolve this issue, this article reports a set of self-aligned photolithography technology for the fabrication of high-voltage devices. High-performance fully-transparent high-voltage thin film transistors, diodes and logic inverters are successfully fabricated with this technology. Unlike other self-aligned routes, opaque masks are introduced on the backside of the transparent substrate to facilitate proximity exposure method. The photolithography process is simulated and analyzed with technology computer aided design simulation to explain the working principle of the proximity exposure method. The substrate thickness is found to be vital for the implementation of this technology based on both simulation and experimental results. The electrical performance of high-voltage devices is dependent on the offset length, which can be delicately modulated by changing the exposure dose. The presented self-aligned photolithography technology is proved to be feasible in high-voltage circuits, demonstrating its huge potential in practical industrial applications.

Design Comparison of Autonomous High Voltage Driving System for DEAP Actuator

DEFF Research Database (Denmark)

Huang, Lina; Pittini, Riccardo; Zhang, Zhe

2014-01-01

As a new type of smart material, the Dielectric Electro Active Polymer (DEAP) is introduced in terms of configuration, working principle and potential applications. The design of an autonomous high voltage driving system for DEAP actuator is investigated. The system configuration and the design...... methodology of a high voltage converter are discussed in detail. Based on the heating valve application, three different high voltage converter solutions have been proposed. The different proposals have been compared in terms of energy loss, volume and cost. Finally, the design selection suggestions...

Enhanced Local Grid Voltage Support Method for High Penetration of Distributed Generators

DEFF Research Database (Denmark)

Demirok, Erhan; Sera, Dezso; Rodriguez, Pedro

2011-01-01

Grid voltage rise and thermal loading of network components are the most remarkable barriers to allow high number of distributed generator (DG) connections on the medium voltage (MV) and low voltage (LV) electricity networks. The other barriers such as grid power quality (harmonics, voltage...

High-Q microwave photonic filter with a tuned modulator.

Science.gov (United States)

Capmany, J; Mora, J; Ortega, B; Pastor, D

2005-09-01

We propose the use of tuned electro-optic or electroabsorption external modulators to implement high-quality (high-Q) factor, single-bandpass photonic filters for microwave signals. Using this approach, we experimentally demonstrate a transversal finite impulse response with a Q factor of 237. This is to our knowledge the highest value ever reported for a passive finite impulse-response microwave photonic filter.

Computer applications: Automatic control system for high-voltage accelerator

International Nuclear Information System (INIS)

Bryukhanov, A.N.; Komissarov, P.Yu.; Lapin, V.V.; Latushkin, S.T.. Fomenko, D.E.; Yudin, L.I.

1992-01-01

An automatic control system for a high-voltage electrostatic accelerator with an accelerating potential of up to 500 kV is described. The electronic apparatus on the high-voltage platform is controlled and monitored by means of a fiber-optic data-exchange system. The system is based on CAMAC modules that are controlled by a microprocessor crate controller. Data on accelerator operation are represented and control instructions are issued by means of an alphanumeric terminal. 8 refs., 6 figs

Technical and economic considerations of extra high voltage power transmission

Energy Technology Data Exchange (ETDEWEB)

Kahnt, R

1966-09-01

The reasons for the employment of higher transmission voltages are listed and the points decisive for the selection of three phase ac or dc systems are reviewed. The technical and economic problems arising in three phase extra high voltage transmission are discussed. These include selection of voltage, economical design of power lines, insulation problems, power supply dependability, equipment rating and reactive power and stability problems.

High-voltage variable-duration pulse generator

International Nuclear Information System (INIS)

Anisimova, T.E.; Akkuratov, E.V.; Gromovenko, V.M.; Nikonov, Yu.P.; Malinin, A.N.

1988-01-01

A high-voltage generator is described that allows pulse duration tau to be varied within wide limits and has high efficiency (at least 50% for tau = 0.5 tau/sub max/) and an amplitude of up to 5 kV, a repetition frequency of up to 200 Hz,and a variable duration of 0-30 μsec. The generator is used in the controller of an electron accelerator

High-voltage polymeric insulated cables

Energy Technology Data Exchange (ETDEWEB)

Ross, A

1987-01-01

Reviews developments in high-voltage (here defined as 25 kV, 66 kV and 132 kV) polymeric insulated cables in the UK over the period 1979-1986, with particular reference to the experience of the Eastern Electricity Board. Outlines the background to the adoption of XPLE-insulated solid cable, and the design, testing, terminations, jointing and costs of 25 kV, 66 kV and 132 kV cables.

High voltage short plus generation based on avalanche circuit

International Nuclear Information System (INIS)

Hu Yuanfeng; Yu Xiaoqi

2006-01-01

Simulate the avalanche circuit in series with PSPICE module, design the high voltage short plus generation circuit by avalanche transistor in series for the sweep deflection circuit of streak camera. The output voltage ranges 1.2 KV into 50 ohm load. The rise time of the circuit is less than 3 ns. (authors)

A high-voltage pulse generator for corona plasma generation

NARCIS (Netherlands)

Yan, K.; Heesch, van E.J.M.; Pemen, A.J.M.; Huijbrechts, P.A.H.J.; Gompel, van F.M.; Leuken, van H.E.M.; Matyas, Z.

2002-01-01

This paper discusses a high-voltage pulse generator for producing corona plasma. The generator consists of three resonant charging circuits, a transmission line transformer, and a triggered spark-gap switch. Voltage pulses in the order of 30-100 kV with a rise time of 10-20 ns, a pulse duration of

On-chip high-voltage generator design design methodology for charge pumps

CERN Document Server

Tanzawa, Toru

2016-01-01

This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

Energy Technology Data Exchange (ETDEWEB)

Erofeev, E. V., E-mail: erofeev@micran.ru [Tomsk State University of Control Systems and Radioelectronics, Research Institute of Electrical-Communication Systems (Russian Federation); Fedin, I. V.; Kutkov, I. V. [Research and Production Company “Micran” (Russian Federation); Yuryev, Yu. N. [National Research Tomsk Polytechnic University, Institute of Physics and Technology (Russian Federation)

2017-02-15

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

International Nuclear Information System (INIS)

Erofeev, E. V.; Fedin, I. V.; Kutkov, I. V.; Yuryev, Yu. N.

2017-01-01

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V_t_h = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V_t_h = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Environmental and biotechnological applications of high-voltage pulsed discharges in water

International Nuclear Information System (INIS)

Sato, Masayuki

2008-01-01

A high-voltage pulse has wide application in fields such as chemistry, physics and biology and their combinations. The high-voltage pulse forms two kinds of physical processes in water, namely (a) a pulsed electric field (PEF) in the parallel electrode configuration and (b) plasma generation by a pulsed discharge in the water phase with a concentrated electric field. The PEF can be used for inactivation of bacteria in liquid foods as a non-thermal process, and the underwater plasma is applicable not only for the decomposition of organic materials in water but also for biological treatment of wastewater. These discharge states are controlled mainly by the applied pulse voltage and the electrode shape. Some examples of environmental and biotechnological applications of a high-voltage pulse are reviewed.

High-voltage test and training of plastic streamer tubes for the DELPHI hadron calorimeter

International Nuclear Information System (INIS)

Alekseev, G.D.; Cellar, S.; Khomenko, B.A.; Korytov, A.V.; Kulinich, P.A.; Micelmacher, G.V.; Sedykh, Yu.V.; Toledo, R.

1987-01-01

The results of high-voltage test and training of plastic streamer tubes of the DELPHI hadron calorimeter are presented. The testing technique is considered in detail. The equipment for high-voltage training consists of a mini-computer, CAMAC-electronics, a controllable high-voltage supply and a digital ampermeter. The experimental results shows that high-voltage training of streamer tubes improves their characteristics. The value of dark current decreased up to 1 μA. The operational voltage range increased by a value more than 300 V

LIMIT SOLUTIONS OF EQUATIONS OF A DC HIGH-VOLTAGE CASCADE GENERATOR

Directory of Open Access Journals (Sweden)

V. O. Brzhezitsky

2015-04-01

Full Text Available In the paper the issue of calculating the high voltage cascade mode oscillator with a nonlinear load using the analytical method under different conditions of selection values of its components is presented. The peculiarity of the method of the study is that during multivariate calculations output parameters load generator remain unchanged. For high-voltage cascade direct current power found conditions under which can be significantly reduced high capacity capacitors cascade generator. The calculations show that acceptable for practical applications of high-voltage characteristics of cascade generators can be achieved with substantial reduction of the volume of their constituents, and thus substantial decline in their value.

A novel high voltage start up circuit for an integrated switched mode power supply

Energy Technology Data Exchange (ETDEWEB)

Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

2010-09-15

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

High Voltage Hybrid Electric Propulsion - Multilayered Functional Insulation System (MFIS) NASA-GRC

Science.gov (United States)

Lizcano, M.

2017-01-01

High power transmission cables pose a key challenge in future Hybrid Electric Propulsion Aircraft. The challenge arises in developing safe transmission lines that can withstand the unique environment found in aircraft while providing megawatts of power. High voltage AC, variable frequency cables do not currently exist and present particular electrical insulation challenges since electrical arcing and high heating are more prevalent at higher voltages and frequencies. Identifying and developing materials that maintain their dielectric properties at high voltage and frequencies is crucial.

Wideband Electrostatic Vibration Energy Harvester (e-VEH) Having a Low Start-Up Voltage Employing a High-Voltage Integrated Interface

International Nuclear Information System (INIS)

Dudka, A; Galayko, D; Basset, P; Cottone, F; Blokhina, E

2013-01-01

This paper reports on an electrostatic Vibration Energy Harvester (e-VEH) system, for which the energy conversion process is initiated with a low bias voltage and is compatible with wideband stochastic external vibrations. The system employs the auto-synchronous conditioning circuit topology with the use of a novel dedicated integrated low-power high-voltage switch that is needed to connect the charge pump and flyback – two main parts of the used conditioning circuit. The proposed switch is designed and implemented in AMS035HV CMOS technology. Thanks to the proposed switch device, which is driven with a low-voltage ground-referenced logic, the e-VEH system may operate within a large voltage range, from a pre-charge low voltage up to several tens volts. With such a high-voltage e-VEH operation, it is possible to obtain a strong mechanical coupling and a high rate of vibration energy conversion. The used transducer/resonator device is fabricated with a batch-processed MEMS technology. When excited with stochastic vibrations having an acceleration level of 0.8 g rms distributed in the band 110–170 Hz, up to 0.75 μW of net electrical power has been harvested with our system. This work presents an important milestone in the challenge of designing a fully integrated smart conditioning interface for the capacitive e-VEHs

Technical and economic considerations of extra high voltage power transmission

Energy Technology Data Exchange (ETDEWEB)

Kahnt, R

1966-09-01

The reasons for the employment of higher transmission voltages are listed and the points decisive for the selection of three phase ac or dc systems are reviewed. This is followed by treatment of the technical and economic problems arising in three phase-extra high voltage transmission. These include selection of voltage, economical design of power lines, insulation problems, power supply dependability, equipment rating, and reactive power and stability problems.

High-voltage therapy of carcinoma of the prostate

International Nuclear Information System (INIS)

Schnorr, D.; Kelly, L.U.; Guddat, H.M.; Schubert, J.; Gorski, J.; Schorcht, J.; Mau, S.; Wehnert, J.; Medizinische Akademie, Dresden

1983-01-01

High-voltage therapy is becoming increasingly important as a form of individual differential therapy of carcinoma of the prostate. Around 40% of all patients with a diagnosis of carcinoma of the prostate can be treated with high-voltage therapy. The precondition is the absence of bone and soft tissue metastases and of juxtaregional lymph node metastases. Individual carcinoma therapy is based on pre therapeutic tumor classification according to the TNM system. The 5-year survival rates are presented from a retrospective study carried out using primary radiation monotherapy and a combined hormone and radiation therapy; these figures were calculated by the life-table method. The study revealed no significant differences between the two forms of therapy as regards 5-year survival rates. The 5-year survival rates of all patients of the classifications T 0 -T 3 N/sub x/-N 2 M 0 irradiated (n: 198) (72% +- 11% for hormone plus radiation therapy and 74% +- 11% for radiation monotherapy) did not differ greatly from those of a normal male population of the same age (77%). High-voltage therapy of carcinoma of the prostate can thus be classified as a curative method of treatment. (author)

Influence of edge effects on single event upset susceptibility of SOI SRAMs

International Nuclear Information System (INIS)

Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

2015-01-01

An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

Interaction between beam control and rf feedback loops for high Q cavities an heavy beam loading. Revision A

International Nuclear Information System (INIS)

Mestha, L.K.; Kwan, C.M.; Yeung, K.S.

1994-04-01

An open-loop state space model of all the major low-level rf feedback control loops is derived. The model has control and state variables for fast-cycling machines to apply modern multivariable feedback techniques. A condition is derived to know when exactly we can cross the boundaries between time-varying and time-invariant approaches for a fast-cycling machine like the Low Energy Booster (LEB). The conditions are dependent on the Q of the cavity and the rate at which the frequency changes with time. Apart from capturing the time-variant characteristics, the errors in the magnetic field are accounted in the model to study the effects on synchronization with the Medium Energy Booster (MEB). The control model is useful to study the effects on beam control due to heavy beam loading at high intensities, voltage transients just after injection especially due to time-varying voltages, instability thresholds created by the cavity tuning feedback system, cross coupling between feedback loops with and without direct rf feedback etc. As a special case we have shown that the model agrees with the well known Pedersen model derived for the CERN PS booster. As an application of the model we undertook a detailed study of the cross coupling between the loops by considering all of them at once for varying time, Q and beam intensities. A discussion of the method to identify the coupling is shown. At the end a summary of the identified loop interactions is presented

High voltage pulsed cable design: a practical example

International Nuclear Information System (INIS)

Kewish, R.W. Jr.; Boicourt, G.P.

1979-01-01

The design of optimum high voltage pulse cable is difficult because very little emperical data are available on performance in pulsed applications. This paper follows the design and testing of one high voltage pulse cable, 40/100 trigger cable. The design was based on an unproven theory and the impressive outcome lends support to the theory. The theory is outlined and it is shown that there exists an inductance which gives a cable of minimum size for a given maximum stress. Test results on cable manufactured according to the design are presented and compared with the test results on the cable that 40/100 replaces

High voltage pulsed cable design: a practical example

Energy Technology Data Exchange (ETDEWEB)

Kewish, R.W. Jr.; Boicourt, G.P.

1979-01-01

The design of optimum high voltage pulse cable is difficult because very little emperical data are available on performance in pulsed applications. This paper follows the design and testing of one high voltage pulse cable, 40/100 trigger cable. The design was based on an unproven theory and the impressive outcome lends support to the theory. The theory is outlined and it is shown that there exists an inductance which gives a cable of minimum size for a given maximum stress. Test results on cable manufactured according to the design are presented and compared with the test results on the cable that 40/100 replaces.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

International Nuclear Information System (INIS)

Wu Hao; Xu Miao; Wan Guangxing; Zhu Huilong; Zhao Lichuan; Tong Xiaodong; Zhao Chao; Chen Dapeng; Ye Tianchun

2014-01-01

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, V t -roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (V t ) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing V t at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated. (semiconductor devices)

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

Science.gov (United States)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

Science.gov (United States)

Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

2009-12-01

The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

Energy Technology Data Exchange (ETDEWEB)

Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

2015-10-15

The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

International Nuclear Information System (INIS)

Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

2010-01-01

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

New Insights into Fully-Depleted SOI Transistor Response During Total Dose Irradiation

International Nuclear Information System (INIS)

Burns, J.A.; Dodd, P.E.; Keast, C.L.; Schwank, J.R.; Shaneyfelt, M.R.; Wyatt, P.W.

1999-01-01

Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. No evidence was found for total-dose induced snap back. These results have implications for hardness assurance testing

High voltage transmission lines studies with the use of artificial intelligence

Energy Technology Data Exchange (ETDEWEB)

Ekonomou, L. [A.S.PE.T.E. - School of Pedagogical and Technological Education, Department of Electrical Engineering Educators, N. Heraklion, 141 21 Athens (Greece)

2009-12-15

The paper presents an alternative approach for the studies of high voltage transmission lines based on artificial intelligence and more specifically artificial neural networks (ANNs). In contrast to the existing conventional-analytical techniques and simulations which are using in the calculations empirical and/or approximating equations, this approach is based only on actual field data and actual measurements. The proposed approach is applied on high voltage transmission lines in order to calculate the lightning outages, on grounding systems in order to assess the grounding resistance and on high voltage transmission lines' polluted insulators in order to estimate the critical flashover voltage. The obtained results are very close to the actual ones for all three case studies, something which clearly implies that the ANN approach is well working and has an acceptable accuracy, constituting an additional tool of electric engineers. (author)

30 CFR 75.803 - Fail safe ground check circuits on high-voltage resistance grounded systems.

Science.gov (United States)

2010-07-01

... High-Voltage Distribution § 75.803 Fail safe ground check circuits on high-voltage resistance grounded systems. [Statutory Provisions] On and after September 30, 1970, high-voltage, resistance grounded systems... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Fail safe ground check circuits on high-voltage...

Contribution to high voltage matrix switches reliability

International Nuclear Information System (INIS)

Lausenaz, Yvan

2000-01-01

Nowadays, power electronic equipment requirements are important, concerning performances, quality and reliability. On the other hand, costs have to be reduced in order to satisfy the market rules. To provide cheap, reliability and performances, many standard components with mass production are developed. But the construction of specific products must be considered following these two different points: in one band you can produce specific components, with delay, over-cost problems and eventuality quality and reliability problems, in the other and you can use standard components in a adapted topologies. The CEA of Pierrelatte has adopted this last technique of power electronic conception for the development of these high voltage pulsed power converters. The technique consists in using standard components and to associate them in series and in parallel. The matrix constitutes high voltage macro-switch where electrical parameters are distributed between the synchronized components. This study deals with the reliability of these structures. It brings up the high reliability aspect of MOSFETs matrix associations. Thanks to several homemade test facilities, we obtained lots of data concerning the components we use. The understanding of defects propagation mechanisms in matrix structures has allowed us to put forwards the necessity of robust drive system, adapted clamping voltage protection, and careful geometrical construction. All these reliability considerations in matrix associations have notably allowed the construction of a new matrix structure regrouping all solutions insuring reliability. Reliable and robust, this product has already reaches the industrial stage. (author) [fr

High-voltage-activated calcium current subtypes in mouse DRG neurons adapt in a subpopulation-specific manner after nerve injury.

Science.gov (United States)

Murali, Swetha S; Napier, Ian A; Mohammadi, Sarasa A; Alewood, Paul F; Lewis, Richard J; Christie, MacDonald J

2015-03-01

Changes in ion channel function and expression are characteristic of neuropathic pain. Voltage-gated calcium channels (VGCCs) are integral for neurotransmission and membrane excitability, but relatively little is known about changes in their expression after nerve injury. In this study, we investigate whether peripheral nerve ligation is followed by changes in the density and proportion of high-voltage-activated (HVA) VGCC current subtypes in dorsal root ganglion (DRG) neurons, the contribution of presynaptic N-type calcium channels in evoked excitatory postsynaptic currents (EPSCs) recorded from dorsal horn neurons in the spinal cord, and the changes in expression of mRNA encoding VGCC subunits in DRG neurons. Using C57BL/6 mice [8- to 11-wk-old males (n = 91)] for partial sciatic nerve ligation or sham surgery, we performed whole cell patch-clamp recordings on isolated DRG neurons and dorsal horn neurons and measured the expression of all VGCC subunits with RT-PCR in DRG neurons. After nerve injury, the density of P/Q-type current was reduced overall in DRG neurons. There was an increase in the percentage of N-type and a decrease in that of P/Q-type current in medium- to large-diameter neurons. No changes were found in the contribution of presynaptic N-type calcium channels in evoked EPSCs recorded from dorsal horn neurons. The α2δ-1 subunit was upregulated by 1.7-fold and γ-3, γ-2, and β-4 subunits were all downregulated 1.7-fold in injured neurons compared with sham-operated neurons. This comprehensive characterization of HVA VGCC subtypes in mouse DRG neurons after nerve injury revealed changes in N- and P/Q-type current proportions only in medium- to large-diameter neurons. Copyright © 2015 the American Physiological Society.

High voltage system design for the IUCF 300 KV electron cooling system

International Nuclear Information System (INIS)

Bertuccio, T.; Brown, B.; Donica, G.; Ellison, T.; Friesel, D.L.

1985-01-01

A summary of the electron beam high voltage system design for the IUCF Cooler now under construction, is presented. There are extremely stringent regulation requirements (about 10ppm) on the main high voltage power supply (-300 kVDC, 15 mA), and less stringent requirements on the gun anode power supply, in order to achieve the regulation needed to store beams in the IUCF Cooler with very low momentum spreads (Δp/p approx. = 2 x 10 -5 ). An overview of the main high voltage power supply (HVPS) specifications and design, as well as provisions and plans to improve the regulation are discussed. The electron collection system, modeled after the FNAL collector which was able to collect between 99.9% and 99.99% of the electron beam, is discussed along with the requirements of the associated power supplies. The designs of the high voltage acceleration structures and high voltage platform are discussed, as well as practical design considerations based upon experience with the Fermilab 120 keV electron cooling system

A high-voltage triggered pseudospark discharge experiment

International Nuclear Information System (INIS)

Ramaswamy, K.; Destler, W.W.; Rodgers, J.

1996-01-01

The design and execution of a pulsed high-voltage (350 endash 400 keV) triggered pseudospark discharge experiment is reported. Experimental studies were carried out to obtain an optimal design for stable and reliable pseudospark operation in a high-voltage regime (approx-gt 350 kV). Experiments were performed to determine the most suitable fill gas for electron-beam formation. The pseudospark discharge is initiated by a trigger mechanism involving a flashover between the trigger electrode and hollow cathode housing. Experimental results characterizing the electron-beam energy using the range-energy method are reported. Source size imaging was carried out using an x-ray pinhole camera and a novel technique using Mylar as a witness plate. It was experimentally determined that strong pinching occurred later in time and was associated with the lower-energy electrons. copyright 1996 American Institute of Physics

High figure-of-merit SOI power LDMOS for power integrated circuits

Directory of Open Access Journals (Sweden)

Yashvir Singh

2015-06-01

Full Text Available The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

Constant potential high-voltage generator

International Nuclear Information System (INIS)

Resnick, T.A.; Dupuis, W.A.; Palermo, T.

1980-01-01

An X-ray tube voltage generator with automatic stabilization circuitry is disclosed. The generator includes a source of pulsating direct current voltage such as from a rectified 3 phase transformer. This pulsating voltage is supplied to the cathode and anode of an X-ray tube and forms an accelerating potential for electrons within that tube. The accelerating potential is stabilized with a feedback signal which is provided by a feedback network. The network includes an error signal generator which compares an instantaneous accelerating potential with a preferred reference accelerating potential and generates an error function. This error function is transmitted to a control tube grid which in turn causes the voltage difference between X-ray tube cathode and anode to stabilize and thereby reduce the error function. In this way stabilized accelerating potentials are realized and uniform X-ray energy distributions produced. (Auth.)

30 CFR 57.12071 - Movement or operation of equipment near high-voltage powerlines.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Movement or operation of equipment near high-voltage powerlines. 57.12071 Section 57.12071 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION...-voltage powerlines. When equipment must be moved or operated near energized high-voltage powerlines (other...

An Inexpensive Source of High Voltage

Science.gov (United States)

Saraiva, Carlos

2012-01-01

As a physics teacher I like recycling old apparatus and using them for demonstrations in my classes. In physics laboratories in schools, sources of high voltage include induction coils or electronic systems that can be bought from companies that sell lab equipment. But these sources can be very expensive. In this article, I will explain how you…

Tentative type test of a non-invasive high-voltage meter with respect to the quantity of practical peak voltage

International Nuclear Information System (INIS)

Peixoto, J.G.P.; Selbach, H.J.; Kramer, H.M.; Lange, B.

2001-04-01

In Working Group 3 of Sub-committee 62C of the international electrotechnical commission (IEC) a new project is underway [1] with the objective of specifying requirements for the performance characteristics of instruments for the non-invasive measurement of the X-ray tube voltage in diagnostic radiology. In this draft the X-ray tube voltage is specified in terms of the practical peak voltage [2]. The objective of the present work is to perform a tentative type test, based on the ''Requirements for Instruments for Non-invasive Measurements of the X-ray Tube Voltage'' defined in the IEC draft, with a commercially available non-invasive high-voltage meter. The instrument was modified so that the practical peak voltage can be measured. It is shown that the instrument, with the modifications made, is suitable for the non-invasive measurement of the practical peak voltage between 50 kV and 150 kV within the required limits of variation of the response. (orig.)

Two types of photomultiplier voltage dividers for high and changing count rates

International Nuclear Information System (INIS)

Reiter, W.L.; Stengl, G.

1980-01-01

We report on the design of two types of voltage distribution circuits for high stability photomultiplier operation. 'Type A' voltage divider is an ohmic voltage divider with high bleeder current (up to 10 mA) and the resistor chain split at one of the last dynodes, usually the dynode where the analog signal is derived from. This simple constructive measure improves the stability of the dynode voltage by a factor of 5 compared with an unsplit conventional resistor chain. 'Type B' is a novel active voltage divider using cold cathode tubes ar regulating elements. This voltage divider exhibits excellent temperature stability (about 10 -4 / 0 C). With 'type B' an equal stability compared with conventional ohmic dividers can be achieved at a bleeder current smaller by one order of magnitude. Of course both concepts, 'type A' and 'type B', can be combined. (orig.)

Preventing Raman Lasing in High-Q WGM Resonators

Science.gov (United States)

Savchenkov, Anatoliy; Matsko, Andrey; Strekalov, Dmitry; Maleki, Lute

2007-01-01

A generic design has been conceived to suppress the Raman effect in whispering- gallery-mode (WGM) optical resonators that have high values of the resonance quality factor (Q). Although it is possible to exploit the Raman effect (even striving to maximize the Raman gain to obtain Raman lasing), the present innovation is intended to satisfy a need that arises in applications in which the Raman effect inhibits the realization of the full potential of WGM resonators as frequency-selection components. Heretofore, in such applications, it has been necessary to operate high-Q WGM resonators at unattractively low power levels to prevent Raman lasing. (The Raman-lasing thresholds of WGM optical resonators are very low and are approximately proportional to Q(sup -2)). Heretofore, two ways of preventing Raman lasting at high power levels have been known, but both entail significant disadvantages: A resonator can be designed so that the optical field is spread over a relatively large mode volume to bring the power density below the threshold. For any given combination of Q and power level, there is certain mode volume wherein Raman lasing does not start. Unfortunately, a resonator that has a large mode volume also has a high spectral density, which is undesirable in a typical photonic application. A resonator can be cooled to the temperature of liquid helium, where the Raman spectrum is narrower and, therefore, the Raman gain is lower. However, liquid-helium cooling is inconvenient. The present design overcomes these disadvantages, making it possible to operate a low-spectral-density (even a single-mode) WGM resonator at a relatively high power level at room temperature, without risk of Raman lasing.

Determining the mode of high voltage breakdowns in vacuum devices

International Nuclear Information System (INIS)

Miller, H.C.; Furno, E.J.; Sturtz, J.P.

1980-01-01

Devices were constructed which were essentially vacuum diodes equipped with windows allowing observation of high voltage breakdowns. The waveform of the applied voltage was photographed, and the x-ray output was monitored to investigate electrical breakdown in these vacuum diodes. Results indicate that breakdowns may be divided into two types: (1) vacuum (interelectrode) breakdown - characterized by a diffuse moderately bright discharge, a relative slow and smooth voltage collapse, and a large burst of x-rays, and (2) surface (insulator) flashover - characterized by a bright discharge with a very bright filamentary core, a relatively fast and noisy voltage collapse and no x-ray burst. Useful information concerning the type of breakdown in a vacuum device can be obtained by monitoring the voltage (current) waveform and the x-ray output

Cermet insert high voltage holdoff for ceramic/metal vacuum devices

Science.gov (United States)

Ierna, William F.

1987-01-01

An improved metal-to-ceramic seal is provided wherein the ceramic body of the seal contains an integral region of cermet material in electrical contact with the metallic member, e.g., an electrode, of the seal. The seal is useful in high voltage vacuum devices, e.g., vacuum switches, and increases the high-voltage holdoff capabilities of such devices. A method of fabricating such seals is also provided.

High-voltage integrated transmitting circuit with differential driving for CMUTs

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

2016-01-01

In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

A high voltage gain quasi Z-source isolated DC/DC converter

DEFF Research Database (Denmark)

Siwakoti, Yam P.; Blaabjerg, Frede; Loh, Poh Chiang

2014-01-01

A compact quasi-Z-source DC/DC converter is presented with high voltage gain, isolated output, and improved efficiency. The improvements in size and performance were achieved by using a square wave inverter with only two output switches driving an isolating transformer in push-pull mode, followed...... by a voltage doubling output rectifier. The converter is well-suited to applications requiring a high voltage gain, especially renewable energy sources such as photovoltaic and fuel-cell power supplies. To demonstrate the converter's performance a prototype designed to output 400 V at 500 W was constructed...

Electronic Current Transducer (ECT) for high voltage dc lines

Science.gov (United States)

Houston, J. M.; Peters, P. H., Jr.; Summerayes, H. R., Jr.; Carlson, G. J.; Itani, A. M.

1980-02-01

The development of a bipolar electronic current transducer (ECT) for measuring the current in a high voltage dc (HVDC) power line at line potential is discussed. The design and construction of a free standing ECT for use on a 400 kV line having a nominal line current of 2000 A is described. Line current is measured by a 0.0001 ohm shunt whose voltage output is sampled by a 14 bit digital data link. The high voltage interface between line and ground is traversed by optical fibers which carry digital light signals as far as 300 m to a control room where the digital signal is converted back to an analog representation of the shunt voltage. Two redundant electronic and optical data links are used in the prototype. Power to operate digital and optical electronics and temperature controlling heaters at the line is supplied by a resistively and capacitively graded 10 stage cascade of ferrite core transformers located inside the hollow, SF6 filled, porcelain support insulator. The cascade is driven by a silicon controlled rectifier inverter which supplies about 100 W of power at 30 kHz.

The effect of gate length on SOI-MOSFETS operation | Baedi ...

African Journals Online (AJOL)

The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

BANSHEE: High-voltage repetitively pulsed electron-beam driver

International Nuclear Information System (INIS)

VanHaaften, F.

1992-01-01

BANSHEE (Beam Accelerator for a New Source of High-Energy Electrons) this is a high-voltage modulator is used to produce a high-current relativistic electron beam for high-power microwave tube development. The goal of the BANSHEE research is first to achieve a voltage pulse of 700--750 kV with a 1-μs pulse width driving a load of ∼100 Ω, the pulse repetition frequency (PRF) of a few hertz. The ensuing goal is to increase the pulse amplitude to a level approaching 1 MV. We conducted tests using half the modulator with an output load of 200 Ω, up to a level of ∼650 kV at a PRF of 1 Hz and 525 kV at a PRF of 5 Hz. We then conducted additional testing using the complete system driving a load of ∼100 Ω

High-voltage nanosecond Marx generator with quasi-rectangular pulses

International Nuclear Information System (INIS)

Bulan, V.V.; Grabovskij, E.V.; Gribov, A.N.; Luzhnov, V.G.

1999-01-01

The automated high-voltage nanosecond generator, forming single pulses of any polarity on the load of 17 Ohm with polarity voltage from 100 up to 300 kV at the semiheight of 80 ns and the front of 7 ns is described. The generator is assembled on the basis of low-inductive capacitors, which by discharge form the pulse, close by form to rectangular one [ru

Switching phenomena in high-voltage circuit breakers

International Nuclear Information System (INIS)

Nakanishi, K.

1991-01-01

The topics covered in this book include: general problems concerning current interruption, the physical arc model, and miscellaneous types of modern switching apparatus, such as gas circuit breakers, gas-insulated switch-gear, vacuum circuit breakers and high-voltage direct-current circuit breakers

High voltage high brightness electron accelerator with MITL voltage adder coupled to foilless diode

International Nuclear Information System (INIS)

Mazarakis, M.G.; Poulkey, J.W.; Rovang, D.

1995-01-01

The design and analysis of a high brightness electron beam experiment under construction at Sandia National Laboratory is presented. The beam energy is 12 MeV, the current 35-40 kA, the rms radius 0.5 mm, and the pulse duration FWHM 40 ns. The accelerator is SABRE a pulsed inductive voltage adder, and the electron source is a magnetically immersed foilless diode. This experiment has as its goal to stretch the technology to the edge and produce the highest possible electron current in a submillimeter radius beam

Atypical Exit Wound in High-Voltage Electrocution.

Science.gov (United States)

Parakkattil, Jamshid; Kandasamy, Shanmugam; Das, Siddhartha; Devnath, Gerard Pradeep; Chaudhari, Vinod Ashok; Shaha, Kusa Kumar

2017-12-01

Electrocution fatality cases are difficult to investigate. High-voltage electrocution burns resemble burns caused by other sources, especially if the person survives for few days. In that case, circumstantial evidence if correlated with the autopsy findings helps in determining the cause and manner of death. In addition, the crime scene findings also help to explain the pattern of injuries observed at autopsy. A farmer came in contact with a high-voltage transmission wire and sustained superficial to deep burns over his body. A charred and deeply scorched area was seen over the face, which was suggestive of the electric entry wound. The exit wound was present over both feet and lower leg and was atypical in the form of a burnt area of peeled blistered skin, charring, and deep scorching. The injuries were correlated with crime scene findings, and the circumstances that lead to his electrocution are discussed here.

High voltage isolation transformer

Science.gov (United States)

Clatterbuck, C. H.; Ruitberg, A. P. (Inventor)

1985-01-01

A high voltage isolation transformer is provided with primary and secondary coils separated by discrete electrostatic shields from the surfaces of insulating spools on which the coils are wound. The electrostatic shields are formed by coatings of a compound with a low electrical conductivity which completely encase the coils and adhere to the surfaces of the insulating spools adjacent to the coils. Coatings of the compound also line axial bores of the spools, thereby forming electrostatic shields separating the spools from legs of a ferromagnetic core extending through the bores. The transformer is able to isolate a high constant potential applied to one of its coils, without the occurrence of sparking or corona, by coupling the coatings, lining the axial bores to the ferromagnetic core and by coupling one terminal of each coil to the respective coating encasing the coil.

The Investigation of Field Plate Design in 500 V High Voltage NLDMOS

Directory of Open Access Journals (Sweden)

Donghua Liu

2015-01-01

Full Text Available This paper presents a 500 V high voltage NLDMOS with breakdown voltage (VBD improved by field plate technology. Effect of metal field plate (MFP and polysilicon field plate (PFP on breakdown voltage improvement of high voltage NLDMOS is studied. The coeffect of MFP and PFP on drain side has also been investigated. A 500 V NLDMOS is demonstrated with a 37 μm drift length and optimized MFP and PFP design. Finally the breakdown voltage 590 V and excellent on-resistance performance (Rsp = 7.88 ohm * mm2 are achieved.

Prototype high voltage bushing: Configuration to its operational demonstration

Energy Technology Data Exchange (ETDEWEB)

Shah, Sejal, E-mail: sshah@iter-india.org [ITER-India, Institute for Plasma Research, Bhat, Gandhinagar 382428 (India); Sharma, D. [Institute for Plasma Research, Bhat, Gandhinagar 382428 (India); Parmar, D.; Tyagi, H.; Joshi, K.; Shishangiya, H.; Bandyopadhyay, M.; Rotti, C.; Chakraborty, A. [ITER-India, Institute for Plasma Research, Bhat, Gandhinagar 382428 (India)

2016-12-15

High Voltage Bushing (HVB) is the key component of Diagnostic Neutral Beam (DNB) system of ITER as it provides access to high voltage electrical, hydraulic, gas and diagnostic feedlines to the beam source with isolation from grounded vessel. HVB also provides primary vacuum confinement for the DNB system. Being Safety Important Class (SIC) component of ITER, it involves several configurational, technological and operational challenges. To ensure its operational performance & reliability, particularly electrostatic behavior, half scale down Prototype High Voltage Bushing (PHVB) is designed considering same design criteria of DNB HVB. Design optimization has been carried out followed by finite element (FE) analysis to obtain DNB HVB equivalent electric stress on different parts of PHVB, taking into account all design, manufacturing & space constraints. PHVB was tested up to 60 kV without breakdown, which validates its design for the envisaged operation of 50 kV DC. This paper presents the design of PHVB, FEA validation, manufacturing constraints, experimental layout with interfacing auxiliary systems and operational results related to functional performance.

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

Science.gov (United States)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

AC transmission, with very high voltages and the 750 kV line

Energy Technology Data Exchange (ETDEWEB)

Bocker, H

1964-01-01

The economic case for adoption of extra-high voltages for transmitting electric power over distances of the order of 1000 km is discussed. Some special technical developments for solving the problems attached to such high voltages are briefly discussed, particularly in the fields of switching and transients suppression. The first 750-kV projects in Canada and Russia are mentioned. Equipment, e.g., bushings, transformers, etc., operating at such voltages are illustrated.

High-voltage pulsed generator for dynamic fragmentation of rocks.

Science.gov (United States)

Kovalchuk, B M; Kharlov, A V; Vizir, V A; Kumpyak, V V; Zorin, V B; Kiselev, V N

2010-10-01

A portable high-voltage (HV) pulsed generator has been designed for rock fragmentation experiments. The generator can be used also for other technological applications. The installation consists of low voltage block, HV block, coaxial transmission line, fragmentation chamber, and control system block. Low voltage block of the generator, consisting of a primary capacitor bank (300 μF) and a thyristor switch, stores pulse energy and transfers it to the HV block. The primary capacitor bank stores energy of 600 J at the maximum charging voltage of 2 kV. HV block includes HV pulsed step up transformer, HV capacitive storage, and two electrode gas switch. The following technical parameters of the generator were achieved: output voltage up to 300 kV, voltage rise time of ∼50 ns, current amplitude of ∼6 kA with the 40 Ω active load, and ∼20 kA in a rock fragmentation regime (with discharge in a rock-water mixture). Typical operation regime is a burst of 1000 pulses with a frequency of 10 Hz. The operation process can be controlled within a wide range of parameters. The entire installation (generator, transmission line, treatment chamber, and measuring probes) is designed like a continuous Faraday's cage (complete shielding) to exclude external electromagnetic perturbations.

High-voltage pulsed generator for dynamic fragmentation of rocks

Science.gov (United States)

Kovalchuk, B. M.; Kharlov, A. V.; Vizir, V. A.; Kumpyak, V. V.; Zorin, V. B.; Kiselev, V. N.

2010-10-01

A portable high-voltage (HV) pulsed generator has been designed for rock fragmentation experiments. The generator can be used also for other technological applications. The installation consists of low voltage block, HV block, coaxial transmission line, fragmentation chamber, and control system block. Low voltage block of the generator, consisting of a primary capacitor bank (300 μF) and a thyristor switch, stores pulse energy and transfers it to the HV block. The primary capacitor bank stores energy of 600 J at the maximum charging voltage of 2 kV. HV block includes HV pulsed step up transformer, HV capacitive storage, and two electrode gas switch. The following technical parameters of the generator were achieved: output voltage up to 300 kV, voltage rise time of ˜50 ns, current amplitude of ˜6 kA with the 40 Ω active load, and ˜20 kA in a rock fragmentation regime (with discharge in a rock-water mixture). Typical operation regime is a burst of 1000 pulses with a frequency of 10 Hz. The operation process can be controlled within a wide range of parameters. The entire installation (generator, transmission line, treatment chamber, and measuring probes) is designed like a continuous Faraday's cage (complete shielding) to exclude external electromagnetic perturbations.

The electric strength of high-voltage transformers insulation at effect of partial dischargers

International Nuclear Information System (INIS)

Khoshravan, E.; Zeraatparvar, A.; Gashimov, A.M.; Mehdizadeh, R.N.

2001-01-01

Full text : In paper the change of electric strength of high-voltage transformers insulation at the effect of partial discharges with space charge accumulation was investigated. It is revealed that the effect of partial discharges of insulation materials results the reduction of their pulsing electric strength which can restore the own initial value at releasing of saved charge the volume of a material under condition of absence the ineversible structural changes in it. Researches of high-voltage transformers insulation's non-failure operation conditions show, that at increasing of insulation work time in a strong electrical field the reduction of average breakdown voltages with simultaneous increasing of spread in discharge voltage values takes place. It authentically testifies to reduction of short-time discharge voltage of insulation materials during their electrical aging. As the basic reason of insulation electrical aging the partial discharges occurring in gas cavities inside insulation were considered. It is known that the space charges will be formed in insulation elements of high-voltage devices which effects in dielectrical property of these elements including the electric strength and the space charge formation can occur also at partial discharges in an alternating voltage while the service of high-voltage transformers. In the given work the experiments in revealing separate influence partial discharges in pulsing electric strength of insulation materials at presence and at absence inside them the space charge were spent

Multi-Port High Voltage Gain Modular Power Converter for Offshore Wind Farms

Directory of Open Access Journals (Sweden)

Sen Song

2018-06-01

Full Text Available In high voltage direct current (HVDC power transmission of offshore wind power systems, DC/DC converters are applied to transfer power from wind generators to HVDC terminals, and they play a crucial role in providing a high voltage gain, high efficiency, and high fault tolerance. This paper introduces an innovative multi-port DC/DC converter with multiple modules connected in a scalable matrix configuration, presenting an ultra-high voltage step-up ratio and low voltage/current rating of components simultaneously. Additionally, thanks to the adoption of active clamping current-fed push–pull (CFPP converters as sub-modules (SMs, soft-switching is obtained for all power switches, and the currents of series-connected CFPP converters are auto-balanced, which significantly reduce switching losses and control complexity. Furthermore, owing to the expandable matrix structure, the output voltage and power of a modular converter can be controlled by those of a single SM, or by adjusting the column and row numbers of the matrix. High control flexibility improves fault tolerance. Moreover, due to the flexible control, the proposed converter can transfer power directly from multiple ports to HVDC terminals without bus cable. In this paper, the design of the proposed converter is introduced, and its functions are illustrated by simulation results.

Energy harvesting in high voltage measuring techniques

International Nuclear Information System (INIS)

Żyłka, Pawel; Doliński, Marcin

2016-01-01

The paper discusses selected problems related to application of energy harvesting (that is, generating electricity from surplus energy present in the environment) to supply autonomous ultra-low-power measurement systems applicable in high voltage engineering. As a practical example of such implementation a laboratory model of a remote temperature sensor is presented, which is self-powered by heat generated in a current-carrying busbar in HV- switchgear. Presented system exploits a thermoelectric harvester based on a passively cooled Peltier module supplying micro-power low-voltage dc-dc converter driving energy-efficient temperature sensor, microcontroller and a fibre-optic transmitter. Performance of the model in laboratory simulated conditions are presented and discussed. (paper)

Theoretical investigation of a photoconductively switched high-voltage spark gap

NARCIS (Netherlands)

Broks, B.H.P.; Hendriks, J.; Brok, W.J.M.; Brussaard, G.J.H.; Mullen, van der J.J.A.M.

2006-01-01

In this contribution, a photoconductively switched high-voltage spark gap with an emphasis on theswitching behavior is modeled. It is known experimentally that not all of the voltage that is present at the input of the spark gap is switched, but rather a fraction of it drops across the spark gap.

30 CFR 75.812-2 - High-voltage power centers and transformers; record of examination.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage power centers and transformers; record of examination. 75.812-2 Section 75.812-2 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... High-Voltage Distribution § 75.812-2 High-voltage power centers and transformers; record of examination...

Summary of transient high-voltage calculations for the FRX-C experiment

International Nuclear Information System (INIS)

Kewish, R.W. Jr.; Rej, D.J.

1982-06-01

Calculations of the electrical circuit equations are performed over a wide range of parameters corresponding to the FRX-C field-reversed THETA-pinch experiment at Los Alamos. Without any plasma or external damping, serious voltage doubling and quadrupling of the main capacitor bank charge voltage are observed. These oscillating high voltages are found to be adequately suppressed by the strategic placement of external snubber circuitry. On the other hand, no doubling of the THETA-pinch preionization bank charge voltage is found. Calculations of the equations for the z-pinch preionization circuit are also performed

High voltage pulse system for the streamer chamber supply of the GIBS spectrometer

International Nuclear Information System (INIS)

Aksinenko, V.D.; Glagoleva, N.S.; Dement'ev, E.A.; Kaminskij, N.I.; Matyushin, A.T.; Matyushin, V.T.; Rozhnyatovskaya, S.A.; Ryakhovskij, V.N.; Nurgozhin, N.N.; Khusainov, E.K.

1987-01-01

Results of development and testing of high voltage pulse system HVPS for the streamer chamber supply of the GIBS spectrometer are presented. HVPS consists of the following basic blocks: nanosecond pulse high voltage generator, high voltage charging supply, trigger generator, chamber parameter control devices, gas-oil vacuuming supply systems, auxiliary and fire-prevention devices. The system blocks are described. Experimental results of HVPC testing are presented. HVPC provides a reliable (10 5 operations) of streamer chamber supply with high voltage pulse parameters: amplitude - 500 kV, amplitude instability (0.5-1.5)%, pulse duration - 12 ns, delay time - 500 ns, delay instability (2.5-5)%, mean frequency of output a signals - 0.1 Hz

Design of high voltage power supply of miniature X-ray tube based on resonant Royer

International Nuclear Information System (INIS)

Liu Xiyao; Zeng Guoqiang; Tan Chengjun; Luo Qun; Gong Chunhui; Huang Rui

2013-01-01

Background: In recent years, X rays are widely used in various fields. With the rapid development of national economy, the demand of high quality, high reliability, and high stability miniature X-ray tube has grown rapidly. As an important core component of miniature X-ray tube, high voltage power supply has attracted wide attention. Purpose: To match miniature, the high voltage power supply should be small, lightweight, good quality, etc. Based on the basic performance requirements of existing micro-X-ray tube high voltage power supply, this paper designs an output from 0 to -30 kV adjustable miniature X-ray tube voltage DC power supply. Compared to half-bridge and full-bridge switching-mode power supply, its driving circuit is simple. With working on the linear condition, it has no switching noise. Methods: The main circuit makes use of DC power supply to provide the energy. The resonant Royer circuit supplies sine wave which drives to the high frequency transformer's primary winding with resultant sine-like high voltage appearing across the secondary winding. Then, the voltage doubling rectifying circuit would achieve further boost. In the regulator circuit, a feedback control resonant transistor base current is adopted. In order to insulate air, a silicone rubber is used for high pressure part packaging, and the output voltage is measured by the dividing voltage below -5 kV. Results: The stability of circuit is better than 0.2%/6 h and the percent of the output ripple voltage is less than 0.3%. Keeping the output voltage constant, the output current can reach 57 μA by changing the size of load resistor. This high voltage power supply based on resonant Royer can meet the requirement of miniature X-ray tube. Conclusions: The circuit can satisfy low noise, low ripple, low power and high voltage regulator power supply design. However, its efficiency is not high enough because of the linear condition. In the next design, to further reduce power consumption, we