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Sample records for voltage high-q soi

  1. Low Voltage, High-Q SOI MEMS Varactors for RF Applications

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Jensen, Søren; Hansen, Ole

    2003-01-01

    A micro electromechanical tunable capacitor with a low control voltage, a wide tuning range and high electrical quality factor is presented with detailed characterizations. A 50μm thick single-crystalline silicon layer was etched using deep reactive ion etching (DRIE) for obtaining high-aspect ra...... is a suitable passive component to be used in band-pass filtering, voltage controlled oscillator or impedance matching applications on the very high frequency(VHF) and ultra high frequency (UHF) bands....

  2. Digitally Programmable High-Q Voltage Mode Universal Filter

    Directory of Open Access Journals (Sweden)

    D. Singh

    2013-12-01

    Full Text Available A new low-voltage low-power CMOS current feedback amplifier (CFA is presented in this paper. This is used to realize a novel digitally programmable CFA (DPCFA using transistor arrays and MOS switches. The proposed realizations nearly allow rail-to-rail swing capability at all the ports. Class-AB output stage ensures low power dissipation and high current drive capability. The proposed CFA/ DPCFA operates at supply voltage of ±0.75 V and exhibits bandwidth better than 95 MHz. An application of the DPCFA to realize a novel voltage mode high-Q digitally programmable universal filter (UF is given. Performances of all the proposed circuits are verified by PSPICE simulation using TSMC 0.25μm technology parameters.

  3. A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer

    International Nuclear Information System (INIS)

    Wu Lijuan; Zhang Wentong; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer (FBL) and its analytical model is analyzed in this paper. The surface heavily doped p-top layers, interface floating buried N + /P + layers, and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance. On the condition of ESIMOX (epoxy separated by implanted oxygen), it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from −232 V of the conventional SOI to −425 V and the specific resistance R on,sp is reduced from 0.88 to 0.2424 Ω·cm 2 . (semiconductor devices)

  4. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    : off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

  5. Process optimization of a deep trench isolation structure for high voltage SOI devices

    International Nuclear Information System (INIS)

    Zhu Kuiying; Qian Qinsong; Zhu Jing; Sun Weifeng

    2010-01-01

    The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

  6. A new SOI high-voltage device with a step-thickness drift region and its analytical model for the electric field and breakdown voltage

    International Nuclear Information System (INIS)

    Luo Xiaorong; Zhang Wei; Zhang Bo; Li Zhaoji; Yang Shouguo; Zhan Zhan; Fu Daping

    2008-01-01

    A new SOI high-voltage device with a step-thickness drift region (ST SOI) and its analytical model for the two-dimension electric field distribution and the breakdown voltage are proposed. The electric field in the drift region is modulated and that of the buried layer is enhanced by the variable thickness SOI layer, thereby resulting in the enhancement of the breakdown voltage. Based on the Poisson equation, the expression for the two-dimension electric field distribution is presented taking the modulation effect into account, from which the RESURF (REduced SURface Field) condition and the approximate but explicit expression for the maximal breakdown voltage are derived. The analytical model can explain the effects of the device parameters, such as the step height and the step length of the SOI layer, the doping concentration and the buried oxide thickness, on the electric field distribution and the breakdown voltage. The validity of this model is demonstrated by a comparison with numerical simulations. Improvement on both the breakdown voltage and the on-resistance (R on ) for the ST SOI is obtained due to the variable thickness SOI layer

  7. Universal trench design method for a high-voltage SOI trench LDMOS

    Institute of Scientific and Technical Information of China (English)

    Hu Xiarong; Zhang Bo; Luo Xiaorong; Li Zhaoji

    2012-01-01

    The design method for a high-voltage SOl trench LDMOS for various trench permittivities,widths and depths is introduced.A universal method for efficient design is presented for the first time,taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account.The high-k (relative permittivity)dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench.An SOI LDMOS with a vacuum trench in the drift region is also discussed.Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

  8. Improving breakdown voltage performance of SOI power device with folded drift region

    Science.gov (United States)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  9. A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

    International Nuclear Information System (INIS)

    Jamali Mahabadi, S E; Orouji, Ali A; Keshavarzi, P; Moghadam, Hamid Amini

    2011-01-01

    In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that the BV of double step partial silicon on insulator is nearly 69% higher and alleviates SHEs 17% in comparison with its single step partial SOI counterpart and nearly 265% higher and alleviate SHEs 18% in comparison with its conventional SOI counterpart

  10. A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

    Science.gov (United States)

    Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

    2007-06-01

    A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode

  11. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    Science.gov (United States)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  12. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    International Nuclear Information System (INIS)

    Zhang Jun; Guo Yu-Feng; Xu Yue; Lin Hong; Yang Hui; Hong Yang; Yao Jia-Fei

    2015-01-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. (paper)

  13. Development of a broadband reflective T-filter for voltage biasing high-Q superconducting microwave cavities

    International Nuclear Information System (INIS)

    Hao, Yu; Rouxinol, Francisco; LaHaye, M. D.

    2014-01-01

    We present the design of a reflective stop-band filter based on quasi-lumped elements that can be utilized to introduce large dc and low-frequency voltage biases into a low-loss superconducting coplanar waveguide (CPW) cavity. Transmission measurements of the filter are seen to be in good agreement with simulations and demonstrate insertion losses greater than 20 dB in the range of 3–10 GHz. Moreover, transmission measurements of the CPW's fundamental mode demonstrate that loaded quality factors exceeding 10 5 can be achieved with this design for dc voltages as large as 20 V and for the cavity operated in the single-photon regime. This makes the design suitable for use in a number of applications including qubit-coupled mechanical systems and circuit QED

  14. A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

    Science.gov (United States)

    Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

    2016-12-01

    The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

  15. A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

    International Nuclear Information System (INIS)

    Fu Qiang; Zhang Wan-Rong; Jin Dong-Yue; Zhao Yan-Xiao; Wang Xiao

    2016-01-01

    The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness ( T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer

  16. Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6 - 1 V)

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Musseau, O.; Leray, J.L.; Faynot, O.; Raynaud, C.; Pelloie, J.L.

    1999-01-01

    In this paper, we presented two DTMOS architectures processed with a partially depleted SOI technology. The first architecture, DTMOS without limiting transistor, is dedicated to ultra-low voltage applications, at 0.6 V. For 1V applications, the second architecture, DTMOS with limiting transistor, needs an additional transistor to limit the body-source diode current. The total dose irradiation of both DTMOS architectures induces no change of the drain current, but an increase of the body-source diode current. Total dose induced trapped charge in the buried oxide increases the body potential of the DTMOS transistor. It induces an increase of the current flow at the back interface of the silicon film. Irradiation of complex circuits using DTMOS transistors would lead to a degradation of the stand-by consumption. (authors)

  17. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Science.gov (United States)

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  18. An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Saramekala, G. K.; Santra, Abirmoya; Dubey, Sarvesh; Jit, Satyabrata; Tiwari, Pramod Kumar

    2013-08-01

    In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

  19. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    Science.gov (United States)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  20. A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications

    Directory of Open Access Journals (Sweden)

    Jader A. De Lima

    2002-01-01

    Full Text Available A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 μm single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm2. Measured resolution of encoding parameter α is better than 10% at 6 MHz and VDD = 3.3 V. Idle-mode consumption is 340 μW. Pulses of frequencies up to15 MHz and α =10% can be discriminated for 2.3 V ≤ VDD ≤ 3.3 V. Such an excellent immunity to VDD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

  1. High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

    International Nuclear Information System (INIS)

    Caër, Charles; Le Roux, Xavier; Cassan, Eric

    2013-01-01

    We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

  2. Characterization of SOI monolithic detector system

    Science.gov (United States)

    Álvarez-Rengifo, P. L.; Soung Yee, L.; Martin, E.; Cortina, E.; Ferrer, C.

    2013-12-01

    A monolithic active pixel sensor for charged particle tracking was developed. This research is performed within the framework of an R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology) whose aim is to evaluate the feasibility of developing a Monolithic Active Pixel Sensor (MAPS) with Silicon-on-Insulator (SOI) technology. Two chips were fabricated: TRAPPISTe-1 and TRAPPISTe-2. TRAPPISTe-1 was produced at the WINFAB facility at the Université catholique de Louvain (UCL), Belgium, in a 2 μm fully depleted (FD-SOI) CMOS process. TRAPPISTe-2 was fabricated with the LAPIS 0.2 μm FD-SOI CMOS process. The electrical characterization on single transistor test structures and of the electronic readout for the TRAPPISTe series of monolithic pixel detectors was carried out. The behavior of the prototypes’ electronics as a function of the back voltage was studied. Results showed that both readout circuits exhibited sensitivity to the back voltage. Despite this unwanted secondary effect, the responses of TRAPPISTe-2 amplifiers can be improved by a variation in the circuit parameters.

  3. An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2016-10-01

    This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

  4. Group Delay of High Q Antennas

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Pedersen, Gert Frølund

    2013-01-01

    Group Delay variations versus frequency is an essential factor which can cause distortion and degradation in the signals. Usually this is an issue in wideband communication systems, such as satellite communication systems, which are used for transmitting wideband data. However, group delay can also...... become an issue, when working with high Q antennas, because of the steep phase shift over the frequency. In this paper, it is measured how large group delay variations can become, when going from a low Q antenna to a high Q antenna. The group delay of a low Q antenna is shown to be around 1.3 ns, whereas...... a high Q antenna has group delay of around 22 ns. It is due to this huge group delay variation characteristics of high Q antennas, that signal distortion might occur in the radio system with high Q antennas....

  5. An SEU resistant 256K SOI SRAM

    Science.gov (United States)

    Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

    1992-12-01

    A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

  6. Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

    Science.gov (United States)

    Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

    2018-02-01

    In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

  7. Worst-Case Bias During Total Dose Irradiation of SOI Transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

    2000-01-01

    The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

  8. SOI technology for power management in automotive and industrial applications

    Science.gov (United States)

    Stork, Johannes M. C.; Hosey, George P.

    2017-02-01

    Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

  9. Research on SOI-based micro-resonator devices

    Science.gov (United States)

    Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

    2010-10-01

    SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

  10. Thermal Loss in High-Q Antennas

    DEFF Research Database (Denmark)

    Barrio, Samantha Caporal Del; Bahramzy, Pevand; Svendsen, Simon

    2014-01-01

    Tunable antennas are very promising for future generations of mobile communications, where antennas are required to cover a wide range operating bands. This letter aims at characterizing the loss mechanism of tunable antennas. Tunable antennas typically exhibit a high Quality factor (Q), which ca...... lead to thermal loss due to the conductivity of the metal. The investigation shows that copper loss is non-negligible for high Q values. In the proposed design the copper loss is 2 dB, for a Q of 260 at 700 MHz....

  11. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    Science.gov (United States)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  12. FinFET and UTBB for RF SOI communication systems

    Science.gov (United States)

    Raskin, Jean-Pierre

    2016-11-01

    Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

  13. A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

    2016-07-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

  14. A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

    2015-10-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

  15. A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

    Science.gov (United States)

    Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

    The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

  16. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

    Science.gov (United States)

    Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

    2016-11-01

    This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

  17. Detuning effect study of High-Q Mobile Phone Antennas

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Pedersen, Gert F.

    2015-01-01

    Number of frequency bands that have to be covered by smart phones, are ever increasing. This broadband coverage can be obtained either by using a low-Q antenna or a high-Q tunable antenna. This study investigates high-Q antennas performance when placed in proximity of the user. This study...

  18. Method to improve commercial bonded SOI material

    Science.gov (United States)

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  19. A MEMS SOI-based piezoresistive fluid flow sensor

    Science.gov (United States)

    Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

    2018-02-01

    In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

  20. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    Science.gov (United States)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  1. HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

    Science.gov (United States)

    Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

    2000-08-01

    Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

  2. A graphene spin diode based on Rashba SOI

    International Nuclear Information System (INIS)

    Mohammadpour, Hakimeh

    2015-01-01

    In this paper a graphene-based two-terminal electronic device is modeled for application in spintronics. It is based on a gapped armchair graphene nanoribbon (GNR). The electron transport is considered through a scattering or channel region which is sandwiched between two lateral semi-infinite ferromagnetic leads. The two ferromagnetic leads, being half-metallic, are supposed to be in either parallel or anti-parallel magnetization. Meanwhile, the central channel region is a normal layer under the influence of the Rashba SOI, induced e.g., by the substrate. The device operation is based on modulating the (spin-) current by tuning the strength of the RSOI. The resultant current, being spin-polarized, is controlled by the RSOI in mutual interplay with the channel length. Inverting alternating bias voltage to a fully rectified spin-current is the main achievement of this paper. - Highlights: • Graphene-based electronic device is modeled with ferromagnetic leads. • The device operation is based on modulating the (spin-) current by Rashba SOI. • Inverting alternating bias voltage to rectified spin-current is the main achievement

  3. Impact of technology scaling in SOI back-channel total dose tolerance. A 2-D numerical study using a self-consistent oxide code; Effet du facteur d'echelle sur la tolerance en dose de rayonnement dans le cas du courant de fuite arriere des transistors MOS/SOI. Une etude d'un oxyde utilise un code auto coherent en deux dimensions

    Energy Technology Data Exchange (ETDEWEB)

    Leray, J.L.; Paillet, Ph.; Ferlet-Cavrois, V. [CEA Bruyeres le Chatel DRIF, 91 (France); Tavernier, C.; Belhaddad, K. [ISE Integrated System Engineering AG (Switzerland); Penzin, O. [ISE Integrated System Engineering Inc., San Jose (United States)

    1999-07-01

    A new 2-D and 3-D self-consistent code has been developed and is applied to understanding the charge trapping in SOI buried oxide causing back-channel MOS leakage in SOI transistors. Clear indications on scaling trends are obtained with respect to supply voltage and oxide thickness. (authors)

  4. Op-amp gyrator simulates high Q inductor

    Science.gov (United States)

    Sutherland, W. C.

    1977-01-01

    Gyrator circuit consisting of dual operational amplifier and four resistors inverts impedance of capacitor to simulate inductor. Synthetic inductor has high Q factor, good stability, wide bandwidth, and easily determined value of inductance that is independent of frequency. It readily lends itself to integrated-circuit applications, including filter networks.

  5. High-Q Bandpass Comb Filter for Mains Interference Extraction

    Directory of Open Access Journals (Sweden)

    Neycheva T.

    2009-12-01

    Full Text Available This paper presents a simple digital high-Q bandpass comb filter for power-line (PL or other periodical interference extraction. The filter concept relies on a correlated signal average resulting in alternating constructive and destructive spectrum interference i.e. the so-called comb frequency response. The presented filter is evaluated by Matlab simulations with real ECG signal contaminated with low amplitude PL interference. The made simulations show that this filter accurately extract the PL interference. It has high-Q notches only at PL odd harmonics and is appropriate for extraction of any kind of odd harmonic interference including rectangular shape. The filter is suitable for real-time operation with popular low-cost microcontrollers.

  6. High-Q microwave photonic filter with a tuned modulator.

    Science.gov (United States)

    Capmany, J; Mora, J; Ortega, B; Pastor, D

    2005-09-01

    We propose the use of tuned electro-optic or electroabsorption external modulators to implement high-quality (high-Q) factor, single-bandpass photonic filters for microwave signals. Using this approach, we experimentally demonstrate a transversal finite impulse response with a Q factor of 237. This is to our knowledge the highest value ever reported for a passive finite impulse-response microwave photonic filter.

  7. Gate Engineering in SOI LDMOS for Device Reliability

    Directory of Open Access Journals (Sweden)

    Aanand

    2016-01-01

    Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

  8. High-Q microwave resonators with a photonic crystal structure

    International Nuclear Information System (INIS)

    Schuster, M.

    2001-08-01

    The localisation of electromagnetic energy at a defect in a photonic crystal is similar to a well known effect employed to construct high-Q microwave resonators: In a whispering gallery (WHG-) mode resonator the high Q-factor is achieved by localisation of the electromagnetic field energy by total reflection inside a disk made of dielectric material. The topic of this work is to demonstrate, that WHG-like modes can exist in an air defect in a photonic crystal that extends over several lattice periods; and that a high-Q microwave resonator can be made, utilizing these resonant modes. In numerical simulations, the transmission properties of a photonic crystal structure with hexagonal lattice symmetry have been investigated with a transfer-matrix-method. The eigenmodes of a defect structure in a photonic crystal have been calculated with a quasi-3d finite element integration technique. Experimental results confirm the simulated transmission properties and show the existence of modes inside the band gap, when a defect is introduced in the crystal. Resonator measurements show that a microwave resonator can be operated with those defect modes. It was found out that the main losses of the resonator were caused by bad microwave properties of the used dielectric material and by metal losses on the top and bottom resonator walls. Furthermore, it turned out that the detection of the photonic crystal defect mode was difficult because of a lack of simulation possibilities and high housing mode density in the resonator. (orig.)

  9. Total dose radiation effects of pressure sensors fabricated on uni-bond-SOI materials

    International Nuclear Information System (INIS)

    Zhu Shiyang; Huang Yiping; Wang Jin; Li Anzhen; Shen Shaoqun; Bao Minhang

    2001-01-01

    Piezoresistive pressure sensors with a twin-island structure were successfully fabricated using high quality Uni-bond-SOI (On Insulator) materials. Since the piezoresistors were structured by the single crystalline silicon overlayer of the SOI wafer and were totally isolated by the buried SiO 2 , the sensors are radiation-hard. The sensitivity and the linearity of the pressure sensors keep their original values after being irradiated by 60 Co γ-rays up to 2.3 x 10 4 Gy(H 2 O). However, the offset voltage of the sensor has a slight drift, increasing with the radiation dose. The absolute value of the offset voltage deviation depends on the pressure sensor itself. For comparison, corresponding polysilicon pressure sensors were fabricated using the similar process and irradiated at the same condition

  10. BUSFET -- A radiation-hardened SOI transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

  11. Technology development for SOI monolithic pixel detectors

    International Nuclear Information System (INIS)

    Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

    2006-01-01

    A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

  12. Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

    International Nuclear Information System (INIS)

    Kumar, V Vinoth; Dasgupta, A; Bhat, K N; KNatarajan

    2006-01-01

    In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process

  13. Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

    Science.gov (United States)

    Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2011-06-01

    For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

  14. High Q-factor tunable superconducting HF circuit

    CERN Document Server

    Vopilkin, E A; Pavlov, S A; Ponomarev, L I; Ganitsev, A Y; Zhukov, A S; Vladimirov, V V; Letyago, A G; Parshikov, V V

    2001-01-01

    Feasibility of constructing a high Q-factor (Q approx 10 sup 5) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz

  15. High Q-factor tunable superconducting HF circuit

    International Nuclear Information System (INIS)

    Vopilkin, E.A.; Parafin, A.E.; Pavlov, S.A.; Ponomarev, L.I.; Ganitsev, A.Yu.; Zhukov, A.S.; Vladimirov, V.V.; Letyago, A.G.; Parshikov, V.V.

    2001-01-01

    Feasibility of constructing a high Q-factor (Q ∼ 10 5 ) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz [ru

  16. Excited baryon form factors at high Q2

    International Nuclear Information System (INIS)

    Paul Stoler; Gary Adams; Abdellah Ahmidouch; Chris Armstrong; K. Assamagan; Steven Avery; K. Baker; Peter Bosted; Volker Burkert; Jim Dunne; Tom Eden; Rolf Ent; V. Frolov; David Gaskell; P. Gueye; Wendy Hinton; Cynthia Keppel; Wooyoung Kim; Michael Klusman; Doug Koltenuk; David Mack; Richard Madey; David Meekins; Ralph Minehart; Joseph Mitchell; Hamlet Mkrtchyan; James Napolitano; Gabriel Niculescu; Ioana Niculescu; Mina Nozar; John Price; Paul Stoler; Vardan Tadevosyan; Liguang Tang; Michael Witkowski; Stephen Wood

    1998-01-01

    The role of resonance electroproduction at high Q 2 is discussed in the context of exclusive reactions, as well as the alternative theoretical models which are proposed to treat exclusive reactions in the few GeV 2 /c 2 region of momentum transfer. Jefferson Lab experiment 94-014, which measured the excitation of the Delta (1232) and S 11 (1535) via the reactions p(e,e ' p)pi 0 and p(e,e ' p)eta respectively at Q 2 ∼ 2.8 and 4 GeV 2 /c 2 is described, and the state of analysis reported

  17. A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

    International Nuclear Information System (INIS)

    Guo Yufeng; Wang Zhigong; Sheu Gene

    2009-01-01

    This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N + N and P + N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications. (semiconductor devices)

  18. A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

    International Nuclear Information System (INIS)

    Wang Zhongjian; Cheng Xinhong; Xia Chao; Xu Dawei; Cao Duo; Song Zhaorui; Yu Yuehui; Shen Dashen

    2012-01-01

    A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an 'oxidation-etch-oxidation' process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm 2 . (semiconductor devices)

  19. Two-body form factors at high Q2

    International Nuclear Information System (INIS)

    Gross, F.; Keister, B.D.

    1983-02-01

    The charge form factor of a scalar deuteron at high momentum transfer is examined in a model employing scalar nucleons and mesons. With an eye toward establishing consistency criteria for more realistic calculations, several aspects of the model are examined in detail: the role of nucleon and meson singularities in the one-loop impulse diagram, the role of positive-and negative-energy nucleons, and the relationship to time-ordered perturbation theory. It is found that at large Q 2 (1) the form factor is dominated by a term in which the spectator nucleon is on the mass shell, and (2) the meson singularity structure of the d-n-p vertex function is unimportant in determining the overall high-Q 2 behaviour of the form factor

  20. High Q, Miniaturized LCP-Based Passive Components

    KAUST Repository

    Shamim, Atif

    2014-10-16

    Various methods and systems are provided for high Q, miniaturized LCP-based passive components. In one embodiment, among others, a spiral inductor includes a center connection and a plurality of inductors formed on a liquid crystal polymer (LCP) layer, the plurality of inductors concentrically spiraling out from the center connection. In another embodiment, a vertically intertwined inductor includes first and second inductors including a first section disposed on a side of the LCP layer forming a fraction of a turn and a second section disposed on another side of the LCP layer. At least a portion of the first section of the first inductor is substantially aligned with at least a portion of the second section of the second inductor and at least a portion of the first section of the second inductor is substantially aligned with at least a portion of the second section of the first inductor.

  1. High Q, Miniaturized LCP-Based Passive Components

    KAUST Repository

    Shamim, Atif; Arabi, Eyad A.

    2014-01-01

    Various methods and systems are provided for high Q, miniaturized LCP-based passive components. In one embodiment, among others, a spiral inductor includes a center connection and a plurality of inductors formed on a liquid crystal polymer (LCP) layer, the plurality of inductors concentrically spiraling out from the center connection. In another embodiment, a vertically intertwined inductor includes first and second inductors including a first section disposed on a side of the LCP layer forming a fraction of a turn and a second section disposed on another side of the LCP layer. At least a portion of the first section of the first inductor is substantially aligned with at least a portion of the second section of the second inductor and at least a portion of the first section of the second inductor is substantially aligned with at least a portion of the second section of the first inductor.

  2. Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins

    KAUST Repository

    Diab, Amer El Hajj

    2014-12-01

    We report the temperature dependence of the core electrical parameters and transport characteristics of a flexible version of fin field-effect transistor (FinFET) on silicon-on-insulator (SOI) with sub-20-nm wide fins and high-k/metal gate-stacks. For the first time, we characterize them from room to high temperature (150 °C) to show the impact of temperature variation on drain current, gate leakage current, and transconductance. Variation of extracted parameters, such as low-field mobility, subthreshold swing, threshold voltage, and ON-OFF current characteristics, is reported too. Direct comparison is made to a rigid version of the SOI FinFETs. The mobility degradation with temperature is mainly caused by phonon scattering mechanism. The overall excellent devices performance at high temperature after release is outlined proving the suitability of truly high-performance flexible inorganic electronics with such advanced architecture.

  3. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  4. Performance analysis of SOI MOSFET with rectangular recessed channel

    Science.gov (United States)

    Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

    2016-03-01

    In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

  5. Performance analysis of SOI MOSFET with rectangular recessed channel

    International Nuclear Information System (INIS)

    Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

    2016-01-01

    In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

  6. High Q diamond hemispherical resonators: fabrication and energy loss mechanisms

    International Nuclear Information System (INIS)

    Bernstein, Jonathan J; Bancu, Mirela G; Bauer, Joseph M; Cook, Eugene H; Kumar, Parshant; Nyinjee, Tenzin; Perlin, Gayatri E; Ricker, Joseph A; Teynor, William A; Weinberg, Marc S; Newton, Eric

    2015-01-01

    We have fabricated polycrystalline diamond hemispheres by hot-filament CVD (HFCVD) in spherical cavities wet-etched into a high temperature glass substrate CTE matched to silicon. Hemispherical resonators 1.4 mm in diameter have a Q of up to 143 000 in the fundamental wineglass mode, for a ringdown time of 2.4 s. Without trimming, resonators have the two degenerate wineglass modes frequency matched as close as 2 Hz, or 0.013% of the resonant frequency (∼16 kHz). Laser trimming was used to match resonant modes on hemispheres to 0.3 Hz. Experimental and FEA energy loss studies on cantilevers and hemispheres examine various energy loss mechanisms, showing that surface related losses are dominant. Diamond cantilevers with a Q of 400 000 and a ringdown time of 15.4 s were measured, showing the potential of polycrystalline diamond films for high Q resonators. These resonators show great promise for use as hemispherical resonant gyroscopes (HRGs) on a chip. (paper)

  7. Twin photon pairs in a high-Q silicon microresonator

    Energy Technology Data Exchange (ETDEWEB)

    Rogers, Steven; Lu, Xiyuan [Department of Physics and Astronomy, University of Rochester, Rochester, New York 14627 (United States); Jiang, Wei C. [Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Lin, Qiang, E-mail: qiang.lin@rochester.edu [Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627 (United States)

    2015-07-27

    We report the generation of high-purity twin photon pairs through cavity-enhanced non-degenerate four-wave mixing (FWM) in a high-Q silicon microdisk resonator. Twin photon pairs are created within the same cavity mode and are consequently expected to be identical in all degrees of freedom. The device is able to produce twin photons at telecommunication wavelengths with a pair generation rate as large as (3.96 ± 0.03) × 10{sup 5} pairs/s, within a narrow bandwidth of 0.72 GHz. A coincidence-to-accidental ratio of 660 ± 62 was measured, the highest value reported to date for twin photon pairs, at a pair generation rate of (2.47 ± 0.04) × 10{sup 4} pairs/s. Through careful engineering of the dispersion matching window, we have reduced the ratio of photons resulting from degenerate FWM to non-degenerate FWM to less than 0.15.

  8. Macroscopic quantum electrodynamics of high-Q cavities

    Energy Technology Data Exchange (ETDEWEB)

    Khanbekyan, Mikayel

    2009-10-27

    In this thesis macroscopic quantum electrodynamics in linear media was applied in order to develop an universally valid quantum theory for the description of the interaction of the electromagnetic field with atomic sources in high-Q cavities. In this theory a complete description of the characteristics of the emitted radiation is given. The theory allows to show the limits of the applicability of the usually applied theory. In order to establish an as possible generally valid theory first the atom-field interaction was studied in the framework of macroscopic quantum electrodynamics in dispersive and absorptive media. In order to describe the electromagnetic field from Maxwell's equations was started, whereby the noise-current densities, which are connected with the absorption of the medium, were included. The solution of these equations expresses the electromagnetic field variables by the noise-current densities by means of Green's tensor of the macroscopic Maxwell equations. The explicit quantization is performed by means of the noise-current densities, whereby a diagonal Hamiltonian is introduced, which then guarantees the time development according to Maxwell's equation and the fulfillment of the fundamental simultaneous commutation relations of the field variables. In the case of the interaction of the medium-supported field with atoms the Hamiltonian must be extended by atom-field interactions energies, whereby the canonical coupling schemes of the minimal or multipolar coupling can be used. The dieelectric properties of the material bodies as well as their shape are coded in the Green tensor of the macroscopic Maxwell equations. As preparing step first the Green tensor was specified in order to derive three-dimensional input-output relations for the electromagnetic field operators on a plane multilayer structure. Such a general dewscription of the electromagnetic field allows the inclusion both of dispersion and absorption of the media and the

  9. Preventing Raman Lasing in High-Q WGM Resonators

    Science.gov (United States)

    Savchenkov, Anatoliy; Matsko, Andrey; Strekalov, Dmitry; Maleki, Lute

    2007-01-01

    A generic design has been conceived to suppress the Raman effect in whispering- gallery-mode (WGM) optical resonators that have high values of the resonance quality factor (Q). Although it is possible to exploit the Raman effect (even striving to maximize the Raman gain to obtain Raman lasing), the present innovation is intended to satisfy a need that arises in applications in which the Raman effect inhibits the realization of the full potential of WGM resonators as frequency-selection components. Heretofore, in such applications, it has been necessary to operate high-Q WGM resonators at unattractively low power levels to prevent Raman lasing. (The Raman-lasing thresholds of WGM optical resonators are very low and are approximately proportional to Q(sup -2)). Heretofore, two ways of preventing Raman lasting at high power levels have been known, but both entail significant disadvantages: A resonator can be designed so that the optical field is spread over a relatively large mode volume to bring the power density below the threshold. For any given combination of Q and power level, there is certain mode volume wherein Raman lasing does not start. Unfortunately, a resonator that has a large mode volume also has a high spectral density, which is undesirable in a typical photonic application. A resonator can be cooled to the temperature of liquid helium, where the Raman spectrum is narrower and, therefore, the Raman gain is lower. However, liquid-helium cooling is inconvenient. The present design overcomes these disadvantages, making it possible to operate a low-spectral-density (even a single-mode) WGM resonator at a relatively high power level at room temperature, without risk of Raman lasing.

  10. Macroscopic quantum electrodynamics of high-Q cavities

    International Nuclear Information System (INIS)

    Khanbekyan, Mikayel

    2009-01-01

    In this thesis macroscopic quantum electrodynamics in linear media was applied in order to develop an universally valid quantum theory for the description of the interaction of the electromagnetic field with atomic sources in high-Q cavities. In this theory a complete description of the characteristics of the emitted radiation is given. The theory allows to show the limits of the applicability of the usually applied theory. In order to establish an as possible generally valid theory first the atom-field interaction was studied in the framework of macroscopic quantum electrodynamics in dispersive and absorptive media. In order to describe the electromagnetic field from Maxwell's equations was started, whereby the noise-current densities, which are connected with the absorption of the medium, were included. The solution of these equations expresses the electromagnetic field variables by the noise-current densities by means of Green's tensor of the macroscopic Maxwell equations. The explicit quantization is performed by means of the noise-current densities, whereby a diagonal Hamiltonian is introduced, which then guarantees the time development according to Maxwell's equation and the fulfillment of the fundamental simultaneous commutation relations of the field variables. In the case of the interaction of the medium-supported field with atoms the Hamiltonian must be extended by atom-field interactions energies, whereby the canonical coupling schemes of the minimal or multipolar coupling can be used. The dieelectric properties of the material bodies as well as their shape are coded in the Green tensor of the macroscopic Maxwell equations. As preparing step first the Green tensor was specified in order to derive three-dimensional input-output relations for the electromagnetic field operators on a plane multilayer structure. Such a general dewscription of the electromagnetic field allows the inclusion both of dispersion and absorption of the media and the possible

  11. Analyses of the radiation-caused characteristics change in SOI MOSFETs using field shield isolation

    International Nuclear Information System (INIS)

    Hirano, Yuuichi; Maeda, Shigeru; Fernandez, Warren; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Maegawa, Shigeto; Nishimura, Tadashi

    1999-01-01

    Reliability against radiation ia an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long regime channel. In transistors with a channel length of 0.18μm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0μm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment. (author)

  12. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    International Nuclear Information System (INIS)

    Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

    2011-01-01

    An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

  13. A low on-resistance SOI LDMOS using a trench gate and a recessed drain

    International Nuclear Information System (INIS)

    Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

    2012-01-01

    An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

  14. Thermal Loss of High-Q Antennas in Time Domain vs. Frequency Domain Solver

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Pedersen, Gert Frølund

    2014-01-01

    High-Q structures pose great challenges to their loss simulations in Time Domain Solvers (TDS). Therefore, in this work the thermal loss of high-Q antennas is calculated both in TDS and Frequency Domain Solver (FDS), which are then compared with each other and with the actual measurements....... The thermal loss calculation in FDS is shown to be more accurate for high-Q antennas....

  15. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    International Nuclear Information System (INIS)

    Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

    2014-01-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

  16. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    Science.gov (United States)

    Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

    2014-12-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

  17. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-01-01

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

  18. Coupling Ideality of Integrated Planar High-Q Microresonators

    Science.gov (United States)

    Pfeiffer, Martin H. P.; Liu, Junqiu; Geiselmann, Michael; Kippenberg, Tobias J.

    2017-02-01

    Chip-scale optical microresonators with integrated planar optical waveguides are useful building blocks for linear, nonlinear, and quantum-optical photonic devices alike. Loss reduction through improving fabrication processes results in several integrated microresonator platforms attaining quality (Q ) factors of several millions. Beyond the improvement of the quality factor, the ability to operate the microresonator with high coupling ideality in the overcoupled regime is of central importance. In this regime, the dominant source of loss constitutes the coupling to a single desired output channel, which is particularly important not only for quantum-optical applications such as the generation of squeezed light and correlated photon pairs but also for linear and nonlinear photonics. However, to date, the coupling ideality in integrated photonic microresonators is not well understood, in particular, design-dependent losses and their impact on the regime of high ideality. Here we investigate design-dependent parasitic losses described by the coupling ideality of the commonly employed microresonator design consisting of a microring-resonator waveguide side coupled to a straight bus waveguide, a system which is not properly described by the conventional input-output theory of open systems due to the presence of higher-order modes. By systematic characterization of multimode high-Q silicon nitride microresonator devices, we show that this design can suffer from low coupling ideality. By performing 3D simulations, we identify the coupling to higher-order bus waveguide modes as the dominant origin of parasitic losses which lead to the low coupling ideality. Using suitably designed bus waveguides, parasitic losses are mitigated with a nearly unity ideality and strong overcoupling (i.e., a ratio of external coupling to internal resonator loss rate >9 ) are demonstrated. Moreover, we find that different resonator modes can exchange power through the coupler, which, therefore

  19. Performance study of double SOI image sensors

    Science.gov (United States)

    Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

    2018-02-01

    Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

  20. Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

    Science.gov (United States)

    Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

    2016-03-01

    In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

  1. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  2. VCSELs and silicon light sources exploiting SOI grating mirrors

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2012-01-01

    In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

  3. Fully On-chip High Q Inductors Based on Microtechnologies

    Directory of Open Access Journals (Sweden)

    Kriyang SHAH

    2010-04-01

    Full Text Available Wireless biosensor networks (WBSNs collect information about biological responses and process it using scattered battery-power sensor nodes. Such nodes demand ultra low-power consumption for longer operating time. Ultra Wide Band (UWB is a potential solution for WBSNs due to its advantage in low power consumption at reasonable data rate. However, such UBW technology requires high quality (Q factor passive components. This paper presents detailed analysis, design and optimization of physical parameters of silicon-on-sapphire (SOS and micro-electro-mechanical-systems (MEMS inductors for application in UWB transceivers. Results showed that the 1.5 nH SOS inductor achieved Q factor of 111 and MEMS inductor achieved Q factor of 45 at 4 GHz frequency. The voltage controlled oscillator (VCO designed with SOS inductor achieved more than 10 dBc/Hz reduction in phase noise and consumed half the power compared to VCO with MEMS inductor. Such low power VCO will improve battery life of a UWB wireless sensor node.

  4. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  5. Total dose induced latch in short channel NMOS/SOI transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

    1998-01-01

    A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

  6. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  7. SOI MESFETs for Extreme Environment Electronics, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We are proposing a new extreme environment electronics (EEE) technology based on silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs)....

  8. Hybrid III-V/SOI Resonant Cavity Photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization.......A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization....

  9. Scaling limits and reliability of SOI CMOS technology

    International Nuclear Information System (INIS)

    Ioannou, D E

    2005-01-01

    As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

  10. Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

    International Nuclear Information System (INIS)

    Liao, Shu-Hui; Chang, Shu-Tong

    2010-01-01

    This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

  11. LORINE: Neutron emission Locator by SOI detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hamrita, H.; Kondrasovs, V.; Borbotte, J. M.; Normand, S. [CEA, LIST, Laboratoire Capteurs et Architectures Electronique, F-91191 Gif-sur-Yvette Cedex (France); Saurel, N. [CEA, DAM, VALDUC, F-21120 Is sur Tille (France)

    2009-07-01

    The aim of this work is to develop a fast Neutron Emission Locator based on silicon on Insulator detector (LORINE). This locator can be used in the presence of significant flux of gamma radiation. LORINE was developed to locate areas containing a significant amount of actinide during the dismantling operations of equipment. From the results obtained in laboratory, we have proposed the prototype of neutron emission locator as follows: the developed design consists of 5 SOI (Silicon-on-insulator) detectors (1*1 cm{sup 2}) with their charge preamplifiers and their respective converters. All are installed on 5 faces of a boron polyethylene cube (5*5*5 cm{sup 3}). This cube plays the role of neutron shielding between the several detectors. The design must be so compact for use in glove boxes. An electronic card based on micro-controller has been made to control sensors and to send the necessary information to the computer. Location of fast neutron sources does not yet exist in a so compact design and it can be operated in the presence of very important gamma radiation flux

  12. DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

    Directory of Open Access Journals (Sweden)

    D. SINDHANAISELVI

    2017-07-01

    Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

  13. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  14. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  15. Electronics and Sensor Study with the OKI SOI process

    CERN Document Server

    Arai, Yasuo

    2007-01-01

    While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

  16. Croire en soi, croire en l'autre

    Directory of Open Access Journals (Sweden)

    Eugène Enriquez

    2014-04-01

    Full Text Available La croyance aux Dieux ou en un Dieu unique c'est-à-dire à l'incroyable est fort répandue et semble normale comme avoir confiance en soi et en l'autre. Mais croire en soi et en l'autre apparaît étonnant car ce serait se mettre sur le même rang que Dieu. Effectivement l'homme essaie de ressembler à Dieu. Mais à Dieu blessé, faillible, s'interrogeant constamment. Ce Dieu nouveau est un "sujet amoureux" amoureux de soi, de l'autre et de la vie. Il se conduit comme un "Dichter" assumant une responsabilité morale. Il est difficile, voire souvent impossible de se situer comme un "Dichter". C'est pourtant la tâche à laquelle l'homme contemporain est confronté.

  17. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  18. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  19. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  20. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

  1. Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

    International Nuclear Information System (INIS)

    Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

    2005-01-01

    This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

  2. The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

    Science.gov (United States)

    Stock, William A.; DiSalvo, Pamela M.

    The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

  3. Nonlinear optical oscillation dynamics in high-Q lithium niobate microresonators.

    Science.gov (United States)

    Sun, Xuan; Liang, Hanxiao; Luo, Rui; Jiang, Wei C; Zhang, Xi-Cheng; Lin, Qiang

    2017-06-12

    Recent advance of lithium niobate microphotonic devices enables the exploration of intriguing nonlinear optical effects. We show complex nonlinear oscillation dynamics in high-Q lithium niobate microresonators that results from unique competition between the thermo-optic nonlinearity and the photorefractive effect, distinctive to other device systems and mechanisms ever reported. The observed phenomena are well described by our theory. This exploration helps understand the nonlinear optical behavior of high-Q lithium niobate microphotonic devices which would be crucial for future application of on-chip nonlinear lithium niobate photonics.

  4. SOI MESFETs on high-resistivity, trap-rich substrates

    Science.gov (United States)

    Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

    2018-04-01

    The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

  5. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    International Nuclear Information System (INIS)

    Dehzangi, Arash; Larki, Farhad; Naseri, Mahmud G.; Navasery, Manizheh; Majlis, Burhanuddin Y.; Razip Wee, Mohd F.; Halimah, M.K.; Islam, Md. Shabiul; Md Ali, Sawal H.; Saion, Elias

    2015-01-01

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated

  6. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    Energy Technology Data Exchange (ETDEWEB)

    Dehzangi, Arash, E-mail: arashd53@hotmail.com [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Larki, Farhad [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Naseri, Mahmud G. [Department of Physics, Faculty of Science, Malayer University, Malayer, Hamedan (Iran, Islamic Republic of); Navasery, Manizheh [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Majlis, Burhanuddin Y.; Razip Wee, Mohd F. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Halimah, M.K. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Islam, Md. Shabiul; Md Ali, Sawal H. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Saion, Elias [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia)

    2015-04-15

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated.

  7. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  8. Numerical and Experimental Study of the Q Factor of High-Q Micropillar Cavities

    DEFF Research Database (Denmark)

    Gregersen, Niels; Reitzenstein, S.; Kistner, C.

    2010-01-01

    Micropillar cavities are potential candidates for high-efficiency single-photon sources and are testbeds for cavity quantum electrodynamics experiments. In both applications a high quality (Q) factor is desired. It was recently shown that the Q of high-Q semiconductor micropillar cavities exhibit...

  9. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

    Science.gov (United States)

    Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

    2018-05-01

    In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

  10. Heterojunction fully depleted SOI-TFET with oxide/source overlap

    Science.gov (United States)

    Chander, Sweta; Bhowmick, B.; Baishya, S.

    2015-10-01

    In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

  11. SOI Digital Accelerometer Based on Pull-in Time Configuration

    NARCIS (Netherlands)

    Pakula, L.S.; Rajaraman, V.; French, P.J.

    2009-01-01

    The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The

  12. A high efficiency lateral light emitting device on SOI

    NARCIS (Netherlands)

    Hoang, T.; Le Minh, P.; Holleman, J.; Zieren, V.; Goossens, M.J.; Schmitz, Jurriaan

    2005-01-01

    The infrared light emission of lateral p/sup +/-p-n/sup +/ diodes realized on SIMOX-SOI (separation by implantation of oxygen - silicon on insulator) substrates has been studied. The confinement of the free carriers in one dimension due to the buried oxide was suggested to be a key point to increase

  13. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  14. SOI Transistor measurement techniques using body contacted transistors

    International Nuclear Information System (INIS)

    Worley, E.R.; Williams, R.

    1989-01-01

    Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

  15. Propriété de soi et indifférence morale du rapport à soi

    Directory of Open Access Journals (Sweden)

    Nathalie Maillard Romagnoli

    2011-05-01

    Full Text Available Je m’interroge dans cet article sur les implications du principe libertarien de la pleine propriété de soi sur la question du rapport moral à soi-même. À travers le principe de la pleine propriété de soi, les libertariens défendent la liberté entière de chacun de vivre comme il l���entend, pourvu que les droits des autres soient respectés. Apparemment, ce principe n’a pas grand-chose à nous dire sur ce que nous sommes moralement autorisés à nous faire à nous-mêmes ou non. Certains libertariens, comme Vallentyne, soutiennent toutefois que le principe de la pleine propriété de soi est incompatible avec l’existence de devoirs envers soi. La pleine propriété de soi impliquerait l’indifférence morale du rapport à soi. Je soutiens dans cet article que le principe de la pleine propriété de soi n’implique pas que ce que nous nous faisons à nous-mêmes soit moralement indifférent. Je veux aussi montrer que même si les libertariens, et en particulier Vallentyne, soutiennent la thèse de l’indifférence morale du rapport à soi, celle-ci n’est pas liée à la thèse de la pleine propriété de soi, mais bien plutôt à leur subjectivisme moral.ABSTRACTI ask in this article what the libertarian principle of full self-ownership has to say about volontary actions directed towards oneself. Through the principle of full self-ownership, libertarians defend the persons’ individual liberty to live as they choose to do, as long as they don’t infringe on the rights of others. Apparently, this principle doesn’t have much to say about what we are morally allowed to do to ourselves or not. Some libertarians, however, like Vallentyne, maintain that, if we have duties or obligations to ourselves, then we cannot be full self-owner. In this perspective, full self-ownership would imply that what we do to ourselves is morally indifferent. I want to show in this article that full self-ownership is compatible with the

  16. A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

    Directory of Open Access Journals (Sweden)

    Saeid Marjani

    2016-09-01

    Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

  17. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

    Science.gov (United States)

    Diaz Llorente, C.; Le Royer, C.; Batude, P.; Fenouillet-Beranger, C.; Martinie, S.; Lu, C.-M. V.; Allain, F.; Colinge, J.-P.; Cristoloveanu, S.; Ghibaudo, G.; Vinet, M.

    2018-06-01

    This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

  18. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

  19. STIR-Physics: Cold Atoms and Nanocrystals in Tapered Nanofiber and High-Q Resonator Potentials

    Science.gov (United States)

    2016-11-02

    STIR- Physics : Cold Atoms and Nanocrystals in Tapered Nanofiber and High-Q Resonator Potentials We worked on a tapered fiber in cold atomic cloud...reviewed journals: Number of Papers published in non peer-reviewed journals: Final Report: STIR- Physics : Cold Atoms and Nanocrystals in Tapered Nanofiber...other than abstracts): Number of Peer-Reviewed Conference Proceeding publications (other than abstracts): Books Number of Manuscripts: 0.00Number of

  20. A new method of distinguishing models of the high-Q2 events at HERA

    International Nuclear Information System (INIS)

    Cao, Z.; He, X.G.; McKellar, B.

    1997-07-01

    A new method is proposed to distinguish models for the high Q 2 e + p → e + X anomaly at HERA by looking at a new observable which is insensitive to parton distribution function (PDF), but sensitive to new physics. Three models have been considered: modification of PDF's, new physics due to s-channel production of new particle and new physics due to contact interactions. Using this new method it is possible to distinguish different models with increased luminosity

  1. Confocal microscopy and spectroscopy of nanocrystals on a high-Q microsphere resonator

    International Nuclear Information System (INIS)

    Goetzinger, S; Menezes, L de S; Benson, O; Talapin, D V; Gaponik, N; Weller, H; Rogach, A L; Sandoghdar, V

    2004-01-01

    We report on experiments where we used a home-made confocal microscope to excite single nanocrystals on a high-Q microsphere resonator. In that way spectra of an individual quantum emitter could be recorded. The Q factor of the microspheres coated with nanocrystals was still up to 10 9 . We also demonstrate the use of a prism coupler as a well-defined output port to collect the fluorescence of an ensemble of nanocrystals coupled to whispering-gallery modes

  2. Bandwidth-limited control and ringdown suppression in high-Q resonators.

    Science.gov (United States)

    Borneman, Troy W; Cory, David G

    2012-12-01

    We describe how the transient behavior of a tuned and matched resonator circuit and a ringdown suppression pulse may be integrated into an optimal control theory (OCT) pulse-design algorithm to derive control sequences with limited ringdown that perform a desired quantum operation in the presence of resonator distortions of the ideal waveform. Inclusion of ringdown suppression in numerical pulse optimizations significantly reduces spectrometer deadtime when using high quality factor (high-Q) resonators, leading to increased signal-to-noise ratio (SNR) and sensitivity of inductive measurements. To demonstrate the method, we experimentally measure the free-induction decay of an inhomogeneously broadened solid-state free radical spin system at high Q. The measurement is enabled by using a numerically optimized bandwidth-limited OCT pulse, including ringdown suppression, robust to variations in static and microwave field strengths. We also discuss the applications of pulse design in high-Q resonators to universal control of anisotropic-hyperfine coupled electron-nuclear spin systems via electron-only modulation even when the bandwidth of the resonator is significantly smaller than the hyperfine coupling strength. These results demonstrate how limitations imposed by linear response theory may be vastly exceeded when using a sufficiently accurate system model to optimize pulses of high complexity. Copyright © 2012 Elsevier Inc. All rights reserved.

  3. A novel SOI pressure sensor for high temperature application

    International Nuclear Information System (INIS)

    Li Sainan; Liang Ting; Wang Wei; Hong Yingping; Zheng Tingli; Xiong Jijun

    2015-01-01

    The silicon on insulator (SOI) high temperature pressure sensor is a novel pressure sensor with high-performance and high-quality. A structure of a SOI high-temperature pressure sensor is presented in this paper. The key factors including doping concentration and power are analyzed. The process of the sensor is designed with the critical process parameters set appropriately. The test result at room temperature and high temperature shows that nonlinear error below is 0.1%, and hysteresis is less than 0.5%. High temperature measuring results show that the sensor can be used for from room temperature to 350 °C in harsh environments. It offers a reference for the development of high temperature piezoresistive pressure sensors. (semiconductor devices)

  4. Performance of the INTPIX6 SOI pixel detector

    Science.gov (United States)

    Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  5. Ultra compact triplexing filters based on SOI nanowire AWGs

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei, E-mail: junming@red.semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2011-04-15

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  6. Ultra compact triplexing filters based on SOI nanowire AWGs

    International Nuclear Information System (INIS)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei

    2011-01-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  7. Ultra compact triplexing filters based on SOI nanowire AWGs

    Science.gov (United States)

    Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

    2011-04-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

  8. Test-beam results of a SOI pixel detector prototype

    CERN Document Server

    Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

    2018-01-01

    This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

  9. Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

    Science.gov (United States)

    Wu, Bin

    Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

  10. Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2016-10-01

    For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

  11. Ultrabroadband Hybrid III-V/SOI Grating Reflector for On-chip Lasers

    DEFF Research Database (Denmark)

    Park, Gyeong Cheol; Taghizadeh, Alireza; Chung, Il-Sug

    2016-01-01

    We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability.......We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability....

  12. Aspects of High-Q Tunable Antennas and Their Deployment for 4G Mobile Communications

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Jagielski, Ole; Svendsen, Simon

    2016-01-01

    Tunable antennas are very promising for future generations of mobile communications, where broad frequency coverage will be required increasingly. This work describes the design of small high-Quality factor (Q) tunable antennas based on Micro-Electro-Mechanical Systems (MEMS), which are capable...... of operation in the frequency ranges 600 - 960 MHz and 1710 - 2690 MHz. Some aspects of high-Q tunable antennas are investigated through experimental measurements and the result are presented. Results show that more than -30 dB of isolation can be achieved between the Transmit (Tx) and Receive (Rx) antennas...

  13. A fast way for calculating longitudinal wakefields for high Q resonances

    International Nuclear Information System (INIS)

    Cheng-Yang Tan and James M Steimel

    2001-01-01

    We have come up with a way for calculating longitudinal wakefields for high Q resonances by mapping the wake functions to a two dimension vector space. Then in this space, a transformation which is basically a scale change and a rotation, allows us to calculate the new wakefield by knowing only one previous wakefield and one previous particle passage through the cavity. We will also compare this method to the brute force method which needs to know all the passages of the previous particles through the cavity

  14. High-Q Defect-Free 2D Photonic Crystal Cavity from Random Localised Disorder

    Directory of Open Access Journals (Sweden)

    Kelvin Chung

    2014-07-01

    Full Text Available We propose a high-Q photonic crystal cavity formed by introducing random disorder to the central region of an otherwise defect-free photonic crystal slab (PhC. Three-dimensional finite-difference time-domain simulations determine the frequency, quality factor, Q, and modal volume, V, of the localized modes formed by the disorder. Relatively large Purcell factors of 500–800 are calculated for these cavities, which can be achieved for a large range of degrees of disorders.

  15. On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

    Energy Technology Data Exchange (ETDEWEB)

    Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

    2016-01-11

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

  16. Charged Particle Production in High Q2 Deep-Inelastic Scattering at HERA

    CERN Document Server

    Aaron, F.D.; Alexa, C.; Andreev, V.; Antunovic, B.; Aplin, S.; Asmone, A.; Astvatsatourov, A.; Backovic, S.; Baghdasaryan, A.; Baranov, P.; Barrelet, E.; Bartel, W.; Baudrand, S.; Beckingham, M.; Begzsuren, K.; Behnke, O.; Behrendt, O.; Belousov, A.; Berger, N.; Bizot, J.C.; Boenig, M.-O.; Boudry, V.; Bozovic-Jelisavcic, I.; Bracinik, J.; Brandt, G.; Brinkmann, M.; Brisson, V.; Bruncko, D.; Busser, F.W.; Bunyatyan, A.; Buschhorn, G.; Bystritskaya, L.; Campbell, A.J.; Cantun Avila, K.B.; Cassol-Brunner, F.; Cerny, K.; Cerny, V.; Chekelian, V.; Cholewa, A.; Contreras, J.G.; Coughlan, J.A.; Cozzika, G.; Cvach, J.; Dainton, J.B.; Daum, K.; Deak, M.; de Boer, Y.; Delcourt, B.; Del Degan, M.; Delvax, J.; De Roeck, A.; De Wolf, E.A.; Diaconu, C.; Dodonov, V.; Dubak, A.; Eckerlin, Guenter; Efremenko, V.; Egli, S.; Eichler, R.; Eisele, F.; Eliseev, A.; Elsen, E.; Essenov, S.; Falkiewicz, A.; Faulkner, P.J.W.; Favart, L.; Fedotov, A.; Felst, R.; Feltesse, J.; Ferencei, J.; Finke, L.; Fleischer, M.; Fomenko, A.; Franke, G.; Frisson, T.; Gabathuler, E.; Gayler, J.; Ghazaryan, Samvel; Ginzburgskaya, S.; Glazov, A.; Glushkov, I.; Goerlich, L.; Goettlich, M.; Gogitidze, N.; Gorbounov, S.; Gouzevitch, M.; Grab, C.; Greenshaw, T.; Grell, B.R.; Grindhammer, G.; Habib, S.; Haidt, D.; Hansson, M.; Heinzelmann, G.; Helebrant, C.; Henderson, R.C.W.; Henschel, H.; Herrera, G.; Hildebrandt, M.; Hiller, K.H.; Hoffmann, D.; Horisberger, R.; Hovhannisyan, A.; Hreus, T.; Jacquet, M.; Janssen, M.E.; Janssen, X.; Jemanov, V.; Jonsson, L.; Johnson, D.P.; Jung, Andreas Werner; Jung, H.; Kapichine, M.; Katzy, J.; Kenyon, I.R.; Kiesling, Christian M.; Klein, M.; Kleinwort, C.; Klimkovich, T.; Kluge, T.; Knutsson, A.; Korbel, V.; Kostka, P.; Kraemer, M.; Krastev, K.; Kretzschmar, J.; Kropivnitskaya, A.; Kruger, K.; Landon, M.P.J.; Lange, W.; Lastovicka-Medin, G.; Laycock, P.; Lebedev, A.; Leibenguth, G.; Lendermann, V.; Levonian, S.; Li, G.; Lindfeld, L.; Lipka, K.; Liptaj, A.; List, B.; List, J.; Loktionova, N.; Lopez-Fernandez, R.; Lubimov, V.; Lucaci-Timoce, A.-I.; Lytkin, L.; Makankine, A.; Malinovski, E.; Marage, P.; Marti, Ll.; Martisikova, M.; Martyn, H.-U.; Maxfield, S.J.; Mehta, A.; Meier, K.; Meyer, A.B.; Meyer, H.; Meyer, J.; Michels, V.; Mikocki, S.; Milcewicz-Mika, I.; Mohamed, A.; Moreau, F.; Morozov, A.; Morris, J.V.; Mozer, Matthias Ulrich; Muller, K.; Murin, P.; Nankov, K.; Naroska, B.; Naumann, Th.; Newman, Paul R.; Niebuhr, C.; Nikiforov, A.; Nowak, G.; Nowak, K.; Nozicka, M.; Oganezov, R.; Olivier, B.; Olsson, J.E.; Osman, S.; Ozerov, D.; Palichik, V.; Panagoulias, I.; Pandurovic, M.; Papadopoulou, Th.; Pascaud, C.; Patel, G.D.; Peng, H.; Perez, E.; Perez-Astudillo, D.; Perieanu, A.; Petrukhin, A.; Picuric, I.; Piec, S.; Pitzl, D.; Placakyte, R.; Polifka, R.; Povh, B.; Preda, T.; Prideaux, P.; Radescu, V.; Rahmat, A.J.; Raicevic, N.; Ravdandorj, T.; Reimer, P.; Risler, C.; Rizvi, E.; Robmann, P.; Roland, B.; Roosen, R.; Rostovtsev, A.; Rurikova, Z.; Rusakov, S.; Salek, D.; Salvaire, F.; Sankey, D.P.C.; Sauter, M.; Sauvan, E.; Schmidt, S.; Schmitt, S.; Schmitz, C.; Schoeffel, L.; Schoning, A.; Schultz-Coulon, H.-C.; Sefkow, F.; Shaw-West, R.N.; Sheviakov, I.; Shtarkov, L.N.; Sloan, T.; Smiljanic, Ivan; Smirnov, P.; Soloviev, Y.; South, D.; Spaskov, V.; Specka, Arnd E.; Staykova, Z.; Steder, M.; Stella, B.; Stiewe, J.; Straumann, U.; Sunar, D.; Sykora, T.; Tchoulakov, V.; Thompson, G.; Thompson, P.D.; Toll, T.; Tomasz, F.; Tran, T.H.; Traynor, D.; Trinh, T.N.; Truol, P.; Tsakov, I.; Tseepeldorj, B.; Tsipolitis, G.; Tsurin, I.; Turnau, J.; Tzamariudaki, E.; Urban, K.; Utkin, D.; Valkarova, A.; Vallee, C.; Van Mechelen, P.; Vargas Trevino, A.; Vazdik, Y.; Vinokurova, S.; Volchinski, V.; Weber, G.; Weber, R.; Wegener, D.; Werner, C.; Wessels, M.; Wissing, Ch.; Wolf, R.; Wunsch, E.; Xella, S.; Yeganov, V.; Zacek, J.; Zalesak, J.; Zhang, Z.; Zhelezov, A.; Zhokin, A.; Zhu, Y.C.; Zimmermann, T.; Zohrabyan, H.; Zomer, F.

    2007-01-01

    The average charged track multiplicity and the normalised distribution of the scaled momentum, $\\xp$, of charged final state hadrons are measured in deep-inelastic $\\ep$ scattering at high $Q^2$ in the Breit frame of reference. The analysis covers the range of photon virtuality $100 < Q^2 < 20 000 \\GeV^{2}$. Compared with previous results presented by HERA experiments this analysis has a significantly higher statistical precision and extends the phase space to higher $Q^{2}$ and to the full range of $\\xp$. The results are compared with $e^+e^-$ annihilation data and with various calculations based on perturbative QCD using different models of the hadronisation process.

  17. Charged particle production in high Q deep-inelastic scattering at HERA

    Science.gov (United States)

    H1 Collaboration; Aaron, F. D.; Aktas, A.; Alexa, C.; Andreev, V.; Antunovic, B.; Aplin, S.; Asmone, A.; Astvatsatourov, A.; Backovic, S.; Baghdasaryan, A.; Baranov, P.; Barrelet, E.; Bartel, W.; Baudrand, S.; Beckingham, M.; Begzsuren, K.; Behnke, O.; Behrendt, O.; Belousov, A.; Berger, N.; Bizot, J. C.; Boenig, M.-O.; Boudry, V.; Bozovic-Jelisavcic, I.; Bracinik, J.; Brandt, G.; Brinkmann, M.; Brisson, V.; Bruncko, D.; Büsser, F. W.; Bunyatyan, A.; Buschhorn, G.; Bystritskaya, L.; Campbell, A. J.; Avila, K. B. Cantun; Cassol-Brunner, F.; Cerny, K.; Cerny, V.; Chekelian, V.; Cholewa, A.; Contreras, J. G.; Coughlan, J. A.; Cozzika, G.; Cvach, J.; Dainton, J. B.; Daum, K.; Deak, M.; de Boer, Y.; Delcourt, B.; Del Degan, M.; Delvax, J.; de Roeck, A.; de Wolf, E. A.; Diaconu, C.; Dodonov, V.; Dubak, A.; Eckerlin, G.; Efremenko, V.; Egli, S.; Eichler, R.; Eisele, F.; Eliseev, A.; Elsen, E.; Essenov, S.; Falkiewicz, A.; Faulkner, P. J. W.; Favart, L.; Fedotov, A.; Felst, R.; Feltesse, J.; Ferencei, J.; Finke, L.; Fleischer, M.; Fomenko, A.; Franke, G.; Frisson, T.; Gabathuler, E.; Gayler, J.; Ghazaryan, S.; Ginzburgskaya, S.; Glazov, A.; Glushkov, I.; Goerlich, L.; Goettlich, M.; Gogitidze, N.; Gorbounov, S.; Gouzevitch, M.; Grab, C.; Greenshaw, T.; Gregori, M.; Grell, B. R.; Grindhammer, G.; Habib, S.; Haidt, D.; Hansson, M.; Heinzelmann, G.; Helebrant, C.; Henderson, R. C. W.; Henschel, H.; Herrera, G.; Hildebrandt, M.; Hiller, K. H.; Hoffmann, D.; Horisberger, R.; Hovhannisyan, A.; Hreus, T.; Jacquet, M.; Janssen, M. E.; Janssen, X.; Jemanov, V.; Jönsson, L.; Johnson, D. P.; Jung, A. W.; Jung, H.; Kapichine, M.; Katzy, J.; Kenyon, I. R.; Kiesling, C.; Klein, M.; Kleinwort, C.; Klimkovich, T.; Kluge, T.; Knutsson, A.; Korbel, V.; Kostka, P.; Kraemer, M.; Krastev, K.; Kretzschmar, J.; Kropivnitskaya, A.; Krüger, K.; Landon, M. P. J.; Lange, W.; Laštovička-Medin, G.; Laycock, P.; Lebedev, A.; Leibenguth, G.; Lendermann, V.; Levonian, S.; Li, G.; Lindfeld, L.; Lipka, K.; Liptaj, A.; List, B.; List, J.; Loktionova, N.; Lopez-Fernandez, R.; Lubimov, V.; Lucaci-Timoce, A.-I.; Lytkin, L.; Makankine, A.; Malinovski, E.; Marage, P.; Marti, Ll.; Martisikova, M.; Martyn, H.-U.; Maxfield, S. J.; Mehta, A.; Meier, K.; Meyer, A. B.; Meyer, H.; Meyer, H.; Meyer, J.; Michels, V.; Mikocki, S.; Milcewicz-Mika, I.; Mohamed, A.; Moreau, F.; Morozov, A.; Morris, J. V.; Mozer, M. U.; Müller, K.; Murín, P.; Nankov, K.; Naroska, B.; Naumann, Th.; Newman, P. R.; Niebuhr, C.; Nikiforov, A.; Nowak, G.; Nowak, K.; Nozicka, M.; Oganezov, R.; Olivier, B.; Olsson, J. E.; Osman, S.; Ozerov, D.; Palichik, V.; Panagoulias, I.; Pandurovic, M.; Papadopoulou, Th.; Pascaud, C.; Patel, G. D.; Peng, H.; Perez, E.; Perez-Astudillo, D.; Perieanu, A.; Petrukhin, A.; Picuric, I.; Piec, S.; Pitzl, D.; Plačakytė, R.; Polifka, R.; Povh, B.; Preda, T.; Prideaux, P.; Radescu, V.; Rahmat, A. J.; Raicevic, N.; Ravdandorj, T.; Reimer, P.; Risler, C.; Rizvi, E.; Robmann, P.; Roland, B.; Roosen, R.; Rostovtsev, A.; Rurikova, Z.; Rusakov, S.; Salek, D.; Salvaire, F.; Sankey, D. P. C.; Sauter, M.; Sauvan, E.; Schmidt, S.; Schmitt, S.; Schmitz, C.; Schoeffel, L.; Schöning, A.; Schultz-Coulon, H.-C.; Sefkow, F.; Shaw-West, R. N.; Sheviakov, I.; Shtarkov, L. N.; Sloan, T.; Smiljanic, I.; Smirnov, P.; Soloviev, Y.; South, D.; Spaskov, V.; Specka, A.; Staykova, Z.; Steder, M.; Stella, B.; Stiewe, J.; Straumann, U.; Sunar, D.; Sykora, T.; Tchoulakov, V.; Thompson, G.; Thompson, P. D.; Toll, T.; Tomasz, F.; Tran, T. H.; Traynor, D.; Trinh, T. N.; Truöl, P.; Tsakov, I.; Tseepeldorj, B.; Tsipolitis, G.; Tsurin, I.; Turnau, J.; Tzamariudaki, E.; Urban, K.; Utkin, D.; Valkárová, A.; Vallée, C.; van Mechelen, P.; Trevino, A. Vargas; Vazdik, Y.; Vinokurova, S.; Volchinski, V.; Weber, G.; Weber, R.; Wegener, D.; Werner, C.; Wessels, M.; Wissing, Ch.; Wolf, R.; Wünsch, E.; Xella, S.; Yeganov, V.; Žáček, J.; Zálešák, J.; Zhang, Z.; Zhelezov, A.; Zhokin, A.; Zhu, Y. C.; Zimmermann, T.; Zohrabyan, H.; Zomer, F.

    2007-10-01

    The average charged track multiplicity and the normalised distribution of the scaled momentum, x, of charged final state hadrons are measured in deep-inelastic ep scattering at high Q in the Breit frame of reference. The analysis covers the range of photon virtuality 100

  18. Charged particle production in high Q2 deep-inelastic scattering at HERA

    Science.gov (United States)

    Aaron, F. D.; Aktas, A.; Alexa, C.; Andreev, V.; Antunovic, B.; Aplin, S.; Asmone, A.; Astvatsatourov, A.; Backovic, S.; Baghdasaryan, A.; Baranov, P.; Barrelet, E.; Bartel, W.; Baudrand, S.; Beckingham, M.; Begzsuren, K.; Behnke, O.; Behrendt, O.; Belousov, A.; Berger, N.; Bizot, J. C.; Boenig, M.-O.; Boudry, V.; Bozovic-Jelisavcic, I.; Bracinik, J.; Brandt, G.; Brinkmann, M.; Brisson, V.; Bruncko, D.; Büsser, F. W.; Bunyatyan, A.; Buschhorn, G.; Bystritskaya, L.; Campbell, A. J.; Avila, K. B. Cantun; Cassol-Brunner, F.; Cerny, K.; Cerny, V.; Chekelian, V.; Cholewa, A.; Contreras, J. G.; Coughlan, J. A.; Cozzika, G.; Cvach, J.; Dainton, J. B.; Daum, K.; Deak, M.; de Boer, Y.; Delcourt, B.; Del Degan, M.; Delvax, J.; De Roeck, A.; De Wolf, E. A.; Diaconu, C.; Dodonov, V.; Dubak, A.; Eckerlin, G.; Efremenko, V.; Egli, S.; Eichler, R.; Eisele, F.; Eliseev, A.; Elsen, E.; Essenov, S.; Falkiewicz, A.; Faulkner, P. J. W.; Favart, L.; Fedotov, A.; Felst, R.; Feltesse, J.; Ferencei, J.; Finke, L.; Fleischer, M.; Fomenko, A.; Franke, G.; Frisson, T.; Gabathuler, E.; Gayler, J.; Ghazaryan, S.; Ginzburgskaya, S.; Glazov, A.; Glushkov, I.; Goerlich, L.; Goettlich, M.; Gogitidze, N.; Gorbounov, S.; Gouzevitch, M.; Grab, C.; Greenshaw, T.; Gregori, M.; Grell, B. R.; Grindhammer, G.; Habib, S.; Haidt, D.; Hansson, M.; Heinzelmann, G.; Helebrant, C.; Henderson, R. C. W.; Henschel, H.; Herrera, G.; Hildebrandt, M.; Hiller, K. H.; Hoffmann, D.; Horisberger, R.; Hovhannisyan, A.; Hreus, T.; Jacquet, M.; Janssen, M. E.; Janssen, X.; Jemanov, V.; Jönsson, L.; Johnson, D. P.; Jung, A. W.; Jung, H.; Kapichine, M.; Katzy, J.; Kenyon, I. R.; Kiesling, C.; Klein, M.; Kleinwort, C.; Klimkovich, T.; Kluge, T.; Knutsson, A.; Korbel, V.; Kostka, P.; Kraemer, M.; Krastev, K.; Kretzschmar, J.; Kropivnitskaya, A.; Krüger, K.; Landon, M. P. J.; Lange, W.; Laštovička-Medin, G.; Laycock, P.; Lebedev, A.; Leibenguth, G.; Lendermann, V.; Levonian, S.; Li, G.; Lindfeld, L.; Lipka, K.; Liptaj, A.; List, B.; List, J.; Loktionova, N.; Lopez-Fernandez, R.; Lubimov, V.; Lucaci-Timoce, A.-I.; Lytkin, L.; Makankine, A.; Malinovski, E.; Marage, P.; Marti, Ll.; Martisikova, M.; Martyn, H.-U.; Maxfield, S. J.; Mehta, A.; Meier, K.; Meyer, A. B.; Meyer, H.; Meyer, H.; Meyer, J.; Michels, V.; Mikocki, S.; Milcewicz-Mika, I.; Mohamed, A.; Moreau, F.; Morozov, A.; Morris, J. V.; Mozer, M. U.; Müller, K.; Murín, P.; Nankov, K.; Naroska, B.; Naumann, Th.; Newman, P. R.; Niebuhr, C.; Nikiforov, A.; Nowak, G.; Nowak, K.; Nozicka, M.; Oganezov, R.; Olivier, B.; Olsson, J. E.; Osman, S.; Ozerov, D.; Palichik, V.; Panagoulias, I.; Pandurovic, M.; Papadopoulou, Th.; Pascaud, C.; Patel, G. D.; Peng, H.; Perez, E.; Perez-Astudillo, D.; Perieanu, A.; Petrukhin, A.; Picuric, I.; Piec, S.; Pitzl, D.; Plačakytė, R.; Polifka, R.; Povh, B.; Preda, T.; Prideaux, P.; Radescu, V.; Rahmat, A. J.; Raicevic, N.; Ravdandorj, T.; Reimer, P.; Risler, C.; Rizvi, E.; Robmann, P.; Roland, B.; Roosen, R.; Rostovtsev, A.; Rurikova, Z.; Rusakov, S.; Salek, D.; Salvaire, F.; Sankey, D. P. C.; Sauter, M.; Sauvan, E.; Schmidt, S.; Schmitt, S.; Schmitz, C.; Schoeffel, L.; Schöning, A.; Schultz-Coulon, H.-C.; Sefkow, F.; Shaw-West, R. N.; Sheviakov, I.; Shtarkov, L. N.; Sloan, T.; Smiljanic, I.; Smirnov, P.; Soloviev, Y.; South, D.; Spaskov, V.; Specka, A.; Staykova, Z.; Steder, M.; Stella, B.; Stiewe, J.; Straumann, U.; Sunar, D.; Sykora, T.; Tchoulakov, V.; Thompson, G.; Thompson, P. D.; Toll, T.; Tomasz, F.; Tran, T. H.; Traynor, D.; Trinh, T. N.; Truöl, P.; Tsakov, I.; Tseepeldorj, B.; Tsipolitis, G.; Tsurin, I.; Turnau, J.; Tzamariudaki, E.; Urban, K.; Utkin, D.; Valkárová, A.; Vallée, C.; Van Mechelen, P.; Trevino, A. Vargas; Vazdik, Y.; Vinokurova, S.; Volchinski, V.; Weber, G.; Weber, R.; Wegener, D.; Werner, C.; Wessels, M.; Wissing, Ch.; Wolf, R.; Wünsch, E.; Xella, S.; Yeganov, V.; Žáček, J.; Zálešák, J.; Zhang, Z.; Zhelezov, A.; Zhokin, A.; Zhu, Y. C.; Zimmermann, T.; Zohrabyan, H.; Zomer, F.; H1 Collaboration

    2007-10-01

    The average charged track multiplicity and the normalised distribution of the scaled momentum, xp, of charged final state hadrons are measured in deep-inelastic ep scattering at high Q2 in the Breit frame of reference. The analysis covers the range of photon virtuality 100

  19. High Q-factor metasurfaces based on miniaturized asymmetric single split resonators

    Science.gov (United States)

    Al-Naib, Ibraheem A. I.; Jansen, Christian; Koch, Martin

    2009-04-01

    We introduce asymmetric single split rectangular resonators as bandstop metasurfaces, which exhibit very high Q-factors in combination with low passband losses and a small electrical footprint. The effect of the degree of asymmetry on the frequency response is thoroughly studied. Furthermore, complementary structures, which feature a bandpass behavior, were derived by applying Babinet's principle and investigated with regards to their transmission characteristics. In future, asymmetric single split rectangular resonators could provide efficient unit cells for frequency selective surface devices, such as thin-film sensors or high performance filters.

  20. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

    Science.gov (United States)

    Jain, Neeraj; Raj, Balwinder

    2017-12-01

    Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

  1. A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

    Science.gov (United States)

    Ghaffari, Majid; Orouji, Ali A.

    2018-06-01

    Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

  2. The combination of high Q factor and chirality in twin cavities and microcavity chain

    Science.gov (United States)

    Song, Qinghai; Zhang, Nan; Zhai, Huilin; Liu, Shuai; Gu, Zhiyuan; Wang, Kaiyang; Sun, Shang; Chen, Zhiwei; Li, Meng; Xiao, Shumin

    2014-01-01

    Chirality in microcavities has recently shown its bright future in optical sensing and microsized coherent light sources. The key parameters for such applications are the high quality (Q) factor and large chirality. However, the previous reported chiral resonances are either low Q modes or require very special cavity designs. Here we demonstrate a novel, robust, and general mechanism to obtain the chirality in circular cavity. By placing a circular cavity and a spiral cavity in proximity, we show that ultra-high Q factor, large chirality, and unidirectional output can be obtained simultaneously. The highest Q factors of the non-orthogonal mode pairs are almost the same as the ones in circular cavity. And the co-propagating directions of the non-orthogonal mode pairs can be reversed by tuning the mode coupling. This new mechanism for the combination of high Q factor and large chirality is found to be very robust to cavity size, refractive index, and the shape deformation, showing very nice fabrication tolerance. And it can be further extended to microcavity chain and microcavity plane. We believe that our research will shed light on the practical applications of chirality and microcavities. PMID:25262881

  3. Modeling and Analysis of a Closed-Loop System for High-Q MEMS Accelerometer Sensor

    Directory of Open Access Journals (Sweden)

    Wang Yalin

    2018-01-01

    Full Text Available High-Q sensing element is desirable for high performance while makes the loop control a great challenge. This paper presents a closed-loop system for high-Q capacitive MEMS accelerometer which has achieved loop control effectively. The proportional-derivative(PDcontrol is developed in the system to improve the system stability. In addition, pulse width modulation (PWM electrostatic force feedback is designed in the loop to overcome the nonlinearity. Furthermore, a sigma-delta (ΣΔ modulator with noise shaping is built to realize digital output. System model is built in Matlab/Simulink. The simulation results indicate that equivalent Q value is reduced to 1.5 to ensure stability and responsiveness of the system. The effective number of bits of system output is 14.7 bits. The system nonlinearity is less than 5‰. The equivalent linear model including main noise factors is built, and then a complete theory of noise and linearity analysis is established to contribute to common MEMS accelerometer research.

  4. Hybrid III-V/SOI resonant cavity enhanced photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III–V/SOI resonant-cavity-enhanced photodetector (RCE-PD) structure comprising a high-contrast grating (HCG) reflector, a hybrid grating (HG) reflector, and an air cavity between them, has been proposed and investigated. In the proposed structure, a light absorbing material is integrated...... as part of the HG reflector, enabling a very compact vertical cavity. Numerical investigations show that a quantum efficiency close to 100 % and a detection linewidth of about 1 nm can be achieved, which are desirable for wavelength division multiplexing applications. Based on these results, a hybrid RCE...

  5. Inverse Design of a SOI T-junction Polarization Beamsplitter

    Science.gov (United States)

    Ye, Zi; Qiu, Jifang; Meng, Chong; Zheng, Li; Dong, Zhenli; Wu, Jian

    2017-06-01

    A SOI T-junction polarization beamsplitter with an ultra-compact footprint of 2.8×2.8μm2 is designed based on the method of inverse design. Simulated results show that the conversion efficiencies for TE and TM lights are 73.34% (simulated insertion loss of 2dB) and 80.4% (simulated insertion loss of 1.7dB) at 1550nm, respectively; the simulated extinction ratios for TE and TM lights are 19.3dB and 13.99dB at 1558nm, respectively.

  6. Thin NbN film structures on SOI for SNSPD

    Energy Technology Data Exchange (ETDEWEB)

    Il' in, Konstantin; Kurz, Stephan; Henrich, Dagmar; Hofherr, Matthias; Siegel, Michael [IMS, KIT, Karlsruhe (Germany); Semenov, Alexei; Huebers, Heinz-Wilhelm [DLR, Berlin (Germany)

    2012-07-01

    Superconducting Nanowire Single-Photon Detectors (SNSPD) made from ultra-thin NbN films on sapphire demonstrate almost 100% intrinsic detection efficiency (DE). However the system DE values is less than 10% mostly limited by a very low absorptance of NbN films thinner than 5 nm. Integration of SNSPD in Si photonic circuit is a promising way to overcome this problem. We present results on optimization of technology of thin NbN film nanostructures on SOI (Silicon on Insulator) substrate used in Si photonics technology. Superconducting and normal state properties of these structures important for SNSPD development are presented and discussed.

  7. The founder of the Friends Foundation--Tessie Soi.

    Science.gov (United States)

    Topurua, Ore

    2013-01-01

    Tessie Soi is well known in Papua New Guinea and beyond for her work with HIV/AIDS (human immunodeficiency virus/acquired immune deficiency syndrome) patients, including through the Friends Foundation, an organization that focuses on helping families affected by HIV and AIDS. This article explores Tessie's early life and childhood, providing insight into some of the values she learned from her parents. Providing details about the Friends Foundation and the Orphan Buddy Systems program, a program Tessie established to support AIDS orphans, the article offers insight into Tessie's beliefs and compassion, simultaneously highlighting the value she places on her family.

  8. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    Science.gov (United States)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  9. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  10. Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

    Science.gov (United States)

    Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

    2017-07-01

    Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

  11. Compact Si-based asymmetric MZI waveguide on SOI as a thermo-optical switch

    Science.gov (United States)

    Rizal, C. S.; Niraula, B.

    2018-03-01

    A compact low power consuming asymmetric MZI based optical modulator with fast response time has been proposed on SOI platform. The geometrical and performance characteristics were analyzed in depth and optimized using coupled mode analysis and FDTD simulation tools, respectively. It was tested with and without implementation of thermo-optic (TO) effect. The device showed good frequency modulating characteristics when tested without the implementation of the TO effect. The fabricated device showed quality factor, Q ≈ 10,000, and this value is comparable to the Q of the device simulated with 25% transmission loss, showing FSR of 0.195 nm, FWHM ≈ 0.16 nm, and ER of 13 dB. With TO effect, it showed temperature sensitivity of 0.01 nm/°C and FSR of 0.19 nm. With the heater length of 4.18 mm, the device required 0.26 mW per π shift power with a switching voltage of 0.309 V, response time of 10 μ, and figure-of-merit of 2.6 mW μs. All of these characteristics make this device highly attractive for use in integrated Si photonics network as optical switch and wavelength modulator.

  12. Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

    Science.gov (United States)

    Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

    2018-05-01

    Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

  13. Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

    Science.gov (United States)

    Duclaux, Benjamin; De Caunes, Jean; Perrier, Robin; Gatefait, Maxime; Le Gratiet, Bertrand; Chapon, Jean-Damien; Monget, Cédric

    2018-03-01

    Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the "more than Moore" path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or "virtual overlay" could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

  14. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

    International Nuclear Information System (INIS)

    Wu Hao; Xu Miao; Wan Guangxing; Zhu Huilong; Zhao Lichuan; Tong Xiaodong; Zhao Chao; Chen Dapeng; Ye Tianchun

    2014-01-01

    The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, V t -roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (V t ) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing V t at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated. (semiconductor devices)

  15. Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

    Science.gov (United States)

    Takulapalli, Bharath R

    2010-02-23

    Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

  16. Characterization of pixel sensor designed in 180 nm SOI CMOS technology

    Science.gov (United States)

    Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

    2018-01-01

    A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

  17. Evanescently Coupled Rectangular Microresonators in Silicon-on-Insulator with High Q-Values: Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Manuel Mendez-Astudillo

    2017-04-01

    Full Text Available We report on evanescently coupled rectangular microresonators with dimensions up to 20 × 10 μm2 in silicon-on-insulator in an add-drop filter configuration. The influence of the geometrical parameters of the device was experimentally characterized and a high Q value of 13,000 was demonstrated as well as the multimode optical resonance characteristics in the drop port. We also show a 95% energy transfer between ports when the device is operated in TM-polarization and determine the full symmetry of the device by using an eight-port configuration, allowing the drop waveguide to be placed on any of its sides, providing a way to filter and route optical signals. We used the FDTD method to analyze the device and e-beam lithography and dry etching techniques for fabrication.

  18. Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

    Science.gov (United States)

    Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

    2013-07-29

    We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

  19. Low Cost SU8 Based Above IC Process for High Q RF Power Inductors Integration

    International Nuclear Information System (INIS)

    Ghannam, A.; Bourrier, D.; Viallon, Ch.; Parra, Th.

    2011-01-01

    This paper presents a new process for integration of high-Q RF power inductors above low resistivity silicon substrates. The process uses the SU8 resin as a dielectric layer. The aim of using the SU8 is to form thick dielectric layer that can enhance the performance of the inductors. The flexibility of the process enables the possibility to realize complex shaped planar inductors with various dielectric and metal thicknesses to meet the requirements of the application. Q values of 55 at 5 GHz has been demonstrated for an inductance value of 0.8 nH using a 60 μm thick SU8 layer and 30 μm thick copper ribbons. (author)

  20. Selective tuning of high-Q silicon photonic crystal nanocavities via laser-assisted local oxidation.

    Science.gov (United States)

    Chen, Charlton J; Zheng, Jiangjun; Gu, Tingyi; McMillan, James F; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee; Wong, Chee Wei

    2011-06-20

    We examine the cavity resonance tuning of high-Q silicon photonic crystal heterostructures by localized laser-assisted thermal oxidation using a 532 nm continuous wave laser focused to a 2.5 μm radius spot-size. The total shift is consistent with the parabolic rate law. A tuning range of up to 8.7 nm is achieved with ∼ 30 mW laser powers. Over this tuning range, the cavity Qs decreases from 3.2×10(5) to 1.2×10(5). Numerical simulations model the temperature distributions in the silicon photonic crystal membrane and the cavity resonance shift from oxidation.

  1. HiQ - A high-Q diffractometer for PDF measurements

    International Nuclear Information System (INIS)

    Brunelli, M.; Fischer, H.E.; Gaehler, R.; Chatterji, T.

    2011-01-01

    The local structure of many important functional materials is often different from the average structure, as revealed by diffraction, due to, e.g. doping, mixed site occupancy, or formation of time-dependent local distortions. To get information on both the average and the local structures one needs to perform a joint Rietveld and PDF (Pair Distribution Function) analysis of the total scattering, for which we need data to Q = 30 - 35 Angstroms with Δd/d ∼ 3*10 -3 . Here, we describe how the hot-source diffractometer D4 can be adapted to achieve this capability, and outline one possible design of a dedicated high-Q diffractometer at the ILL (Laue Langevin Institute), using the vacant inclined hot-neutron beam IH2. (authors)

  2. Enhancing the resonance stability of a high-Q micro/nanoresonator by an optical means

    Science.gov (United States)

    Sun, Xuan; Luo, Rui; Zhang, Xi-Cheng; Lin, Qiang

    2016-02-01

    High-quality optical resonators underlie many important applications ranging from optical frequency metrology, precision measurement, nonlinear/quantum photonics, to diverse sensing such as detecting single biomolecule, electromagnetic field, mechanical acceleration/rotation, among many others. All these applications rely essentially on the stability of optical resonances, which, however, is ultimately limited by the fundamental thermal fluctuations of the devices. The resulting thermo-refractive and thermo-elastic noises have been widely accepted for nearly two decades as the fundamental thermodynamic limit of an optical resonator, limiting its resonance uncertainty to a magnitude 10-12 at room temperature. Here we report a novel approach that is able to significantly improve the resonance stability of an optical resonator. We show that, in contrast to the common belief, the fundamental temperature fluctuations of a high-Q micro/nanoresonator can be suppressed remarkably by pure optical means without cooling the device temperature, which we term as temperature squeezing. An optical wave with only a fairly moderate power launched into the device is able to produce strong photothermal backaction that dramatically suppresses the spectral intensity of temperature fluctuations by five orders of magnitudes and squeezes the overall level (root-mean-square value) of temperature fluctuations by two orders of magnitude. The proposed approach is universally applicable to various micro/nanoresonator platforms and the optimal temperature squeezing can be achieved with an optical Q around 106-107 that is readily available in various current devices. The proposed photothermal temperature squeezing is expected to have profound impact on broad applications of high-Q cavities in sensing, metrology, and integrated nonlinear/quantum photonics.

  3. Performance of the INTPIX6 SOI pixel detector

    International Nuclear Information System (INIS)

    Arai, Y.; Miyoshi, T.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Turala, M.; Kucewicz, W.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ  m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241 Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e − . The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e − . The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  4. Méditation et pratique de soi chez Malebranche.

    Directory of Open Access Journals (Sweden)

    Éric Dubreucq

    2004-04-01

    Full Text Available Une étude des Méditations pour se disposer à l’Humilité et à la pénitence qui les replace dans le cadre des pratiques de son époque, par exemple, chez François de Sales, celles de l’oraison, de la méditation et de la contemplation, permet d’apercevoir que l’une des thèses majeures du malebranchisme, la vision en Dieu, est un effet instauré dans le destinataire par un dispositif textuel. Celui-ci tire sa puissance prescriptive de l’a priori pratique où il s’inscrit. C’est à une opération de production de soi que l’exercice spirituel donne lieu : l’analyse des quatre premières Méditations chrétiennes et métaphysiques, en particulier, montre que c’est une organisation de la substance personnelle que provoque le travail spirituel sur soi. Celui-ci consiste à déterminer le rapport à soi comme relation d’une vision attentive à une activité illuminante, par un décentrement textuel du « je » vers le « tu ».One of the major Malebranche’s assertion, that we see truth in God, is not a mere theoretical thesis. I study first the Méditations pour se disposer à l’Humilité et à la pénitence and compare them with François de Sales’ spiritual exercitations, and show that prayer, meditation and contemplation constitute the practical frameworks of this period. The text of the Méditations is an apparatus which is fit to cause an effect in its target – the self of the reader : the vision in God. The practical a priori of the meditation provides the text with prescriptive power to transform the self. Then I study the Méditations chrétiennes et métaphysiques i-iv : we see that Malebranche set his textual apparatus so that it prescribes its receiver a form of « work-on-one’s-self ». The self is here produced by the organisation of relationship between attentive vision and lighting action, and this structure is built in the self by a movement, induced by the text, which leads the self from

  5. Observation of the fundamental Nyquist noise limit in an ultra-high Q-factor cryogenic bulk acoustic wave cavity

    Energy Technology Data Exchange (ETDEWEB)

    Goryachev, Maxim, E-mail: maxim.goryachev@uwa.edu.au; Ivanov, Eugene N.; Tobar, Michael E. [ARC Centre of Excellence for Engineered Quantum Systems, University of Western Australia, 35 Stirling Highway, Crawley, WA 6009 (Australia); Kann, Frank van [School of Physics, University of Western Australia, 35 Stirling Highway, Crawley, WA 6009 (Australia); Galliou, Serge [Department of Time and Frequency, FEMTO-ST Institute, ENSMM, 26 Chemin de l' Épitaphe, 25000 Besançon (France)

    2014-10-13

    Thermal Nyquist noise fluctuations of high-Q bulk acoustic wave cavities have been observed at cryogenic temperatures with a DC superconducting quantum interference device amplifier. High Q modes with bandwidths of few tens of milliHz produce thermal fluctuations with a signal-to-noise ratio of up to 23 dB. The estimated effective temperature from the Nyquist noise is in good agreement with the physical temperature of the device, confirming the validity of the equivalent circuit model and the non-existence of any excess resonator self-noise. The measurements also confirm that the quality factor remains extremely high (Q > 10{sup 8} at low order overtones) for very weak (thermal) system motion at low temperatures, when compared to values measured with relatively strong external excitation. This result represents an enabling step towards operating such a high-Q acoustic device at the standard quantum limit.

  6. L’estime de soi : un cas particulier d’estime sociale ?

    OpenAIRE

    Santarelli, Matteo

    2016-01-01

    Un des traits plus originaux de la théorie intersubjective de la reconnaissance d’Axel Honneth, consiste dans la façon dont elle discute la relation entre estime sociale et estime de soi. En particulier, Honneth présente l’estime de soi comme un reflet de l’estime sociale au niveau individuel. Dans cet article, je discute cette conception, en posant la question suivante : l’estime de soi est-elle un cas particulier de l’estime sociale ? Pour ce faire, je me concentre sur deux problèmes crucia...

  7. Special Issue: Planar Fully-Depleted SOI technology

    Science.gov (United States)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  8. Effects of finite temperature on two-photon transitions in a Rydberg atom in a high-Q cavity

    International Nuclear Information System (INIS)

    Puri, R.R.; Joshi, A.

    1989-01-01

    The effects of cavity temperature on an effective two-level atom undergoing two-photon transitions in a high-Q cavity are investigated. The quantum statistical properties of the field and the dynamical properties of the atom in this case are studied and compared with those for an atom making one-photon transitions between the two levels. The analysis is based on the solution of the equation for the density matrix in the secular approximation which is known to be a valid approximation in the case of a Rydberg atom in a high-Q cavity. (orig.)

  9. Fiber-Optic Refractometer Based on an Etched High-Q ?-Phase-Shifted Fiber-Bragg-Grating

    OpenAIRE

    Zhang, Qi; Ianno, Natale J.; Han, Ming

    2013-01-01

    We present a compact and highly-sensitive fiber-optic refractometer based on a high-Q p-phase-shifted fiber-Bragg-grating (pFBG) that is chemically etched to the core of the fiber. Due to the p phase-shift, a strong pFBG forms a high-Q optical resonator and the reflection spectrum features an extremely narrow notch that can be used for highly sensitivity refractive index measurement. The etched pFBG demonstrated here has a diameter of ~9.3 μm and a length of only 7 mm, leading to a refractive...

  10. Nucleon form factors at high q2 within constituent quark models

    International Nuclear Information System (INIS)

    Desplanques, B.; Silvestre-Brac, B.; Cano, F.; Noguera, S.; Gonzalez, P.; .

    2000-01-01

    The nucleon form factors are calculated using a non-relativistic description in terms of constituent quarks. The emphasis is put on present numerical methods used to solve the three-body problem in order to reliably predict the expected asymptotic behavior of form factors. Nucleon wave functions obtained in the hyperspherical formalism or employing Faddeev equations have been considered. While a q -8 behavior is expected at high q for a quark-quark force behaving like 1/r at short distances, it is found that the hyper central approximation in the hyperspherical formalism (K = 0) leads to a q -7 behavior. An infinite set of waves would be required to get the correct behavior. Solutions of the Faddeev equations lead to the q -8 behavior. The coefficient of the corresponding term, however, depends on the number of partial waves retained in the Faddeev amplitude. The convergence to the asymptotic behavior has also been studied. Approximate expressions characterizing this one have been derived. From the comparison with the most complete Faddeev calculation, a validity range is inferred for restricted calculations. Refs. 46 (author)

  11. Coherent stacking of picosecond laser pulses in a high-Q optical cavity for accelerator applications

    International Nuclear Information System (INIS)

    Androsov, V.P.; Karnaukhov, I.M.; Telegin, Yu.N.

    2007-01-01

    We have performed the harmonic analysis of the steady-state coherent pulse-stacking process in a high-Q Fabry-Perot cavity. The expression for the stacked pulse shape is obtained as a function of both the laser cavity and pulse-stacking cavity parameters. We have also estimated the pulse power gains attainable in the laser-optical system of NESTOR storage ring, which is under development at Kharkov Institute of Physics and Technology. It is shown that high power gains (∼10 4 ) can be, in principle, achieved in a cavity, formed with low-absorption, high reflectivity (R ∼ 0.9999) mirrors, if the laser cavity length will differ exactly by half wavelength from the pulse-stacking cavity length. It implies development of the sophisticated frequency stabilization loop for maintaining the cavity length constant within a sub-nanometer range. At the same time, power gains of ∼10 3 can be obtained with medium reflectivity mirrors (R ∼ 0.999) at considerably lower cost

  12. High-Q/V Monolithic Diamond Microdisks Fabricated with Quasi-isotropic Etching.

    Science.gov (United States)

    Khanaliloo, Behzad; Mitchell, Matthew; Hryciw, Aaron C; Barclay, Paul E

    2015-08-12

    Optical microcavities enhance light-matter interactions and are essential for many experiments in solid state quantum optics, optomechanics, and nonlinear optics. Single crystal diamond microcavities are particularly sought after for applications involving diamond quantum emitters, such as nitrogen vacancy centers, and for experiments that benefit from diamond's excellent optical and mechanical properties. Light-matter coupling rates in experiments involving microcavities typically scale with Q/V, where Q and V are the microcavity quality-factor and mode-volume, respectively. Here we demonstrate that microdisk whispering gallery mode cavities with high Q/V can be fabricated directly from bulk single crystal diamond. By using a quasi-isotropic oxygen plasma to etch along diamond crystal planes and undercut passivated diamond structures, we create monolithic diamond microdisks. Fiber taper based measurements show that these devices support TE- and TM-like optical modes with Q > 1.1 × 10(5) and V < 11(λ/n) (3) at a wavelength of 1.5 μm.

  13. First results of a Double-SOI pixel chip for X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Yunpeng, E-mail: yplu@ihep.ac.cn [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Ouyang, Qun [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Arai, Yasuo [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801 (Japan); Liu, Yi; Wu, Zhigang; Zhou, Yang [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China)

    2016-09-21

    Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I–V curve. An s-curve fitting resulted in a sigma of 153 e{sup −} among which equivalent noise charge (ENC) contributed 113 e{sup −}. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

  14. New Insights into Fully-Depleted SOI Transistor Response During Total Dose Irradiation

    International Nuclear Information System (INIS)

    Burns, J.A.; Dodd, P.E.; Keast, C.L.; Schwank, J.R.; Shaneyfelt, M.R.; Wyatt, P.W.

    1999-01-01

    Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. No evidence was found for total-dose induced snap back. These results have implications for hardness assurance testing

  15. Le soi et l’estime de soi chez l’enfant: Une revue systématique de la littérature

    OpenAIRE

    Pinto, Alexandra Maria Pereira Inácio Sequeira; Gatinho, Ana Rita dos Santos; Tereno, Susana; Veríssimo, Manuela

    2016-01-01

    Cette étude vise : a) à analyser les différentes méthodes utilisées pour l’étude du Soi et chez les enfants, en ce que concerne sa qualité et son potentiel et b) à synthétiser les résultats déjà obtenus en termes de Soi/d’estime de soi/d’autoconcept, pour les enfants en âge préscolaire. Après avoir établi des critères rigoureux d’inclusion et d’exclusion, 33 articles ont été sélectionnés, dans plusieurs bases de données, nationales et international...

  16. Deep sub-micron FD-SOI for front-end application

    International Nuclear Information System (INIS)

    Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

    2007-01-01

    In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

  17. Micromachined thin-film sensors for SOI-CMOS co-integration

    CERN Document Server

    Laconte, Jean; Raskin, Jean-Pierre

    2006-01-01

    Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

  18. Generation and confinement of mobile charges in buried oxide of SOI substrates; Generation et confinement de charges mobiles dans les oxydes enterres de substrats SOI

    Energy Technology Data Exchange (ETDEWEB)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A. [CEA Bruyeres-le-Chatel, DIF, 91 (France)

    1999-07-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO{sub 2} interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  19. Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2013-01-01

    Full Text Available Ultrathin body (UTB and nanoscale body (NSB SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

  20. Beam induced rf cavity transient voltage

    International Nuclear Information System (INIS)

    Kramer, S.L.; Wang, J.M.

    1998-10-01

    The authors calculate the transient voltage induced in a radio frequency cavity by the injection of a relativistic bunched beam into a circular accelerator. A simplified model of the beam induced voltage, using a single tone current signal, is generated and compared with the voltage induced by a more realistic model of a point-like bunched beam. The high Q limit of the bunched beam model is shown to be related simply to the simplified model. Both models are shown to induce voltages at the resonant frequency ω r of the cavity and at an integer multiple of the bunch revolution frequency (i.e. the accelerating frequency for powered cavity operation) hω ο . The presence of two nearby frequencies in the cavity leads to a modulation of the carrier wave exp(hω ο t). A special emphasis is placed in this paper on studying the modulation function. These models prove useful for computing the transient voltage induced in superconducting rf cavities, which was the motivation behind this research. The modulation of the transient cavity voltage discussed in this paper is the physical basis of the recently observed and explained new kinds of longitudinal rigid dipole mode which differs from the conventional Robinson mode

  1. Development of Electromechanical Architectures for AC Voltage Metrology

    Directory of Open Access Journals (Sweden)

    Alexandre BOUNOUH

    2010-12-01

    Full Text Available This paper presents results of work undertaken for exploring MEMS capabilities to fabricate AC voltage references for electrical metrology and high precision instrumentation through the mechanical-electrical coupling in MEMS. From first MEMS test structures previously realized, a second set of devices with improved characteristics has been developed and fabricated with Silicon on Insulator (SOI Surface Micromachining process. These MEMS exhibit pull-in voltages of 5 V and 10 V to match with the best performance of the read-out electronics developed for driving the MEMS. Deep Level Transient Spectroscopy measurements carried out on the new design show resonance frequencies of about only some kHz, and the stability of the MEMS output voltage measured at 100 kHz has been found very promising for the best samples where the relative deviation from the mean value over almost 12 hours showed a standard deviation of about 6.3 ppm.

  2. μ-'Diving suit' for liquid-phase high-Q resonant detection.

    Science.gov (United States)

    Yu, Haitao; Chen, Ying; Xu, Pengcheng; Xu, Tiegang; Bao, Yuyang; Li, Xinxin

    2016-03-07

    A resonant cantilever sensor is, for the first time, dressed in a water-proof 'diving suit' for real-time bio/chemical detection in liquid. The μ-'diving suit' technology can effectively avoid not only unsustainable resonance due to heavy liquid-damping, but also inevitable nonspecific adsorption on the cantilever body. Such a novel technology ensures long-time high-Q resonance of the cantilever in solution environment for real-time trace-concentration bio/chemical detection and analysis. After the formation of the integrated resonant micro-cantilever, a patterned photoresist and hydrophobic parylene thin-film are sequentially formed on top of the cantilever as sacrificial layer and water-proof coat, respectively. After sacrificial-layer release, an air gap is formed between the parylene coat and the cantilever to protect the resonant cantilever from heavy liquid damping effect. Only a small sensing-pool area, located at the cantilever free-end and locally coated with specific sensing-material, is exposed to the liquid analyte for gravimetric detection. The specifically adsorbed analyte mass can be real-time detected by recording the frequency-shift signal. In order to secure vibration movement of the cantilever and, simultaneously, reject liquid leakage from the sensing-pool region, a hydrophobic parylene made narrow slit structure is designed surrounding the sensing-pool. The anti-leakage effect of the narrow slit and damping limited resonance Q-factor are modelled and optimally designed. Integrated with electro-thermal resonance excitation and piezoresistive frequency readout, the cantilever is embedded in a micro-fluidic chip to form a lab-chip micro-system for liquid-phase bio/chemical detection. Experimental results show the Q-factor of 23 in water and longer than 20 hours liquid-phase continuous working time. Loaded with two kinds of sensing-materials at the sensing-pools, two types of sensing chips successfully show real-time liquid-phase detection to ppb

  3. Investigation of AWG demultiplexer based SOI for CWDM application

    Directory of Open Access Journals (Sweden)

    Juhari Nurjuliana

    2017-01-01

    Full Text Available 9-channel Arrayed Waveguide Grating (AWG demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n~3.47 material namely silicon-on-insulator (SOI with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM wavelength grid.

  4. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  5. High-Q contacted ring microcavities with scatterer-avoiding “wiggler” Bloch wave supermode fields

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Yangyang, E-mail: yangyang.liu@colorado.edu; Popović, Miloš A., E-mail: milos.popovic@colorado.edu [Nanophotonic Systems Laboratory, Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, Colorado 80309 (United States)

    2014-05-19

    High-Q ring resonators with contacts to the waveguide core provide a versatile platform for various applications in chip-scale optomechanics, thermo-, and electro-optics. We propose and demonstrate azimuthally periodic contacted ring resonators based on multi-mode Bloch matching that support contacts on both the inner and outer radius edges with small degradation to the optical quality factor (Q). Radiative coupling between degenerate modes of adjacent radial spatial order leads to imaginary frequency (Q) splitting and a scatterer avoiding high-Q “wiggler” supermode field. We experimentally measure Qs up to 258 000 in devices fabricated in a silicon device layer on buried oxide undercladding and up to 139 000 in devices fully suspended in air using an undercut step. Wiggler supermodes are true modes of the microphotonic system that offer additional degrees of freedom in electrical, thermal, and mechanical design.

  6. Carbon Nanofiber-Based, High-Frequency, High-Q, Miniaturized Mechanical Resonators

    Science.gov (United States)

    Kaul, Anupama B.; Epp, Larry W.; Bagge, Leif

    2011-01-01

    High Q resonators are a critical component of stable, low-noise communication systems, radar, and precise timing applications such as atomic clocks. In electronic resonators based on Si integrated circuits, resistive losses increase as a result of the continued reduction in device dimensions, which decreases their Q values. On the other hand, due to the mechanical construct of bulk acoustic wave (BAW) and surface acoustic wave (SAW) resonators, such loss mechanisms are absent, enabling higher Q-values for both BAW and SAW resonators compared to their electronic counterparts. The other advantages of mechanical resonators are their inherently higher radiation tolerance, a factor that makes them attractive for NASA s extreme environment planetary missions, for example to the Jovian environments where the radiation doses are at hostile levels. Despite these advantages, both BAW and SAW resonators suffer from low resonant frequencies and they are also physically large, which precludes their integration into miniaturized electronic systems. Because there is a need to move the resonant frequency of oscillators to the order of gigahertz, new technologies and materials are being investigated that will make performance at those frequencies attainable. By moving to nanoscale structures, in this case vertically oriented, cantilevered carbon nanotubes (CNTs), that have larger aspect ratios (length/thickness) and extremely high elastic moduli, it is possible to overcome the two disadvantages of both bulk acoustic wave (BAW) and surface acoustic wave (SAW) resonators. Nano-electro-mechanical systems (NEMS) that utilize high aspect ratio nanomaterials exhibiting high elastic moduli (e.g., carbon-based nanomaterials) benefit from high Qs, operate at high frequency, and have small force constants that translate to high responsivity that results in improved sensitivity, lower power consumption, and im - proved tunablity. NEMS resonators have recently been demonstrated using topdown

  7. Reduced nonlinearities in 100-nm high SOI waveguides

    Science.gov (United States)

    Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

    2016-03-01

    Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

  8. Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

    2012-01-01

    The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

  9. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  10. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  11. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  12. High-Q microsphere resonators for angular velocity sensing in gyroscopes

    International Nuclear Information System (INIS)

    An, Panlong; Zheng, Yongqiu; Yan, Shubin; Xue, Chenyang; Liu, Jun; Wang, Wanjun

    2015-01-01

    A resonator gyroscope based on the Sagnac effect is proposed using a core unit that is generated by water-hydrogen flame melting. The relationship between the quality factor Q and diameter D is revealed. The Q factor of the spectral lines of the microsphere cavity coupling system, which uses tapered fibers, is found to be 10 6 or more before packaging with a low refractive curable ultraviolet polymer, although it drops to approximately 10 5 after packaging. In addition, a rotating test platform is built, and the transmission spectrum and discriminator curves of a microsphere cavity with Q of 3.22×10 6 are measured using a semiconductor laser (linewidth less than 1 kHz) and a real-time proportional-integral circuit tracking and feedback technique. Equations fitting the relation between the voltage and angular rotation rate are obtained. According to the experimentally measured parameters, the sensitivity of the microsphere-coupled system can reach 0.095 ∘ /s

  13. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2017-08-01

    Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

  14. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  15. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  16. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  17. Towards Polarization Diversity on the SOI Platform With Simple Fabrication Process

    DEFF Research Database (Denmark)

    Ding, Yunhong; Liu, Liu; Peucheret, Christophe

    2011-01-01

    We present a polarization diversity circuit built on the silicon-on-insulator (SOI) platform, which can be fabricated by a simple process. The polarization diversity is based on two identical air-clad asymmetrical directional couplers, which simultaneously play the roles of polarization splitter...... and rotator. A silicon polarization diversity circuit with a single microring resonator is fabricated on the SOI platform. Only ${1-dB polarization-dependent loss is demonstrated. A significant improvement of the polarization dependence is obtained for 20-Gb/s nonreturn-to-zero differential phase-shift keying...

  18. Charge collection mechanisms in MOS/SOI transistors irradiated by energetic heavy ions

    International Nuclear Information System (INIS)

    Musseau, O.; Leray, J.L.; Ferlet, V.; Umbert, A.; Coic, Y.M.; Hesto, P.

    1991-01-01

    We have investigated with both experimental and numerical methods (Monte Carlo and drift-diffusion models) various charge collection mechanisms in NMOS/SOI transistors irradiated by single energetic heavy ions. Our physical interpretations of data emphasize the influence of various parasitic structures of the device. Two charge collection mechanisms are detailed: substrate funneling in buried MOS capacitor and latching of the parasitic bipolar transistor. Based on carrier transport and charge collection, the sensitivity of future scaled down CMOS/SOI technologies is finally discussed

  19. Generation and confinement of mobile charges in buried oxide of SOI substrates

    International Nuclear Information System (INIS)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A.

    1999-01-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO 2 interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  20. A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

    Science.gov (United States)

    Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

    2016-03-01

    Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

  1. Improvement of SOI microdosimeter performance using pulse shape discrimination techniques

    International Nuclear Information System (INIS)

    Cornelius, I.

    2002-01-01

    Full text: Microdosimetry is used to study the radiobiological properties of densely ionising radiations encountered in hadron therapy and space environments by measuring energy deposition in microscopic volumes. The creation of a solid state microdosimeter to replace the traditional tissue equivalent proportional counter is a topic of ongoing research. The Centre for Medical Radiation Physics has been investigating a technique using microscopic arrays of reverse biased pn junctions to measure the linear energy transfer of ions. A prototype silicon-on-insulator (SOI) microdosimeter was developed and measurements were conducted at boron neutron capture therapy, proton therapy, and fast neutron therapy facilities. Previous studies have shown the current microdosimeter possesses a poorly defined sensitive volume, a consequence of charge collection events being measured for ion strikes outside the pn junction via the diffusion of charge carriers. As a result, the amount of charge collected by the microdosimeter following an ion strike has a strong dependence on the location of the strike on the device and the angle of incidence of the ion. The aim of this work was to investigate the use of pulse shape discrimination (PSD) techniques to preclude the acquisition of events resulting from ion strikes outside the depletion region of the pn junction. Experiments were carried out using the Heavy Ion Microprobe (HIMP) at the Australian Nuclear Science and Technology Organisation, Lucas Heights, Australia. The HIMP was used to measure the charge collection time as a function of ion strike location on the microdosimeter array. As expected, the charge collection time was seen to increase monotonically as the distance of the ion strike from the junction increased. The charge collection time corresponding to ion strikes within the junction was determined. Through use of suitable electronics it was possible to gate the charge collection signal based on simultaneous measurements of

  2. Fano resonances in a high-Q terahertz whispering-gallery mode resonator coupled to a multi-mode waveguide.

    Science.gov (United States)

    Vogt, Dominik Walter; Leonhardt, Rainer

    2017-11-01

    We report on Fano resonances in a high-quality (Q) whispering-gallery mode (WGM) spherical resonator coupled to a multi-mode waveguide in the terahertz (THz) frequency range. The asymmetric line shape and phase of the Fano resonances detected with coherent continuous-wave (CW) THz spectroscopy measurements are in excellent agreement with the analytical model. A very high Q factor of 1600, and a finesse of 22 at critical coupling is observed around 0.35 THz. To the best of our knowledge this is the highest Q factor ever reported for a THz WGM resonator.

  3. Voltage regulating circuit

    NARCIS (Netherlands)

    2005-01-01

    A voltage regulating circuit comprising a rectifier (2) for receiving an AC voltage (Vmains) and for generating a rectified AC voltage (vrec), and a capacitor (3) connected in parallel with said rectified AC voltage for providing a DC voltage (VDC) over a load (5), characterized by a unidirectional

  4. Structural studies of WO3-TeO2 glasses by high-Q-neutron diffraction and Raman spectroscopy

    International Nuclear Information System (INIS)

    Khanna, A.; Kaur, A.; Krishna, P.S.R.; Shinde, A.B.

    2013-01-01

    Glasses from the system: xWO 3 -(100-x)TeO 2 (x=15, 20 and 25 mol %) were prepared by melt quenching technique and characterized by density, UV-visible absorption spectroscopy, Differential Scanning Calorimetry (DSC), Raman spectroscopy and high-Q neutron diffraction measurements. Glass density and glass transition temperature increased with increase in WO 3 concentration, Raman spectroscopy indicated the conversion of TeO 4 units into TeO 3 units with increase in WO 3 content. The increase in glass transition temperature with the incorporation of WO 3 was attributed to the increase in average bond strength of the glass network since the bond dissociation energy of W-O bonds (672 kJ/mol) is significantly higher than that of Te-O bonds (376 kJ/mol). UV-visible studies found a very strong optical absorption band due to W 6+ ions, just below the absorption edge. High-Q neutron diffraction measurements were performed on glasses and radial distribution function analyses revealed changes in W-O and Te-O correlations in the glass network. The findings about changes in glass structure from neutron diffraction studies were consistent with structural information obtained from Raman spectroscopy and structure-property correlations were made. (author)

  5. Fiber-optic refractometer based on an etched high-Q π-phase-shifted fiber-Bragg-grating.

    Science.gov (United States)

    Zhang, Qi; Ianno, Natale J; Han, Ming

    2013-07-10

    We present a compact and highly-sensitive fiber-optic refractometer based on a high-Q π-phase-shifted fiber-Bragg-grating (πFBG) that is chemically etched to the core of the fiber. Due to the p phase-shift, a strong πFBG forms a high-Q optical resonator and the reflection spectrum features an extremely narrow notch that can be used for highly sensitivity refractive index measurement. The etched πFBG demonstrated here has a diameter of ~9.3 μm and a length of only 7 mm, leading to a refractive index responsivity of 2.9 nm/RIU (RIU: refractive index unit) at an ambient refractive index of 1.318. The reflection spectrum of the etched πFBG features an extremely narrow notch with a linewidth of only 2.1 pm in water centered at ~1,550 nm, corresponding to a Q-factor of 7.4 × 10(5), which allows for potentially significantly improved sensitivity over refractometers based on regular fiber Bragg gratings.

  6. Fiber-Optic Refractometer Based on an Etched High-Q π-Phase-Shifted Fiber-Bragg-Grating

    Directory of Open Access Journals (Sweden)

    Ming Han

    2013-07-01

    Full Text Available We present a compact and highly-sensitive fiber-optic refractometer based on a high-Q p-phase-shifted fiber-Bragg-grating (pFBG that is chemically etched to the core of the fiber. Due to the p phase-shift, a strong pFBG forms a high-Q optical resonator and the reflection spectrum features an extremely narrow notch that can be used for highly sensitivity refractive index measurement. The etched pFBG demonstrated here has a diameter of ~9.3 μm and a length of only 7 mm, leading to a refractive index responsivity of 2.9 nm/RIU (RIU: refractive index unit at an ambient refractive index of 1.318. The reflection spectrum of the etched pFBG features an extremely narrow notch with a linewidth of only 2.1 pm in water centered at ~1,550 nm, corresponding to a Q-factor of 7.4 ´ 105, which allows for potentially significantly improved sensitivity over refractometers based on regular fiber Bragg gratings.

  7. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  8. Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

    2012-01-01

    Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

  9. Extreme group index measured and calculated in 2D SOI-based photonic crystal waveguides

    DEFF Research Database (Denmark)

    Lavrinenko, Andrei; Jacobsen, Rune Shim; Fage-Pedersen, Jacob

    2005-01-01

    lattice of air-holes in the 216-nm thick silicon layer in an SOI material. Experimental transmission spectra show a mode cut-off around 1562.5 nm for the fundamental photonic bandgap mode. In order to measure and model the group index of modes in the PCW, a time-of-flight (ToF) method is applied....

  10. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  11. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    Science.gov (United States)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  12. An analysis of radiation effects on electronics and soi-mos devices as an alternative

    International Nuclear Information System (INIS)

    Ikraiam, F. A.

    2013-01-01

    The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

  13. Juan Goytisolo: Le soi, le monde et la création littéraire

    Directory of Open Access Journals (Sweden)

    Pablo Romero Alegría

    2010-01-01

    Full Text Available Reseña de la obra: Yannick Llored. Le soi, le monde et la création littéraire. Presses Universitaires du Septentrion. Villeneuve d’Ascq (Francia. 2009. 421 págs. ISBN: 978-2-75740-0089-0

  14. Voltage-driven versus current-driven spin torque in anisotropic tunneling junctions

    KAUST Repository

    Manchon, Aurelien

    2011-01-01

    Nonequilibrium spin transport in a magnetic tunnel junction comprising a single magnetic layer in the presence of interfacial spin-orbit interaction (SOI) is studied theoretically. The interfacial SOI generates a spin torque of the form T=T∥ M×(z× M)+T⊥ z× M, even in the absence of an external spin polarizer. For thick and large tunnel barriers, the torque reduces to the perpendicular component T⊥, which can be electrically tuned by applying a voltage across the insulator. In the limit of thin and low tunnel barriers, the in-plane torque T∥ emerges, proportional to the tunneling current density. Experimental implications on magnetic devices are discussed. © 2011 IEEE.

  15. Voltage-driven versus current-driven spin torque in anisotropic tunneling junctions

    KAUST Repository

    Manchon, Aurelien

    2011-10-01

    Nonequilibrium spin transport in a magnetic tunnel junction comprising a single magnetic layer in the presence of interfacial spin-orbit interaction (SOI) is studied theoretically. The interfacial SOI generates a spin torque of the form T=T∥ M×(z× M)+T⊥ z× M, even in the absence of an external spin polarizer. For thick and large tunnel barriers, the torque reduces to the perpendicular component T⊥, which can be electrically tuned by applying a voltage across the insulator. In the limit of thin and low tunnel barriers, the in-plane torque T∥ emerges, proportional to the tunneling current density. Experimental implications on magnetic devices are discussed. © 2011 IEEE.

  16. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    Science.gov (United States)

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-08-18

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  17. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    Directory of Open Access Journals (Sweden)

    Ha-Duong Ngo

    2015-08-01

    Full Text Available In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load with an accuracy of 0.25% Full Scale Output (FSO. A push rod (mounted onto the steel membrane transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process. A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  18. Temporal Bell-type inequalities for two-level Rydberg atoms coupled to a high-Q resonator

    International Nuclear Information System (INIS)

    Huelga, S.F.; Marshall, T.W.; Santos, E.

    1996-01-01

    Following the strategy of showing specific quantum effects by means of the violation of a classical inequality, a pair of Bell-type inequalities is derived on the basis of certain additional assumptions, whose plausibility is discussed in detail. Such inequalities are violated by the quantum mechanical predictions for the interaction of a two-level Rydberg atom with a single mode sustained by a high-Q resonator. The experimental conditions required in order to show the existence of forbidden values, according to a hidden variables formalism, in a real experiment are analyzed for various initial field statistics. In particular, the revival dynamics expected for the interaction with a coherent field leads to classically forbidden values, which would indicate a purely quantum effect. copyright 1996 The American Physical Society

  19. Measurement of charged and neutral current e-p deep inelastic scattering cross sections at high Q2

    International Nuclear Information System (INIS)

    Derrick, M.; Krakauer, D.; Magill, S.

    1995-03-01

    Deep inelastic e - p scattering has been studied in both the charged current (CC) and neutral current (NC) reactions at momentum transfers squared, Q 2 , between 400 GeV 2 and the kinematic limit of 87500 GeV 2 using the ZEUS detector at the HERA ep collider. The CC and NC total cross sections, the NC to CC cross section ratio, and the differential cross sections, dσ/dQ 2 , are presented. For Q 2 ∝M W 2 , where M W is the mass of the W boson, the CC and NC cross sections have comparable magnitudes, demonstrating the equal strengths of the weak and electromagnetic interactions at high Q 2 . The Q 2 dependence of the CC cross section determines the mass term in the CC propagator to be M W =76±16±13 GeV. (orig.)

  20. Coupling single NV-centres to high-Q whispering gallery modes of a preselected frequency-matched microresonator

    International Nuclear Information System (INIS)

    Schietinger, Stefan; Benson, Oliver

    2009-01-01

    In this paper, we report the controlled coupling of fluorescence from a single NV-centre in a single nanodiamond to the high-Q modes of a preselected microsphere. Microspheres from an ensemble with a finite size distribution can be characterized precisely via white light Mie-scattering. The mode spectrum of individual spheres can be determined with high precision. A sphere with an appropriate spectrum can be selected, and a nanodiamond containing a single NV-centre can be coupled to it. The spectral position of the calculated lowest order whispering gallery modes are found to be in very good agreement with the experimentally observed resonances of the coupled fluorescence from the single NV-re.

  1. Theoretical study of high-Q Fano resonance and extrinsic chirality in an ultrathin Babinet-inverted metasurface

    Science.gov (United States)

    Wang, Feng; Wang, Zhengping; Shi, Jinhui

    2014-10-01

    A high-Q Fano resonance and giant extrinsic chirality have been demonstrated in an ultrathin Babinet-inverted metasurface composed of asymmetrical split ring apertures (ASRAs) perforated through a metal plate based on the full-wave simulations. The performance of the Fano resonance at normal incidence strongly depends on the asymmetry of the ASRA. The quality factor is larger than 1000 and the local field enhancement is an order of 104. For oblique incidence, giant extrinsic chirality can be achieved in the Babinet-inverted metasurface. It reveals a cross-polarization transmission band with a ripple-free peak and also a spectrum split for large angles of incidence. The electromagnetic response of the metasurface can be easily tuned via angles of incidence and asymmetry. The proposed ASRA metasurface is of importance to develop many metamaterial-based devices, such as filters and circular polarizers.

  2. Novel high-voltage power lateral MOSFET with adaptive buried electrodes

    International Nuclear Information System (INIS)

    Zhang Wen-Tong; Wu Li-Juan; Qiao Ming; Luo Xiao-Rong; Zhang Bo; Li Zhao-Ji

    2012-01-01

    A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and −587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  3. Comparative study of SOI/Si hybrid substrates fabricated using high-dose and low-dose oxygen implantation

    International Nuclear Information System (INIS)

    Dong Yemin; Chen Meng; Chen Jing; Wang Xiang; Wang Xi

    2004-01-01

    Hybrid substrates comprising both silicon-on-insulator (SOI) and bulk Si regions have been fabricated using the technique of patterned separation by implantation of oxygen (SIMOX) with high-dose (1.5 x 10 18 cm -2 ) and low-dose ((1.5-3.5) x 10 17 cm -2 ) oxygen ions, respectively. Cross-sectional transmission electron microscopy (XTEM) was employed to examine the microstructures of the resulting materials. Experimental results indicate that the SOI/Si hybrid substrate fabricated using high-dose SIMOX is of inferior quality with very large surface height step and heavily damaged transitions between the SOI and bulk regions. However, the quality of the SOI/Si hybrid substrate is enhanced dramatically by reducing the implant dose. The defect density in transitions is reduced considerably. Moreover, the expected surface height difference does not exist and the surface is exceptionally flat. The possible mechanisms responsible for the improvements in quality are discussed

  4. Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

    DEFF Research Database (Denmark)

    Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

    2014-01-01

    We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

  5. Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

    Directory of Open Access Journals (Sweden)

    A. Daghighi

    2013-09-01

    Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

  6. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  7. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    International Nuclear Information System (INIS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

  8. Superconducting nanowire single-photon detectors (SNSPDs) on SOI for near-infrared range

    Energy Technology Data Exchange (ETDEWEB)

    Trojan, Philipp; Il' in, Konstantin; Henrich, Dagmar; Hofherr, Matthias; Doerner, Steffen; Siegel, Michael [Institut fuer Mikro- und Nanoelektronische Systeme (IMS), Karlsruher Institut fuer Technologie (KIT) (Germany); Semenov, Alexey [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Huebers, Heinz-Wilhelm [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Institut fuer Optik und Atomare Physik, Technische Universitaet Berlin (Germany)

    2013-07-01

    Superconducting nanowire single-photon detectors are promising devices for photon detectors with high count rates, low dark count rates and low dead times. At wavelengths beyond the visible range, the detection efficiency of today's SNSPDs drops significantly. Moreover, the low absorption in ultra-thin detector films is a limiting factor over the entire spectral range. Solving this problem requires approaches for an enhancement of the absorption range in feeding the light to the detector element. A possibility to obtain a better absorption is the use of multilayer substrate materials for photonic waveguide structures. We present results on development of superconducting nanowire single-photon detectors made from niobium nitride on silicon-on-insulator (SOI) multilayer substrates. Optical and superconducting properties of SNSPDs on SOI will be discussed and compared with the characteristics of detectors on common substrates.

  9. New insights into fully-depleted SOI transistor response during total-dose irradiation

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.

    1999-01-01

    In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)

  10. Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

    Science.gov (United States)

    Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

    Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

  11. Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

    Science.gov (United States)

    Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

    2001-12-01

    We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

  12. Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

    International Nuclear Information System (INIS)

    Barchuk, I.P.; Kilchitskaya, V.I.; Lysenko, V.S.

    1997-01-01

    In this work SOI structures with buried SiO 2 -Si 3 N 4 -SiO 2 layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO 2 layers produced by either the ZMR or the SIMOX technique

  13. Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

    Directory of Open Access Journals (Sweden)

    Avi Karsenty

    2015-01-01

    Full Text Available Nanoscale Gate-Recessed Channel (GRC Fully Depleted- (FD- SOI MOSFET device with a silicon channel thickness (tSi as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

  14. 300 nm bandwidth adiabatic SOI polarization splitter-rotators exploiting continuous symmetry breaking.

    Science.gov (United States)

    Socci, Luciano; Sorianello, Vito; Romagnoli, Marco

    2015-07-27

    Adiabatic polarization splitter-rotators are investigated exploiting continuous symmetry breaking thereby achieving significant device size and losses reduction in a single mask fabrication process for both SOI channel and ridge waveguides. A crosstalk lower than -25 dB is expected over 300nm bandwidth, making the device suitable for full grid CWDM and diplexer/triplexer FTTH applications at 1310, 1490 and 1550nm.

  15. Formation of SIMOX–SOI structure by high-temperature oxygen implantation

    International Nuclear Information System (INIS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-01-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 10"1"7–10"1"8 ions/cm"2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO_2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO_2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  16. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  17. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    Science.gov (United States)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  18. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  19. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  20. Electron mobility in the inversion layers of fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2017-04-15

    The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

  1. High voltage systems

    International Nuclear Information System (INIS)

    Martin, M.

    1991-01-01

    Industrial processes usually require electrical power. This power is used to drive motors, to heat materials, or in electrochemical processes. Often the power requirements of a plant require the electric power to be delivered at high voltage. In this paper high voltage is considered any voltage over 600 V. This voltage could be as high as 138,000 V for some very large facilities. The characteristics of this voltage and the enormous amounts of power being transmitted necessitate special safety considerations. Safety must be considered during the four activities associated with a high voltage electrical system. These activities are: Design; Installation; Operation; and Maintenance

  2. Measurement of the neutral current reaction at high Q{sup 2} in the H1 experiment at HERA II

    Energy Technology Data Exchange (ETDEWEB)

    Shushkevich, Stanislav

    2012-12-15

    This thesis presents inclusive e{sup {+-}}p double and single differential cross section measurements for neutral current deep inelastic scattering of longitudinally polarized leptons on protons as a function of the negative four-momentum transfer squared Q{sup 2} and the Bjorken variable x. The data were collected in the years 2003-2007 in the H1 experiment at HERA with positively and negatively longitudinally polarized lepton beams of 27 GeV and a proton beam of 920 GeV corresponding to the centre-of-mass energy of {radical}(s)=319 GeV. The integrated luminosity is about 330 pb{sup -1}. An overview of the phenomenology of the deep inelastic scattering is given and the experimental apparatus is described. The NC cross section measurement procedure is presented and discussed in details. The measured cross sections are used to investigate electroweak effects at high Q{sup 2}. The proton structure function xF{sub 3}, sensitive to the valence quarks in the proton, is measured. The polarization effects sensitive to the chiral structure of neutral currents are investigated. The Standard Model predictions are found to be in a good agreement with the measurement.

  3. Measurement of high-Q2 neutral current cross-sections with longitudinally polarised positrons with the ZEUS detector

    International Nuclear Information System (INIS)

    Stewart, Trevor P.

    2012-07-01

    The cross sections for neutral current (NC) deep inelastic scattering (DIS) in e + p collisions with a longitudinally polarised positron beam are measured at high momentum transfer squared (Q 2 >185 GeV 2 ) at the ZEUS detector at HERA. The HERA accelerator provides e ± p collisions at a centre-of-mass energy of 318 GeV, which allows the weak contribution to the NC process to be studied at high Q 2 . The measurements are based on a data sample with an integrated luminosity of 135.5 pb -1 collected with the ZEUS detector in 2006 and 2007. The single differential NC cross sections dσ/dQ 2 , dσ/dx and dσ/dy and the reduced cross section σ are measured. The structure function xF 3 is determined by combining the e + p NC reduced cross sections with the previously measured e - p measurements. The interference structure function xF 3 γZ is extracted at Q 2 =1500 GeV 2 . The cross-section asymmetry between the positive and negative polarisation of the positron beam is measured and the parity violation effects of the electroweak interaction are observed. The predictions of the Standard Model of particle physics agree well with the measurements. (orig.)

  4. Proof-of-principle demonstration of Nb3Sn superconducting radiofrequency cavities for high Q0 applications

    Science.gov (United States)

    Posen, S.; Liepe, M.; Hall, D. L.

    2015-02-01

    Many future particle accelerators require hundreds of superconducting radiofrequency (SRF) cavities operating with high duty factor. The large dynamic heat load of the cavities causes the cryogenic plant to make up a significant part of the overall cost of the facility. This contribution can be reduced by replacing standard niobium cavities with ones coated with a low-dissipation superconductor such as Nb3Sn. In this paper, we present results for single cell cavities coated with Nb3Sn at Cornell. Five coatings were carried out, showing that at 4.2 K, high Q0 out to medium fields was reproducible, resulting in an average quench field of 14 MV/m and an average 4.2 K Q0 at quench of 8 × 109. In each case, the peak surface magnetic field at quench was well above Hc1, showing that it is not a limiting field in these cavities. The coating with the best performance had a quench field of 17 MV/m, exceeding gradient requirements for state-of-the-art high duty factor SRF accelerators. It is also shown that—taking into account the thermodynamic efficiency of the cryogenic plant—the 4.2 K Q0 values obtained meet the AC power consumption requirements of state-of-the-art high duty factor accelerators, making this a proof-of-principle demonstration for Nb3Sn cavities in future applications.

  5. Measurement of high-Q{sup 2} neutral current cross-sections with longitudinally polarised positrons with the ZEUS detector

    Energy Technology Data Exchange (ETDEWEB)

    Stewart, Trevor P.

    2012-07-15

    The cross sections for neutral current (NC) deep inelastic scattering (DIS) in e{sup +}p collisions with a longitudinally polarised positron beam are measured at high momentum transfer squared (Q{sup 2}>185 GeV{sup 2}) at the ZEUS detector at HERA. The HERA accelerator provides e{sup {+-}}p collisions at a centre-of-mass energy of 318 GeV, which allows the weak contribution to the NC process to be studied at high Q{sup 2}. The measurements are based on a data sample with an integrated luminosity of 135.5 pb{sup -1} collected with the ZEUS detector in 2006 and 2007. The single differential NC cross sections d{sigma}/dQ{sup 2}, d{sigma}/dx and d{sigma}/dy and the reduced cross section {sigma} are measured. The structure function xF{sub 3} is determined by combining the e{sup +}p NC reduced cross sections with the previously measured e{sup -}p measurements. The interference structure function xF{sub 3}{sup {gamma}Z} is extracted at Q{sup 2}=1500 GeV{sup 2}. The cross-section asymmetry between the positive and negative polarisation of the positron beam is measured and the parity violation effects of the electroweak interaction are observed. The predictions of the Standard Model of particle physics agree well with the measurements. (orig.)

  6. Voltage regulator for generator

    Energy Technology Data Exchange (ETDEWEB)

    Naoi, K

    1989-01-17

    It is an object of this invention to provide a voltage regulator for a generator charging a battery, wherein even if the ambient temperature at the voltage regulator rises abnormally high, possible thermal breakage of the semiconductor elements constituting the voltage regulator can be avoided. A feature of this invention is that the semiconductor elements can be protected from thermal breakage, even at an abnormal ambient temperature rise at the voltage regulator for the battery charging generator, by controlling a maximum conduction ratio of a power transistor in the voltage regulator in accordance with the temperature at the voltage regulator. This is achieved through a switching device connected in series to the field coil of the generator and adapted to be controlled in accordance with an output voltage of the generator and the ambient temperature at the voltage regulator. 6 figs.

  7. Automatic voltage imbalance detector

    Science.gov (United States)

    Bobbett, Ronald E.; McCormick, J. Byron; Kerwin, William J.

    1984-01-01

    A device for indicating and preventing damage to voltage cells such as galvanic cells and fuel cells connected in series by detecting sequential voltages and comparing these voltages to adjacent voltage cells. The device is implemented by using operational amplifiers and switching circuitry is provided by transistors. The device can be utilized in battery powered electric vehicles to prevent galvanic cell damage and also in series connected fuel cells to prevent fuel cell damage.

  8. A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

    International Nuclear Information System (INIS)

    Patil, Ganesh C; Qureshi, S

    2011-01-01

    In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

  9. Reduction of ripple voltage in a dynamitron

    International Nuclear Information System (INIS)

    Langsdorf, A. Jr.

    1982-01-01

    We determined that a precise neutralization of the RF ripple voltage on the high-voltage terminal of a Dynamitron has previously been prevented by a nonegligible phase shift of RF currents in the two halves of the approx. 100-kHz class C oscillator tank circuit, which is actually constituted of two slightly unequal high-Q coupled circuits because it has two ground points: the inescapable center-tap-ground in the capacitive legs and a center-tap-ground lead to the induction coil. The latter is needed to prevent damage by flashover transients; equivalent to its removal was the adjusting of RF ground return current to a null by aid of a current transformer on this lead and the suitable adjusting of trimmer capacitance. While the phase shift was thus held to a null, the actual ripple amplitude on the hv terminal was minimized by adjusting additional trimmer capacitances installed in the terminal of the machine. Then p/p 100-kHz ripple at 2-MV dc output was reduced to about 50V and RMS resolution by (p,#betta#) resonance threshold data near 1 MV was about 250 V. The limit to resolution has various causes including mechanical vibrations and unbalanced harmonics of the RF

  10. Demonstration of suppressed phonon tunneling losses in phononic bandgap shielded membrane resonators for high-Q optomechanics.

    Science.gov (United States)

    Tsaturyan, Yeghishe; Barg, Andreas; Simonsen, Anders; Villanueva, Luis Guillermo; Schmid, Silvan; Schliesser, Albert; Polzik, Eugene S

    2014-03-24

    Dielectric membranes with exceptional mechanical and optical properties present one of the most promising platforms in quantum opto-mechanics. The performance of stressed silicon nitride nanomembranes as mechanical resonators notoriously depends on how their frame is clamped to the sample mount, which in practice usually necessitates delicate, and difficult-to-reproduce mounting solutions. Here, we demonstrate that a phononic bandgap shield integrated in the membrane's silicon frame eliminates this dependence, by suppressing dissipation through phonon tunneling. We dry-etch the membrane's frame so that it assumes the form of a cm-sized bridge featuring a 1-dimensional periodic pattern, whose phononic density of states is tailored to exhibit one, or several, full band gaps around the membrane's high-Q modes in the MHz-range. We quantify the effectiveness of this phononic bandgap shield by optical interferometry measuring both the suppressed transmission of vibrations, as well as the influence of frame clamping conditions on the membrane modes. We find suppressions up to 40 dB and, for three different realized phononic structures, consistently observe significant suppression of the dependence of the membrane's modes on sample clamping-if the mode's frequency lies in the bandgap. As a result, we achieve membrane mode quality factors of 5 × 10(6) with samples that are tightly bolted to the 8 K-cold finger of a cryostat. Q × f -products of 6 × 10(12) Hz at 300 K and 14 × 10(12) Hz at 8 K are observed, satisfying one of the main requirements for optical cooling of mechanical vibrations to their quantum ground-state.

  11. Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

    International Nuclear Information System (INIS)

    Hamilton, J.J.; Collart, E.J.H.; Colombeau, B.; Jeynes, C.; Bersani, M.; Giubertoni, D.; Sharp, J.A.; Cowern, N.E.B.; Kirkby, K.J.

    2005-01-01

    The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface

  12. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  13. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-01-01

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

  14. A New Nonlinear Model of Body Resistance in Nanometer PD SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    Arash Daghighi

    2011-01-01

    Full Text Available In this paper, a nonlinear model for the body resistance of a 45nm PD SOI MOSFET is developed. This model verified on the base of the small signal three-dimensional simulation results. In this paper by using the three-dimensional simulation of ISE-TCAD software, the indicating factors of body resistance in nanometer transistors and then are shown, using the surface potential model. A mathematical relation to calculat the body resistance incorporating device width and body potential was derived. Excellent agreement was obtained by comparing the model outputs and three-dimensional simulation results.

  15. Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

    Science.gov (United States)

    Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

    2008-04-01

    We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

  16. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  17. Mapping the broadband polarization properties of linear 2D SOI photonic crystal waveguides

    DEFF Research Database (Denmark)

    Canning, John; Skivesen, Nina; Kristensen, Martin

    2007-01-01

    Both quasi-TE and TM polarisation spectra for a silicon- on-insulator (SOI) waveguide are recorded over (1100-1700) nm using a broadband supercontinuum source. By studying both the input and output polarisation eigenstates we observe narrowband resonant cross coupling near the lowest quasi-TE mode...... cut-off. We also observe relatively broadband mixing between the two eigenstates to generate a complete photonic bandgap. By careful analysis of the output polarisation state we report on an inherent non-reciprocity between quasi TE and TM fundamental mode cross coupling. The nature of polarisation...

  18. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...... Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize...

  19. Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

    2017-02-11

    We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

  20. A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

    Science.gov (United States)

    Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

    2012-12-01

    A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

  1. A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

    International Nuclear Information System (INIS)

    Lin, Jyi-Tsong; Lee, Tai-Yi; Lin, Kao-Cheng

    2008-01-01

    A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase

  2. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

    Science.gov (United States)

    Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

    2009-12-01

    The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

  3. Technological Aspects: High Voltage

    International Nuclear Information System (INIS)

    Faircloth, D C

    2013-01-01

    This paper covers the theory and technological aspects of high-voltage design for ion sources. Electric field strengths are critical to understanding high-voltage breakdown. The equations governing electric fields and the techniques to solve them are discussed. The fundamental physics of high-voltage breakdown and electrical discharges are outlined. Different types of electrical discharges are catalogued and their behaviour in environments ranging from air to vacuum are detailed. The importance of surfaces is discussed. The principles of designing electrodes and insulators are introduced. The use of high-voltage platforms and their relation to system design are discussed. The use of commercially available high-voltage technology such as connectors, feedthroughs and cables are considered. Different power supply technologies and their procurement are briefly outlined. High-voltage safety, electric shocks and system design rules are covered. (author)

  4. Technological Aspects: High Voltage

    CERN Document Server

    Faircloth, D.C.

    2013-12-16

    This paper covers the theory and technological aspects of high-voltage design for ion sources. Electric field strengths are critical to understanding high-voltage breakdown. The equations governing electric fields and the techniques to solve them are discussed. The fundamental physics of high-voltage breakdown and electrical discharges are outlined. Different types of electrical discharges are catalogued and their behaviour in environments ranging from air to vacuum are detailed. The importance of surfaces is discussed. The principles of designing electrodes and insulators are introduced. The use of high-voltage platforms and their relation to system design are discussed. The use of commercially available high-voltage technology such as connectors, feedthroughs and cables are considered. Different power supply technologies and their procurement are briefly outlined. High-voltage safety, electric shocks and system design rules are covered.

  5. Stray voltage mitigation

    Energy Technology Data Exchange (ETDEWEB)

    Jamali, B.; Piercy, R.; Dick, P. [Kinetrics Inc., Toronto, ON (Canada). Transmission and Distribution Technologies

    2008-04-09

    This report discussed issues related to farm stray voltage and evaluated mitigation strategies and costs for limiting voltage to farms. A 3-phase, 3-wire system with no neutral ground was used throughout North America before the 1930s. Transformers were connected phase to phase without any electrical connection between the primary and secondary sides of the transformers. Distribution voltage levels were then increased and multi-grounded neutral wires were added. The earth now forms a parallel return path for the neutral current that allows part of the neutral current to flow continuously through the earth. The arrangement is responsible for causing stray voltage. Stray voltage causes uneven milk production, increased incidences of mastitis, and can create a reluctance to drink water amongst cows when stray voltages are present. Off-farm sources of stray voltage include phase unbalances, undersized neutral wire, and high resistance splices on the neutral wire. Mitigation strategies for reducing stray voltage include phase balancing; conversion from single to 3-phase; increasing distribution voltage levels, and changing pole configurations. 22 refs., 5 tabs., 13 figs.

  6. High voltage engineering

    CERN Document Server

    Rizk, Farouk AM

    2014-01-01

    Inspired by a new revival of worldwide interest in extra-high-voltage (EHV) and ultra-high-voltage (UHV) transmission, High Voltage Engineering merges the latest research with the extensive experience of the best in the field to deliver a comprehensive treatment of electrical insulation systems for the next generation of utility engineers and electric power professionals. The book offers extensive coverage of the physical basis of high-voltage engineering, from insulation stress and strength to lightning attachment and protection and beyond. Presenting information critical to the design, selec

  7. High voltage test techniques

    CERN Document Server

    Kind, Dieter

    2001-01-01

    The second edition of High Voltage Test Techniques has been completely revised. The present revision takes into account the latest international developments in High Voltage and Measurement technology, making it an essential reference for engineers in the testing field.High Voltage Technology belongs to the traditional area of Electrical Engineering. However, this is not to say that the area has stood still. New insulating materials, computing methods and voltage levels repeatedly pose new problems or open up methods of solution; electromagnetic compatibility (EMC) or components and systems al

  8. Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

    Science.gov (United States)

    Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

    2018-04-01

    The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

  9. Interaction between beam control and rf feedback loops for high Q cavities an heavy beam loading. Revision A

    International Nuclear Information System (INIS)

    Mestha, L.K.; Kwan, C.M.; Yeung, K.S.

    1994-04-01

    An open-loop state space model of all the major low-level rf feedback control loops is derived. The model has control and state variables for fast-cycling machines to apply modern multivariable feedback techniques. A condition is derived to know when exactly we can cross the boundaries between time-varying and time-invariant approaches for a fast-cycling machine like the Low Energy Booster (LEB). The conditions are dependent on the Q of the cavity and the rate at which the frequency changes with time. Apart from capturing the time-variant characteristics, the errors in the magnetic field are accounted in the model to study the effects on synchronization with the Medium Energy Booster (MEB). The control model is useful to study the effects on beam control due to heavy beam loading at high intensities, voltage transients just after injection especially due to time-varying voltages, instability thresholds created by the cavity tuning feedback system, cross coupling between feedback loops with and without direct rf feedback etc. As a special case we have shown that the model agrees with the well known Pedersen model derived for the CERN PS booster. As an application of the model we undertook a detailed study of the cross coupling between the loops by considering all of them at once for varying time, Q and beam intensities. A discussion of the method to identify the coupling is shown. At the end a summary of the identified loop interactions is presented

  10. Development of an X-ray imaging system with SOI pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Nishimura, Ryutaro, E-mail: ryunishi@post.kek.jp [School of High Energy Accelerator Science, SOKENDAI (The Graduate University for Advanced Studies), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK-IPNS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo [Institute of Materials Structure Science, High Energy Accelerator Research Organization (KEK-IMSS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan)

    2016-09-21

    An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented. - Highlights: • The X-ray imaging system employing the SOI pixel sensor is currently under development. • The DAQ of the first prototype has the bottleneck in the total throughput. • The new DAQ release solve the bottleneck by parallel processing and FIFO buffer. • The new DAQ release was tested using 33.3 keV and 9.5 keV mono X-rays.

  11. Photonic bandpass filter characteristics of multimode SOI waveguides integrated with submicron gratings.

    Science.gov (United States)

    Sah, Parimal; Das, Bijoy Krishna

    2018-03-20

    It has been shown that a fundamental mode adiabatically launched into a multimode SOI waveguide with submicron grating offers well-defined flat-top bandpass filter characteristics in transmission. The transmitted spectral bandwidth is controlled by adjusting both waveguide and grating design parameters. The bandwidth is further narrowed down by cascading two gratings with detuned parameters. A semi-analytical model is used to analyze the filter characteristics (1500  nm≤λ≤1650  nm) of the device operating in transverse-electric polarization. The proposed devices were fabricated with an optimized set of design parameters in a SOI substrate with a device layer thickness of 250 nm. The pass bandwidth of waveguide devices integrated with single-stage gratings are measured to be ∼24  nm, whereas the device with two cascaded gratings with slightly detuned periods (ΔΛ=2  nm) exhibits a pass bandwidth down to ∼10  nm.

  12. Characterization of ultrathin SOI film and application to short channel MOSFETs.

    Science.gov (United States)

    Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

    2008-04-23

    In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

  13. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  14. Demonstration of a switchable damping system to allow low-noise operation of high-Q low-mass suspension systems

    Science.gov (United States)

    Hennig, Jan-Simon; Barr, Bryan W.; Bell, Angus S.; Cunningham, William; Danilishin, Stefan L.; Dupej, Peter; Gräf, Christian; Hough, James; Huttner, Sabina H.; Jones, Russell; Leavey, Sean S.; Pascucci, Daniela; Sinclair, Martin; Sorazu, Borja; Spencer, Andrew; Steinlechner, Sebastian; Strain, Kenneth A.; Wright, Jennifer; Zhang, Teng; Hild, Stefan

    2017-12-01

    Low-mass suspension systems with high-Q pendulum stages are used to enable quantum radiation pressure noise limited experiments. Utilizing multiple pendulum stages with vertical blade springs and materials with high-quality factors provides attenuation of seismic and thermal noise; however, damping of these high-Q pendulum systems in multiple degrees of freedom is essential for practical implementation. Viscous damping such as eddy-current damping can be employed, but it introduces displacement noise from force noise due to thermal fluctuations in the damping system. In this paper we demonstrate a passive damping system with adjustable damping strength as a solution for this problem that can be used for low-mass suspension systems without adding additional displacement noise in science mode. We show a reduction of the damping factor by a factor of 8 on a test suspension and provide a general optimization for this system.

  15. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits; Quantification, modelisation et conception prenant en compte les etats anterieurs des signaux dans les circuits mixtes SOI/SOS

    Energy Technology Data Exchange (ETDEWEB)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S. [Southampton Univ., Dept. of Electronics and Computer Sciences (United Kingdom); Uren, M.J.; Brunson, K.M. [DERA Farnborough, GU, Hants (United Kingdom)

    1999-07-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  16. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-03-03

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

  17. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  18. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

    International Nuclear Information System (INIS)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.; Uren, M.J.; Brunson, K.M.

    1999-01-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  19. A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

    Science.gov (United States)

    Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

    2010-01-01

    A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

  20. based dynamic voltage restorer

    African Journals Online (AJOL)

    HOD

    operation due to presence of increased use of nonlinear loads (computers, microcontrollers ... simulations of a dynamic voltage restorer (DVR) was achieved using MATLAB/Simulink. ..... using Discrete PWM generator, then the IGBT inverter.

  1. High voltage engineering fundamentals

    CERN Document Server

    Kuffel, E; Hammond, P

    1984-01-01

    Provides a comprehensive treatment of high voltage engineering fundamentals at the introductory and intermediate levels. It covers: techniques used for generation and measurement of high direct, alternating and surge voltages for general application in industrial testing and selected special examples found in basic research; analytical and numerical calculation of electrostatic fields in simple practical insulation system; basic ionisation and decay processes in gases and breakdown mechanisms of gaseous, liquid and solid dielectrics; partial discharges and modern discharge detectors; and over

  2. Low-voltage gyrotrons

    International Nuclear Information System (INIS)

    Glyavin, M. Yu.; Zavolskiy, N. A.; Sedov, A. S.; Nusinovich, G. S.

    2013-01-01

    For a long time, the gyrotrons were primarily developed for electron cyclotron heating and current drive of plasmas in controlled fusion reactors where a multi-megawatt, quasi-continuous millimeter-wave power is required. In addition to this important application, there are other applications (and their number increases with time) which do not require a very high power level, but such issues as the ability to operate at low voltages and have compact devices are very important. For example, gyrotrons are of interest for a dynamic nuclear polarization, which improves the sensitivity of the nuclear magnetic resonance spectroscopy. In this paper, some issues important for operation of gyrotrons driven by low-voltage electron beams are analyzed. An emphasis is made on the efficiency of low-voltage gyrotron operation at the fundamental and higher cyclotron harmonics. These efficiencies calculated with the account for ohmic losses were, first, determined in the framework of the generalized gyrotron theory based on the cold-cavity approximation. Then, more accurate, self-consistent calculations for the fundamental and second harmonic low-voltage sub-THz gyrotron designs were carried out. Results of these calculations are presented and discussed. It is shown that operation of the fundamental and second harmonic gyrotrons with noticeable efficiencies is possible even at voltages as low as 5–10 kV. Even the third harmonic gyrotrons can operate at voltages about 15 kV, albeit with rather low efficiency (1%–2% in the submillimeter wavelength region).

  3. Growth and characterization of InP/GaAs on SOI by MOCVD

    International Nuclear Information System (INIS)

    Karam, N.H.; Haven, V.; Vernon, S.M.; Namavar, F.; El-Masry, N.; Haegel, N.; Al-Jassin, M.M.

    1990-01-01

    This paper reports that epitaxial InP films have been successfully deposited on GaAs coated silicon wafers with a buried oxide for the first time by MOCVD. The SOI wafers were prepared using the Separation by Implantation of Oxygen (SIMOX) process. The quality of InP on SIMOX is comparable to the best of InP on Si deposited in the same reactor. Preliminary results on defect reduction techniques such as Thermal Cycle Growth (TCG) show an order of magnitude increase in the photoluminescence intensity and a factor of five reduction in the defect density. TCG has been found more effective than Thermal Cycle Annealing (TCA) in improving the crystalline perfection and optical properties of the deposited films

  4. Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

    Science.gov (United States)

    Katz, Oded; Malka, Dror

    2017-07-01

    In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

  5. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    International Nuclear Information System (INIS)

    Trimpl, M.; Deptuch, G.; Yarema, R.

    2010-01-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm 2 large detector array with 20 (micro)m and 40 (micro)m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  6. Device for monitoring cell voltage

    Science.gov (United States)

    Doepke, Matthias [Garbsen, DE; Eisermann, Henning [Edermissen, DE

    2012-08-21

    A device for monitoring a rechargeable battery having a number of electrically connected cells includes at least one current interruption switch for interrupting current flowing through at least one associated cell and a plurality of monitoring units for detecting cell voltage. Each monitoring unit is associated with a single cell and includes a reference voltage unit for producing a defined reference threshold voltage and a voltage comparison unit for comparing the reference threshold voltage with a partial cell voltage of the associated cell. The reference voltage unit is electrically supplied from the cell voltage of the associated cell. The voltage comparison unit is coupled to the at least one current interruption switch for interrupting the current of at least the current flowing through the associated cell, with a defined minimum difference between the reference threshold voltage and the partial cell voltage.

  7. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-01-01

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

  8. FUNDAMENTAL AREAS OF PHENOMENOLOGY (INCLUDING APPLICATIONS): Teleportation of Entangled States through Divorce of Entangled Pair Mediated by a Weak Coherent Field in a High-Q Cavity

    Science.gov (United States)

    Cardoso B., W.; Almeida G. de, N.

    2008-07-01

    We propose a scheme to partially teleport an unknown entangled atomic state. A high-Q cavity, supporting one mode of a weak coherent state, is needed to accomplish this process. By partial teleportation we mean that teleportation will occur by changing one of the partners of the entangled state to be teleported. The entangled state to be teleported is composed by one pair of particles, we called this surprising characteristic of maintaining the entanglement, even when one of the particle of the entangled pair being teleported is changed, of divorce of entangled states.

  9. Teleportation of Entangled States through Divorce of Entangled Pair Mediated by a Weak Coherent Field in a High-Q Cavity

    International Nuclear Information System (INIS)

    Cardoso, W. B.; Almeida, N. G. de

    2008-01-01

    We propose a scheme to partially teleport an unknown entangled atomic state. A high-Q cavity, supporting one mode of a weak coherent state, is needed to accomplish this process. By partial teleportation we mean that teleportation will occur by changing one of the partners of the entangled state to be teleported. The entangled state to be teleported is composed by one pair of particles, we called this surprising characteristic of maintaining the entanglement, even when one of the particle of the entangled pair being teleported is changed, of divorce of entangled states. (fundamental areas of phenomenology (including applications))

  10. Teleportation of Entangled States through Divorce of Entangled Pair Mediated by a Weak Coherent Field in a High-Q Cavity

    Institute of Scientific and Technical Information of China (English)

    W. B. Cardosol; N. G. de Almeida

    2008-01-01

    We propose a scheme to partially teleport an unknown entangled atomic state. A high-Q cavity, supporting one mode of a weak coherent state, is needed to accomplish this process. By partial teleportation we mean that teleportation will occur by changing one of the partners of the entangled state to be teleported. The entangled state to be teleported is composed by one pair of particles, we called this surprising characteristic of maintaining the entanglement, even when one of the particle of the entangled pair being teleported is changed, of divorce of entangled states.

  11. High sensitivity and high Q-factor nanoslotted parallel quadrabeam photonic crystal cavity for real-time and label-free sensing

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Daquan [Rowland Institute at Harvard University, Cambridge, Massachusetts 02142 (United States); State Key Laboratory of Information Photonics and Optical Communications, School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing 100876 (China); School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts 02138 (United States); Kita, Shota; Wang, Cheng; Lončar, Marko [School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts 02138 (United States); Liang, Feng; Quan, Qimin [Rowland Institute at Harvard University, Cambridge, Massachusetts 02142 (United States); Tian, Huiping; Ji, Yuefeng [State Key Laboratory of Information Photonics and Optical Communications, School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing 100876 (China)

    2014-08-11

    We experimentally demonstrate a label-free sensor based on nanoslotted parallel quadrabeam photonic crystal cavity (NPQC). The NPQC possesses both high sensitivity and high Q-factor. We achieved sensitivity (S) of 451 nm/refractive index unit and Q-factor >7000 in water at telecom wavelength range, featuring a sensor figure of merit >2000, an order of magnitude improvement over the previous photonic crystal sensors. In addition, we measured the streptavidin-biotin binding affinity and detected 10 ag/mL concentrated streptavidin in the phosphate buffered saline solution.

  12. Jean-Pierre Famose et Jean Bertsch, L’estime de soi : une controverse éducative, Paris, PUF, 2009, 192 p

    OpenAIRE

    Benamar, Aïcha

    2015-01-01

    L’ouvrage porte sur l’estime de soi, dans la sphère sociale en général et le monde éducatif en particulier. L’estime de soi est au cœur du comportement individuel, apportant confiance et assurance, permettant de progresser et in fine de réussir. Une faible estime de soi est fréquemment à l’origine de difficultés pour un individu : doutes, hésitations, ou à l’inverse vanité et arrogance. Un bon niveau d’estime de soi confère à la personnalité : capacité à s’affirmer et respect des autres. Cent...

  13. High frequency breakdown voltage

    International Nuclear Information System (INIS)

    Chu, Thanh Duy.

    1992-03-01

    This report contains information about the effect of frequency on the breakdown voltage of an air gap at standard pressure and temperature, 76 mm Hg and O degrees C, respectively. The frequencies of interest are 47 MHz and 60 MHz. Additionally, the breakdown in vacuum is briefly considered. The breakdown mechanism is explained on the basis of collision and ionization. The presence of the positive ions produced by ionization enhances the field in the gap, and thus determines the breakdown. When a low-frequency voltage is applied across the gap, the breakdown mechanism is the same as that caused by the DC or static voltage. However, when the frequency exceeds the first critical value f c , the positive ions are trapped in the gap, increasing the field considerably. This makes the breakdown occur earlier; in other words, the breakdown voltage is lowered. As the frequency increases two decades or more, the second critical frequency, f ce , is reached. This time the electrons start being trapped in the gap. Those electrons that travel multiple times across the gap before reaching the positive electrode result in an enormous number of electrons and positive ions being present in the gap. The result is a further decrease of the breakdown voltage. However, increasing the frequency does not decrease the breakdown voltage correspondingly. In fact, the associated breakdown field intensity is almost constant (about 29 kV/cm).The reason is that the recombination rate increases and counterbalances the production rate, thus reducing the effect of the positive ions' concentration in the gap. The theory of collision and ionization does not apply to the breakdown in vacuum. It seems that the breakdown in vacuum is primarily determined by the irregularities on the surfaces of the electrodes. Therefore, the effect of frequency on the breakdown, if any, is of secondary importance

  14. Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

    International Nuclear Information System (INIS)

    Naumova, O V; Fomin, B I; Ilnitsky, M A; Popov, V P

    2012-01-01

    In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 10 5 –5 × 10 7 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO 2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to k i ln D. The coefficients k i for as-fabricated and ion-implanted Si/buried SiO 2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO 2 interface. (paper)

  15. A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

    Science.gov (United States)

    Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

    2018-04-01

    We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

  16. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  17. Comparison of short-circuit characteristics of trench gate and planar gate U-shaped channel SOI-LIGBTs

    Science.gov (United States)

    Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

    2017-09-01

    Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.

  18. Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

    International Nuclear Information System (INIS)

    Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

    1989-01-01

    Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

  19. Digital voltage discriminator

    International Nuclear Information System (INIS)

    Zhou Zhicheng

    1992-01-01

    A digital voltage discriminator is described, which is synthesized by digital comparator and ADC. The threshold is program controllable with high stability. Digital region of confusion is approximately equal to 1.5 LSB. This discriminator has a single channel analyzer function model with channel width of 1.5 LSB

  20. High-voltage picoamperemeter

    Energy Technology Data Exchange (ETDEWEB)

    Bugl, Andrea; Ball, Markus; Boehmer, Michael; Doerheim, Sverre; Hoenle, Andreas; Konorov, Igor [Technische Universitaet Muenchen, Garching (Germany); Ketzer, Bernhard [Technische Universitaet Muenchen, Garching (Germany); Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany)

    2014-07-01

    Current measurements in the nano- and picoampere region on high voltage are an important tool to understand charge transfer processes in micropattern gas detectors like the Gas Electron Multiplier (GEM). They are currently used to e.g. optimize the field configuration in a multi-GEM stack to be used in the ALICE TPC after the upgrade of the experiment during the 2nd long shutdown of the LHC. Devices which allow measurements down to 1pA at high voltage up to 6 kV have been developed at TU Muenchen. They are based on analog current measurements via the voltage drop over a switchable shunt. A microcontroller collects 128 digital ADC values and calculates their mean and standard deviation. This information is sent with a wireless transmitting unit to a computer and stored in a root file. A nearly unlimited number of devices can be operated simultaneously and read out by a single receiver. The results can also be displayed on a LCD directly at the device. Battery operation and the wireless readout are important to protect the user from any contact to high voltage. The principle of the device is explained, and systematic studies of their properties are shown.

  1. Geomagnetism and Induced Voltage

    Science.gov (United States)

    Abdul-Razzaq, W.; Biller, R. D.

    2010-01-01

    Introductory physics laboratories have seen an influx of "conceptual integrated science" over time in their classrooms with elements of other sciences such as chemistry, biology, Earth science, and astronomy. We describe a laboratory to introduce this development, as it attracts attention to the voltage induced in the human brain as it…

  2. Investigations of a voltage-biased microwave cavity for quantum measurements of nanomechanical resonators

    Science.gov (United States)

    Rouxinol, Francisco; Hao, Hugo; Lahaye, Matt

    2015-03-01

    Quantum electromechanical systems incorporating superconducting qubits have received extensive interest in recent years due to their promising prospects for studying fundamental topics of quantum mechanics such as quantum measurement, entanglement and decoherence in new macroscopic limits, also for their potential as elements in technological applications in quantum information network and weak force detector, to name a few. In this presentation we will discuss ours efforts toward to devise an electromechanical circuit to strongly couple a nanomechanical resonator to a superconductor qubit, where a high voltage dc-bias is required, to study quantum behavior of a mechanical resonator. Preliminary results of our latest generation of devices integrating a superconductor qubit into a high-Q voltage biased microwave cavities are presented. Developments in the circuit design to couple a mechanical resonator to a qubit in the high-Q voltage bias CPW cavity is discussed as well prospects of achieving single-phonon measurement resolution. National Science Foundation under Grant No. DMR-1056423 and Grant No. DMR-1312421.

  3. Mitigation of Unbalanced Voltage Sags and Voltage Unbalance in CIGRE Low Voltage Distribution Network

    DEFF Research Database (Denmark)

    Mustafa, Ghullam; Bak-Jensen, Birgitte; Mahat, Pukar

    2013-01-01

    Any problem with voltage in a power network is undesirable as it aggravates the quality of the power. Power electronic devices such as Voltage Source Converter (VSC) based Static Synchronous Compensator (STATCOM) etc. can be used to mitigate the voltage problems in the distribution system...... to unbalanced faults. The compensation of unbalanced voltage sags and voltage unbalance in the CIGRE distribution network is done by using the four STATCOM compensators already existing in the test grid. The simulations are carried out in DIgSILENT power factory software version 15.0........ The voltage problems dealt with in this paper are to show how to mitigate unbalanced voltage sags and voltage unbalance in the CIGRE Low Voltage (LV) test network and net-works like this. The voltage unbalances, for the tested cases in the CIGRE LV test network are mainly due to single phase loads and due...

  4. Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

    International Nuclear Information System (INIS)

    Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

    2011-01-01

    This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

  5. Analytical and semi-analytical formalism for the voltage and the current sources of a superconducting cavity under dynamic detuning

    CERN Document Server

    Doleans, M

    2003-01-01

    Elliptical superconducting radio frequency (SRF) cavities are sensitive to frequency detuning because they have a high Q value in comparison with normal conducting cavities and weak mechanical properties. Radiation pressure on the cavity walls, microphonics, and tuning system are possible sources of dynamic detuning during SRF cavity-pulsed operation. A general analytic relation between the cavity voltage, the dynamic detuning function, and the RF control function is developed. This expression for the voltage envelope in a cavity under dynamic detuning and dynamic RF controls is analytically expressed through an integral formulation. A semi-analytical scheme is derived to calculate the voltage behavior in any practical case. Examples of voltage envelope behavior for different cases of dynamic detuning and RF control functions are shown. The RF control function for a cavity under dynamic detuning is also investigated and as an application various filling schemes are presented.

  6. Mitigation of Voltage Sags in CIGRE Low Voltage Distribution Network

    DEFF Research Database (Denmark)

    Mustafa, Ghullam; Bak-Jensen, Birgitte; Mahat, Pukar

    2013-01-01

    Any problem in voltage in a power network is undesirable as it aggravates the quality of the power. Power electronic devices such as Voltage Source Converter (VSC) based Static Synchronous Compensator (STATCOM), Dynamic Voltage Restorer (DVR) etc. are commonly used for the mitigation of voltage p....... The compensation of voltage sags in the different parts of CIGRE distribution network is done by using the four STATCOM compensators already existing in the test grid. The simulations are carried out in DIgSILENT power factory software version 15.0.......Any problem in voltage in a power network is undesirable as it aggravates the quality of the power. Power electronic devices such as Voltage Source Converter (VSC) based Static Synchronous Compensator (STATCOM), Dynamic Voltage Restorer (DVR) etc. are commonly used for the mitigation of voltage...... problems in the distribution system. The voltage problems dealt with in this paper are to show how to mitigate voltage sags in the CIGRE Low Voltage (LV) test network and networks like this. The voltage sags, for the tested cases in the CIGRE LV test network are mainly due to three phase faults...

  7. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.; Deptuch, G.; Yarema, R.; /Fermilab

    2010-11-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  8. Design and fabrication of two kind of SOI-based EA-type VOAs

    Science.gov (United States)

    Yuan, Pei; Wang, Yue; Wu, Yuanda; An, Junming; Hu, Xiongwei

    2018-06-01

    SOI-based variable optical attenuators based on electro-absorption mechanism are demonstrated in this paper. Two different doping structures are adopted to realize the attenuation: a structure with a single lateral p-i-n diode and a structure with several lateral p-i-n diodes connected in series. The VOAs with lateral p-i-n diodes connected in series (series VOA) can greatly improve the device attenuation efficiency compared to VOAs with a single lateral p-i-n diode structure (single VOA), which is verified by the experimental results that the attenuation efficiency of the series VOA and the single VOA is 3.76 dB/mA and 0.189 dB/mA respectively. The corresponding power consumption at 20 dB attenuation is 202 mW (series VOA) and 424 mW (single VOA) respectively. The raise time is 34.5 ns (single VOA) and 45.5 ns (series VOA), and the fall time is 37 ns (single VOA) and 48.5 ns (series VOA).

  9. High temperature piezoresistive {beta}-SiC-on-SOI pressure sensor for combustion engines

    Energy Technology Data Exchange (ETDEWEB)

    Berg, J. von; Ziermann, R.; Reichert, W.; Obermeier, E. [Tech. Univ. Berlin (Germany). Microsensor and Actuator Technol. Center; Eickhoff, M.; Kroetz, G. [Daimler Benz AG, Munich (Germany); Thoma, U.; Boltshauser, T.; Cavalloni, C. [Kistler Instrumente AG, Winterthur (Switzerland); Nendza, J.P. [TRW Deutschland GmbH, Barsinghausen (Germany)

    1998-08-01

    For measuring the cylinder pressure in combustion engines of automobiles a high temperature pressure sensor has been developed. The sensor is made of a membrane based piezoresistive {beta}-SiC-on-SOI (SiCOI) sensor chip and a specially designed housing. The SiCOI sensor was characterized under static pressures of up to 200 bar in the temperature range between room temperature and 300 C. The sensitivity of the sensor at room temperature is approximately 0.19 mV/bar and decreases to about 0.12 mV/bar at 300 C. For monitoring the dynamic cylinder pressure the sensor was placed into the combustion chamber of a gasoline engine. The measurements were performed at 1500 rpm under different loads, and for comparison a quartz pressure transducer from Kistler AG was used as a reference. The maximum pressure at partial load operation amounts to about 15 bar. The difference between the calibrated SiCOI sensor and the reference sensor is significantly less than 1 bar during the whole operation. (orig.) 8 refs.

  10. Development of monolithic pixel detector with SOI technology for the ILC vertex detector

    Science.gov (United States)

    Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

    2018-01-01

    We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

  11. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    International Nuclear Information System (INIS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-01-01

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10 −9 of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved

  12. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    Energy Technology Data Exchange (ETDEWEB)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 UKM Bangi, Selangor (Malaysia)

    2015-04-24

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  13. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    Science.gov (United States)

    Olszacki, M.; Maj, C.; Bahri, M. Al; Marrot, J.-C.; Boukabache, A.; Pons, P.; Napieralski, A.

    2010-06-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 1017 at cm-3 to 1.6 × 1019 at cm-3. The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 1018-1019 at cm-3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  14. Athermal and wavelength-trimmable photonic filters based on TiO₂-cladded amorphous-SOI.

    Science.gov (United States)

    Lipka, Timo; Moldenhauer, Lennart; Müller, Jörg; Trieu, Hoc Khiem

    2015-07-27

    Large-scale integrated silicon photonic circuits suffer from two inevitable issues that boost the overall power consumption. First, fabrication imperfections even on sub-nm scale result in spectral device non-uniformity that require fine-tuning during device operation. Second, the photonic devices need to be actively corrected to compensate thermal drifts. As a result significant amount of power is wasted if no athermal and wavelength-trimmable solutions are utilized. Consequently, in order to minimize the total power requirement of photonic circuits in a passive way, trimming methods are required to correct the device inhomogeneities from manufacturing and athermal solutions are essential to oppose temperature fluctuations of the passive/active components during run-time. We present an approach to fabricate CMOS backend-compatible and athermal passive photonic filters that can be corrected for fabrication inhomogeneities by UV-trimming based on low-loss amorphous-SOI waveguides with TiO2 cladding. The trimming of highly confined 10 μm ring resonators is proven over a free spectral range retaining athermal operation. The athermal functionality of 2nd-order 5 μm add/drop microrings is demonstrated over 40°C covering a broad wavelength interval of 60 nm.

  15. Analysis of the rectangular resonator with butterfly MMI coupler using SOI

    Science.gov (United States)

    Kim, Sun-Ho; Park, Jun-Hee; Kim, Eudum; Jeon, Su-Jin; Kim, Ji-Hoon; Choi, Young-Wan

    2018-02-01

    We propose a rectangular resonator sensor structure with butterfly MMI coupler using SOI. It consists of the rectangular resonator, total internal reflection (TIR) mirror, and the butterfly MMI coupler. The rectangular resonator is expected to be used as bio and chemical sensors because of the advantages of using MMI coupler and the absence of bending loss unlike ring resonators. The butterfly MMI coupler can miniaturize the device compared to conventional MMI by using a linear butterfly shape instead of a square in the MMI part. The width, height, and slab height of the rib type waveguide are designed to be 1.5 μm, 1.5 μm, and 0.9 μm, respectively. This structure is designed as a single mode. When designing a TIR mirror, we considered the Goos-Hänchen shift and critical angle. We designed 3:1 MMI coupler because rectangular resonator has no bending loss. The width of MMI is designed to be 4.5 μm and we optimize the length of the butterfly MMI coupler using finite-difference time-domain (FDTD) method for higher Q-factor. It has the equal performance with conventional MMI even though the length is reduced by 1/3. As a result of the simulation, Qfactor of rectangular resonator can be obtained as 7381.

  16. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    Science.gov (United States)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  17. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    International Nuclear Information System (INIS)

    Olszacki, M; Maj, C; Al Bahri, M; Marrot, J-C; Boukabache, A; Pons, P; Napieralski, A

    2010-01-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 10 17 at cm −3 to 1.6 × 10 19 at cm −3 . The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 10 18 –10 19 at cm −3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  18. Line-edge roughness induced single event transient variation in SOI FinFETs

    International Nuclear Information System (INIS)

    Wu Weikang; An Xia; Jiang Xiaobo; Chen Yehua; Liu Jingjing; Zhang Xing; Huang Ru

    2015-01-01

    The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (V gs = 0, V ds = V dd ) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size. (paper)

  19. High Voltage Charge Pump

    KAUST Repository

    Emira, Ahmed A.; Abdelghany, Mohamed A.; Elsayed, Mohannad Yomn; Elshurafa, Amro M; Salama, Khaled N.

    2014-01-01

    Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

  20. High Voltage Charge Pump

    KAUST Repository

    Emira, Ahmed A.

    2014-10-09

    Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.

  1. High Voltage Seismic Generator

    Science.gov (United States)

    Bogacz, Adrian; Pala, Damian; Knafel, Marcin

    2015-04-01

    This contribution describes the preliminary result of annual cooperation of three student research groups from AGH UST in Krakow, Poland. The aim of this cooperation was to develop and construct a high voltage seismic wave generator. Constructed device uses a high-energy electrical discharge to generate seismic wave in ground. This type of device can be applied in several different methods of seismic measurement, but because of its limited power it is mainly dedicated for engineering geophysics. The source operates on a basic physical principles. The energy is stored in capacitor bank, which is charged by two stage low to high voltage converter. Stored energy is then released in very short time through high voltage thyristor in spark gap. The whole appliance is powered from li-ion battery and controlled by ATmega microcontroller. It is possible to construct larger and more powerful device. In this contribution the structure of device with technical specifications is resented. As a part of the investigation the prototype was built and series of experiments conducted. System parameter was measured, on this basis specification of elements for the final device were chosen. First stage of the project was successful. It was possible to efficiently generate seismic waves with constructed device. Then the field test was conducted. Spark gap wasplaced in shallowborehole(0.5 m) filled with salt water. Geophones were placed on the ground in straight line. The comparison of signal registered with hammer source and sparker source was made. The results of the test measurements are presented and discussed. Analysis of the collected data shows that characteristic of generated seismic signal is very promising, thus confirms possibility of practical application of the new high voltage generator. The biggest advantage of presented device after signal characteristics is its size which is 0.5 x 0.25 x 0.2 m and weight approximately 7 kg. This features with small li-ion battery makes

  2. Increased voltage photovoltaic cell

    Science.gov (United States)

    Ross, B.; Bickler, D. B.; Gallagher, B. D. (Inventor)

    1985-01-01

    A photovoltaic cell, such as a solar cell, is provided which has a higher output voltage than prior cells. The improved cell includes a substrate of doped silicon, a first layer of silicon disposed on the substrate and having opposite doping, and a second layer of silicon carbide disposed on the first layer. The silicon carbide preferably has the same type of doping as the first layer.

  3. DC and RF Characterization of Laser Annealed Metal-Gate SOI CMOS Field-Effect Transistors

    National Research Council Canada - National Science Library

    Lu, R. P; Offord, B. W; Popp, J. D; Ramirez, A. D; Rowland, J. F; Russell, S. D

    2005-01-01

    .... The 0.25-micron devices were found to be more sensitive to the laser energy which showed up in the DC measurements in threshold voltage variations and larger leakage currents in the subthreshold characteristics...

  4. Suppressing voltage transients in high voltage power supplies

    International Nuclear Information System (INIS)

    Lickel, K.F.; Stonebank, R.

    1979-01-01

    A high voltage power supply for an X-ray tubes includes voltage adjusting means, a high voltage transformer, switch means connected to make and interrupt the primary current of the transformer, and over-voltage suppression means to suppress the voltage transient produced when the current is switched on. In order to reduce the power losses in the suppression means, an impedance is connected in the transformer primary circuit on operation of the switch means and is subsequently short-circuited by a switch controlled by a timer after a period which is automatically adjusted to the duration of the transient overvoltage. (U.K.)

  5. Benchmarking of Voltage Sag Generators

    DEFF Research Database (Denmark)

    Yang, Yongheng; Blaabjerg, Frede; Zou, Zhixiang

    2012-01-01

    The increased penetration of renewable energy systems, like photovoltaic and wind power systems, rises the concern about the power quality and stability of the utility grid. Some regulations for Low Voltage Ride-Through (LVRT) for medium voltage or high voltage applications, are coming into force...

  6. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P [Albuquerque, NM; Christenson, Todd R [Albuquerque, NM

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  7. Transient voltage sharing in series-coupled high voltage switches

    Directory of Open Access Journals (Sweden)

    Editorial Office

    1992-07-01

    Full Text Available For switching voltages in excess of the maximum blocking voltage of a switching element (for example, thyristor, MOSFET or bipolar transistor such elements are often coupled in series - and additional circuitry has to be provided to ensure equal voltage sharing. Between each such series element and system ground there is a certain parasitic capacitance that may draw a significant current during high-speed voltage transients. The "open" switch is modelled as a ladder network. Analy­sis reveals an exponential progression in the distribution of the applied voltage across the elements. Overstressing thus oc­curs in some of the elements at levels of the total voltage that are significantly below the design value. This difficulty is overcome by grading the voltage sharing circuitry, coupled in parallel with each element, in a prescribed manner, as set out here.

  8. Coordinated Voltage Control of Distributed PV Inverters for Voltage Regulation in Low Voltage Distribution Networks

    DEFF Research Database (Denmark)

    Nainar, Karthikeyan; Pokhrel, Basanta Raj; Pillai, Jayakrishnan Radhakrishna

    2017-01-01

    This paper reviews and analyzes the existing voltage control methods of distributed solar PV inverters to improve the voltage regulation and thereby the hosting capacity of a low-voltage distribution network. A novel coordinated voltage control method is proposed based on voltage sensitivity...... optimization. The proposed method is used to calculate the voltage bands and droop settings of PV inverters at each node by the supervisory controller. The local controller of each PV inverter implements the volt/var control and if necessary, the active power curtailment as per the received settings and based...... on measured local voltages. The advantage of the proposed method is that the calculated reactive power and active power droop settings enable fair contribution of the PV inverters at each node to the voltage regulation. Simulation studies are conducted using DigSilent Power factory software on a simplified...

  9. Sensing voltage across lipid membranes

    Science.gov (United States)

    Swartz, Kenton J.

    2009-01-01

    The detection of electrical potentials across lipid bilayers by specialized membrane proteins is required for many fundamental cellular processes such as the generation and propagation of nerve impulses. These membrane proteins possess modular voltage-sensing domains, a notable example being the S1-S4 domains of voltage-activated ion channels. Ground-breaking structural studies on these domains explain how voltage sensors are designed and reveal important interactions with the surrounding lipid membrane. Although further structures are needed to fully understand the conformational changes that occur during voltage sensing, the available data help to frame several key concepts that are fundamental to the mechanism of voltage sensing. PMID:19092925

  10. InP on SOI devices for optical communication and optical network on chip

    Science.gov (United States)

    Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

    2011-01-01

    For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

  11. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    International Nuclear Information System (INIS)

    Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

    2008-01-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

  12. Blog : un journal intime comme mémoire de soi

    Directory of Open Access Journals (Sweden)

    Nolwenn Hénaff

    2011-08-01

    Full Text Available Tenir un journal est devenu, pour un individu, une manière possible de vivre, ou d’accompagner un moment de sa vie (Lejeune, 2006. Les usages sont donc multiples : construction d’une identité narrative, fixation du temps, libération du moi, introspection, outil de contrôle, de soutien, méthode d’organisation de la pensée, plaisir d’écrire. Si l’écriture papier reste la forme la plus courante du récit biographique, d’autres supports médiatiques comme la télévision ou la radio sont venus offrir de nouveaux terrains d’expérimentation de ces récits de soi. Plus récemment, l’avènement d’Internet et de ses outils simplifiés de publication ont fait émerger des formes biographiques innovantes. Pourtant, qu’il s’agisse de traverser une crise, de garder la mémoire d’une expérience forte, ou, plus ordinairement, de relater ses vacances et ses voyages, le journal se positionne avant tout, et résolument, comme un espace de liberté : on écrit quand on veut, comme on veut. Le « Souci de soi » comme dirait Foucault, l’espace dominé par les sensations, et la temporalité marquée par la notion d’instants, de moments ayant une connotation expressément personnelle sont autant d’indices révélant la pratique de l’écriture intime en ligne. Le blog apparaît à des moments de vie et accompagne souvent des tournants biographiques (ruptures, questionnement mais aussi nouveaux apprentissages, nouvelles rencontres, etc.. Nous proposons dans cet article d’analyser le blog en tant que support de mémoire personnelle et d’étudier à travers des exemples concrets les stratégies développées par les blogueurs pour se créer via ce dispositif communicationnel innovant un « espace de conserverie de soi » en ligne.Keeping a journal has become a way of live, or to moment a moment in one’s life (Lejeune, 2006. It has multiple uses: construction of a narrative identity, marking time, liberating the

  13. Modulation of the SSTA decadal variation on ENSO events and relationships of SSTA With LOD,SOI, etc

    Science.gov (United States)

    Liao, D. C.; Zhou, Y. H.; Liao, X. H.

    2007-01-01

    Interannual and decadal components of the length of day (LOD), Southern Oscillation Index (SOI) and Sea Surface Temperature anomaly (SSTA) in Nino regions are extracted by band-pass filtering, and used for research of the modulation of the SSTA on the ENSO events. Results show that besides the interannual components, the decadal components in SSTA have strong impacts on monitoring and representing of the ENSO events. When the ENSO events are strong, the modulation of the decadal components of the SSTA tends to prolong the life-time of the events and enlarge the extreme anomalies of the SST, while the ENSO events, which are so weak that they can not be detected by the interannual components of the SSTA, can also be detected with the help of the modulation of the SSTA decadal components. The study further draws attention to the relationships of the SSTA interannual and decadal components with those of LOD, SOI, both of the sea level pressure anomalies (SLPA) and the trade wind anomalies (TWA) in tropic Pacific, and also with those of the axial components of the atmospheric angular momentum (AAM) and oceanic angular momentum (OAM). Results of the squared coherence and coherent phases among them reveal close connections with the SSTA and almost all of the parameters mentioned above on the interannual time scales, while on the decadal time scale significant connections are among the SSTA and SOI, SLPA, TWA, ?3w and ?3w+v as well, and slight weaker connections between the SSTA and LOD, ?3pib and ?3bp

  14. Heat-pump performance: voltage dip/sag, under-voltage and over-voltage

    Directory of Open Access Journals (Sweden)

    William J.B. Heffernan

    2014-12-01

    Full Text Available Reverse cycle air-source heat-pumps are an increasingly significant load in New Zealand and in many other countries. This has raised concern over the impact wide-spread use of heat-pumps may have on the grid. The characteristics of the loads connected to the power system are changing because of heat-pumps. Their performance during under-voltage events such as voltage dips has the potential to compound the event and possibly cause voltage collapse. In this study, results from testing six heat-pumps are presented to assess their performance at various voltages and hence their impact on voltage stability.

  15. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  16. Une dialectique de la pudeur : les pratiques de mise en visibilité de soi sur Facebook

    OpenAIRE

    Mell , Laurent

    2017-01-01

    L’amplification des usages des technologies de l’information et de la communication (TIC), et plus particulièrement des réseaux socionumériques, ont induit des évolutions significatives dans le rapport des individus aux normes relatives à la pudeur. Dans cet article, nous proposons de discuter des pratiques de mise en visibilité de soi sur le réseau socionumérique Facebook. Tout d’abord, nous montrons que l’augmentation de la considération pour la vie privée amène à une sélection des informat...

  17. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  18. Investigation of the stability of polysilicon layers in SOI-structures under irradiation by electrons and hard magnetic field influence

    Directory of Open Access Journals (Sweden)

    Khoverko Yu. N.

    2010-10-01

    Full Text Available The properties of recrystallized polysilicon on insulator layers of p-type conductive SOI-structures with different carrier concentration irradiated with high-energy electrons flow about 1017 сm–2 in temperature range 4,2—300 К and high magnetic fields were investigated. It was found that heavily doped laser recrystallized polysilicon on insulator layers show its radiation resistance under irradiation with high-energy electrons and magnetoresistance of such material remains quite low in magnetic field about 14 T does not exceed 1—2%. Such qulity can be applied in designing of microelectronic sensors of mechanical values operable in hard conditions of exploitation.

  19. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  20. Directly Modulated and ER Enhanced Hybrid III-V/SOI DFB Laser Operating up to 20 Gb/s for Extended Reach Applications in PONs

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Da Ros, Francesco; Chaibi, Mohamed E.

    2017-01-01

    We demonstrate error-free performance of an MRR filtered DML on the SOI platform over 40- and 81-km of SSW. The device operates up to 17.5 Gb/s over 81 km and 20 Gb/s over 40 km.......We demonstrate error-free performance of an MRR filtered DML on the SOI platform over 40- and 81-km of SSW. The device operates up to 17.5 Gb/s over 81 km and 20 Gb/s over 40 km....

  1. PROCEEDINGS OF RIKEN BNL RESEARCH CENTER WORKSHOP ON RHIC SPIN PHYSICS III AND IV, POLARIZED PARTONS AT HIGH Q2 REGION (VOLUME 31)

    International Nuclear Information System (INIS)

    BUNCE, G.; VIGDOR, S.

    2001-01-01

    International workshop on II Polarized Partons at High Q2 region 11 was held at the Yukawa Institute for Theoretical Physics, Kyoto University, Kyoto, Japan on October 13-14, 2000, as a satellite of the international conference ''SPIN 2000'' (Osaka, Japan, October 16-21,2000). This workshop was supported by RIKEN (The Institute of Physical and Chemical Research) and by Yukawa Institute. The scientific program was focused on the upcoming polarized collider RHIC. The workshop was also an annual meeting of RHIC Spin Collaboration (RSC). The number of participants was 55, including 28 foreign visitors and 8 foreign-resident Japanese participants, reflecting the international nature of the RHIC spin program. At the workshop there were 25 oral presentations in four sessions, (1) RHIC Spin Commissioning, (2) Polarized Partons, Present and Future, (3) New Ideas on Polarization Phenomena, (4) Strategy for the Coming Spin Running. In (1) the successful polarized proton commissioning and the readiness of the accelerator for the physics program impressed us. In (2) and (3) active discussions were made on the new structure function to be firstly measured at RHIC, and several new theoretical ideas were presented. In session (4) we have established a plan for the beam time requirement toward the first collision of polarized protons. These proceedings include the transparencies presented at the workshop. The discussion on ''Strategy for the Coming Spin Running'' was summarized by the chairman of the session, S. Vigdor and G. Bunce

  2. High voltage isolation transformer

    Science.gov (United States)

    Clatterbuck, C. H.; Ruitberg, A. P. (Inventor)

    1985-01-01

    A high voltage isolation transformer is provided with primary and secondary coils separated by discrete electrostatic shields from the surfaces of insulating spools on which the coils are wound. The electrostatic shields are formed by coatings of a compound with a low electrical conductivity which completely encase the coils and adhere to the surfaces of the insulating spools adjacent to the coils. Coatings of the compound also line axial bores of the spools, thereby forming electrostatic shields separating the spools from legs of a ferromagnetic core extending through the bores. The transformer is able to isolate a high constant potential applied to one of its coils, without the occurrence of sparking or corona, by coupling the coatings, lining the axial bores to the ferromagnetic core and by coupling one terminal of each coil to the respective coating encasing the coil.

  3. High figure-of-merit SOI power LDMOS for power integrated circuits

    Directory of Open Access Journals (Sweden)

    Yashvir Singh

    2015-06-01

    Full Text Available The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

  4. Pulse-voltage fast generator

    International Nuclear Information System (INIS)

    Valeev, R.I.; Nikiforov, M.G.; Kharchenko, A.F.

    1988-01-01

    The design is described and the test results of a four-channel pulse-voltage generator with maximum output voltage 200 kV are presented. The measurement results of generator triggering time depending on the value and polarity of the triggering voltage pulse for different triggering circuits are presented. The tests have shown stable triggering of all four channels of the generator in the range up to 40 % from selfbreakdown voltage. The generator triggering delay in the given range is <25 ns, asynchronism in channel triggering is <±1 ns

  5. Voltage Dependence of Supercapacitor Capacitance

    Directory of Open Access Journals (Sweden)

    Szewczyk Arkadiusz

    2016-09-01

    Full Text Available Electronic Double-Layer Capacitors (EDLC, called Supercapacitors (SC, are electronic devices that are capable to store a relatively high amount of energy in a small volume comparing to other types of capacitors. They are composed of an activated carbon layer and electrolyte solution. The charge is stored on electrodes, forming the Helmholtz layer, and in electrolyte. The capacitance of supercapacitor is voltage- dependent. We propose an experimental method, based on monitoring of charging and discharging a supercapacitor, which enables to evaluate the charge in an SC structure as well as the Capacitance-Voltage (C-V dependence. The measurement setup, method and experimental results of charging/discharging commercially available supercapacitors in various voltage and current conditions are presented. The total charge stored in an SC structure is proportional to the square of voltage at SC electrodes while the charge on electrodes increases linearly with the voltage on SC electrodes. The Helmholtz capacitance increases linearly with the voltage bias while a sublinear increase of total capacitance was found. The voltage on SC increases after the discharge of electrodes due to diffusion of charges from the electrolyte to the electrodes. We have found that the recovery voltage value is linearly proportional to the initial bias voltage value.

  6. Optimal Design of an Ultrasmall SOI-Based 1 × 8 Flat-Top AWG by Using an MMI

    Directory of Open Access Journals (Sweden)

    Hongqiang Li

    2013-01-01

    Full Text Available Four methods based on a multimode interference (MMI structure are optimally designed to flatten the spectral response of silicon-on-insulator- (SOI- based arrayed-waveguide grating (AWG applied in a demodulation integration microsystem. In the design for each method, SOI is selected as the material, the beam propagation method is used, and the performances (including the 3 dB passband width, the crosstalk, and the insertion loss of the flat-top AWG are studied. Moreover, the output spectrum responses of AWGs with or without a flattened structure are compared. The results show that low insertion loss, crosstalk, and a flat and efficient spectral response are simultaneously achieved for each kind of structure. By comparing the four designs, the design that combines a tapered MMI with tapered input/output waveguides, which has not been previously reported, was shown to yield better results than others. The optimized design reduced crosstalk to approximately −21.9 dB and had an insertion loss of −4.36 dB and a 3 dB passband width, that is, approximately 65% of the channel spacing.

  7. Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

    Science.gov (United States)

    Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

    2018-02-01

    A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

  8. Temporary over voltages in the high voltage networks

    International Nuclear Information System (INIS)

    Vukelja, Petar; Naumov, Radomir; Mrvic, Jovan; Minovski, Risto

    2001-01-01

    The paper treats the temporary over voltages that may arise in the high voltage networks as a result of: ground faults, loss of load, loss of one or two phases and switching operation. Based on the analysis, the measures for their limitation are proposed. (Original)

  9. Computer controlled high voltage system

    Energy Technology Data Exchange (ETDEWEB)

    Kunov, B; Georgiev, G; Dimitrov, L [and others

    1996-12-31

    A multichannel computer controlled high-voltage power supply system is developed. The basic technical parameters of the system are: output voltage -100-3000 V, output current - 0-3 mA, maximum number of channels in one crate - 78. 3 refs.

  10. A Voltage Quality Detection Method

    DEFF Research Database (Denmark)

    Chen, Zhe; Wei, Mu

    2008-01-01

    This paper presents a voltage quality detection method based on a phase-locked loop (PLL) technique. The technique can detect the voltage magnitude and phase angle of each individual phase under both normal and fault power system conditions. The proposed method has the potential to evaluate various...

  11. High Q ceramics in the ACe2(MoO4)4 (A = Ba, Sr and Ca) system for LTCC applications

    International Nuclear Information System (INIS)

    Surjith, A.; Ratheesh, R.

    2013-01-01

    Highlights: ► Solid state synthesis of phase pure ACe 2 (MoO 4 ) 4 (A = Ba, Sr and Ca) ceramics. ► Structural and microstructural evaluation of the synthesized ceramic materials. ► Microwave dielectric property studies of ACe 2 (MoO 4 ) 4 (A = Ba, Sr and Ca) ceramics. ► Structure-property correlation through Laser Raman studies. - Abstract: Novel low temperature sinterable high Q ceramic systems ACe 2 (MoO 4 ) 4 (A = Ba, Sr and Ca) have been prepared through solid state ceramic method. The effect of ionic radii of alkaline earth cations on the structure, microstructure and microwave dielectric properties of these ceramics were studied using powder X-ray diffraction, Laser Raman spectroscopy, scanning electron microscopy and Vector Network Analyzer. A structural change from monoclinic to tetragonal structure was observed while substituting Sr 2+ and Ca 2+ cations in place of Ba 2+ . The Sr and Ca analogues possess better microwave dielectric properties compared to BaCe 2 (MoO 4 ) 4 . All the ceramics were well sintered below 840 °C with dielectric constant in the range 10.2–12.3 together with good quality factor. The SrCe 2 (MoO 4 ) 4 ceramic exhibits an unloaded quality factor of 6762 at 8.080662 GHz with a temperature coefficient of resonant frequency of −46 ppm/°C while the CaCe 2 (MoO 4 ) 4 ceramic shows an unloaded quality factor of 7549 at 6.928868 GHz and a temperature coefficient of resonant frequency of −44 ppm/°C.

  12. Proof-of-principle demonstration of Nb{sub 3}Sn superconducting radiofrequency cavities for high Q{sub 0} applications

    Energy Technology Data Exchange (ETDEWEB)

    Posen, S., E-mail: sep93@cornell.edu; Liepe, M.; Hall, D. L. [Cornell Laboratory for Accelerator-Based Sciences and Education, Ithaca, New York 14853 (United States)

    2015-02-23

    Many future particle accelerators require hundreds of superconducting radiofrequency (SRF) cavities operating with high duty factor. The large dynamic heat load of the cavities causes the cryogenic plant to make up a significant part of the overall cost of the facility. This contribution can be reduced by replacing standard niobium cavities with ones coated with a low-dissipation superconductor such as Nb{sub 3}Sn. In this paper, we present results for single cell cavities coated with Nb{sub 3}Sn at Cornell. Five coatings were carried out, showing that at 4.2 K, high Q{sub 0} out to medium fields was reproducible, resulting in an average quench field of 14 MV/m and an average 4.2 K Q{sub 0} at quench of 8 × 10{sup 9}. In each case, the peak surface magnetic field at quench was well above H{sub c1}, showing that it is not a limiting field in these cavities. The coating with the best performance had a quench field of 17 MV/m, exceeding gradient requirements for state-of-the-art high duty factor SRF accelerators. It is also shown that—taking into account the thermodynamic efficiency of the cryogenic plant—the 4.2 K Q{sub 0} values obtained meet the AC power consumption requirements of state-of-the-art high duty factor accelerators, making this a proof-of-principle demonstration for Nb{sub 3}Sn cavities in future applications.

  13. A high-Q low threshold thulium-doped silica microsphere laser in the 2 μm wavelength region designed for gas sensing applications

    International Nuclear Information System (INIS)

    Pal, Atasi; Chen, Shu Ying; Sun, Tong; Grattan, K T V; Sen, Ranjan

    2013-01-01

    A high-Q and low threshold laser resonator, operating in the 2 μm wavelength region, has been demonstrated by coupling a thulium-doped silica microsphere to a tapered fibre. Microspheres with diameters ranging from fifty to a few hundred micrometres were carefully fabricated for this purpose by melting an etched-clad thulium-doped silica fibre tip using a focused beam from a CO 2 laser, while the tapered fibre with waist diameter in the desired range of 2 μm was fabricated by using heating and stretching of standard single-mode telecommunication fibre. The tapered fibre served the dual purpose of transporting pump power into the sphere and allowing the extraction of the resulting laser emission. Under excitation at a wavelength of ∼1.6 μm, lasing occurred at wavelengths over the range from 1.9 to 2.0 μm. Single-mode laser operation was obtained by exciting the fundamental whispering gallery mode resonance of the microsphere, while multi-mode lasing occurred for non-fundamental mode excitation. The threshold power of the laser was measured to be about 50 μW delivered pump power, and a maximum laser power of 0.8 mW at around 1.94 μm was observed for a 6 mW pump power, operating at wavelengths around 1.6 μm. The laser was designed as a low threshold and compact source for miniaturized gas sensing devices operating over this important wavelength region. (letter)

  14. Voltage Controlled Dynamic Demand Response

    DEFF Research Database (Denmark)

    Bhattarai, Bishnu Prasad; Bak-Jensen, Birgitte; Mahat, Pukar

    2013-01-01

    Future power system is expected to be characterized by increased penetration of intermittent sources. Random and rapid fluctuations in demands together with intermittency in generation impose new challenges for power balancing in the existing system. Conventional techniques of balancing by large...... central or dispersed generations might not be sufficient for future scenario. One of the effective methods to cope with this scenario is to enable demand response. This paper proposes a dynamic voltage regulation based demand response technique to be applied in low voltage (LV) distribution feeders....... An adaptive dynamic model has been developed to determine composite voltage dependency of an aggregated load on feeder level. Following the demand dispatch or control signal, optimum voltage setting at the LV substation is determined based on the voltage dependency of the load. Furthermore, a new technique...

  15. Transient voltage oscillations in coils

    International Nuclear Information System (INIS)

    Chowdhuri, P.

    1985-01-01

    Magnet coils may be excited into internal voltage oscillations by transient voltages. Such oscillations may electrically stress the magnet's dielectric components to many times its normal stress. This may precipitate a dielectric failure, and the attendant prolonged loss of service and costly repair work. Therefore, it is important to know the natural frequencies of oscillations of a magnet during the design stage, and to determine whether the expected switching transient voltages can excite the magnet into high-voltage internal oscillations. The series capacitance of a winding significantly affects its natural frequencies. However, the series capacitance is difficult to calculate, because it may comprise complex capacitance network, consisting of intra- and inter-coil turn-to-turn capacitances of the coil sections. A method of calculating the series capacitance of a winding is proposed. This method is rigorous but simple to execute. The time-varying transient voltages along the winding are also calculated

  16. Error-free Dispersion-uncompensated Transmission at 20 Gb/s over SSMF using a Hybrid III-V/SOI DML with MRR Filtering

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Kamchevska, Valerija; Ding, Yunhong

    2016-01-01

    Error-free 20-Gb/s directly-modulated transmission is achieved by enhancing the dispersion tolerance of a III-V/SOI DFB laser with a silicon micro-ring resonator. Low (∼0.4 dB) penalty compared to back-to-back without ring is demonstrated after 5-km SSMF....

  17. Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

    International Nuclear Information System (INIS)

    Damiran, D.; Yu, P.

    2010-01-01

    Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE L3x , 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  18. Structural makeup, biopolymer conformation, and biodegradation characteristics of a newly developed super genotype of oats (CDC SO-I versus conventional varieties): a novel approach.

    Science.gov (United States)

    Damiran, Daalkhaijav; Yu, Peiqiang

    2010-02-24

    Recently, a new "super" genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE(L3x), 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  19. Le tourisme gay : aller ailleurs pour être soi-même ?

    Directory of Open Access Journals (Sweden)

    Emmanuel Jaurand

    2010-02-01

    Full Text Available L’orientation dominante des études sur le tourisme, longtemps marquées par l’importance de la dimension économique et par un désintérêt pour les questions touchant au corps, au sexe ou au genre, explique le silence autour du tourisme gay (qui n’est pas le tourisme des gays jusqu’aux années 1990. Pourtant, ce tourisme identitaire existe depuis longtemps et sa visibilité se développe, surtout dans les pays développés occidentaux. La métaphore du voyage et la recherche du paradis (sexuel perdu sont au cœur de l’identité homosexuelle depuis le 19 e siècle. Le tourisme gay se caractérise par des structures (tour-opérateurs, hébergements, croisières… et des destinations spécifiques. Pour les gays il s’agit, dans l’espace-temps des vacances, propice au relâchement et à la recréation de soi, de fuir un monde structuré par le système hétérosexiste et de rejoindre les autres (gays. La recherche de la rencontre du semblable et la sexualisation assumée du tourisme gay, à travers la libération et la dénudation des corps, participent d’une véritable quête pour valider son identité de gay. Elles font que les destinations préférées par les gays sont les stations balnéaires et les grandes villes : elles sont en effet dotées d’espaces publics, d’équipements commerciaux et de formes d’hébergement fermées favorables aux interactions et à la réalisation d’une éphémère « communauté gay ». The mainstream orientation of tourism studies, focused on the sole economic dimension for a long time, without any interest for questions about the body, sex or gender, explains the silence surrounding gay tourism (which is not the tourism of gay men since the 1990s. However, this identity tourism has existed for a long time and its visibility is growing, especially in Western developed countries. The metaphor of the journey and the search for a (sexual paradise lost have been at the core of the

  20. LOFT voltage insertion calibaration program

    International Nuclear Information System (INIS)

    Tillitt, D.N.; Miyasaki, F.S.

    1975-08-01

    The Loss-of-Fluid Test (LOFT) Facility is an experimental facility built around a ''scaled'' version of a large pressurized water reactor (LPWR). Part of this facility is the Data Acquisition and Visual Display System (DAVDS) as defined by the LOFT System Design Document SDD 1.4.2C. The DAVDS has a 702 data channel recording capability of which 548 are recorded digitally. The DAVDS also contains a Voltage Insertion Calibration Subsystem used to inject precise and known voltage steps into the recording systems. The computer program that controls the Voltage Insertion Calibration Subsystem is presented. 7 references. (auth)

  1. Power-MOSFET Voltage Regulator

    Science.gov (United States)

    Miller, W. N.; Gray, O. E.

    1982-01-01

    Ninety-six parallel MOSFET devices with two-stage feedback circuit form a high-current dc voltage regulator that also acts as fully-on solid-state switch when fuel-cell out-put falls below regulated voltage. Ripple voltage is less than 20 mV, transient recovery time is less than 50 ms. Parallel MOSFET's act as high-current dc regulator and switch. Regulator can be used wherever large direct currents must be controlled. Can be applied to inverters, industrial furnaces photovoltaic solar generators, dc motors, and electric autos.

  2. High-Q energy trapping of temperature-stable shear waves with Lamé cross-sectional polarization in a single crystal silicon waveguide

    Science.gov (United States)

    Tabrizian, R.; Daruwalla, A.; Ayazi, F.

    2016-03-01

    A multi-port electrostatically driven silicon acoustic cavity is implemented that efficiently traps the energy of a temperature-stable eigen-mode with Lamé cross-sectional polarization. Dispersive behavior of propagating and evanescent guided waves in a ⟨100⟩-aligned single crystal silicon waveguide is used to engineer the acoustic energy distribution of a specific shear eigen-mode that is well known for its low temperature sensitivity when implemented in doped single crystal silicon. Such an acoustic energy trapping in the central region of the acoustic cavity geometry and far from substrate obviates the need for narrow tethers that are conventionally used for non-destructive and high quality factor (Q) energy suspension in MEMS resonators; therefore, the acoustically engineered waveguide can simultaneously serve as in-situ self-oven by passing large uniformly distributed DC currents through its body and without any concern about perturbing the mode shape or deforming narrow supports. Such a stable thermo-structural performance besides large turnover temperatures than can be realized in Lamé eigen-modes make this device suitable for implementation of ultra-stable oven-controlled oscillators. 78 MHz prototypes implemented in arsenic-doped single crystal silicon substrates with different resistivity are transduced by in- and out-of-plane narrow-gap capacitive ports, showing high Q of ˜43k. The low resistivity device shows an overall temperature-induced frequency drift of 200 ppm over the range of -20 °C to 80 °C, which is ˜15× smaller compared to overall frequency drift measured for the similar yet high resistivity device in the same temperature range. Furthermore, a frequency tuning of ˜2100 ppm is achieved in high resistivity device by passing 45 mA DC current through its body. Continuous operation of the device under such a self-ovenizing current over 10 days did not induce frequency instability or degradation in Q.

  3. Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

    Science.gov (United States)

    Sarkar, Partha; Mallik, Abhijit; Sarkar, Chandan Kumar

    2009-03-01

    In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID, etc) for the sub-100 nm technologies.

  4. Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

    International Nuclear Information System (INIS)

    Sarkar, Partha; Mallik, Abhijit; Sarkar, Chandan Kumar

    2009-01-01

    In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g m /I D , etc) for the sub-100 nm technologies

  5. Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    International Nuclear Information System (INIS)

    Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

    2010-01-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

  6. Food security among individuals experiencing homelessness and mental illness in the At Home/Chez Soi Trial.

    Science.gov (United States)

    O'Campo, Patricia; Hwang, Stephen W; Gozdzik, Agnes; Schuler, Andrée; Kaufman-Shriqui, Vered; Poremski, Daniel; Lazgare, Luis Ivan Palma; Distasio, Jino; Belbraouet, Slimane; Addorisio, Sindi

    2017-08-01

    Individuals experiencing homelessness are particularly vulnerable to food insecurity. The At Home/Chez Soi study provides a unique opportunity to first examine baseline levels of food security among homeless individuals with mental illness and second to evaluate the effect of a Housing First (HF) intervention on food security in this population. At Home/Chez Soi was a 2-year randomized controlled trial comparing the effectiveness of HF compared with usual care among homeless adults with mental illness, stratified by level of need for mental health services (high or moderate). Logistic regressions tested baseline associations between food security (US Food Security Survey Module), study site, sociodemographic variables, duration of homelessness, alcohol/substance use, physical health and service utilization. Negative binomial regression determined the impact of the HF intervention on achieving levels of high or marginal food security over an 18-month follow-up period (6 to 24 months). Community settings at five Canadian sites (Moncton, Montreal, Toronto, Winnipeg and Vancouver). Homeless adults with mental illness (n 2148). Approximately 41 % of our sample reported high or marginal food security at baseline, but this figure varied with gender, age, mental health issues and substance use problems. High need participants who received HF were more likely to achieve marginal or high food security than those receiving usual care, but only at the Toronto and Moncton sites. Our large multi-site study demonstrated low levels of food security among homeless experiencing mental illness. HF showed promise for improving food security among participants with high levels of need for mental health services, with notable site differences.

  7. Characterization of dielectric materials in thin layers for the development of S.O.I. (Silicon on Insulator) substrates

    International Nuclear Information System (INIS)

    Gruber, Olivier

    1999-01-01

    This thesis deals with the characterization of oxide layer placed inside S.O.I. substrates and submitted to irradiation. This type of material is used for the development of hardened electronic components, that is to say components able to be used in a radiative environment. The irradiation induces charges (electrons or holes) in the recovered oxide. A part of these charges is trapped which leads to changes of the characteristics of the electronic components made on these substrates. The main topic of this study is the characterization of trapping properties of recovered oxides and more particularly of 'Unibond' material carried out with a new fabrication process: the 'smart-cut' process. This work is divided into three parts: - study with one carrier: this case is limited to low radiation doses where is only observed holes trapping. The evolution of the physical and chemical properties of the 'Unibond' material recovered oxide has been revealed, this evolution being due to the fabrication process. - Study with two carriers: in this case, there is trapping of holes and electrons. This type of trapping is observed in the case of strong radiation doses. A new type of electrons traps has been identified with the 'Unibond' material oxide. The transport and the trapping of holes and electrons have been studied in the case of transient phenomena created by short radiative pulses. This study has been carried out using a new measurement method. - Study with three carriers: here are added to holes and electrons the protons introduced in the recovered oxide by the annealing under hydrogen. These protons are movable when they are submitted to the effect of an electric field and they induce a memory effect according to their position in the oxide. These different works show that the 'Unibond' material is a very good solution for the future development of S.O.I. (author) [fr

  8. Modular High Voltage Power Supply

    Energy Technology Data Exchange (ETDEWEB)

    Newell, Matthew R. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

    2017-05-18

    The goal of this project is to develop a modular high voltage power supply that will meet the needs of safeguards applications and provide a modular plug and play supply for use with standard electronic racks.

  9. Reliability criteria for voltage stability

    Energy Technology Data Exchange (ETDEWEB)

    Taylor, Carson W; Silverstein, Brian L [Bonneville Power Administration, Portland, OR (United States)

    1994-12-31

    In face of costs pressures, there is need to allocate scare resources more effectively in order to achieve voltage stability. This naturally leads to development of probabilistic criteria and notions of rick management. In this paper it is presented a discussion about criteria for long term voltage stability limited to the case in which the time frames are topically several minutes. (author) 14 refs., 1 fig.

  10. High voltage distributions in RPCs

    International Nuclear Information System (INIS)

    Inoue, Y.; Muranishi, Y.; Nakamura, M.; Nakano, E.; Takahashi, T.; Teramoto, Y.

    1996-01-01

    High voltage distributions on the inner surfaces of RPCs electrodes were calculated by using a two-dimensional resistor network model. The calculated result shows that the surface resistivity of the electrodes should be high, compared to their volume resistivity, to get a uniform high voltage over the surface. Our model predicts that the rate capabilities of RPCs should be inversely proportional to the thickness of the electrodes if the ratio of surface-to-volume resistivity is low. (orig.)

  11. Macroeconomic Assessment of Voltage Sags

    Directory of Open Access Journals (Sweden)

    Sinan Küfeoğlu

    2016-12-01

    Full Text Available The electric power sector has changed dramatically since the 1980s. Electricity customers are now demanding uninterrupted and high quality service from both utilities and authorities. By becoming more and more dependent on the voltage sensitive electronic equipment, the industry sector is the one which is affected the most by voltage disturbances. Voltage sags are one of the most crucial problems for these customers. The utilities, on the other hand, conduct cost-benefit analyses before going through new investment projects. At this point, understanding the costs of voltage sags become imperative for planning purposes. The characteristics of electric power consumption and hence the susceptibility against voltage sags differ considerably among different industry subsectors. Therefore, a model that will address the estimation of worth of electric power reliability for a large number of customer groups is necessary. This paper introduces a macroeconomic model to calculate Customer Voltage Sag Costs (CVSCs for the industry sector customers. The proposed model makes use of analytical data such as value added, annual energy consumption, working hours, and average outage durations and provides a straightforward, credible, and easy to follow methodology for the estimation of CVSCs.

  12. A matter of quantum voltages

    Energy Technology Data Exchange (ETDEWEB)

    Sellner, Bernhard; Kathmann, Shawn M., E-mail: Shawn.Kathmann@pnnl.gov [Physical Sciences Division, Pacific Northwest National Laboratory, Richland, Washington 99352 (United States)

    2014-11-14

    Voltages inside matter are relevant to crystallization, materials science, biology, catalysis, and aqueous chemistry. The variation of voltages in matter can be measured by experiment, however, modern supercomputers allow the calculation of accurate quantum voltages with spatial resolutions of bulk systems well beyond what can currently be measured provided a sufficient level of theory is employed. Of particular interest is the Mean Inner Potential (V{sub o}) – the spatial average of these quantum voltages referenced to the vacuum. Here we establish a protocol to reliably evaluate V{sub o} from quantum calculations. Voltages are very sensitive to the distribution of electrons and provide metrics to understand interactions in condensed phases. In the present study, we find excellent agreement with measurements of V{sub o} for vitrified water and salt crystals and demonstrate the impact of covalent and ionic bonding as well as intermolecular/atomic interactions. Certain aspects in this regard are highlighted making use of simple model systems/approximations. Furthermore, we predict V{sub o} as well as the fluctuations of these voltages in aqueous NaCl electrolytes and characterize the changes in their behavior as the resolution increases below the size of atoms.

  13. Mitigation of voltage sags in the distribution system with dynamic voltage restorer

    International Nuclear Information System (INIS)

    Viglas, D.; Belan, A.

    2012-01-01

    Dynamic voltage restorer is a custom power device that is used to improve voltage sags or swells in electrical distribution system. The components of the Dynamic Voltage Restorer consist of injection transformers, voltage source inverter, passive filters and energy storage. The main function of the Dynamic voltage restorer is used to inject three phase voltage in series and in synchronism with the grid voltages in order to compensate voltage disturbances. This article deals with mitigation of voltage sags caused by three-phase short circuit. Dynamic voltage restorer is modelled in MATLAB/Simulink. (Authors)

  14. A 6 device SOI new technology for mixed analog-digital and rad-hard applications

    International Nuclear Information System (INIS)

    Blanc, J.P.; Bonaime, J.; Delevoye, E.; Pontcharra, J. de; Gautier, J.; Truche, R.

    1993-01-01

    DMILL technology is being developed for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva). Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2μm thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric isolation and low temperature process. The mean feature is that six different components are fabricated on the same wafer, taking into account the 12 volts supply voltage constraint for some analog applications. The first electrical characteristics are presented in this paper. The optimization capabilities of such a hardened CBi-CJ-CMOS technology are discussed

  15. SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

    International Nuclear Information System (INIS)

    Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

    1993-01-01

    A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

  16. Tailoring the High-Q LC Filter Arrays for Readout of Kilo-Pixel TES Arrays in the SPICA-SAFARI Instrument

    Science.gov (United States)

    Bruijn, M. P.; Gottardi, L.; den Hartog, R. H.; van der Kuur, J.; van der Linden, A. J.; Jackson, B. D.

    2014-08-01

    Following earlier presentations of arrays of high quality factor (Q 10.000) superconducting resonators in the MHz regime, we report on improvement of the packing density of resonance frequencies to 160 in the 1-3 MHz band. Spread in the spacing of resonances is found to be limited to 1 kHz (1 with the present fabrication procedure. The present packing density of frequencies and chip area approaches the requirements for the SAFARI instrument on the SPICA mission (in preparation). The a-Si:H dielectric layer in the planar S-I-S capacitors shows a presently unexplained apparent negative effective series resistance, depending on operating temperature and applied testing voltage.

  17. Low-Energy Real-Time OS Using Voltage Scheduling Algorithm for Variable Voltage Processors

    OpenAIRE

    Okuma, Takanori; Yasuura, Hiroto

    2001-01-01

    This paper presents a real-time OS based on $ mu $ITRON using proposed voltage scheduling algorithm for variable voltage processors which can vary supply voltage dynamically. The proposed voltage scheduling algorithms assign voltage level for each task dynamically in order to minimize energy consumption under timing constraints. Using the presented real-time OS, running tasks with low supply voltage leads to drastic energy reduction. In addition, the presented voltage scheduling algorithm is ...

  18. Development of a New Cascade Voltage-Doubler for Voltage Multiplication

    OpenAIRE

    Toudeshki, Arash; Mariun, Norman; Hizam, Hashim; Abdul Wahab, Noor Izzri

    2014-01-01

    For more than eight decades, cascade voltage-doubler circuits are used as a method to produce DC output voltage higher than the input voltage. In this paper, the topological developments of cascade voltage-doublers are reviewed. A new circuit configuration for cascade voltage-doubler is presented. This circuit can produce a higher value of the DC output voltage and better output quality compared to the conventional cascade voltage-doubler circuits, with the same number of stages.

  19. Cavity Voltage Phase Modulation MD

    CERN Document Server

    Mastoridis, Themistoklis; Molendijk, John; Timko, Helga; CERN. Geneva. ATS Department

    2016-01-01

    The LHC RF/LLRF system is currently configured for extremely stable RF voltage to minimize transient beam loading effects. The present scheme cannot be extended beyond nominal beam current since the demanded power would exceed the peak klystron power and lead to saturation. A new scheme has therefore been proposed: for beam currents above nominal (and possibly earlier), the cavity phase modulation by the beam will not be corrected (transient beam loading), but the strong RF feedback and One-Turn Delay feedback will still be active for loop and beam stability in physics. To achieve this, the voltage set point will be adapted for each bunch. The goal of this MD was to test a new algorithm that would adjust the voltage set point to achieve the cavity phase modulation that would minimize klystron forward power.

  20. On-chip grating coupler array on the SOI platform for fan-in/fan-out of multi-core fibers with low insertion loss and crosstalk

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ye, Feihong; Peucheret, Christophe

    2014-01-01

    We design and fabricate a compact multi-core fiber fan-in/fan-out using a fully-etched grating coupler array on the SOI platform. Lowest coupling loss of 6.8 dB with 3 dB bandwidth of 48 nm and crosstalk lower than ×32 dB are demonstrated.......We design and fabricate a compact multi-core fiber fan-in/fan-out using a fully-etched grating coupler array on the SOI platform. Lowest coupling loss of 6.8 dB with 3 dB bandwidth of 48 nm and crosstalk lower than ×32 dB are demonstrated....

  1. Design of shielded voltage divider for impulse voltage measurement

    International Nuclear Information System (INIS)

    Kato, Shohei; Kouno, Teruya; Maruyama, Yoshio; Kikuchi, Koji.

    1976-01-01

    The dividers used for the study of the insulation and electric discharge phenomena in high voltage equipments have the problems of the change of response characteristics owing to adjacent bodies and of induced noise. To improve the characteristics, the enclosed type divider shielded with metal has been investigated, and the divider of excellent response has been obtained by adopting the frequency-separating divider system, which is divided into two parts, resistance divider (lower frequency region) and capacitance divider (higher frequency region), for avoiding to degrade the response. Theoretical analysis was carried out in the cases that residual inductance can be neglected or can not be neglected in the small capacitance divider, and that the connecting wires are added. Next, the structure of the divider and the design of the electric field for the divider manufactured on the basis of the theory are described. The response characteristics were measured. The results show that 1 MV impulse voltage can be measured within the response time of 10 ns. Though this divider aims at the impulse voltage, the duration time of which is about that of standard lightning impulse, in view of the heat capacity because of the input resistance of 10.5 kΩ, it is expected that the divider can be applied to the voltage of longer duration time by increasing the input resistance in future. (Wakatsuki, Y.)

  2. Unbalanced Voltage Compensation in Low Voltage Residential AC Grids

    DEFF Research Database (Denmark)

    Trintis, Ionut; Douglass, Philip; Munk-Nielsen, Stig

    2016-01-01

    This paper describes the design and test of a control algorithm for active front-end rectifiers that draw power from a residential AC grid to feed heat pump loads. The control algorithm is able to control the phase to neutral or phase to phase RMS voltages at the point of common coupling...

  3. The high voltage homopolar generator

    Science.gov (United States)

    Price, J. H.; Gully, J. H.; Driga, M. D.

    1986-11-01

    System and component design features of proposed high voltage homopolar generator (HVHPG) are described. The system is to have an open circuit voltage of 500 V, a peak output current of 500 kA, 3.25 MJ of stored inertial energy and possess an average magnetic-flux density of 5 T. Stator assembly components are discussed, including the stator, mount structure, hydrostatic bearings, main and motoring brushgears and rotor. Planned operational procedures such as monitoring the rotor to full speed and operation with a superconducting field coil are delineated.

  4. Fabrication of SGOI material by oxidation of an epitaxial SiGe layer on an SOI wafer with H ions implantation

    International Nuclear Information System (INIS)

    Cheng Xinli; Chen Zhijun; Wang Yongjin; Jin Bo; Zhang Feng; Zou Shichang

    2005-01-01

    SGOI materials were fabricated by thermal dry oxidation of epitaxial H-ion implanted SiGe layers on SOI wafers. The hydrogen implantation was found to delay the oxidation rate of SiGe layer and to decrease the loss of Ge atoms during oxidation. Further, the H implantation did not degrade the crystallinity of SiGe layer during fabrication of the SGOI

  5. Resilient architecture design for voltage variation

    CERN Document Server

    Reddi, Vijay Janapa

    2013-01-01

    Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe

  6. Voltage Weak DC Distribution Grids

    NARCIS (Netherlands)

    Hailu, T.G.; Mackay, L.J.; Ramirez Elizondo, L.M.; Ferreira, J.A.

    2017-01-01

    This paper describes the behavior of voltage weak DC distribution systems. These systems have relatively small system capacitance. The size of system capacitance, which stores energy, has a considerable effect on the value of fault currents, control complexity, and system reliability. A number of

  7. Nonlinear electrokinetics at large voltages

    Energy Technology Data Exchange (ETDEWEB)

    Bazant, Martin Z [Department of Chemical Engineering and Institute for Soldier Nanotechnologies, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Sabri Kilic, Mustafa; Ajdari, Armand [Department of Mathematics, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Storey, Brian D [Franklin W Olin College of Engineering, Needham, MA 02492 (United States)], E-mail: bazant@mit.edu

    2009-07-15

    The classical theory of electrokinetic phenomena assumes a dilute solution of point-like ions in chemical equilibrium with a surface whose double-layer voltage is of order the thermal voltage, k{sub B}T/e=25 mV. In nonlinear 'induced-charge' electrokinetic phenomena, such as ac electro-osmosis, several volts {approx}100k{sub B}T/e are applied to the double layer, and the theory breaks down and cannot explain many observed features. We argue that, under such a large voltage, counterions 'condense' near the surface, even for dilute bulk solutions. Based on simple models, we predict that the double-layer capacitance decreases and the electro-osmotic mobility saturates at large voltages, due to steric repulsion and increased viscosity of the condensed layer, respectively. The former suffices to explain observed high-frequency flow reversal in ac electro-osmosis; the latter leads to a salt concentration dependence of induced-charge flows comparable to experiments, although a complete theory is still lacking.

  8. High voltage power network construction

    CERN Document Server

    Harker, Keith

    2018-01-01

    This book examines the key requirements, considerations, complexities and constraints relevant to the task of high voltage power network construction, from design, finance, contracts and project management to installation and commissioning, with the aim of providing an overview of the holistic end to end construction task in a single volume.

  9. Voltage control of ferromagnetic resonance

    Directory of Open Access Journals (Sweden)

    Ziyao Zhou

    2016-06-01

    Full Text Available Voltage control of magnetism in multiferroics, where the ferromagnetism and ferroelectricity are simultaneously exhibiting, is of great importance to achieve compact, fast and energy efficient voltage controllable magnetic/microwave devices. Particularly, these devices are widely used in radar, aircraft, cell phones and satellites, where volume, response time and energy consumption is critical. Researchers realized electric field tuning of magnetic properties like magnetization, magnetic anisotropy and permeability in varied multiferroic heterostructures such as bulk, thin films and nanostructure by different magnetoelectric (ME coupling mechanism: strain/stress, interfacial charge, spin–electromagnetic (EM coupling and exchange coupling, etc. In this review, we focus on voltage control of ferromagnetic resonance (FMR in multiferroics. ME coupling-induced FMR change is critical in microwave devices, where the electric field tuning of magnetic effective anisotropic field determines the tunability of the performance of microwave devices. Experimentally, FMR measurement technique is also an important method to determine the small effective magnetic field change in small amount of magnetic material precisely due to its high sensitivity and to reveal the deep science of multiferroics, especially, voltage control of magnetism in novel mechanisms like interfacial charge, spin–EM coupling and exchange coupling.

  10. High voltage MOSFET switching circuit

    Science.gov (United States)

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  11. Voltage linear transformation circuit design

    Science.gov (United States)

    Sanchez, Lucas R. W.; Jin, Moon-Seob; Scott, R. Phillip; Luder, Ryan J.; Hart, Michael

    2017-09-01

    Many engineering projects require automated control of analog voltages over a specified range. We have developed a computer interface comprising custom hardware and MATLAB code to provide real-time control of a Thorlabs adaptive optics (AO) kit. The hardware interface includes an op amp cascade to linearly shift and scale a voltage range. With easy modifications, any linear transformation can be accommodated. In AO applications, the design is suitable to drive a range of different types of deformable and fast steering mirrors (FSM's). Our original motivation and application was to control an Optics in Motion (OIM) FSM which requires the customer to devise a unique interface to supply voltages to the mirror controller to set the mirror's angular deflection. The FSM is in an optical servo loop with a wave front sensor (WFS), which controls the dynamic behavior of the mirror's deflection. The code acquires wavefront data from the WFS and fits a plane, which is subsequently converted into its corresponding angular deflection. The FSM provides +/-3° optical angular deflection for a +/-10 V voltage swing. Voltages are applied to the mirror via a National Instruments digital-to-analog converter (DAC) followed by an op amp cascade circuit. This system has been integrated into our Thorlabs AO testbed which currently runs at 11 Hz, but with planned software upgrades, the system update rate is expected to improve to 500 Hz. To show that the FSM subsystem is ready for this speed, we conducted two different PID tuning runs at different step commands. Once 500 Hz is achieved, we plan to make the code and method for our interface solution freely available to the community.

  12. Photographie et représentation de soi dans W ou le Souvenir d’enfance de Georges Perec

    Directory of Open Access Journals (Sweden)

    Siriki Ouattara

    2014-04-01

    Full Text Available W ou le souvenir d’enfance convoque ouvertement en son sein des éléments paralittéraires comme la photographie qui le déconstruit. Le désir de Georges Perec de reconstituer ou de reconstruire son histoire est si ardent qu’il lui a consacré ce roman particulier. Dans cette œuvre autobiographique atypique, l’auteur fait appel à diverses techniques de représentation de soi, la photographie. Cette dernière est un élément nouveau en littérature (même s´elle y est prise en compte depuis le dix-neuvième siècle qui redéfinit nombre d´habitudes littéraires. Ainsi, elle occasionne un renouvellement de l´écriture à travers l´institution de nouveaux rapports qui, tout en changeant les vieux rôles narratifs, invitent à dire autrement, voire à raconter différemment. La photographie offre alors l´occasion d´expérimenter une nouvelle discursivité de la représentation.

  13. Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

    International Nuclear Information System (INIS)

    Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

    2008-01-01

    Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

  14. Analyzing randomly occurring voltage breakdowns

    International Nuclear Information System (INIS)

    Wiltshire, C.W.

    1977-01-01

    During acceptance testing of high-vacuum neutron tubes, 40% of the tubes failed after experiencing high-voltage breakdowns during the aging process. Use of a digitizer in place of an oscilloscope revealed two types of breakdowns, only one of which affected acceptance testing. This information allowed redesign of the aging sequence to prevent tube damage and improve yield and quality of the final product

  15. Advances in high voltage engineering

    CERN Document Server

    Haddad, A

    2005-01-01

    This book addresses the very latest research and development issues in high voltage technology and is intended as a reference source for researchers and students in the field, specifically covering developments throughout the past decade. This unique blend of expert authors and comprehensive subject coverage means that this book is ideally suited as a reference source for engineers and academics in the field for years to come.

  16. High-voltage CMOS detectors

    International Nuclear Information System (INIS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-01-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  17. Low voltage electron beam accelerators

    International Nuclear Information System (INIS)

    Ochi, Masafumi

    2003-01-01

    Widely used electron accelerators in industries are the electron beams with acceleration voltage at 300 kV or less. The typical examples are shown on manufactures in Japan, equipment configuration, operation, determination of process parameters, and basic maintenance requirement of the electron beam processors. New electron beam processors with acceleration voltage around 100 kV were introduced maintaining the relatively high dose speed capability of around 10,000 kGy x mpm at production by ESI (Energy Science Inc. USA, Iwasaki Electric Group). The application field like printing and coating for packaging requires treating thickness of 30 micron or less. It does not require high voltage over 110 kV. Also recently developed is a miniature bulb type electron beam tube with energy less than 60 kV. The new application area for this new electron beam tube is being searched. The drive force of this technology to spread in the industries would be further development of new application, process and market as well as the price reduction of the equipment, upon which further acknowledgement and acceptance of the technology to societies and industries would entirely depend. (Y. Tanaka)

  18. High-voltage CMOS detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

    2016-07-11

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  19. Low voltage electron beam accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Ochi, Masafumi [Iwasaki Electric Co., Ltd., Tokyo (Japan)

    2003-02-01

    Widely used electron accelerators in industries are the electron beams with acceleration voltage at 300 kV or less. The typical examples are shown on manufactures in Japan, equipment configuration, operation, determination of process parameters, and basic maintenance requirement of the electron beam processors. New electron beam processors with acceleration voltage around 100 kV were introduced maintaining the relatively high dose speed capability of around 10,000 kGy x mpm at production by ESI (Energy Science Inc. USA, Iwasaki Electric Group). The application field like printing and coating for packaging requires treating thickness of 30 micron or less. It does not require high voltage over 110 kV. Also recently developed is a miniature bulb type electron beam tube with energy less than 60 kV. The new application area for this new electron beam tube is being searched. The drive force of this technology to spread in the industries would be further development of new application, process and market as well as the price reduction of the equipment, upon which further acknowledgement and acceptance of the technology to societies and industries would entirely depend. (Y. Tanaka)

  20. Light-voltage conversion apparatus

    Energy Technology Data Exchange (ETDEWEB)

    Fujioka, Yoshiki

    1987-09-19

    In a light-voltage conversion unit, when input signal is applied, the output signal to the control circuit has quick rise-up time and slow breaking time. In order to improve this, a short-circuit transistor is placed at the diode, and this transistor is forced ON, when an output signal to the control circuit is lowered down to a constant voltage, to short-circuit between the output terminals. This, however, has a demerit of high power consumption by a transistor. In this invention, by connecting a light-emitting element which gets ON at the first transition and a light-emitting element which gets ON at the last transition, placing a light receiving element in front of each light-emitting element, when an input signal is applied; thus a load is driven only with ON signal of each light-emitting element, eliminating the delay in the last transition. All of these give a quick responsive light-voltage conversion without unnecessary power consumption. (5 figs)

  1. [Development of residual voltage testing equipment].

    Science.gov (United States)

    Zeng, Xiaohui; Wu, Mingjun; Cao, Li; He, Jinyi; Deng, Zhensheng

    2014-07-01

    For the existing measurement methods of residual voltage which can't turn the power off at peak voltage exactly and simultaneously display waveforms, a new residual voltage detection method is put forward in this paper. First, the zero point of the power supply is detected with zero cross detection circuit and is inputted to a single-chip microcomputer in the form of pulse signal. Secend, when the zero point delays to the peak voltage, the single-chip microcomputer sends control signal to power off the relay. At last, the waveform of the residual voltage is displayed on a principal computer or oscilloscope. The experimental results show that the device designed in this paper can turn the power off at peak voltage and is able to accurately display the voltage waveform immediately after power off and the standard deviation of the residual voltage is less than 0.2 V at exactly one second and later.

  2. Symmetric voltage-controlled variable resistance

    Science.gov (United States)

    Vanelli, J. C.

    1978-01-01

    Feedback network makes resistance of field-effect transistor (FET) same for current flowing in either direction. It combines control voltage with source and load voltages to give symmetric current/voltage characteristics. Since circuit produces same magnitude output voltage for current flowing in either direction, it introduces no offset in presense of altering polarity signals. It is therefore ideal for sensor and effector circuits in servocontrol systems.

  3. Ultra Low-Voltage Energy Harvesting

    Science.gov (United States)

    2013-09-01

    if in a solar battery charger the level of illumination were to drop due to cloud cover, the diode would prevent discharging of the battery when...the source voltage becomes lower than battery voltage. The drawback of a simple circuit like this is that once the source voltage is lower than the...longer charged when the battery voltage is above the OV setting. Figure 13. Block diagram of BQ25504 circuit . (From [10]) 18 THIS PAGE

  4. Voltage Quality of Grid Connected Wind Turbines

    DEFF Research Database (Denmark)

    Chen, Zhe; Blaabjerg, Frede; Sun, Tao

    2004-01-01

    Grid connected wind turbines may cause quality problems, such as voltage variation and flicker. This paper discusses the voltage variation and flicker emission of grid connected wind turbines with doubly-fed induction generators. A method to compensate flicker by using a voltage source converter...

  5. Manufacturing technology for practical Josephson voltage normals

    International Nuclear Information System (INIS)

    Kohlmann, Johannes; Kieler, Oliver

    2016-01-01

    In this contribution we present the manufacturing technology for the fabrication of integrated superconducting Josephson serial circuits for voltage normals. First we summarize some foundations for Josephson voltage normals and sketch the concept and the setup of the circuits, before we describe the manufacturing technology form modern practical Josephson voltage normals.

  6. 49 CFR 234.221 - Lamp voltage.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Lamp voltage. 234.221 Section 234.221 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION..., Inspection, and Testing Maintenance Standards § 234.221 Lamp voltage. The voltage at each lamp shall be...

  7. Bootstrapped Low-Voltage Analog Switches

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1999-01-01

    Novel low-voltage constant-impedance analog switch circuits are proposed. The switch element is a single MOSFET, and constant-impedance operation is obtained using simple circuits to adjust the gate and bulk voltages relative to the switched signal. Low-voltage (1-volt) operation is made feasible...

  8. Voltage generators of high voltage high power accelerators

    International Nuclear Information System (INIS)

    Svinin, M.P.

    1981-01-01

    High voltage electron accelerators are widely used in modern radiation installations for industrial purposes. In the near future further increasing of their power may be effected, which enables to raise the efficiency of the radiation processes known and to master new power-consuming production in industry. Improvement of HV generators by increasing their power and efficiency is one of many scientific and engineering aspects the successful solution of which provides further development of these accelerators and their technical parameters. The subject is discussed in detail. (author)

  9. SEMICONDUCTOR DEVICES: Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    Science.gov (United States)

    Jin, Li; Hongxia, Liu; Bin, Li; Lei, Cao; Bo, Yuan

    2010-08-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a “rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

  10. Invention de soi et compétences à l’ère des réseaux sociaux

    Directory of Open Access Journals (Sweden)

    Daniel Apollon

    2011-06-01

    Full Text Available Les réseaux sociaux en ligne encouragent de nouvelles approches de la compétence centrées sur la construction biographique de l’individu et l’invention de soi. Ce nouvel art de faire des « produsagers », répond au besoin d’inventer une réponse individuelle et collective au sentiment aliénant de vacuité des sociétés post-industrielles et post-traditionnelles. Combinant opposition et soumission aux éléments structurants et aliénants de cette modernité tardive, ces produsagers réactualisent diverses ruses, tactiques et schèmes immémoriaux déjà explorés par divers auteurs avant Internet. Sur cette toile de fond, l’auteur propose une réinterprétation plus large de la notion de compétence.Social media practices encourage new approaches and visions of competence focusing on the construction of individual biography and the "invention of oneself". The new "artful skills" of "produsers" address the need to invent individual and collective responses to the sense of alienating emptiness pervading postindustrial and posttraditional societies. Combining and submission and opposition to both structuring and alienating aspects of late modernity, these produsagers actualize various tricks, tactics and immemorial schemes already mapped by various authors before the Internet. On this backdrop the author proposes a broader reinterpretation of the concept of competence.

  11. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  12. Analysis of photonic spot profile converter and bridge structure on SOI platform for horizontal and vertical integration

    Science.gov (United States)

    Majumder, Saikat; Jha, Amit Kr.; Biswas, Aishik; Banerjee, Debasmita; Ganguly, Dipankar; Chakraborty, Rajib

    2017-08-01

    Horizontal spot size converter required for horizontal light coupling and vertical bridge structure required for vertical integration are designed on high index contrast SOI platform in order to form more compact integrated photonic circuits. Both the structures are based on the concept of multimode interference. The spot size converter can be realized by successive integration of multimode interference structures with reducing dimension on horizontal plane, whereas the optical bridge structure consists of a number of vertical multimode interference structure connected by single mode sections. The spot size converter can be modified to a spot profile converter when the final single mode waveguide is replaced by a slot waveguide. Analysis have shown that by using three multimode sections in a spot size converter, an Gaussian input having spot diameter of 2.51 μm can be converted to a spot diameter of 0.25 μm. If the output single mode section is replaced by a slot waveguide, this input profile can be converted to a flat top profile of width 50 nm. Similarly, vertical displacement of 8μm is possible by using a combination of two multimode sections and three single mode sections in the vertical bridge structure. The analyses of these two structures are carried out for both TE and TM modes at 1550 nm wavelength using the semi analytical matrix method which is simple and fast in computation time and memory. This work shows that the matrix method is equally applicable for analysis of horizontally as well as vertically integrated photonic circuit.

  13. Voltage Management in Unbalanced Low Voltage Networks Using a Decoupled Phase-Tap-Changer Transformer

    DEFF Research Database (Denmark)

    Coppo, Massimiliano; Turri, Roberto; Marinelli, Mattia

    2014-01-01

    The paper studies a medium voltage-low voltage transformer with a decoupled on load tap changer capability on each phase. The overall objective is the evaluation of the potential benefits on a low voltage network of such possibility. A realistic Danish low voltage network is used for the analysis...

  14. 76 FR 70721 - Voltage Coordination on High Voltage Grids; Notice of Staff Workshop

    Science.gov (United States)

    2011-11-15

    ... DEPARTMENT OF ENERGY Federal Energy Regulatory Commission [Docket No. AD12-5-000] Voltage Coordination on High Voltage Grids; Notice of Staff Workshop Take notice that the Federal Energy Regulatory Commission will hold a Workshop on Voltage Coordination on High Voltage Grids on Thursday, December 1, 2011...

  15. Piezo Voltage Controlled Planar Hall Effect Devices.

    Science.gov (United States)

    Zhang, Bao; Meng, Kang-Kang; Yang, Mei-Yin; Edmonds, K W; Zhang, Hao; Cai, Kai-Ming; Sheng, Yu; Zhang, Nan; Ji, Yang; Zhao, Jian-Hua; Zheng, Hou-Zhi; Wang, Kai-You

    2016-06-22

    The electrical control of the magnetization switching in ferromagnets is highly desired for future spintronic applications. Here we report on hybrid piezoelectric (PZT)/ferromagnetic (Co2FeAl) devices in which the planar Hall voltage in the ferromagnetic layer is tuned solely by piezo voltages. The change of planar Hall voltage is associated with magnetization switching through 90° in the plane under piezo voltages. Room temperature magnetic NOT and NOR gates are demonstrated based on the piezo voltage controlled Co2FeAl planar Hall effect devices without the external magnetic field. Our demonstration may lead to the realization of both information storage and processing using ferromagnetic materials.

  16. Capacitor Voltages Measurement and Balancing in Flying Capacitor Multilevel Converters Utilizing a Single Voltage Sensor

    DEFF Research Database (Denmark)

    Farivar, Glen; Ghias, Amer M. Y. M.; Hredzak, Branislav

    2017-01-01

    This paper proposes a new method for measuring capacitor voltages in multilevel flying capacitor (FC) converters that requires only one voltage sensor per phase leg. Multiple dc voltage sensors traditionally used to measure the capacitor voltages are replaced with a single voltage sensor at the ac...... side of the phase leg. The proposed method is subsequently used to balance the capacitor voltages using only the measured ac voltage. The operation of the proposed measurement and balancing method is independent of the number of the converter levels. Experimental results presented for a five-level FC...

  17. Voltage-Gated Calcium Channels

    Science.gov (United States)

    Zamponi, Gerald Werner

    Voltage Gated Calcium Channels is the first comprehensive book in the calcium channel field, encompassing over thirty years of progress towards our understanding of calcium channel structure, function, regulation, physiology, pharmacology, and genetics. This book balances contributions from many of the leading authorities in the calcium channel field with fresh perspectives from risings stars in the area, taking into account the most recent literature and concepts. This is the only all-encompassing calcium channel book currently available, and is an essential resource for academic researchers at all levels in the areas neuroscience, biophysics, and cardiovascular sciences, as well as to researchers in the drug discovery area.

  18. Influence of Bipolar Pulse Poling Technique for Piezoelectric Vibration Energy Harvesters using Pb(Zr,Ti)O3 Films on 200 mm SOI Wafers

    International Nuclear Information System (INIS)

    Moriwaki, N; Fujimoto, K; Suzuki, K; Kobayashi, T; Itoh, T; Maeda, R; Suzuki, Y; Makimoto, N

    2013-01-01

    Piezoelectric vibration energy harvester arrays using Pb(Zr,Ti)O 3 thin films on 200 mm SOI wafers were fabricated. In-plane distribution of influence of bipolar pulse poling technique on direct current (DC) power output from the harvesters was investigated. The results indicate that combination poling treatment of DC and bipolar pulse poling increases a piezoelectric property and reduces a dielectric constant. It means that this poling technique improves the figure of merit of sensors and harvesters. Maximum DC power from a harvester treated by DC poling after bipolar pulse poling is about five times larger than a one treated by DC poling only

  19. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

    Science.gov (United States)

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-11-17

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a silicon photonics technology.

  20. Beyond voltage-gated ion channels: Voltage-operated membrane proteins and cellular processes.

    Science.gov (United States)

    Zhang, Jianping; Chen, Xingjuan; Xue, Yucong; Gamper, Nikita; Zhang, Xuan

    2018-04-18

    Voltage-gated ion channels were believed to be the only voltage-sensitive proteins in excitable (and some non-excitable) cells for a long time. Emerging evidence indicates that the voltage-operated model is shared by some other transmembrane proteins expressed in both excitable and non-excitable cells. In this review, we summarize current knowledge about voltage-operated proteins, which are not classic voltage-gated ion channels as well as the voltage-dependent processes in cells for which single voltage-sensitive proteins have yet to be identified. Particularly, we will focus on the following. (1) Voltage-sensitive phosphoinositide phosphatases (VSP) with four transmembrane segments homologous to the voltage sensor domain (VSD) of voltage-gated ion channels; VSPs are the first family of proteins, other than the voltage-gated ion channels, for which there is sufficient evidence for the existence of the VSD domain; (2) Voltage-gated proton channels comprising of a single voltage-sensing domain and lacking an identified pore domain; (3) G protein coupled receptors (GPCRs) that mediate the depolarization-evoked potentiation of Ca 2+ mobilization; (4) Plasma membrane (PM) depolarization-induced but Ca 2+ -independent exocytosis in neurons. (5) Voltage-dependent metabolism of phosphatidylinositol 4,5-bisphosphate (PtdIns[4,5]P 2 , PIP 2 ) in the PM. These recent discoveries expand our understanding of voltage-operated processes within cellular membranes. © 2018 Wiley Periodicals, Inc.

  1. Observability of Low Voltage grids

    DEFF Research Database (Denmark)

    Martin-Loeches, Ruben Sánchez; Iov, Florin; Kemal, Mohammed Seifu

    2017-01-01

    Low Voltage (LV) distribution power grids are experiencing a transformation from a passive to a more active role due to the increasing penetration of distributed generation, heat pumps and electrical vehicles. The first step towards a smarter operation of LV electrical systems is to provide grid ...... an updated state of the art on DSSE-AMI based, adaptive data collection techniques and database management system types. Moreover, the ongoing Danish RemoteGRID project is presented as a realistic case study.......Low Voltage (LV) distribution power grids are experiencing a transformation from a passive to a more active role due to the increasing penetration of distributed generation, heat pumps and electrical vehicles. The first step towards a smarter operation of LV electrical systems is to provide grid....... It becomes unrealistic to provide near real time full observability of the LV grid by applying Distribution System State Estimation (DSSE) utilizing the classical data collection and storage/preprocessing techniques. This paper investigates up-todate the observability problem in LV grids by providing...

  2. Fully-etched apodized fiber-to-chip grating coupler on the SOI platform with -0.78 dB coupling efficiency using photonic crystals and bonded Al mirror

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Peucheret, Christophe

    2014-01-01

    We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated.......We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated....

  3. Power conditioning using dynamic voltage restorers under different voltage sag types.

    Science.gov (United States)

    Saeed, Ahmed M; Abdel Aleem, Shady H E; Ibrahim, Ahmed M; Balci, Murat E; El-Zahab, Essam E A

    2016-01-01

    Voltage sags can be symmetrical or unsymmetrical depending on the causes of the sag. At the present time, one of the most common procedures for mitigating voltage sags is by the use of dynamic voltage restorers (DVRs). By definition, a DVR is a controlled voltage source inserted between the network and a sensitive load through a booster transformer injecting voltage into the network in order to correct any disturbance affecting a sensitive load voltage. In this paper, modelling of DVR for voltage correction using MatLab software is presented. The performance of the device under different voltage sag types is described, where the voltage sag types are introduced using the different types of short-circuit faults included in the environment of the MatLab/Simulink package. The robustness of the proposed device is evaluated using the common voltage sag indices, while taking into account voltage and current unbalance percentages, where maintaining the total harmonic distortion percentage of the load voltage within a specified range is desired. Finally, several simulation results are shown in order to highlight that the DVR is capable of effective correction of the voltage sag while minimizing the grid voltage unbalance and distortion, regardless of the fault type.

  4. High voltage load resistor array

    Science.gov (United States)

    Lehmann, Monty Ray [Smithfield, VA

    2005-01-18

    A high voltage resistor comprising an array of a plurality of parallel electrically connected resistor elements each containing a resistive solution, attached at each end thereof to an end plate, and about the circumference of each of the end plates, a corona reduction ring. Each of the resistor elements comprises an insulating tube having an electrode inserted into each end thereof and held in position by one or more hose clamps about the outer periphery of the insulating tube. According to a preferred embodiment, the electrode is fabricated from stainless steel and has a mushroom shape at one end, that inserted into the tube, and a flat end for engagement with the end plates that provides connection of the resistor array and with a load.

  5. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

    International Nuclear Information System (INIS)

    Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

    2014-01-01

    In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

  6. L’empathie comme outil herméneutique du soi: Note sur Paul Ricœur et Heinz Kohut

    Directory of Open Access Journals (Sweden)

    Michel Dupuis

    2011-01-01

    Full Text Available Le bref texte que Paul Ricœur consacre en 1986 à la psychanalyse développée par Heinz Kohut révèle une réinterprétation phénoménologique à la fois du contenu et des fonctions de l'empathie, au total considérée comme un véritable outil à l'œuvre dans l'herméneutique du soi. La vision kohutienne de la constitution du soi et du processus thérapeutique analytique produit une espèce de “dé-sentimentalisation” de l'empathie, en soulignant le rôle crucial du transfert intersubjectif, fort à distance de la théorie (freudienne solipsiste de l'ego.The short text published in 1986 by Paul Ricoeur about Heinz Kohut's psychoanalysis of the self reveals a phenomenological reinterpretation of the content and the functions of empathy, finally considered as an effective tool of the hermeneutics of the self. Kohut's model of constitution of the self and of the therapeutic analytical process produces a kind of “de-sentimentalization” of empathy, pointing to the crucial role of intersubjective transfer, far from a (Freudian solipsistic theory of the ego.

  7. Effect of the Ion Mass and Energy on the Response of 70-nm SOI Transistors to the Ion Deposited Charge by Direct Ionization

    International Nuclear Information System (INIS)

    Raine, M.; Gaillardin, M.; Sauvestre, J.E.; Flament, O.; Bournel, A.; Aubry-Fortuna, V.

    2010-01-01

    The response of SOI transistors under heavy ion irradiation is analyzed using Geant4 and Synopsys Sentaurus device simulations. The ion mass and energy have a significant impact on the radial ionization profile of the ion deposited charge. For example, for an identical LET, the higher the ion energy per nucleon, the wider the radial ionization track. For a 70-nm SOI technology, the track radius of high energy ions (≥ 10 MeV/a) is larger than the transistor sensitive volume; part of the ion charge recombines in the highly doped source or drain regions and does not participate to the transistor electric response. At lower energy (≤ 10 MeV/a), as often used for ground testing, the track radius is smaller than the transistor sensitive volume, and the entire charge is used for the transistor response. The collected charge is then higher, corresponding to a worst-case response of the transistor. Implications for the hardness assurance of highly-scaled generations are discussed. (authors)

  8. arXiv Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

    CERN Document Server

    INSPIRE-00541780; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

    2017-10-25

    Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The r...

  9. Theoretical analysis of magnetic sensor output voltage

    International Nuclear Information System (INIS)

    Liu Haishun; Dun Chaochao; Dou Linming; Yang Weiming

    2011-01-01

    The output voltage is an important parameter to determine the stress state in magnetic stress measurement, the relationship between the output voltage and the difference in the principal stresses was investigated by a comprehensive application of magnetic circuit theory, magnetization theory, stress analysis as well as the law of electromagnetic induction, and a corresponding quantitative equation was derived. It is drawn that the output voltage is proportional to the difference in the principal stresses, and related to the angle between the principal stress and the direction of the sensor. This investigation provides a theoretical basis for the principle stresses measurement by output voltage. - Research highlights: → A comprehensive investigation of magnetic stress signal. → Derived a quantitative equation about output voltage and the principal stresses. → The output voltage is proportional to the difference of the principal stresses. → Provide a theoretical basis for the principle stresses measurement.

  10. Voltage-Controlled Floating Resistor Using DDCC

    Directory of Open Access Journals (Sweden)

    M. Kumngern

    2011-04-01

    Full Text Available This paper presents a new simple configuration to realize the voltage-controlled floating resistor, which is suitable for integrated circuit implementation. The proposed resistor is composed of three main components: MOS transistor operating in the non-saturation region, DDCC, and MOS voltage divider. The MOS transistor operating in the non-saturation region is used to configure a floating linear resistor. The DDCC and the MOS transistor voltage divider are used for canceling the nonlinear component term of MOS transistor in the non-saturation region to obtain a linear current/voltage relationship. The DDCC is employed to provide a simple summer of the circuit. This circuit offers an ease for realizing the voltage divider circuit and the temperature effect that includes in term of threshold voltage can be compensated. The proposed configuration employs only 16 MOS transistors. The performances of the proposed circuit are simulated with PSPICE to confirm the presented theory.

  11. Spectrum analysis of a voltage source converter due to semiconductor voltage drops

    DEFF Research Database (Denmark)

    Rasmussen, Tonny Wederberg; Eltouki, Mustafa

    2017-01-01

    It is known that power electronic voltage source converters are non-ideal. This paper presents a state-of-the-art review on the effect of semiconductor voltage drop on the output voltage spectrum, using single-phase H-bridge two-level converter topology with natural sampled pulse width modulation....... The paper describes the analysis of output voltage spectrum, when the semiconductor voltage drop is added. The results of the analysis of the spectral contribution including and excluding semiconductor voltage drop reveal a good agreement between the theoretical results, simulations and laboratory...

  12. Distributed Monitoring of Voltage Collapse Sensitivity Indices

    OpenAIRE

    Simpson-Porco, John W.; Bullo, Francesco

    2016-01-01

    The assessment of voltage stability margins is a promising direction for wide-area monitoring systems. Accurate monitoring architectures for long-term voltage instability are typically centralized and lack scalability, while completely decentralized approaches relying on local measurements tend towards inaccuracy. Here we present distributed linear algorithms for the online computation of voltage collapse sensitivity indices. The computations are collectively performed by processors embedded ...

  13. High voltage investigations for ITER coils

    International Nuclear Information System (INIS)

    Fink, S.; Fietz, W.H.

    2006-01-01

    The superconducting ITER magnets will be excited with high voltage during operation and fast discharge. Because the coils are complex systems the internal voltage distribution can differ to a large extent from the ideal linear voltage distribution. In case of fast excitations internal voltages between conductor and radial plate of a TF coil can be even higher than the terminal voltage of 3.5 kV to ground which appears during a fast discharge without a fault. Hence the determination of the transient voltage distribution is important for a proper insulation co-ordination and will provide a necessary basis for the verification of the individual insulation design and the choice of test voltages and waveforms. Especially the extent of internal overvoltages in case of failures, e. g. malfunction of discharge units and / or arcing is of special interest. Transient calculations for the ITER TF coil system have been performed for fast discharge and fault scenarios to define test voltages for ITER TF. The conductor and radial plate insulation of the ITER TF Model Coil were exposed at room temperature to test voltages derived from the results from these calculations. Breakdown appeared during the highest AC voltage step. A fault scenario for the TF fast discharge system is presented where one fault triggers a second fault, leading to considerable voltage stress. In addition a FEM model of Poloidal Field Coil 3 for the determination of the parameters of a detailed network model is presented in order to prepare detailed investigations of the transient voltage behaviour of the PF coils. (author)

  14. Maximum permissible voltage of YBCO coated conductors

    Energy Technology Data Exchange (ETDEWEB)

    Wen, J.; Lin, B.; Sheng, J.; Xu, J.; Jin, Z. [Department of Electrical Engineering, Shanghai Jiao Tong University, Shanghai (China); Hong, Z., E-mail: zhiyong.hong@sjtu.edu.cn [Department of Electrical Engineering, Shanghai Jiao Tong University, Shanghai (China); Wang, D.; Zhou, H.; Shen, X.; Shen, C. [Qingpu Power Supply Company, State Grid Shanghai Municipal Electric Power Company, Shanghai (China)

    2014-06-15

    Highlights: • We examine three kinds of tapes’ maximum permissible voltage. • We examine the relationship between quenching duration and maximum permissible voltage. • Continuous I{sub c} degradations under repetitive quenching where tapes reaching maximum permissible voltage. • The relationship between maximum permissible voltage and resistance, temperature. - Abstract: Superconducting fault current limiter (SFCL) could reduce short circuit currents in electrical power system. One of the most important thing in developing SFCL is to find out the maximum permissible voltage of each limiting element. The maximum permissible voltage is defined as the maximum voltage per unit length at which the YBCO coated conductors (CC) do not suffer from critical current (I{sub c}) degradation or burnout. In this research, the time of quenching process is changed and voltage is raised until the I{sub c} degradation or burnout happens. YBCO coated conductors test in the experiment are from American superconductor (AMSC) and Shanghai Jiao Tong University (SJTU). Along with the quenching duration increasing, the maximum permissible voltage of CC decreases. When quenching duration is 100 ms, the maximum permissible of SJTU CC, 12 mm AMSC CC and 4 mm AMSC CC are 0.72 V/cm, 0.52 V/cm and 1.2 V/cm respectively. Based on the results of samples, the whole length of CCs used in the design of a SFCL can be determined.

  15. Microprocessor-controlled, programmable ramp voltage generator

    International Nuclear Information System (INIS)

    Hopwood, J.

    1978-11-01

    A special-purpose voltage generator has been developed for driving the quadrupole mass filter of a residual gas analyzer. The generator is microprocessor-controlled with desired ramping parameters programmed by setting front-panel digital thumb switches. The start voltage, stop voltage, and time of each excursion are selectable. A maximum of five start-stop levels may be pre-selected for each program. The ramp voltage is 0 to 10 volts with sweep times from 0.1 to 999.99 seconds

  16. Low-Voltage Switched-Capacitor Circuits

    DEFF Research Database (Denmark)

    Bidari, E.; Keskin, M.; Maloberti, F.

    1999-01-01

    Switched-capacitor stages are described which can function with very low (typically 1 V) supply voltages, without using voltage boosting or switched op-amps. Simulations indicate that high performance may be achieved using these circuits in filter or data converter applications.......Switched-capacitor stages are described which can function with very low (typically 1 V) supply voltages, without using voltage boosting or switched op-amps. Simulations indicate that high performance may be achieved using these circuits in filter or data converter applications....

  17. Voltage-dependent gating in a "voltage sensor-less" ion channel.

    Directory of Open Access Journals (Sweden)

    Harley T Kurata

    2010-02-01

    Full Text Available The voltage sensitivity of voltage-gated cation channels is primarily attributed to conformational changes of a four transmembrane segment voltage-sensing domain, conserved across many levels of biological complexity. We have identified a remarkable point mutation that confers significant voltage dependence to Kir6.2, a ligand-gated channel that lacks any canonical voltage-sensing domain. Similar to voltage-dependent Kv channels, the Kir6.2[L157E] mutant exhibits time-dependent activation upon membrane depolarization, resulting in an outwardly rectifying current-voltage relationship. This voltage dependence is convergent with the intrinsic ligand-dependent gating mechanisms of Kir6.2, since increasing the membrane PIP2 content saturates Po and eliminates voltage dependence, whereas voltage activation is more dramatic when channel Po is reduced by application of ATP or poly-lysine. These experiments thus demonstrate an inherent voltage dependence of gating in a "ligand-gated" K+ channel, and thereby provide a new view of voltage-dependent gating mechanisms in ion channels. Most interestingly, the voltage- and ligand-dependent gating of Kir6.2[L157E] is highly sensitive to intracellular [K+], indicating an interaction between ion permeation and gating. While these two key features of channel function are classically dealt with separately, the results provide a framework for understanding their interaction, which is likely to be a general, if latent, feature of the superfamily of cation channels.

  18. Excitation of voltage oscillations in an induction voltage adder

    Directory of Open Access Journals (Sweden)

    Nichelle Bruner

    2009-07-01

    Full Text Available The induction voltage adder is an accelerator architecture used in recent designs of pulsed-power driven x-ray radiographic systems such as Sandia National Laboratories’ Radiographic Integrated Test Stand (RITS, the Atomic Weapons Establishment’s planned Hydrus Facility, and the Naval Research Laboratory’s Mercury. Each of these designs relies on magnetic insulation to prevent electron loss across the anode-cathode gap in the vicinity of the adder as well as in the coaxial transmission line. Particle-in-cell simulations of the RITS adder and transmission line show that, as magnetic insulation is being established during a pulse, some electron loss occurs across the gap. Sufficient delay in the cavity pulse timings provides an opportunity for high-momentum electrons to deeply penetrate the cavities of the adder cells where they can excite radio-frequency resonances. These oscillations may be amplified in subsequent gaps, resulting in oscillations in the output power. The specific modes supported by the RITS-6 accelerator and details of the mechanism by which they are excited are presented in this paper.

  19. Mapping of Residues Forming the Voltage Sensor of the Voltage-Dependent Anion-Selective Channel

    Science.gov (United States)

    Thomas, Lorie; Blachly-Dyson, Elizabeth; Colombini, Marco; Forte, Michael

    1993-06-01

    Voltage-gated ion-channel proteins contain "voltage-sensing" domains that drive the conformational transitions between open and closed states in response to changes in transmembrane voltage. We have used site-directed mutagenesis to identify residues affecting the voltage sensitivity of a mitochondrial channel, the voltage-dependent anion-selective channel (VDAC). Although charge changes at many sites had no effect, at other sites substitutions that increased positive charge also increased the steepness of voltage dependance and substitutions that decreased positive charge decreased voltage dependance by an appropriate amount. In contrast to the plasma membrane K^+ and Na^+ channels, these residues are distributed over large parts of the VDAC protein. These results have been used to define the conformational transitions that accompany voltage gating of an ion channel. This gating mechanism requires the movement of large portions of the VDAC protein through the membrane.

  20. N*(1535) electroproduction at high Q2

    Energy Technology Data Exchange (ETDEWEB)

    G. Ramalho, M.T. Pena, K. Tsushima

    2012-04-01

    A covariant spectator quark model is applied to study the {gamma}N {yields} N*(1535) reaction in the large Q{sup 2} region. Starting from the relation between the nucleon and N*(1535) systems, the N*(1535) valence quark wave function is determined without the addition of any parameters. The model is then used to calculate the {gamma}N {yields} N*(1535) transition form factors. A very interesting, useful relation between the A{sub 1/2} and S{sub 1/2} helicity amplitudes for Q{sup 2} > GeV{sup 2}, is also derived.

  1. High-Q plasmonic bottle microresonator

    Science.gov (United States)

    Mohd Nasir, M. Narizee; Ding, Ming; Murugan, G. Senthil; Zervas, Michalis N.

    2014-03-01

    In this paper, we demonstrate a hybrid plasmonic bottle microresonator (PBMR) which supports whispering gallery modes (WGMs) along with surface plasmon waves (SPWs) for high performance optical sensor applications. The BMR was fabricated through "soften-and-compress" technique with a thin gold layer deposited on top of the resonator. A polarization-resolved measurement was set-up in order to fully characterize the fabricated PBMR. Initially, the uncoated BMR with waist diameter of 181 μm, stem diameter of 125 μm and length of 400 μm was fabricated and then gold film was deposited on the surface. Due to surface curvature, the gold film covering half of the BMR had a characteristic meniscus shape and maximum thickness of 30 nm. The meniscus provides appropriately tapered edges which facilitate the adiabatic transformation of BMR WGMs to SPWs and vice versa. This results in low transition losses, which combined with partially-metal-coated resonator, can result in high hybrid-PBMR Q's. The transmission spectra of the hybrid PBMR are dramatically different to the original uncoated BMR. Under TE(TM) excitation, the PBMR showed composite resonances with Q of ~2100(850) and almost identical ~ 3 nm FSR. We have accurately fitted the observed transmission resonances with Lorentzian-shaped curves and showed that the TE and TM excitations are actually composite resonances comprise of two and three partially overlapping resonances with Q's in excess of 2900 and 2500, respectively. To the best of our knowledge these are the highest Qs observed in plasmonic microcavities.

  2. Voltage stability in low voltage microgrids in aspects of active and reactive power demand

    Directory of Open Access Journals (Sweden)

    Parol Mirosław

    2016-03-01

    Full Text Available Low voltage microgrids are autonomous subsystems, in which generation, storage and power and electrical energy consumption appear. In the paper the main attention has been paid to the voltage stability issue in low voltage microgrid for different variants of its operation. In the introduction a notion of microgrid has been presented, and also the issue of influence of active and reactive power balance on node voltage level has been described. Then description of voltage stability issue has been presented. The conditions of voltage stability and indicators used to determine voltage stability margin in the microgrid have been described. Description of the low voltage test microgrid, as well as research methodology along with definition of considered variants of its operation have been presented further. The results of exemplary calculations carried out for the daily changes in node load of the active and reactive power, i.e. the voltage and the voltage stability margin indexes in nodes have been presented. Furthermore, the changes of voltage stability margin indexes depending on the variant of the microgrid operation have been presented. Summary and formulation of conclusions related to the issue of voltage stability in microgrids have been included at the end of the paper.

  3. Influence of current limitation on voltage stability with voltage sourced converter HVDC

    DEFF Research Database (Denmark)

    Zeni, Lorenzo; Jóhannsson, Hjörtur; Hansen, Anca Daniela

    2013-01-01

    A first study of voltage stability with relevant amount of Voltage Sourced Converter based High Voltage Direct Current (VSC-HVDC) transmission is presented, with particular focus on the converters’ behaviour when reaching their rated current. The detrimental effect of entering the current...

  4. Voltage-Sensitive Load Controllers for Voltage Regulation and Increased Load Factor in Distribution Systems

    DEFF Research Database (Denmark)

    Douglass, Philip James; Garcia-Valle, Rodrigo; Østergaard, Jacob

    2014-01-01

    This paper presents a novel controller design for controlling appliances based on local measurements of voltage. The controller finds the normalized voltage deviation accounting for the sensitivity of voltage measurements to appliance state. The controller produces a signal indicating desired pow...

  5. On-site voltage measurement with capacitive sensors on high voltage systems

    NARCIS (Netherlands)

    Wu, L.; Wouters, P.A.A.F.; Heesch, van E.J.M.; Steennis, E.F.

    2011-01-01

    In Extra/High-Voltage (EHV/HV) power systems, over-voltages occur e.g. due to transients or resonances. At places where no conventional voltage measurement devices can be installed, on-site measurement of these occurrences requires preferably non intrusive sensors, which can be installed with little

  6. 76 FR 72203 - Voltage Coordination on High Voltage Grids; Notice of Reliability Workshop Agenda

    Science.gov (United States)

    2011-11-22

    ... DEPARTMENT OF ENERGY Federal Energy Regulatory Commission [Docket No. AD12-5-000] Voltage Coordination on High Voltage Grids; Notice of Reliability Workshop Agenda As announced in the Notice of Staff..., from 9 a.m. to 4:30 p.m. to explore the interaction between voltage control, reliability, and economic...

  7. Modeling and Simulation of Low Voltage Arcs

    NARCIS (Netherlands)

    Ghezzi, L.; Balestrero, A.

    2010-01-01

    Modeling and Simulation of Low Voltage Arcs is an attempt to improve the physical understanding, mathematical modeling and numerical simulation of the electric arcs that are found during current interruptions in low voltage circuit breakers. An empirical description is gained by refined electrical

  8. Reduced Voltage Scaling in Clock Distribution Networks

    Directory of Open Access Journals (Sweden)

    Khader Mohammad

    2009-01-01

    Full Text Available We propose a novel circuit technique to generate a reduced voltage swing (RVS signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV devices and the programmability of the low voltage value.

  9. The LMF triaxial MITL voltage adder system

    International Nuclear Information System (INIS)

    Mazarakis, M.G.; Smith, D.L.; Bennett, L.F.; Lockner, T.R.; Olson, R.E.; Poukey, J.W.

    1992-01-01

    The light-ion microfusion driver design consists of multiple accelerating modules fired in coincidence and sequentially in order to provide the desired ion energy, power pulse shape and energy deposition uniformity on an Inertial Confinement Fusion (ICF) target. The basic energy source is a number of Marx generators which, through the appropriate pulse power conditioning, provide the necessary voltage pulse wave form to the accelerating gaps or feeds of each module. The cavity gaps are inductively isolated, and the voltage addition occurs in the center conductor of the voltage adder which is the positive electrode while the electrons of the sheath flow closer to the outer cylinder which is the magnetically insulated cathode electrode. Each module powers a separate two-stage extraction diode which provides a low divergence ion beam. In order to provide the two separate voltage pulses required by the diode, a triaxial adder system is designed for each module. The voltage addition occurs in two separate MITLs. The center hollow cylinder (anode) of the second MITL also serves as the outer cathode electrode for the extension of the first voltage adder MITL. The voltage of the second stage is about twice that of the first stage. The cavities are connected in series to form the outer cylinder of each module. The accelerating modules are positioned radially in a symmetrical way around the fusion chamber. A preliminary conceptual design of the LMF modules with emphasis on the voltage adders and extension MITLs will be presented and discussed

  10. Time isolation high-voltage impulse generator

    International Nuclear Information System (INIS)

    Chodorow, A.M.

    1975-01-01

    Lewis' high-voltage impulse generator is analyzed in greater detail, demonstrating that voltage between adjacent nodes can be equalized by proper selection of parasitic impedances. This permits improved TEM mode propagation to a matched load, with more faithful source waveform preservation

  11. High-voltage engineering and testing

    CERN Document Server

    Ryan, Hugh M

    2013-01-01

    This 3rd edition of High Voltage Engineering Testing describes strategic developments in the field and reflects on how they can best be managed. All the key components of high voltage and distribution systems are covered including electric power networks, UHV and HV. Distribution systems including HVDC and power electronic systems are also considered.

  12. Improving transition voltage spectroscopy of molecular junctions

    DEFF Research Database (Denmark)

    Markussen, Troels; Chen, Jingzhe; Thygesen, Kristian Sommer

    2011-01-01

    Transition voltage spectroscopy (TVS) is a promising spectroscopic tool for molecular junctions. The principles in TVS is to find the minimum on a Fowler-Nordheim plot where ln(I/V2) is plotted against 1/V and relate the voltage at the minimum Vmin to the closest molecular level. Importantly, Vmin...

  13. Reducing Ripple In A Switching Voltage Regulator

    Science.gov (United States)

    Paulkovich, John; Rodriguez, G. Ernest

    1994-01-01

    Ripple voltage in output of switching voltage regulator reduced substantially by simple additional circuitry adding little to overall weight and size of regulator. Heretofore, additional filtering circuitry needed to obtain comparable reductions in ripple typically as large and heavy as original regulator. Current opposing ripple current injected into filter capacitor.

  14. Wide-range voltage modulation

    International Nuclear Information System (INIS)

    Rust, K.R.; Wilson, J.M.

    1992-06-01

    The Superconducting Super Collider's Medium Energy Booster Abort (MEBA) kicker modulator will supply a current pulse to the abort magnets which deflect the proton beam from the MEB ring into a designated beam stop. The abort kicker will be used extensively during testing of the Low Energy Booster (LEB) and the MEB rings. When the Collider is in full operation, the MEBA kicker modulator will abort the MEB beam in the event of a malfunction during the filling process. The modulator must generate a 14-μs wide pulse with a rise time of less than 1 μs, including the delay and jitter times. It must also be able to deliver a current pulse to the magnet proportional to the beam energy at any time during ramp-up of the accelerator. Tracking the beam energy, which increases from 12 GeV at injection to 200 GeV at extraction, requires the modulator to operate over a wide range of voltages (4 kV to 80 kV). A vacuum spark gap and a thyratron have been chosen for test and evaluation as candidate switches for the abort modulator. Modulator design, switching time delay, jitter and pre-fire data are presented

  15. Practical considerations in voltage stability assessment

    Energy Technology Data Exchange (ETDEWEB)

    Kundur, P; Gao, B [Powertech Labs. Inc., Surrey, BC (Canada)

    1994-12-31

    This paper deals with some of the most important practical issues related to voltage stability assessment of large practical systems. A brief discussion of the practical aspects of voltage stability problem and prevention of voltage instability is given first, followed by descriptions of different analytical techniques and tools for voltage stability analysis. Presentations of analytical tools is focused on the VSTAB program which incorporates the modal analysis, continuation power flow, and shortest distance to instability techniques, Finally, an example case study of a practical large system is presented. The case study illustrates how modal analysis is used to determine the most effective load shedding scheme for preventing voltage instability. (author) 15 refs., 2 figs., 2 tabs.

  16. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  17. Voltage-gated lipid ion channels

    DEFF Research Database (Denmark)

    Blicher, Andreas; Heimburg, Thomas Rainer

    2013-01-01

    Synthetic lipid membranes can display channel-like ion conduction events even in the absence of proteins. We show here that these events are voltage-gated with a quadratic voltage dependence as expected from electrostatic theory of capacitors. To this end, we recorded channel traces and current...... histograms in patch-experiments on lipid membranes. We derived a theoretical current-voltage relationship for pores in lipid membranes that describes the experimental data very well when assuming an asymmetric membrane. We determined the equilibrium constant between closed and open state and the open...... probability as a function of voltage. The voltage-dependence of the lipid pores is found comparable to that of protein channels. Lifetime distributions of open and closed events indicate that the channel open distribution does not follow exponential statistics but rather power law behavior for long open times...

  18. Non-contact current and voltage sensor

    Science.gov (United States)

    Carpenter, Gary D; El-Essawy, Wael; Ferreira, Alexandre Peixoto; Keller, Thomas Walter; Rubio, Juan C; Schappert, Michael A

    2014-03-25

    A detachable current and voltage sensor provides an isolated and convenient device to measure current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a housing that contains the current and voltage sensors, which may be a ferrite cylinder with a hall effect sensor disposed in a gap along the circumference to measure current, or alternative a winding provided through the cylinder along its axis and a capacitive plate or wire disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage.

  19. Coordinated Voltage Control of Active Distribution Network

    Directory of Open Access Journals (Sweden)

    Xie Jiang

    2016-01-01

    Full Text Available This paper presents a centralized coordinated voltage control method for active distribution network to solve off-limit problem of voltage after incorporation of distributed generation (DG. The proposed method consists of two parts, it coordinated primal-dual interior point method-based voltage regulation schemes of DG reactive powers and capacitors with centralized on-load tap changer (OLTC controlling method which utilizes system’s maximum and minimum voltages, to improve the qualified rate of voltage and reduce the operation numbers of OLTC. The proposed coordination has considered the cost of capacitors. The method is tested using a radial edited IEEE-33 nodes distribution network which is modelled using MATLAB.

  20. Determined Initial lead for South Of Isua (SOI) terrain suggests a single homogeneous source for it and possibly other archaean rocks

    Science.gov (United States)

    Tera, F.

    2011-12-01

    A Thorogenic-Uranogenic Lead Isotope Plane (TULIP), which entails plotting 206/208 (or its reverse) vs 207/208 (or its reverse), was applied to the Pb data on South of Isua (SOI) by Kamber et al., (1). When the data on 20 samples of these rocks and feldspars are plotted in pairs (each pair is a rock and its feldspar) on TULIP, they fall on 10 mixing lines that converge on a single spot (Fig. 1). This is the end member initial lead (EMIL). The 206/208 & 207/208 so determined are 0.3675 and 0.43525, respectively. From these values one calculates 207/206 = 1.1843 ± 0.0007, for EMIL. This pattern requires either: A) each pair has a singular kappa, K = 232Th/238U, different from others, or B) a pair's in situ decay Pb was homogenized in recent times. On 204/206 vs 207/206 diagram, the whole rocks of SOI define a 3.776 Ga isochron (2). From this and EMIL's 207/206, one obtains: 206/204 = 10.977, 207/204 = 12.974; and 208/204 = 29.756. This singularity of initial Pb contrasts with a deduced variability by the original authors (1). EMIL's radiogenic *(207/206) = 1.6220, gives a single-stage age = 5.9 Ga, indicating inapplicability of its evolution in one stage. Also, the μ calculated from 238U-206Pb for the single stage is different from that inferred from 235U-207Pb, confirming disqualification of this scenario. Reconciliation of the two decay schemes necessitates assumption of EMIL evolution in a minimum of two stages. Starting at 4.563 Ga, five scenarios were assumed: First stage ends and second starts at 4.55, 4.54, 4.53, 4.52 or 4.51 Ga. Second stages end at 3.776 Ga. The calculated μ1 for the first stage are 106, 59.5, 44.6, 36.3 and 30.9 respectively. For μ2 the change is limited, from 5.45 to 5.28. Only an average calculated K for both stages is possible. For the five outlined scenarios it ranges from 1.118 to 1.111. Earlier, Tera (3) observed that initial Pb of the oldest terrestrial reservoir requires evolution in two stages. There too μ1 >> μ2. Data on

  1. Reliability of supply of switchgear for auxiliary low voltage in substations extra high voltage to high voltage

    Directory of Open Access Journals (Sweden)

    Perić Dragoslav M.

    2015-01-01

    Full Text Available Switchgear for auxiliary low voltage in substations (SS of extra high voltages (EHV to high voltage (HV - SS EHV/HV kV/kV is of special interest for the functioning of these important SS, as it provides a supply for system of protection and other vital functions of SS. The article addresses several characteristic examples involving MV lines with varying degrees of independence of their supply, and the possible application of direct transformation EHV/LV through special voltage transformers. Auxiliary sources such as inverters and diesel generators, which have limited power and expensive energy, are also used for the supply of switchgear for auxiliary low voltage. Corresponding reliability indices are calculated for all examples including mean expected annual engagement of diesel generators. The applicability of certain solutions of switchgear for auxiliary low voltage SS EHV/HV, taking into account their reliability, feasibility and cost-effectiveness is analyzed too. In particular, the analysis of applications of direct transformation EHV/LV for supply of switchgear for auxiliary low voltage, for both new and existing SS EHV/HV.

  2. A Novel Index for Online Voltage Stability Assessment Based on Correlation Characteristic of Voltage Profiles

    Directory of Open Access Journals (Sweden)

    M. R. Aghamohammadi

    2011-06-01

    Full Text Available Abstract: Voltage instability is a major threat for security of power systems. Preserving voltage security margin at a certain limit is a vital requirement for today’s power systems. Assessment of voltage security margin is a challenging task demanding sophisticated indices. In this paper, for the purpose of on line voltage security assessment a new index based on the correlation characteristic of network voltage profile is proposed. Voltage profile comprising all bus voltages contains the effect of network structure, load-generation patterns and reactive power compensation on the system behaviour and voltage security margin. Therefore, the proposed index is capable to clearly reveal the effect of system characteristics and events on the voltage security margin. The most attractive feature for this index is its fast and easy calculation from synchronously measured voltage profile without any need to system modelling and simulation and without any dependency on network size. At any instant of system operation by merely measuring network voltage profile and no further simulation calculation this index could be evaluated with respect to a specific reference profile. The results show that the behaviour of this index with respect to the change in system security is independent of the selected reference profile. The simplicity and easy calculation make this index very suitable for on line application. The proposed approach has been demonstrated on IEEE 39 bus test system with promising results showing its effectiveness and applicability.

  3. Novel Voltage limiting concept for avalance breakdown protection

    NARCIS (Netherlands)

    Ruijs, L.C.H.; Bezooijen, van A.; Mahmoudi, R.; Roermund, van A.H.M.

    2006-01-01

    Destructive over-voltage breakdown of cellular phone power transistors is prevented by using a new voltage-limiting concept. The output voltage is detected by an avalanche-based detector, and limited by decreasing the output power when needed. The voltage detector contains a low voltage bipolar NPN

  4. On-chip grating coupler array on the SOI platform for fan-in/fan-out of MCFs with low insertion loss and crosstalk

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ye, Feihong; Peucheret, Christophe

    2015-01-01

    We report the design and fabrication of a compact multi-core fiber fan-in/fan-out using a grating coupler array on the SOI platform. The grating couplers are fully-etched, enabling the whole circuit to be fabricated in a single lithography and etching step. Thanks to the apodized design...... for the grating couplers and the introduction of an aluminum reflective mirror, a highest coupling efficiency of -3.8 dB with 3 dB coupling bandwidth of 48 nm and 1.5 dB bandwidth covering the whole C band, together with crosstalk lower than -32 dB are demonstrated. (C)2015 Optical Society of America...

  5. Fuel Cell/Electrochemical Cell Voltage Monitor

    Science.gov (United States)

    Vasquez, Arturo

    2012-01-01

    A concept has been developed for a new fuel cell individual-cell-voltage monitor that can be directly connected to a multi-cell fuel cell stack for direct substack power provisioning. It can also provide voltage isolation for applications in high-voltage fuel cell stacks. The technology consists of basic modules, each with an 8- to 16-cell input electrical measurement connection port. For each basic module, a power input connection would be provided for direct connection to a sub-stack of fuel cells in series within the larger stack. This power connection would allow for module power to be available in the range of 9-15 volts DC. The relatively low voltage differences that the module would encounter from the input electrical measurement connection port, coupled with the fact that the module's operating power is supplied by the same substack voltage input (and so will be at similar voltage), provides for elimination of high-commonmode voltage issues within each module. Within each module, there would be options for analog-to-digital conversion and data transfer schemes. Each module would also include a data-output/communication port. Each of these ports would be required to be either non-electrical (e.g., optically isolated) or electrically isolated. This is necessary to account for the fact that the plurality of modules attached to the stack will normally be at a range of voltages approaching the full range of the fuel cell stack operating voltages. A communications/ data bus could interface with the several basic modules. Options have been identified for command inputs from the spacecraft vehicle controller, and for output-status/data feeds to the vehicle.

  6. PROCEEDINGS OF RIKEN BNL RESEARCH CENTER WORKSHOP ON RHIC SPIN PHYSICS III AND IV, POLARIZED PARTONS AT HIGH Q2 REGION, AUGUST 3, 2000 AT BNL, OCTOBER 14, 2000 AT KYOTO UNIVERSITY.

    Energy Technology Data Exchange (ETDEWEB)

    BUNCE, G.; VIGDOR, S.

    2001-03-15

    International workshop on II Polarized Partons at High Q2 region 11 was held at the Yukawa Institute for Theoretical Physics, Kyoto University, Kyoto, Japan on October 13-14, 2000, as a satellite of the international conference ''SPIN 2000'' (Osaka, Japan, October 16-21,2000). This workshop was supported by RIKEN (The Institute of Physical and Chemical Research) and by Yukawa Institute. The scientific program was focused on the upcoming polarized collider RHIC. The workshop was also an annual meeting of RHIC Spin Collaboration (RSC). The number of participants was 55, including 28 foreign visitors and 8 foreign-resident Japanese participants, reflecting the international nature of the RHIC spin program. At the workshop there were 25 oral presentations in four sessions, (1) RHIC Spin Commissioning, (2) Polarized Partons, Present and Future, (3) New Ideas on Polarization Phenomena, (4) Strategy for the Coming Spin Running. In (1) the successful polarized proton commissioning and the readiness of the accelerator for the physics program impressed us. In (2) and (3) active discussions were made on the new structure function to be firstly measured at RHIC, and several new theoretical ideas were presented. In session (4) we have established a plan for the beam time requirement toward the first collision of polarized protons. These proceedings include the transparencies presented at the workshop. The discussion on ''Strategy for the Coming Spin Running'' was summarized by the chairman of the session, S. Vigdor and G. Bunce.

  7. High voltage electricity installations a planning perspective

    CERN Document Server

    Jay, Stephen Andrew

    2006-01-01

    The presence of high voltage power lines has provoked widespread concern for many years. High Voltage Electricity Installations presents an in-depth study of policy surrounding the planning of high voltage installations, discussing the manner in which they are percieved by the public, and the associated environmental issues. An analysis of these concerns, along with the geographical, environmental and political influences that shape their expression, is presented. Investigates local planning policy in an area of the energy sector that is of highly topical environmental and public concern Cover

  8. Investigation of voltage swell mitigation using STATCOM

    International Nuclear Information System (INIS)

    Razak, N A Abdul; Jaafar, S; Hussain, I S

    2013-01-01

    STATCOM is one of the best applications of a self commutated FACTS device to control power quality problems in the distribution system. This project proposed a STATCOM model with voltage control mechanism. DQ transformation was implemented in the controller system to achieve better estimation. Then, the model was used to investigate and analyse voltage swell problem in distribution system. The simulation results show that voltage swell could contaminate distribution network with unwanted harmonic frequencies. Negative sequence frequencies give harmful effects to the network. System connected with proposed STATCOM model illustrates that it could mitigate this problems efficiently.

  9. Analysis of NSTX TF Joint Voltage Measurements

    International Nuclear Information System (INIS)

    Woolley R

    2005-01-01

    This report presents findings of analyses of recorded current and voltage data associated with 72 electrical joints operating at high current and high mechanical stress. The analysis goal was to characterize the mechanical behavior of each joint and thus evaluate its mechanical supports. The joints are part of the toroidal field (TF) magnet system of the National Spherical Torus Experiment (NSTX) pulsed plasma device operating at the Princeton Plasma Physics Laboratory (PPPL). Since there is not sufficient space near the joints for much traditional mechanical instrumentation, small voltage probes were installed on each joint and their voltage monitoring waveforms have been recorded on sampling digitizers during each NSTX ''shot''

  10. Design and Control of a Dynamic Voltage Restorer

    DEFF Research Database (Denmark)

    Nielsen, John Godsk

    voltage until the energy storage is completely drained or the voltages have returned to normal voltage levels. The control of the HV-DVR is a combined feedforward and feedback control to have a fast response time and load independent voltages. The control is implemented in a rotating dq-reference frame...... electric consumers against voltage dips and surges in the medium and low voltage distribution grid. The thesis first gives an introduction to relevant power quality issues for a DVR and power electronic controllers for voltage dip mitigation. Thereafter the operation and the elements in a DVR are described...... of symmetrical and non-symmetrical voltage dips. In most cases the DVR is capable of restoring the load voltages within 2 ms. During the transition phases load voltage oscillations can be generated and during the return of the supply voltages short time over-voltages can be generated by the DVR. Both...

  11. Fiber-optic voltage measuring system

    Science.gov (United States)

    Ye, Miaoyuan; Nie, De-Xin; Li, Yan; Peng, Yu; Lin, Qi-Qing; Wang, Jing-Gang

    1993-09-01

    A new fibre optic voltage measuring system has been developed based on the electrooptic effect of bismuth germanium oxide (Bi4Ge3O12)crystal. It uses the LED as the light source. The light beam emitted from the light source is transmitted to the sensor through the optic fibre and the intensity of the output beam is changed by the applied voltage. This optic signal is transmitted to the PIN detector and converted to an electric signal which is processed by the electronic circuit and 8098 single chip microcomputer the output voltage signal obtained is directly proportional to the applied voltage. This paper describes the principle the configuration and the performance parameters of the system. Test results are evaluated and discussed.

  12. Constant potential high-voltage generator

    International Nuclear Information System (INIS)

    Resnick, T.A.; Dupuis, W.A.; Palermo, T.

    1980-01-01

    An X-ray tube voltage generator with automatic stabilization circuitry is disclosed. The generator includes a source of pulsating direct current voltage such as from a rectified 3 phase transformer. This pulsating voltage is supplied to the cathode and anode of an X-ray tube and forms an accelerating potential for electrons within that tube. The accelerating potential is stabilized with a feedback signal which is provided by a feedback network. The network includes an error signal generator which compares an instantaneous accelerating potential with a preferred reference accelerating potential and generates an error function. This error function is transmitted to a control tube grid which in turn causes the voltage difference between X-ray tube cathode and anode to stabilize and thereby reduce the error function. In this way stabilized accelerating potentials are realized and uniform X-ray energy distributions produced. (Auth.)

  13. Nested high voltage generator/particle accelerator

    International Nuclear Information System (INIS)

    Adler, R.J.

    1992-01-01

    This patent describes a modular high voltage particle accelerator having an emission axis and an emission end, the accelerator. It comprises: a plurality of high voltage generators in nested adjacency to form a nested stack, each the generator comprising a cup-like housing having a base and a tubular sleeve extending from the base, a primary transformer winding encircling the nested stack; a secondary transformer winding between each adjacent pair of housings, magnetically linked to the primary transformer winding through the gaps; a power supply respective to each of the secondary windings converting alternating voltage from its respective secondary winding to d.c. voltage, the housings at the emission end forming a hollow throat for particle acceleration, a vacuum seal at the emission end of the throat which enables the throat to be evacuated; a particle source in the thrond power means to energize the primary transformer winding

  14. Low voltage arc formation in railguns

    Science.gov (United States)

    Hawke, R.S.

    1985-08-05

    A low voltage plasma arc is first established across the rails behind the projectile by switching a low voltage high current source across the rails to establish a plasma arc by vaporizing a fuse mounted on the back of the projectile, maintaining the voltage across the rails below the railgun breakdown voltage to prevent arc formation ahead of the projectile. After the plasma arc has been formed behind the projectile a discriminator switches the full energy bank across the rails to accelerate the projectile. A gas gun injector may be utilized to inject a projectile into the breech of a railgun. The invention permits the use of a gas gun or gun powder injector and an evacuated barrel without the risk of spurious arc formation in front of the projectile.

  15. Voltage, Temperature, Frequency Margin Test Report

    DEFF Research Database (Denmark)

    Denver, Troelz

    1999-01-01

    The purpose of the tests is to establish the camera functionality when it is exposed to an extreme environment for prolonged periods, thus simulating the end of life performance. This environment covers temperature, input clock frequency and supply voltage variation......The purpose of the tests is to establish the camera functionality when it is exposed to an extreme environment for prolonged periods, thus simulating the end of life performance. This environment covers temperature, input clock frequency and supply voltage variation...

  16. Detecting Faults In High-Voltage Transformers

    Science.gov (United States)

    Blow, Raymond K.

    1988-01-01

    Simple fixture quickly shows whether high-voltage transformer has excessive voids in dielectric materials and whether high-voltage lead wires too close to transformer case. Fixture is "go/no-go" indicator; corona appears if transformer contains such faults. Nests in wire mesh supported by cap of clear epoxy. If transformer has defects, blue glow of corona appears in mesh and is seen through cap.

  17. Ultra-low Voltage CMOS Cascode Amplifier

    OpenAIRE

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

  18. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  19. Modular high voltage power supply for chemical analysis

    Science.gov (United States)

    Stamps, James F [Livermore, CA; Yee, Daniel D [Dublin, CA

    2008-07-15

    A high voltage power supply for use in a system such as a microfluidics system, uses a DC-DC converter in parallel with a voltage-controlled resistor. A feedback circuit provides a control signal for the DC-DC converter and voltage-controlled resistor so as to regulate the output voltage of the high voltage power supply, as well as, to sink or source current from the high voltage supply.

  20. Wind Power Plant Voltage Stability Evaluation: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Muljadi, E.; Zhang, Y. C.

    2014-09-01

    Voltage stability refers to the ability of a power system to maintain steady voltages at all buses in the system after being subjected to a disturbance from a given initial operating condition. Voltage stability depends on a power system's ability to maintain and/or restore equilibrium between load demand and supply. Instability that may result occurs in the form of a progressive fall or rise of voltages of some buses. Possible outcomes of voltage instability are the loss of load in an area or tripped transmission lines and other elements by their protective systems, which may lead to cascading outages. The loss of synchronism of some generators may result from these outages or from operating conditions that violate a synchronous generator's field current limit, or in the case of variable speed wind turbine generator, the current limits of power switches. This paper investigates the impact of wind power plants on power system voltage stability by using synchrophasor measurements.

  1. Experimental validation of prototype high voltage bushing

    Science.gov (United States)

    Shah, Sejal; Tyagi, H.; Sharma, D.; Parmar, D.; M. N., Vishnudev; Joshi, K.; Patel, K.; Yadav, A.; Patel, R.; Bandyopadhyay, M.; Rotti, C.; Chakraborty, A.

    2017-08-01

    Prototype High voltage bushing (PHVB) is a scaled down configuration of DNB High Voltage Bushing (HVB) of ITER. It is designed for operation at 50 kV DC to ensure operational performance and thereby confirming the design configuration of DNB HVB. Two concentric insulators viz. Ceramic and Fiber reinforced polymer (FRP) rings are used as double layered vacuum boundary for 50 kV isolation between grounded and high voltage flanges. Stress shields are designed for smooth electric field distribution. During ceramic to Kovar brazing, spilling cannot be controlled which may lead to high localized electrostatic stress. To understand spilling phenomenon and precise stress calculation, quantitative analysis was performed using Scanning Electron Microscopy (SEM) of brazed sample and similar configuration modeled while performing the Finite Element (FE) analysis. FE analysis of PHVB is performed to find out electrical stresses on different areas of PHVB and are maintained similar to DNB HV Bushing. With this configuration, the experiment is performed considering ITER like vacuum and electrical parameters. Initial HV test is performed by temporary vacuum sealing arrangements using gaskets/O-rings at both ends in order to achieve desired vacuum and keep the system maintainable. During validation test, 50 kV voltage withstand is performed for one hour. Voltage withstand test for 60 kV DC (20% higher rated voltage) have also been performed without any breakdown. Successful operation of PHVB confirms the design of DNB HV Bushing. In this paper, configuration of PHVB with experimental validation data is presented.

  2. VKCDB: Voltage-gated potassium channel database

    Directory of Open Access Journals (Sweden)

    Gallin Warren J

    2004-01-01

    Full Text Available Abstract Background The family of voltage-gated potassium channels comprises a functionally diverse group of membrane proteins. They help maintain and regulate the potassium ion-based component of the membrane potential and are thus central to many critical physiological processes. VKCDB (Voltage-gated potassium [K] Channel DataBase is a database of structural and functional data on these channels. It is designed as a resource for research on the molecular basis of voltage-gated potassium channel function. Description Voltage-gated potassium channel sequences were identified by using BLASTP to search GENBANK and SWISSPROT. Annotations for all voltage-gated potassium channels were selectively parsed and integrated into VKCDB. Electrophysiological and pharmacological data for the channels were collected from published journal articles. Transmembrane domain predictions by TMHMM and PHD are included for each VKCDB entry. Multiple sequence alignments of conserved domains of channels of the four Kv families and the KCNQ family are also included. Currently VKCDB contains 346 channel entries. It can be browsed and searched using a set of functionally relevant categories. Protein sequences can also be searched using a local BLAST engine. Conclusions VKCDB is a resource for comparative studies of voltage-gated potassium channels. The methods used to construct VKCDB are general; they can be used to create specialized databases for other protein families. VKCDB is accessible at http://vkcdb.biology.ualberta.ca.

  3. Prediction of breakdown voltages in novel gases for high voltage insulation

    Energy Technology Data Exchange (ETDEWEB)

    Koch, M.

    2015-07-01

    This thesis submitted to the Swiss Federal Institute of Technology ETH in Zurich examines the use of sulphur hexafluoride (SF{sub 6}) and similar gases as important insulation media for high voltage equipment. Due to its superior insulation properties, SF{sub 6} is widely used in gas-insulated switchgear. However, the gas also has a very high global warming potential and the content of SF{sub 6} in the atmosphere is constantly increasing. The search for new insulation gases using classical breakdown experiments is discussed. A model for SF{sub 6} based on the stepped leader model is described. This calculates the breakdown voltages in arbitrary electrode configurations and under standard voltage waveforms. Thus, the thesis provides a method for the prediction of breakdown voltages of arbitrary field configurations under standard voltage waveforms for gases with electron-attaching properties. With this, further gases can be characterized for usage as high voltage insulation media.

  4. Prediction of breakdown voltages in novel gases for high voltage insulation

    International Nuclear Information System (INIS)

    Koch, M.

    2015-01-01

    This thesis submitted to the Swiss Federal Institute of Technology ETH in Zurich examines the use of sulphur hexafluoride (SF_6) and similar gases as important insulation media for high voltage equipment. Due to its superior insulation properties, SF_6 is widely used in gas-insulated switchgear. However, the gas also has a very high global warming potential and the content of SF_6 in the atmosphere is constantly increasing. The search for new insulation gases using classical breakdown experiments is discussed. A model for SF_6 based on the stepped leader model is described. This calculates the breakdown voltages in arbitrary electrode configurations and under standard voltage waveforms. Thus, the thesis provides a method for the prediction of breakdown voltages of arbitrary field configurations under standard voltage waveforms for gases with electron-attaching properties. With this, further gases can be characterized for usage as high voltage insulation media

  5. Advanced Control of the Dynamic Voltage Restorer for Mitigating Voltage Sags in Power Systems

    Directory of Open Access Journals (Sweden)

    Dung Vo Tien

    2018-01-01

    Full Text Available The paper presents a vector control with two cascaded loops to improve the properties of Dynamic Voltage Restorer (DVR to minimize Voltage Sags on the grid. Thereby, a vector controlled structure was built on the rotating dq-coordinate system with the combination of voltage control and the current control. The proposed DVR control method is modelled using MATLAB-Simulink. It is tested using balanced/unbalanced voltage sags as well as fluctuant and distorted voltages. As a result, by using this controlling method, the dynamic characteristics of the system have been improved significantly. The system performed with higher accuracy, faster response and lower distortion in the voltage sags compensation. The paper presents real time experimental results to verify the performance of the proposed method in real environments.

  6. Multifunction Voltage-Mode Filter Using Single Voltage Differencing Differential Difference Amplifier

    Directory of Open Access Journals (Sweden)

    Chaichana Amornchai

    2017-01-01

    Full Text Available In this paper, a voltage mode multifunction filter based on single voltage differencing differential difference amplifier (VDDDA is presented. The proposed filter with three input voltages and single output voltage is constructed with single VDDDA, two capacitors and two resistors. Its quality factor can be adjusted without affecting natural frequency. Also, the natural frequency can be electronically tuned via adjusting of bias current. The filter can offer five output responses, high-pas (HP, band-pass (BP, band-reject (BR, low-pass (LP and all-ass (AP functions in the same circuit topology. The output response can be selected by choosing the suitable input voltage without the component matching condition and the requirement of additional double gain voltage amplifier. PSpice simulation results to confirm an operation of the proposed filter correspond to the theory.

  7. Engineering of a genetically encodable fluorescent voltage sensor exploiting fast Ci-VSP voltage-sensing movements.

    Science.gov (United States)

    Lundby, Alicia; Mutoh, Hiroki; Dimitrov, Dimitar; Akemann, Walther; Knöpfel, Thomas

    2008-06-25

    Ci-VSP contains a voltage-sensing domain (VSD) homologous to that of voltage-gated potassium channels. Using charge displacement ('gating' current) measurements we show that voltage-sensing movements of this VSD can occur within 1 ms in mammalian membranes. Our analysis lead to development of a genetically encodable fluorescent protein voltage sensor (VSFP) in which the fast, voltage-dependent conformational changes of the Ci-VSP voltage sensor are transduced to similarly fast fluorescence read-outs.

  8. Voltage scheduling for low power/energy

    Science.gov (United States)

    Manzak, Ali

    2001-07-01

    Power considerations have become an increasingly dominant factor in the design of both portable and desk-top systems. An effective way to reduce power consumption is to lower the supply voltage since voltage is quadratically related to power. This dissertation considers the problem of lowering the supply voltage at (i) the system level and at (ii) the behavioral level. At the system level, the voltage of the variable voltage processor is dynamically changed with the work load. Processors with limited sized buffers as well as those with very large buffers are considered. Given the task arrival times, deadline times, execution times, periods and switching activities, task scheduling algorithms that minimize energy or peak power are developed for the processors equipped with very large buffers. A relation between the operating voltages of the tasks for minimum energy/power is determined using the Lagrange multiplier method, and an iterative algorithm that utilizes this relation is developed. Experimental results show that the voltage assignment obtained by the proposed algorithm is very close (0.1% error) to that of the optimal energy assignment and the optimal peak power (1% error) assignment. Next, on-line and off-fine minimum energy task scheduling algorithms are developed for processors with limited sized buffers. These algorithms have polynomial time complexity and present optimal (off-line) and close-to-optimal (on-line) solutions. A procedure to calculate the minimum buffer size given information about the size of the task (maximum, minimum), execution time (best case, worst case) and deadlines is also presented. At the behavioral level, resources operating at multiple voltages are used to minimize power while maintaining the throughput. Such a scheme has the advantage of allowing modules on the critical paths to be assigned to the highest voltage levels (thus meeting the required timing constraints) while allowing modules on non-critical paths to be assigned

  9. Investigation of phase-wise voltage regulator control logics for compensating voltage deviations in an experimental low voltage network

    DEFF Research Database (Denmark)

    Hu, Junjie; Zecchino, Antonio; Marinelli, Mattia

    2016-01-01

    This paper investigates the control logics of an on-load tap-changer (OLTC) transformer by means of an experimental system validation. The experimental low-voltage unbalanced system consists of a decoupled single-phase OLTC transformer, a 75-metre 16 mm2 cable, a controllable single-phase resistive...... load and an electric vehicle, which has the vehicle-to-grid function. Three control logics of the OLTC transformer are described in the study. The three control logics are classified based on their control objectives and control inputs, which include network currents and voltages, and can be measured...... either locally or remotely. To evaluate and compare the control performances of the three control logics, all the tests use the same loading profiles. The experimental results indicate that the modified line compensation control can regulate voltage in a safe band in the case of various load...

  10. Transmission of power at high voltages

    Energy Technology Data Exchange (ETDEWEB)

    Lane, F J

    1963-01-01

    High voltage transmission is considered to be concerned with circuits and systems operating at or above 132 kV. While the general examination is concerned with ac transmission, dc systems are also included. The choice of voltage for a system will usually involve hazardous assessments of the future requirements of industry, commerce and a changing population. Experience suggests that, if the estimated economic difference between two voltages is not significant, there is good reason to choose the higher voltage, as this will make the better provision for unexpected future expansion. Two principal functions served by transmission circuits in a supply system are: (a) the transportation of energy in bulk from the generator to the reception point in the distribution system; and (b) the interconnection and integration of the generating plant and associated loads. These functions are considered and various types of system are discussed in terms of practicability, viability, quality and continuity of supply. Future developments requiring transmission voltages up to 750 kV will raise many problems which are in the main empirical. Examples are given of the type of problem envisaged and it is suggested that these can only be partially solved by theory and model operation.

  11. Induced Voltage in an Open Wire

    Science.gov (United States)

    Morawetz, K.; Gilbert, M.; Trupp, A.

    2017-07-01

    A puzzle arising from Faraday's law has been considered and solved concerning the question which voltage will be induced in an open wire with a time-varying homogeneous magnetic field. In contrast to closed wires where the voltage is determined by the time variance of the magnetic field and the enclosed area, in an open wire we have to integrate the electric field along the wire. It is found that the longitudinal electric field with respect to the wave vector contributes with 1/3 and the transverse field with 2/3 to the induced voltage. In order to find the electric fields the sources of the magnetic fields are necessary to know. The representation of a spatially homogeneous and time-varying magnetic field implies unavoidably a certain symmetry point or symmetry line which depend on the geometry of the source. As a consequence the induced voltage of an open wire is found to be the area covered with respect to this symmetry line or point perpendicular to the magnetic field. This in turn allows to find the symmetry points of a magnetic field source by measuring the voltage of an open wire placed with different angles in the magnetic field. We present exactly solvable models of the Maxwell equations for a symmetry point and for a symmetry line, respectively. The results are applicable to open circuit problems like corrosion and for astrophysical applications.

  12. Dispersion of breakdown voltage of liquid helium

    International Nuclear Information System (INIS)

    Ishii, Itaru; Noguchi, Takuya

    1978-01-01

    As for the electrical insulation characteristics of liquid helium, the discrepancy among the measured values by each person is very large even in the fundamental DC breakdown voltage in uniform electric field. The dispersion of experimental values obtained in the experiments by the same person is also large. Hereafter, the difference among the mean values obtained by each experimenter will be referred to as ''deviation of mean values'', and the dispersion of measured values around the mean value obtained by the same person as ''deviation around the man value''. The authors have mainly investigated on the latter experimentally. The cryostat was made of stainless steel, and the innermost helium chamber was of 500 mm I.D. and approximately 1200 mm deep. The high voltage electrode was of brass sphere of 25 mm diameter, and the low voltage electrode was of brass plate. The experiment was conducted for liquid helium boiling at 4.2 K and 1 atm, and the breakdown voltage and time lag were measured by applying the approximately square wave impulses of fast rise and long tail, ramp and DC voltages. The cause of the deviation of mean values may be the presence of impurity particles or the effect of electrode shape. As for the deviation around the mean value, the dispersion is large, and its standard deviation may amount to 10 to 20% of the man value. The dispersion is not due to the statistical time lag, but is due to parameters that vary with breakdown. (Wakatsuki, Y.)

  13. Voltage breakdown on niobium and copper surfaces

    International Nuclear Information System (INIS)

    Werner, G.R.; Padamsee, H.; Betzwieser, J.C.; Liu, Y.G.; Rubin, K.H.R.; Shipman, J.E.; Ying, L.T.

    2003-01-01

    Experiments have shown that voltage breakdown in superconducting niobium RF cavities is in many ways similar to voltage breakdown on niobium cathodes in DC voltage gaps; most striking are the distinctive starburst patterns and craters that mark the site of voltage breakdown in both superconducting cavities and DC vacuum gaps. Therefore, we can learn much about RF breakdown from simpler, faster DC experiments. We have direct evidence, in the form of before'' and ''after'' pictures, that breakdown events caused by high surface electric fields occur with high probability at contaminant particles on surfaces. Although the pre-breakdown behavior (field emission) seems to depend mostly on the contaminant particles present and little on the substrate, the breakdown event itself is greatly affected by the substrate-niobium, heavily oxidized niobium, electropolished copper, and diamond-machined copper cathodes lead to different kinds of breakdown events. By studying DC voltage breakdown we hope to learn more details about the processes involved in the transition from field emission to catastrophic arcing and the cratering of the surface; as well as learning how to prevent breakdown, we would like to learn how to cause breakdown, which could be important when ''processing'' cavities to reduce field emission. (author)

  14. Vivitron 1995, transient voltage simulation, high voltage insulator tests, electric field calculation

    International Nuclear Information System (INIS)

    Frick, G.; Osswald, F.; Heusch, B.

    1996-01-01

    Preliminary investigations showed clearly that, because of the discrete electrode structure of the Vivitron, important overvoltage leading to insulator damage can appear in case of a spark. The first high voltage tests showed damage connected with such events. This fact leads to a severe voltage limitation. This work describes, at first, studies made to understand the effects of transients and the associated over-voltage appearing in the Vivitron. Then we present the high voltage tests made with full size Vivitron components using the CN 6 MV machine as a pilot machine. Extensive field calculations were made. These involve simulations of static stresses and transient overvoltages, on insulating boards and electrodes. This work gave us the solutions for arrangements and modifications in the machine. After application, the Vivitron runs now without any sparks and damage at 20 MV. In the same manner, we tested column insulators of a new design and so we will find out how to get to higher voltages. Electric field calculation around the tie bars connecting the discrete electrodes together showed field enhancements when the voltages applied on the discrete electrodes are not equally distributed. This fact is one of the sources of discharges and voltage limitations. A scenario of a spark event is described and indications are given how to proceed towards higher voltages, in the 30 MV range. (orig.)

  15. Low-Voltage Consumption Coordination for Loss Minimization and Voltage Control

    DEFF Research Database (Denmark)

    Juelsgaard, Morten; Sloth, Christoffer; Wisniewski, Rafal

    2014-01-01

    This work presents a strategy for minimizing active power losses in low-voltage grids, by coordinating the consumption of electric vehicles and power generation from solar panels. We show that minimizing losses, also reduces voltage variations, and illustrate how this may be employed for increasing...

  16. Analysis of Voltage Support by Electric Vehicles and Photovoltaic in a Real Danish Low Voltage Network

    DEFF Research Database (Denmark)

    Knezovic, Katarina; Marinelli, Mattia; Juul Møller, René

    2014-01-01

    of incorporating electric vehicles (EVs) in a low voltage distribution network with high penetration of photovoltaic installations (PVs), and focuses on analysing potential voltage support functions from EVs and PVs. In addition, the paper evaluates the benefits that reactive power control may provide...

  17. Light emitting diode driver with differential voltage supply

    NARCIS (Netherlands)

    2015-01-01

    The current invention relates to a driver for driving one or a plurality of LEDs (D1, D2), comprising at least one driving unit (201, 202) adapted to be supplied with a differential voltage, between one first bias voltage (VB1) and one second bias voltage (VB2), the differential voltage being

  18. 30 CFR 75.804 - Underground high-voltage cables.

    Science.gov (United States)

    2010-07-01

    ... AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Underground High-Voltage Distribution § 75.804 Underground high-voltage cables. (a) Underground high-voltage cables used in resistance... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Underground high-voltage cables. 75.804 Section...

  19. 30 CFR 75.813 - High-voltage longwalls; scope.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false High-voltage longwalls; scope. 75.813 Section... AND HEALTH MANDATORY SAFETY STANDARDS-UNDERGROUND COAL MINES Underground High-Voltage Distribution High-Voltage Longwalls § 75.813 High-voltage longwalls; scope. Sections 75.814 through 75.822 of this...

  20. Voltage Support from Electric Vehicles in Distribution Grid

    DEFF Research Database (Denmark)

    Huang, Shaojun; Pillai, Jayakrishnan Radhakrishna; Bak-Jensen, Birgitte

    2013-01-01

    The paper evaluates the voltage support functions from electric vehicles (EVs) on a typical Danish distribution grid with high EV penetration. In addition to the popular voltage control modes, such as voltage droop charging (low voltage level leads to low charging power) and reactive power support...