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Sample records for vlsi processing arrays

  1. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  2. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  3. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  4. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  5. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  6. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  7. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  8. A Methodology for Mapping and Partitioning Arbitrary N—Dimensional Nested Loops into 2—Dimensional VLSI Arrays

    Institute of Scientific and Technical Information of China (English)

    刘弘; 王文红; 等

    1993-01-01

    A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.

  9. A VLSI field-programmable mixed-signal array to perform neural signal processing and neural modeling in a prosthetic system.

    Science.gov (United States)

    Bamford, Simeon A; Hogri, Roni; Giovannucci, Andrea; Taub, Aryeh H; Herreros, Ivan; Verschure, Paul F M J; Mintz, Matti; Del Giudice, Paolo

    2012-07-01

    A very-large-scale integration field-programmable mixed-signal array specialized for neural signal processing and neural modeling has been designed. This has been fabricated as a core on a chip prototype intended for use in an implantable closed-loop prosthetic system aimed at rehabilitation of the learning of a discrete motor response. The chosen experimental context is cerebellar classical conditioning of the eye-blink response. The programmable system is based on the intimate mixing of switched capacitor analog techniques with low speed digital computation; power saving innovations within this framework are presented. The utility of the system is demonstrated by the implementation of a motor classical conditioning model applied to eye-blink conditioning in real time with associated neural signal processing. Paired conditioned and unconditioned stimuli were repeatedly presented to an anesthetized rat and recordings were taken simultaneously from two precerebellar nuclei. These paired stimuli were detected in real time from this multichannel data. This resulted in the acquisition of a trigger for a well-timed conditioned eye-blink response, and repetition of unpaired trials constructed from the same data led to the extinction of the conditioned response trigger, compatible with natural cerebellar learning in awake animals.

  10. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  11. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  12. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  13. Design and Realization of Array Signal Processor VLSI Architecture for Phased Array System

    Directory of Open Access Journals (Sweden)

    D. Govind Rao

    2016-08-01

    Full Text Available A method for implementing an array signal processor for phased array radars. The array signal processor can receive planar array antenna inputs and can process it. It is based on the application of Adaptive Digital beam formers using FPGAs. Adaptive filter algorithm used here is Inverse Q-R Decomposition based Recursive Least Squares (IQRD-RLS [1] algorithm. Array signal processor based on FPGAs is suitable in the areas of Phased Array Radar receiver, where speed, accuracy and numerical stability are of utmost important. Using IQRD-RLS algorithm, optimal weights are calculated in much less time compared to conventional QRD-RLS algorithm. A customized multiple FPGA board comprising three Kintex-7 FPGAs is employed to implement array signal processor. The proposed architecture can form multiple beams from planar array antenna elements

  14. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  15. VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.

    Science.gov (United States)

    Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V

    2007-03-01

    A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

  16. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  17. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  18. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  19. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  20. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  1. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  2. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    Science.gov (United States)

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-04

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.

  3. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  4. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  5. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  6. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  7. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  8. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  9. Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.

    Science.gov (United States)

    1984-10-01

    analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI

  10. An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

    Directory of Open Access Journals (Sweden)

    Tze-Yun Sung

    2010-01-01

    Full Text Available Discrete Cosine transform (DCT and inverse DCT (IDCT have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array and SoC (system on chip. The linear-array DCT/IDCT processor with the computation complexity O(5N/8 and hardware complexity O(5N/8 is fully pipelined and scalable for variable-length DCT/IDCT computations.

  11. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  12. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  13. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  14. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  15. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  16. A unified approach to VLSI layout automation and algorithm mapping on processor arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.

    1993-01-01

    Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.

  17. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  18. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  19. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  20. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  1. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  2. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  3. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  4. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  5. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  6. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  7. Acoustic signal processing toolbox for array processing

    Science.gov (United States)

    Pham, Tien; Whipps, Gene T.

    2003-08-01

    The US Army Research Laboratory (ARL) has developed an acoustic signal processing toolbox (ASPT) for acoustic sensor array processing. The intent of this document is to describe the toolbox and its uses. The ASPT is a GUI-based software that is developed and runs under MATLAB. The current version, ASPT 3.0, requires MATLAB 6.0 and above. ASPT contains a variety of narrowband (NB) and incoherent and coherent wideband (WB) direction-of-arrival (DOA) estimation and beamforming algorithms that have been researched and developed at ARL. Currently, ASPT contains 16 DOA and beamforming algorithms. It contains several different NB and WB versions of the MVDR, MUSIC and ESPRIT algorithms. In addition, there are a variety of pre-processing, simulation and analysis tools available in the toolbox. The user can perform simulation or real data analysis for all algorithms with user-defined signal model parameters and array geometries.

  8. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  9. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  10. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  11. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  12. VLSI Research

    Science.gov (United States)

    1984-04-01

    massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly

  13. BM/C3 Force Model VLSI/VHSIC Digital Processing: A Cost Methodology

    Science.gov (United States)

    1988-10-01

    instructions per second. Three module types from the 1750A program are planned for use in CSP configurations. These are the 1750A central processing unit (CPU...number of produccions lots is increased. This is similar to a learning curve effect. Quantity demanded largely explains the reason why memory chips are

  14. Modeling latency code processing in the electric sense: from the biological template to its VLSI implementation.

    Science.gov (United States)

    Engelmann, Jacob; Walther, Tim; Grant, Kirsty; Chicca, Elisabetta; Gómez-Sena, Leonel

    2016-09-13

    Understanding the coding of sensory information under the temporal constraints of natural behavior is not yet well resolved. There is a growing consensus that spike timing or latency coding can maximally exploit the timing of neural events to make fast computing elements and that such mechanisms are essential to information processing functions in the brain. The electric sense of mormyrid fish provides a convenient biological model where this coding scheme can be studied. The sensory input is a physically ordered spatial pattern of current densities, which is coded in the precise timing of primary afferent spikes. The neural circuits of the processing pathway are well known and the system exhibits the best known illustration of corollary discharge, which provides the reference to decoding the sensory afferent latency pattern. A theoretical model has been constructed from available electrophysiological and neuroanatomical data to integrate the principal traits of the neural processing structure and to study sensory interaction with motor-command-driven corollary discharge signals. This has been used to explore neural coding strategies at successive stages in the network and to examine the simulated network capacity to reproduce output neuron responses. The model shows that the network has the ability to resolve primary afferent spike timing differences in the sub-millisecond range, and that this depends on the coincidence of sensory and corollary discharge-driven gating signals. In the integrative and output stages of the network, corollary discharge sets up a proactive background filter, providing temporally structured excitation and inhibition within the network whose balance is then modulated locally by sensory input. This complements the initial gating mechanism and contributes to amplification of the input pattern of latencies, conferring network hyperacuity. These mechanisms give the system a robust capacity to extract behaviorally meaningful features of the

  15. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  16. Plasmonics based VLSI processes

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2013-04-01

    Full Text Available In continuum to my previous paper titled‘Implementation of plasmonics in VLSI’, this paperattempts to explore further, the actual physicalrealization of an all-plasmonic chip. In this paper,various methods of plasmon-basedphotolithography have been discussed and anobservation is made w.r.t the cost effectiveness andease of adaptability. Also, plasmonics based activeelement has been discussed which would helpunravel further arenas ofapproaches and methodstowards the realization of an all-plasmonic chip.

  17. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  18. Array Processing for Radar: Achievements and Challenges

    Directory of Open Access Journals (Sweden)

    Ulrich Nickel

    2013-01-01

    Full Text Available Array processing for radar is well established in the literature, but only few of these algorithms have been implemented in real systems. The reason may be that the impact of these algorithms on the overall system must be well understood. For a successful implementation of array processing methods exploiting the full potential, the desired radar task has to be considered and all processing necessary for this task has to be eventually adapted. In this tutorial paper, we point out several viewpoints which are relevant in this context: the restrictions and the potential provided by different array configurations, the predictability of the transmission function of the array, the constraints for adaptive beamforming, the inclusion of monopulse, detection and tracking into the adaptive beamforming concept, and the assessment of superresolution methods with respect to their application in a radar system. The problems and achieved results are illustrated by examples from previous publications.

  19. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  20. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  1. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  2. High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug

    2006-07-24

    Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

  3. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  4. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  5. Astronomical Image Processing with Array Detectors

    CERN Document Server

    Houde, Martin

    2007-01-01

    We address the question of astronomical image processing from data obtained with array detectors. We define and analyze the cases of evenly, regularly, and irregularly sampled maps for idealized (i.e., infinite) and realistic (i.e., finite) detectors. We concentrate on the effect of interpolation on the maps, and the choice of the kernel used to accomplish this task. We show how the normalization intrinsic to the interpolation process must be carefully accounted for when dealing with irregularly sampled grids. We also analyze the effect of missing or dead pixels in the array, and their consequences for the Nyquist sampling criterion.

  6. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  7. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  8. Contour Estimation by Array Processing Methods

    Directory of Open Access Journals (Sweden)

    Bourennane Salah

    2006-01-01

    Full Text Available This work is devoted to the estimation of rectilinear and distorted contours in images by high-resolution methods. In the case of rectilinear contours, it has been shown that it is possible to transpose this image processing problem to an array processing problem. The existing straight line characterization method called subspace-based line detection (SLIDE leads to models with orientations and offsets of straight lines as the desired parameters. Firstly, a high-resolution method of array processing leads to the orientation of the lines. Secondly, their offset can be estimated by either the well-known method of extension of the Hough transform or another method, namely, the variable speed propagation scheme, that belongs to the array processing applications field. We associate it with the method called "modified forward-backward linear prediction" (MFBLP. The signal generation process devoted to straight lines retrieval is retained for the case of distorted contours estimation. This issue is handled for the first time thanks to an inverse problem formulation and a phase model determination. The proposed method is initialized by means of the SLIDE algorithm.

  9. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  10. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  11. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  12. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  13. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  14. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  15. An algorithm for signal processing in multibeam antenna arrays

    Science.gov (United States)

    Danilevskii, L. N.; Domanov, Iu. A.; Korobko, O. V.

    1980-09-01

    A signal processing method for multibeam antenna arrays is presented which can be used to effectively reduce discrete-phasing sidelobes. Calculations of an 11-element array are presented as an example.

  16. Array signal processing in the NASA Deep Space Network

    Science.gov (United States)

    Pham, Timothy T.; Jongeling, Andre P.

    2004-01-01

    In this paper, we will describe the benefits of arraying and past as well as expected future use of this application. The signal processing aspects of array system are described. Field measurements via actual tracking spacecraft are also presented.

  17. Multipath Array Processing for Co-Prime and Under-Sampled Sensor Arrays

    Science.gov (United States)

    2015-09-30

    freedom than physical sensors present in the array. However, the cost of the achievable degrees of freedom is a loss of approximately half of the array...of degrees of freedom of the array. A co-prime frequency comb is a novel active sonar waveform that achieves range-Doppler performance similar...localization with moving co-prime arrays,” in Acoustics, Speech and Signal Processing (ICASSP), 2015 IEEE International Conference on, 2015. 6 2

  18. Square Kilometre Array Science Data Processing

    Science.gov (United States)

    Nikolic, Bojan; SDP Consortium, SKA

    2014-04-01

    The Square Kilometre Array (SKA) is planned to be, by a large factor, the largest and most sensitive radio telescope ever constructed. The first phase of the telescope (SKA1), now in the design phase, will in itself represent a major leap in capabilities compared to current facilities. These advances are to a large extent being made possible by advances in available computer processing power so that that larger numbers of smaller, simpler and cheaper receptors can be used. As a result of greater reliance and demands on computing, ICT is becoming an ever more integral part of the telescope. The Science Data Processor is the part of the SKA system responsible for imaging, calibration, pulsar timing, confirmation of pulsar candidates, derivation of some further derived data products, archiving and providing the data to the users. It will accept visibilities at data rates at several TB/s and require processing power for imaging in range 100 petaFLOPS -- ~1 ExaFLOPS, putting SKA1 into the regime of exascale radio astronomy. In my talk I will present the overall SKA system requirements and how they drive these high data throughput and processing requirements. Some of the key challenges for the design of SDP are: - Identifying sufficient parallelism to utilise very large numbers of separate compute cores that will be required to provide exascale computing throughput - Managing efficiently the high internal data flow rates - A conceptual architecture and software engineering approach that will allow adaptation of the algorithms as we learn about the telescope and the atmosphere during the commissioning and operational phases - System management that will deal gracefully with (inevitably frequent) failures of individual units of the processing system In my talk I will present possible initial architectures for the SDP system that attempt to address these and other challenges.

  19. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  20. Implementation and Performance of GaAs Digital Signal Processing ASICs

    Science.gov (United States)

    Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

    1993-01-01

    The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

  1. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  2. Acetylcholine molecular arrays enable quantum information processing

    Science.gov (United States)

    Tamulis, Arvydas; Majauskaite, Kristina; Talaikis, Martynas; Zborowski, Krzysztof; Kairys, Visvaldas

    2017-09-01

    We have found self-assembly of four neurotransmitter acetylcholine (ACh) molecular complexes in a water molecules environment by using geometry optimization with DFT B97d method. These complexes organizes to regular arrays of ACh molecules possessing electronic spins, i.e. quantum information bits. These spin arrays could potentially be controlled by the application of a non-uniform external magnetic field. The proper sequence of resonant electromagnetic pulses would then drive all the spin groups into the 3-spin entangled state and proceed large scale quantum information bits.

  3. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  4. Theory and applications of spherical microphone array processing

    CERN Document Server

    Jarrett, Daniel P; Naylor, Patrick A

    2017-01-01

    This book presents the signal processing algorithms that have been developed to process the signals acquired by a spherical microphone array. Spherical microphone arrays can be used to capture the sound field in three dimensions and have received significant interest from researchers and audio engineers. Algorithms for spherical array processing are different to corresponding algorithms already known in the literature of linear and planar arrays because the spherical geometry can be exploited to great beneficial effect. The authors aim to advance the field of spherical array processing by helping those new to the field to study it efficiently and from a single source, as well as by offering a way for more experienced researchers and engineers to consolidate their understanding, adding either or both of breadth and depth. The level of the presentation corresponds to graduate studies at MSc and PhD level. This book begins with a presentation of some of the essential mathematical and physical theory relevant to ...

  5. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  6. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  7. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  8. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  9. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    Science.gov (United States)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  10. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  11. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  12. Signal processing method of a novel polarized array radar seeker

    Institute of Scientific and Technical Information of China (English)

    Lizhong Song; Xiaolin Qiao

    2013-01-01

    This paper proposes a novel polarized radar seeker based on the polarized antenna array. A ful y polarized signal processing method for the proposed radar seeker is studied un-der the environments with electromagnetic interferences. A dual polarized antenna array is employed to transmit and receive the radar signals. The instantaneous polarization signal processing technique is used to detect and recognize the targets. The di-rection of arrival (DOA) of the target is measured through the spatial spectrum with high resolution for the polarized array radar seeker system. The ful y polarized signal model of the polarized array radar seeker is formulated and a specific signal processing algorithm is expounded. The theoretical research and numerical simulation results demonstrate that the proposed radar seeker has good performances in target detection and electronic warfare. The research results can provide an effective technical approach to develop and research the new generation radar seeker.

  13. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  14. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  15. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  16. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  17. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  18. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  19. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  20. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  1. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  2. The Signal Processing Firmware for the Low Frequency Aperture Array

    Science.gov (United States)

    Comoretto, Gianni; Chiello, Riccardo; Roberts, Matt; Halsall, Rob; Adami, Kristian Zarb; Alderighi, Monica; Aminaei, Amin; Baker, Jeremy; Belli, Carolina; Chiarucci, Simone; D'Angelo, Sergio; De Marco, Andrea; Mura, Gabriele Dalle; Magro, Alessio; Mattana, Andrea; Monari, Jader; Naldi, Giovanni; Pastore, Sandro; Perini, Federico; Poloni, Marco; Pupillo, Giuseppe; Rusticelli, Simone; Schiaffino, Marco; Schillirò, Francesco; Zaccaro, Emanuele

    The signal processing firmware that has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA) is described. The firmware is implemented on a dual FPGA board, that is capable of processing the streams from 16 dual polarization antennas. Data processing includes channelization of the sampled data for each antenna, correction for instrumental response and for geometric delays and formation of one or more beams by combining the aligned streams. The channelizer uses an oversampling polyphase filterbank architecture, allowing a frequency continuous processing of the input signal without discontinuities between spectral channels. Each board processes the streams from 16 antennas, as part of larger beamforming system, linked by standard Ethernet interconnections. These are envisaged to be 8192 of these signal processing platforms in the first phase of the SKA so particular attention has been devoted to ensure the design is low cost and low power.

  3. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  4. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  5. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  6. Generic nano-imprint process for fabrication of nanowire arrays

    Energy Technology Data Exchange (ETDEWEB)

    Pierret, Aurelie; Hocevar, Moira; Algra, Rienk E; Timmering, Eugene C; Verschuuren, Marc A; Immink, George W G; Verheijen, Marcel A; Bakkers, Erik P A M [Philips Research Laboratories Eindhoven, High Tech Campus 11, 5656 AE Eindhoven (Netherlands); Diedenhofen, Silke L [FOM Institute for Atomic and Molecular Physics c/o Philips Research Laboratories, High Tech Campus 4, 5656 AE Eindhoven (Netherlands); Vlieg, E, E-mail: e.p.a.m.bakkers@tue.nl [IMM, Solid State Chemistry, Radboud University Nijmegen, Heyendaalseweg 135, 6525 AJ Nijmegen (Netherlands)

    2010-02-10

    A generic process has been developed to grow nearly defect-free arrays of (heterostructured) InP and GaP nanowires. Soft nano-imprint lithography has been used to pattern gold particle arrays on full 2 inch substrates. After lift-off organic residues remain on the surface, which induce the growth of additional undesired nanowires. We show that cleaning of the samples before growth with piranha solution in combination with a thermal anneal at 550 deg. C for InP and 700 deg. C for GaP results in uniform nanowire arrays with 1% variation in nanowire length, and without undesired extra nanowires. Our chemical cleaning procedure is applicable to other lithographic techniques such as e-beam lithography, and therefore represents a generic process.

  7. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  8. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  9. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  10. On a single step technique for adaptive array processing

    Science.gov (United States)

    Worms, Josef

    1986-07-01

    An improved adaptation algorithm designed for real time signal processing in antenna arrays is presented. The method is used for determining the filter weights in a sidelobe cancellation system. The Wiener filter equation is solved by using the well known Gauss-Seidel method and a sample matrix estimate. This algorithm (SSM - Single Step Method) combines rapid convergence and numerical stability. Compared with the direct SMI-technique and the Widrow LMS-algorithm, the properties of the proposed algorithm lead us to the conclusion that it is especially well suited for airborne antenna array applications.

  11. Finite difference programs and array processors. [High-speed floating point processing by coupling host computer to programable array processor

    Energy Technology Data Exchange (ETDEWEB)

    Rudy, T.E.

    1977-08-01

    An alternative to maxi computers for high-speed floating-point processing capabilities is the coupling of a host computer to a programable array processor. This paper compares the performance of two finite difference programs on various computers and their expected performance on commercially available array processors. The significance of balancing array processor computation, host-array processor control traffic, and data transfer operations is emphasized. 3 figures, 1 table.

  12. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  13. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  14. Full process for integrating silicon nanowire arrays into solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Perraud, Simon; Poncet, Severine; Noel, Sebastien; Levis, Michel; Faucherand, Pascal; Rouviere, Emmanuelle [CEA, LITEN, Laboratoire des Composants pour la Recuperation d' Energie, 17 rue des Martyrs, 38054 Grenoble Cedex 9 (France); Thony, Philippe; Jaussaud, Claude; Delsol, Regis [CEA, LITEN, Laboratoire des Composants Solaires, INES-RDI, Savoie Technolac, 50 avenue du Lac Leman, 73377 Le-Bourget-du-Lac (France)

    2009-09-15

    A novel process was developed for integrating silicon nanowire arrays into solar cells. n-Type silicon nanowires were grown by chemical-vapour deposition via the gold-catalysed vapour-liquid-solid method, on a p-type silicon substrate. After the growth, the nanowire array was planarized, by embedding the nanowires in a spin-on glass matrix and subsequent chemical-mechanical polishing of the front surface. This planarization step allows to deposit a continuous and uniform conductive film on top of the nanowire array, and thus to form a high-quality front electrical contact. For an illumination intensity of 100 mW/cm{sup 2}, our devices exhibit an energy conversion efficiency of 1.9%. The main performance limiting factor is a high pn junction reverse current, due to contamination by the growth catalyst or to a lack of passivation of surface electronic defects. (author)

  15. Model-based processing for underwater acoustic arrays

    CERN Document Server

    Sullivan, Edmund J

    2015-01-01

    This monograph presents a unified approach to model-based processing for underwater acoustic arrays. The use of physical models in passive array processing is not a new idea, but it has been used on a case-by-case basis, and as such, lacks any unifying structure. This work views all such processing methods as estimation procedures, which then can be unified by treating them all as a form of joint estimation based on a Kalman-type recursive processor, which can be recursive either in space or time, depending on the application. This is done for three reasons. First, the Kalman filter provides a natural framework for the inclusion of physical models in a processing scheme. Second, it allows poorly known model parameters to be jointly estimated along with the quantities of interest. This is important, since in certain areas of array processing already in use, such as those based on matched-field processing, the so-called mismatch problem either degrades performance or, indeed, prevents any solution at all. Third...

  16. Signal Processing for a Lunar Array: Minimizing Power Consumption

    Science.gov (United States)

    D'Addario, Larry; Simmons, Samuel

    2011-01-01

    Motivation for the study is: (1) Lunar Radio Array for low frequency, high redshift Dark Ages/Epoch of Reionization observations (z =6-50, f=30-200 MHz) (2) High precision cosmological measurements of 21 cm H I line fluctuations (3) Probe universe before first star formation and provide information about the Intergalactic Medium and evolution of large scale structures (5) Does the current cosmological model accurately describe the Universe before reionization? Lunar Radio Array is for (1) Radio interferometer based on the far side of the moon (1a) Necessary for precision measurements, (1b) Shielding from earth-based and solar RFI (12) No permanent ionosphere, (2) Minimum collecting area of approximately 1 square km and brightness sensitivity 10 mK (3)Several technologies must be developed before deployment The power needed to process signals from a large array of nonsteerable elements is not prohibitive, even for the Moon, and even in current technology. Two different concepts have been proposed: (1) Dark Ages Radio Interferometer (DALI) (2)( Lunar Array for Radio Cosmology (LARC)

  17. Signal Processing for a Lunar Array: Minimizing Power Consumption

    Science.gov (United States)

    D'Addario, Larry; Simmons, Samuel

    2011-01-01

    Motivation for the study is: (1) Lunar Radio Array for low frequency, high redshift Dark Ages/Epoch of Reionization observations (z =6-50, f=30-200 MHz) (2) High precision cosmological measurements of 21 cm H I line fluctuations (3) Probe universe before first star formation and provide information about the Intergalactic Medium and evolution of large scale structures (5) Does the current cosmological model accurately describe the Universe before reionization? Lunar Radio Array is for (1) Radio interferometer based on the far side of the moon (1a) Necessary for precision measurements, (1b) Shielding from earth-based and solar RFI (12) No permanent ionosphere, (2) Minimum collecting area of approximately 1 square km and brightness sensitivity 10 mK (3)Several technologies must be developed before deployment The power needed to process signals from a large array of nonsteerable elements is not prohibitive, even for the Moon, and even in current technology. Two different concepts have been proposed: (1) Dark Ages Radio Interferometer (DALI) (2)( Lunar Array for Radio Cosmology (LARC)

  18. Planar Thinned Arrays: Optimization and Subarray Based Adaptive Processing

    Directory of Open Access Journals (Sweden)

    P. Lombardo

    2013-01-01

    Full Text Available A new approach is presented for the optimized design of a planar thinned array; the proposed strategy works with single antenna elements or with small sets of different subarray types, properly located on a planar surface. The optimization approach is based on the maximization of an objective function accounting for side lobe level and considering a fixed number of active elements/subarrays. The proposed technique is suitable for different shapes of the desired output array, allowing the achievement of the desired directivity properties on the corresponding antenna pattern. The use of subarrays with a limited number of different shapes is relevant for industrial production, which would benefit from reduced design and manufacturing costs. The resulting modularity allows scalable antenna designs for different applications. Moreover, subarrays can be arranged in a set of subapertures, each connected to an independent receiving channel. Therefore, adaptive processing techniques could be applied to cope with and mitigate clutter echoes and external electromagnetic interferences. The performance of adaptive techniques with subapertures taken from the optimized thinned array is evaluated against assigned clutter and jamming scenarios and compared to the performance achievable considering a subarray based filled array with the same number of active elements.

  19. Superresolution with Seismic Arrays using Empirical Matched Field Processing

    Energy Technology Data Exchange (ETDEWEB)

    Harris, D B; Kvaerna, T

    2010-03-24

    Scattering and refraction of seismic waves can be exploited with empirical matched field processing of array observations to distinguish sources separated by much less than the classical resolution limit. To describe this effect, we use the term 'superresolution', a term widely used in the optics and signal processing literature to denote systems that break the diffraction limit. We illustrate superresolution with Pn signals recorded by the ARCES array in northern Norway, using them to identify the origins with 98.2% accuracy of 549 explosions conducted by closely-spaced mines in northwest Russia. The mines are observed at 340-410 kilometers range and are separated by as little as 3 kilometers. When viewed from ARCES many are separated by just tenths of a degree in azimuth. This classification performance results from an adaptation to transient seismic signals of techniques developed in underwater acoustics for localization of continuous sound sources. Matched field processing is a potential competitor to frequency-wavenumber and waveform correlation methods currently used for event detection, classification and location. It operates by capturing the spatial structure of wavefields incident from a particular source in a series of narrow frequency bands. In the rich seismic scattering environment, closely-spaced sources far from the observing array nonetheless produce distinct wavefield amplitude and phase patterns across the small array aperture. With observations of repeating events, these patterns can be calibrated over a wide band of frequencies (e.g. 2.5-12.5 Hertz) for use in a power estimation technique similar to frequency-wavenumber analysis. The calibrations enable coherent processing at high frequencies at which wavefields normally are considered incoherent under a plane wave model.

  20. Physics-based signal processing algorithms for micromachined cantilever arrays

    Science.gov (United States)

    Candy, James V; Clague, David S; Lee, Christopher L; Rudd, Robert E; Burnham, Alan K; Tringe, Joseph W

    2013-11-19

    A method of using physics-based signal processing algorithms for micromachined cantilever arrays. The methods utilize deflection of a micromachined cantilever that represents the chemical, biological, or physical element being detected. One embodiment of the method comprises the steps of modeling the deflection of the micromachined cantilever producing a deflection model, sensing the deflection of the micromachined cantilever and producing a signal representing the deflection, and comparing the signal representing the deflection with the deflection model.

  1. Radar Array Signal Processing in the Presence of Scattering Effects

    Science.gov (United States)

    2008-01-15

    Final INov . 2004 - Oct. 2007 4. TITLE AND SUBTITLE Sa. CON RACT NUMBER Radar Array Signal Processing in the Presence of Scattering Effects N/A 5b. GRANT...polarization. Hence, we considered models depicting how the features of this signal are affected by the medium materials through which the signal propagates. We...security (e.g., for nuclear materials ), and particle communications. We assume Poisson distribution for each detectors measurement within the

  2. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  3. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  4. ArrayPipe: a flexible processing pipeline for microarray data

    Science.gov (United States)

    Hokamp, Karsten; Roche, Fiona M.; Acab, Michael; Rousseau, Marc-Etienne; Kuo, Byron; Goode, David; Aeschliman, Dana; Bryan, Jenny; Babiuk, Lorne A.; Hancock, Robert E. W.; Brinkman, Fiona S. L.

    2004-01-01

    A number of microarray analysis software packages exist already; however, none combines the user-friendly features of a web-based interface with potential ability to analyse multiple arrays at once using flexible analysis steps. The ArrayPipe web server (freely available at www.pathogenomics.ca/arraypipe) allows the automated application of complex analyses to microarray data which can range from single slides to large data sets including replicates and dye-swaps. It handles output from most commonly used quantification software packages for dual-labelled arrays. Application features range from quality assessment of slides through various data visualizations to multi-step analyses including normalization, detection of differentially expressed genes, andcomparison and highlighting of gene lists. A highly customizable action set-up facilitates unrestricted arrangement of functions, which can be stored as action profiles. A unique combination of web-based and command-line functionality enables comfortable configuration of processes that can be repeatedly applied to large data sets in high throughput. The output consists of reports formatted as standard web pages and tab-delimited lists of calculated values that can be inserted into other analysis programs. Additional features, such as web-based spreadsheet functionality, auto-parallelization and password protection make this a powerful tool in microarray research for individuals and large groups alike. PMID:15215429

  5. Investigation of certain characteristics of thinned antenna arrays with digital signal processing

    Science.gov (United States)

    Danilevskii, L. V.; Domanov, Iu. A.; Korobko, O. V.; Tauroginskii, B. I.

    1983-11-01

    A thinned array with correlation processing of input signals is examined. It is shown that amplitude quantization does not change the signal at the thinned-array input as compared with the complete antenna array. The discreteness of time delay causes the thinned and complete arrays to become nonequivalent. Computer-simulation results are presented.

  6. SAR processing with stepped chirps and phased array antennas.

    Energy Technology Data Exchange (ETDEWEB)

    Doerry, Armin Walter

    2006-09-01

    Wideband radar signals are problematic for phased array antennas. Wideband radar signals can be generated from series or groups of narrow-band signals centered at different frequencies. An equivalent wideband LFM chirp can be assembled from lesser-bandwidth chirp segments in the data processing. The chirp segments can be transmitted as separate narrow-band pulses, each with their own steering phase operation. This overcomes the problematic dilemma of steering wideband chirps with phase shifters alone, that is, without true time-delay elements.

  7. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  8. Array Processing in the Cloud: the rasdaman Approach

    Science.gov (United States)

    Merticariu, Vlad; Dumitru, Alex

    2015-04-01

    The multi-dimensional array data model is gaining more and more attention when dealing with Big Data challenges in a variety of domains such as climate simulations, geographic information systems, medical imaging or astronomical observations. Solutions provided by classical Big Data tools such as Key-Value Stores and MapReduce, as well as traditional relational databases, proved to be limited in domains associated with multi-dimensional data. This problem has been addressed by the field of array databases, in which systems provide database services for raster data, without imposing limitations on the number of dimensions that a dataset can have. Examples of datasets commonly handled by array databases include 1-dimensional sensor data, 2-D satellite imagery, 3-D x/y/t image time series as well as x/y/z geophysical voxel data, and 4-D x/y/z/t weather data. And this can grow as large as simulations of the whole universe when it comes to astrophysics. rasdaman is a well established array database, which implements many optimizations for dealing with large data volumes and operation complexity. Among those, the latest one is intra-query parallelization support: a network of machines collaborate for answering a single array database query, by dividing it into independent sub-queries sent to different servers. This enables massive processing speed-ups, which promise solutions to research challenges on multi-Petabyte data cubes. There are several correlated factors which influence the speedup that intra-query parallelisation brings: the number of servers, the capabilities of each server, the quality of the network, the availability of the data to the server that needs it in order to compute the result and many more. In the effort of adapting the engine to cloud processing patterns, two main components have been identified: one that handles communication and gathers information about the arrays sitting on every server, and a processing unit responsible with dividing work

  9. High-resolution imaging methods in array signal processing

    DEFF Research Database (Denmark)

    Xenaki, Angeliki

    The purpose of this study is to develop methods in array signal processing which achieve accurate signal reconstruction from limited observations resulting in high-resolution imaging. The focus is on underwater acoustic applications and sonar signal processing both in active (transmit and receive...... in active sonar signal processing for detection and imaging of submerged oil contamination in sea water from a deep-water oil leak. The submerged oil _eld is modeled as a uid medium exhibiting spatial perturbations in the acoustic parameters from their mean ambient values which cause weak scattering......) and passive (only receive) mode. The study addresses the limitations of existing methods and shows that, in many cases, the proposed methods overcome these limitations and outperform traditional methods for acoustic imaging. The project comprises two parts; The first part deals with computational methods...

  10. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  11. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  12. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  13. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  14. Solution processed semiconductor alloy nanowire arrays for optoelectronic applications

    Science.gov (United States)

    Shimpi, Paresh R.

    In this dissertation, we use ZnO nanowire as a model system to investigate the potential of solution routes for bandgap engineering in semiconductor nanowires. Excitingly, successful Mg-alloying into ZnO nanowire arrays has been achieved using a two-step sequential hydrothermal method at low temperature (green-yellow-red band (˜400-660 nm) increased whereas intensity of NBE UV peak decreased and completely got quenched. This might be due to interface diffusion of oxidized Si (SiOx) and formation of (Zn,Mg)1.7SiO4 epitaxially overcoated around individual ZnMgO nanowire. On the other hand, ambient annealed ZnMgO nanowires grown on quartz showed a ˜6-10 nm blue-shift in NBE UV emission, indicating significantly enhanced inter-diffusion of Mg into ZnO nanowires in this oxygen-rich environment. The successfully developed solution process for semiconductor nanowires alloying has few advantages in low cost, large yield, environmental friendliness and low reaction temperature. This solution processed ZnMgO nanowire arrays could provide a new class of nanoscale building blocks for various optoelectronic devices in UV lighting and visible solar energy harvesting.

  15. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  16. Phased array ultrasonic processing for enhanced and affordable diagnosis

    Science.gov (United States)

    Dominguez, N.; Rougeron, G.; Leberre, S.; Pautel, R.

    2013-01-01

    Phased array ultrasonic reconstruction techniques are often presented as a prospect for better and enhanced diagnosis. However to date few applications of these techniques can be found in the industry, partly because of questions on sizing but also because they often require heavy acquisitions. A way forward is then to propose techniques requiring less intensive data acquisition to make them broadly affordable in practice. Several approaches ranging from full matrix capture to paintbrush acquisitions are presented in this paper in combination with associated reconstruction processing like the Total Focusing Method (TFM) and the Time Domain Topological Energy (TDTE) techniques. Emphasis is given to their relative relevancies and practical applicability on typical configurations of interest for industries. The paper also presents recent efforts made on the acceleration of processing computation times, in particular through the use of GPU architectures.

  17. Analysis of Wide-Band Signals Using Wavelet Array Processing

    Science.gov (United States)

    Nisii, V.; Saccorotti, G.

    2005-12-01

    Wavelets transforms allow for precise time-frequency localization in the analysis of non-stationary signals. In wavelet analysis the trade-off between frequency bandwidth and time duration, also known as Heisenberg inequality, is by-passed using a fully scalable modulated window which solves the signal-cutting problem of Windowed Fourier Transform. We propose a new seismic array data processing procedure capable of displaying the localized spatial coherence of the signal in both the time- and frequency-domain, in turn deriving the propagation parameters of the most coherent signals crossing the array. The procedure consists in: a) Wavelet coherence analysis for each station pair of the instruments array, aimed at retrieving the frequency- and time-localisation of coherent signals. To this purpose, we use the normalised wavelet cross- power spectrum, smoothed along the time and scale domains. We calculate different coherence spectra adopting smoothing windows of increasing lengths; a final, robust estimate of the time-frequency localisation of spatially-coherent signals is eventually retrieved from the stack of the individual coherence distribution. This step allows for a quick and reliable signal discrimination: wave groups propagating across the network will manifest as high-coherence patches spanning the corresponding time-scale region. b) Once the signals have been localised in the time and frequency domain,their propagation parameters are estimated using a modified MUSIC (MUltiple SIgnal Characterization) algorithm. We select the MUSIC approach as it demonstrated superior performances in the case of low SNR signals, more plane waves contemporaneously impinging at the array and closely separated sources. The narrow-band Coherent Signal Subspace technique is applied to the complex Continuous Wavelet Transform of multichannel data for improving the singularity of the estimated cross-covariance matrix and the accuracy of the estimated signal eigenvectors. Using

  18. Error analysis of subaperture processing in 1-D ultrasound arrays.

    Science.gov (United States)

    Zhao, Kang-Qiao; Bjåstad, Tore Gruner; Kristoffersen, Kjell

    2015-04-01

    To simplify the medical ultrasound system and reduce the cost, several techniques have been proposed to reduce the interconnections between the ultrasound probe and the back-end console. Among them, subaperture processing (SAP) is the most straightforward approach and is widely used in commercial products. This paper reviews the most important error sources of SAP, such as static focusing, delay quantization, linear delay profile, and coarse apodization, and the impacts introduced by these errors are shown. We propose to use main lobe coherence loss as a simple classification of the quality of the beam profile for a given design. This figure-ofmerit (FoM) is evaluated by simulations with a 1-D ultrasound subaperture array setup. The analytical expressions and the coherence loss can work as a quick guideline in subaperture design by equalizing the merit degradations from different error sources, as well as minimizing the average or maximum loss over ranges. For the evaluated 1-D array example, a good balance between errors and cost was achieved using a subaperture size of 5 elements, focus at 40 mm range, and a delay quantization step corresponding to a phase of π/4.

  19. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  20. Non-linear, adaptive array processing for acoustic interference suppression.

    Science.gov (United States)

    Hoppe, Elizabeth; Roan, Michael

    2009-06-01

    A method is introduced where blind source separation of acoustical sources is combined with spatial processing to remove non-Gaussian, broadband interferers from space-time displays such as bearing track recorder displays. This differs from most standard techniques such as generalized sidelobe cancellers in that the separation of signals is not done spatially. The algorithm performance is compared to adaptive beamforming techniques such as minimum variance distortionless response beamforming. Simulations and experiments using two acoustic sources were used to verify the performance of the algorithm. Simulations were also used to determine the effectiveness of the algorithm under various signal to interference, signal to noise, and array geometry conditions. A voice activity detection algorithm was used to benchmark the performance of the source isolation.

  1. An operational approach for infrasound multi-array processing

    Science.gov (United States)

    Vergoz, J.; Le Pichon, A.; Herry, P.; Blanc, E.

    2009-04-01

    The infrasound network of the International Monitoring Network (IMS) of the Comprehensive Nuclear-Test-Ban Treaty Organization (CTBTO) is currently not fully established. However, it has demonstrated its capability for detecting and locating infrasonic sources like meteorites as well as volcanic eruptions on a global scale. Unfortunately, such ground truth events are rare. Therefore, regions with dense infrasound networks have to be considered in order to test and calibrate detection and location procedures (Le Pichon. et al. 2008, J. Geophys. Res., 113, D12115, doi:10.1029/2007JD009509). In Central Europe, several years of continuous infrasound recordings are available for many infrasound arrays, where not all of them are part of the IMS. Infrasound waveforms are routinely processed in the 0.1 to 4 Hz frequency band using PMCC as a real-time detector. After applying a categorization procedure to remove detections associated with environmental noise, a blind fusion provides a list of events to be reviewed by the analyst. In order to check the geophysical consistency of the located events, an interactive tool has been developed. All results of the automatic processing are presented along with a realistic estimate of the network detection capability which incorporates near-real time atmospheric updates. Among the dominant acoustic sources of human origin, peaks in the geographical distribution of infrasound events correspond well with seismically active regions where operational mines have been identified. With the increasing number of IMS and regional cluster infrasound arrays deployed around the globe, conducting consistent analyses on a routine-basis provides an extensive database for discriminating between natural and artificial acoustic sources. Continuing such studies may also help quantifying relationships between infrasonic observables and atmospheric specification problems, thus opening new fields for investigations into inverse problems.

  2. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  3. Proceedings of USC (University of Southern California) Workshop on VLSI (Very Large Scale Integration) & Modern Signal Processing, held at Los Angeles, California on 1-3 November 1982

    Science.gov (United States)

    1983-11-15

    WSI and IFT techniques applied to a random point defect distribucion . 151 used some time redundancy.) This discussion has centered around one...linear transport theory as well as the experimental means that monolayer epitaxy can provide may well be reflected in signal processing concepts

  4. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  5. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  6. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  7. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  8. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  9. Damage Detection in Composite Structures with Wavenumber Array Data Processing

    Science.gov (United States)

    Tian, Zhenhua; Leckey, Cara; Yu, Lingyu

    2013-01-01

    Guided ultrasonic waves (GUW) have the potential to be an efficient and cost-effective method for rapid damage detection and quantification of large structures. Attractive features include sensitivity to a variety of damage types and the capability of traveling relatively long distances. They have proven to be an efficient approach for crack detection and localization in isotropic materials. However, techniques must be pushed beyond isotropic materials in order to be valid for composite aircraft components. This paper presents our study on GUW propagation and interaction with delamination damage in composite structures using wavenumber array data processing, together with advanced wave propagation simulations. Parallel elastodynamic finite integration technique (EFIT) is used for the example simulations. Multi-dimensional Fourier transform is used to convert time-space wavefield data into frequency-wavenumber domain. Wave propagation in the wavenumber-frequency domain shows clear distinction among the guided wave modes that are present. This allows for extracting a guided wave mode through filtering and reconstruction techniques. Presence of delamination causes spectral change accordingly. Results from 3D CFRP guided wave simulations with delamination damage in flat-plate specimens are used for wave interaction with structural defect study.

  10. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  11. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  12. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  13. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  14. Signal processing for solar array monitoring, fault detection, and optimization

    CERN Document Server

    Braun, Henry; Spanias, Andreas

    2012-01-01

    Although the solar energy industry has experienced rapid growth recently, high-level management of photovoltaic (PV) arrays has remained an open problem. As sensing and monitoring technology continues to improve, there is an opportunity to deploy sensors in PV arrays in order to improve their management. In this book, we examine the potential role of sensing and monitoring technology in a PV context, focusing on the areas of fault detection, topology optimization, and performance evaluation/data visualization. First, several types of commonly occurring PV array faults are considered and detection algorithms are described. Next, the potential for dynamic optimization of an array's topology is discussed, with a focus on mitigation of fault conditions and optimization of power output under non-fault conditions. Finally, monitoring system design considerations such as type and accuracy of measurements, sampling rate, and communication protocols are considered. It is our hope that the benefits of monitoring presen...

  15. Signal processing techniques applied to a small circular seismic array

    Science.gov (United States)

    Mosher, C. C.

    1980-03-01

    The travel time method (TTM) for locating earthquakes and the wavefront curvature method (WCM), which determines distance to an event by measuring the curvature of the wavefront can be combined in a procedure referred to as Apparent Velocity Mapping (AVM). Apparent velocities for mine blasts and local earthquakes computed by the WCM are inverted for a velocity structure. The velocity structure is used in the TTM to relocate events. Model studies indicate that AVM can adequately resolve the velocity structure for the case of linear velocity-depth gradient. Surface waves from mine blasts recorded by the Central Minnesota Seismic Array were analyzed using a modification of the multiple filter analysis (MFA) technique to determine group arrival times at several stations of an array. The advantages of array MFA are that source location need not be known, lateral refraction can be detected and removed, and multiple arrivals can be separated. A modeling procedure that can be used with array MFA is described.

  16. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  17. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  18. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  19. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  20. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  1. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  2. Simulation and Data Processing for Ultrasonic Phased-Arrays Applications

    Science.gov (United States)

    Chaffaï-Gargouri, S.; Chatillon, S.; Mahaut, S.; Le Ber, L.

    2007-03-01

    The use of phased-arrays techniques has considerably contributed to extend the domain of applications and the performances of ultrasonic methods on complex configurations. Their adaptability offers a great freedom for conceiving the inspection leading to a wide range of functionalities gathering electronic commutation, applications of different delay laws and so on. This advantage allows to circumvent the difficulties encountered with more classical techniques especially when the inspection is assisted by simulation at the different stages : probe design (optimization of the number and characteristics of the elements), evaluation of the performances in terms of flaw detection (zone coverage) and characterization, driving the array (computation of adapted delay laws) and finally analyzing the results (versatile model-based imaging tools allowing in particular to locate the data in the real space). The CEA is strongly involved in the development of efficient simulation-based tools adapted to these needs. In this communication we present the recent advances done at CEA in this field and show several examples of complex NDT phased arrays applications. On these cases we show the interest and the performances of simulation-helped array design, array-driving and data analysis.

  3. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  4. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  5. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  6. Adaptive Antenna-array Processing: A DSP Implementation

    NARCIS (Netherlands)

    Abayomi, T.

    2007-01-01

    Adaptive beamforming is used to increase the gain of a receiver in the direction of a desired signal using antenna arrays. The gain is also decreased in the direction of interference and noise. This report describes the implementation of a baseband processor that calculates the beamforming paramete

  7. Adaptive Antenna-array Processing: A DSP Implementation

    NARCIS (Netherlands)

    Abayomi, T.

    2007-01-01

    Adaptive beamforming is used to increase the gain of a receiver in the direction of a desired signal using antenna arrays. The gain is also decreased in the direction of interference and noise. This report describes the implementation of a baseband processor that calculates the beamforming

  8. High Resolution Processing with an Active Phased Array SAR

    NARCIS (Netherlands)

    Nijenboer, F.J.; Otten, M.P.G.

    1999-01-01

    The Dutch PHARUS system is a polarimetric active phased array SAR capable of performing advanced SAR modes. Advanced SAR modes that are being investigated are: spotlight SAR, sliding spotlight SAR, stepped frequency SAR and interferometric SAR. The flight experiments and automatic beam steering

  9. Analysis of Eigenspace Dynamics with Applications to Array Processing

    Science.gov (United States)

    2014-09-30

    be met in most practical situations,1-2 in which large-aperture arrays operate in the presence of fast maneuvering interferers, or with towed...the improvement of subspace beamforming processors , in which the data snapshots are projected into particular subspaces of interest such as mm xPy

  10. Dimpled Ball Grid Array process development for space flight applications

    Science.gov (United States)

    Barr, S. L.; Mehta, A.

    2000-01-01

    The 472 Dimpled Ball Grid Array (D-BGA) package has not been used in past space flight environments, therefore it is necessary to determine the robustness and reliability of the solder joints. The 472 D-BGA packages passed the above environmental tests within the specifications and are now qualified for use on space flight electronics.

  11. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  12. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  13. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  14. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  15. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  16. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  17. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  18. Study of acoustic signal in the process of resistance spot welding based on array sensor system

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    This investigation was performed to study acoustic field signal in order to improve RSW quality. Researchers firstly built an acoustic array sensor system, which included 8 MPA-416 acoustic sensors, data acquisition card and LabVIEW. The system obtained the acoustic field information in the process of nugget growing. Due to the nonlinearity field signal, array sensor algorithm was utilized to quantitatively analyze the characteristics of acoustic field and reduced noise. The experiment and calculation results show that array sensor system can acquire acoustic field signal of nugget growing in the RSW process and array processing algorithm based on acoustic field can extract characteristic parameters to evaluate RSW quality. It was concluded that the acoustic array sensor system offers a new methodology for RSW quality inspection.

  19. Algorithm-structured computer arrays and networks architectures and processes for images, percepts, models, information

    CERN Document Server

    Uhr, Leonard

    1984-01-01

    Computer Science and Applied Mathematics: Algorithm-Structured Computer Arrays and Networks: Architectures and Processes for Images, Percepts, Models, Information examines the parallel-array, pipeline, and other network multi-computers.This book describes and explores arrays and networks, those built, being designed, or proposed. The problems of developing higher-level languages for systems and designing algorithm, program, data flow, and computer structure are also discussed. This text likewise describes several sequences of successively more general attempts to combine the power of arrays wi

  20. Application of Seismic Array Processing to Tsunami Early Warning

    Science.gov (United States)

    An, C.; Meng, L.

    2015-12-01

    Tsunami wave predictions of the current tsunami warning systems rely on accurate earthquake source inversions of wave height data. They are of limited effectiveness for the near-field areas since the tsunami waves arrive before data are collected. Recent seismic and tsunami disasters have revealed the need for early warning to protect near-source coastal populations. In this work we developed the basis for a tsunami warning system based on rapid earthquake source characterisation through regional seismic array back-projections. We explored rapid earthquake source imaging using onshore dense seismic arrays located at regional distances on the order of 1000 km, which provides faster source images than conventional teleseismic back-projections. We implement this method in a simulated real-time environment, and analysed the 2011 Tohoku earthquake rupture with two clusters of Hi-net stations in Kyushu and Northern Hokkaido, and the 2014 Iquique event with the Earthscope USArray Transportable Array. The results yield reasonable estimates of rupture area, which is approximated by an ellipse and leads to the construction of simple slip models based on empirical scaling of the rupture area, seismic moment and average slip. The slip model is then used as the input of the tsunami simulation package COMCOT to predict the tsunami waves. In the example of the Tohoku event, the earthquake source model can be acquired within 6 minutes from the start of rupture and the simulation of tsunami waves takes less than 2 min, which could facilitate a timely tsunami warning. The predicted arrival time and wave amplitude reasonably fit observations. Based on this method, we propose to develop an automatic warning mechanism that provides rapid near-field warning for areas of high tsunami risk. The initial focus will be Japan, Pacific Northwest and Alaska, where dense seismic networks with the capability of real-time data telemetry and open data accessibility, such as the Japanese HiNet (>800

  1. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  2. A Phased Array Antenna Signal Processing Structure, a Method and a Computer Program Product

    NARCIS (Netherlands)

    Vliet, F.E. van; Dijk, R. van

    2011-01-01

    The invention relates to a phased array antenna signal processing structure. The structure comprises a processor that includes a digital beam forming unit for generating partial beam data from digitized samples of a set of phased array antenna elements. The processor further comprises a set of input

  3. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  4. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  5. Kalman filter-based microphone array signal processing using the equivalent source model

    Science.gov (United States)

    Bai, Mingsian R.; Chen, Ching-Cheng

    2012-10-01

    This paper demonstrates that microphone array signal processing can be implemented by using adaptive model-based filtering approaches. Nearfield and farfield sound propagation models are formulated into state-space forms in light of the Equivalent Source Method (ESM). In the model, the unknown source amplitudes of the virtual sources are adaptively estimated by using Kalman filters (KFs). The nearfield array aimed at noise source identification is based on a Multiple-Input-Multiple-Output (MIMO) state-space model with minimal realization, whereas the farfield array technique aimed at speech quality enhancement is based on a Single-Input-Multiple-Output (SIMO) state-space model. Performance of the nearfield array is evaluated in terms of relative error of the velocity reconstructed on the actual source surface. Numerical simulations for the nearfield array were conducted with a baffled planar piston source. From the error metric, the proposed KF algorithm proved effective in identifying noise sources. Objective simulations and subjective experiments are undertaken to validate the proposed farfield arrays in comparison with two conventional methods. The results of objective tests indicated that the farfield arrays significantly enhanced the speech quality and word recognition rate. The results of subjective tests post-processed with the analysis of variance (ANOVA) and a post-hoc Fisher's least significant difference (LSD) test have shown great promise in the KF-based microphone array signal processing techniques.

  6. Efficient processing of two-dimensional arrays with C or C++

    Science.gov (United States)

    Donato, David I.

    2017-07-20

    Because fast and efficient serial processing of raster-graphic images and other two-dimensional arrays is a requirement in land-change modeling and other applications, the effects of 10 factors on the runtimes for processing two-dimensional arrays with C and C++ are evaluated in a comparative factorial study. This study’s factors include the choice among three C or C++ source-code techniques for array processing; the choice of Microsoft Windows 7 or a Linux operating system; the choice of 4-byte or 8-byte array elements and indexes; and the choice of 32-bit or 64-bit memory addressing. This study demonstrates how programmer choices can reduce runtimes by 75 percent or more, even after compiler optimizations. Ten points of practical advice for faster processing of two-dimensional arrays are offered to C and C++ programmers. Further study and the development of a C and C++ software test suite are recommended.Key words: array processing, C, C++, compiler, computational speed, land-change modeling, raster-graphic image, two-dimensional array, software efficiency

  7. Characterization of diffusivity based on spherical array processing

    DEFF Research Database (Denmark)

    Nolan, Melanie; Fernandez Grande, Efren; Jeong, Cheol-Ho

    2015-01-01

    the sound waves impinge on the array from multiple directions, as they have convenient properties such as omnidirectionality and compensable scattering from the rigid sphere. The proposed methodology makes use of a spherical equivalent source method (S-ESM) to reconstruct the sound field over a three......-dimensional domain and consequently examine some of its fundamental properties: spatial distribution of sound pressure levels, particle velocity and sound intensity. The study allows for visualization of the intensity field inside a reverberant space, and successfully illustrates the behavior of the sound field...

  8. Compressive MUSIC: A Missing Link Between Compressive Sensing and Array Signal Processing

    CERN Document Server

    Kim, Jong Min; Ye, Jong Chul

    2010-01-01

    Multiple measurement vector (MMV) problem addresses identification of unknown input vectors that share common sparse support sets, and has many practical applications. Even though MMV problems had been traditionally addressed within the context of sensory array signal processing, recent research trend is to apply compressive sensing (CS) theory due to its capability to estimate sparse support even with insufficient number of snapshots, in which cases classical array signal processing approaches fail. However, CS approaches guarantees the accurate recovery of support in a probabilistic manner, which often shows inferior performance in the regime where the traditional array signal processing approaches succeed. The main contribution of the present article is, therefore, a unified approach that unveils a {missing link} between compressive sensing and array signal processing approaches for the multiple measurement vector problem. The new algorithm, which we call {\\em compressive MUSIC}, identifies the parts of su...

  9. A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing

    Science.gov (United States)

    2012-03-01

    adopted by the ASIC industry. As a result, this tool has broad support for commercial hardware description languages such as Verilog and VHDL . A...Switch box SRAM Static Random Access Memory VHDL Very High Speed Integrated Circuit Hardware Description Language VLSI Very Large Scale Integration VPR Versatile Place and Route

  10. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  11. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  12. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  13. High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

    Science.gov (United States)

    Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

    2016-04-01

    In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

  14. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  15. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  16. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  17. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  18. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  19. Model-based Processing of Microcantilever Sensor Arrays

    Energy Technology Data Exchange (ETDEWEB)

    Tringe, J W; Clague, D S; Candy, J V; Sinensky, A K; Lee, C L; Rudd, R E; Burnham, A K

    2005-04-27

    We have developed a model-based processor (MBP) for a microcantilever-array sensor to detect target species in solution. We perform a proof-of-concept experiment, fit model parameters to the measured data and use them to develop a Gauss-Markov simulation. We then investigate two cases of interest, averaged deflection data and multi-channel data. For this evaluation we extract model parameters via a model-based estimation, perform a Gauss-Markov simulation, design the optimal MBP and apply it to measured experimental data. The performance of the MBP in the multi-channel case is evaluated by comparison to a ''smoother'' (averager) typically used for microcantilever signal analysis. It is shown that the MBP not only provides a significant gain ({approx} 80dB) in signal-to-noise ratio (SNR), but also consistently outperforms the smoother by 40-60 dB. Finally, we apply the processor to the smoothed experimental data and demonstrate its capability for chemical detection. The MBP performs quite well, apart from a correctable systematic bias error.

  20. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  1. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  2. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  3. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  4. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  5. APD arrays and large-area APDs via a new planar process

    CERN Document Server

    Farrell, R; Vanderpuye, K; Grazioso, R; Myers, R; Entine, G

    2000-01-01

    A fabrication process has been developed which allows the beveled-edge-type of avalanche photodiode (APD) to be made without the need for the artful bevel formation steps. This new process, applicable to both APD arrays and to discrete detectors, greatly simplifies manufacture and should lead to significant cost reduction for such photodetectors. This is achieved through a simple innovation that allows isolation around the device or array pixel to be brought into the plane of the surface of the silicon wafer, hence a planar process. A description of the new process is presented along with performance data for a variety of APD device and array configurations. APD array pixel gains in excess of 10 000 have been measured. Array pixel coincidence timing resolution of less than 5 ns has been demonstrated. An energy resolution of 6% for 662 keV gamma-rays using a CsI(T1) scintillator on a planar processed large-area APD has been recorded. Discrete APDs with active areas up to 13 cm sup 2 have been operated.

  6. An array microscope for ultrarapid virtual slide processing and telepathology. Design, fabrication, and validation study.

    Science.gov (United States)

    Weinstein, Ronald S; Descour, Michael R; Liang, Chen; Barker, Gail; Scott, Katherine M; Richter, Lynne; Krupinski, Elizabeth A; Bhattacharyya, Achyut K; Davis, John R; Graham, Anna R; Rennels, Margaret; Russum, William C; Goodall, James F; Zhou, Pixuan; Olszak, Artur G; Williams, Bruce H; Wyant, James C; Bartels, Peter H

    2004-11-01

    This paper describes the design and fabrication of a novel array microscope for the first ultrarapid virtual slide processor (DMetrix DX-40 digital slide scanner). The array microscope optics consists of a stack of three 80-element 10 x 8-lenslet arrays, constituting a "lenslet array ensemble." The lenslet array ensemble is positioned over a glass slide. Uniquely shaped lenses in each of the lenslet arrays, arranged perpendicular to the glass slide constitute a single "miniaturized microscope." A high-pixel-density image sensor is attached to the top of the lenslet array ensemble. In operation, the lenslet array ensemble is transported by a motorized mechanism relative to the long axis of a glass slide. Each of the 80 miniaturized microscopes has a lateral field of view of 250 microns. The microscopes of each row of the array are offset from the microscopes in other rows. Scanning a glass slide with the array microscope produces seamless two-dimensional image data of the entire slide, that is, a virtual slide. The optical system has a numerical aperture of N.A.= 0.65, scans slides at a rate of 3 mm per second, and accrues up to 3,000 images per second from each of the 80 miniaturized microscopes. In the ultrarapid virtual slide processing cycle, the time for image acquisition takes 58 seconds for a 2.25 cm2 tissue section. An automatic slide loader enables the scanner to process up to 40 slides per hour without operator intervention. Slide scanning and image processing are done concurrently so that post-scan processing is eliminated. A virtual slide can be viewed over the Internet immediately after the scanning is complete. A validation study compared the diagnostic accuracy of pathologist case readers using array microscopy (with images viewed as virtual slides) and conventional light microscopy. Four senior pathologists diagnosed 30 breast surgical pathology cases each using both imaging modes, but on separate occasions. Of 120 case reads by array microscopy

  7. Using adaptive antenna array in LTE with MIMO for space-time processing

    Directory of Open Access Journals (Sweden)

    Abdourahamane Ahmed Ali

    2015-04-01

    Full Text Available The actual methods of improvement the existent wireless transmission systems are proposed. Mathematical apparatus is considered and proved by models, graph of which are shown, using the adaptive array antenna in LTE with MIMO for space-time processing. The results show that improvements, which are joined with space-time processing, positively reflects on LTE cell size or on throughput

  8. X-ray imaging sensor arrays on foil using solution processed organic photodiodes and organic transistors

    Science.gov (United States)

    Kumar, Abhishek; Moet, Date; van der Steen, Jan-Laurens; Tripathi, Ashutosh; Rodriguez, Francisco G.; Maas, Joris; Simon, Matthias; Reutten, Walter; Douglas, Alexander; Raaijmakers, Rob; Malinowski, Pawel E.; Myny, Kris; Shafique, Umar; Andriessen, Ronn; Heremans, Paul; Gelinck, Gerwin

    2014-05-01

    We demonstrate organic imaging sensor arrays fabricated on flexible plastic foil with the solution processing route for both photodiodes and thin film transistors. We used the photovoltaic P3HT:PCBM blend for fabricating the photodiodes using spin coating and pentacene as semiconductor material for the TFTs. Photodiodes fabricated with P3HT:PCBM absorb in the green part of the visible spectrum which matches with the typical scintillator output wavelength. The arrays consist of 32x32 pixels with variation in pixel resolution of 200μmx200μm, 300μmx300μm and of 1mmx1mm. The accurate reproducibility of shadow images of the objects demonstrates the potential of these arrays for imaging purposes. We also demonstrate that the crosstalk is relatively insignificant despite the fact that the active photodiode forms a continuous layer in the array. Since both photodiodes and TFTs are made of organic material, they are processed at low temperatures below 150°C on foil which means that these imaging sensors can be flexible, light weight and low cost when compared to conventional amorphous silicon based imaging sensors on rigid substrates. In combination with a scintillator on top of the arrays, we show the potential of these arrays for the X-ray imaging applications.

  9. Design, processing and testing of LSI arrays: Hybrid microelectronics task

    Science.gov (United States)

    Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.

    1979-01-01

    Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.

  10. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  11. Efficient Data Capture and Post-Processing for Real-Time Imaging Using AN Ultrasonic Array

    Science.gov (United States)

    Moreau, L.; Hunter, A. J.; Drinkwater, B. W.; Wilcox, P. D.

    2010-02-01

    Over the past few years, ultrasonic phased arrays have shown good potential for nondestructive testing (NDT), thanks to high resolution imaging algorithms. Many algorithms are based on the full matrix capture, obtained by firing each element of an ultrasonic array independently, and collecting the data with all elements. Because of the finite sound velocity in the specimen, two consecutive firings must be separated by a minimum time interval. Therefore, more array elements require longer data acquisition times. Moreover, if the array has N elements, then the full matrix contains N2 temporal signals to be processed. Because of the limited calculation speed of current computers, a large matrix of data can result in long post-processing times. In an industrial context where real-time imaging is desirable, it is crucial to reduce acquisition and/or post-processing times. This paper investigates methods designed to reduce acquisition and post-processing times for the total focusing method and wavenumber imaging algorithms. Limited transmission cycles are used to reduce data capture and post-processing. Post-processing times are further reduced by demodulating the data to temporal baseband frequencies. Results are presented so that a compromise can be made between acquisition time, post-processing time and image quality.

  12. Root crack sizing using phased array inspections and autoregressive spectral extrapolation signal processing

    Science.gov (United States)

    Caldwell, J.; Shakibi, B.; Moles, M.; Sinclair, A. N.

    2013-01-01

    Phased array inspection was conducted on a V-butt welded steel sample with multiple shallow flaws of varying depths. The inspection measurements were processed using Wiener filtering and Autoregressive Spectral Extrapolation (AS) to enhance the signals. Phased array inspections were conducted using multiple phased array probes of varying nominal central frequencies (2.25, 4, 5 and 10 MHz). This paper describes the measured results, which show high accuracy, typically in the range of 0.1-0.2 mm. The results concluded that: 1. There was no statistical difference between the calculated flaw depths from phased array inspections at different flaw tip angles. 2. There was no statistical difference in flaw depths calculated using phased array data collected from either side of the weld. 3. Flaws with depths less than the estimated probe signal shear wavelength could not be sized. 4. Finally, there was no statistical difference in the calculated flaw depths using phased array probes with different sampling frequencies and destructive measurements of the flaws.

  13. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  14. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  15. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  16. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  17. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  18. Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducer Arrays Using Glass Reflow Process

    Directory of Open Access Journals (Sweden)

    Nguyen Van Toan

    2016-04-01

    Full Text Available This paper presents a process for the fabrication of vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT arrays using glass reflow and anodic bonding techniques. Silicon through-wafer interconnects have been investigated by the glass reflow process. Then, the patterned silicon-glass reflow wafer is anodically bonded to an SOI (silicon-on-insulator wafer for the fabrication of CMUT devices. The CMUT 5 × 5 array has been successfully fabricated. The resonant frequency of the CMUT array with a one-cell radius of 100 µm and sensing gap of 3.2 µm (distance between top and bottom electrodes is observed at 2.84 MHz. The Q factor is approximately 1300 at pressure of 0.01 Pa.

  19. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  20. Assessment of Measurement Distortions in GNSS Antenna Array Space-Time Processing

    Directory of Open Access Journals (Sweden)

    Thyagaraja Marathe

    2016-01-01

    Full Text Available Antenna array processing techniques are studied in GNSS as effective tools to mitigate interference in spatial and spatiotemporal domains. However, without specific considerations, the array processing results in biases and distortions in the cross-ambiguity function (CAF of the ranging codes. In space-time processing (STP the CAF misshaping can happen due to the combined effect of space-time processing and the unintentional signal attenuation by filtering. This paper focuses on characterizing these degradations for different controlled signal scenarios and for live data from an antenna array. The antenna array simulation method introduced in this paper enables one to perform accurate analyses in the field of STP. The effects of relative placement of the interference source with respect to the desired signal direction are shown using overall measurement errors and profile of the signal strength. Analyses of contributions from each source of distortion are conducted individually and collectively. Effects of distortions on GNSS pseudorange errors and position errors are compared for blind, semi-distortionless, and distortionless beamforming methods. The results from characterization can be useful for designing low distortion filters that are especially important for high accuracy GNSS applications in challenging environments.

  1. Array Signal Processing Under Model Errors With Application to Speech Separation

    Science.gov (United States)

    1992-10-31

    Acoust. Speech Sig. Proc., pp. 1149-1152, Alburqueque NM, 1990. [37] E. A. Patrick , Fundamentals of Pattern Recognition, Englewood Cliffs, NJ, 1972...Proc., Toronto, pp. 1365-1368, 1991. [411 S. U. Pillai , Array Signal Processing, Springer Verlag, NY, 1989. [42] B. Porat and B. Friedlander

  2. Effects of process parameters on the molding quality of the micro-needle array

    Science.gov (United States)

    Qiu, Z. J.; Ma, Z.; Gao, S.

    2016-07-01

    Micro-needle array, which is used in medical applications, is a kind of typical injection molded products with microstructures. Due to its tiny micro-features size and high aspect ratios, it is more likely to produce short shots defects, leading to poor molding quality. The injection molding process of the micro-needle array was studied in this paper to find the effects of the process parameters on the molding quality of the micro-needle array and to provide theoretical guidance for practical production of high-quality products. With the shrinkage ratio and warpage of micro needles as the evaluation indices of the molding quality, the orthogonal experiment was conducted and the analysis of variance was carried out. According to the results, the contribution rates were calculated to determine the influence of various process parameters on molding quality. The single parameter method was used to analyse the main process parameter. It was found that the contribution rate of the holding pressure on shrinkage ratio and warpage reached 83.55% and 94.71% respectively, far higher than that of the other parameters. The study revealed that the holding pressure is the main factor which affects the molding quality of micro-needle array so that it should be focused on in order to obtain plastic parts with high quality in the practical production.

  3. An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

    Science.gov (United States)

    Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

    2010-01-01

    In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

  4. X-ray imaging sensor arrays on foil using solution processed organic photodiodes and organic transistors

    NARCIS (Netherlands)

    Kumar, A.; Moet, D.; Steen, J.L. van der; Tripathi, A.K.; Rodriguez, F.G.; Maas, J.; Simon, M.; Reutten, W.; Douglas, A.; Raaijmakers, R.; Malinowski, P.E.; Myny, K.; Shafique, U.; Andriessen, R.; Heremans, P.; Gelinck, G.H.

    2014-01-01

    We demonstrate organic imaging sensor arrays fabricated on flexible plastic foil with the solution processing route for both photodiodes and thin film transistors. We used the photovoltaic P3HT:PCBM blend for fabricating the photodiodes using spin coating and pentacene as semiconductor material for

  5. Fourier Array Processing for Buried Victims Detection using Ultra Wide Band Radar with Uncalibrated Sensors

    NARCIS (Netherlands)

    Lidicky, L.

    2008-01-01

    The purpose of this paper is to propose a new way to detect victims buried in or under layers of rubble or debris in case of disasters such as earthquakes, fires or terrorist attacks. The method is based on Fourier Processing and Principal Component Analysis (PCA). It utilizes a moving array of

  6. Assessment of low-cost manufacturing process sequences. [photovoltaic solar arrays

    Science.gov (United States)

    Chamberlain, R. G.

    1979-01-01

    An extensive research and development activity to reduce the cost of manufacturing photovoltaic solar arrays by a factor of approximately one hundred is discussed. Proposed and actual manufacturing process descriptions were compared to manufacturing costs. An overview of this methodology is presented.

  7. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  8. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  9. Assembly, integration, and verification (AIV) in ALMA: series processing of array elements

    Science.gov (United States)

    Lopez, Bernhard; Jager, Rieks; Whyborn, Nicholas D.; Knee, Lewis B. G.; McMullin, Joseph P.

    2012-09-01

    The Atacama Large Millimeter/submillimeter Array (ALMA) is a joint project between astronomical organizations in Europe, North America, and East Asia, in collaboration with the Republic of Chile. ALMA will consist of at least 54 twelve-meter antennas and 12 seven-meter antennas operating as an aperture synthesis array in the (sub)millimeter wavelength range. It is the responsibility of ALMA AIV to deliver the fully assembled, integrated, and verified antennas (array elements) to the telescope array. After an initial phase of infrastructure setup AIV activities began when the first ALMA antenna and subsystems became available in mid 2008. During the second semester of 2009 a project-wide effort was made to put in operation a first 3- antenna interferometer at the Array Operations Site (AOS). In 2010 the AIV focus was the transition from event-driven activities towards routine series production. Also, due to the ramp-up of operations activities, AIV underwent an organizational change from an autonomous department into a project within a strong matrix management structure. When the subsystem deliveries stabilized in early 2011, steady-state series processing could be achieved in an efficient and reliable manner. The challenge today is to maintain this production pace until completion towards the end of 2013. This paper describes the way ALMA AIV evolved successfully from the initial phase to the present steady-state of array element series processing. It elaborates on the different project phases and their relationships, presents processing statistics, illustrates the lessons learned and relevant best practices, and concludes with an outlook of the path towards completion.

  10. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  11. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  12. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  13. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  14. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  15. VLSI digital PSK demodulator for space communication

    Science.gov (United States)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  16. Enhancing four-wave-mixing processes by nanowire arrays coupled to a gold film.

    Science.gov (United States)

    Poutrina, Ekaterina; Ciracì, Cristian; Gauthier, Daniel J; Smith, David R

    2012-05-07

    We consider the process of four-wave mixing in an array of gold nanowires strongly coupled to a gold film. Using full-wave simulations, we perform a quantitative comparison of the four-wave mixing efficiency associated with a bare film and films with nanowire arrays. We find that the strongly localized surface plasmon resonances of the coupled nanowires provide an additional local field enhancement that, along with the delocalized surface plasmon of the film, produces an overall four-wave mixing efficiency enhancement of up to six orders of magnitude over that of the bare film. The enhancement occurs over a wide range of excitation angles. The film-coupled nanowire array is easily amenable to nanofabrication, and could find application as an ultra-compact component for integrated photonic and quantum optic systems.

  17. Applying Convolution-Based Processing Methods To A Dual-Channel, Large Array Artificial Olfactory Mucosa

    Science.gov (United States)

    Taylor, J. E.; Che Harun, F. K.; Covington, J. A.; Gardner, J. W.

    2009-05-01

    Our understanding of the human olfactory system, particularly with respect to the phenomenon of nasal chromatography, has led us to develop a new generation of novel odour-sensitive instruments (or electronic noses). This novel instrument is in need of new approaches to data processing so that the information rich signals can be fully exploited; here, we apply a novel time-series based technique for processing such data. The dual-channel, large array artificial olfactory mucosa consists of 3 arrays of 300 sensors each. The sensors are divided into 24 groups, with each group made from a particular type of polymer. The first array is connected to the other two arrays by a pair of retentive columns. One channel is coated with Carbowax 20 M, and the other with OV-1. This configuration partly mimics the nasal chromatography effect, and partly augments it by utilizing not only polar (mucus layer) but also non-polar (artificial) coatings. Such a device presents several challenges to multi-variate data processing: a large, redundant dataset, spatio-temporal output, and small sample space. By applying a novel convolution approach to this problem, it has been demonstrated that these problems can be overcome. The artificial mucosa signals have been classified using a probabilistic neural network and gave an accuracy of 85%. Even better results should be possible through the selection of other sensors with lower correlation.

  18. Sample processing for DNA chip array-based analysis of enterohemorrhagic Escherichia coli (EHEC

    Directory of Open Access Journals (Sweden)

    Enfors Sven-Olof

    2008-10-01

    Full Text Available Abstract Background Exploitation of DNA-based analyses of microbial pathogens, and especially simultaneous typing of several virulence-related genes in bacteria is becoming an important objective of public health these days. Results A procedure for sample processing for a confirmative analysis of enterohemorrhagic Escherichia coli (EHEC on a single colony with DNA chip array was developed and is reported here. The protocol includes application of fragmented genomic DNA from ultrasonicated colonies. The sample processing comprises first 2.5 min of ultrasonic treatment, DNA extraction (2×, and afterwards additional 5 min ultrasonication. Thus, the total sample preparation time for a confirmative analysis of EHEC is nearly 10 min. Additionally, bioinformatic revisions were performed in order to design PCR primers and array probes specific to most conservative regions of the EHEC-associated genes. Six strains with distinct pathogenic properties were selected for this study. At last, the EHEC chip array for a parallel and simultaneous detection of genes etpC-stx1-stx2-eae was designed and examined. This should permit to sense all currently accessible variants of the selected sequences in EHEC types and subtypes. Conclusion In order to implement the DNA chip array-based analysis for direct EHEC detection the sample processing was established in course of this work. However, this sample preparation mode may also be applied to other types of EHEC DNA-based sensing systems.

  19. Multiplexed optical operation of nanoelectromechanical systems (NEMS) arrays for sensing and signal-processing applications

    Science.gov (United States)

    Sampathkumar, Ashwin

    2014-06-01

    NEMS are rapidly being developed for a variety of sensing applications as well as for exploring interesting regimes in fundamental physics. In most of these endeavors, operation of a NEMS device involves actuating the device harmonically around its fundamental resonance and detecting subsequent motion while the device interacts with its environment. Even though a single NEMS resonator is exceptionally sensitive, a typical application, such as sensing or signal processing, requires the detection of signals from many resonators distributed over the surface of a chip. Therefore, one of the key technological challenges in the field of NEMS is development of multiplexed measurement techniques to detect the motion of a large number of NEMS resonators simultaneously. In this work, we address the important and difficult problem of interfacing with a large number of NEMS devices and facilitating the use of such arrays in, for example, sensing and signal processing applications. We report a versatile, all-optical technique to excite and read-out a distributed NEMS array. The NEMS array is driven by a distributed, intensity-modulated, optical pump through the photothermal effect. The ensuing vibrational response of the array is multiplexed onto a single, probe beam as a high-frequency phase modulation. The phase modulation is optically down converted to a low-frequency, intensity modulation using an adaptive full -field interferometer, and subsequently is detected using a charge-coupled device (CCD) array. Rapid and single-step mechanical characterization of approximately 60 nominally identical, high-frequency resonators is demonstrated. The technique may enable sensitivity improvements over single NEMS resonators by averaging signals coming from a multitude of devices in the array. In addition, the diffraction-limited spatial resolution may allow for position-dependent read-out of NEMS sensor chips for sensing multiple analytes or spatially inhomogeneous forces.

  20. An Opto-VLSI-based reconfigurable optical adddrop multiplexer employing an off-axis 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Ahderom, Selam; Alameh, Kamal

    2009-08-03

    A novel reconfigurable optical add-drop multiplexer (ROADM) structure is proposed and demonstrated experimentally. The ROADM structure employs two arrayed waveguide gratings (AWGs), an array of optical fiber pairs, an array of 4-f imaging microlenses that are offset in relation to the axis of symmetry of the fiber pairs, and a reconfigurable Opto-VLSI processor that switches various wavelength channels between the fiber pairs to achieve add or drop multiplexing. Experimental results are shown, which demonstrate the principle of add/drop multiplexing with crosstalk of less than -27dB and insertion loss of less than 8dB over the Cband for drop and through operation modes.

  1. Vector-Sensor Array Processing for Polarization Parameters and DOA Estimation

    Directory of Open Access Journals (Sweden)

    Paulus Caroline

    2010-01-01

    Full Text Available This paper presents a method allowing a complete characterization of wave signals received on a vector-sensor array. The proposed technique is based on wavefields separation processing and on estimation of fundamental waves attributes as the state of polarization state and the direction of arrival. Estimation of these attributes is an important step in data processing for a wide range of applications where vector sensor antennas technology is involved such as seismic processing, electromagnetic fields studies, and telecommunications. Compared to the classic techniques, the proposed method is based on computation of multicomponent wideband spectral matrices which enable to take into account all information given by the vector sensor array structures and thus provide a complete characterization of a larger number of sources.

  2. Direct Growth of Crystalline Tungsten Oxide Nanorod Arrays by a Hydrothermal Process and Their Electrochromic Properties

    Science.gov (United States)

    Lu, Chih-Hao; Hon, Min Hsiung; Leu, Ing-Chi

    2016-12-01

    Transparent crystalline tungsten oxide nanorod arrays for use as an electrochromic layer have been directly prepared on fluorine-doped tin oxide-coated glass via a facile tungsten film-assisted hydrothermal process using aqueous tungsten hexachloride solution. X-ray diffraction analysis and field-emission scanning electron microscopy were used to characterize the phase and morphology of the grown nanostructures. Arrays of tungsten oxide nanorods with diameter of ˜22 nm and length of ˜240 nm were obtained at 200°C after 8 h of hydrothermal reaction. We propose a growth mechanism for the deposition of the monoclinic tungsten oxide phase in the hydrothermal environment. The tungsten film was first oxidized to tungsten oxide to provide seed sites for crystal growth and address the poor connection between the growing tungsten oxide and substrate. Aligned tungsten oxide nanorod arrays can be grown by a W thin film-assisted heterogeneous nucleation process with NaCl as a structure-directing agent. The fabricated electrochromic device demonstrated optical modulation (coloration/bleaching) at 632.8 nm of ˜41.2% after applying a low voltage of 0.1 V for 10 s, indicating the potential of such nanorod array films for use in energy-saving smart windows.

  3. Direct Growth of Crystalline Tungsten Oxide Nanorod Arrays by a Hydrothermal Process and Their Electrochromic Properties

    Science.gov (United States)

    Lu, Chih-Hao; Hon, Min Hsiung; Leu, Ing-Chi

    2017-04-01

    Transparent crystalline tungsten oxide nanorod arrays for use as an electrochromic layer have been directly prepared on fluorine-doped tin oxide-coated glass via a facile tungsten film-assisted hydrothermal process using aqueous tungsten hexachloride solution. X-ray diffraction analysis and field-emission scanning electron microscopy were used to characterize the phase and morphology of the grown nanostructures. Arrays of tungsten oxide nanorods with diameter of ˜22 nm and length of ˜240 nm were obtained at 200°C after 8 h of hydrothermal reaction. We propose a growth mechanism for the deposition of the monoclinic tungsten oxide phase in the hydrothermal environment. The tungsten film was first oxidized to tungsten oxide to provide seed sites for crystal growth and address the poor connection between the growing tungsten oxide and substrate. Aligned tungsten oxide nanorod arrays can be grown by a W thin film-assisted heterogeneous nucleation process with NaCl as a structure-directing agent. The fabricated electrochromic device demonstrated optical modulation (coloration/bleaching) at 632.8 nm of ˜41.2% after applying a low voltage of 0.1 V for 10 s, indicating the potential of such nanorod array films for use in energy-saving smart windows.

  4. Whole-genome microarrays of fission yeast: characteristics, accuracy, reproducibility, and processing of array data

    Directory of Open Access Journals (Sweden)

    Chen Dongrong

    2003-07-01

    Full Text Available Abstract Background The genome of the fission yeast Schizosaccharomyces pombe has recently been sequenced, setting the stage for the post-genomic era of this increasingly popular model organism. We have built fission yeast microarrays, optimised protocols to improve array performance, and carried out experiments to assess various characteristics of microarrays. Results We designed PCR primers to amplify specific probes (180–500 bp for all known and predicted fission yeast genes, which are printed in duplicate onto separate regions of glass slides together with control elements (~13,000 spots/slide. Fluorescence signal intensities depended on the size and intragenic position of the array elements, whereas the signal ratios were largely independent of element properties. Only the coding strand is covalently linked to the slides, and our array elements can discriminate transcriptional direction. The microarrays can distinguish sequences with up to 70% identity, above which cross-hybridisation contributes to the signal intensity. We tested the accuracy of signal ratios and measured the reproducibility of array data caused by biological and technical factors. Because the technical variability is lower, it is best to use samples prepared from independent biological experiments to obtain repeated measurements with swapping of fluorochromes to prevent dye bias. We also developed a script that discards unreliable data and performs a normalization to correct spatial artefacts. Conclusions This paper provides data for several microarray properties that are rarely measured. The results define critical parameters for microarray design and experiments and provide a framework to optimise and interpret array data. Our arrays give reproducible and accurate expression ratios with high sensitivity. The scripts for primer design and initial data processing as well as primer sequences and detailed protocols are available from our website.

  5. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  6. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  7. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  8. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  9. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  10. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  11. Fabrication of hybrid nanostructured arrays using a PDMS/PDMS replication process.

    Science.gov (United States)

    Hassanin, H; Mohammadkhani, A; Jiang, K

    2012-10-21

    In the study, a novel and low cost nanofabrication process is proposed for producing hybrid polydimethylsiloxane (PDMS) nanostructured arrays. The proposed process involves monolayer self-assembly of polystyrene (PS) spheres, PDMS nanoreplication, thin film coating, and PDMS to PDMS (PDMS/PDMS) replication. A self-assembled monolayer of PS spheres is used as the first template. Second, a PDMS template is achieved by replica moulding. Third, the PDMS template is coated with a platinum or gold layer. Finally, a PDMS nanostructured array is developed by casting PDMS slurry on top of the coated PDMS. The cured PDMS is peeled off and used as a replica surface. In this study, the influences of the coating on the PDMS topography, contact angle of the PDMS slurry and the peeling off ability are discussed in detail. From experimental evaluation, a thickness of at least 20 nm gold layer or 40 nm platinum layer on the surface of the PDMS template improves the contact angle and eases peeling off. The coated PDMS surface is successfully used as a template to achieve the replica with a uniform array via PDMS/PDMS replication process. Both the PDMS template and the replica are free of defects and also undistorted after demoulding with a highly ordered hexagonal arrangement. In addition, the geometry of the nanostructured PDMS can be controlled by changing the thickness of the deposited layer. The simplicity and the controllability of the process show great promise as a robust nanoreplication method for functional applications.

  12. Low frequency ultrasonic array imaging using signal post-processing for concrete material

    Science.gov (United States)

    Ozawa, Akio; Izumi, Hideki; Nakahata, Kazuyuki; Ohira, Katsumi; Ogawa, Kenzo

    2017-02-01

    The use of ultrasonic arrays to conduct nondestructive evaluation has significantly increased in recent years. A post-processing beam-forming technique that utilizes a complete set of signals of all combinations of transmission and reception el-ements was proposed as an array imaging technique. In this study, a delay-and-sum beam reconstruction method utilizing post-processing was applied to the imaging of internal voids and reinforced steel bars in concrete material. Due to the high attenuation of the ultrasonic wave in concrete, it is necessary to use an ultrasonic wave as the incident wave at low frequencies and high in-tensities. In this study, an array transducer with a total of 16 elements was designed on the basis of a multigaussian beam model. The center frequency of the transducer was 50 kHz, and low frequency imaging was achieved by performing computations using a graphics processing unit accelerators in the post-processing beam formation. The results indicated that the shapes of through holes and steel bars in a concrete specimen with 700 mm height were reconstructed with high resolution.

  13. Effect of Source, Surfactant, and Deposition Process on Electronic Properties of Nanotube Arrays

    Directory of Open Access Journals (Sweden)

    Dheeraj Jain

    2011-01-01

    Full Text Available The electronic properties of arrays of carbon nanotubes from several different sources differing in the manufacturing process used with a variety of average properties such as length, diameter, and chirality are studied. We used several common surfactants to disperse each of these nanotubes and then deposited them on Si wafers from their aqueous solutions using dielectrophoresis. Transport measurements were performed to compare and determine the effect of different surfactants, deposition processes, and synthesis processes on nanotubes synthesized using CVD, CoMoCAT, laser ablation, and HiPCO.

  14. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  15. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  16. Subspace Dimensionality: A Tool for Automated QC in Seismic Array Processing

    Science.gov (United States)

    Rowe, C. A.; Stead, R. J.; Begnaud, M. L.

    2013-12-01

    Because of the great resolving power of seismic arrays, the application of automated processing to array data is critically important in treaty verification work. A significant problem in array analysis is the inclusion of bad sensor channels in the beamforming process. We are testing an approach to automated, on-the-fly quality control (QC) to aid in the identification of poorly performing sensor channels prior to beam-forming in routine event detection or location processing. The idea stems from methods used for large computer servers, when monitoring traffic at enormous numbers of nodes is impractical on a node-by node basis, so the dimensionality of the node traffic is instead monitoried for anomalies that could represent malware, cyber-attacks or other problems. The technique relies upon the use of subspace dimensionality or principal components of the overall system traffic. The subspace technique is not new to seismology, but its most common application has been limited to comparing waveforms to an a priori collection of templates for detecting highly similar events in a swarm or seismic cluster. In the established template application, a detector functions in a manner analogous to waveform cross-correlation, applying a statistical test to assess the similarity of the incoming data stream to known templates for events of interest. In our approach, we seek not to detect matching signals, but instead, we examine the signal subspace dimensionality in much the same way that the method addresses node traffic anomalies in large computer systems. Signal anomalies recorded on seismic arrays affect the dimensional structure of the array-wide time-series. We have shown previously that this observation is useful in identifying real seismic events, either by looking at the raw signal or derivatives thereof (entropy, kurtosis), but here we explore the effects of malfunctioning channels on the dimension of the data and its derivatives, and how to leverage this effect for

  17. Ultra-Fast Processing of Gigapixel Tissue MicroArray Images Using High Performance Computing

    OpenAIRE

    Yinhai Wang; David McCleary; Ching-Wei Wang; Paul Kelly; Jackie James; Fennell, Dean A; Peter Hamilton

    2010-01-01

    Background: Tissue MicroArrays (TMAs) are a valuable platform for tissue based translational research and the discovery of tissue biomarkers. The digitised TMA slides or TMA Virtual Slides, are ultra-large digital images, and can contain several hundred samples. The processing of such slides is time-consuming, bottlenecking a potentially high throughput platform. Methods: A High Performance Computing (HPC) platform for the rapid analysis of TMA virtual slides is presented in this study. Using...

  18. Signal Processing for Radar with Array Antennas and for Radar with Micro-Doppler Measurements

    OpenAIRE

    Björklund, Svante

    2017-01-01

    Radar (RAdio Detection And Ranging) uses radio waves to detect the presence of a target and measure its position and other properties. This sensor has found many civilian and military applications due to advantages such as possible large surveillance areas and operation day and night and in all weather. The contributions of this thesis are within applied signal processing for radar in two somewhat separate research areas: 1) radar with array antennas and 2) radar with micro-Doppler measuremen...

  19. Sample processing for DNA chip array-based analysis of enterohemorrhagic Escherichia coli (EHEC)

    OpenAIRE

    Enfors Sven-Olof; Wegrzyn Grzegorz; Basselet Pascal; Gabig-Ciminska Magdalena

    2008-01-01

    Abstract Background Exploitation of DNA-based analyses of microbial pathogens, and especially simultaneous typing of several virulence-related genes in bacteria is becoming an important objective of public health these days. Results A procedure for sample processing for a confirmative analysis of enterohemorrhagic Escherichia coli (EHEC) on a single colony with DNA chip array was developed and is reported here. The protocol includes application of fragmented genomic DNA from ultrasonicated co...

  20. Monitoring and evaluation of alcoholic fermentation processes using a chemocapacitor sensor array.

    Science.gov (United States)

    Oikonomou, Petros; Raptis, Ioannis; Sanopoulou, Merope

    2014-09-02

    The alcoholic fermentation of Savatiano must variety was initiated under laboratory conditions and monitored daily with a gas sensor array without any pre-treatment steps. The sensor array consisted of eight interdigitated chemocapacitors (IDCs) coated with specific polymers. Two batches of fermented must were tested and also subjected daily to standard chemical analysis. The chemical composition of the two fermenting musts differed from day one of laboratory monitoring (due to different storage conditions of the musts) and due to a deliberate increase of the acetic acid content of one of the musts, during the course of the process, in an effort to spoil the fermenting medium. Sensor array responses to the headspace of the fermenting medium were compared with those obtained either for pure or contaminated samples with controlled concentrations of standard ethanol solutions of impurities. Results of data processing with Principal Component Analysis (PCA), demonstrate that this sensing system could discriminate between a normal and a potential spoiled grape must fermentation process, so this gas sensing system could be potentially applied during wine production as an auxiliary qualitative control instrument.

  1. High density processing electronics for superconducting tunnel junction x-ray detector arrays

    Energy Technology Data Exchange (ETDEWEB)

    Warburton, W.K., E-mail: bill@xia.com [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Harris, J.T. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Friedrich, S. [Lawrence Livermore National Laboratory, Livermore, CA 94550 (United States)

    2015-06-01

    Superconducting tunnel junctions (STJs) are excellent soft x-ray (100–2000 eV) detectors, particularly for synchrotron applications, because of their ability to obtain energy resolutions below 10 eV at count rates approaching 10 kcps. In order to achieve useful solid detection angles with these very small detectors, they are typically deployed in large arrays – currently with 100+ elements, but with 1000 elements being contemplated. In this paper we review a 5-year effort to develop compact, computer controlled low-noise processing electronics for STJ detector arrays, focusing on the major issues encountered and our solutions to them. Of particular interest are our preamplifier design, which can set the STJ operating points under computer control and achieve 2.7 eV energy resolution; our low noise power supply, which produces only 2 nV/√Hz noise at the preamplifier's critical cascode node; our digital processing card that digitizes and digitally processes 32 channels; and an STJ I–V curve scanning algorithm that computes noise as a function of offset voltage, allowing an optimum operating point to be easily selected. With 32 preamplifiers laid out on a custom 3U EuroCard, and the 32 channel digital card in a 3U PXI card format, electronics for a 128 channel array occupy only two small chassis, each the size of a National Instruments 5-slot PXI crate, and allow full array control with simple extensions of existing beam line data collection packages.

  2. Structural control of ultra-fine CoPt nanodot arrays via electrodeposition process

    Science.gov (United States)

    Wodarz, Siggi; Hasegawa, Takashi; Ishio, Shunji; Homma, Takayuki

    2017-05-01

    CoPt nanodot arrays were fabricated by combining electrodeposition and electron beam lithography (EBL) for the use of bit-patterned media (BPM). To achieve precise control of deposition uniformity and coercivity of the CoPt nanodot arrays, their crystal structure and magnetic properties were controlled by controlling the diffusion state of metal ions from the initial deposition stage with the application of bath agitation. Following bath agitation, the composition gradient of the CoPt alloy with thickness was mitigated to have a near-ideal alloy composition of Co:Pt =80:20, which induces epitaxial-like growth from Ru substrate, thus resulting in the improvement of the crystal orientation of the hcp (002) structure from its initial deposition stages. Furthermore, the cross-sectional transmission electron microscope (TEM) analysis of the nanodots deposited with bath agitation showed CoPt growth along its c-axis oriented in the perpendicular direction, having uniform lattice fringes on the hcp (002) plane from the Ru underlayer interface, which is a significant factor to induce perpendicular magnetic anisotropy. Magnetic characterization of the CoPt nanodot arrays showed increase in the perpendicular coercivity and squareness of the hysteresis loops from 2.0 kOe and 0.64 (without agitation) to 4.0 kOe and 0.87 with bath agitation. Based on the detailed characterization of nanodot arrays, the precise crystal structure control of the nanodot arrays with ultra-high recording density by electrochemical process was successfully demonstrated.

  3. Sub-threshold signal processing in arrays of non-identical nanostructures.

    Science.gov (United States)

    Cervera, Javier; Manzanares, José A; Mafé, Salvador

    2011-10-28

    Weak input signals are routinely processed by molecular-scaled biological networks composed of non-identical units that operate correctly in a noisy environment. In order to show that artificial nanostructures can mimic this behavior, we explore theoretically noise-assisted signal processing in arrays of metallic nanoparticles functionalized with organic ligands that act as tunneling junctions connecting the nanoparticle to the external electrodes. The electronic transfer through the nanostructure is based on the Coulomb blockade and tunneling effects. Because of the fabrication uncertainties, these nanostructures are expected to show a high variability in their physical characteristics and a diversity-induced static noise should be considered together with the dynamic noise caused by thermal fluctuations. This static noise originates from the hardware variability and produces fluctuations in the threshold potential of the individual nanoparticles arranged in a parallel array. The correlation between different input (potential) and output (current) signals in the array is analyzed as a function of temperature, applied voltage, and the variability in the electrical properties of the nanostructures. Extensive kinetic Monte Carlo simulations with nanostructures whose basic properties have been demonstrated experimentally show that variability can enhance the correlation, even for the case of weak signals and high variability, provided that the signal is processed by a sufficiently high number of nanostructures. Moderate redundancy permits us not only to minimize the adverse effects of the hardware variability but also to take advantage of the nanoparticles' threshold fluctuations to increase the detection range at low temperatures. This conclusion holds for the average behavior of a moderately large statistical ensemble of non-identical nanostructures processing different types of input signals and suggests that variability could be beneficial for signal processing

  4. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  5. Grid Size Selection for Nonlinear Least-Squares Optimization in Spectral Estimation and Array Processing

    DEFF Research Database (Denmark)

    Nielsen, Jesper Kjær; Jensen, Tobias Lindstrøm; Jensen, Jesper Rindom;

    2016-01-01

    time. Additionally, we show via three common examples how the grid size depends on parameters such as the number of data points or the number of sensors in DOA estimation. We also demonstrate that the computation time can potentially be lowered by several orders of magnitude by combining a coarse grid......In many spectral estimation and array processing problems, the process of finding estimates of model parameters often involves the optimisation of a cost function containing multiple peaks and dips. Such non-convex problems are hard to solve using traditional optimisation algorithms developed...

  6. Increasing the specificity and function of DNA microarrays by processing arrays at different stringencies

    DEFF Research Database (Denmark)

    Dufva, Martin; Petersen, Jesper; Poulsen, Lena

    2009-01-01

    DNA microarrays have for a decade been the only platform for genome-wide analysis and have provided a wealth of information about living organisms. DNA microarrays are processed today under one condition only, which puts large demands on assay development because all probes on the array need...... to function optimally under one condition only. Microarrays are often burdened with a significant degree of cross-hybridization, because of a poor combination of assay conditions and probe choice. As reviewed here, a number of promising microfluidics-based technologies can provide automatic processing...

  7. Reversible Back-Propagation Imaging Algorithm for Post-Processing of Ultrasonic Array Data

    Science.gov (United States)

    Velichko, A.; Wilcox, P. D.

    2009-03-01

    The paper describes a method for processing data from an ultrasonic transducer array. The proposed algorithm is formulated in such a way that it is reversible, i.e. the raw data set can be recovered from the image. This is of practical significance because it allows the raw-data to be spatially filtered using the image to extract, for example, only the raw data associated with a particular reflector. The method is tested on experimental data obtained from a commercial 64-element, 5-MHZ array on an aluminium specimen that contains a number of machined slots and side-drilled holes. The raw transmitter-receiver data corresponded to each reflector is extracted and the scattering matrices of different reflectors are reconstructed. It allows the signals from 1-mm-long slot and a 1-mm-diameter hole to be clearly distinguished and the orientation and the size of the slots to be determined.

  8. Arrays of surface-normal electroabsorption modulators for the generation and signal processing of microwave photonics signals

    NARCIS (Netherlands)

    Noharet, Bertrand; Wang, Qin; Platt, Duncan; Junique, Stéphane; Marpaung, D.A.I.; Roeloffzen, C.G.H.

    2011-01-01

    The development of an array of 16 surface-normal electroabsorption modulators operating at 1550nm is presented. The modulator array is dedicated to the generation and processing of microwave photonics signals, targeting a modulation bandwidth in excess of 5GHz. The hybrid integration of the

  9. Process development for automated solar cell and module production. Task 4: automated array assembly

    Energy Technology Data Exchange (ETDEWEB)

    Hagerty, J.J.

    1980-06-30

    The scope of work under this contract involves specifying a process sequence which can be used in conjunction with automated equipment for the mass production of solar cell modules for terrestrial use. This process sequence is then critically analyzed from a technical and economic standpoint to determine the technological readiness of each process step for implementation. The process steps are ranked according to the degree of development effort required and according to their significance to the overall process. Under this contract the steps receiving analysis were: back contact metallization, automated cell array layup/interconnect, and module edge sealing. For automated layup/interconnect both hard automation and programmable automation (using an industrial robot) were studied. The programmable automation system was then selected for actual hardware development. Economic analysis using the SAMICS system has been performed during these studies to assure that development efforts have been directed towards the ultimate goal of price reduction. Details are given. (WHK)

  10. Rapid prototyping of biodegradable microneedle arrays by integrating CO2 laser processing and polymer molding

    Science.gov (United States)

    Tu, K. T.; Chung, C. K.

    2016-06-01

    An integrated technology of CO2 laser processing and polymer molding has been demonstrated for the rapid prototyping of biodegradable poly-lactic-co-glycolic acid (PLGA) microneedle arrays. Rapid and low-cost CO2 laser processing was used for the fabrication of a high-aspect-ratio microneedle master mold instead of conventional time-consuming and expensive photolithography and etching processes. It is crucial to use flexible polydimethylsiloxane (PDMS) to detach PLGA. However, the direct CO2 laser-ablated PDMS could generate poor surfaces with bulges, scorches, re-solidification and shrinkage. Here, we have combined the polymethyl methacrylate (PMMA) ablation and two-step PDMS casting process to form a PDMS female microneedle mold to eliminate the problem of direct ablation. A self-assembled monolayer polyethylene glycol was coated to prevent stiction between the two PDMS layers during the peeling-off step in the PDMS-to-PDMS replication. Then the PLGA microneedle array was successfully released by bending the second-cast PDMS mold with flexibility and hydrophobic property. The depth of the polymer microneedles can range from hundreds of micrometers to millimeters. It is linked to the PMMA pattern profile and can be adjusted by CO2 laser power and scanning speed. The proposed integration process is maskless, simple and low-cost for rapid prototyping with a reusable mold.

  11. In-TFT-Array-Process Micro Defect Inspection Using Nonlinear Principal Component Analysis

    Directory of Open Access Journals (Sweden)

    Zhi-Hao Kang

    2009-10-01

    Full Text Available Defect inspection plays a critical role in thin film transistor liquid crystal display (TFT-LCD manufacture, and has received much attention in the field of automatic optical inspection (AOI. Previously, most focus was put on the problems of macro-scale Mura-defect detection in cell process, but it has recently been found that the defects which substantially influence the yield rate of LCD panels are actually those in the TFT array process, which is the first process in TFT-LCD manufacturing. Defect inspection in TFT array process is therefore considered a difficult task. This paper presents a novel inspection scheme based on kernel principal component analysis (KPCA algorithm, which is a nonlinear version of the well-known PCA algorithm. The inspection scheme can not only detect the defects from the images captured from the surface of LCD panels, but also recognize the types of the detected defects automatically. Results, based on real images provided by a LCD manufacturer in Taiwan, indicate that the KPCA-based defect inspection scheme is able to achieve a defect detection rate of over 99% and a high defect classification rate of over 96% when the imbalanced support vector machine (ISVM with 2-norm soft margin is employed as the classifier. More importantly, the inspection time is less than 1 s per input image.

  12. Optoelectronic signal processing for phased-array antennas II; Proceedings of the Meeting, Los Angeles, CA, Jan. 16, 17, 1990

    Science.gov (United States)

    Hendrickson, Brian M.; Koepf, Gerhard A.

    Various papers on optoelectronic signal processing for phased-array antennas (PAAs) are presented. Individual topics addressed include: the dynamics of high-frequency lasers, an electrooptic phase modulator for PA applications, a laser mixer for microwave fiber optics, optical control of microwaves with III-V semiconductor optical waveguides, a high-dynamic-range modulator for microwave PAs, the high-modulation-rate potential of surface-emitter laser-diode arrays, an electrooptical switch for antenna beam steering, and adaptive PA radar processing using photorefractive crystals. Also discussed are an optical processor for array antenna beam shaping and steering, an integrated optical Butler matrix for beam forming in PAAs, an acoustooptic/photorefractive processor for adaptive antenna arrays, BER testing of fiber-optic data links for MMIC-based phased-array antennas, and the design of an optically controlled K(a)-band GaAs MMIC PAA.

  13. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  14. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  15. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  16. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  17. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  18. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  19. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  20. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  1. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  2. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  3. Evaluation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Array

    Science.gov (United States)

    Pang, Jackson; Liddicoat, Albert; Ralston, Jesse; Pingree, Paula

    2006-01-01

    The current implementation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays (TRIGA) is equipped with CFDP protocol and CCSDS Telemetry and Telecommand framing schemes to replace the CPU intensive software counterpart implementation for reliable deep space communication. We present the hardware/software co-design methodology used to accomplish high data rate throughput. The hardware CFDP protocol stack implementation is then compared against the two recent flight implementations. The results from our experiments show that TRIGA offers more than 3 orders of magnitude throughput improvement with less than one-tenth of the power consumption.

  4. An Evaluation of Signal Processing Tools for Improving Phased Array Ultrasonic Weld Inspection

    Energy Technology Data Exchange (ETDEWEB)

    Ramuhalli, Pradeep; Cinson, Anthony D.; Crawford, Susan L.; Harris, Robert V.; Diaz, Aaron A.; Anderson, Michael T.

    2011-03-24

    Cast austenitic stainless steel (CASS) commonly used in U.S. nuclear power plants is a coarse-grained, elastically anisotropic material. The coarse-grained nature of CASS makes ultrasonic inspection of in-service components difficult. Recently, low-frequency phased array ultrasound has emerged as a candidate for the CASS piping weld inspection. However, issues such as low signal-to-noise ratio and difficulty in discriminating between flaw and non-flaw signals remain. This paper discusses the evaluation of a number of signal processing algorithms for improving flaw detection in CASS materials. The full paper provides details of the algorithms being evaluated, along with preliminary results.

  5. Automatic Defect Detection for TFT-LCD Array Process Using Quasiconformal Kernel Support Vector Data Description

    Directory of Open Access Journals (Sweden)

    Yi-Hung Liu

    2011-09-01

    Full Text Available Defect detection has been considered an efficient way to increase the yield rate of panels in thin film transistor liquid crystal display (TFT-LCD manufacturing. In this study we focus on the array process since it is the first and key process in TFT-LCD manufacturing. Various defects occur in the array process, and some of them could cause great damage to the LCD panels. Thus, how to design a method that can robustly detect defects from the images captured from the surface of LCD panels has become crucial. Previously, support vector data description (SVDD has been successfully applied to LCD defect detection. However, its generalization performance is limited. In this paper, we propose a novel one-class machine learning method, called quasiconformal kernel SVDD (QK-SVDD to address this issue. The QK-SVDD can significantly improve generalization performance of the traditional SVDD by introducing the quasiconformal transformation into a predefined kernel. Experimental results, carried out on real LCD images provided by an LCD manufacturer in Taiwan, indicate that the proposed QK-SVDD not only obtains a high defect detection rate of 96%, but also greatly improves generalization performance of SVDD. The improvement has shown to be over 30%. In addition, results also show that the QK-SVDD defect detector is able to accomplish the task of defect detection on an LCD image within 60 ms.

  6. The Role of Water Vapor and Dissociative Recombination Processes in Solar Array Arc Initiation

    Science.gov (United States)

    Galofar, J.; Vayner, B.; Degroot, W.; Ferguson, D.

    2002-01-01

    Experimental plasma arc investigations involving the onset of arc initiation for a negatively biased solar array immersed in low-density plasma have been performed. Previous studies into the arc initiation process have shown that the most probable arcing sites tend to occur at the triple junction involving the conductor, dielectric and plasma. More recently our own experiments have led us to believe that water vapor is the main causal factor behind the arc initiation process. Assuming the main component of the expelled plasma cloud by weight is water, the fastest process available is dissociative recombination (H2O(+) + e(-) (goes to) H* + OH*). A model that agrees with the observed dependency of arc current pulse width on the square root of capacitance is presented. A 400 MHz digital storage scope and current probe was used to detect arcs at the triple junction of a solar array. Simultaneous measurements of the arc trigger pulse, the gate pulse, the arc current and the arc voltage were then obtained. Finally, a large number of measurements of individual arc spectra were obtained in very short time intervals, ranging from 10 to 30 microseconds, using a 1/4 a spectrometer coupled with a gated intensified CCD. The spectrometer was systematically tuned to obtain optical arc spectra over the entire wavelength range of 260 to 680 nanometers. All relevant atomic lines and molecular bands were then identified.

  7. Automatic defect detection for TFT-LCD array process using quasiconformal kernel support vector data description.

    Science.gov (United States)

    Liu, Yi-Hung; Chen, Yan-Jen

    2011-01-01

    Defect detection has been considered an efficient way to increase the yield rate of panels in thin film transistor liquid crystal display (TFT-LCD) manufacturing. In this study we focus on the array process since it is the first and key process in TFT-LCD manufacturing. Various defects occur in the array process, and some of them could cause great damage to the LCD panels. Thus, how to design a method that can robustly detect defects from the images captured from the surface of LCD panels has become crucial. Previously, support vector data description (SVDD) has been successfully applied to LCD defect detection. However, its generalization performance is limited. In this paper, we propose a novel one-class machine learning method, called quasiconformal kernel SVDD (QK-SVDD) to address this issue. The QK-SVDD can significantly improve generalization performance of the traditional SVDD by introducing the quasiconformal transformation into a predefined kernel. Experimental results, carried out on real LCD images provided by an LCD manufacturer in Taiwan, indicate that the proposed QK-SVDD not only obtains a high defect detection rate of 96%, but also greatly improves generalization performance of SVDD. The improvement has shown to be over 30%. In addition, results also show that the QK-SVDD defect detector is able to accomplish the task of defect detection on an LCD image within 60 ms.

  8. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  9. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  10. Fabrication of CoZn alloy nanowire arrays: Significant improvement in magnetic properties by annealing process

    Energy Technology Data Exchange (ETDEWEB)

    Koohbor, M. [Department of Physics, University of Kurdistan, Sanandaj (Iran, Islamic Republic of); Soltanian, S., E-mail: s.soltanian@gmail.com [Department of Physics, University of Kurdistan, Sanandaj (Iran, Islamic Republic of); Department of Electrical and Computer Engineering, University of British Columbia, Vancouver (Canada); Najafi, M. [Department of Physics, University of Kurdistan, Sanandaj (Iran, Islamic Republic of); Department of Physics, Hamadan University of Technology, Hamadan (Iran, Islamic Republic of); Servati, P. [Department of Electrical and Computer Engineering, University of British Columbia, Vancouver (Canada)

    2012-01-05

    Highlights: Black-Right-Pointing-Pointer Increasing the Zn concentration changes the structure of NWs from hcp to amorphous. Black-Right-Pointing-Pointer Increasing the Zn concentration significantly reduces the Hc value of NWs. Black-Right-Pointing-Pointer Magnetic properties of CoZn NWs can be significantly enhanced by appropriate annealing. Black-Right-Pointing-Pointer The pH of electrolyte has no significant effect on the properties of the NW arrays. Black-Right-Pointing-Pointer Deposition frequency has considerable effects on the magnetic properties of NWs. - Abstract: Highly ordered arrays of Co{sub 1-x}Zn{sub x} (0 {<=} x {<=} 0.74) nanowires (NWs) with diameters of {approx}35 nm and high length-to-diameter ratios (up to 150) were fabricated by co-electrodeposition of Co and Zn into pores of anodized aluminum oxide (AAO) templates. The Co and Zn contents of the NWs were adjusted by varying the ratio of Zn and Co ion concentrations in the electrolyte. The effect of the Zn content, electrodeposition conditions (frequency and pH) and annealing on the structural and magnetic properties (e.g., coercivity (Hc) and squareness (Sq)) of NW arrays were investigated using X-ray diffraction (XRD), scanning electron microscopy, electron diffraction, and alternating gradient force magnetometer (AGFM). XRD patterns reveal that an increase in the concentration of Zn ions of the electrolyte forces the hcp crystal structure of Co NWs to change into an amorphous phase, resulting in a significant reduction in Hc. It was found that the magnetic properties of NWs can be significantly improved by appropriate annealing process. The highest values for Hc (2050 Oe) and Sq (0.98) were obtained for NWs electrodeposited using 0.95/0.05 Co:Zn concentrations at 200 Hz and annealed at 575 Degree-Sign C. While the pH of electrolyte is found to have no significant effect on the structural and magnetic properties of the NW arrays, the electrodeposition frequency has considerable effects on

  11. VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.

    Science.gov (United States)

    Hoang, Linh; Yang, Zhi; Liu, Wentai

    2009-01-01

    An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.

  12. Analyzing VLSI component test results of a GenRad GR125 tester

    Science.gov (United States)

    Zulaica, D.; Lee, C.-H.

    1995-06-01

    The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.

  13. Sub-threshold signal processing in arrays of non-identical nanostructures

    Energy Technology Data Exchange (ETDEWEB)

    Cervera, Javier; Manzanares, Jose A; Mafe, Salvador, E-mail: Javier.Cervera@uv.es [Facultat de Fisica, Universitat de Valencia, E-46100 Burjassot (Spain)

    2011-10-28

    Weak input signals are routinely processed by molecular-scaled biological networks composed of non-identical units that operate correctly in a noisy environment. In order to show that artificial nanostructures can mimic this behavior, we explore theoretically noise-assisted signal processing in arrays of metallic nanoparticles functionalized with organic ligands that act as tunneling junctions connecting the nanoparticle to the external electrodes. The electronic transfer through the nanostructure is based on the Coulomb blockade and tunneling effects. Because of the fabrication uncertainties, these nanostructures are expected to show a high variability in their physical characteristics and a diversity-induced static noise should be considered together with the dynamic noise caused by thermal fluctuations. This static noise originates from the hardware variability and produces fluctuations in the threshold potential of the individual nanoparticles arranged in a parallel array. The correlation between different input (potential) and output (current) signals in the array is analyzed as a function of temperature, applied voltage, and the variability in the electrical properties of the nanostructures. Extensive kinetic Monte Carlo simulations with nanostructures whose basic properties have been demonstrated experimentally show that variability can enhance the correlation, even for the case of weak signals and high variability, provided that the signal is processed by a sufficiently high number of nanostructures. Moderate redundancy permits us not only to minimize the adverse effects of the hardware variability but also to take advantage of the nanoparticles' threshold fluctuations to increase the detection range at low temperatures. This conclusion holds for the average behavior of a moderately large statistical ensemble of non-identical nanostructures processing different types of input signals and suggests that variability could be beneficial for signal

  14. Post-Processing of the Full Matrix of Ultrasonic Transmit-Receive Array Data for Guided Wave Pipe Inspection

    Science.gov (United States)

    Velichko, A.; Wilcox, P. D.

    2009-03-01

    The paper describes a method for processing data from a guided wave transducer array on a pipe. The raw data set from such an array contains the full matrix of time-domain signals from each transmitter-receiver combination. It is shown that for certain configurations of an array the total focusing method can be applied which allows the array to be focused at every point on a pipe surface in both transmission and reception. The effect of array configuration parameters on the sensitivity of the proposed method to the random and coherent noise is discussed. Experimental results are presented using electromagnetic acoustic transducers (EMAT) for exciting and detecting the S0 Lamb wave mode in a 12 inch steel pipe at 200 kHz excitation frequency. The results show that using the imaging algorithm a 2-mm-diameter (0.08 wavelength) half-thickness hole can be detected.

  15. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  16. Parallel pipeline networking and signal processing with field-programmable gate arrays (FPGAs) and VCSEL-MSM smart pixels

    Science.gov (United States)

    Kuznia, C. B.; Sawchuk, Alexander A.; Zhang, Liping; Hoanca, Bogdan; Hong, Sunkwang; Min, Chris; Pansatiankul, Dhawat E.; Alpaslan, Zahir Y.

    2000-05-01

    We present a networking and signal processing architecture called Transpar-TR (Translucent Smart Pixel Array-Token- Ring) that utilizes smart pixel technology to perform 2D parallel optical data transfer between digital processing nodes. Transpar-TR moves data through the network in the form of 3D packets (2D spatial and 1D time). By utilizing many spatial parallel channels, Transpar-TR can achieve high throughput, low latency communication between nodes, even with each channel operating at moderate data rates. The 2D array of optical channels is created by an array of smart pixels, each with an optical input and optical output. Each smart pixel consists of two sections, an optical network interface and ALU-based processor with local memory. The optical network interface is responsible for transmitting and receiving optical data packets using a slotted token ring network protocol. The smart pixel array operates as a single-instruction multiple-data processor when processing data. The Transpar-TR network, consisting of networked smart pixel arrays, can perform pipelined parallel processing very efficiently on 2D data structures such as images and video. This paper discusses the Transpar-TR implementation in which each node is the printed circuit board integration of a VCSEL-MSM chip, a transimpedance receiver array chip and an FPGA chip.

  17. Fabricating process of hollow out-of-plane Ni microneedle arrays and properties of the integrated microfluidic device

    Science.gov (United States)

    Zhu, Jun; Cao, Ying; Wang, Hong; Li, Yigui; Chen, Xiang; Chen, Di

    2013-07-01

    Although microfluidic devices that integrate microfluidic chips with hollow out-of-plane microneedle arrays have many advantages in transdermal drug delivery applications, difficulties exist in their fabrication due to the special three-dimensional structures of hollow out-of-plane microneedles. A new, cost-effective process for the fabrication of a hollow out-of-plane Ni microneedle array is presented. The integration of PDMS microchips with the Ni hollow microneedle array and the properties of microfluidic devices are also presented. The integrated microfluidic devices provide a new approach for transdermal drug delivery.

  18. Accurate depth measurement of small surface-breaking cracks using an ultrasonic array post-processing technique

    OpenAIRE

    Felice, Maria; Velichko, Alexander; Wilcox, Paul D.

    2014-01-01

    In this paper, the half-skip configuration of the Total Focusing Method (TFM) is used to image and size surface-breaking cracks. The TFM is an ultrasonic array post-processing technique which is used to synthetically focus at every image point in a target region. This paper considers the case of inspecting for cracks which have initiated from the far surface of a parallel-sided sample using an array on the near surface. Typically, only direct ray paths between the array and image points are i...

  19. Analysis of Deep Drawing Process for Stainless Steel Micro-Channel Array.

    Science.gov (United States)

    Chen, Tsung-Chia; Lin, Jiang-Cheng; Lee, Rong-Mao

    2017-04-18

    The stainless steel bipolar plate has received much attention due to the cost of graphite bipolar plates. Since the micro-channel of bipolar plates plays the role of fuel flow field, electric connector and fuel sealing, an investigation of the deep drawing process for stainless steel micro-channel arrays is reported in this work. The updated Lagrangian formulation, degenerated shell finite element analysis, and the r-minimum rule have been employed to study the relationship between punch load and stroke, distributions of stress and strain, thickness variations and depth variations of individual micro-channel sections. A micro-channel array is practically formed, with a width and depth of a single micro-channel of 0.75 mm and 0.5 mm, respectively. Fractures were usually observed in the fillet corner of the micro-channel bottom. According to the experimental results, more attention should be devoted to the fillet dimension design of punch and die. A larger die fillet can lead to better formability and a reduction of the punch load. In addition, the micro-channel thickness and the fillet radius have to be taken into consideration at the same time. Finally, the punch load estimated by the unmodified metal forming equation is higher than that of experiments.

  20. Cascaded Multitype Interferences Suppression Method Using Sparse Representation and Array Processing for GNSS Receiver

    Directory of Open Access Journals (Sweden)

    Qiang Guo

    2017-01-01

    Full Text Available Interference suppression techniques have been intensively studied in nearly two decades due to their importance for maintaining the integrity and functionality of global navigation satellite system (GNSS. However, the interference suppression method applicable for the complex receiving environment in which there are multitype interfering signals has not been considered in most of the researches. To deal with this problem better, a cascaded multitype interferences suppression method using sparse representation and array processing is proposed. In the first stage, according to the sparsity of the narrowband and modulated wideband interference signals, a novel parallel multichannel signal interference suppression method based on matching pursuit (MP algorithm and a design strategy for the overcomplete dictionary are proposed to mitigate the interferences with sparse features. Then, the minimum power distortionless response (MPDR beamformer is employed in the second stage to suppress the residuary interferences (such as Gaussian noise interferences. Compared with existing algorithms, the proposed method can not only effectively suppress the interference arriving from the same direction with the desired signal and increase the Degree of Freedom (DoF of the array antenna, but also introduce no distortion into the navigation signal. The effectiveness of the proposed method is illustrated by theoretical analysis and several simulation results.

  1. Electricity from photovoltaic solar cells: Flat-Plate Solar Array Project final report. Volume V: Process development

    OpenAIRE

    Gallagher, B.; P. Alexander; D.Burger

    1986-01-01

    The Flat-Plate Solar Array (FSA) Project, funded by the U.S. Government and managed by the Jet Propulsion Laboratory, was formed in 1975 to develop the module/array technology needed to attain widespread terrestrial use of photovoltaics by 1985. To accomplish this, the FSA Project established and managed an Industry, University, and Federal Government Team to perform the needed research and development. The goal of the Process Development Area, as part of the FSA Project, was to develop ...

  2. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  3. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  4. Improving GPR Surveys Productivity by Array Technology and Fully Automated Processing

    Science.gov (United States)

    Morello, Marco; Ercoli, Emanuele; Mazzucchelli, Paolo; Cottino, Edoardo

    2016-04-01

    The realization of network infrastructures with lower environmental impact and the tendency to use digging technologies less invasive in terms of time and space of road occupation and restoration play a key-role in the development of communication networks. However, pre-existing buried utilities must be detected and located in the subsurface, to exploit the high productivity of modern digging apparatus. According to SUE quality level B+ both position and depth of subsurface utilities must be accurately estimated, demanding for 3D GPR surveys. In fact, the advantages of 3D GPR acquisitions (obtained either by multiple 2D recordings or by an antenna array) versus 2D acquisitions are well-known. Nonetheless, the amount of acquired data for such 3D acquisitions does not usually allow to complete processing and interpretation directly in field and in real-time, thus limiting the overall efficiency of the GPR acquisition. As an example, the "low impact mini-trench "technique (addressed in ITU - International Telecommunication Union - L.83 recommendation) requires that non-destructive mapping of buried services enhances its productivity to match the improvements of new digging equipment. Nowadays multi-antenna and multi-pass GPR acquisitions demand for new processing techniques that can obtain high quality subsurface images, taking full advantage of 3D data: the development of a fully automated and real-time 3D GPR processing system plays a key-role in overall optical network deployment profitability. Furthermore, currently available computing power suggests the feasibility of processing schemes that incorporate better focusing algorithms. A novel processing scheme, whose goal is the automated processing and detection of buried targets that can be applied in real-time to 3D GPR array systems, has been developed and fruitfully tested with two different GPR arrays (16 antennas, 900 MHz central frequency, and 34 antennas, 600 MHz central frequency). The proposed processing

  5. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  6. Integration of field emitter array and thin-film transistor using polycrystalline silicon process technology

    CERN Document Server

    Song, Y H; Kang, S Y; Park Jeong Man; Cho, K I

    1998-01-01

    We present the monolithic integration of a gated polycrystalline silicon field emitter array (poly-Si FEA) and a thin-film transistor(TFT) on an insulating substrate for active-matrix field emission displays (AMFEDs). The TFT was designed to have low off-state currents even at a high drain voltage. Amorphous silicon has been used as a starting material of the poly-Si FEA for improving surface smoothness and uniformity of the tips, and the gate holes have been formed by using an etch-back process. The integrated poly-Si TFT controlled electron emissions of the poly-Si FEA actively, resulting in great improvement in the emission reliability along with a low-voltage control, below 15 V, of field emission, The developed technology has potential applications in AMFEDs on glass substrates.

  7. A field-programmable analog array development platform for vestibular prosthesis signal processing.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela

    2013-06-01

    We report on a vestibular prosthesis signal processor realized using an experimental field programmable analog array (FPAA). Completing signal processing functions in the analog domain, the processor is designed to help replace a malfunctioning inner ear sensory organ, a semicircular canal. Relying on angular head motion detected by an inertial sensor, the signal processor maps angular velocity into meaningful control signals to drive a current stimulator. To demonstrate biphasic pulse control a 1 k Ω resistive load was placed across an H-bridge circuit. When connected to a 2.4 V supply, a biphasic current of 100 μA was maintained at stimulation frequencies from 50-350 Hz, pulsewidths from 25-400 μ sec, and interphase gaps ranging from 25-250 μsec.

  8. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  9. Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

  10. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  11. X-ray imager using solution processed organic transistor arrays and bulk heterojunction photodiodes on thin, flexible plastic substrate

    NARCIS (Netherlands)

    Gelinck, G.H.; Kumar, A.; Moet, D.; Steen, J.L. van der; Shafique, U.; Malinowski, P.E.; Myny, K.; Rand, B.P.; Simon, M.; Rütten, W.; Douglas, A.; Jorritsma, J.; Heremans, P.L.; Andriessen, H.A.J.M.

    2013-01-01

    We describe the fabrication and characterization of large-area active-matrix X-ray/photodetector array of high quality using organic photodiodes and organic transistors. All layers with the exception of the electrodes are solution processed. Because it is processed on a very thin plastic substrate o

  12. Vector computing oriented Array OLAP query processing tech-nique%向量计算Array OLAP查询处理技术

    Institute of Scientific and Technical Information of China (English)

    张宇; 张延松; 陈红; 王珊

    2015-01-01

    , the computing framework prefers a code efficient and scalable design for massive processing cores. This paper presents an in-memory analytical computing framework Array OLAP with array store and vector processing to simplify storage model and processing model. In Array OLAP, dimensions are normalized as vector based dimension filter. The fact table is normalized as measure attributes with multidimensional index. With multidimensional index computing, a multidimensional query is simplified as vector index scan on fact table and the measure expressions are aggregated. The normalized vector lookup and vector index scan are efficient in code execution, and the staged processing model is adaptive for different computing platforms by assigning processing stages to the most suitable platform. Moreover, Array OLAP is data warehouse schema aware design. The vector processing model is simple but efficient enough for the small and slow incremental dimensions. It illus-trates the Array OLAP framework in various platforms and evaluates the benchmark performance with state-of-the-art in-memory analytical databases. The experimental results show that Array OLAP outperforms other in-memory analytical engines and can be smoothly migrated to new hardware platform.

  13. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  14. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  15. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  16. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  17. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  18. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  19. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  20. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  1. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  2. Perforated nanocap array: Facile fabrication process and efficient surface enhanced Raman scattering with fluorescence suppression

    Institute of Scientific and Technical Information of China (English)

    Wang Jun; Huang Li-Qing; Tong Hui-Min; Zhai Li-Peng; Yuan Lin; Zhao Li-Hua; Zhang Wei-Wei

    2013-01-01

    Recently,individual reduced-symmetry metal nanostructures and their plasmonic properties have been studied extensively.However,little attention has been paid to the approach to fabricating ordered reduced-symmetry metal nanostructure arrays.In this paper,a novel perforated silver nanocap array with high surface-enhanced Raman scattering (SERS) activity and fluorescence suppression is reported.The array is fabricated by electron beam evaporating Ag onto the perforated barrier layer side of a hard anodization (HA) anodic aluminum oxide (AAO) template.The morphology and optical property of the perforated silver nanocap array are characterized by an atomic force microscope (AFM),a scanning electron microscope (SEM),and absorption spectra.The results of SERS measurements reveal that the perforated silver nanocap array offers high SERS activity and fluorescence suppression compared with an imperforated silver nanocap array.

  3. Feasibility study, software design, layout and simulation of a two-dimensional Fast Fourier Transform machine for use in optical array interferometry

    Science.gov (United States)

    Boriakoff, Valentin

    1994-01-01

    The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a time-domain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).

  4. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  5. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  6. Fabrication of an array-like freeform molding tool for UV-replication using a step and repeat process

    Science.gov (United States)

    Dunkel, J.; Wippermann, F.; Brückner, A.; Reimann, A.; Bräuer, A.

    2013-05-01

    Artificial compound eye cameras are a prominent approach of next generation wafer level cameras for consumer electronics due to their lower z-height compared to conventional single aperture objectives. In order to address low cost and high volume markets, their fabrication is based on a wafer level UV-replication process. The image quality of compound eye cameras can be increased significantly by the use of refractive freeform arrays (RFFA) instead of conventional microlens arrays. Therefore, we present the fabrication of a RFFA wafer level molding tool by a step and repeat process for the first time. The surface qualities of the fabricated structures were characterized with a white light interferometer.

  7. Dual Butterfly Match Filter VLSI Design

    Institute of Scientific and Technical Information of China (English)

    LIU Zhenyu; HAN Yueqiu

    2001-01-01

    Match filter is widely used in realtime signal processing, especially in Radar Signal Processing. This paper provides a novel ASIC design,which not only saves resource, but also improves thethroughput of the system. This ASIC is specially designed for Radar Pulse Compression. Certainly it canalso be used in other circumstances, such as FIR filter.

  8. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  9. The Earthscope USArray Array Network Facility (ANF): Evolution of Data Acquisition, Processing, and Storage Systems

    Science.gov (United States)

    Davis, G. A.; Battistuz, B.; Foley, S.; Vernon, F. L.; Eakins, J. A.

    2009-12-01

    Since April 2004 the Earthscope USArray Transportable Array (TA) network has grown to over 400 broadband seismic stations that stream multi-channel data in near real-time to the Array Network Facility in San Diego. In total, over 1.7 terabytes per year of 24-bit, 40 samples-per-second seismic and state of health data is recorded from the stations. The ANF provides analysts access to real-time and archived data, as well as state-of-health data, metadata, and interactive tools for station engineers and the public via a website. Additional processing and recovery of missing data from on-site recorders (balers) at the stations is performed before the final data is transmitted to the IRIS Data Management Center (DMC). Assembly of the final data set requires additional storage and processing capabilities to combine the real-time data with baler data. The infrastructure supporting these diverse computational and storage needs currently consists of twelve virtualized Sun Solaris Zones executing on nine physical server systems. The servers are protected against failure by redundant power, storage, and networking connections. Storage needs are provided by a hybrid iSCSI and Fiber Channel Storage Area Network (SAN) with access to over 40 terabytes of RAID 5 and 6 storage. Processing tasks are assigned to systems based on parallelization and floating-point calculation needs. On-site buffering at the data-loggers provide protection in case of short-term network or hardware problems, while backup acquisition systems at the San Diego Supercomputer Center and the DMC protect against catastrophic failure of the primary site. Configuration management and monitoring of these systems is accomplished with open-source (Cfengine, Nagios, Solaris Community Software) and commercial tools (Intermapper). In the evolution from a single server to multiple virtualized server instances, Sun Cluster software was evaluated and found to be unstable in our environment. Shared filesystem

  10. Investigation of Proposed Process Sequence for the Array Automated Assembly Task, Phase 2. [low cost silicon solar array fabrication

    Science.gov (United States)

    Mardesich, N.; Garcia, A.; Bunyan, S.; Pepe, A.

    1979-01-01

    The technological readiness of the proposed process sequence was reviewed. Process steps evaluated include: (1) plasma etching to establish a standard surface; (2) forming junctions by diffusion from an N-type polymeric spray-on source; (3) forming a p+ back contact by firing a screen printed aluminum paste; (4) forming screen printed front contacts after cleaning the back aluminum and removing the diffusion oxide; (5) cleaning the junction by a laser scribe operation; (6) forming an antireflection coating by baking a polymeric spray-on film; (7) ultrasonically tin padding the cells; and (8) assembling cell strings into solar circuits using ethylene vinyl acetate as an encapsulant and laminating medium.

  11. A fast processing route of aspheric polydimethylsiloxane lenses array (APLA) and optical characterization for smartphone microscopy

    Science.gov (United States)

    Fuh, Yiin-Kuen; Lai, Zheng-Hong

    2017-02-01

    A fast processing route of aspheric polydimethylsiloxane (PDMS) lenses array (APLA) is proposed via the combined effect of inverted gravitational and heat-assisted forces. The fabrication time can be dramatically reduced to 30 s, compared favorably to the traditional duration of 2 hours of repeated cycles of addition-curing processes. In this paper, a low-cost flexible lens can be fabricated by repeatedly depositing, inverting, curing a hanging transparent PDMS elastomer droplet on a previously deposited curved structure. Complex structures with aspheric curve features and various focal lengths can be successfully produced and the fabricated 4 types of APLA have various focal lengths in the range of 7.03 mm, 6.00 mm, 5.33 mm, and 4.43 mm, respectively. Empirically, a direct relationship between the PDMS volume and focal lengths of the lenses can be experimentally deducted. Using these fabricated APLA, an ordinary commercial smartphone camera can be easily transformed to a low-cost, portable digital microscopy (50×magnification) such that point of care diagnostic can be implemented pervasively.

  12. Array Processing and Fast Optimization Algorithms for Distorted Circular Contour Retrieval

    Directory of Open Access Journals (Sweden)

    Marot Julien

    2007-01-01

    Full Text Available A specific formalism for virtual signal generation permits to transpose an image processing problem to an array processing problem. The existing method for straight-line characterization relies on the estimation of orientations and offsets of expected lines. This estimation is performed thanks to a subspace-based algorithm called subspace-based line detection (SLIDE. In this paper, we propose to retrieve circular and nearly circular contours in images. We estimate the radius of circles and we extend the estimation of circles to the retrieval of circular-like distorted contours. For this purpose we develop a new model for virtual signal generation; we simulate a circular antenna, so that a high-resolution method can be employed for radius estimation. An optimization method permits to extend circle fitting to the segmentation of objects which have any shape. We evaluate the performances of the proposed methods, on hand-made and real-world images, and we compare them with generalized Hough transform (GHT and gradient vector flow (GVF.

  13. Biologically inspired large scale chemical sensor arrays and embedded data processing

    Science.gov (United States)

    Marco, S.; Gutiérrez-Gálvez, A.; Lansner, A.; Martinez, D.; Rospars, J. P.; Beccherelli, R.; Perera, A.; Pearce, T.; Vershure, P.; Persaud, K.

    2013-05-01

    Biological olfaction outperforms chemical instrumentation in specificity, response time, detection limit, coding capacity, time stability, robustness, size, power consumption, and portability. This biological function provides outstanding performance due, to a large extent, to the unique architecture of the olfactory pathway, which combines a high degree of redundancy, an efficient combinatorial coding along with unmatched chemical information processing mechanisms. The last decade has witnessed important advances in the understanding of the computational primitives underlying the functioning of the olfactory system. EU Funded Project NEUROCHEM (Bio-ICT-FET- 216916) has developed novel computing paradigms and biologically motivated artefacts for chemical sensing taking inspiration from the biological olfactory pathway. To demonstrate this approach, a biomimetic demonstrator has been built featuring a large scale sensor array (65K elements) in conducting polymer technology mimicking the olfactory receptor neuron layer, and abstracted biomimetic algorithms have been implemented in an embedded system that interfaces the chemical sensors. The embedded system integrates computational models of the main anatomic building blocks in the olfactory pathway: the olfactory bulb, and olfactory cortex in vertebrates (alternatively, antennal lobe and mushroom bodies in the insect). For implementation in the embedded processor an abstraction phase has been carried out in which their processing capabilities are captured by algorithmic solutions. Finally, the algorithmic models are tested with an odour robot with navigation capabilities in mixed chemical plumes

  14. A Sub-pixel Image Processing Algorithm of a Detector Based on Staring Focal Plane Array

    Institute of Scientific and Technical Information of China (English)

    LI Ya-qiong; JIN Wei-qi; XU Chao; WANG Xia

    2008-01-01

    Optical micro-scanning technology can be used to increase spatial resolution of many optical imaging systems, especially thermal imaging system. One of its key issues is relevant image processing algorithm. A fast reconstruction algo-rithm is proposed for two dimensional 2×2 micro-scanning based on the sub-pixel imaging and reconstruction principle of two-dimensional stating focal plane arrays (FPA). Specifically, three initialization methods are presented and implemented with the simulated data, their performances are compared according to image quality index . Experiment results show that, by the first initialization approach, tirnely over-sampled image can be accurately recovered, although special field diaphragm is needed. In the second initialization, the extrapolation approximation in obtaining reconstruction results is better than either bilinear interpolation or over-sampling reconstruction, without requiting any special process on system. The proposed algorithm has simple structure, low computational cost and can be realized in real-time. A high-resolution image can be obtained by low-resolution detectors. So, the algorithm has potential applications in visible light and infrared imaging area.

  15. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  16. VLSI for High-Speed Digital Signal Processing

    Science.gov (United States)

    1994-09-30

    GND K8 X[5] B4 GND F9 VDD K9 X[21 B5 Y[9] FlO out_clk K1O VDD B6 Y[6] FI1 phil-in K11 X[1] B7 Yf4] GI proc[1] LI GND B8 Y[21 G2 proc[O] L2 data[4] B9...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

  17. Astronomical data processing using SciQL, an SQL based query language for array data

    NARCIS (Netherlands)

    Y. Zhang; B. Scheers; M. Kersten; M. Ivanova; N. Nes

    2011-01-01

    SciQL (pronounced as ‘cycle’) is a novel SQL-based array query language for scientific applications with both tables and arrays as first class citizens. SciQL lowers the entrance fee of adopting relational DBMS (RDBMS) in scientific domains, because it includes functionality often only found in math

  18. Astronomical Data Processing Using SciQL, an SQL Based Query Language for Array Data

    NARCIS (Netherlands)

    Y. Zhang; B. Scheers; M. Kersten; M. Ivanova; N. Nes; P. Ballester; D. Egret; N.P.F. Lorente

    2012-01-01

    SciQL (pronounced as ‘cycle’) is a novel SQL-based array query language for scientific applications with both tables and arrays as first class citizens. SciQL lowers the entrance fee of adopting relational DBMS (RDBMS) in scientific domains, because it includes functionality often only found in math

  19. Error, reproducibility and sensitivity: a pipeline for data processing of Agilent oligonucleotide expression arrays

    Directory of Open Access Journals (Sweden)

    Posch Wilfried

    2010-06-01

    Full Text Available Abstract Background Expression microarrays are increasingly used to obtain large scale transcriptomic information on a wide range of biological samples. Nevertheless, there is still much debate on the best ways to process data, to design experiments and analyse the output. Furthermore, many of the more sophisticated mathematical approaches to data analysis in the literature remain inaccessible to much of the biological research community. In this study we examine ways of extracting and analysing a large data set obtained using the Agilent long oligonucleotide transcriptomics platform, applied to a set of human macrophage and dendritic cell samples. Results We describe and validate a series of data extraction, transformation and normalisation steps which are implemented via a new R function. Analysis of replicate normalised reference data demonstrate that intrarray variability is small (only around 2% of the mean log signal, while interarray variability from replicate array measurements has a standard deviation (SD of around 0.5 log2 units ( 6% of mean. The common practise of working with ratios of Cy5/Cy3 signal offers little further improvement in terms of reducing error. Comparison to expression data obtained using Arabidopsis samples demonstrates that the large number of genes in each sample showing a low level of transcription reflect the real complexity of the cellular transcriptome. Multidimensional scaling is used to show that the processed data identifies an underlying structure which reflect some of the key biological variables which define the data set. This structure is robust, allowing reliable comparison of samples collected over a number of years and collected by a variety of operators. Conclusions This study outlines a robust and easily implemented pipeline for extracting, transforming normalising and visualising transcriptomic array data from Agilent expression platform. The analysis is used to obtain quantitative estimates of

  20. Comparison of Frequency-Domain Array Methods for Studying Earthquake Rupture Process

    Science.gov (United States)

    Sheng, Y.; Yin, J.; Yao, H.

    2014-12-01

    Seismic array methods, in both time- and frequency- domains, have been widely used to study the rupture process and energy radiation of earthquakes. With better spatial resolution, the high-resolution frequency-domain methods, such as Multiple Signal Classification (MUSIC) (Schimdt, 1986; Meng et al., 2011) and the recently developed Compressive Sensing (CS) technique (Yao et al., 2011, 2013), are revealing new features of earthquake rupture processes. We have performed various tests on the methods of MUSIC, CS, minimum-variance distortionless response (MVDR) Beamforming and conventional Beamforming in order to better understand the advantages and features of these methods for studying earthquake rupture processes. We use the ricker wavelet to synthesize seismograms and use these frequency-domain techniques to relocate the synthetic sources we set, for instance, two sources separated in space but, their waveforms completely overlapping in the time domain. We also test the effects of the sliding window scheme on the recovery of a series of input sources, in particular, some artifacts that are caused by the sliding window scheme. Based on our tests, we find that CS, which is developed from the theory of sparsity inversion, has relatively high spatial resolution than the other frequency-domain methods and has better performance at lower frequencies. In high-frequency bands, MUSIC, as well as MVDR Beamforming, is more stable, especially in the multi-source situation. Meanwhile, CS tends to produce more artifacts when data have poor signal-to-noise ratio. Although these techniques can distinctly improve the spatial resolution, they still produce some artifacts along with the sliding of the time window. Furthermore, we propose a new method, which combines both the time-domain and frequency-domain techniques, to suppress these artifacts and obtain more reliable earthquake rupture images. Finally, we apply this new technique to study the 2013 Okhotsk deep mega earthquake

  1. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  2. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  3. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  4. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  5. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  6. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  7. High-resolution focal plane array IR detection modules and digital signal processing technologies at AIM

    Science.gov (United States)

    Cabanski, Wolfgang A.; Breiter, Rainer; Koch, R.; Mauk, Karl-Heinz; Rode, Werner; Ziegler, Johann; Eberhardt, Kurt; Oelmaier, Reinhard; Schneider, Harald; Walther, Martin

    2000-07-01

    Full video format focal plane array (FPA) modules with up to 640 X 512 pixels have been developed for high resolution imaging applications in either mercury cadmium telluride (MCT) mid wave (MWIR) infrared (IR) or platinum silicide (PtSi) and quantum well infrared photodetector (QWIP) technology as low cost alternatives to MCT for high performance IR imaging in the MWIR or long wave spectral band (LWIR). For the QWIP's, a new photovoltaic technology was introduced for improved NETD performance and higher dynamic range. MCT units provide fast frame rates > 100 Hz together with state of the art thermal resolution NETD rates of 30 - 60 Hz and provide thermal resolutions of NETD exchangeability of the units. New modular image processing hardware platforms and software for image visualization and nonuniformity correction including scene based self learning algorithms had to be developed to accomplish for the high data rates of up to 18 M pixels/s with 14-bit deep data, allowing to take into account nonlinear effects to access the full NETD by accurate reduction of residual fixed pattern noise. The main features of these modules are summarized together with measured performance data for long range detection systems with moderately fast to slow F-numbers like F/2.0 - F/3.5. An outlook shows most recent activities at AIM, heading for multicolor and faster frame rate detector modules based on MCT devices.

  8. Vlsi Implementation of Edge Detection for Images

    Directory of Open Access Journals (Sweden)

    T. Mahalakshmi

    2012-12-01

    Full Text Available Edge is the boundary between the image and its background. Edge detection in general is defined as the local maxima obtained from high pass filters, but an optimized edge detector should mark the edges with respect to luminance or brightness changes. It is easy to obtain them in software implementation but for hardware implementation there is an issue with percentage of accuracy and processing time. This study discusses various edge detection algorithms and proposes an optimized edge detector which provides the solution for mentioned above issue. Since FPGA provides practical solutions for most of the image processing problems, the proposed architecture has been developed using Matlab System generator. Experimental results show the accuracy of edge detected using proposed architecture.

  9. Simplified microprocessor design for VLSI control applications

    Science.gov (United States)

    Cameron, K.

    1991-01-01

    A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

  10. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  11. Solution-Processed Organic Thin-Film Transistor Array for Active-Matrix Organic Light-Emitting Diode

    Science.gov (United States)

    Harada, Chihiro; Hata, Takuya; Chuman, Takashi; Ishizuka, Shinichi; Yoshizawa, Atsushi

    2013-05-01

    We developed a 3-in. organic thin-film transistor (OTFT) array with an ink-jetted organic semiconductor. All layers except electrodes were fabricated by solution processes. The OTFT performed well without hysteresis, and the field-effect mobility in the saturation region was 0.45 cm2 V-1 s-1, the threshold voltage was 3.3 V, and the on/off current ratio was more than 106. We demonstrated a 3-in. active-matrix organic light-emitting diode (AMOLED) display driven by the OTFT array. The display could provide clear moving images. The peak luminance of the display was 170 cd/m2.

  12. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  13. Finite Field Arithmetic Architecture Based on Cellular Array

    Directory of Open Access Journals (Sweden)

    Kee-Won Kim

    2015-05-01

    Full Text Available Recently, various finite field arithmetic structures are introduced for VLSI circuit implementation on cryptosystems and error correcting codes. In this study, we present an efficient finite field arithmetic architecture based on cellular semi-systolic array for Montgomery multiplication by choosing a proper Montgomery factor which is highly suitable for the design on parallel structures. Therefore, our architecture has reduced a time complexity by 50% compared to typical architecture.

  14. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  15. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  16. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  17. Final Scientific Report, Integrated Seismic Event Detection and Location by Advanced Array Processing

    Energy Technology Data Exchange (ETDEWEB)

    Kvaerna, T.; Gibbons. S.J.; Ringdal, F; Harris, D.B.

    2007-01-30

    primarily the result of spurious identification and incorrect association of phases, and of excessive variability in estimates for the velocity and direction of incoming seismic phases. The mitigation of these causes has led to the development of two complimentary techniques for classifying seismic sources by testing detected signals under mutually exclusive event hypotheses. Both of these techniques require appropriate calibration data from the region to be monitored, and are therefore ideally suited to mining areas or other sites with recurring seismicity. The first such technique is a classification and location algorithm where a template is designed for each site being monitored which defines which phases should be observed, and at which times, for all available regional array stations. For each phase, the variability of measurements (primarily the azimuth and apparent velocity) from previous events is examined and it is determined which processing parameters (array configuration, data window length, frequency band) provide the most stable results. This allows us to define optimal diagnostic tests for subsequent occurrences of the phase in question. The calibration of templates for this project revealed significant results with major implications for seismic processing in both automatic and analyst reviewed contexts: • one or more fixed frequency bands should be chosen for each phase tested for. • the frequency band providing the most stable parameter estimates varies from site to site and a frequency band which provides optimal measurements for one site may give substantially worse measurements for a nearby site. • slowness corrections applied depend strongly on the frequency band chosen. • the frequency band providing the most stable estimates is often neither the band providing the greatest SNR nor the band providing the best array gain. For this reason, the automatic template location estimates provided here are frequently far better than those obtained by

  18. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  19. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  20. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  1. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  2. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  3. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  4. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  5. The Digital Signal Processing Platform for the Low Frequency Aperture Array: Preliminary Results on the Data Acquisition Unit

    Science.gov (United States)

    Naldi, Giovanni; Mattana, Andrea; Pastore, Sandro; Alderighi, Monica; Zarb Adami, Kristian; Schillirò, Francesco; Aminaei, Amin; Baker, Jeremy; Belli, Carolina; Comoretto, Gianni; Chiarucci, Simone; Chiello, Riccardo; D'Angelo, Sergio; Dalle Mura, Gabriele; De Marco, Andrea; Halsall, Rob; Magro, Alessio; Monari, Jader; Roberts, Matt; Perini, Federico; Poloni, Marco; Pupillo, Giuseppe; Rusticelli, Simone; Schiaffino, Marco; Zaccaro, Emanuele

    A signal processing hardware platform has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA). The processing board, called an Analog Digital Unit (ADU), is able to acquire and digitize broadband (up to 500MHz bandwidth) radio-frequency streams from 16 dual polarized antennas, channel the data streams and then combine them flexibly as part of a larger beamforming system. It is envisaged that there will be more than 8000 of these signal processing platforms in the first phase of the SKA, so particular attention has been devoted to ensure the design is low-cost and low-power. This paper describes the main features of the data acquisition unit of such a platform and presents preliminary results characterizing its performance.

  6. Simulation of Z-Pinch Processes of Nested Tungsten Wire-Array on Angara-5-1 Facility

    Institute of Scientific and Technical Information of China (English)

    NING Cheng; DING Ning; LIU Quan; YANG Zhen-Hua; FAN Wen-Bin; ZHANG Yang

    2006-01-01

    @@ Based on the hydrodynamic shell-on-shell collision model, the Z-pinch processes of nested tungsten wire-array in Sino-Russian joint experiments on Angara-5-1 facility are simulated by means of our one-dimensional threetemperature radiation magneto-hydrodynamic code. The results show the evolutions of x-ray radiation burst,implosion trajectories of interfaces, current transfer in inner and outer wire-array plasmas, and the temporal and spatial changes of magnetic field and current density in the process. About 20% of the total driven current is transferred into the inner wire-array plasma by convection and diffusion of magnetic field when the two shells are pinched closest. Compared to the measured x-ray power, the simulated full width at half maximum and time at the strongest radiation agree approximately with the measured values. It is also demonstrated in our simulation that the radiation of nested wire-array Z-pinch is enhanced. The effects of fluctuations of driven current on yields of x-ray are also investigated.

  7. Air shower registration algorithm and mathematical processing of showers with radio signal at the Yakutsk array

    CERN Document Server

    Petrov, I; Petrov, Z

    2013-01-01

    The paper describes the techniques and method of registration of air shower radio emission at the Yakutsk array of extensive air showers at a frequency of 32 MHz. At this stage, emission registration involves two set of antennas, the distance between them is 500m. One set involves 8 antennas, second - 4 antennas. The antennas are perpendicularly crossed dipoles with radiation pattern North South,West East and raised 1.5 m above the ground. Each set of antennas connected to an industrial PC. The registration requires one of two triggers. First trigger are generated by scintillation detectors of Yakutsk array. Scintillation detectors cover area of 12 km^2 and registers air showers with energy more than 10^17 eV. The second trigger is generated by Small Cherenkov Array that covers area of 1 km^2 and registers air showers with energy 10^15 - 5*10^17 eV. Small Cherenkov Array is part of Yakutsk array and involve Cherenkov detectors located at a distance of 50, 100, 250 m. For further selection we are using an addi...

  8. Structure and Process of Infrared Hot Electron Transistor Arrays

    Directory of Open Access Journals (Sweden)

    Richard Fu

    2012-05-01

    Full Text Available An infrared hot-electron transistor (IHET 5 × 8 array with a common base configuration that allows two-terminal readout integration was investigated and fabricated for the first time. The IHET structure provides a maximum factor of six in improvement in the photocurrent to dark current ratio compared to the basic quantum well infrared photodetector (QWIP, and hence it improved the array S/N ratio by the same factor. The study also showed for the first time that there is no electrical cross-talk among individual detectors, even though they share the same emitter and base contacts. Thus, the IHET structure is compatible with existing electronic readout circuits for photoconductors in producing sensitive focal plane arrays.

  9. Optical properties of electrochemically processed ZnO nanowire array in quasi-microgravity condition

    OpenAIRE

    2007-01-01

    Free standing ZnO (Zinc Oxide) nanowire array was successfully synthesized on ITO (Indium Tin Oxide)/FTO (Fluorine-doped Tin Oxide) substrate by template-free method in Zn(NO3)2 aqueous solutions. Two types of electrode configurations were employed in order to quantitatively examine the effect of gravitational strength on electrodeposited ZnO nanowire array: (a) a horizontal cathode surface facing downward over an anode (C/A) and (b) an anode over a cathode (A/C). The former configuration may...

  10. Application of bistable optical logic gate arrays to all-optical digital parallel processing

    Science.gov (United States)

    Walker, A. C.

    1986-05-01

    Arrays of bistable optical gates can form the basis of an all-optical digital parallel processor. Two classes of signal input geometry exist - on- and off-axis - and lead to distinctly different device characteristics. The optical implementation of multisignal fan-in to an array of intrinsically bistable optical gates using the more efficient off-axis option is discussed together with the construction of programmable read/write memories from optically bistable devices. Finally the design of a demonstration all-optical parallel processor incorporating these concepts is presented.

  11. Growth process and mechanism of a multi-walled carbon nanotube nest deposited on a silicon nanoporous pillar array

    Energy Technology Data Exchange (ETDEWEB)

    Jiang Weifen, E-mail: gingerwfj@yahoo.com.cn [Department of Mathematics and Information Science, North China Institute of Water Conservancy and Hydroelectric Power, No. 36 Beihuan Road, Zhengzhou 450011 (China); Jian Lv; Yang Xiaohui [Department of Mathematics and Information Science, North China Institute of Water Conservancy and Hydroelectric Power, No. 36 Beihuan Road, Zhengzhou 450011 (China); Li Xinjian [Department of Physics and Laboratory of Material Physics, Zhengzhou University, Zhengzhou 450052 (China)

    2010-03-01

    A large scale nest array of multi-walled carbon nanotubes (NACNTs) was grown on silicon nanoporous pillar array (Si-NPA) by thermal chemical vapor deposition. Through observing its macro/micromorphology and structure, ascertaining the catalyst component and its locations at different growth time by hiring field emission scanning electron microscopy, transmission electron microscopy (TEM), high-resolution TEM, and selected area electron diffraction, the growth process was deduced. Its thermal properties were also investigated by using a thermogravimetric analyzer. Our experiments demonstrated that the CNTs growth by means of root-growth mechanism at the initial growth stage, then a continuous growth process with its tip open is suggested, finally, a schematic growth model of NACNT/Si-NPA was presented.

  12. Design and characterization of a p+/n-well SPAD array in 150nm CMOS process.

    Science.gov (United States)

    Xu, Hesong; Pancheri, Lucio; Betta, Gian-Franco Dalla; Stoppa, David

    2017-05-29

    This paper reports on characterization results of a single-photon avalanche diode (SPAD) array in standard CMOS 150nm technology. The array is composed by 25 (5 × 5) SPADs, based on p(+)/n-well active junction along with a retrograde deep n-well guard ring. The square-shaped SPAD has a 10µm active diameter and 15.6µm pitch size, achieving a 39.9% array fill factor. Characterization results show a good breakdown voltage uniformity (40mV max-min) within each chip and 17mV/°C temperature coefficient. The median DCR is 0.4Hz/µm(2), and the afterpulsing probability is 0.85% for a dead time of 150ns at 3V excess bias voltage. The peak PDP is 31% at 450nm wavelength and a good uniformity (1.1% standard deviation) is observed for the array at 5V excess bias. The single SPADs exhibit a timing jitter of 52ps (FWHM) and 42ps (FWHM) under a 468-nm and a 831-nm laser, respectively. The crosstalk probability as a function of pixel-to-pixel distance and excess bias voltage is presented, and random telegraph signal (RTS) noise is also discussed in detail.

  13. Mathematical analysis of the real time array PCR (RTA PCR) process

    NARCIS (Netherlands)

    Dijksman J.F.; Pierik, A.

    2012-01-01

    Real Time Array PCR is a recently developed biochemical technique that measures amplification curves (like quantitative real time Polymerase Chain Reaction (qPCR)) of a multitude of different templates ina sample. It combines two different techniques to profit from theadvantages of both techniques,

  14. Mathematical analysis of the real time array PCR (RTA PCR) process

    NARCIS (Netherlands)

    Dijksman, Johan Frederik; Pierik, A.

    2012-01-01

    Real time array PCR (RTA PCR) is a recently developed biochemical technique that measures amplification curves (like with quantitative real time Polymerase Chain Reaction (qRT PCR)) of a multitude of different templates in a sample. It combines two different methods in order to profit from the

  15. Mathematical analysis of the real time array PCR (RTA PCR) process

    NARCIS (Netherlands)

    Dijksman J.F.; Pierik, A.

    2012-01-01

    Real Time Array PCR is a recently developed biochemical technique that measures amplification curves (like quantitative real time Polymerase Chain Reaction (qPCR)) of a multitude of different templates ina sample. It combines two different techniques to profit from theadvantages of both techniques,

  16. A NEW FABRICATION PROCESS FOR A FLEXIBLE SKIN WITH TEMPERATURE SENSOR ARRAY AND ITS APPLICATIONS

    Institute of Scientific and Technical Information of China (English)

    LEE Gwo-Bin; HUANG Fu-Chun; Lee Chia-Yen; Mian Jiun-Jih

    2004-01-01

    This paper reports a novel technique for fabrication of a flexible skin with a temperature sensor array (40 × 1 sensors). A simplified MEMS technology using platinum resistors as sensing materials, which are sandwiched between two polyimide layers as flexible substrates is developed. The two polyimide layers are deposited on top of a thin aluminum layer, which serves as a sacrificial layer such that the flexible skin can be released by metal etching and peeled off easily. The flexible skin with a temperature sensor array has a high mechanical flexibility and can be handily attached on a highly curved surface to detect tiny temperature distribution inside a small area. The sensor array shows a linear output and has a sensitivity of 7.SmV/℃ (prior to amplifiers) at a drive current of 1 mA. To demonstrate its applications, two examples have been demonstrated, including measurement of temperature distribution around a micro heater of a micro PCR (polymerase chain reaction) chip for DNA amplification and detection of separation point for flow over a circular cylinder. The development of the flexible skin with a temperature sensor array may be crucial for measuring temperature distribution on any curved surface in the fields of aerodynamics, space exploration, auto making and biomedical applications etc.

  17. Mathematical analysis of the real time array PCR (RTA PCR) process

    NARCIS (Netherlands)

    Dijksman, J.F.; Pierik, A.

    2012-01-01

    Real time array PCR (RTA PCR) is a recently developed biochemical technique that measures amplification curves (like with quantitative real time Polymerase Chain Reaction (qRT PCR)) of a multitude of different templates in a sample. It combines two different methods in order to profit from the adva

  18. Real-time data acquisition and parallel data processing solution for TJ-II Bolometer arrays diagnostic

    Energy Technology Data Exchange (ETDEWEB)

    Barrera, E. [Departamento de Sistemas Electronicos y de Control, Universidad Politecnica de Madrid, Crta. Valencia Km. 7, 28031 Madrid (Spain)]. E-mail: eduardo.barrera@upm.es; Ruiz, M. [Grupo de Investigacion en Instrumentacion y Acustica Aplicada, Universidad Politecnica de Madrid, Crta. Valencia Km. 7, 28031 Madrid (Spain); Lopez, S. [Departamento de Sistemas Electronicos y de Control, Universidad Politecnica de Madrid, Crta. Valencia Km. 7, 28031 Madrid (Spain); Machon, D. [Departamento de Sistemas Electronicos y de Control, Universidad Politecnica de Madrid, Crta. Valencia Km. 7, 28031 Madrid (Spain); Vega, J. [Asociacion EURATOM/CIEMAT para Fusion, 28040 Madrid (Spain); Ochando, M. [Asociacion EURATOM/CIEMAT para Fusion, 28040 Madrid (Spain)

    2006-07-15

    Maps of local plasma emissivity of TJ-II plasmas are determined using three-array cameras of silicon photodiodes (AXUV type from IRD). They have assigned the top and side ports of the same sector of the vacuum vessel. Each array consists of 20 unfiltered detectors. The signals from each of these detectors are the inputs to an iterative algorithm of tomographic reconstruction. Currently, these signals are acquired by a PXI standard system at approximately 50 kS/s, with 12 bits of resolution and are stored for off-line processing. A 0.5 s discharge generates 3 Mbytes of raw data. The algorithm's load exceeds the CPU capacity of the PXI system's controller in a continuous mode, making unfeasible to process the samples in parallel with their acquisition in a PXI standard system. A new architecture model has been developed, making possible to add one or several processing cards to a standard PXI system. With this model, it is possible to define how to distribute, in real-time, the data from all acquired signals in the system among the processing cards and the PXI controller. This way, by distributing the data processing among the system controller and two processing cards, the data processing can be done in parallel with the acquisition. Hence, this system configuration would be able to measure even in long pulse devices.

  19. Solid-state curved focal plane arrays

    Science.gov (United States)

    Nikzad, Shouleh (Inventor); Hoenk, Michael (Inventor); Jones, Todd (Inventor)

    2010-01-01

    The present invention relates to curved focal plane arrays. More specifically, the present invention relates to a system and method for making solid-state curved focal plane arrays from standard and high-purity devices that may be matched to a given optical system. There are two ways to make a curved focal plane arrays starting with the fully fabricated device. One way, is to thin the device and conform it to a curvature. A second way, is to back-illuminate a thick device without making a thinned membrane. The thick device is a special class of devices; for example devices fabricated with high purity silicon. One surface of the device (the non VLSI fabricated surface, also referred to as the back surface) can be polished to form a curved surface.

  20. AGV trace sensing and processing technology based on RGB color sensor array

    Science.gov (United States)

    Xu, Kebao; Zhu, Ping; Wang, Juncheng; Yun, Yuliang

    2009-05-01

    AGV(Automatic Guided Vehicle) is widely used in manufacturing factories, harbors, docks and logistics fields, because of its accurate automatic tracking. An AGV tracking method of detecting trace color based on RGB color sensor is provided here. DR, DG, DB values of trace color are obtained by color sensor, with which hue value denoting trace color characteristic can be calculated. Combined with graph theory algorithm, hue value can be used as a parameter for tracking deviation and branch identification to implement shortest path tracking. In addition, considering discreteness and uncertainty of single sensor in detecting trace information, sensor array is adopted for information fusion to achieve accurate tracking. Compared to tracking trace by single intensity sensor, AGV tracking based on RGB color sensor array has much better trace tracking and branch identification performances on complex roads.

  1. Process Study of Oceanic Responses to Typhoons Using Arrays of EM-APEX Floats and Moorings

    Science.gov (United States)

    2015-03-01

    Arrays of EM-APEX Floats and Moorings Ren-Chieh Lien Applied Physics Laboratory University of Washington 1013 NE 40th Street Seattle, Washington...Long-term observations of atmospheric forcing and upper oceanic conditions were made by moorings in the western Pacific Ocean, in collaboration with...of ITOP), subsurface temperature measurements on the moorings were transmitted via Iridium satellite, and one upward-looking 75-kHz Long Ranger ADCP

  2. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  3. Fabrication process responsible for fundamentally improving Silicon X-ray microcalorimeter arrays

    Energy Technology Data Exchange (ETDEWEB)

    Brekosky, R.P. E-mail: regis.brekosky@gsfc.nasa.gov; Allen, C.A.; Galeazzi, M.; Gygax, J.D.; Isenburg, H.; Kelley, R.L.; McCammon, D.; McClanahan, R.A.; Porter, F.S.; Stahle, C.K.; Szymkowiak, A.E

    2004-03-11

    We have developed an improved microcalorimeter array that will be used on the AstroE-2 satellite mission. The 6x6 array consists of a grid of 36 suspended pixels. Each 1.5 {mu}m thick pixel has an ion-implanted thermometer, four thermal links (support beams), and four X-ray absorber support tabs. Improvements in Silicon micro-machining capabilities and the availability of custom Silicon-on-Insulator (SOI) wafers has enabled us to precisely control pixel geometry, lead widths, and develop a more compact array. Knowing the silicon thickness, we can calculate a precise implant dose for the thermometer. Using a high-temperature anneal, we can uniformly diffuse the implant throughout the depth of the top layer of the SOI wafer. Defining the length, width, and thickness of the support beams, we can control the thermal conductance of the pixel. Advancements in polymer-photo resists have enabled us to develop a new absorber support tab attachment scheme resulting in more controlled heat dissipation from the absorber to the thermometer on the pixel. An overview of fabrication improvements focusing on these topics will be discussed.

  4. Research and development of low cost processes for integrated solar arrays. Final report, April 15, 1974--January 14, 1976

    Energy Technology Data Exchange (ETDEWEB)

    Graham, C.D.; Kulkarni, S.; Louis, E.

    1976-05-01

    Results of a program to study process routes leading to a low cost large area integrated silicon solar array manufacture for terrestrial applications are reported. Potential processes for the production of solar-grade silicon are evaluated from thermodynamic, economic, and technical feasibility points of view. Upgrading of the present arc-furnace process is found most favorable. Experimental studies of the Si/SiF/sub 4/ transport and purification process show considerable impurity removal and reasonable transport rates. Silicon deformation experiments indicate production of silicon sheet by rolling at 1350/sup 0/C is feasible. Significant recrystallization by strain-anneal technique has been observed. Experimental recrystallization studies using an electron beam line source are discussed. A maximum recrystallization velocity of approximately 9 m/hr is calculated for silicon sheet. A comparative process rating technique based on detailed cost analysis is presented.

  5. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  6. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  7. Deep sub-micron stud-via technology for superconductor VLSI circuits

    Science.gov (United States)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  8. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  9. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  10. An analog VLSI chip emulating polarization vision of Octopus retina.

    Science.gov (United States)

    Momeni, Massoud; Titus, Albert H

    2006-01-01

    Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

  11. A Spatiotemporal Indexing Approach for Efficient Processing of Big Array-Based Climate Data with MapReduce

    Science.gov (United States)

    Li, Zhenlong; Hu, Fei; Schnase, John L.; Duffy, Daniel Q.; Lee, Tsengdar; Bowen, Michael K.; Yang, Chaowei

    2016-01-01

    Climate observations and model simulations are producing vast amounts of array-based spatiotemporal data. Efficient processing of these data is essential for assessing global challenges such as climate change, natural disasters, and diseases. This is challenging not only because of the large data volume, but also because of the intrinsic high-dimensional nature of geoscience data. To tackle this challenge, we propose a spatiotemporal indexing approach to efficiently manage and process big climate data with MapReduce in a highly scalable environment. Using this approach, big climate data are directly stored in a Hadoop Distributed File System in its original, native file format. A spatiotemporal index is built to bridge the logical array-based data model and the physical data layout, which enables fast data retrieval when performing spatiotemporal queries. Based on the index, a data-partitioning algorithm is applied to enable MapReduce to achieve high data locality, as well as balancing the workload. The proposed indexing approach is evaluated using the National Aeronautics and Space Administration (NASA) Modern-Era Retrospective Analysis for Research and Applications (MERRA) climate reanalysis dataset. The experimental results show that the index can significantly accelerate querying and processing (10 speedup compared to the baseline test using the same computing cluster), while keeping the index-to-data ratio small (0.0328). The applicability of the indexing approach is demonstrated by a climate anomaly detection deployed on a NASA Hadoop cluster. This approach is also able to support efficient processing of general array-based spatiotemporal data in various geoscience domains without special configuration on a Hadoop cluster.

  12. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  13. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  14. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  15. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  16. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  17. Development of a floating point convolver (array processor) and integration into a computer system for the processing of seismic data

    Energy Technology Data Exchange (ETDEWEB)

    Meinicke, G.; Loeb, E.; M' Seddi, A.

    1979-11-01

    The development of a floating point convolver and its integration into a computer system for the processing of seismic data inevitably resulted in the development of an efficient Array Processor System (APS). The total project of a small efficient seismic processing system SSP-11 A with the host computer PDP 11/45 with integrated APS can be considered as a successful one. Seismic processes are carried out in floating point format by the APS and, thus, the basis for the Real Amplitude Processing is provided. Moreover, the efficiency of the system SSP-11 A, in the relation to SSP-11, can be doubled, with regard to the throughput of seismic data. Thus, in the new system SSP-11 A capacity for more sophisticated seismic programs is available. For decentralized operation the SSP-11 A is, as a minicomputer system, a real economical alternative to large computer systems. 7 figures.

  18. Real-time processing of fast-scan cyclic voltammetry (FSCV) data using a field-programmable gate array (FPGA).

    Science.gov (United States)

    Bozorgzadeh, Bardia; Covey, Daniel P; Heidenreich, Byron A; Garris, Paul A; Mohseni, Pedram

    2014-01-01

    This paper reports the hardware implementation of a digital signal processing (DSP) unit for real-time processing of data obtained by fast-scan cyclic voltammetry (FSCV) at a carbon-fiber microelectrode (CFM), an electrochemical transduction technique for high-resolution monitoring of brain neurochemistry. Implemented on a field-programmable gate array (FPGA), the DSP unit comprises a decimation filter and an embedded processor to process the oversampled FSCV data and obtain in real time a temporal profile of concentration variation along with a chemical signature to identify the target neurotransmitter. Interfaced with an integrated, FSCV-sensing front-end, the DSP unit can successfully process FSCV data obtained by bolus injection of dopamine in a flow cell as well as electrically evoked, transient dopamine release in the dorsal striatum of an anesthetized rat.

  19. A Novel Self-aligned and Maskless Process for Formation of Highly Uniform Arrays of Nanoholes and Nanopillars

    Directory of Open Access Journals (Sweden)

    Wu Wei

    2008-01-01

    Full Text Available AbstractFabrication of a large area of periodic structures with deep sub-wavelength features is required in many applications such as solar cells, photonic crystals, and artificial kidneys. We present a low-cost and high-throughput process for realization of 2D arrays of deep sub-wavelength features using a self-assembled monolayer of hexagonally close packed (HCP silica and polystyrene microspheres. This method utilizes the microspheres as super-lenses to fabricate nanohole and pillar arrays over large areas on conventional positive and negative photoresist, and with a high aspect ratio. The period and diameter of the holes and pillars formed with this technique can be controlled precisely and independently. We demonstrate that the method can produce HCP arrays of hole of sub-250 nm size using a conventional photolithography system with a broadband UV source centered at 400 nm. We also present our 3D FDTD modeling, which shows a good agreement with the experimental results.

  20. Sparse model inversion and processing of spatial frequency-domain electromagnetic induction sensor array data for improved landmine discrimination

    Science.gov (United States)

    Tantum, Stacy L.; Colwell, Kenneth A.; Scott, Waymond R.; Torrione, Peter A.; Collins, Leslie M.; Morton, Kenneth D.

    2013-06-01

    Frequency-domain electromagnetic induction (EMI) sensors have been shown to provide target signatures which enable discrimination of landmines from harmless clutter. In particular, frequency-domain EMI sensors are well-suited for target characterization by inverting a physics-based signal model. In many model-based signal processing paradigms, the target signatures can be decomposed into a weighted sum of parameterized basis functions, where the basis functions are intrinsic to the target under consideration and the associated weights are a function of the target sensor orientation. When sensor array data is available, the spatial diversity of the measured signals may provide more information for estimating the basis function parameters. After model inversion, the basis function parameters can form the foundation of model-based classification of the target as landmine or clutter. In this work, sparse model inversion of spatial frequency-domain EMI sensor array data followed by target classification using a statistical model is investigated. Results for data measured with a prototype frequency-domain EMI sensor at a standardized test site are presented. Preliminary results indicate that extracting physics-based features from spatial frequency-domain EMI sensor array data followed by statistical classification provides an effective approach for classifying targets as landmine or clutter.

  1. Light absorption processes and optimization of ZnO/CdTe core-shell nanowire arrays for nanostructured solar cells

    Science.gov (United States)

    Michallon, Jérôme; Bucci, Davide; Morand, Alain; Zanuccoli, Mauro; Consonni, Vincent; Kaminski-Cachopo, Anne

    2015-02-01

    The absorption processes of extremely thin absorber solar cells based on ZnO/CdTe core-shell nanowire (NW) arrays with square, hexagonal or triangular arrangements are investigated through systematic computations of the ideal short-circuit current density using three-dimensional rigorous coupled wave analysis. The geometrical dimensions are optimized for optically designing these solar cells: the optimal NW diameter, height and array period are of 200 ± 10 nm, 1-3 μm and 350-400 nm for the square arrangement with CdTe shell thickness of 40-60 nm. The effects of the CdTe shell thickness on the absorption of ZnO/CdTe NW arrays are revealed through the study of two optical key modes: the first one is confining the light into individual NWs, the second one is strongly interacting with the NW arrangement. It is also shown that the reflectivity of the substrate can improve Fabry-Perot resonances within the NWs: the ideal short-circuit current density is increased by 10% for the ZnO/fluorine-doped tin oxide (FTO)/ideal reflector as compared to the ZnO/FTO/glass substrate. Furthermore, the optimized square arrangement absorbs light more efficiently than both optimized hexagonal and triangular arrangements. Eventually, the enhancement factor of the ideal short-circuit current density is calculated as high as 1.72 with respect to planar layers, showing the high optical potentiality of ZnO/CdTe core-shell NW arrays.

  2. Light absorption processes and optimization of ZnO/CdTe core-shell nanowire arrays for nanostructured solar cells.

    Science.gov (United States)

    Michallon, Jérôme; Bucci, Davide; Morand, Alain; Zanuccoli, Mauro; Consonni, Vincent; Kaminski-Cachopo, Anne

    2015-02-20

    The absorption processes of extremely thin absorber solar cells based on ZnO/CdTe core-shell nanowire (NW) arrays with square, hexagonal or triangular arrangements are investigated through systematic computations of the ideal short-circuit current density using three-dimensional rigorous coupled wave analysis. The geometrical dimensions are optimized for optically designing these solar cells: the optimal NW diameter, height and array period are of 200 ± 10 nm, 1-3 μm and 350-400 nm for the square arrangement with CdTe shell thickness of 40-60 nm. The effects of the CdTe shell thickness on the absorption of ZnO/CdTe NW arrays are revealed through the study of two optical key modes: the first one is confining the light into individual NWs, the second one is strongly interacting with the NW arrangement. It is also shown that the reflectivity of the substrate can improve Fabry-Perot resonances within the NWs: the ideal short-circuit current density is increased by 10% for the ZnO/fluorine-doped tin oxide (FTO)/ideal reflector as compared to the ZnO/FTO/glass substrate. Furthermore, the optimized square arrangement absorbs light more efficiently than both optimized hexagonal and triangular arrangements. Eventually, the enhancement factor of the ideal short-circuit current density is calculated as high as 1.72 with respect to planar layers, showing the high optical potentiality of ZnO/CdTe core-shell NW arrays.

  3. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  4. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  5. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  6. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  7. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  8. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  9. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  10. Phonon processes in vertically aligned silicon nanowire arrays produced by low-cost all-solution galvanic displacement method

    Science.gov (United States)

    Banerjee, Debika; Trudeau, Charles; Gerlein, Luis Felipe; Cloutier, Sylvain G.

    2016-03-01

    The nanoscale engineering of silicon can significantly change its bulk optoelectronic properties to make it more favorable for device integration. Phonon process engineering is one way to enhance inter-band transitions in silicon's indirect band structure alignment. This paper demonstrates phonon localization at the tip of silicon nanowires fabricated by galvanic displacement using wet electroless chemical etching of a bulk silicon wafer. High-resolution Raman micro-spectroscopy reveals that such arrayed structures of silicon nanowires display phonon localization behaviors, which could help their integration into the future generations of nano-engineered silicon nanowire-based devices such as photodetectors and solar cells.

  11. Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Wei [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Choi, Yong, E-mail: ychoi.image@gmail.com [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Hong, Key Jo [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kang, Jihoon [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Jung, Jin Ho [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Huh, Youn Suk [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Lim, Hyun Keong; Kim, Sang Su [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kim, Byung-Tae [Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Chung, Yonghyun [Department of Radiological Science, Yonsei University College of Health Science, 234 Meaji, Heungup Wonju, Kangwon-Do 220-710 (Korea, Republic of)

    2012-02-01

    Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm) coupled 1:1 with LYSO scintillators (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm Multiplication-Sign 20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and

  12. Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

    Science.gov (United States)

    Hu, Wei; Choi, Yong; Hong, Key Jo; Kang, Jihoon; Jung, Jin Ho; Huh, Youn Suk; Lim, Hyun Keong; Kim, Sang Su; Kim, Byung-Tae; Chung, Yonghyun

    2012-02-01

    Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4×4 array, pixel size: 3 mm×3 mm) coupled 1:1 with LYSO scintillators (4×4 array, pixel size: 3 mm×3 mm×20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and then transferred to a host computer for coincidence sorting and image reconstruction. In order to

  13. Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

    Science.gov (United States)

    Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

    2004-06-01

    Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

  14. Signal processing of MEMS gyroscope arrays to improve accuracy using a 1st order Markov for rate signal modeling.

    Science.gov (United States)

    Jiang, Chengyu; Xue, Liang; Chang, Honglong; Yuan, Guangmin; Yuan, Weizheng

    2012-01-01

    This paper presents a signal processing technique to improve angular rate accuracy of the gyroscope by combining the outputs of an array of MEMS gyroscope. A mathematical model for the accuracy improvement was described and a Kalman filter (KF) was designed to obtain optimal rate estimates. Especially, the rate signal was modeled by a first-order Markov process instead of a random walk to improve overall performance. The accuracy of the combined rate signal and affecting factors were analyzed using a steady-state covariance. A system comprising a six-gyroscope array was developed to test the presented KF. Experimental tests proved that the presented model was effective at improving the gyroscope accuracy. The experimental results indicated that six identical gyroscopes with an ARW noise of 6.2 °/√h and a bias drift of 54.14 °/h could be combined into a rate signal with an ARW noise of 1.8 °/√h and a bias drift of 16.3 °/h, while the estimated rate signal by the random walk model has an ARW noise of 2.4 °/√h and a bias drift of 20.6 °/h. It revealed that both models could improve the angular rate accuracy and have a similar performance in static condition. In dynamic condition, the test results showed that the first-order Markov process model could reduce the dynamic errors 20% more than the random walk model.

  15. Direct fabrication of compound-eye microlens array on curved surfaces by a facile femtosecond laser enhanced wet etching process

    Science.gov (United States)

    Bian, Hao; Wei, Yang; Yang, Qing; Chen, Feng; Zhang, Fan; Du, Guangqing; Yong, Jiale; Hou, Xun

    2016-11-01

    We report a direct fabrication of an omnidirectional negative microlens array on a curved substrate by a femtosecond laser enhanced chemical etching process, which is utilized as a molding template for duplicating bioinspired compound eyes. The femtosecond laser treatment of the curved glass substrate employs a common x-y-z stage without rotating the sample surface perpendicular to the laser beam, and uniform, omnidirectional-aligned negative microlenses are generated after a hydrofluoric acid etching. Using the negative microlens array on the concave glass substrate as a molding template, we fabricate an artificial compound eye with 3000 positive microlenses of 95-μm diameter close-packed on a 5-mm polymer hemisphere. Compared to the transferring process, the negative microlenses directly fabricated on the curved mold by our method are distortion-free, and the duplicated artificial eye presents clear and uniform imaging capabilities. This work provides a facile and efficient route to the fabrication of microlenses on any curved substrates without complicated alignment and motion control processes, which has the potential for the development of new microlens-based devices and systems.

  16. Analysis of process parameter effect on DIBL in n-channel MOSFET device using L27 orthogonal array

    Science.gov (United States)

    Salehuddin, F.; Kaharudin, K. E.; Zain, A. S. M.; Yamin, A. K. Mat; Ahmad, I.

    2014-10-01

    In this research, the effect of the process parameters variation on drain induced barrier lowering (DIBL) was investigated. The fabrication of the transistor device was performed using TCAD simulator, consisting of ATHENA and ATLAS modules. These two modules were combined with Taguchi method to optimize the process parameters. The setting of process parameters was determined by using the orthogonal array of L27 in Taguchi Method. In NMOS device, the most dominant or significant factors for S/N Ratio are halo implant energy, S/D implant dose and S/D implant energy. Meanwhile, the S/N Ratio values of DIBL after the optimization approaches for array L27 is 29.42 dB. In L27 experiments, DIBL value for n-channel MOSFET device after optimizations approaches is +37.8 mV. The results obtained were satisfied to be small as expected. As conclusions, by setting up design of experiment with the Taguchi Method and TCAD simulator, the optimal solutions on DIBL for the robust design recipe of 32nm n-channel MOSFET device was successfully achieved.

  17. Primary Dendrite Array Morphology: Observations from Ground-based and Space Station Processed Samples

    Science.gov (United States)

    Tewari, Surendra; Rajamure, Ravi; Grugel, Richard; Erdmann, Robert; Poirier, David

    2012-01-01

    Influence of natural convection on primary dendrite array morphology during directional solidification is being investigated under a collaborative European Space Agency-NASA joint research program, "Microstructure Formation in Castings of Technical Alloys under Diffusive and Magnetically Controlled Convective Conditions (MICAST)". Two Aluminum-7 wt pct Silicon alloy samples, MICAST6 and MICAST7, were directionally solidified in microgravity on the International Space Station. Terrestrially grown dendritic monocrystal cylindrical samples were remelted and directionally solidified at 18 K/cm (MICAST6) and 28 K/cm (MICAST7). Directional solidification involved a growth speed step increase (MICAST6-from 5 to 50 micron/s) and a speed decrease (MICAST7-from 20 to 10 micron/s). Distribution and morphology of primary dendrites is currently being characterized in these samples, and also in samples solidified on earth under nominally similar thermal gradients and growth speeds. Primary dendrite spacing and trunk diameter measurements from this investigation will be presented.

  18. Primary Dendrite Array: Observations from Ground-Based and Space Station Processed Samples

    Science.gov (United States)

    Tewari, Surendra N.; Grugel, Richard N.; Erdman, Robert G.; Poirier, David R.

    2012-01-01

    Influence of natural convection on primary dendrite array morphology during directional solidification is being investigated under a collaborative European Space Agency-NASA joint research program, Microstructure Formation in Castings of Technical Alloys under Diffusive and Magnetically Controlled Convective Conditions (MICAST). Two Aluminum-7 wt pct Silicon alloy samples, MICAST6 and MICAST7, were directionally solidified in microgravity on the International Space Station. Terrestrially grown dendritic monocrystal cylindrical samples were remelted and directionally solidified at 18 K per centimeter (MICAST6) and 28 K per centimeter (MICAST7). Directional solidification involved a growth speed step increase (MICAST6-from 5 to 50 millimeters per second) and a speed decrease (MICAST7-from 20 to 10 millimeters per second). Distribution and morphology of primary dendrites is currently being characterized in these samples, and also in samples solidified on earth under nominally similar thermal gradients and growth speeds. Primary dendrite spacing and trunk diameter measurements from this investigation will be presented.

  19. Scalable stacked array piezoelectric deformable mirror for astronomy and laser processing applications.

    Science.gov (United States)

    Wlodarczyk, Krystian L; Bryce, Emma; Schwartz, Noah; Strachan, Mel; Hutson, David; Maier, Robert R J; Atkinson, David; Beard, Steven; Baillie, Tom; Parr-Burman, Phil; Kirk, Katherine; Hand, Duncan P

    2014-02-01

    A prototype of a scalable and potentially low-cost stacked array piezoelectric deformable mirror (SA-PDM) with 35 active elements is presented in this paper. This prototype is characterized by a 2 μm maximum actuator stroke, a 1.4 μm mirror sag (measured for a 14 mm × 14 mm area of the unpowered SA-PDM), and a ±200 nm hysteresis error. The initial proof of concept experiments described here show that this mirror can be successfully used for shaping a high power laser beam in order to improve laser machining performance. Various beam shapes have been obtained with the SA-PDM and examples of laser machining with the shaped beams are presented.

  20. From Spin Noise to Systematics: Stochastic Processes in the First International Pulsar Timing Array Data Release

    CERN Document Server

    Lentati, L; Coles, W A; Verbiest, J P W; van Haasteren, R; Ellis, J A; Caballero, R N; Manchester, R N; Arzoumanian, Z; Babak, S; Bassa, C G; Bhat, N D R; Brem, P; Burgay, M; Burke-Spolaor, S; Champion, D; Chatterjee, S; Cognard, I; Cordes, J M; Dai, S; Demorest, P; Desvignes, G; Dolch, T; Ferdman, R D; Fonseca, E; Gair, J R; Gonzalez, M E; Graikou, E; Guillemot, L; Hessels, J W T; Hobbs, G; Janssen, G H; Jones, G; Karuppusamy, R; Keith, M; Kerr, M; Kramer, M; Lam, M T; Lasky, P D; Lassus, A; Lazarus, P; Lazio, T J W; Lee, K J; Levin, L; Liu, K; Lynch, R S; Madison, D R; McKee, J; McLaughlin, M; McWilliams, S T; Mingarelli, C M F; Nice, D J; Osłowski, S; Pennucci, T T; Perera, B B P; Perrodin, D; Petiteau, A; Possenti, A; Ransom, S M; Reardon, D; Rosado, P A; Sanidas, S A; Sesana, A; Shaifullah, G; Siemens, X; Smits, R; Stairs, I; Stappers, B; Stinebring, D R; Stovall, K; Swiggum, J; Taylor, S R; Theureau, G; Tiburzi, C; Toomey, L; Vallisneri, M; van Straten, W; Vecchio, A; Wang, J -B; Wang, Y; You, X P; Zhu, W W; Zhu, X -J

    2016-01-01

    We analyse the stochastic properties of the 49 pulsars that comprise the first International Pulsar Timing Array (IPTA) data release. We use Bayesian methodology, performing model selection to determine the optimal description of the stochastic signals present in each pulsar. In addition to spin-noise and dispersion-measure (DM) variations, these models can include timing noise unique to a single observing system, or frequency band. We show the improved radio-frequency coverage and presence of overlapping data from different observing systems in the IPTA data set enables us to separate both system and band-dependent effects with much greater efficacy than in the individual PTA data sets. For example, we show that PSR J1643$-$1224 has, in addition to DM variations, significant band-dependent noise that is coherent between PTAs which we interpret as coming from time-variable scattering or refraction in the ionised interstellar medium. Failing to model these different contributions appropriately can dramatically...

  1. A High Performance Backend for Array-Oriented Programming on Next-Generation Processing Units

    DEFF Research Database (Denmark)

    Lund, Simon Andreas Frimann

    and the efficient execution of them on high performance systems. This work investigates the requirements for, and the implementation of, a high performance backend supporting these goals. This involves an outline of the hardware available today, in the near future and how to program it for high performance......The financial crisis, which started in 2008, spawned the HIPERFIT research center as a preventive measure against future financial crises. The goal of prevention is to be met by improving mathematical models for finance, the verifiable description of them in domain-specific languages....... The main challenge is to bridge the gaps between performance, productivity and portability. A declarative high-level array-oriented programming model is explored to achieve this goal and a backend implemented to support it. Different strategies to the backend design and application of optimizations...

  2. Design and Evaluation of Fault-Tolerant VLSI/WSI Processor Arrays.

    Science.gov (United States)

    1987-12-31

    way that production quantitiis. However, the -arR-- adata item is not only used when it is input advantages of this technology are nut fully FIR, IIR...rla’lt fP i m iodhile is r , -aIict i tn o’ raftlier low% wh~en N i. very big . ’lf’s i 𔃾n -V4let2t Ito Ill’ statement thlat, regardless of the relia

  3. Runtimes for tests of array-processing speed: Factorial tests using C and C++ under Windows and Linux

    Science.gov (United States)

    Donato, David I.

    2017-01-01

    The dataset is provided as a .zip archive containing two .csv data files. These two data files contain the results of a series of timing runs made with a suite of 28 C test programs and 20 C++ test programs using three different computers and two operating systems (Windows and Linux). All 48 test programs carry out processing of two-dimensional arrays. One of the files, "C_CppTimeTestsAllRecords.csv", contains three replicated times for each of 960 combinations of factor levels that potentially might have affected the time required to process two-dimensional arrays. The other file, "C_CppTimeTestsAverages.csv", contains the average of the three replicated times for each of the 960 combinations of factor levels. Both files have the same column headers and data formats, and the meaning of the data fields (columns) is the same in both files, with one exception. The exception is that the file for all records contains actual runtimes (in seconds) in the "ProcTime" field, whereas the other file contains averaged runtimes in the "ProcTime" field.

  4. Sequential growth of zinc oxide nanorod arrays at room temperature via a corrosion process: application in visible light photocatalysis.

    Science.gov (United States)

    Iqbal, Danish; Kostka, Aleksander; Bashir, Asif; Sarfraz, Adnan; Chen, Ying; Wieck, Andreas D; Erbe, Andreas

    2014-11-12

    Many photocatalyst systems catalyze chemical reactions under ultraviolet (UV) illumination, because of its high photon energies. Activating inexpensive, widely available materials as photocatalyst using the intense visible part of the solar spectrum is more challenging. Here, nanorod arrays of the wide-band-gap semiconductor zinc oxide have been shown to act as photocatalysts for the aerobic photo-oxidation of organic dye Methyl Orange under illumination with red light, which is normally accessible only to narrow-band semiconductors. The homogeneous, 800-1000-nm-thick ZnO nanorod arrays show substantial light absorption (absorbances >1) throughout the visible spectral range. This absorption is caused by defect levels inside the band gap. Multiple scattering processes by the rods make the nanorods appear black. The dominantly crystalline ZnO nanorod structures grow in the (0001) direction, i.e., with the c-axis perpendicular to the surface of polycrystalline zinc. The room-temperature preparation route relies on controlled cathodic delamination of a weakly bound polymer coating from metallic zinc, an industrially produced and cheaply available substrate. Cathodic delamination is a sequential synthesis process, because it involves the propagation of a delamination front over the base material. Consequently, arbitrarily large sample surfaces can be nanostructured using this approach.

  5. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  6. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  7. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  8. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  9. Low cost solar array project production process and equipment task. A Module Experimental Process System Development Unit (MEPSDU)

    Science.gov (United States)

    1981-01-01

    Technical readiness for the production of photovoltaic modules using single crystal silicon dendritic web sheet material is demonstrated by: (1) selection, design and implementation of solar cell and photovoltaic module process sequence in a Module Experimental Process System Development Unit; (2) demonstration runs; (3) passing of acceptance and qualification tests; and (4) achievement of a cost effective module.

  10. Focal plane array with modular pixel array components for scalability

    Energy Technology Data Exchange (ETDEWEB)

    Kay, Randolph R; Campbell, David V; Shinde, Subhash L; Rienstra, Jeffrey L; Serkland, Darwin K; Holmes, Michael L

    2014-12-09

    A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.

  11. Elastomeric inverse moulding and vacuum casting process characterization for the fabrication of arrays of concave refractive microlenses

    Science.gov (United States)

    Desmet, L.; Van Overmeire, S.; Van Erps, J.; Ottevaere, H.; Debaes, C.; Thienpont, H.

    2007-01-01

    We present a complete and precise quantitative characterization of the different process steps used in an elastomeric inverse moulding and vacuum casting technique. We use the latter replication technique to fabricate concave replicas from an array of convex thermal reflow microlenses. During the inverse elastomeric moulding we obtain a secondary silicone mould of the original silicone mould in which the master component is embedded. Using vacuum casting, we are then able to cast out of the second mould several optical transparent poly-urethane arrays of concave refractive microlenses. We select ten particular representative microlenses on the original, the silicone moulds and replica sample and quantitatively characterize and statistically compare them during the various fabrication steps. For this purpose, we use several state-of-the-art and ultra-precise characterization tools such as a stereo microscope, a stylus surface profilometer, a non-contact optical profilometer, a Mach-Zehnder interferometer, a Twyman-Green interferometer and an atomic force microscope to compare various microlens parameters such as the lens height, the diameter, the paraxial focal length, the radius of curvature, the Strehl ratio, the peak-to-valley and the root-mean-square wave aberrations and the surface roughness. When appropriate, the microlens parameter under test is measured with several different measuring tools to check for consistency in the measurement data. Although none of the lens samples shows diffraction-limited performance, we prove that the obtained replicated arrays of concave microlenses exhibit sufficiently low surface roughness and sufficiently high lens quality for various imaging applications.

  12. Signal Processing of MEMS Gyroscope Arrays to Improve Accuracy Using a 1st Order Markov for Rate Signal Modeling

    Directory of Open Access Journals (Sweden)

    Weizheng Yuan

    2012-02-01

    Full Text Available This paper presents a signal processing technique to improve angular rate accuracy of the gyroscope by combining the outputs of an array of MEMS gyroscope. A mathematical model for the accuracy improvement was described and a Kalman filter (KF was designed to obtain optimal rate estimates. Especially, the rate signal was modeled by a first-order Markov process instead of a random walk to improve overall performance. The accuracy of the combined rate signal and affecting factors were analyzed using a steady-state covariance. A system comprising a six-gyroscope array was developed to test the presented KF. Experimental tests proved that the presented model was effective at improving the gyroscope accuracy. The experimental results indicated that six identical gyroscopes with an ARW noise of 6.2 °/√h and a bias drift of 54.14 °/h could be combined into a rate signal with an ARW noise of 1.8 °/√h and a bias drift of 16.3 °/h, while the estimated rate signal by the random walk model has an ARW noise of 2.4 °/√h and a bias drift of 20.6 °/h. It revealed that both models could improve the angular rate accuracy and have a similar performance in static condition. In dynamic condition, the test results showed that the first-order Markov process model could reduce the dynamic errors 20% more than the random walk model.

  13. Signal Processing of MEMS Gyroscope Arrays to Improve Accuracy Using a 1st Order Markov for Rate Signal Modeling

    Science.gov (United States)

    Jiang, Chengyu; Xue, Liang; Chang, Honglong; Yuan, Guangmin; Yuan, Weizheng

    2012-01-01

    This paper presents a signal processing technique to improve angular rate accuracy of the gyroscope by combining the outputs of an array of MEMS gyroscope. A mathematical model for the accuracy improvement was described and a Kalman filter (KF) was designed to obtain optimal rate estimates. Especially, the rate signal was modeled by a first-order Markov process instead of a random walk to improve overall performance. The accuracy of the combined rate signal and affecting factors were analyzed using a steady-state covariance. A system comprising a six-gyroscope array was developed to test the presented KF. Experimental tests proved that the presented model was effective at improving the gyroscope accuracy. The experimental results indicated that six identical gyroscopes with an ARW noise of 6.2 °/√h and a bias drift of 54.14 °/h could be combined into a rate signal with an ARW noise of 1.8 °/√h and a bias drift of 16.3 °/h, while the estimated rate signal by the random walk model has an ARW noise of 2.4 °/√h and a bias drift of 20.6 °/h. It revealed that both models could improve the angular rate accuracy and have a similar performance in static condition. In dynamic condition, the test results showed that the first-order Markov process model could reduce the dynamic errors 20% more than the random walk model. PMID:22438734

  14. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  15. Multidimensional Systolic Arrays of LMS AlgorithmAdaptive (FIR Digital Filters

    Directory of Open Access Journals (Sweden)

    Bakir A. R. Al-Hashemy

    2009-01-01

    Full Text Available A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR filter may be opposed the fundamental requirements of fast convergence rate in most adaptive filter applications.

  16. A Sparsity-Based Approach to 3D Binaural Sound Synthesis Using Time-Frequency Array Processing

    Directory of Open Access Journals (Sweden)

    Spors Sascha

    2010-01-01

    Full Text Available Localization of sounds in physical space plays a very important role in multiple audio-related disciplines, such as music, telecommunications, and audiovisual productions. Binaural recording is the most commonly used method to provide an immersive sound experience by means of headphone reproduction. However, it requires a very specific recording setup using high-fidelity microphones mounted in a dummy head. In this paper, we present a novel processing framework for binaural sound recording and reproduction that avoids the use of dummy heads, which is specially suitable for immersive teleconferencing applications. The method is based on a time-frequency analysis of the spatial properties of the sound picked up by a simple tetrahedral microphone array, assuming source sparseness. The experiments carried out using simulations and a real-time prototype confirm the validity of the proposed approach.

  17. A Sparsity-Based Approach to 3D Binaural Sound Synthesis Using Time-Frequency Array Processing

    Science.gov (United States)

    Cobos, Maximo; Lopez, JoseJ; Spors, Sascha

    2010-12-01

    Localization of sounds in physical space plays a very important role in multiple audio-related disciplines, such as music, telecommunications, and audiovisual productions. Binaural recording is the most commonly used method to provide an immersive sound experience by means of headphone reproduction. However, it requires a very specific recording setup using high-fidelity microphones mounted in a dummy head. In this paper, we present a novel processing framework for binaural sound recording and reproduction that avoids the use of dummy heads, which is specially suitable for immersive teleconferencing applications. The method is based on a time-frequency analysis of the spatial properties of the sound picked up by a simple tetrahedral microphone array, assuming source sparseness. The experiments carried out using simulations and a real-time prototype confirm the validity of the proposed approach.

  18. Optimizing laser beam profiles using micro-lens arrays for efficient material processing: applications to solar cells

    Science.gov (United States)

    Hauschild, Dirk; Homburg, Oliver; Mitra, Thomas; Ivanenko, Mikhail; Jarczynski, Manfred; Meinschien, Jens; Bayer, Andreas; Lissotschenko, Vitalij

    2009-02-01

    High power laser sources are used in various production tools for microelectronic products and solar cells, including the applications annealing, lithography, edge isolation as well as dicing and patterning. Besides the right choice of the laser source suitable high performance optics for generating the appropriate beam profile and intensity distribution are of high importance for the right processing speed, quality and yield. For industrial applications equally important is an adequate understanding of the physics of the light-matter interaction behind the process. In advance simulations of the tool performance can minimize technical and financial risk as well as lead times for prototyping and introduction into series production. LIMO has developed its own software founded on the Maxwell equations taking into account all important physical aspects of the laser based process: the light source, the beam shaping optical system and the light-matter interaction. Based on this knowledge together with a unique free-form micro-lens array production technology and patented micro-optics beam shaping designs a number of novel solar cell production tool sub-systems have been built. The basic functionalities, design principles and performance results are presented with a special emphasis on resilience, cost reduction and process reliability.

  19. In-line Ultrasonic Array System for Monitoring Dynamic of Coating Forming by Cold Spray Process

    Science.gov (United States)

    Lubrick, M.; Titov, S.; Leshchynsky, V.; Maev, R. Gr.

    This study attempts to test the viability of studying the cold spray process using acoustic methods, specifically testing during the actual spray process itself. Multiple composites studied by flat and multi channel transducers as well as actual online measurements are presented. It is shown that the final thickness as well as the dynamics of buildup can be evaluated (including plotting rates of buildup). Cross sections of the coating thickness are also easy to obtain and show true profiles of the coating. The data can also be used to generate real estimates for nozzle speed and spray diameter. Finally comparisons of real thickness and acoustically estimated thickness show a close linear relationship with the y intercept seeming to depend on the composition. The data clearly shows that online acoustic measurement is a viable method for estimating thickness buildup.

  20. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  1. Nested Vector-Sensor Array Processing via Tensor Modeling (Briefing Charts)

    Science.gov (United States)

    2014-04-24

    Processing via Tensor Modeling (Briefing Charts) 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e...and U2,U4 ∈ CNc ×Nc are orthonormal matrices, provided by the SVD of the i-mode matricization of the tensor T : T (i) = UiΛiV H i . K ∈ CN̄×Nc×N̄×Nc is

  2. Neuromorphic VLSI vision system for real-time texture segregation.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2008-10-01

    The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

  3. Low cost solar array project production process and equipment task: A Module Experimental Process System Development Unit (MEPSDU)

    Science.gov (United States)

    1981-01-01

    Several major modifications were made to the design presented at the PDR. The frame was deleted in favor of a "frameless" design which will provide a substantially improved cell packing factor. Potential shaded cell damage resulting from operation into a short circuit can be eliminated by a change in the cell series/parallel electrical interconnect configuration. The baseline process sequence defined for the MEPSON was refined and equipment design and specification work was completed. SAMICS cost analysis work accelerated, format A's were prepared and computer simulations completed. Design work on the automated cell interconnect station was focused on bond technique selection experiments.

  4. Framework for Managing the Very Large Scale Integration Design Process

    Directory of Open Access Journals (Sweden)

    Sabah Al-Fedaghi

    2012-01-01

    Full Text Available Problem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as control flow and data structure. It was important to fill the gap between these two levels of description because VLSI chip manufacturing was a complex management project and providing a conceptual detailed depiction of the design process would assist in managing operations on the great number of generated artifacts. Approach: This study introduces a conceptual framework representing flows and transformations of various descriptions (e.g., circuits, technical sketches to be used as a tracking apparatus for directing traffic during the VLSI design process. The proposed methodology views a description as an integral element of a process, called a flow system, constructed from six generic operations and designed to handle descriptions. It draws maps of flows of representations (called flowthings that run through the design flow. These flowthings are created, transformed (processed, transferred, released and received by various functions along the design flow at different levels (a hierarchy. The resultant conceptual framework can be used to support designers with computer-aided tools to organize and manage chains of tasks. Results: The proposed model for managing the VLSI design process was characterized by being conceptual (no technical or implementation details and can be uniformly applied at different levels of design and to various kinds of artifacts. The methodology is applied to describe the VLSI physical design stage that includes partitioning, floorplanning and placement, routing, compaction and extraction

  5. A novel array processing method for precise depth detection of ultrasound point scatter

    DEFF Research Database (Denmark)

    Diamantis, Konstantinos; Dalgarno, Paul A.; Greenaway, Alan H.;

    2016-01-01

    simulation software. A 7 MHz linear transducer is used to scan a single point scatterer phantom that can move in the axial direction. Individual beamformer outputs from 3 different foci are post-processed using the highly-dependent on focusing errors, metric of sharpness to estimate the position of the point...... scatter. A 37.8 μm uncertainty in depth estimation is achieved, which attains an almost 3-fold improvement compared to conventional ultrasound imaging axial resolution. Future work on the development of this algorithm requires experimental validation in tissue-like materials that provide strong...

  6. Low cost silicon solar array project large area silicon sheet task: Silicon web process development

    Science.gov (United States)

    Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Blais, P. D.; Davis, J. R., Jr.

    1977-01-01

    Growth configurations were developed which produced crystals having low residual stress levels. The properties of a 106 mm diameter round crucible were evaluated and it was found that this design had greatly enhanced temperature fluctuations arising from convection in the melt. Thermal modeling efforts were directed to developing finite element models of the 106 mm round crucible and an elongated susceptor/crucible configuration. Also, the thermal model for the heat loss modes from the dendritic web was examined for guidance in reducing the thermal stress in the web. An economic analysis was prepared to evaluate the silicon web process in relation to price goals.

  7. Reconfiguration Schemes for Fault-Tolerant Processor Arrays

    Science.gov (United States)

    1992-10-15

    Computacion UDEM󈨞, Universidad de Monterrey, Monterrey, Mexico , September 28, 1990. [2] "Systolic Array Design in the Linear Algebra Framework...integers. 8.Applications, 1915 . pp 268-M7. i.NI8S.Y. Kung. VLSI .4rrav Pr’ocessors. EnglewoodClfsN.: N’: set of positive integers. Prenuce-Hall. 1987...ns: number of components of index points in 9. C. Guerra and R. Melhem. Synthesizing non-uniformn systolic 1: see Definition 2.1 M1. designs. Pr’oc

  8. Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Reliazation of Digital Signal Processing Functions

    Directory of Open Access Journals (Sweden)

    Amitabha Sinha

    2013-04-01

    Full Text Available Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is redolent to FPGA, but with basic fixed Common Modules (CMs (like adders, subtractors, multipliers, scaling units, shifters instead of CLBs. This pape r introduces the development of a reconfigurable DSP processor that integrates different filter and transform functions. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.

  9. Investigation and process optimization of SONOS cell's drain disturb in 2-transistor structure flash arrays

    Science.gov (United States)

    Xu, Zhaozhao; Qian, Wensheng; Chen, Hualun; Xiong, Wei; Hu, Jun; Liu, Donghua; Duan, Wenting; Kong, Weiran; Na, Wei; Zou, Shichang

    2017-03-01

    The mechanism and distribution of drain disturb (DD) are investigated in silicon-oxide-nitride-oxide-silicon (SONOS) flash cells. It is shown that DD is the only concern in this paper. First, the distribution of trapped charge in nitride layer is found to be non-localized (trapped in entire nitride layer along the channel) after programming. Likewise, the erase is also non-localized. Then, the main disturb mechanism: Fowler Nordheim tunneling (FNT) has been confirmed in this paper with negligible disturb effect from hot-hole injection (HHI). And then, distribution of DD is confirmed to be non-localized similarly, which denotes that DD exists in entire tunneling oxide (Oxide for short). Next, four process optimization ways are proposed for minimization of DD, and VTH shift is measured. It reveals that optimized lightly doped drain (LDD), halo, and channel implant are required for the fabrication of a robust SONOS cell. Finally, data retention and endurance of the optimized SONOS are demonstrated.

  10. Quantitative Analysis of Rat Dorsal Root Ganglion Neurons Cultured on Microelectrode Arrays Based on Fluorescence Microscopy Image Processing.

    Science.gov (United States)

    Mari, João Fernando; Saito, José Hiroki; Neves, Amanda Ferreira; Lotufo, Celina Monteiro da Cruz; Destro-Filho, João-Batista; Nicoletti, Maria do Carmo

    2015-12-01

    Microelectrode Arrays (MEA) are devices for long term electrophysiological recording of extracellular spontaneous or evocated activities on in vitro neuron culture. This work proposes and develops a framework for quantitative and morphological analysis of neuron cultures on MEAs, by processing their corresponding images, acquired by fluorescence microscopy. The neurons are segmented from the fluorescence channel images using a combination of segmentation by thresholding, watershed transform, and object classification. The positioning of microelectrodes is obtained from the transmitted light channel images using the circular Hough transform. The proposed method was applied to images of dissociated culture of rat dorsal root ganglion (DRG) neuronal cells. The morphological and topological quantitative analysis carried out produced information regarding the state of culture, such as population count, neuron-to-neuron and neuron-to-microelectrode distances, soma morphologies, neuron sizes, neuron and microelectrode spatial distributions. Most of the analysis of microscopy images taken from neuronal cultures on MEA only consider simple qualitative analysis. Also, the proposed framework aims to standardize the image processing and to compute quantitative useful measures for integrated image-signal studies and further computational simulations. As results show, the implemented microelectrode identification method is robust and so are the implemented neuron segmentation and classification one (with a correct segmentation rate up to 84%). The quantitative information retrieved by the method is highly relevant to assist the integrated signal-image study of recorded electrophysiological signals as well as the physical aspects of the neuron culture on MEA. Although the experiments deal with DRG cell images, cortical and hippocampal cell images could also be processed with small adjustments in the image processing parameter estimation.

  11. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  12. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  13. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  14. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  15. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  16. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  17. VLSI Architecture Of A Binary Up/Down Counter

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie; Reed, I. S.

    1988-01-01

    Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.

  18. Determination of Rayleigh wave ellipticity across the Earthscope Transportable Array using single-station and array-based processing of ambient seismic noise

    Science.gov (United States)

    Workman, Eli; Lin, Fan-Chi; Koper, Keith D.

    2017-01-01

    We present a single station method for the determination of Rayleigh wave ellipticity, or Rayleigh wave horizontal to vertical amplitude ratio (H/V) using Frequency Dependent Polarization Analysis (FDPA). This procedure uses singular value decomposition of 3-by-3 spectral covariance matrices over 1-hr time windows to determine properties of the ambient seismic noise field such as particle motion and dominant wave-type. In FPDA, if the noise is mostly dominated by a primary singular value and the phase difference is roughly 90° between the major horizontal axis and the vertical axis of the corresponding singular vector, we infer that Rayleigh waves are dominant and measure an H/V ratio for that hour and frequency bin. We perform this analysis for all available data from the Earthscope Transportable Array between 2004 and 2014. We compare the observed Rayleigh wave H/V ratios with those previously measured by multicomponent, multistation noise cross-correlation (NCC), as well as classical noise spectrum H/V ratio analysis (NSHV). At 8 s the results from all three methods agree, suggesting that the ambient seismic noise field is Rayleigh wave dominated. Between 10 and 30 s, while the general pattern agrees well, the results from FDPA and NSHV are persistently slightly higher (˜2 per cent) and significantly higher (>20 per cent), respectively, than results from the array-based NCC. This is likely caused by contamination from other wave types (i.e. Love waves, body waves, and tilt noise) in the single station methods, but it could also reflect a small, persistent error in NCC. Additionally, we find that the single station method has difficulty retrieving robust Rayleigh wave H/V ratios within major sedimentary basins, such as the Williston Basin and Mississippi Embayment, where the noise field is likely dominated by reverberating Love waves and tilt noise.

  19. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  20. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  1. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  2. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  3. 阵列信号处理实验平台设计%Design on Experimental Platform for Array Signal Processing

    Institute of Scientific and Technical Information of China (English)

    杨涛; 朱闪闪; 刘玉佼

    2015-01-01

    本文针对一维线阵和二维面阵的阵列信号处理算法研究,设计了一种发射阵列和接收阵列上下交错排布的二维稀疏超声相控阵列信号处理实验平台,并给出了实验平台的硬件总体功能设计、发射和接收电路设计及软件架构。相控阵声场特性仿真分析结果表明该实验平台具有较好的波束成形和波达方向估计效果。%Focused on the algorithm study of one-dimensional and two-dimensional array signal processing,this pa-per designs an experimental platform for two-dimensional sparse ultrasonic phased array signal processing in which transmit array and receive array are interleavingly arranged and gives the general functional design of hardware( in-cluding the transmit circuit and receive circuit)and the software architecture. The simulation of the acoustic field characteristics of the phased array demonstrates that the experimental platform has better beamforming and direction of arrival( DOA)estimation results.

  4. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  5. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  6. Coherent-subspace array processing based on wavelet covariance: an application to broad-band, seismo-volcanic signals

    Science.gov (United States)

    Saccorotti, G.; Nisii, V.; Del Pezzo, E.

    2008-07-01

    Long-Period (LP) and Very-Long-Period (VLP) signals are the most characteristic seismic signature of volcano dynamics, and provide important information about the physical processes occurring in magmatic and hydrothermal systems. These events are usually characterized by sharp spectral peaks, which may span several frequency decades, by emergent onsets, and by a lack of clear S-wave arrivals. These two latter features make both signal detection and location a challenging task. In this paper, we propose a processing procedure based on Continuous Wavelet Transform of multichannel, broad-band data to simultaneously solve the signal detection and location problems. Our method consists of two steps. First, we apply a frequency-dependent threshold to the estimates of the array-averaged WCO in order to locate the time-frequency regions spanned by coherent arrivals. For these data, we then use the time-series of the complex wavelet coefficients for deriving the elements of the spatial Cross-Spectral Matrix. From the eigenstructure of this matrix, we eventually estimate the kinematic signals' parameters using the MUltiple SIgnal Characterization (MUSIC) algorithm. The whole procedure greatly facilitates the detection and location of weak, broad-band signals, in turn avoiding the time-frequency resolution trade-off and frequency leakage effects which affect conventional covariance estimates based upon Windowed Fourier Transform. The method is applied to explosion signals recorded at Stromboli volcano by either a short-period, small aperture antenna, or a large-aperture, broad-band network. The LP (0.2 2s) of the explosion recordings from the broad-band network. Source locations obtained this way are fully compatible with those retrieved from application of more traditional (and computationally expensive) time-domain techniques, such as the Radial Semblance method.

  7. Analysis of boundary point (break point) in Linear Delay Model for nanoscale VLSI standard cell library characterization at PVT corners

    CERN Document Server

    Agarwal, Gaurav Kumar

    2014-01-01

    In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay is picked from Look Up Tables (LUT) rather than conventional SPICE simulations. But accuracy of this method depends upon the underlying delay model with which LUT was characterized. Non Linear Delay Model (NLDM) based LUTs are quite common in industries. These LUT requires huge amount to time during characterization because of huge number of SPICE simulations done at arbitrary points. To improve this people proposed various other delay models like alpha-power and piecewise linear delay models. Bulusu et al proposed Linear Delay Model(LDM) which reduces LUT generation time to 50 percent. LDM divides delay curve w.r.t input rise time(trin) into two different region one is linear and other is non-linear. This boundary point between linear and non- linear region was called break point (trb). Linear region will be done if we simulate at only two points. This advantage...

  8. Simultaneous and automated monitoring of the multimetal biosorption processes by potentiometric sensor array and artificial neural network.

    Science.gov (United States)

    Wilson, D; del Valle, M; Alegret, S; Valderrama, C; Florido, A

    2013-09-30

    In this communication, a new methodology for the simultaneous and automated monitoring of biosorption processes of multimetal mixtures of polluting heavy metals on vegetable wastes based on flow-injection potentiometry (FIP) and electronic tongue detection (ET) is presented. A fixed-bed column filled with grape stalks from wine industry wastes is used as the biosorption setup to remove the metal mixtures from the influent solution. The monitoring system consists in a computer controlled-FIP prototype with the ET based on an array of 9 flow-through ion-selective electrodes and electrodes with generic response to divalent ions placed in series, plus an artificial neural network response model. The cross-response to Cu(2+), Cd(2+), Zn(2+), Pb(2+) and Ca(2+) (as target ions) is used, and only when dynamic treatment of the kinetic components of the transient signal is incorporated, a correct operation of the system is achieved. For this purpose, the FIA peaks are transformed via use of Fourier treatment, and selected coefficients are used to feed an artificial neural network response model. Real-time monitoring of different binary (Cu(2+)/ Pb(2+)), (Cu(2+)/ Zn(2+)) and ternary mixtures (Cu(2+)/ Pb(2+)/ Zn(2+)), (Cu(2+)/ Zn(2+)/ Cd(2+)), simultaneous to the release of Ca(2+) in the effluent solution, are achieved satisfactorily using the reported system, obtaining the corresponding breakthrough curves, and showing the ion-exchange mechanism among the different metals. Analytical performance is verified against conventional spectroscopic techniques, with good concordance of the obtained breakthrough curves and modeled adsorption parameters.

  9. Enhanced processing in arrays of optimally tuned nonlinear biomimetic sensors: A coupling-mediated Ringelmann effect and its dynamical mitigation

    Science.gov (United States)

    Nikitin, Alexander P.; Bulsara, Adi R.; Stocks, Nigel G.

    2017-03-01

    Inspired by recent results on self-tunability in the outer hair cells of the mammalian cochlea, we describe an array of magnetic sensors where each individual sensor can self-tune to an optimal operating regime. The self-tuning gives the array its "biomimetic" features. We show that the overall performance of the array can, as expected, be improved by increasing the number of sensors but, however, coupling between sensors reduces the overall performance even though the individual sensors in the system could see an improvement. We quantify the similarity of this phenomenon to the Ringelmann effect that was formulated 103 years ago to account for productivity losses in human and animal groups. We propose a global feedback scheme that can be used to greatly mitigate the performance degradation that would, normally, stem from the Ringelmann effect.

  10. Arrays of holes fabricated by electron-beam lithography combined with image reversal process using nickel pulse reversal plating

    Science.gov (United States)

    Awad, Yousef; Lavallée, Eric; Lau, Kien Mun; Beauvais, Jacques; Drouin, Dominique; Cloutier, Melanie; Turcotte, David; Yang, Pan; Kelkar, Prasad

    2004-05-01

    A critical issue in fabricating arrays of holes is to achieve high-aspect-ratio structures. Formation of ordered arrays of nanoholes in silicon nitride was investigated by the use of ultrathin hard etch mask formed by nickel pulse reversal plating to invert the tonality of a dry e-beam resist patterned by e-beam lithography. Ni plating was carried out using a commercial plating solution based on nickel sulfamate salt without organic additives. Reactive ion etching using SF6/CH4 was found to be very effective for pattern transfer to silicon nitride. Holes array of 100 nm diam, 270 nm period, and 400 nm depth was fabricated on a 5×5 mm2 area. .

  11. Radar techniques using array antennas

    CERN Document Server

    Wirth, Wulf-Dieter

    2013-01-01

    Radar Techniques Using Array Antennas is a thorough introduction to the possibilities of radar technology based on electronic steerable and active array antennas. Topics covered include array signal processing, array calibration, adaptive digital beamforming, adaptive monopulse, superresolution, pulse compression, sequential detection, target detection with long pulse series, space-time adaptive processing (STAP), moving target detection using synthetic aperture radar (SAR), target imaging, energy management and system parameter relations. The discussed methods are confirmed by simulation stud

  12. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  13. Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

    Science.gov (United States)

    Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

    2015-09-09

    Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes.

  14. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  15. New Metric Based Algorithm for Test Vector Generation in VLSI Testing

    Directory of Open Access Journals (Sweden)

    M. V. Atre

    1995-07-01

    Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.

  16. Spike-based VLSI modeling of the ILD system in the echolocating bat.

    Science.gov (United States)

    Horiuchi, T; Hynna, K

    2001-01-01

    The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.

  17. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  18. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  19. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  20. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  1. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  2. Using Array Methods to Identify and Process Weak Signals Generated by the Brightlight(Ⅰ)50t Explosion

    Institute of Scientific and Technical Information of China (English)

    Hao Chunyue; Zheng Zhong; Zhang Shuang

    2010-01-01

    Waveforms generated by the 50t explosion of project Brightlight(Ⅰ)were recorded by HILR array.Using array techniques,the author performed identification,f-k analysis,velocity spectrum analysis,etc.of the weak signals.The analysis results show that the signal-to-noise ratio after beamforming was obviously enhanced,and the signal could be clearly shown.The energy from this explosion was mainly concentrated in the 1~8Hz range from f-k analysis.The velocity spectrum gave clear positions of event phases,which could not be seen in the original weak signals.The maximum energy distribution obtained by the Beaman method is close to the theoretical value in the azimuth-slowness domain.

  3. Biological Inspired Stochastic Optimization Technique (PSO for DOA and Amplitude Estimation of Antenna Arrays Signal Processing in RADAR Communication System

    Directory of Open Access Journals (Sweden)

    Khurram Hammed

    2016-01-01

    Full Text Available This paper presents a stochastic global optimization technique known as Particle Swarm Optimization (PSO for joint estimation of amplitude and direction of arrival of the targets in RADAR communication system. The proposed scheme is an excellent optimization methodology and a promising approach for solving the DOA problems in communication systems. Moreover, PSO is quite suitable for real time scenario and easy to implement in hardware. In this study, uniform linear array is used and targets are supposed to be in far field of the arrays. Formulation of the fitness function is based on mean square error and this function requires a single snapshot to obtain the best possible solution. To check the accuracy of the algorithm, all of the results are taken by varying the number of antenna elements and targets. Finally, these results are compared with existing heuristic techniques to show the accuracy of PSO.

  4. Resolution and signal-to-noise ratio improvement in confocal fluorescence microscopy using array detection and maximum-likelihood processing

    Science.gov (United States)

    Kakade, Rohan; Walker, John G.; Phillips, Andrew J.

    2016-08-01

    Confocal fluorescence microscopy (CFM) is widely used in biological sciences because of its enhanced 3D resolution that allows image sectioning and removal of out-of-focus blur. This is achieved by rejection of the light outside a detection pinhole in a plane confocal with the illuminated object. In this paper, an alternative detection arrangement is examined in which the entire detection/image plane is recorded using an array detector rather than a pinhole detector. Using this recorded data an attempt is then made to recover the object from the whole set of recorded photon array data; in this paper maximum-likelihood estimation has been applied. The recovered object estimates are shown (through computer simulation) to have good resolution, image sectioning and signal-to-noise ratio compared with conventional pinhole CFM images.

  5. Tantalum (oxy)nitrides nanotube arrays for the degradation of atrazine in vis-Fenton-like process.

    Science.gov (United States)

    Du, Yingxun; Zhao, Lu; Chang, Yuguang; Su, Yaling

    2012-07-30

    In order to overcome the limitation of the application of nanoparticles, tantalum (oxy)nitrides nanotube arrays on a Ta foil were synthesized and introduced in vis (visible light)-Fenton-like system to enhance the degradation of atrazine. At first, the anodization of tantalum foil in a mild electrolyte solution containing ethylene glycol and water (v:v=2:1) plus 0.5wt.% NH(4)F produced tantala nanotubes with an average diameter of 30nm and a length of approximately 1μm. Then the nitridation of tantala nanotube arrays resulted in the replacement of N atoms to O atoms to form tantalum (oxy)nitrides (TaON and Ta(3)N(5)), as testified by XRD and XPS analyses. The synthesized tantalum (oxy)nitrides nanotubes absorb well in the visible region up to 600nm. Under visible light, tantalum (oxy)nitrides nanotube arrays were catalytically active for Fe(3+) reduction. With tantalum (oxy)nitrides nanotube arrays, the degradation of atrazine and the formation of the intermediates in vis/Fe(3+)/H(2)O(2) system were significantly accelerated. This was explained by the higher concentration of Fe(2+) and thus the faster decomposition of H(2)O(2) with tantalum (oxy)nitrides nanotubes. In addition, tantalum (oxy)nitrides nanotubes exhibited stable performance during atrazine degradation for three runs. The good performance and stability of the tantalum (oxy)nitrides nanotubes film with the convenient separation, suggest that this film is a promising catalyst for vis-Fenton-like degradation.

  6. Integration of Fiber-Optic Sensor Arrays into a Multi-Modal Tactile Sensor Processing System for Robotic End-Effectors

    Science.gov (United States)

    Kampmann, Peter; Kirchner, Frank

    2014-01-01

    With the increasing complexity of robotic missions and the development towards long-term autonomous systems, the need for multi-modal sensing of the environment increases. Until now, the use of tactile sensor systems has been mostly based on sensing one modality of forces in the robotic end-effector. The use of a multi-modal tactile sensory system is motivated, which combines static and dynamic force sensor arrays together with an absolute force measurement system. This publication is focused on the development of a compact sensor interface for a fiber-optic sensor array, as optic measurement principles tend to have a bulky interface. Mechanical, electrical and software approaches are combined to realize an integrated structure that provides decentralized data pre-processing of the tactile measurements. Local behaviors are implemented using this setup to show the effectiveness of this approach. PMID:24743158

  7. Integration of Fiber-Optic Sensor Arrays into a Multi-Modal Tactile Sensor Processing System for Robotic End-Effectors

    Directory of Open Access Journals (Sweden)

    Peter Kampmann

    2014-04-01

    Full Text Available With the increasing complexity of robotic missions and the development towards long-term autonomous systems, the need for multi-modal sensing of the environment increases. Until now, the use of tactile sensor systems has been mostly based on sensing one modality of forces in the robotic end-effector. The use of a multi-modal tactile sensory system is motivated, which combines static and dynamic force sensor arrays together with an absolute force measurement system. This publication is focused on the development of a compact sensor interface for a fiber-optic sensor array, as optic measurement principles tend to have a bulky interface. Mechanical, electrical and software approaches are combined to realize an integrated structure that provides decentralized data pre-processing of the tactile measurements. Local behaviors are implemented using this setup to show the effectiveness of this approach.

  8. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  9. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    Science.gov (United States)

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.

  10. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  11. The digi-neocognitron: a digital neocognitron neural network model for VLSI.

    Science.gov (United States)

    White, B A; Elmasry, M I

    1992-01-01

    One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

  12. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  13. VLSI Neural Networks Help To Compress Video Signals

    Science.gov (United States)

    Fang, Wai-Chi; Sheu, Bing J.

    1996-01-01

    Advanced analog/digital electronic system for compression of video signals incorporates artificial neural networks. Performs motion-estimation and image-data-compression processing. Effectively eliminates temporal and spatial redundancies of sequences of video images; processes video image data, retaining only nonredundant parts to be transmitted, then transmits resulting data stream in form of efficient code. Reduces bandwidth and storage requirements for transmission and recording of video signal.

  14. Programmable retinal dynamics in a CMOS mixed-signal array processor chip

    Science.gov (United States)

    Carmona, Ricardo A.; Jimenez-Garrido, Francisco J.; Dominguez-Castro, Rafael; Espejo, Servando; Rodriguez-Vazquez, Angel

    2003-04-01

    The retina is responsible of the treatment of visual information at early stages. Visual stimuli generate patterns of activity that are transmitted through its layered structure up to the ganglion cells that interface it to the optical nerve. In this trip of micrometers, information is sustained by continuous signals that interact in excitatory and inhibitory ways. This low-level processing compresses the relevant information of the images to a manageable size. The behavior of the more external layers of the biological retina has been successfully modelled within the Cellular Neural Network framework. Interactions between cells are realized on a local basic. Each cell interacts with its nearest neighbors and every cell in the same layer follows the same interconnection pattern. Intra- and inter-layer interactions are continuous in magnitude and time. The evolution of the network can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. A CMOS Programmable Array Processor prototype chip has been designed and fabricated in a standard technology. It has been successfully tested, validating the proposed design techniques. The integrated system consists of a network of 2 coupled layers, containing 32×32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnection weights, internally coded as analog but programmed via a digital interface. Propagative, active wave phenomena and retina-lake effects can be observed in this chip. Low-level image processing tasks for early vision applications can be developed based on these high-order dynamics.

  15. An efficient VLSI implementation of H.264/AVC entropy decoder

    Institute of Scientific and Technical Information of China (English)

    Jongsik; PARK; Jeonhak; MOON; Seongsoo; LEE

    2010-01-01

    <正>This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and internal buffers,which significantly improves area,speed,and power.The proposed entropy decoder does not exploit embedded processor for bitstream manipulation, which also improves area,speed,and power.Its gate counts and maximum operation frequency are 77515 gates and 175MHz in 0.18um fabrication process,respectively.The proposed entropy decoder needs 2303 cycles in average for one macroblock decoding.It can run at 28MHz to meet the real-time processing requirement for CIF format video decoding on mobile applications.

  16. Handbook of VLSI microlithography principles, technology and applications

    CERN Document Server

    Glendinning, William B

    1991-01-01

    This handbook gives readers a close look at the entire technology of printing very high resolution and high density integrated circuit (IC) patterns into thin resist process transfer coatings-- including optical lithography, electron beam, ion beam, and x-ray lithography. The book's main theme is the special printing process needed to achieve volume high density IC chip production, especially in the Dynamic Random Access Memory (DRAM) industry. The book leads off with a comparison of various lithography methods, covering the three major patterning parameters of line/space, resolution, line e

  17. Complex VLSI Feature Comparison for Commercial Microelectronics Verification

    Science.gov (United States)

    2014-03-27

    verification of untrusted circuits using industry-standard and custom software. The process developed under TRUST and implemented at the AFRL Mixed Signal...79 5.2.3 SCR and Other Netlists . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.4 Additional Tools...Reliability of Integrated Circuits LVS layout versus schematic MOSIS the Metal Oxide Semiconductor Implementation Service MSDC Mixed Signal Design

  18. Low noise Millimeter-wave and THz Receivers, Imaging Arrays, Switches in Advanced CMOS and SiGe Processes /

    OpenAIRE

    Uzunkol, Mehmet

    2013-01-01

    The thesis presents advanced millimeter-wave and THz receivers, imaging arrays, switches and detectors in CMOS and SiGe BiCMOS technologies. First, an in-depth analysis of a SiGe BiCMOS on-off keying (OOK) receiver composed of a low noise SiGe amplifier and an OOK detector is presented. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. Also, the LO leakage from the transmitter can have a detrim...

  19. Tantalum (oxy)nitrides nanotube arrays for the degradation of atrazine in vis-Fenton-like process

    Energy Technology Data Exchange (ETDEWEB)

    Du, Yingxun, E-mail: yxdu@niglas.ac.cn [Nanjing Institute of Geography and Limnology, State Key Laboratory of Lake Science and Environment, Chinese Academy of Sciences, Nanjing 210008 (China); Zhao, Lu [Nanjing Institute of Geography and Limnology, State Key Laboratory of Lake Science and Environment, Chinese Academy of Sciences, Nanjing 210008 (China); Chang, Yuguang [School of Biochemical and Environmental Engineering, Nanjing Xiaozhuang Univeristy, Nanjing 211171 (China); Su, Yaling [Nanjing Institute of Geography and Limnology, State Key Laboratory of Lake Science and Environment, Chinese Academy of Sciences, Nanjing 210008 (China)

    2012-07-30

    Highlights: Black-Right-Pointing-Pointer Tantala nanotubes on a Ta foil were formed by anodization in a NH{sub 4}F-containing electrolyte. Black-Right-Pointing-Pointer Tantalum (oxy)nitrides nanotubes were active for Fe{sup 3+} reduction under visible light. Black-Right-Pointing-Pointer Atrazine degradation by {center_dot}OH was accelerated with tantalum (oxy)nitrides nanotubes. Black-Right-Pointing-Pointer Tantalum (oxy)nitrides nanotubes display stable performance for atrazine degradation. - Abstract: In order to overcome the limitation of the application of nanoparticles, tantalum (oxy)nitrides nanotube arrays on a Ta foil were synthesized and introduced in vis (visible light)-Fenton-like system to enhance the degradation of atrazine. At first, the anodization of tantalum foil in a mild electrolyte solution containing ethylene glycol and water (v:v = 2:1) plus 0.5 wt.% NH{sub 4}F produced tantala nanotubes with an average diameter of 30 nm and a length of approximately 1 {mu}m. Then the nitridation of tantala nanotube arrays resulted in the replacement of N atoms to O atoms to form tantalum (oxy)nitrides (TaON and Ta{sub 3}N{sub 5}), as testified by XRD and XPS analyses. The synthesized tantalum (oxy)nitrides nanotubes absorb well in the visible region up to 600 nm. Under visible light, tantalum (oxy)nitrides nanotube arrays were catalytically active for Fe{sup 3+} reduction. With tantalum (oxy)nitrides nanotube arrays, the degradation of atrazine and the formation of the intermediates in vis/Fe{sup 3+}/H{sub 2}O{sub 2} system were significantly accelerated. This was explained by the higher concentration of Fe{sup 2+} and thus the faster decomposition of H{sub 2}O{sub 2} with tantalum (oxy)nitrides nanotubes. In addition, tantalum (oxy)nitrides nanotubes exhibited stable performance during atrazine degradation for three runs. The good performance and stability of the tantalum (oxy)nitrides nanotubes film with the convenient separation, suggest that this film is

  20. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.