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Sample records for vlsi physical design

  1. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  2. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  3. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  4. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  5. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  6. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  7. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  8. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  9. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  10. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  11. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  12. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  13. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  14. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  15. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  16. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  17. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  18. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  19. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  20. A Coherent VLSI Design Environment.

    Science.gov (United States)

    2014-09-26

    physical devices from which physical circuits are fabricated. By analogy with context-free languages , a class of circuits is generated by a phrase-structure... language called CLU [131. It consists of SPICE interface, minimization, and matrix manipulation program modules. These modules contain 3200, 1800, and...greatly simplify the optimization problem. They reformulated the original problem, a minimization subject to nonlinear constraints, as an

  1. A Coherent VLSI Design Environment

    Science.gov (United States)

    1987-03-31

    In the figure, AminH and Ama.H represent the smallest and largest eigenvalues I of YH and AminAH and AmaAH represent the smallest and largest...Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International Conference on Computer-Aided

  2. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  3. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  4. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  5. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  6. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  7. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  8. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  9. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  10. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  11. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  12. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  13. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  14. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  15. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  16. Dual Butterfly Match Filter VLSI Design

    Institute of Scientific and Technical Information of China (English)

    LIU Zhenyu; HAN Yueqiu

    2001-01-01

    Match filter is widely used in realtime signal processing, especially in Radar Signal Processing. This paper provides a novel ASIC design,which not only saves resource, but also improves thethroughput of the system. This ASIC is specially designed for Radar Pulse Compression. Certainly it canalso be used in other circumstances, such as FIR filter.

  17. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  18. Simplified microprocessor design for VLSI control applications

    Science.gov (United States)

    Cameron, K.

    1991-01-01

    A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

  19. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  20. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  1. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  2. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  3. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  4. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  5. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  6. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  7. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  8. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  9. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  10. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  11. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  12. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  13. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  14. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  15. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  16. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  17. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  18. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  19. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  20. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  1. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  2. Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments

    Science.gov (United States)

    Loinaz, Marc Joseph

    1995-11-01

    This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-μm CMOS technology. Each channel includes a wideband amplifier, a

  3. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  4. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  5. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  6. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  7. Research News: Are VLSI Microcircuits Too Hard to Design?

    Science.gov (United States)

    Robinson, Arthur L.

    1980-01-01

    This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

  8. Principles of VLSI RTL design a practical guide

    CERN Document Server

    Churiwala, Sanjay; Gianfagna, Mike

    2011-01-01

    This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

  9. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  10. Design and implementation of multipattern generators in analog VLSI.

    Science.gov (United States)

    Kier, Ryan J; Ames, Jeffrey C; Beer, Randall D; Harrison, Reid R

    2006-07-01

    In recent years, computational biologists have shown through simulation that small neural networks with fixed connectivity are capable of producing multiple output rhythms in response to transient inputs. It is believed that such networks may play a key role in certain biological behaviors such as dynamic gait control. In this paper, we present a novel method for designing continuous-time recurrent neural networks (CTRNNs) that contain multiple embedded limit cycles, and we show that it is possible to switch the networks between these embedded limit cycles with simple transient inputs. We also describe the design and testing of a fully integrated four-neuron CTRNN chip that is used to implement the neural network pattern generators. We provide two example multipattern generators and show that the measured waveforms from the chip agree well with numerical simulations.

  11. A digital neuron-type processor and its VLSI design

    Science.gov (United States)

    Akel, H.; Habib, Mahmoud K.

    1989-05-01

    A set of neuron-type circuits elements based on logic gate circuits with multiinput multifan output capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base, and the axon circuit. These three elements are cascaded to form a neuron-type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VSLI techniques.

  12. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  13. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  14. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  15. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  16. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  17. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  18. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  19. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    Science.gov (United States)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  20. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  1. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  2. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  3. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  4. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  5. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  6. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  7. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  8. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  9. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  10. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  11. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  12. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  13. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  14. Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology

    Directory of Open Access Journals (Sweden)

    Joyashree Bag

    2012-12-01

    Full Text Available RFID is a low power wireless emerging technology which has given rise to highly promising applications in real life. It can be employed for robot navigation. In multi-robot environment, when many robots are moving in the same work space, there is a possibility of their physical collision with themselves as well as with physical objects. In the present work, we have proposed and developed a processor incorporating smart algorithm for avoiding such collisions with the help of RFID technology and implemented it by using VHDL. The design procedure and the simulated results are very useful in designing and implementing a practical RFID system. The RTL schematic view of the processor is achieved by successfully synthesizing the proposed design.KEYWORDS

  15. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  16. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  17. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  18. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  19. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  20. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  1. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  2. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  3. Design of a VLSI charge-coupled device analog delay line

    Science.gov (United States)

    Gedra, David R.

    1995-03-01

    Charge coupled devices (CCD's) are semiconductor devices which can transfer information, represented by a quantity of electrical charge, from one physical location of the semiconductor substrate to another in a controlled manner with the use of properly sequenced clock pulses. These devices can be applied to imaging, signal processing, logic, and digital storage applications. In this thesis, the design of an electrically stimulated CCD analog delay line, using the design tools currently available at the Naval Postgraduate School, is reported on. The major issues addressed are the electrode gate structure and composition, charge confinement techniques, and clocking schemes. Additionally, techniques for inpuning and detecting charge packets from the CCD register are examined. The Metal Oxide Semiconductor Integration Service (MOSIS) design rules only permit Bulk Channel Charge Couple Devices (BCCD's) to be lald out, and not Surface Channel Charge Coupled Devices (SCCD's). Restricted to a die size of 2.24 mm length, the electrode gates were chosen to be polysilicon polysilicon 8 micron length with 2 micron overlap and 20 micron width, giving the BCCD 64 stages. An on chip four phase clocking circuit with output drivers on each phase provides the control voltage for the gate electrodes. The small width of the BCCD delay line utilizes only a small portion of the available 2.22 mm die width. Therefore, four different BCCD's were designed in the layout. Two of the BCCD's have a p-diffusion stop to contain the charge laterally as it propagates along the channel while two BCCD's do not. Additionally, two of the BCCD's utilize the charge partition input technique with three control gates and two BCCD's use the dynamic current injection with one control gate.

  4. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  5. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  6. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  7. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  8. A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.

    Science.gov (United States)

    Tseng, Yu-Cheng; Hsu, Po-Hsiung; Chang, Tian-Sheuan

    2011-11-01

    This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.

  9. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    OpenAIRE

    Rita M. Shende; Pritesh R. Gumble

    2012-01-01

    Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the prod...

  10. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  11. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  12. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    Directory of Open Access Journals (Sweden)

    Rita M. Shende

    2012-01-01

    Full Text Available Analog-to-digital converters (ADCs are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since theADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially powerconsumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

  13. VLSI design of lossless frame recompression using multi-orientation prediction

    Science.gov (United States)

    Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

    2016-01-01

    Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

  14. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  15. Statistics on VLSI Designs.

    Science.gov (United States)

    1980-04-17

    been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE

  16. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  17. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  18. Physical database design using Oracle

    CERN Document Server

    Burleson, Donald K

    2004-01-01

    INTRODUCTION TO ORACLE PHYSICAL DESIGNPrefaceRelational Databases and Physical DesignSystems Analysis and Physical Database DesignIntroduction to Logical Database DesignEntity/Relation ModelingBridging between Logical and Physical ModelsPhysical Design Requirements Validation PHYSICAL ENTITY DESIGN FOR ORACLEData Relationships and Physical DesignMassive De-Normalization: STAR Schema DesignDesigning Class HierarchiesMaterialized Views and De-NormalizationReferential IntegrityConclusionORACLE HARDWARE DESIGNPlanning the Server EnvironmentDesigning the Network Infrastructure for OracleOracle Netw

  19. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  20. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  1. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  2. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  3. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  4. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  5. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  6. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  7. 超大规模集成电路可调试性设计综述%Survey of Design-for-Debug of VLSI

    Institute of Scientific and Technical Information of China (English)

    钱诚; 沈海华; 陈天石; 陈云霁

    2012-01-01

    随着硬件复杂度的不断提高和并行软件调试的需求不断增长,可调试性设计已经成为集成电路设计中的重要内容.一方面,仅靠传统的硅前验证已经无法保证现代超大规模复杂集成电路设计验证的质量,因此作为硅后验证重要支撑技术的可调试性设计日渐成为大规模集成电路设计领域的研究热点.另一方面,并行程序的调试非常困难,很多细微的bug无法直接用传统的单步、断点等方法进行调试,如果没有专门的硬件支持,需要耗费极大的人力和物力.全面分析了现有的可调试性设计,在此基础上归纳总结了可调试性设计技术的主要研究方向并介绍了各个方向的研究进展,深入探讨了可调试性结构设计研究中的热点问题及其产生根源,给出了可调试性结构设计领域的发展趋势.%Design-for-debug (DFD) has become an important feature of modern VLSI. On the one hand, traditional pre-silicon verification methods are not sufficient to enssure the quality of modern complex VLSI designs, thus employing DFD to facilitate post-silicon verification has attracted wide interests from both academia and industry; on the other hand, debugging parallel program is a worldwide difficult problem, which cries out for DFD hardware supports. In this paper, we analyze the existing structures of DFD comprehensively and introduce different fields of DFD for debugging hardware and software. These fields contain various kinds of DFD infrastructures, such as the DFD infrastructure for the pipe line of processor, the system-on-chips (SOC) and the networks on multi-cores processor. We also introduce the recent researches on how to design the DFD infrastructures with certain processor architecture and how to use the DFD infrastructures to solve the debug problems in these different fields. The topologic of the whole infrastructure, the hardware design of components, the methods of analyzing signals, the

  8. AN EXPANSIVE AND COMPARABLE STUDY OF EFFECTUAL ALGORITHMS FOR PLACEMENT IN PHYSICAL DESIGN

    Directory of Open Access Journals (Sweden)

    PRAGYA SHARMA

    2014-11-01

    Full Text Available This review paper consists of comprehensive study of VLSI algorithms for placement in physical design. The work has been classified under different perspectives like performance,area,wirelength,cost and power and the algorithms address the coverage and optimization of these factors. Placement is a major step for VLSI physical design as it involves placing the blocks on the chip with minimum possible area consumption however the initial placement is done by constructive placement algorithms such as constructive and iterative placement. Under the survey work which is done, the knowledge of placement algorithms with their merits and limitations has been provided so that according to the requirement one can choose the best algorithm. The survey involves simulation of different algorithms implemented in C and C++ programming languages. Tools from the EDA vendors have been provided for the simulation work so as to achieve the results and to have best possible outcomes. We survey the history of placement research, the progress achieved up to now, and outstanding challenges. Some future work has also been mentioned in which the research work can be carried upon.

  9. Physicality and Cooperative Design

    NARCIS (Netherlands)

    Vyas, Dhaval; Heylen, Dirk K.J.; Nijholt, Antinus; Popescu-Belis, Andrei; Stiefelhagen, Rainer

    2008-01-01

    CSCW researchers have increasingly come to realize that material work setting and its population of artefacts play a crucial part in coordination of distributed or co-located work. This paper uses the notion of physicality as a basis to understand cooperative work. Using examples from an ongoing

  10. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  11. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  12. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments practical design aspects

    CERN Document Server

    Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    1999-01-01

    We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).

  13. Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Adhiyaman P1 ,

    2014-03-01

    Full Text Available In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF and a novel embedded logic module (DDFF-ELM based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.

  14. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  15. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  16. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  17. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  18. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  19. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  20. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  1. A Method of Neural Network Controller Implementation in VLSI Design%将神经网络控制器用于VLSI设计的方法研究

    Institute of Scientific and Technical Information of China (English)

    詹璨铭

    2015-01-01

    This article presents an approach to neural network implementation in VLSI ,which is called as neural network controller based on Petri net .The structure of the neurons in the network is uniform ;it is triggered by external events ,and output place and transition signals of petri net .Two types of neurons are introduced ,one is standing for serial process ,and the other is used in synchronization of processes .The dual types of neurons are chained together by stimulate inputs ,and compose the fabric .The controller is designed to conquer the side effects of state machine ,and improves the performance and reliability .Typically ,the controller is a precise description of the circuits .It is optimized to timing closure against constraints much easier than state machine .Reduplication of each node in neural network decrease single event upset (SEU) .Finally ,the controller is easy to rebuild .The new design flow has applied in practice ,and proved effectively .%探索在超大规模集成电路中应用神经网络控制器的方法.根据Petri网理论,将库所与变迁组合成神经节点,节点通过输入触发信号链接组成复杂控制网络.定义两种类型神经节点,一种是节点组成串行分枝,另外一种用于同步并发分枝.通过两种节点组合,形成三种基本网络结构,三种结构再次组合又可形成任意复杂控制器结构.根据控制器分枝内串行、分枝间并行的特点,设计编译软件,输入更抽象的分枝描述代码,自动生成对应神经网络控制器逻辑电路描述代码.VLSI设计中使用神经网络控制器,能够更接近了寄存器传输级电路,以及更精确地描述电路,还能提高设计性能与可靠性.复制神经节点减小单节点负载,可优化电路时序;复制节点还可构成冗余缓解空间单粒子翻转.神经网络控制器可以处理各种异常情况,提高功能容错性和可维护性.这种方法已经用

  2. A Coherent VLSI Design Environment

    Science.gov (United States)

    1987-12-31

    April 1, L0 A Mastiplexd Switched-Capacitor Filter Bank, Patrick Bosshart, MIT April 8, IM Analog Circuits in DOS PSI, Yannis Tsividis , Columbia...A.I. (Analog Intelligence), Yanni Tsividis , Columbia University, New York, NY December 2,1986 The Semiconductor Industry (Losing Sight of Your Added...Dept. of Elec. Eng. & Comp. Sci. 3:50 Yannis Tsividis and Dimitri A. Antoniadis, "A Mulitproject Chip i Approach to the Teaching of Analog MOS LSI and

  3. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-09-30

    85-257, September, 1985. e b . . B% V" 4 pathway in bipolar logic. ii) finding a rational and easily automated method for modeling the driving-point...where the resistors are fixed, there is no internodal coupling capacitance, the pullup and pulldown networks have no internal capacitance, and the

  4. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  5. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  6. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  7. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  8. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  9. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  10. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  11. 用于混合信号VLSI的可扩展JTAG控制器IP核设计%Design of Extendable JTAG Controller IP Core for Mixed-signal VLSI

    Institute of Scientific and Technical Information of China (English)

    段延亮; 魏廷存; 高武; 许望洋

    2012-01-01

    The front-end read-out circuit for Positron Emission Tomography(PET) imaging system is a kind of digital-analog mixed-signal VLSI.Based on the features of multi-channel and high performances of these kinds of chip,the JTAG controller is adopted to realize the initial control and auxiliary test of the chip.An extendable JTAG controller IP core is designed using TSMC 0.18 μm CMOS process,which supports 14 groups of extendable control signal and also supports the reading and writing operations of 16 multi-bits registers scan chains,and joins with the customized substrate driving software.The designed JTAG controller IP core can be also used for the controlling and testing of other mixed-signal VLSI,and has good universality and engineering usage.%正电子发射断层成像系统(PET)前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值.

  12. Framework for Managing the Very Large Scale Integration Design Process

    Directory of Open Access Journals (Sweden)

    Sabah Al-Fedaghi

    2012-01-01

    Full Text Available Problem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as control flow and data structure. It was important to fill the gap between these two levels of description because VLSI chip manufacturing was a complex management project and providing a conceptual detailed depiction of the design process would assist in managing operations on the great number of generated artifacts. Approach: This study introduces a conceptual framework representing flows and transformations of various descriptions (e.g., circuits, technical sketches to be used as a tracking apparatus for directing traffic during the VLSI design process. The proposed methodology views a description as an integral element of a process, called a flow system, constructed from six generic operations and designed to handle descriptions. It draws maps of flows of representations (called flowthings that run through the design flow. These flowthings are created, transformed (processed, transferred, released and received by various functions along the design flow at different levels (a hierarchy. The resultant conceptual framework can be used to support designers with computer-aided tools to organize and manage chains of tasks. Results: The proposed model for managing the VLSI design process was characterized by being conceptual (no technical or implementation details and can be uniformly applied at different levels of design and to various kinds of artifacts. The methodology is applied to describe the VLSI physical design stage that includes partitioning, floorplanning and placement, routing, compaction and extraction

  13. 2-D DCT Algorithm and Its Reduced VLSI Design%二维DCT算法及其精简的VLSI设计

    Institute of Scientific and Technical Information of China (English)

    陈伟; 卢贵主; 郑灵翔

    2008-01-01

    采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.

  14. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  15. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  16. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  17. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  18. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  19. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  20. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

  1. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  2. A Coherent VLSI Environment

    Science.gov (United States)

    1987-03-31

    smallest and largest eigenvalues of YH and AminAH and Am,..AH represent the smallest and largest eigenvalues of YAH, respectively. Fig. 3b illustrates a...101, Princeton U. Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International

  3. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  4. Experiment Design and Analysis Guide - Neutronics & Physics

    Energy Technology Data Exchange (ETDEWEB)

    Misti A Lillo

    2014-06-01

    The purpose of this guide is to provide a consistent, standardized approach to performing neutronics/physics analysis for experiments inserted into the Advanced Test Reactor (ATR). This document provides neutronics/physics analysis guidance to support experiment design and analysis needs for experiments irradiated in the ATR. This guide addresses neutronics/physics analysis in support of experiment design, experiment safety, and experiment program objectives and goals. The intent of this guide is to provide a standardized approach for performing typical neutronics/physics analyses. Deviation from this guide is allowed provided that neutronics/physics analysis details are properly documented in an analysis report.

  5. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  6. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  7. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  8. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  9. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  10. Quantum circuit physical design methodology with emphasis on physical synthesis

    Science.gov (United States)

    Mohammadzadeh, Naser; Saheb Zamani, Morteza; Sedighi, Mehdi

    2013-11-01

    In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging and auxiliary qubit selection) to demonstrate the effectiveness of the physical synthesis. However, the previous contributions focused mainly on the physical synthesis concept, and the techniques were proposed only as a proof of concept. In this paper, we propose a methodological framework for physical synthesis that involves all previously proposed techniques along with a newly introduced one (called auxiliary qubit insertion). We will show that the entire flow can be seen as one monolithic methodology. The proposed methodology is analyzed using a large set of benchmarks. Experimental results show that the proposed methodology decreases the average latency of quantum circuits by about 36.81 % for the attempted benchmarks.

  11. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  12. Physical Activity Design Guidelines for School Architecture.

    Directory of Open Access Journals (Sweden)

    Jeri Brittin

    Full Text Available Increasing children's physical activity at school is a national focus in the U.S. to address childhood obesity. While research has demonstrated associations between aspects of school environments and students' physical activity, the literature currently lacks a synthesis of evidence to serve as a practical, spatially-organized resource for school designers and decision-makers, as well as to point to pertinent research opportunities. This paper describes the development of a new practical tool: Physical Activity Design Guidelines for School Architecture. Its aims are to provide architects and designers, as well as school planners, educators, and public health professionals, with strategies for making K-12 school environments conducive to healthy physical activity, and to engage scientists in transdisciplinary perspectives toward improved knowledge of the school environment's impact. We used a qualitative review process to develop evidence-based and theory-driven school design guidelines that promote increased physical activity among students. The design guidelines include specific strategies in 10 school design domains. Implementation of the guidelines is expected to enable students to adopt healthier physical activity behaviors. The tool bridges a translational gap between research and environmental design practice, and may contribute to setting new industry and education standards.

  13. Physical Activity Design Guidelines for School Architecture

    Science.gov (United States)

    Brittin, Jeri; Sorensen, Dina; Trowbridge, Matthew; Lee, Karen K.; Breithecker, Dieter; Frerichs, Leah; Huang, Terry

    2015-01-01

    Increasing children’s physical activity at school is a national focus in the U.S. to address childhood obesity. While research has demonstrated associations between aspects of school environments and students’ physical activity, the literature currently lacks a synthesis of evidence to serve as a practical, spatially-organized resource for school designers and decision-makers, as well as to point to pertinent research opportunities. This paper describes the development of a new practical tool: Physical Activity Design Guidelines for School Architecture. Its aims are to provide architects and designers, as well as school planners, educators, and public health professionals, with strategies for making K-12 school environments conducive to healthy physical activity, and to engage scientists in transdisciplinary perspectives toward improved knowledge of the school environment’s impact. We used a qualitative review process to develop evidence-based and theory-driven school design guidelines that promote increased physical activity among students. The design guidelines include specific strategies in 10 school design domains. Implementation of the guidelines is expected to enable students to adopt healthier physical activity behaviors. The tool bridges a translational gap between research and environmental design practice, and may contribute to setting new industry and education standards. PMID:26230850

  14. Physical Activity Design Guidelines for School Architecture.

    Science.gov (United States)

    Brittin, Jeri; Sorensen, Dina; Trowbridge, Matthew; Lee, Karen K; Breithecker, Dieter; Frerichs, Leah; Huang, Terry

    2015-01-01

    Increasing children's physical activity at school is a national focus in the U.S. to address childhood obesity. While research has demonstrated associations between aspects of school environments and students' physical activity, the literature currently lacks a synthesis of evidence to serve as a practical, spatially-organized resource for school designers and decision-makers, as well as to point to pertinent research opportunities. This paper describes the development of a new practical tool: Physical Activity Design Guidelines for School Architecture. Its aims are to provide architects and designers, as well as school planners, educators, and public health professionals, with strategies for making K-12 school environments conducive to healthy physical activity, and to engage scientists in transdisciplinary perspectives toward improved knowledge of the school environment's impact. We used a qualitative review process to develop evidence-based and theory-driven school design guidelines that promote increased physical activity among students. The design guidelines include specific strategies in 10 school design domains. Implementation of the guidelines is expected to enable students to adopt healthier physical activity behaviors. The tool bridges a translational gap between research and environmental design practice, and may contribute to setting new industry and education standards.

  15. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  16. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  17. Modern Physics Buildings, Design and Function.

    Science.gov (United States)

    Palmer, R. Ronald; Rice, William Maxwell

    In order to serve college administrators, architects and physics educators, a collection was made of material reflecting the state-of-the-art of physics building design. This body of material, including drawings, diagrams, and photographs, resulted largely from extensive interviews with about 50 institutions who had recently built such facilities.…

  18. Physical Science Day: Design, Implementation, and Assessment

    Science.gov (United States)

    Zeng, Liang; Cunningham, Mark A.; Tidrow, Steven C.; Smith, K. Christopher; Contreras, Jerry

    2016-01-01

    Physical Science Day at The University of Texas--Pan American (UTPA), in collaboration with the Edinburg Consolidated Independent School District, has been designed, developed and implemented to address an identified fundamental shortcoming in our educational process within this primarily (90+%) Hispanic serving border region. Physical Science Day…

  19. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  20. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  1. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  2. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  3. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  4. Statistical Physics of Vaccine Design

    Science.gov (United States)

    Deem, Michael

    2009-03-01

    I will define a new parameter to quantify the antigenic distance between two H3N2 influenza strains. I will use this parameter to measure antigenic distance between circulating H3N2 strains and the closest vaccine component of the influenza vaccine. For the data between 1971 and 2004, the measure of antigenic distance correlates better with efficacy in humans of the H3N2 influenza A annual vaccine than do current state of the art measures of antigenic distance such as phylogenetic sequence analysis or ferret antisera inhibition assays. I suggest that this measure of antigenic distance can be used to guide the design of the annual flu vaccine. I will describe combining this measure of antigenic distance with a multiple-strain avian influenza transmission model to study the threat of simultaneous introduction of multiple avian influenza strains. For H3N2 influenza, the model is validated against observed viral fixation rates and epidemic progression rates from the World Health Organization FluNet - Global Influenza Surveillance Network. I find that a multiple-component avian influenza vaccine is helpful to control a simultaneous multiple introduction of bird-flu strains. I introduce Population at Risk (PaR) to quantify the risk of a flu pandemic, and calculate by this metric the improvement that a multiple vaccine offers.

  5. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  6. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  7. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 2: Hardware design verification

    Science.gov (United States)

    Carlan, A. J.; Breuer, M. A.

    1982-10-01

    The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

  8. Designing physics video hooks for science students

    Science.gov (United States)

    McHugh, M.; McCauley, V.

    2016-01-01

    This paper offers an insight into the design structure of physics video hooks that were developed by the Science Education Resource design team in the school of education (SOE) in National University of Ireland, Galway (NUI Galway). A hook, is an instructional technique used to stimulate student attention (Hunter 1994, Lemov 2010), interest (Jewett 2013) and engagement (McCrory 2011, Riendeau 2013). The physics video hooks followed a design framework that is illustrated below by breaking down the centre of gravity (COG) hook. Various design principles and elements embedded within the COG hook are presented with examples and the time they occur within the video. The intention of this article is that the design can be replicated and modified to aid teachers and designers in the development of a multitude of classroom based multimedia resources.

  9. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Sudarshan Tiwari

    2012-05-01

    Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.

  10. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  11. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  12. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  13. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  14. Distinct rhythmic locomotor patterns can be generated by a simple adaptive neural circuit: biology, simulation, and VLSI implementation.

    Science.gov (United States)

    Ryckebusch, S; Wehr, M; Laurent, G

    1994-12-01

    Rhythmic motor patterns can be induced in leg motor neurons of isolated locust thoracic ganglia by bath application of pilocarpine. We observed that the relative phases of levators and depressors differed in the three thoracic ganglia. Assuming that the central pattern generating circuits underlying these three segmental rhythms are probably very similar, we developed a simple model circuit that can produce any one of the three activity patterns and characteristic phase relationships by modifying a single synaptic weight. We show results of a computer simulation of this circuit using the neuronal simulator NeuraLOG/Spike. We built and tested an analog VLSI circuit implementation of this model circuit that exhibits the same range of "behaviors" as the computer simulation. This multidisciplinary strategy will be useful to explore the dynamics of central pattern generating networks coupled to physical actuators, and ultimately should allow the design of biologically realistic walking robots.

  15. The Creative Design of Physical Rehabilitation Games

    OpenAIRE

    QUINTEN, Niels; Malliet, Steven; Coninx, Karin

    2014-01-01

    This working example describes a research project on digital games which assist stroke survivors in learning once more the physical abilities they lost during a stroke (e.g. drinking from a glass). Specifically, we aim to create a more engaging learning experience adapted to the needs and disabilities of stroke patients. Our focus lies on the creative design of these games.

  16. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  17. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  18. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  19. Advances in VLSI testing at MultiGb per second rates

    Directory of Open Access Journals (Sweden)

    Topisirović Dragan

    2005-01-01

    Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

  20. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  1. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  2. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  3. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  4. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  5. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  6. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  7. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  8. Physics design of SSRF synchrotron radiation security

    Institute of Scientific and Technical Information of China (English)

    XU Yi; DAI Zhi-Min; LIU Gui-Min

    2009-01-01

    High brightness of SSRF brings about synchrotron radiation security problems,which will be solved in physics design.The main radiations are generated from bending magnets and insertion devices.Since the fact that radiation power and radiating area are different in these two kinds of synchrotron radiation,the arrangements of photon absorbers,diaphragms and other vacuum components need to be treated distinctively.In addition.SSRF interlock protection threshold is defined and the beam orbit in the straight line is limited.Hence.beam orbit in the bending magnets and IDs are also restricted by the threshold.The orbit restriction is calculated and helps us to arrange the vacuum components.In this paper,beam orbit distortion restricted by interlock protection threshold,radiation power,radiation angle and illuminating area are calculated.From the calculation results,the physics designs in manufacture and installation vacuum components are put forward.By commissioning,it is shown that physics requirements are met rigidly in the engineering process.

  9. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  10. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  11. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  12. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  13. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  14. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  15. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  16. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  17. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  18. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  19. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  20. Physics Considerations in the Design of NCSX

    Energy Technology Data Exchange (ETDEWEB)

    G.H. Neilson; M.C. Zarnstorff; L.P. Ku; E.A. Lazarus; P.K. Mioduszewski; M. Fenstermacher; E. Fredrickson; G.Y. Fu; A. Grossman; P.J. Heitzenroeder; R.H. Hatcher; S.P. Hirshman; S.R. Hudson; D.W. Johnson; H.W. Kugel; J.F. Lyon; R. Majeski; D.R. Mikkelsen; D.A. Monticello; B.E. Nelson; N. Pomphrey; W.T. Reiersen; A.H. Reiman; P.H. Rutherford; J.A. Schmidt; D.A. Spong; D.J. Strickler

    2002-10-09

    Compact stellarators have the potential to make steady-state, disruption-free magnetic fusion systems with beta approximately 5% and relatively low aspect ratio (R/ < 4.5) compared to most drift-optimized stellarators. Magnetic quasi-symmetry can be used to reduce orbit losses. The National Compact Stellarator Experiment (NCSX) is designed to test compact stellarator physics in a high-beta quasi-axisymmetric configuration and to determine the conditions for high-beta disruption-free operation. It is designed around a reference plasma with low ripple, good magnetic surfaces, and stability to the important ideal instabilities at beta approximately 4%. The device size, available heating power, and pulse lengths provide access to a high-beta target plasma state. The NCSX has magnetic flexibility to explore a wide range of equilibrium conditions and has operational flexibility to achieve a wide range of beta and collisionality values. The design provides space to accommodate plasma-facing components for divertor operation and ports for an extensive array of diagnostics.

  1. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  2. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  3. Physics Buildings Today. A Supplement to Modern Physics Buildings: Design and Function.

    Science.gov (United States)

    American Inst. of Physics, New York, NY.

    This supplement to "Modern Physics Buildings: Design and Function" is intended as an aid to physics department faculties, administrators, and architects responsible for designing new science buildings. It provides descriptions of 26 new physics buildings and science buildings with physics facilities. Presented are (1) floor plans, (2)…

  4. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  5. Designing Learning Environments to Teach Interactive Quantum Physics

    Science.gov (United States)

    Puente, Sonia M. Gomez; Swagten, Henk J. M.

    2012-01-01

    This study aims at describing and analysing systematically an interactive learning environment designed to teach Quantum Physics, a second-year physics course. The instructional design of Quantum Physics is a combination of interactive lectures (using audience response systems), tutorials and self-study in unit blocks, carried out with small…

  6. Designing Learning Environments to Teach Interactive Quantum Physics

    Science.gov (United States)

    Puente, Sonia M. Gomez; Swagten, Henk J. M.

    2012-01-01

    This study aims at describing and analysing systematically an interactive learning environment designed to teach Quantum Physics, a second-year physics course. The instructional design of Quantum Physics is a combination of interactive lectures (using audience response systems), tutorials and self-study in unit blocks, carried out with small…

  7. New physical model design for Vapex experiments

    Energy Technology Data Exchange (ETDEWEB)

    Yazdani, A.; Maini, B.B. [Calgary Univ., AB (Canada)

    2004-07-01

    Solvent extraction is gaining much attention as an in-situ recovery method for difficult to produce heavy oil and tar sand deposits. Vapour extraction (VAPEX) is similar to the steam assisted gravity drainage (SAGD) process used in heavy oil production. In VAPEX, vaporized solvents are used instead of high temperature steam and the viscosity of the oil is reduced in situ. VAPEX is well suited for formations that are thin and where heat losses are unavoidable. It can be applied in the presence of overlying gas caps; bottom water aquifers; low thermal conductivity; high water saturation; clay swelling; and, formation damage. Modelling studies that use rectangular shaped models are limited at high reservoir pressures. This study presents a new design of physical models that overcomes this limitation. The annular space between two cylindrical pipes is used for developing slice-type and sand-filled models. This newly developed model is more compatible with high pressure. This paper compares results of VAPEX experiments using the cylindrical models and the rectangular models. The stabilized drainage rates from the newly developed cylindrical models are in very good agreement with those from the rectangular models. 16 refs., 3 tabs., 11 figs.

  8. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  9. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  10. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  11. 低成本可调FFT处理器的超大规模集成电路设计%Low Cost VLSI Design of a Flexible FFT Processor

    Institute of Scientific and Technical Information of China (English)

    戴亦奇

    2011-01-01

    In this paper, a radix-22/23 based pipeline structure is presented, in order to implement a low-cost VLSI fast Fourier transform (FFT) processor. As well as reducing the steps of normal complex multiplications, it minimizes the memory words to get the FFT results with the single-path delay feedback (SDF) memory access method. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements.%文章提出了一种以基-22/23为基础的流水线结构,用以实现低成本、超大规模集成电路(VLSI)的快速傅里叶变换(FFT)处理器设计。该处理器在减少普通复数乘法器级数的同时,通过单路延时反馈(SDF)存取方式,以最少的存储字来获得FFT结果。对于数据通路,我们采用了混合浮点的数据缩放方式,在保证信噪比的同时,降低了数据长度和RAM容量的需求。

  12. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  13. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  14. Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac%面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现

    Institute of Scientific and Technical Information of China (English)

    潘志鹏; 吴斌; 尉志伟; 叶甜春

    2015-01-01

    针对IEEE 802.11i协议中多种安全协议实现进行研究,结合以IEEE 802.11ac协议为代表的下一代无线局域网( WLAN)系统对高吞吐率的需求,提出了一种支持WEP/TKIP/CCMP协议的多模、高速安全加速引擎的大规模集成电路( VLSI)架构. 提出了基于哈希算法的密钥信息查找算法,缩小了查找时钟延迟. 基于复合域的运算方式实现高级加密标准( AES)算法,提出双AES运算核的并行架构实现计数器与密码分组链接( CCM)模式,提升运算吞吐率的同时也降低了引擎的响应延迟. 经过FPGA实现和ASIC流片验证表明,该安全加速引擎具备可重构性,处理延迟仅为33个时钟周期,在322 MHz工作频率下运算吞吐率可达3.747 Gbit/s.%In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration ( VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP proto-cols was presented taking into account the demand for high throughput of the next generation wireless local area net-work ( WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryp-tion standard ( AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code ( CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz.

  15. Teaching for physical literacy: Implications to instructional design and PETE

    Directory of Open Access Journals (Sweden)

    Stephen Silverman

    2015-06-01

    Full Text Available Physical education teachers play an important role in helping students' development of the motor skills needed to be physically literate individuals. Research suggests that teacher made instructional design decisions can lead to enhanced motor skill learning. After presenting a model of evidence-based research this paper presents information that will help teachers plan and execute lessons designed to improve students' motor skills. Variables that impact motor skill learning in physical education including time, type of practice, content, presentation and organizational strategies, and student skill level are presented and discussed. A brief section on student attitudes, their relation to motor skill learning and to physical literacy is included. Motor skills are needed for physically literate people to enjoy lifelong physical activity. Physical education teachers and the decisions they make contribute to students' learning and whether the goal of physical literacy is met.

  16. Physical design method of MPSoC

    Institute of Scientific and Technical Information of China (English)

    LIU Peng; XIA Bing-jie; TENG Zhao-wei

    2007-01-01

    Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.

  17. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  18. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  19. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  20. Designing Flight Experiments for Hypersonic Flow Physics

    OpenAIRE

    Longo, J.M.A.; Eggers, Th.; Gülhan, A.; Turner, J.; Weihs, H.

    2005-01-01

    A major problem of concen for the success of physical-modelling resides in the availability of experimental data for model validation, particularly in the hot hypersonic regime. In the past, validation data have been achieved as secondary product of expensive space-transportation programs. Since in the last ten years there has been almost no successfull program due to lack of investment, no new experimental data are available. According, a new trend is emerging for low cost technology vali...

  1. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  2. A Physical Approach to Tangible Interaction Design

    DEFF Research Database (Denmark)

    Jensen, Mads Vedel

    2007-01-01

    The field of tangible interaction is growing in rich and diverse directions calling for new forms of understanding. In this paper I will present a view on tangible interaction that has a strong focus on movement and interaction qualities. I will describe a design exercise that transfers interaction...... qualities identified from user observations made in particular contexts to the design of new interaction modalities. The exercise was completed with 16 graduate students and resulted in a set of interactive sculptures that aim to convey particular interaction experiences. I will introduce the process...

  3. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  4. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  5. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  6. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  7. Physics Design for ARIES-CS

    Energy Technology Data Exchange (ETDEWEB)

    L.P. Ku, P.R. Garabedian, J. Lyon, A. Turnbull, A. Grossman, T.K. Mau, M. Zarnstorff, and the ARIES Team

    2007-10-10

    Novel stellarator configurations have been developed for ARIES-CS. These configurations are optimized to provide good plasma confinement and flux surface integrity at high beta. Modular coils have been designed for them in which the space needed for the breeding blanket and radiation shielding was specifically targeted such that reactors generating GW electrical powers would require only moderate major radii (<10 m). These configurations are quasi-axially symmetric in the magnetic field topology and have small number of field periods (≤3) and low aspect ratios (≤6). The baseline design chosen for detailed systems and power plant studies has 3 field periods, aspect ratio 4.5 and major radius 7.5 m operating at β~6.5% to yield 1 GW electric power. The shaping of the plasma accounts for ≥75% of the rotational transform. The effective helical ripples are very small (< 0.6% everywhere) and the energy loss of alpha particles is calculated to be ≤5% when operating in high density regimes. An interesting feature in this configuration is that instead of minimizing all residues in the magnetic spectrum, we preferentially retained a small amount of the non-axisymmetric mirror field. The presence of this mirror and its associated helical field alters the ripple distribution, resulting in the reduced ripple-trapped loss of alpha particles despite the long connection length in a tokamak-like field structure. Additionally, we discuss two other potentially attractive classes of configurations, both quasi-axisymmetric: one with only two field periods, very low aspect ratios (~2.5), and less complex coils, and the other with the plasma shaping designed to produce low shear rotational transform so as to assure the robustness and integrity of flux surfaces when operating at high β.

  8. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  9. Security Implications of Physical Design Attributes in the Emergency Department.

    Science.gov (United States)

    Pati, Debajyoti; Pati, Sipra; Harvey, Thomas E

    2016-07-01

    Security, a subset of safety, is equally important in the efficient delivery of patient care. The emergency department (ED) is susceptible to violence creating concerns for the safety and security of patients, staff, and visitors and for the safe and efficient delivery of care. Although there is an implicit and growing recognition of the role of the physical environment, interventions typically have been at the microlevel. The objective of this study was to identify physical design attributes that potentially influence safety and efficiency of ED operations. An exploratory, qualitative research design was adopted to examine the efficiency and safety correlates of ED physical design attributes. The study comprised a multimeasure approach involving multidisciplinary gaming, semistructured interviews, and touring interviews of frontline staff in four EDs at three hospital systems across three states. Five macro physical design attributes (issues that need to be addressed at the design stage and expensive to rectify once built) emerged from the data as factors substantially associated with security issues. They are design issues pertaining to (a) the entry zone, (b) traffic management, (c) patient room clustering, (d) centralization versus decentralization, and (e) provisions for special populations. Data from this study suggest that ED security concerns are generally associated with three sources: (a) gang-related violence, (b) dissatisfied patients, and (c) behavioral health patients. Study data show that physical design has an important role in addressing the above-mentioned concerns. Implications for ED design are outlined in the article. © The Author(s) 2016.

  10. LTA Physics Design: Description of All MOX Pin LTA Design

    Energy Technology Data Exchange (ETDEWEB)

    Pavlovichev, A.M.

    2001-09-28

    In this document issued according to Work Release 02. P. 99-lb the results of neutronics studies of <<100%Pu>> MOX LTA design are presented. The parametric studies of infinite MOX-UOX grids, MOX-UOX core fragments and of VVER-1000 core with 3 MOX LTAs are performed. The neutronics parameters of MOX fueled core have been performed for the chosen design MOX LTA using the Russian 3D code BIPR-7A and 2D code PERMAK-A with the constants prepared by the cell spectrum code TVS-M.

  11. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  12. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  13. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  14. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  15. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  16. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  17. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  18. Guided exploration of physically valid shapes for furniture design

    KAUST Repository

    Umetani, Nobuyuki

    2012-07-01

    Geometric modeling and the physical validity of shapes are traditionally considered independently. This makes creating aesthetically pleasing yet physically valid models challenging. We propose an interactive design framework for efficient and intuitive exploration of geometrically and physically valid shapes. During any geometric editing operation, the proposed system continuously visualizes the valid range of the parameter being edited. When one or more constraints are violated after an operation, the system generates multiple suggestions involving both discrete and continuous changes to restore validity. Each suggestion also comes with an editing mode that simultaneously adjusts multiple parameters in a coordinated way to maintain validity. Thus, while the user focuses on the aesthetic aspects of the design, our computational design framework helps to achieve physical realizability by providing active guidance to the user. We demonstrate our framework on plankbased furniture design with nail-joint and frictional constraints. We use our system to design a range of examples, conduct a user study, and also fabricate a physical prototype to test the validity and usefulness of the system. © 2012 ACM 0730-0301/2012/08- ART86.

  19. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  20. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  1. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  2. Advances in the physics basis for the European DEMO design

    Science.gov (United States)

    Wenninger, R.; Arbeiter, F.; Aubert, J.; Aho-Mantila, L.; Albanese, R.; Ambrosino, R.; Angioni, C.; Artaud, J.-F.; Bernert, M.; Fable, E.; Fasoli, A.; Federici, G.; Garcia, J.; Giruzzi, G.; Jenko, F.; Maget, P.; Mattei, M.; Maviglia, F.; Poli, E.; Ramogida, G.; Reux, C.; Schneider, M.; Sieglin, B.; Villone, F.; Wischmeier, M.; Zohm, H.

    2015-06-01

    In the European fusion roadmap, ITER is followed by a demonstration fusion power reactor (DEMO), for which a conceptual design is under development. This paper reports the first results of a coherent effort to develop the relevant physics knowledge for that (DEMO Physics Basis), carried out by European experts. The program currently includes investigations in the areas of scenario modeling, transport, MHD, heating & current drive, fast particles, plasma wall interaction and disruptions.

  3. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  4. The program structure designing and optimizing tests of GRAPES physics

    Institute of Scientific and Technical Information of China (English)

    XU GuoQiang; WANG ShiYu; CHEN DeHui; XUE JiShan; SUN Jian; SHEN XueShun; SHEN YuanFang; HUANG LiPing; WU XiangJun; ZHANG HongLiang

    2008-01-01

    According to the modularization and standardization of program structure in Global/Regional Assimi-lation and Prediction System (GRAPES), the plug-compatible and transplantable regional meso-scale and global middle-range physics software package is established, The package's component integrality is comparative with the other advanced models physics. A three-level structure of connecting GRAPES physics and dynamic frame has been constructed. The friendly interface is designed for users to plug in their own physics packages. Phenomenon of grid-point storm rainfall in numerical prediction is analyzed with the numerical tests. The scheme of air vertical velocity calculation is improved. Opti-mizing tests of physics schemes are performed with the correlative parameters adjusting. The results show that the false grid-point storm rainfall is removed by precipitation scheme improving. Then the score of precipitation forecast is enhanced.

  5. Neighborhood Design, Physical Activity, and Wellbeing: Applying the Walkability Model.

    Science.gov (United States)

    Zuniga-Teran, Adriana A; Orr, Barron J; Gimblett, Randy H; Chalfoun, Nader V; Guertin, David P; Marsh, Stuart E

    2017-01-13

    Neighborhood design affects lifestyle physical activity, and ultimately human wellbeing. There are, however, a limited number of studies that examine neighborhood design types. In this research, we examine four types of neighborhood designs: traditional development, suburban development, enclosed community, and cluster housing development, and assess their level of walkability and their effects on physical activity and wellbeing. We examine significant associations through a questionnaire (n = 486) distributed in Tucson, Arizona using the Walkability Model. Among the tested neighborhood design types, traditional development showed significant associations and the highest value for walkability, as well as for each of the two types of walking (recreation and transportation) representing physical activity. Suburban development showed significant associations and the highest mean values for mental health and wellbeing. Cluster housing showed significant associations and the highest mean value for social interactions with neighbors and for perceived safety from crime. Enclosed community did not obtain the highest means for any wellbeing benefit. The Walkability Model proved useful in identifying the walkability categories associated with physical activity and perceived crime. For example, the experience category was strongly and inversely associated with perceived crime. This study provides empirical evidence of the importance of including vegetation, particularly trees, throughout neighborhoods in order to increase physical activity and wellbeing. Likewise, the results suggest that regular maintenance is an important strategy to improve mental health and overall wellbeing in cities.

  6. Neighborhood Design, Physical Activity, and Wellbeing: Applying the Walkability Model

    Directory of Open Access Journals (Sweden)

    Adriana A. Zuniga-Teran

    2017-01-01

    Full Text Available Neighborhood design affects lifestyle physical activity, and ultimately human wellbeing. There are, however, a limited number of studies that examine neighborhood design types. In this research, we examine four types of neighborhood designs: traditional development, suburban development, enclosed community, and cluster housing development, and assess their level of walkability and their effects on physical activity and wellbeing. We examine significant associations through a questionnaire (n = 486 distributed in Tucson, Arizona using the Walkability Model. Among the tested neighborhood design types, traditional development showed significant associations and the highest value for walkability, as well as for each of the two types of walking (recreation and transportation representing physical activity. Suburban development showed significant associations and the highest mean values for mental health and wellbeing. Cluster housing showed significant associations and the highest mean value for social interactions with neighbors and for perceived safety from crime. Enclosed community did not obtain the highest means for any wellbeing benefit. The Walkability Model proved useful in identifying the walkability categories associated with physical activity and perceived crime. For example, the experience category was strongly and inversely associated with perceived crime. This study provides empirical evidence of the importance of including vegetation, particularly trees, throughout neighborhoods in order to increase physical activity and wellbeing. Likewise, the results suggest that regular maintenance is an important strategy to improve mental health and overall wellbeing in cities.

  7. An instructional design for online college physics laboratories

    Science.gov (United States)

    Ruby, Gail G.

    Online learner-centered self-directed educational opportunities are growing in scope and acceptance across the academic curriculum because of the flexibility for the learner and cost-effectiveness for the institution. However the offering of online science courses and particularly physics instruction has lagged behind due to the challenge of re-creating the hands-on laboratory learning experience. This research examines the effectiveness of the design of a series of physics laboratory experiments for potential online delivery which provide learners with hands on experiences. Two groups of college physics learners conducted physics experiments inside and outside of the physical laboratory using instructions and equipment provided in a kit. Learning outcomes as determined by pretest, written laboratory report, and posttest assessments and learner reactions as determined by a questionnaire were utilized to compare both types of laboratory experiences. The research findings indicated learning outcomes achieved by learners outside of the physical laboratory were statistically greater than the equivalent face-to-face instruction. Evidence from learner reactions comparing both types of laboratory formats indicated learner preference for the online laboratory format. These results are an initial contribution to the design of an entire sequence of experiments that can be performed independently by online learners outside of the laboratory satisfying the laboratory requirement for the two semester college physics course.

  8. 一种深亚微米复杂芯片物理设计的时序收敛方法%A Method of Timing Closure in Deep Submicron Physical Design of Complex Chip

    Institute of Scientific and Technical Information of China (English)

    郑天华; 梁利平

    2013-01-01

    The deep submicron technology presents lots of challenges to the physical design of VLSI ,the key to timing closure is the interconnect delay and crosstalk . A method based on re-synthesis , region constraints and crosstalk prevent is presented to resolved the timing closure problem of physical design in the paper .The method is verified by design a 5 .3 million gate multi-core DSP chip in 65nm technology .The design example demonstrate that the method efficiently solves the interconnect delay and crosstalk ,and achieves timing closure .%深亚微米工艺下超大规模芯片的物理设计面临很多挑战,互连延时和串扰效应成为影响时序收敛的关键因素。文中介绍了一种采用二次综合、区域约束和串扰预防等措施实现渐进式时序收敛的方法。在65纳米工艺下,通过530万门多核DSP芯片设计验证了该方法。实例设计结果表明,这种方法可以有效地解决互连延时和串扰问题,实现复杂芯片的时序收敛。

  9. Introduction to the overall physics design of CSNS accelerators

    Institute of Scientific and Technical Information of China (English)

    WANG Sheng; FANG Shou-Xian; FU Shi-Nian; LIU Wei-Bin; OUYANG Hua-Fu; QIN Qing; TANG Jing-Yu; WEI Jie

    2009-01-01

    The China Spallation Neutron Source(CSNS)is an accelerator-based facility.The accelerator of CSNS consists of a low energy linac,a Rapid Cycling Synchrotron(RCS)and two beam transport lines.The overall physits design of CSNS accelerator is described,including the design principle,the choice of the main parameters and design of each part of accelerators.The key problems of the physics design,such as beam loss and control,are also discussed.The interface between the different parts of accelerator,as well as between accelerator and target,are introduced.

  10. Physics calculations for charge design at Savannah River

    Energy Technology Data Exchange (ETDEWEB)

    Sharp, D.A.

    1976-01-01

    The physics calculations used at Savannah River for charge design are described. A standard computational system, composed of modular computer codes and a data base, is used for routine design studies. Its primary functions consist of lattice and charge analysis. The system is supplemented by empirical procedures to improve its accuracy. Auxiliary computational techniques are employed, along with the standard system, for design of new assemblies and charge types. With these supplements, the standard system is sufficiently accurate and efficient to meet the current design needs of Savannah River.

  11. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  12. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  13. An Access Path Model for Physical Database Design.

    Science.gov (United States)

    1979-12-28

    target system. 4.1 Algebraic Structure for Physical Design For the purposes of implementation-oriented design, we shall use the logical access paths...subsection, we present an algorithm for gen- erating a maximal labelling that specifies superior support for the access paths most heavily travelled. Assume...A.C.M. SIGMOD Conf., (May 79). [CARD731 Cardenas , A. F., "Evaluation and Selection of File Organization - A Model and a System," Comm. A.C.M., V 16, N

  14. Model-Based Optimal Experimental Design for Complex Physical Systems

    Science.gov (United States)

    2015-12-03

    an open-loop behavior , where no feedback is involved , and the observations from any experiment do not affect the design of other experiments...developing and refining models of physical systems. Yet experimental observations can be difficult, time- consuming , and expensive to acquire. In this...improve design and decision-making under uncertainty. Yet experimental observations can be difficult, time- consuming , and expensive to acquire. In this

  15. Continuous-Flow Biochips: Technology, Physical Design Methods and Testing

    DEFF Research Database (Denmark)

    Pop, Paul; Araci, Ismail Emre; Chakrabarty, Krishnendu

    2015-01-01

    This article is a tutorial on continuous-flow biochips where the basic building blocks are microchannels, and microvalves, and by combining them, more complex units such as mixers, switches, and multiplexers can be built. It also presents the state of the art in flow-based biochip technology...... and emerging research challenges in the areas of physical design and testing techniques....

  16. Physical and Model Uncertainty for Fatigue Design of Composite Material

    DEFF Research Database (Denmark)

    Toft, Henrik Stensgaard; Sørensen, John Dalsgaard

    The main aim of the present report is to establish stochastic models for the uncertainties related to fatigue design of composite materials. The uncertainties considered are the physical uncertainty related to the static and fatigue strength and the model uncertainty related to Miners rule...

  17. Visible Light Communication Physical Layer Design for Jist Simulation

    Directory of Open Access Journals (Sweden)

    Tomaš Boris

    2014-12-01

    Full Text Available Current advances in computer networking consider using visible light spectrum to encode and decode digital data. This approach is relatively non expensive. However, designing appropriate MAC or any other upper layer protocol for Visible Light Communication (VLC requires appropriate hardware. This paper proposes and implements such hardware simulation (physical layer that is compatible with existing network stack.

  18. The Adaptive Physical Education Program: Its Design and Curriculum.

    Science.gov (United States)

    Henn, Joan M.

    The booklet describes a program designed to improve the play skills of seriously disturbed, multiply handicapped children (5 to 13 years old) through gross motor skill development. A six step process is described for the adaptive physical education program: assessment, development of interdisciplinary goals, interventions, development of goals for…

  19. Design of the sex hormones and physical exercise (SHAPE study

    Directory of Open Access Journals (Sweden)

    Peeters Petra HM

    2007-09-01

    Full Text Available Abstract Background Physical activity has been associated with a decreased risk for breast cancer. The biological mechanismn(s underlying the association between physical activity and breast cancer is not clear. Most prominent hypothesis is that physical activity may protect against breast cancer through reduced lifetime exposure to endogenous hormones either direct, or indirect by preventing overweight and abdominal adiposity. In order to get more insight in the causal pathway between physical activity and breast cancer risk, we designed the Sex Hormones and Physical Exercise (SHAPE study. Purpose of SHAPE study is to examine the effects of a 1-year moderate-to-vigorous intensity exercise programme on endogenous hormone levels associated with breast cancer among sedentary postmenopausal women and whether the amount of total body fat or abdominal fat mediates the effects. Methods/Design In the SHAPE study, 189 sedentary postmenopausal women, aged 50–69 years, are randomly allocated to an intervention or a control group. The intervention consists of an 1-year moderate-to-vigorous intensity aerobic and strenght training exercise programme. Partcipants allocated to the control group are requested to retain their habitual exercise pattern. Primary study parameters measured at baseline, at four months and at 12 months are: serum concentrations of endogenous estrogens, endogenous androgens, sex hormone binding globuline and insuline. Other study parameters include: amount of total and abdominal fat, weight, BMI, body fat distribution, physical fitness, blood pressure and lifestyle factors. Discussion This study will contribute to the body of evidence relating physical activity and breast cancer risk and will provide insight into possible mechanisms through which physical activity might be associated with reduced risk of breast cancer in postmenopausal women. Trial registration NCT00359060

  20. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  1. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  2. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  3. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  4. Physics issues in diffraction limited storage ring design

    Institute of Scientific and Technical Information of China (English)

    FAN Wei; BAI ZhengHe; GAO WeiWei; FENG GuangYao; LI WeiMin; WANG Lin; HE DuoHui

    2012-01-01

    Diffraction limited electron storage ring is considered a promising candidate for future light sources,whose main characteristics are higher brilliance,better transverse coherence and better stability.The challenge of diffraction limited storage ring design is how to achieve the ultra low beam emittance with acceptable nonlinear performance.Effective linear and nonlinear parameter optimization methods based on Artificial Intelligence were developed for the storage ring physical design.As an example of application,partial physical design of HALS (Hefei Advanced Light Source),which is a diffraction limited VUV and soft X-ray light source,was introduced.Severe emittance growth due to the Intra Beam Scattering effect,which is the main obstacle to achieve ultra low emittance,was estimated quantitatively and possible cures were discussed.It is inspiring that better performance of diffraction limited storage ring can be achieved in principle with careful parameter optimization.

  5. Physics issues in diffraction limited storage ring design

    Science.gov (United States)

    Fan, Wei; Bai, ZhengHe; Gao, WeiWei; Feng, GuangYao; Li, WeiMin; Wang, Lin; He, DuoHui

    2012-05-01

    Diffraction limited electron storage ring is considered a promising candidate for future light sources, whose main characteristics are higher brilliance, better transverse coherence and better stability. The challenge of diffraction limited storage ring design is how to achieve the ultra low beam emittance with acceptable nonlinear performance. Effective linear and nonlinear parameter optimization methods based on Artificial Intelligence were developed for the storage ring physical design. As an example of application, partial physical design of HALS (Hefei Advanced Light Source), which is a diffraction limited VUV and soft X-ray light source, was introduced. Severe emittance growth due to the Intra Beam Scattering effect, which is the main obstacle to achieve ultra low emittance, was estimated quantitatively and possible cures were discussed. It is inspiring that better performance of diffraction limited storage ring can be achieved in principle with careful parameter optimization.

  6. Integrated Circuit Design in US High-Energy Physics

    CERN Document Server

    De Geronimo, G; Bebek, C; Garcia-Sciveres, M; Von der Lippe, H; Haller, G; Grillo, A A; Newcomer, M

    2013-01-01

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies...

  7. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  8. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  9. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  10. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  11. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  12. Physics and Its Interfaces with Medicinal Chemistry and Drug Design

    Science.gov (United States)

    Santos, Ricardo N.; Andricopulo, Adriano D.

    2013-08-01

    Medicinal chemistry is a multidisciplinary subject that integrates knowledge from a variety of fields of science, including, but not limited to, chemistry, biology, and physics. The area of drug design involves the cooperative work of scientists with a diverse range of backgrounds and technical skills, trying to tackle complex problems using an integration of approaches and methods. One important contribution to this field comes from physics through studies that attempt to identify and quantify the molecular interactions between small molecules (drugs) and biological targets (receptors), such as the forces that govern the interactions, the thermodynamics of the drug-receptor interactions, and so on. In this context, the interfaces of physics, medicinal chemistry, and drug design are of vital importance for the development of drugs that not only have the right chemistry but also the right intermolecular properties to interact at the macromolecular level, providing useful information about the principles and molecular mechanisms underlying the therapeutic action of drugs. This article highlights some of the most important connections between physics and medicinal chemistry in the design of new drugs.

  13. Physical Layer Design in Wireless Sensor Networks for Fading Mitigation

    Directory of Open Access Journals (Sweden)

    Nuo Chen

    2013-09-01

    Full Text Available This paper presents the theoretical analysis, simulation results and suggests design in digital technology of a physical layer for wireless sensor networks. The proposed design is able to mitigate fading inside communication channel. To mitigate fading the chip interleaving technique is proposed. For the proposed theoretical model of physical layer, a rigorous mathematical analysis is conducted, where all signals are presented and processed in discrete time domain form which is suitable for further direct processing necessary for devices design in digital technology. Three different channels are used to investigate characteristics of the physical layer: additive white Gaussian noise channel (AWGN, AWG noise and flat fading channel and AWG noise and flat fading channel with interleaver and deinterleaver blocks in the receiver and transmitter respectively. Firstly, the mathematical model of communication system representing physical layer is developed based on the discrete time domain signal representation and processing. In the existing theory, these signals and their processing are represented in continuous time form, which is not suitable for direct implementation in digital technology. Secondly, the expressions for the probability of chip, symbol and bit error are derived. Thirdly, the communication system simulators are developed in MATLAB. The simulation results confirmed theoretical findings.

  14. Learning physics: A comparative analysis between instructional design methods

    Science.gov (United States)

    Mathew, Easow

    The purpose of this research was to determine if there were differences in academic performance between students who participated in traditional versus collaborative problem-based learning (PBL) instructional design approaches to physics curricula. This study utilized a quantitative quasi-experimental design methodology to determine the significance of differences in pre- and posttest introductory physics exam performance between students who participated in traditional (i.e., control group) versus collaborative problem solving (PBL) instructional design (i.e., experimental group) approaches to physics curricula over a college semester in 2008. There were 42 student participants (N = 42) enrolled in an introductory physics course at the research site in the Spring 2008 semester who agreed to participate in this study after reading and signing informed consent documents. A total of 22 participants were assigned to the experimental group (n = 22) who participated in a PBL based teaching methodology along with traditional lecture methods. The other 20 students were assigned to the control group (n = 20) who participated in the traditional lecture teaching methodology. Both the courses were taught by experienced professors who have qualifications at the doctoral level. The results indicated statistically significant differences (p academic performance between students who participated in traditional (i.e., lower physics posttest scores and lower differences between pre- and posttest scores) versus collaborative (i.e., higher physics posttest scores, and higher differences between pre- and posttest scores) instructional design approaches to physics curricula. Despite some slight differences in control group and experimental group demographic characteristics (gender, ethnicity, and age) there were statistically significant (p = .04) differences between female average academic improvement which was much higher than male average academic improvement (˜63%) in the control

  15. A system for designing and simulating particle physics experiments

    Science.gov (United States)

    Żelazny, Roman; Strzałkowski, Piotr

    1987-01-01

    In view of the rapid development of experimental facilities and their costs, the systematic design and preparation of particle physics experiments have become crucial. A software system is proposed as an aid for the experimental designer, mainly for experimental geometry analysis and experimental simulation. The following model is adopted: the description of an experiment is formulated in a language (here called XL) and put by its processor in a data base. The language is based on the entity-relationship-attribute approach. The information contained in the data base can be reported and analysed by an analyser (called XA) and modifications can be made at any time. In particular, the Monte Carlo methods can be used in experiment simulation for both physical phenomena in experimental set-up and detection analysis. The general idea of the system is based on the design concept of ISDOS project information systems. The characteristics of the simulation module are similar to those of the CERN Geant system, but some extensions are proposed. The system could be treated as a component of a greater, integrated software environment for the design of particle physics experiments, their monitoring and data processing.

  16. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  17. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  18. Physical explosion analysis in heat exchanger network design

    Science.gov (United States)

    Pasha, M.; Zaini, D.; Shariff, A. M.

    2016-06-01

    The failure of shell and tube heat exchangers is being extensively experienced by the chemical process industries. This failure can create a loss of production for long time duration. Moreover, loss of containment through heat exchanger could potentially lead to a credible event such as fire, explosion and toxic release. There is a need to analyse the possible worst case effect originated from the loss of containment of the heat exchanger at the early design stage. Physical explosion analysis during the heat exchanger network design is presented in this work. Baker and Prugh explosion models are deployed for assessing the explosion effect. Microsoft Excel integrated with process design simulator through object linking and embedded (OLE) automation for this analysis. Aspen HYSYS V (8.0) used as a simulation platform in this work. A typical heat exchanger network of steam reforming and shift conversion process was presented as a case study. It is investigated from this analysis that overpressure generated from the physical explosion of each heat exchanger can be estimated in a more precise manner by using Prugh model. The present work could potentially assist the design engineer to identify the critical heat exchanger in the network at the preliminary design stage.

  19. Designing Drops, Loops, and Hills: The Physics behind Roller Coaster Design

    Science.gov (United States)

    Christiana, Katharyn; Ilie, Carolina

    2013-03-01

    Almost everyone has seen a roller coaster at one time in their life. They range in type from old wooden coasters from decades passes to modern machines made of steel that allow you to stand up while riding. The basic physics behind these machines is relatively simple, but in the modern world we strive to design bigger and better machines that push the human body and the laws of physics to their limits. But how do the designers of these rides maintain the balance between making riders feel like they're on the brink of death while keeping them completely safe? The answer can be found in basic physics and mechanical engineering. This is a part of the honors thesis that focuses on the mechanical principles applied in roller coaster design. The theoretical part of the thesis will be complemented by a full small scale ride design.

  20. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  1. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  2. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  3. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  4. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  5. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  6. Real-time motion detection using an analog VLSI zero-crossing chip

    Science.gov (United States)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  7. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  8. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  9. Rethinking Physics for Biologists: A design-based research approach

    Science.gov (United States)

    Sawtelle, Vashti

    2015-03-01

    Biology majors at the University of Maryland are required to take courses in biology, chemistry, and physics - but they often see these courses as disconnected. Over the past three years the NEXUS/Physics course has been working to develop an interdisciplinary learning environment that bridges the disciplinary domains of biology and physics. Across the three years we have gone from teaching in a small class with one instructor to teaching in a large lecture hall with multiple instructors. We have used a design-based research approach to support critical reflection of the course at multiple-time scales. In this presentation I will detail our process of collecting systematic data, listening to and valuing students' reasoning, and bridging diverse perspectives led. I will demonstrate how this process led to improved curricular design, refined assessment objectives, and new design heuristics. This work is supported by NSF-TUES DUE 11-22818, the HHMI NEXUS grant, and a NSF Graduate Research Fellowship (DGE 0750616).

  10. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  11. CLIC CDR - physics and detectors: CLIC conceptual design report.

    Energy Technology Data Exchange (ETDEWEB)

    Berger, E.; Demarteau, M.; Repond, J.; Xia, L.; Weerts, H. (High Energy Physics); (Many)

    2012-02-10

    This report forms part of the Conceptual Design Report (CDR) of the Compact LInear Collider (CLIC). The CLIC accelerator complex is described in a separate CDR volume. A third document, to appear later, will assess strategic scenarios for building and operating CLIC in successive center-of-mass energy stages. It is anticipated that CLIC will commence with operation at a few hundred GeV, giving access to precision standard-model physics like Higgs and top-quark physics. Then, depending on the physics landscape, CLIC operation would be staged in a few steps ultimately reaching the maximum 3 TeV center-of-mass energy. Such a scenario would maximize the physics potential of CLIC providing new physics discovery potential over a wide range of energies and the ability to make precision measurements of possible new states previously discovered at the Large Hadron Collider (LHC). The main purpose of this document is to address the physics potential of a future multi-TeV e{sup +}e{sup -} collider based on CLIC technology and to describe the essential features of a detector that are required to deliver the full physics potential of this machine. The experimental conditions at CLIC are significantly more challenging than those at previous electron-positron colliders due to the much higher levels of beam-induced backgrounds and the 0.5 ns bunch-spacing. Consequently, a large part of this report is devoted to understanding the impact of the machine environment on the detector with the aim of demonstrating, with the example of realistic detector concepts, that high precision physics measurements can be made at CLIC. Since the impact of background increases with energy, this document concentrates on the detector requirements and physics measurements at the highest CLIC center-of-mass energy of 3 TeV. One essential output of this report is the clear demonstration that a wide range of high precision physics measurements can be made at CLIC with detectors which are challenging, but

  12. Design and Realization of a New Signal Security System for Multimedia Data Transmission

    Directory of Open Access Journals (Sweden)

    Hun-Chen Chen

    2003-12-01

    Full Text Available We propose a new signal security system and its VLSI architecture for real-time multimedia data transmission applications. We first define two bit-circulation functions for one-dimensional binary array transformation. Then, we exploit a chaotic system in generating a binary sequence to control the bit-circulation functions defined for performing the successive transformation on the input data. Each eight 8-bit data elements is regarded as a set and is fed into an 8×8 binary matrix being transformed on each row and each column of the matrix by these two bit-circulation functions such that the signal can be transformed into completely disordered data. The features of the proposed design include low computational complexity, regular operations suitable for low-cost VLSI implementation, high data security, and high feasibility for easy integration with commercial multimedia storage and transmission applications. We have performed Matlab simulation to verify the functional correctness of the proposed system. In implementing the system, a low-cost VLSI architecture has been designed, verified, and physically realized based on a 0.35 μm CMOS technology. The implementation results show that the proposed signal security system can achieve 117 Mbytes/s data throughput rate that is fast enough for real-time data protection in multimedia transmission applications.

  13. Handbook of Modern Sensors Physics, Designs, and Applications

    CERN Document Server

    Fraden, Jacob

    2010-01-01

    This book is about devices commonly called sensors. Digital systems, however complex and intelligent they might be, must receive information from the outside world that is generally analog and not electrical. Sensors are interface devices between various physical values and the electronic circuits who "understand" only a language of moving electrical charges. In other words, sensors are the eyes, ears, and noses of silicon chips. Unlike other books on sensors, this book is organized according to the measured variables (temperature, pressure, position, etc.) that make it much more practical and easier to read. In this new edition recent ideas and developments have been added while less important and non-essential designs were dropped. Sections on practical designs and use of the modern micro-machining technologies have been revised substantially. This book is a reference text that can be used by students, researchers interested in modern instrumentation (applied physicists and engineers), sensor designers, app...

  14. Designing quantum information processing via structural physical approximation

    Science.gov (United States)

    Bae, Joonwoo

    2017-10-01

    In quantum information processing it may be possible to have efficient computation and secure communication beyond the limitations of classical systems. In a fundamental point of view, however, evolution of quantum systems by the laws of quantum mechanics is more restrictive than classical systems, identified to a specific form of dynamics, that is, unitary transformations and, consequently, positive and completely positive maps to subsystems. This also characterizes classes of disallowed transformations on quantum systems, among which positive but not completely maps are of particular interest as they characterize entangled states, a general resource in quantum information processing. Structural physical approximation offers a systematic way of approximating those non-physical maps, positive but not completely positive maps, with quantum channels. Since it has been proposed as a method of detecting entangled states, it has stimulated fundamental problems on classifications of positive maps and the structure of Hermitian operators and quantum states, as well as on quantum measurement such as quantum design in quantum information theory. It has developed efficient and feasible methods of directly detecting entangled states in practice, for which proof-of-principle experimental demonstrations have also been performed with photonic qubit states. Here, we present a comprehensive review on quantum information processing with structural physical approximations and the related progress. The review mainly focuses on properties of structural physical approximations and their applications toward practical information applications.

  15. Model-implementation fidelity in cyber physical system design

    CERN Document Server

    Fabre, Christian

    2017-01-01

    This book puts in focus various techniques for checking modeling fidelity of Cyber Physical Systems (CPS), with respect to the physical world they represent. The authors' present modeling and analysis techniques representing different communities, from very different angles, discuss their possible interactions, and discuss the commonalities and differences between their practices. Coverage includes model driven development, resource-driven development, statistical analysis, proofs of simulator implementation, compiler construction, power/temperature modeling of digital devices, high-level performance analysis, and code/device certification. Several industrial contexts are covered, including modeling of computing and communication, proof architectures models and statistical based validation techniques. Addresses CPS design problems such as cross-application interference, parsimonious modeling, and trustful code production Describes solutions, such as simulation for extra-functional properties, extension of cod...

  16. Handbook of modern sensors physics, designs, and applications

    CERN Document Server

    Fraden, Jacob

    2016-01-01

    This book presents a comprehensive and up-to-date account of the theory (physical principles), design, and practical implementations of various sensors for scientific, industrial, and consumer applications. This latest edition focuses on the sensing technologies driven by the expanding use of sensors in mobile devices. These new miniature sensors will be described, with an emphasis on smart sensors which have embedded processing systems. The chapter on chemical sensors has also been expanded to present the latest developments. Digital systems, however complex and intelligent they may be, must receive information from the outside world that is generally analog and not electrical. Sensors are interface devices between various physical values and the electronic circuits that "understand" only a language of moving electrical charges. In other words, sensors are the eyes, ears, and noses of silicon chips. Unlike other books on sensors, the Handbook of Modern Sensors is organized according to the measured variables...

  17. Stellarator Wendelstein VII-AS; Physics and engineering design

    Energy Technology Data Exchange (ETDEWEB)

    Sapper, J.; Renner, H. (Max-Planck-Institut fuer Plasmaphysik, Garching (Germany, F.R.))

    1990-01-01

    The advanced stellarator Wendelstein VII-AS is a medium-sized experimental machine with the following properties and aims: a broadly optimized magnetic configuration with improved plasma equilibrium and smaller neoclassical transport losses compared to classical stellarators; operation with net-current-free plasma; field generation with a modular set of coils instead of the conventional helix/toroidal field coil; system; and good access for plasma heating methods, e.g., neutral beam injection, electron cyclotron heating, and ion cyclotron heating. The physics characteristics and the engineering design of the experiment as well as results from the initial operation period are reported.

  18. Associative Memory design for the FastTrack processor (FTK) at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Piendibene, M; Sacco, I; Sartori, L; Tripiccione, R

    2010-01-01

    We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs, minimizes the power consumption and improves the functionality for the Fast Tracker (FTK) proposed to upgrade the ATLAS trigger at LHC. Finally we will focus on possible future applications inside and outside High Physics Energy (HEP).

  19. Associative Memory Design for the FastTrack Processor (FTK) at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Volpi, G; Beccherle, R; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Amerio, S; Hoff, J; Liu, T; Sacco, I; Liberali, V; Stabile, A; Schoening, A; Soltveit, H; Tripiccione, R

    2011-01-01

    We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new Associative Memory project: it maximizes the pattern density on ASICs, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC. Finally we will focus on possible future applications inside and outside high physics energy.

  20. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  1. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  2. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  3. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  4. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  5. Ground Bounce Noise Reduction in Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Vipin Kumar Sharma

    2015-12-01

    Full Text Available : Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.

  6. Exergames for physical education: an overview about interaction design perspectives

    Directory of Open Access Journals (Sweden)

    Francesco Sgrò

    2013-08-01

    Full Text Available Exertion games represent an interesting, funny and innovative way to involve people in physical activities, fighting with troublesome phenomenon of obesity in children and young. In the educational context ICT technologies represent a basic instruments of the learning process. In literature several studies addressed the videogame’s implication in the learning process. In this work the interaction design aspects dealing with the use of exergames in physical activities educational process will be analysed using the same approach proposed by Mueller et al. (2011. In detail we will focus on the corporeal experience descended from the interaction procedure. An ideal graphical user interface for exergames is also presented. Moreover, an analysis of the most shared devices for exergames will be depictured. The paper infers the useful interaction elements that can improve the learning process of physical education, as well as transfer effect that may correlate with health and social outcomes. Furthermore, this work suggests the theoretical approach which has to guide the development of exergames for educational environment.

  7. ITER-EDA physics design requirements and plasma performance assessments

    Energy Technology Data Exchange (ETDEWEB)

    Uckan, N.A.; Galambos, J. [Oak Ridge National Lab., TN (United States); Wesley, J.; Boucher, D.; Perkins, F.; Post, D.; Putvinski, S. [ITER San Diego Joint Work Site, CA (United States)

    1996-07-01

    Physics design guidelines, plasma performance estimates, and sensitivity of performance to changes in physics assumptions are presented for the ITER-EDA Interim Design. The overall ITER device parameters have been derived from the performance goals using physics guidelines based on the physics R&D results. The ITER-EDA design has a single-null divertor configuration (divertor at the bottom) with a nominal plasma current of 21 MA, magnetic field of 5.68 T, major and minor radius of 8.14 m and 2.8 m, and a plasma elongation (at the 95% flux surface) of {approximately}1.6 that produces a nominal fusion power of {approximately}1.5 GW for an ignited burn pulse length of {ge}1000 s. The assessments have shown that ignition at 1.5 GW of fusion power can be sustained in ITER for 1000 s given present extrapolations of H-mode confinement ({tau}{sub E} = 0.85 {times} {tau}{sub ITER93H}), helium exhaust ({tau}*{sub He}/{tau}{sub E} = 10), representative plasma impurities (n{sub Be}/n{sub e} = 2%), and beta limit [{beta}{sub N} = {beta}(%)/(I/aB) {le} 2.5]. The provision of 100 MW of auxiliary power, necessary to access to H-mode during the approach to ignition, provides for the possibility of driven burn operations at Q = 15. This enables ITER to fulfill its mission of fusion power ({approximately} 1--1.5 GW) and fluence ({approximately}1 MWa/m{sup 2}) goals if confinement, impurity levels, or operational (density, beta) limits prove to be less favorable than present projections. The power threshold for H-L transition, confinement uncertainties, and operational limits (Greenwald density limit and beta limit) are potential performance limiting issues. Improvement of the helium exhaust ({tau}*{sub He}/{tau}{sub E} {le} 5) and potential operation in reverse-shear mode significantly improve ITER performance.

  8. A VLSI design for a trace-back Viterbi decoder

    Science.gov (United States)

    Truong, T. K.; Shih, Ming-Tang; Reed, Irving S.; Satorius, E. H.

    1992-01-01

    A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

  9. Design and Implementation of VLSI Prime Factor Algorithm Processor.

    Science.gov (United States)

    1987-12-01

    for A, 1i ’ 1 1 Fh Ai ,,r equjAtIInI. art, ( , 4 10 4,t’ 4 ( - /’ cr tht, (-arr% sur ma% akL, be represented as Figure 36 Carry Select Adder Blocking... Select Adder Blocking .......................................................... 81 Figure 37: ALU Adder Cell...ALU Logic Implementation............................................................ 81 viii J,.. in List of Figures (continued) Figure 36: Carry

  10. VLSI Design Tools, Reference Manual, Release 2.0.

    Science.gov (United States)

    1984-08-01

    xz) -.. ISOCMOS Macros md(x,y); ba(x ,y); Sop(x,y); bm(xy); 8.10. CMOSFW Macrof rgb (z,yl; rb(z,Y); 9. ISOCMOS Example The following is a sample file of...ABC B Y Eqalvalesit: Nodes A I BIC I YI I I I I IInpu Load I I I I I I I I I I mock Diev d 1/0 PWm CAI misb 32 X ~ AC Cherdortas V0 - $ input Imidm...A 1B C YI Input Load III Mek Dlr= o !/O pbS Call Wdtl 5 AC EhmdWdIes VD, - SV bpt 1tmidm TN - Sm .1. Fm Ot FIND One r. mes, Led -I Led -1l

  11. ELEC-2005: Electronics in High Energy Physics

    CERN Multimedia

    Monique Duval

    2004-01-01

    ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers in the format of the successful ELEC-2002 course series, and within the framework of the 2005 Technical Training Programme. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 will composed of four Terms throughout the year: Winter Term: Introduction to electronics in HEP (January-February, 6 lectures) Spring Term: Integrated circuits and VLSI technology for physics (March, 6 lectures) Summer Term: System electronics for physics: Issues (May, 7 lectures) Winter Term: Electronics applications in HEP experiments (November-December, 10 lectures) Lectures within each Term will take place on Tuesdays and Thursdays, from 10:00 to 12:30. The...

  12. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  13. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  14. Low-power VLSI circuits and systems

    CERN Document Server

    Pal, Ajit

    2015-01-01

    The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.

  15. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  16. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  17. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  18. A Low power and area efficient CLA adder design using Full swing GDI technique

    OpenAIRE

    Matcha Hemanth Kumar; Prof. Dr.S.M.VALI

    2015-01-01

    The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gat...

  19. Photonic Design: From Fundamental Solar Cell Physics to Computational Inverse Design

    CERN Document Server

    Miller, Owen D

    2013-01-01

    Photonic innovation is becoming ever more important in the modern world. Optical systems are dominating shorter and shorter communications distances, LED's are rapidly emerging for a variety of applications, and solar cells show potential to be a mainstream technology in the energy space. The need for novel, energy-efficient photonic and optoelectronic devices will only increase. This work unites fundamental physics and a novel computational inverse design approach towards such innovation. The first half of the dissertation is devoted to the physics of high-efficiency solar cells. As solar cells approach fundamental efficiency limits, their internal physics transforms. Photonic considerations, instead of electronic ones, are the key to reaching the highest voltages and efficiencies. Proper photon management led to Alta Device's recent dramatic increase of the solar cell efficiency record to 28.3%. Moreover, approaching the Shockley-Queisser limit for any solar cell technology will require light extraction to ...

  20. Research-design model for professional development of teachers: Designing lessons with physics education research

    Directory of Open Access Journals (Sweden)

    Esther Bagno

    2006-09-01

    Full Text Available How can one increase the awareness of teachers to the existence and importance of knowledge gained through physics education research (PER and provide them with capabilities to use it? How can one enrich teachers’ physics knowledge and the related pedagogical content knowledge of topics singled out by PER? In this paper we describe a professional development model that attempts to respond to these needs. We report on a study of the model’s implementation in a program for 22 high-school experienced physics teachers. In this program teachers (in teams of 5-6 developed during a year and a half (about 330 h , several lessons (minimodules dealing with a topic identified as problematic by PER. The teachers employed a systematic research-based approach and used PER findings. The program consisted of three stages, each culminating with a miniconference: 1. Defining teaching and/or learning goals based on content analysis and diagnosis of students’ prior knowledge. 2. Designing the lessons using PER-based instructional strategies. 3. Performing a small-scale research study that accompanies the development process and publishing the results. We describe a case study of one of the groups and bring evidence that demonstrates how the workshop advanced: (a Teachers’ awareness of deficiencies in their own knowledge of physics and pedagogy, and their perceptions about their students’ knowledge; (b teachers’ knowledge of physics and physics pedagogy; (c a systematic research-based approach to the design of lessons; (d the formation of a community of practice; and (e acquaintance with central findings of PER. There was a clear effect on teachers’ practice in the context of the study as indicated by the materials brought to the workshop. The teachers also reported that they continued to use the insights gained, mainly in the topics that were investigated by themselves and by their peers.

  1. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  2. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  3. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  4. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  5. VLSI digital PSK demodulator for space communication

    Science.gov (United States)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  6. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  7. The International Linear Collider Technical Design Report - Volume 2: Physics

    CERN Document Server

    Barklow, Tim; Fujii, Keisuke; Gao, Yuanning; Hoang, Andre; Kanemura, Shinya; List, Jenny; Logan, Heather E; Nomerotski, Andrei; Perelstein, Maxim; Peskin, Michael E; Pöschl, Roman; Reuter, Jürgen; Riemann, Sabine; Savoy-Navarro, Aurore; Servant, Geraldine; Tait, Tim M P

    2013-01-01

    The International Linear Collider Technical Design Report (TDR) describes in four volumes the physics case and the design of a 500 GeV centre-of-mass energy linear electron-positron collider based on superconducting radio-frequency technology using Niobium cavities as the accelerating structures. The accelerator can be extended to 1 TeV and also run as a Higgs factory at around 250 GeV and on the Z0 pole. A comprehensive value estimate of the accelerator is give, together with associated uncertainties. It is shown that no significant technical issues remain to be solved. Once a site is selected and the necessary site-dependent engineering is carried out, construction can begin immediately. The TDR also gives baseline documentation for two high-performance detectors that can share the ILC luminosity by being moved into and out of the beam line in a "push-pull" configuration. These detectors, ILD and SiD, are described in detail. They form the basis for a world-class experimental programme that promises to incr...

  8. The International Linear Collider Technical Design Report - Volume 2: Physics

    Energy Technology Data Exchange (ETDEWEB)

    Baer, Howard [Univ. of Oklahoma, Norman, OK (United States); Barklow, Tim [SLAC National Accelerator Lab., Menlo Park, CA (United States); Fujii, Keisuke [National Lab. for High Energy Physics (KEK), Tokai (Japan); Gao, Yuanning [Unlisted; Hoang, Andre [Univ. of Vienna (Austria); Kanemura, Shinya [Univ. of Toyama (Japan); List, Jenny [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Logan, Heather E. [Carleton Univ., Ottawa, ON (Canada); Nomerotski, Andrei [Univ. of Oxford (United Kingdom); Perelstein, Maxim [Cornell Univ., Ithaca, NY (United States); Peskin, Michael E. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Pöschl, Roman [Univ. Paris-Sud, Orsay (France). Linear Accelerator Lab. (LAL); Reuter, Jürgen [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Riemann, Sabine [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Savoy-Navarro, Aurore [CNRS/IN2P3. Univ. Paris (France). Observatoire de Paris. AstroParticule et Cosmologie (APC); Servant, Geraldine [European Organization for Nuclear Research (CERN), Geneva (Switzerland); Tait, Tim P. [Univ. of California, Los Angeles, CA (United States); Yu, Jaehoon [Univ. of Science and Technology of China, Hefei (China)

    2013-06-26

    The International Linear Collider Technical Design Report (TDR) describes in four volumes the physics case and the design of a 500 GeV centre-of-mass energy linear electron-positron collider based on superconducting radio-frequency technology using Niobium cavities as the accelerating structures. The accelerator can be extended to 1 TeV and also run as a Higgs factory at around 250 GeV and on the Z0 pole. A comprehensive value estimate of the accelerator is give, together with associated uncertainties. It is shown that no significant technical issues remain to be solved. Once a site is selected and the necessary site-dependent engineering is carried out, construction can begin immediately. The TDR also gives baseline documentation for two high-performance detectors that can share the ILC luminosity by being moved into and out of the beam line in a "push-pull" configuration. These detectors, ILD and SiD, are described in detail. They form the basis for a world-class experimental programme that promises to increase significantly our understanding of the fundamental processes that govern the evolution of the Universe.

  9. Neuromorphic VLSI realization of the hippocampal formation.

    Science.gov (United States)

    Aggarwal, Anu

    2016-05-01

    The medial entorhinal cortex grid cells, aided by the subicular head direction cells, are thought to provide a matrix which is utilized by the hippocampal place cells for calculation of position of an animal during spatial navigation. The place cells are thought to function as an internal GPS for the brain and provide a spatiotemporal stamp on episodic memories. Several computational neuroscience models have been proposed to explain the place specific firing patterns of the cells of the hippocampal formation - including the GRIDSmap model for grid cells and Bayesian integration for place cells. In this work, we present design and measurement results from a first ever system of silicon circuits which successfully realize the function of the hippocampal formation of brain based on these models.

  10. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  11. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  12. Review Committee report on the conceptual design of the Tokamak Physics Experiment

    Energy Technology Data Exchange (ETDEWEB)

    1993-04-01

    This report discusses the following topics on the conceptual design of the Tokamak Physics Experiment: Role and mission of TPX; overview of design; physics design assessment; engineering design assessment; evaluation of cost, schedule, and management plans; and, environment safety and health.

  13. Cyber-Physical Systems: two case studies in design methodologies

    OpenAIRE

    Rizzon, Luca

    2016-01-01

    To analyze embedded systems, engineers use tools that can simulate the performance of software components executed on hardware architectures. When the embedded system functionality is strongly correlated to physical quantities, as in the case of Cyber-Physical System (CPS), we need to model physical processes to determine the overall behavior of the system. Unfortunately, embedded systems simulators are not generally suitable to evaluate physical processes, and in the same way physical model ...

  14. Technical Training: ELEC-2005: Electronics in High Energy Physics

    CERN Multimedia

    Monique Duval

    2005-01-01

    CERN Technical Training 2005: Learning for the LHC! ELEC-2005: Electronics in High Energy Physics - Spring Term ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the successful ELEC-2002 course series. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 is composed of four Terms: the Winter Term, Introduction to electronics in HEP, already took place; the next three Terms will run throughout the year: Spring Term: Integrated circuits and VLSI technology for physics (March, 6 lectures) - now open for registration Summer Term: System electronics for physics: Issues (May, 7 lectures) Autumn Term: Ele...

  15. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  16. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  17. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  18. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  19. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  20. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  1. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  2. Design methods for fault-tolerant finite state machines

    Science.gov (United States)

    Niranjan, Shailesh; Frenzel, James F.

    1993-01-01

    VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

  3. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  4. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  5. Associative Memory Design for the Fast TracKer Processor (FTK) at ATLAS

    CERN Document Server

    Beretta, M; The ATLAS collaboration

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. We have developed this device using 65 nm technology combining a full custom CAM cell with standard-cell control logic. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution pattern matching technique using “don’t care” bits to set the pattern-matching window for each pattern and each layer can be independently.

  6. Design of the Sex Hormones and Physical Exercise (SHAPE) Study.

    OpenAIRE

    Peeters Petra HM; Monninkhof Evelyn M; Schuit Albertine J

    2007-01-01

    Abstract Background Physical activity has been associated with a decreased risk for breast cancer. The biological mechanismn(s) underlying the association between physical activity and breast cancer is not clear. Most prominent hypothesis is that physical activity may protect against breast cancer through reduced lifetime exposure to endogenous hormones either direct, or indirect by preventing overweight and abdominal adiposity. In order to get more insight in the causal pathway between physi...

  7. Playscapes : A design perspective on young children's physical play

    NARCIS (Netherlands)

    Boon, Boudewijn; Van Der Net, Janjaap; Rozendaal, Marco; Stappers, Pieter Jan; van den Heuvel-Eibrink, Marry M.

    2016-01-01

    In early childhood, children develop motor skills that form the basis of their future physical activities. This development can stagnate when children face long-term hospitalization due to injury or disease. Most interventions to facilitate their physical development are built on exercise and struct

  8. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  9. A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.

    Science.gov (United States)

    Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

    2011-04-01

    Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.

  10. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  11. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  12. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  13. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  14. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  15. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  16. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  17. Technical Training: ELEC-2005 - Electronics in High Energy Physics

    CERN Multimedia

    Monique Duval

    2005-01-01

    Learning for the LHC! ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the successful ELEC-2002 course series. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 is composed of four Terms that will run throughout the year: Winter Term: Introduction to electronics in HEP (January-February, 6 lectures) Spring Term: Integrated circuits and VLSI technology for physics (March, 6 lectures) Summer Term: System electronics for physics: Issues (May, 7 lectures) Autumn Term: Electronics applications in HEP experiments (November-December, 10 lectures) Lectures within each Term will take place on Tuesdays an...

  18. The Contribution of Virtual Reality Software to Design in Teaching Physical Education

    Directory of Open Access Journals (Sweden)

    Esther Zaretsky

    2011-08-01

    Full Text Available Up to date research shows that training with virtual software develops the design of virtual simulations by physical education pre service teachers. The design of virtual simulations improved spatial skills, especially visualization of the body

  19. Cyber-physical system design with sensor networking technologies

    CERN Document Server

    Zeadally, Sherali

    2016-01-01

    This book describes how wireless sensor networking technologies can help in establishing and maintaining seamless communications between the physical and cyber systems to enable efficient, secure, reliable acquisition, management, and routing of data.

  20. Communicating Emotion through Haptic Design: A Study Using Physical Keys

    DEFF Research Database (Denmark)

    Kjellerup, Marie Kjær; Larsen, Anne Cathrine; Maier, Anja

    2014-01-01

    This paper explores how designers may communicate with the users of their products through haptic design. More specifically, how tactile properties of materials evoke emotions such as satisfaction, joy, or disgust. A research through design approach has been followed; mood- and material boards an...

  1. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  2. A Checklist for Designing and Evaluating Physical Education Program Web Sites

    Science.gov (United States)

    Tucker, Michael; Hill, Grant

    2009-01-01

    Creating a physical education department web site is an excellent way to promote a positive image of the program, because students and parents are able to find important information and improve the lines of communication. A well-designed physical education web site can even encourage students to increase their physical activity levels. Improved…

  3. A Checklist for Designing and Evaluating Physical Education Program Web Sites

    Science.gov (United States)

    Tucker, Michael; Hill, Grant

    2009-01-01

    Creating a physical education department web site is an excellent way to promote a positive image of the program, because students and parents are able to find important information and improve the lines of communication. A well-designed physical education web site can even encourage students to increase their physical activity levels. Improved…

  4. Design of an instrument to measure the quality of care in Physical Therapy

    Science.gov (United States)

    Cavalheiro, Leny Vieira; Eid, Raquel Afonso Caserta; Talerman, Claudia; do Prado, Cristiane; Gobbi, Fátima Cristina Martorano; Andreoli, Paola Bruno de Araujo

    2015-01-01

    ABSTRACT Objective: To design an instrument composed of domains that would demonstrate physical therapy activities and generate a consistent index to represent the quality of care in physical therapy. Methods: The methodology Lean Six Sigma was used to design the tool. The discussion involved seven different management groups staff. By means of brainstorming and Cause & Effect Matrix, we set up the process map. Results: Five requirements composed the quality of care index in physical therapy, after application of the tool called Cause & Effect Matrix. The following requirements were assessed: physical therapist performance, care outcome indicator, adherence to physical therapy protocols, measure whether the prognosis and treatment outcome was achieved and Infrastructure. Conclusion: The proposed design allowed evaluating several items related to physical therapy service, enabling customization, reproducibility and benchmarking with other organizations. For management, this index provides the opportunity to identify areas for improvement and the strengths of the team and process of physical therapy care. PMID:26154548

  5. ReleQuant – Improving teaching and learning in quantum physics through educational design research

    Directory of Open Access Journals (Sweden)

    Berit Bungum

    2015-05-01

    Full Text Available Quantum physics and relativity are demanding for teachers and students, but have the potential for students to experience physics as fascinating and meaningful. Project ReleQuant engaged in educational design research to improve teaching and learning in these topics in Norwegian upper secondary schools. The paper focuses on the first cycle of development of a teaching module on quantum physics and how design principles were developed. We construct the design principles by reviewing relevant research literature and conducting three pilot studies. The process resulted in the following principles for designing the quantum physics teaching module: 1 clarify how quantum physics breaks with classical physics; 2 use simulations of phenomena that cannot be experienced directly; 3 provide students to use written and oral language; 4 address and discuss wave-particle duality and the uncertainty

  6. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  7. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  8. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  9. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  10. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  11. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  12. Physical Planning in Place-Making through Design and Image Building

    OpenAIRE

    2013-01-01

    This paper discusses how physical planning works with place-making through urban design to support image creation in a municipality that aims to create a new image for its city. Two large-scale urban development projects in Sweden are analysed. The analysis focuses on official plans and documentation, and expert interviews. It distinguishes how place-making by physical planning happens through aestheticisation, the design of physical environments for specific groups of inhabitants, and by gra...

  13. Occupant safety design approaches using physical testing and numerical simulation.

    NARCIS (Netherlands)

    Linzmaier, L.C.; Carvalho, J.R.; Benar, M.; Vilela, D.; Altamore, P.

    2001-01-01

    The vehicle design environment from a crashworthiness and safety perspective has become increasingly complex in recent years. New legal requirements imposed by the European Union (EU) and the United States National Highway Traffic Safety Administration (NHTSA) have created a design space of great

  14. Integration of educational methods and physical settings: design ...

    African Journals Online (AJOL)

    Quality design and appropriate space organization in preschool settings can ... an educational method in designing the school setting environment (Ata, .... and their experience of fulfilment in what they do (George, Louw & Badenhorst, .... pected to participate in the children's play and activities, so the size of the activity.

  15. Database design for Physical Access Control System for nuclear facilities

    Energy Technology Data Exchange (ETDEWEB)

    Sathishkumar, T., E-mail: satishkumart@igcar.gov.in; Rao, G. Prabhakara, E-mail: prg@igcar.gov.in; Arumugam, P., E-mail: aarmu@igcar.gov.in

    2016-08-15

    Highlights: • Database design needs to be optimized and highly efficient for real time operation. • It requires a many-to-many mapping between Employee table and Doors table. • This mapping typically contain thousands of records and redundant data. • Proposed novel database design reduces the redundancy and provides abstraction. • This design is incorporated with the access control system developed in-house. - Abstract: A (Radio Frequency IDentification) RFID cum Biometric based two level Access Control System (ACS) was designed and developed for providing access to vital areas of nuclear facilities. The system has got both hardware [Access controller] and software components [server application, the database and the web client software]. The database design proposed, enables grouping of the employees based on the hierarchy of the organization and the grouping of the doors based on Access Zones (AZ). This design also illustrates the mapping between the Employee Groups (EG) and AZ. By following this approach in database design, a higher level view can be presented to the system administrator abstracting the inner details of the individual entities and doors. This paper describes the novel approach carried out in designing the database of the ACS.

  16. Occupant safety design approaches using physical testing and numerical simulation.

    NARCIS (Netherlands)

    Linzmaier, L.C.; Carvalho, J.R.; Benar, M.; Vilela, D.; Altamore, P.

    2001-01-01

    The vehicle design environment from a crashworthiness and safety perspective has become increasingly complex in recent years. New legal requirements imposed by the European Union (EU) and the United States National Highway Traffic Safety Administration (NHTSA) have created a design space of great co

  17. Designing for Enhanced Conceptual Understanding in an Online Physics Course

    Science.gov (United States)

    Dunlap, Joanna C.; Furtak, Thomas E.; Tucker, Susan A.

    2009-01-01

    The calculus-based, introductory physics course is the port of entry for any student interested in pursuing a college degree in the sciences, mathematics, or engineering. There is increasing demand for online delivery options that make the course more widely available, especially those that use best practices in student engagement. However,…

  18. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  19. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  20. Design Dimensions Enabling Divergent Behaviour across Physical, Digital, and Social Library Interfaces

    Science.gov (United States)

    Björneborn, Lennart

    What design dimensions across physical, digital, and social library interfaces may enable and trigger users to find more information resources than planned or known in advance? The paper outlines a conceptual framework with libraries as integrative interfaces across physical, digital, and social affordances and users that mix convergent (goal-directed) and divergent (exploratory) information behaviour. Ten design dimensions that enable and trigger divergent behaviour are outlined. Implications for persuasive design are discussed.

  1. Design and Study of Cognitive Network Physical Layer Simulation Platform

    Directory of Open Access Journals (Sweden)

    Yongli An

    2014-01-01

    Full Text Available Cognitive radio technology has received wide attention for its ability to sense and use idle frequency. IEEE 802.22 WRAN, the first to follow the standard in cognitive radio technology, is featured by spectrum sensing and wireless data transmission. As far as wireless transmission is concerned, the availability and implementation of a mature and robust physical layer algorithm are essential to high performance. For the physical layer of WRAN using OFDMA technology, this paper proposes a synchronization algorithm and at the same time provides a public platform for the improvement and verification of that new algorithm. The simulation results show that the performance of the platform is highly close to the theoretical value.

  2. Design and Implementation of a Sort-Free K-Best Sphere Decoder

    KAUST Repository

    Mondal, Sudip

    2012-10-18

    This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.

  3. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  4. Conceptual design report: Neutrino physics after the Main Injector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Bernstein, R.; Beverly, L.; Browning, F.; Childress, S.; Freeman, W.; Jacobsen, V.; Koizumi, G.; Krider, J.; Kula, L.; Malensek, A.; Pordes, Stephen H.; /Fermilab /Ohio State U.

    1991-01-01

    The Main Injector will provide an unprecedented opportunity for challenging the Standard Model. The increased fluxes available from this essential upgrade make possible neutrino experiments of great power both at the Tevatron and at intermediate energies. With a factor of six increase in flux, experiments at higher energies probe with great sensitivity the electroweak sector, test QCD, and search for rare processes which could point the way to new physics. Such experiments can make simultaneous measurements of the Standard Model {rho} parameter and sin{sup 2} {theta}{sub W} to 0.25% and 0.6%, respectively. Measurements of the radiative corrections in electroweak physics will reveal physics at the TeV mass scale. {rho} probes the Higgs sector, and deviations from its expected value would be unambiguous signals of new phenomena and possibly our first clear window into physics beyond the Standard Model. Another way to quantify these corrections is through measurements of sin{sup 2} {theta}{sub W} in different processes; comparisons among an ensemble of precise electroweak measurements can then distinguish among alternatives and pin down the sources of new phenomena. Four processes likely to be important in the coming decade are the direct boson mass measurements, Z polarization asymmetries, atomic parity violation, and neutrino-nucleon scattering. Each of these processes has a different dependence on the various sources of new physics: such phenomena as multiple Z's, supersymmetry, or technicolor are just three of many possibilities. Neutral current measurements of sin{sup 2} {theta}{sub W} and {rho} have already provided constraints on m{sub t}; improved measurements will extend their reach and help us interpret the information from the colliders. QCD tests, especially those involving the structure function xF{sub 3}, can check two fundamental predictions of the theory: the dependence of the strong-coupling constant {alpha}{sub S}(Q{sup 2}) on Q{sup 2}, and the

  5. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  6. DESIGNING PHYSICAL EDUCATION LESSONS IN PRIMARY SCHOOL BY CONTENT TYPE FEED-FORWARD

    Directory of Open Access Journals (Sweden)

    Cojanu Florin

    2010-06-01

    Full Text Available In actual didactic design is need to anticipate problems that may arise during implementation of proposed interdisciplinary content in the physical education lesson in class, by projecting sequential forward type of content, there by ensuring quality and efficiency. Its necessary to include in the design content of physical education lessons in primary sequence type of feed-forward, to increase the quality and effectiveness of physical education lessons at the operational objectives achieved. To development modern didactics of physical education we can keep some purchases of traditionalteaching, but still with emphasis currently reconsidering its entire system on the content, forms, methods of education.

  7. Research in Geant4 electromagnetic physics design, and its effects on computational performance and quality assurance

    CERN Document Server

    Augelli, M; Hauf, S; Kim, C H; Kuster, M; Pia, M G; Filho, P Queiroz; Quintieri, L; Saracco, P; Santos, D Souza; Weidenspointner, G; Zoglauer, A

    2009-01-01

    The Geant4 toolkit offers a rich variety of electromagnetic physics models; so far the evaluation of this Geant4 domain has been mostly focused on its physics functionality, while the features of its design and their impact on simulation accuracy, computational performance and facilities for verification and validation have not been the object of comparable attention yet, despite the critical role they play in many experimental applications. A new project is in progress to study the application of new design concepts and software techniques in Geant4 electromagnetic physics, and to evaluate how they can improve on the current simulation capabilities. The application of a policy-based class design is investigated as a means to achieve the objective of granular decomposition of processes; this design technique offers various advantages in terms of flexibility of configuration and computational performance. The current Geant4 physics models have been re-implemented according to the new design as a pilot project....

  8. Impact of the LHCb upgrade detector design choices on physics and trigger performance

    CERN Document Server

    LHCb Collaboration

    2014-01-01

    The design of the detector for the LHCb upgrade has progressed rapidly to reach the status described in the subdetector technical design reports. The impact of the design choices that have been made on the physics and trigger performance is evaluated, and expected sensitivities for various key observables are updated based on the latest information.

  9. Towards Primary School Physics Teaching and Learning: Design Research Approach. Research Report 256

    Science.gov (United States)

    Juuti, Kalle

    2005-01-01

    This thesis describes a project to design a primary school physics learning environment which takes into account teachers' needs, design procedures, properties of the learning environment, and pupil learning outcomes. The project's design team has wide experience in research and development work in relation to science education, the use of ICT in…

  10. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  11. Value-driven coordination process design using physical delivery models

    NARCIS (Netherlands)

    Wieringa, R.J.; Pijpers, V.; Bodenstaff, L.; Gordijn, J.

    2008-01-01

    Current e-business technology enables the execution of increasingly complex coordination processes that link IT services of different companies. Successful design of cross-organizational coordination processes requires the mutual alignment of the coordination process with a commercial business case.

  12. Physical Theory of Vaccine Design for Influenza and Dengue Fever

    Science.gov (United States)

    Deem, Michael

    2009-03-01

    The immune system normally protects the human host against death by infection. I will introduce a physical theory of the evolutionary dynamics that occurs in the antibody-mediated and T cell-mediated immune responses. The theory will be used to provide a mechanism for original antigenic sin, wherein an initial exposure to antigen can degrade the response of the immune system upon subsequent exposure to related, but different, antigens. A new order parameter to characterize antigenic distance will be introduced from the theory. This order parameter predicts effectiveness of the influenza vaccine more reliably than do results from animal model studies currently used by world health authorities. I will discuss how this order parameter might be a valuable new tool for making vaccine-related public health policy decisions. Next, I will briefly discuss dengue fever. Infection with, or vaccination against, one of the four serotypes of dengue fever typically increases susceptibility to dengue hemorrhagic fever from one of the other three serotypes. I will present a physical theory of this immunodominance and use this theory to quantify the predicted mitigation of immunodominance in a novel formulation of the dengue vaccine.

  13. Design of Physical Games for Learning the Lotus Effect

    Directory of Open Access Journals (Sweden)

    Wernhuar Tarng

    2013-01-01

    Full Text Available The lotus effect is a learning topic of nanoscience commonly seen in elementary schools. However,nanostructures cannot be observed with naked eyes or using general microscopes. Lacking interactiveoperating environments, it is not easy to inspire students to explore nanophenomena. This study usedvirtual reality (VR technology to develop two physical games, namely “Water Drop in the Maze” and“Cleaning the Dust”, to show the macroscopic and microscopic structures of lotus leaves respectively.Students can control the rolling direction of water drop by the 3-axis accelerometers in smart phones ortablet PCs to complete the missions, and observe the hydrophobic effect and self-cleaning effect of the lotusas well the as the scales of water drops, dust and the nanostructure on the surface of lotus leaves. Ateaching experiment was conducted and the results showed the learning achievement of using physicalgames to learn the lotus effect was significantly higher than that of using instructional video. Thequestionnaire results also revealed that most students thought the physical games could enhance theirmotivation and interest in learning the lotus effect.

  14. Physics design of a saddle coil system for TCV

    Energy Technology Data Exchange (ETDEWEB)

    Rossel, J.X., E-mail: jonathan.rossel@epfl.ch; Moret, J.-M.; Martin, Y.; Pochon, G.

    2011-12-15

    Highlights: Black-Right-Pointing-Pointer The design of a saddle coil system for TCV is presented. Black-Right-Pointing-Pointer The system is designed for ELM control, error field correction and vertical control. Black-Right-Pointing-Pointer The issue of optimal design determination is addressed. Black-Right-Pointing-Pointer Electrical properties in the presence of a conducting wall are quantified. Black-Right-Pointing-Pointer Coil heating due to Joule effect and impact of plasma disruptions are considered. - Abstract: The upgrade project for TCV (Tokamak a Configuration Variable) includes the installation of a set of saddle coils, namely the saddle coil system (SCS), located and powered such as to create a helical magnetic perturbation. Using independent power supplies, the toroidal periodicity of this perturbation is tunable, allowing simultaneously edge localized modes (ELM) control through resonant magnetic perturbation (RMP), error field correction and vertical control. Other experimental applications, like resistive wall mode and rotation control, are also in view. In this article, the adequacy of two SCS designs, an in-vessel one and an ex-vessel one, is assessed with respect to the desired experimental applications. The current requirements and the system performances are also characterized. The conducting vessel wall is accounted for in a model used to determine the coupled response functions of the SCS, the screening of the magnetic perturbation by the wall, the induced voltages and currents during a plasma disruption and the maximal magnetic forces exerted on the SCS. A scaling of the SCS parameters with the number of coil turns is presented and the issue of coil heating and cooling is discussed.

  15. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  16. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  17. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  18. The Image Transceiver Device: Studies of Improved Physical Design

    Directory of Open Access Journals (Sweden)

    Uzi Efron

    2008-07-01

    Full Text Available The Image Transceiver Device (ITD design is based on combining LCOS micro-display, image processing tools and back illuminated APS imager in single CMOS chip [1]. The device is under development for Head-Mounted Display applications in augmented and virtual reality systems. The main issues with the present design are a high crosstalk of the backside imager and the need to shield the pixel circuitry from the photocharges generated in the silicon substrate. In this publication we present a modified, “deep p-well” ITD pixel design, which provides a significantly reduced crosstalk level, as well as an effective shielding of photo-charges for the pixel circuitry. The simulation performed using Silvaco software [ATLAS Silicon Device Simulator, Ray Trace and Light Absorption programs, Silvaco International, 1998] shows that the new approach provides high photo response and allows increasing the optimal thickness of the die over and above the 10-15 micrometers commonly used for back illuminated imaging devices, thereby improving its mechanical ruggedness following the thinning process and also providing a more efficient absorption of the long wavelength photons. The proposed deep p-well pixel structure is also a technology solution for the fabrication of high performance back illuminated CMOS image sensors.

  19. Designing and using multiple-possibility physics problems in physics courses

    Science.gov (United States)

    Shekoyan, Vazgen

    2012-02-01

    One important aspect of physics instruction is helping students develop better problem solving expertise. Besides enhancing the content knowledge, problems help students develop different cognitive abilities and skills. This presentation focuses on multiple-possibility problems (alternatively called ill-structured problems). These problems are different from traditional ``end of chapter'' single-possibility problems. They do not have one right answer and thus the student has to examine different possibilities, assumptions and evaluate the outcomes. To solve such problems one has to engage in a cognitive monitoring called epistemic cognition. It is an important part of thinking in real life. Physicists routinely use epistemic cognition when they solve problems. I have explored the instructional value of using such problems in introductory physics courses.

  20. Physical and Structural Design of Fast Extraction Kickers for CSNS/RCS

    CERN Document Server

    Lei, Wang; Yao-Dou, Hao; Yuan, Chen; Li-Hua, Huo

    2013-01-01

    China Spallation Neutron Source (CSNS) is a high intensity beam facility being built now in China. Three kicker assemblies, eight pulsed magnets, will be used in the CSNS rapid circle synchrotron (RCS). The physical and structural designs of eight kicker magnets that are grouped in 5 different types are presented. The results of OPERA-3D simulation show that magnet center field integral meet the physics requirements of design by choosing a suitable magnet coil structure. Field uniformity for 60% width is +/-0.7%. The ferrite magnet structure and composition is introduced, and the high voltage feedthrough design, the installation of six magnets in long vacuum cavity design is discussed.

  1. Physical design of positronium time of flight spectroscopy apparatus

    Institute of Scientific and Technical Information of China (English)

    JIANG Xiao-Pan; ZHANG Zi-Liang; QIN Xiu-Bo; YU Run-Sheng; WANG Bao-Yi

    2010-01-01

    Positronium time of flight spectroscopy(Ps-TOF)is an effective technique for porous material research.It has advantages over other techniques for analyzing the porosity and pore tortuosity of materials.This paper describes a design for Ps-TOF apparatus based on the Beijing intense slow positron beam,supplying a new material characterization technique.In order to improve the time resolution and increase the count rate of the apparatus,the detector system is optimized.For 3 eV o-Ps,the time broadening is 7.66 ns and the count rate is 3 cps after correction.

  2. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  3. Design Research in Cyber-Physical Systems through Weak-Bisimulation

    Directory of Open Access Journals (Sweden)

    Roy Mccann

    2011-12-01

    Full Text Available Bisimulation methods for design and verification of complex digital electronics have become well established in engineering practice. Concurrently, there have been dramatic theoretical advances in the theory of hybrid dynamical systems. This paper explores the how these advances can be incorporated into research methods for the emerging area of cyber-physical systems from a cybernetics perspective. The results can be used in determining how design of engineered systems can be safely integrated into physical systems.

  4. Physics design of the DARHT 2nd axis accelerator cell

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y J; Houck, T L; Reginato, L J; Shang, C C; Yu, S S

    1999-08-19

    The next generation of radiographic machines based on induction accelerators require very high brightness electron beams to realize the desired x-ray spot size and intensity. This high brightness must be maintained throughout the beam transport, from source to x-ray converter target. The accelerator for the second-axis of the Dual Axis Radiographic Hydrodynamic Test (DARHT) facility is being designed to accelerate a 4-kA, 2-{micro}s pulse of electrons to 20 MeV. After acceleration, the 2-{micro}s pulse will be chopped into a train of four 50-ns pulses with variable temporal spacing by rapidly deflecting the beam between a beam stop and the final transport section. The short beam pulses will be focused onto an x-ray converter target generating four radiographic pulses within the 2-{micro}s window. Beam instability due to interaction with the accelerator cells can very adversely effect the beam brightness and radiographic pulse quality. This paper describes the various issues considered in the design of the accelerator cell with emphasis on transverse impedance and minimizing beam instabilities.

  5. A quantum physical design flow using ILP and graph drawing

    Science.gov (United States)

    Yazdani, Maryam; Saheb Zamani, Morteza; Sedighi, Mehdi

    2013-10-01

    Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11 % for a set of attempted benchmarks and by about 9 % for another set of benchmarks compared with the best in literature.

  6. KIT multi-physics tools for the analysis of design and beyond design basis accidents of light water reactors

    Energy Technology Data Exchange (ETDEWEB)

    Sanchez, Victor Hugo; Miassoedov, Alexei; Steinbrueck, M.; Tromm, W. [Karlsruhe Institute of Technology (KIT), Eggenstein-Leopoldshafen (Germany)

    2016-05-15

    This paper describes the KIT numerical simulation tools under extension and validation for the analysis of design and beyond design basis accidents (DBA) of Light Water Reactors (LWR). The description of the complex thermal hydraulic, neutron kinetics and chemo-physical phenomena going on during off-normal conditions requires the development of multi-physics and multi-scale simulations tools which are fostered by the rapid increase in computer power nowadays. The KIT numerical tools for DBA and beyond DBA are validated using experimental data of KIT or from abroad. The developments, extensions, coupling approaches and validation work performed at KIT are shortly outlined and discussed in this paper.

  7. The physics design of accelerator-driven transmutation systems

    Energy Technology Data Exchange (ETDEWEB)

    Venneri, F.

    1995-02-01

    Nuclear systems under study in the Los Alamos Accelerator-Driven Transmutation Technology program (ADTT) will allow the destruction of nuclear spent fuel and weapons-return plutonium, as well as the production of nuclear energy from the thorium cycle, without a long-lived radioactive waste stream. The subcritical systems proposed represent a radical departure from traditional nuclear concepts (reactors), yet the actual implementation of ADTT systems is based on modest extrapolations of existing technology. These systems strive to keep the best that the nuclear technology has developed over the years, within a sensible conservative design envelope and eventually manage to offer a safer, less expensive and more environmentally sound approach to nuclear power.

  8. Resistive wall mode active control physics design for KSTAR

    Science.gov (United States)

    Park, Y. S.; Sabbagh, S. A.; Bak, J. G.; Bialek, J. M.; Berkery, J. W.; Lee, S. G.; Oh, Y. K.

    2014-01-01

    As KSTAR H-mode operation approaches the region where the resistive wall mode (RWM) can be unstable, an important issue for future long pulse, high beta plasma operation is to evaluate RWM active feedback control performance using a planned active/passive RWM stabilization system on the device. In particular, an optimal design of feedback sensors allows mode stabilization up to the highest achievable βN close to the ideal with-wall limit, βNwall, with reduced control power requirements. The computed ideal n = 1 mode structure from the DCON code has been input to the VALEN-3D code to calculate the projected performance of an active RWM control system in the KSTAR three-dimensional conducting structure device geometry. Control performance with the midplane locked mode detection sensors, off-midplane saddle loops, and magnetic pickup coils is examined. The midplane sensors measuring the radial component of the mode perturbation is found to be strongly affected by the wall eddy current. The off-axis saddle loops with proper compensation of the prompt applied field are computed to provide stabilization at βN up to 86% of βNwall but the low RWM amplitude computed in the off-axis regions near the sensors can produce a low signal-to-noise ratio. The required control power and bandwidth are also estimated with varied noise levels in the feedback sensors. Further improvements have been explored by examining a new RWM sensor design motivated by the off-midplane poloidal magnetic field sensors in NSTX. The new sensors mounted off of the copper passive stabilizer plates near the device midplane show a clear advantage in control performance corresponding to achieving 99% of βNwall without the need of compensation of the prompt field. The result shows a significant improvement of RWM feedback stabilization using the new sensor set which motivates a future feedback sensor upgrade.

  9. Associative Memory design for the Fast TracK processor (FTK) at Atlas

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Piendibene, M; Sacco, I; Sartori, L; Tripiccione, R

    2010-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. We propose now a new design (90 nm technology) where we introduce a full custom standard cell. This is a customized design that allows to maximize the pattern density and to minimize the power consumption. We discuss also possible future extensions based on 3-D technology. This processor has a flexible and easily configurable structure that makes it suitabl...

  10. Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

  11. Public open space, physical activity, urban design and public health: Concepts, methods and research agenda.

    Science.gov (United States)

    Koohsari, Mohammad Javad; Mavoa, Suzanne; Villanueva, Karen; Sugiyama, Takemi; Badland, Hannah; Kaczynski, Andrew T; Owen, Neville; Giles-Corti, Billie

    2015-05-01

    Public open spaces such as parks and green spaces are key built environment elements within neighbourhoods for encouraging a variety of physical activity behaviours. Over the past decade, there has been a burgeoning number of active living research studies examining the influence of public open space on physical activity. However, the evidence shows mixed associations between different aspects of public open space (e.g., proximity, size, quality) and physical activity. These inconsistencies hinder the development of specific evidence-based guidelines for urban designers and policy-makers for (re)designing public open space to encourage physical activity. This paper aims to move this research agenda forward, by identifying key conceptual and methodological issues that may contribute to inconsistencies in research examining relations between public open space and physical activity.

  12. ELEC-2005 - Electronics in High Energy Physics: Autumn Term (November-December 2005)

    CERN Multimedia

    Davide Vitè

    2005-01-01

    ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the ELEC-2002 course series. This new, comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 is composed of four Terms. The Winter (Introduction to electronics in HEP), Spring (Integrated circuits and VLSI technology for physics), and Summer (System electronics for physics: Issues) Terms already took place. The Autumn Term - Electronics applications in HEP experiments (November-December, 10 lectures) is still open for registration, and has started on November 8th with the following programme: Tuesday 8.11 - Tracking (Geoff Hall). Thursday 10.11 - Calorimetr...

  13. Technical Training: ELEC-2005 - Electronics in High Energy Physics: Summer Term (May 2005)

    CERN Multimedia

    Monique Duval

    2005-01-01

    ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the successful ELEC-2002 course series. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments. ELEC-2005 is composed of four Terms. The Winter (Introduction to electronics in HEP) and Spring (Integrated circuits and VLSI technology for physics) Terms already took place; the next two Terms will run with the following schedule: Summer Term: System electronics for physics: Issues (May, 7 lectures) - now open for registration Autumn Term: Electronics applications in HEP experiments (November-December, 10 lectures) Lectures within each Term will take place on Tuesday...

  14. CERN Technical Training 2005 - ELEC-2005: Electronics in High Energy Physics

    CERN Multimedia

    Monique Duval

    2004-01-01

    Learning for the LHC!ELEC-2005 is a new course series on modern electronics, given by CERN physicists and engineers within the framework of the 2005 Technical Training Programme, in an extended format of the successful ELEC-2002 course series. This comprehensive course series is designed for people who are not electronics specialists, for example physicists, engineers and technicians working at or visiting the laboratory, who use or will use electronics in their present or future activities, in particular in the context of the LHC accelerator and experiments.ELEC-2005 is composed of four Terms that will run throughout the year:Winter Term: Introduction to electronics in HEP (January-February, 6 lectures) Spring Term: Integrated circuits and VLSI technology for physics (March, 6 lectures) Summer Term: System electronics for physics: Issues (May, 7 lectures) Winter Term: Electronics applications in HEP experiments (November-December, 10 lectures) Lectures within each Term will take place on Tuesdays and Thursd...

  15. Vertical bifacial solar farms: Physics, design, and global optimization

    KAUST Repository

    Khan, M. Ryyan

    2017-09-04

    There have been sustained interest in bifacial solar cell technology since 1980s, with prospects of 30–50% increase in the output power from a stand-alone panel. Moreover, a vertical bifacial panel reduces dust accumulation and provides two output peaks during the day, with the second peak aligned to the peak electricity demand. Recent commercialization and anticipated growth of bifacial panel market have encouraged a closer scrutiny of the integrated power-output and economic viability of bifacial solar farms, where mutual shading will erode some of the anticipated energy gain associated with an isolated, single panel. Towards that goal, in this paper we focus on geography-specific optimization of ground-mounted vertical bifacial solar farms for the entire world. For local irradiance, we combine the measured meteorological data with the clear-sky model. In addition, we consider the effects of direct, diffuse, and albedo light. We assume the panel is configured into sub-strings with bypass-diodes. Based on calculated light collection and panel output, we analyze the optimum farm design for maximum yearly output at any given location in the world. Our results predict that, regardless of the geographical location, a vertical bifacial farm will yield 10–20% more energy than a traditional monofacial farm for a practical row-spacing of 2 m (corresponding to 1.2 m high panels). With the prospect of additional 5–20% energy gain from reduced soiling and tilt optimization, bifacial solar farm do offer a viable technology option for large-scale solar energy generation.

  16. Designing I*CATch: A Multipurpose, Education-Friendly Construction Kit for Physical and Wearable Computing

    Science.gov (United States)

    Ngai, Grace; Chan, Stephen C. F.; Leong, Hong Va; Ng, Vincent T. Y.

    2013-01-01

    This article presents the design and development of i*CATch, a construction kit for physical and wearable computing that was designed to be scalable, plug-and-play, and to provide support for iterative and exploratory learning. It consists of a standardized construction interface that can be adapted for a wide range of soft textiles or electronic…

  17. Developing a Conceptual Framework for Participatory Design of Psychosocial and Physical Learning Environments

    Science.gov (United States)

    Mäkelä, Tiina; Helfenstein, Sacha

    2016-01-01

    The present study shows how the mixed-methods approach can be used in capturing and organising learning environment (LE) characteristics for the participatory design of psychosocial and physical LEs involving learners. Theoretical constructs were tested and further elaborated on in the analysis of two similar educational design research studies:…

  18. The Effectiveness of Scaffolding Design in Training Writing Skills Physics Teaching Materials

    Science.gov (United States)

    Sinaga, Parlindungan; Suhandi, Andi; Liliasari

    2015-01-01

    Result of field studies showed low writing skill of teachers in teaching material. The root of the problem lies in their inability on translating description of teaching material into writing. This research focused on the effectiveness of scaffolding design. The scaffolding design was tested in the selected topics of physics courses for…

  19. Modelling of physical systems for the design and control of mechatronic systems

    NARCIS (Netherlands)

    Amerongen, van J.; Breedveld, P.C.

    2003-01-01

    Mechatronic design requires that a mechanical system and its control system be designed as an integrated system. This contribution covers the background and tools for modelling and simulation of physical systems and their controllers, with parameters that are directly related to the real-world syste

  20. Classroom Physical Design Influencing Student Learning and Evaluations of College Instructors: A Review of Literature

    Science.gov (United States)

    Lei, Simon A.

    2010-01-01

    The physical design of classrooms, including studios, laboratories, auditoriums, and other indoor environments, can have a profound impact on student learning and subsequent overall ratings (student evaluations) of college instructors. Many college classrooms have been conventionally designed in the shape of a square or a rectangle, with…

  1. Developing a Conceptual Framework for Participatory Design of Psychosocial and Physical Learning Environments

    Science.gov (United States)

    Mäkelä, Tiina; Helfenstein, Sacha

    2016-01-01

    The present study shows how the mixed-methods approach can be used in capturing and organising learning environment (LE) characteristics for the participatory design of psychosocial and physical LEs involving learners. Theoretical constructs were tested and further elaborated on in the analysis of two similar educational design research studies:…

  2. (Dis)Solving the Differences: A Physical Science Lesson Using Universal Design

    Science.gov (United States)

    Kurtts, Stephanie A.; Matthews, Catherine E.; Smallwood, Tammy

    2009-01-01

    Universal design for learning (UDL) holds promise for teachers who are struggling with creating lessons that allow all students access to and engagement with the general science curriculum. In this article, the authors demonstrate how a secondary physical science lesson about solubility and concentration can be designed for diverse learners' needs…

  3. Security-aware design for cyber-physical systems a platform-based approach

    CERN Document Server

    Lin, Chung-Wei

    2017-01-01

    Addressing the rising security issues during the design stages of cyber-physical systems, this book develops a systematic approach to address security at early design stages together with all other design constraints. Cyber-attacks become more threatening as systems are becoming more connected with the surrounding environment, infrastructures, and other systems. Security mechanisms can be designed to protect against attacks and meet security requirements, but there are many challenges of applying security mechanisms to cyber-physical systems including open environments, limited resources, strict timing requirements, and large number of devices. Designed for researchers and professionals, this book is valuable for individuals working in network systems, security mechanisms, and system design. It is also suitable for advanced-level students of computer science. .

  4. Aircraft Conceptual Design and Risk Analysis Using Physics-Based Noise Prediction

    Science.gov (United States)

    Olson, Erik D.; Mavris, Dimitri N.

    2006-01-01

    An approach was developed which allows for design studies of commercial aircraft using physics-based noise analysis methods while retaining the ability to perform the rapid trade-off and risk analysis studies needed at the conceptual design stage. A prototype integrated analysis process was created for computing the total aircraft EPNL at the Federal Aviation Regulations Part 36 certification measurement locations using physics-based methods for fan rotor-stator interaction tones and jet mixing noise. The methodology was then used in combination with design of experiments to create response surface equations (RSEs) for the engine and aircraft performance metrics, geometric constraints and take-off and landing noise levels. In addition, Monte Carlo analysis was used to assess the expected variability of the metrics under the influence of uncertainty, and to determine how the variability is affected by the choice of engine cycle. Finally, the RSEs were used to conduct a series of proof-of-concept conceptual-level design studies demonstrating the utility of the approach. The study found that a key advantage to using physics-based analysis during conceptual design lies in the ability to assess the benefits of new technologies as a function of the design to which they are applied. The greatest difficulty in implementing physics-based analysis proved to be the generation of design geometry at a sufficient level of detail for high-fidelity analysis.

  5. Enhancing pre-service physics teachers' creative thinking skills through HOT lab design

    Science.gov (United States)

    Malik, Adam; Setiawan, Agus; Suhandi, Andi; Permanasari, Anna

    2017-08-01

    A research on the implementation of HOT (Higher Order Thinking) Laboratory has been carried out. This research is aimed to compare increasing of creative thinking skills of pre-service physics teachers who receive physics lesson with HOT Lab and with verification lab for the topic of electric circuit. This research used a quasi-experiment methods with control group pretest-posttest design. The subject of the research is 40 Physics Education pre-service physics teachers of UIN Sunan Gunung Djati Bandung. Research samples were selected by class random sampling technique. Data on pre-service physics teachers' creative thinking skills were collected using test of creative thinking skills in the form of essay. The results of the research reveal that average of N-gain of creative thinking skills are for pre-service physics teachers who received lesson with HOT Lab design and for pre-service physics teachers who received lesson with verification lab, respectively. Therefore, we conclude that application of HOT Lab design is more effective to increase creative thinking skills in the lesson of electric circuit.

  6. Safeguards-by-Design: Early Integration of Physical Protection and Safeguardability into Design of Nuclear Facilities

    Energy Technology Data Exchange (ETDEWEB)

    T. Bjornard; R. Bean; S. DeMuth; P. Durst; M. Ehinger; M. Golay; D. Hebditch; J. Hockert; J. Morgan

    2009-09-01

    The application of a Safeguards-by-Design (SBD) process for new nuclear facilities has the potential to minimize proliferation and security risks as the use of nuclear energy expands worldwide. This paper defines a generic SBD process and its incorporation from early design phases into existing design / construction processes and develops a framework that can guide its institutionalization. SBD could be a basis for a new international norm and standard process for nuclear facility design. This work is part of the U.S. DOE’s Next Generation Safeguards Initiative (NGSI), and is jointly sponsored by the Offices of Non-proliferation and Nuclear Energy.

  7. Physical design correlates of efficiency and safety in emergency departments: a qualitative examination.

    Science.gov (United States)

    Pati, Debajyoti; Harvey, Thomas E; Pati, Sipra

    2014-01-01

    The objective of this study was to explore and identify physical design correlates of safety and efficiency in emergency department (ED) operations. This study adopted an exploratory, multimeasure approach to (1) examine the interactions between ED operations and physical design at 4 sites and (2) identify domains of physical design decision-making that potentially influence efficiency and safety. Multidisciplinary gaming and semistructured interviews were conducted with stakeholders at each site. Study data suggest that 16 domains of physical design decisions influence safety, efficiency, or both. These include (1) entrance and patient waiting, (2) traffic management, (3) subwaiting or internal waiting areas, (4) triage, (5) examination/treatment area configuration, (6) examination/treatment area centralization versus decentralization, (7) examination/treatment room standardization, (8) adequate space, (9) nurse work space, (10) physician work space, (11) adjacencies and access, (12) equipment room, (13) psych room, (14) staff de-stressing room, (15) hallway width, and (16) results waiting area. Safety and efficiency from a physical environment perspective in ED design are mutually reinforcing concepts--enhancing efficiency bears positive implications for safety. Furthermore, safety and security emerged as correlated concepts, with security issues bearing implications for safety, thereby suggesting important associations between safety, security, and efficiency.

  8. The T-Ruby Design System

    DEFF Research Database (Denmark)

    Sharp, Robin; Rasmussen, Ole Steen

    1997-01-01

    This paper describes the T-Ruby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctness-preserving transformations based on proved equivalences between...

  9. The T-Ruby design system

    DEFF Research Database (Denmark)

    Sharp, Robin; Rasmussen, Ole

    1995-01-01

    This paper describes the T-Ruby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctness-preserving transformations based on proved equivalences between...

  10. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  11. 3D Projection on Physical Objects: Design Insights from Five Real Life Cases

    DEFF Research Database (Denmark)

    Dalsgaard, Peter; Halskov, Kim

    2011-01-01

    3D projection on physical objects is a particular kind of Augmented Reality that augments a physical object by projecting digital content directly onto it, rather than by using a mediating device, such as a mobile phone or a head- mounted display. In this paper, we present five cases in which we...... have developed installations that employ 3D projection on physical objects. The installations have been developed in collaboration with external partners and have been put into use in real-life settings such as museums, exhibitions and interaction design laboratories. On the basis of these cases, we...... present and discuss three central design insights concerning new potentials for well-known 3D effects, dynamics between digital world and physical world, and relations between object, content and context....

  12. Physical and Emotional Benefits of Different Exercise Environments Designed for Treadmill Running

    Directory of Open Access Journals (Sweden)

    Hsiao-Pu Yeh

    2017-07-01

    Full Text Available (1 Background: Green physical activity promotes physical health and mental wellbeing and interesting questions concern effects of this information on designing indoor exercise environments. This study examined the physical and emotional effects of different nature-based environments designed for indoor treadmill running; (2 Methods: In a counterbalanced experimental design, 30 participants performed three, twenty-minute treadmill runs at a self-selected pace while viewing either a static nature image, a dynamic nature image or self-selected entertainment. Distance ran, heart rate (HR and five pre-and post-exercise emotional states were measured; (3 Results: Participants ran farther, and with higher HRs, with self-selected entertainment compared to the two nature-based environment designs. Participants attained lowered anger, dejection, anxiety and increased excitement post exercise in all of the designed environments. Happiness increased during the two nature-based environment designs compared with self-selected entertainment; (4 Conclusions: Self-selected entertainment encouraged greater physical performances whereas running in nature-based exercise environments elicited greater happiness immediately after running.

  13. Physical and Emotional Benefits of Different Exercise Environments Designed for Treadmill Running

    Science.gov (United States)

    Churchill, Sarah M.; Brymer, Eric; Davids, Keith

    2017-01-01

    (1) Background: Green physical activity promotes physical health and mental wellbeing and interesting questions concern effects of this information on designing indoor exercise environments. This study examined the physical and emotional effects of different nature-based environments designed for indoor treadmill running; (2) Methods: In a counterbalanced experimental design, 30 participants performed three, twenty-minute treadmill runs at a self-selected pace while viewing either a static nature image, a dynamic nature image or self-selected entertainment. Distance ran, heart rate (HR) and five pre-and post-exercise emotional states were measured; (3) Results: Participants ran farther, and with higher HRs, with self-selected entertainment compared to the two nature-based environment designs. Participants attained lowered anger, dejection, anxiety and increased excitement post exercise in all of the designed environments. Happiness increased during the two nature-based environment designs compared with self-selected entertainment; (4) Conclusions: Self-selected entertainment encouraged greater physical performances whereas running in nature-based exercise environments elicited greater happiness immediately after running. PMID:28696384

  14. A unified modeling approach for physical experiment design and optimization in laser driven inertial confinement fusion

    Energy Technology Data Exchange (ETDEWEB)

    Li, Haiyan [Mechatronics Engineering School of Guangdong University of Technology, Guangzhou 510006 (China); Huang, Yunbao, E-mail: Huangyblhy@gmail.com [Mechatronics Engineering School of Guangdong University of Technology, Guangzhou 510006 (China); Jiang, Shaoen, E-mail: Jiangshn@vip.sina.com [Laser Fusion Research Center, China Academy of Engineering Physics, Mianyang 621900 (China); Jing, Longfei, E-mail: scmyking_2008@163.com [Laser Fusion Research Center, China Academy of Engineering Physics, Mianyang 621900 (China); Tianxuan, Huang; Ding, Yongkun [Laser Fusion Research Center, China Academy of Engineering Physics, Mianyang 621900 (China)

    2015-11-15

    Highlights: • A unified modeling approach for physical experiment design is presented. • Any laser facility can be flexibly defined and included with two scripts. • Complex targets and laser beams can be parametrically modeled for optimization. • Automatically mapping of laser beam energy facilitates targets shape optimization. - Abstract: Physical experiment design and optimization is very essential for laser driven inertial confinement fusion due to the high cost of each shot. However, only limited experiments with simple structure or shape on several laser facilities can be designed and evaluated in available codes, and targets are usually defined by programming, which may lead to it difficult for complex shape target design and optimization on arbitrary laser facilities. A unified modeling approach for physical experiment design and optimization on any laser facilities is presented in this paper. Its core idea includes: (1) any laser facility can be flexibly defined and included with two scripts, (2) complex shape targets and laser beams can be parametrically modeled based on features, (3) an automatically mapping scheme of laser beam energy onto discrete mesh elements of targets enable targets or laser beams be optimized without any additional interactive modeling or programming, and (4) significant computation algorithms are additionally presented to efficiently evaluate radiation symmetry on the target. Finally, examples are demonstrated to validate the significance of such unified modeling approach for physical experiments design and optimization in laser driven inertial confinement fusion.

  15. Industry 4.0 with Cyber-Physical Integration: A Design and Manufacture Perspective

    OpenAIRE

    Saldivar, Alfredo Alan Flores; Li, Yun; Chen, Wei-Neng; Zhan, Zhi-Hui; Zhang, Jun; Chen, Leo Yi

    2015-01-01

    Foreseeing changes in the way companies manufacture products and provide services, future trends are emerging in design and manufacture. Together with growing internet applications and technologies connected through the cloud, a new Industrial Revolution, named “Industry 4.0”, aims to integrate cyber-virtual and cyber-physical systems to aid smart manufacturing, as presented in this paper. Connecting information and physical machinery, this new paradigm relies on how effective and fast connec...

  16. Evaluation of a course designed to teach physics to students of physiotherapy

    Science.gov (United States)

    Simpson, Ian A.; Singer, Kevin P.; Treagust, David; Zadnik, Marjan G.

    1990-01-01

    This paper describes the development and evaluation of a course in physiotherapy whereby the physics fundamental to the modalities of cold, heat and ultrasound therapies was integrated in lectures and actual physiotherapy activities. The design of the course is described together with the perceptions of physiotherapy students regarding the organisation of the course, safety aspects and how well the integration contributed to their understanding of the physics involved in electrotherapy.

  17. Design of Video Games for Children’s Diet and Physical Activity Behavior Change

    OpenAIRE

    Baranowski, Tom; Thompson, Debbe; Buday, Richard; Lu, Amy Shirong; Baranowski, Janice

    2010-01-01

    Serious video games (VG) offer new opportunities for promoting health related diet and physical activity change among children. Games can be designed to use storylines, characters, and behavior change procedures, including modeling (e.g., engaging characters make changes themselves, and face and overcome challenges related to fruit and vegetable (FV) and physical activity (PA) goal attainment and/or consumption), skill development (e.g., asking behaviors; virtual recipe preparation), self reg...

  18. Design and Simulation of a Quaternary Memory Cell based on a Physical Memristor

    DEFF Research Database (Denmark)

    Nannarelli, Alberto; Taylor, Jonathan

    2016-01-01

    Memristors were theorized more than fifty years ago, but only recently physical devices with memristor’s behavior have been fabricated and shipped. In this work, we experiment on one of these physical memristors by designing a memristorbased memory cell, implementing the cell, and testing it. Our...... experiments demonstrate that the memristor technology is not yet mature for practical applications, but, nevertheless, when production will provide reliable and dependable devices, memristorbased memory systems may replace CMOS memories with some advantages....

  19. Physical Layer Security Jamming: Theoretical Limits and Practical Designs in Wireless Networks

    OpenAIRE

    Cumanan, Kanapathippillai; Xing, Hong; Xu, Peng; Zheng, Gan; Dai, Xuchu; Nallanathan, Arumugam; Ding, Zhiguo; Karagiannidis, George K.

    2016-01-01

    Physical layer security has been recently recognizedas a promising new design paradigm to provide security inwireless networks. In addition to the existing conventional cryp-tographic methods, physical layer security exploits the dynamicsof fading channels to enhance secured wireless links. In thisapproach, jamming plays a key role by generating noise signalsto confuse the potential eavesdroppers, and significantly improvesquality and reliability of secure communications between legitimate te...

  20. Physical Layer Security Jamming: Theoretical Limits and Practical Designs in Wireless Networks

    OpenAIRE

    Cumanan, Kanapathippillai; Xing, Hong; Xu, Peng; Zheng, Gan; Dai, Xuchu; Nallanathan, Arumugam; Ding, Zhiguo; Karagiannidis, George K.

    2017-01-01

    Physical layer security has been recently recognized as a promising new design paradigm to provide security in wireless networks. In addition to the existing conventional cryptographic methods, physical layer security exploits the dynamics of fading channels to enhance secured wireless links. In this approach, jamming plays a key role by generating noise signals to confuse the potential eavesdroppers, and significantly improves quality and reliability of secure communications between legitima...

  1. DESIGNING A SYLLABUS OF COLLABORATIVE ENGLISH TEACHING FOR PHYSICS STUDY PROGRAM

    Directory of Open Access Journals (Sweden)

    Esti Junining

    2015-11-01

    Full Text Available The recommended model of teaching English for students of non-English department is collaborative teaching which provides subject lecturer‘s involvement in the curriculum design. This paper reported the process of designing a syllabus of collaborative teaching for ESP teaching in Indonesian context. As a part of curriculum design, this ESP syllabus focuses on content area reading in the area of physics. Several text types commonly used in physics department and vocabulary building of academic word lists and the ones related to physics area study were elaborated as well. The paper concludes that the implementation of this program needs high commitment from the stakeholders in order to make the program successfully implemented.

  2. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  3. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  4. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  5. 3D Projection on Physical Objects: Design Insights from Five Real Life Cases

    DEFF Research Database (Denmark)

    Dalsgaard, Peter; Halskov, Kim

    2011-01-01

    3D projection on physical objects is a particular kind of Augmented Reality that augments a physical object by projecting digital content directly onto it, rather than by using a mediating device, such as a mobile phone or a head- mounted display. In this paper, we present five cases in which we...... have developed installations that employ 3D projection on physical objects. The installations have been developed in collaboration with external partners and have been put into use in real-life settings such as museums, exhibitions and interaction design laboratories. On the basis of these cases, we...

  6. Evaluating the Physical Environment of Design Studios: A Case study in Malaysian Private Architecture Schools

    Directory of Open Access Journals (Sweden)

    Shanthi Muniandy

    2015-09-01

    Full Text Available Understanding the notion of learner’s experiences in the design of physical environment of an architecture design studio is a necessity as it contains certain values of influence. It is due to the unique learning experiences which are accrued particularly in design studio that is continued during professional practice as well. Most architectural campuses in Malaysian Private Higher Education Institutions (MPHEI are devoid of certain important elements and this issue needs to be looked into seriously. Apparently, most architectural design studios today have different physical settings, and have developed their own learning culture based on the typical space that they have. Reviewing the physical environment and how it contributes to the social environ-ment in MPHEI’s architectural context requires certain understanding on the learner’s psycho-logical needs, expectations and in the same time to meet the educational objective which is never an easy task. Hence, this paper reviewed the studies of the possible physical environment approaches in connecting the learner’s connections in architecture studio learning environ-ment. A questionnaire survey with Likert-scale components, and semi-structured interview on learners of five distinguished Private Architectural schools in Malaysia unveiled several signifi-cant findings that can lead entrepreneurs to upgrade the physical environment of these MPHEIs in order to cope with the demands of the stakeholders.

  7. Toward Co-Design of Autonomous Aerospace Cyber-Physical Systems

    Science.gov (United States)

    Bradley, Justin M.

    Modern vehicles are equipped with a complex suite of computing (cyber) and electromechanical (physical) systems. Holistic design, modeling, and optimization of such Cyber-Physical Systems (CPS) requires new techniques capable of integrated analysis across the full CPS. This dissertations introduces two methods for balancing cyber and physical resources in a step toward holistic co-design of CPS. First, an ordinary differential equation model abstraction of controller sampling rate is developed and added to the equations of motion of a physical system to form a holistic discrete-time-varying linear system representing the CPS controller. Using feedback control, this cyber effector, sampling rate, is then co-regulated alongside physical effectors in response to physical system tracking error. This technique is applied to a spring-mass-damper, inverted pendulum, and finally to attitude control of a small satellite (CubeSat). Additionally, two new controllers for discrete-time-varying systems are introduced; a gain-scheduled discrete-time linear regulator (DLQR) in which DLQR gains are scheduled over time-varying sampling rates, and a forward-propagation Riccati-based (FPRB) controller. The FPRB CPS controller shows promise in balancing cyber and physical resources. Second, we propose a cost function of cyber and physical parameters to optimize an Unmanned Aircraft System (UAS) trajectory for a pipeline surveillance mission. Optimization parameters are UAV velocity and mission-critical surveillance task execution rate. Metrics for pipeline image information, energy, cyber utilization, and time comprise the cost function and Pareto fronts are analyzed to gain insight into cyber and physical tradeoffs for mission success. Finally, the cost function is optimized using numerical methods, and results from several cost weightings and Pareto front analyses are tabulated. We show that increased mission success can be achieved by considering both cyber and physical parameters

  8. 2nd Workshop on Design for Social Interaction through Physical Play

    Science.gov (United States)

    Bekker, Tilde; Sturm, Janienke; Barakova, Emilia

    We aim to stimulate social interaction by designing and creating interactive objects for physical play for diverse user groups, such as children, elderly or people with special needs. With this workshop we aim to bring researchers and practitioners together to share and explore issues and opportunities for technology-enhanced physical play for stimulating face-to-face social interaction (as opposed to virtual interaction through a computer). The focus of this workshop is on sharing theories that are valuable for the design and research of products and applications in this field.

  9. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  10. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  11. Worksite interventions for preventing physical deterioration among employees in job-groups with high physical work demands: background, design and conceptual model of FINALE

    DEFF Research Database (Denmark)

    Holtermann, Andreas; Jørgensen, Marie B; Gram, Bibi;

    2010-01-01

    A mismatch between individual physical capacities and physical work demands enhance the risk for musculoskeletal disorders, poor work ability and sickness absence, termed physical deterioration. However, effective intervention strategies for preventing physical deterioration in job groups with high...... physical demands remains to be established. This paper describes the background, design and conceptual model of the FINALE programme, a framework for health promoting interventions at 4 Danish job groups (i.e. cleaners, health-care workers, construction workers and industrial workers) characterized by high...... physical work demands, musculoskeletal disorders, poor work ability and sickness absence....

  12. Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Directory of Open Access Journals (Sweden)

    Danielle S Bassett

    2010-04-01

    Full Text Available Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.

  13. Goals and design of public physics lectures: perspectives of high-school students, physics teachers and lecturers

    Science.gov (United States)

    Kapon, S.; Ganiel, U.; Eylon, B.

    2009-09-01

    Many large scientific projects and scientific centres incorporate some kind of outreach programme. Almost all of these outreach programmes include public scientific lectures delivered by practising scientists. In this article, we examine such lectures from the perspectives of: (i) lecturers (7) who are practising scientists acknowledged to be good public lecturers and (ii) audiences composed of high-school students (169) and high-school physics teachers (80) who attended these lectures. We identify and discuss the main goals as expressed by the lecturers and the audiences, and the correspondence between these goals. We also discuss how the lecturers' goals impact on the design of their lectures and examine how the lecture affects audiences with different attitudes towards (and interests in) physics. Our findings suggest that the goals of the participating lecturers and the expectations of their audiences were highly congruent. Both believe that a good public scientific lecture must successfully communicate state-of-the-art scientific knowledge to the public, while inspiring interest in and appreciation of science. Our findings also suggest that exemplary public scientific lectures incorporate content, structure and explanatory means that explicitly adhere to the lecturers' goals. We identify and list several design principles.

  14. Physical Design Progress of an 800 MeV Proton Cyclotron

    Institute of Scientific and Technical Information of China (English)

    YANG; Jian-jun; LI; Ming; ZHANG; Tian-jue

    2013-01-01

    Based on the pervious conceptual design work,we carried out further physical design recently.A 3D FEA model of the magnet is built(as is shown in Fig.1)and the isochronous magnet field is obtained by iterative optimization of the magnet structure.Fig.2 shows the differential phase error of the field,which is within 0.05 percent except the extraction region.After that the accelerating orbit is calculated.In the

  15. Description of research design of articles published in four Brazilian physical therapy journals

    Directory of Open Access Journals (Sweden)

    Bruno T. Saragiotto

    2014-03-01

    Full Text Available Background : While the research design of articles published in medical journals and in some physical therapy journals has already been evaluated, this has not been investigated in Brazilian physical therapy journals. Objective : To describe the research design used in all articles published in Brazilian scientific journals that are freely available, have high Qualis rankings, and are relevant to physical therapy over a 7-year period. Method : We extracted the bibliometric data, research design, research type (human or animal, and clinical area for all articles published. The articles were grouped into their level of evidence, and descriptive analyses were performed. We calculated the frequency, proportions of articles, and 95% confidence interval of these proportions with each research design in each journal. We cross-tabulated the clinical areas with research designs (expressed as number and percentages. Results : A total of 1,458 articles from four Brazilian journals were found: Revista Brasileira de Fisioterapia, Revista Fisioterapia em Movimento, Revista Fisioterapia e Pesquisa, and Revista Acta Fisiátrica. The majority of articles were classified as level II of evidence (60%, followed by level III (29% and level I (10%. The most prevalent research designs were cross-sectional studies (38%, single-case or case-series studies, and narrative reviews. Most articles reported human research and were in the musculoskeletal, neurologic, and cardiothoracic areas. Conclusions : Most of the research published in Brazilian physical therapy journals used levels II and III of evidence. Increasing the publication rate of systematic reviews and randomized controlled trials would provide more high-quality evidence to guide evidence-based physical therapy practice.

  16. Description of research design of articles published in four Brazilian physical therapy journals.

    Science.gov (United States)

    Saragiotto, Bruno T; Costa, Lucíola C M; Oliveira, Ronaldo F; Lopes, Alexandre D; Moseley, Anne M; Costa, Leonardo O P

    2014-01-01

    While the research design of articles published in medical journals and in some physical therapy journals has already been evaluated, this has not been investigated in Brazilian physical therapy journals. Objective : To describe the research design used in all articles published in Brazilian scientific journals that are freely available, have high Qualis rankings, and are relevant to physical therapy over a 7-year period. We extracted the bibliometric data, research design, research type (human or animal), and clinical area for all articles published. The articles were grouped into their level of evidence, and descriptive analyses were performed. We calculated the frequency, proportions of articles, and 95% confidence interval of these proportions with each research design in each journal. We cross-tabulated the clinical areas with research designs (expressed as number and percentages). A total of 1,458 articles from four Brazilian journals were found: Revista Brasileira de Fisioterapia, Revista Fisioterapia em Movimento, Revista Fisioterapia e Pesquisa, and Revista Acta Fisiátrica. The majority of articles were classified as level II of evidence (60%), followed by level III (29%) and level I (10%). The most prevalent research designs were cross-sectional studies (38%), single-case or case-series studies, and narrative reviews. Most articles reported human research and were in the musculoskeletal, neurologic, and cardiothoracic areas. Most of the research published in Brazilian physical therapy journals used levels II and III of evidence. Increasing the publication rate of systematic reviews and randomized controlled trials would provide more high-quality evidence to guide evidence-based physical therapy practice.

  17. Output Feedback Controller Design with Symbolic Observers for Cyber-physical Systems

    Directory of Open Access Journals (Sweden)

    Masashi Mizoguchi

    2016-12-01

    Full Text Available In this paper, we design a symbolic output feedback controller of a cyber-physical system (CPS. The physical plant is modeled by an infinite transition system. We consider the situation that a finite abstracted system of the physical plant, called a c-abstracted system, is given. There exists an approximate alternating simulation relation from the c-abstracted system to the physical plant. A desired behavior of the c-abstracted system is also given, and we have a symbolic state feedback controller of the physical plant. We consider the case where some states of the plant are not measured. Then, to estimate the states with abstracted outputs measured by sensors, we introduce a finite abstracted system of the physical plant, called an o-abstracted system, such that there exists an approximate simulation relation. The relation guarantees that an observer designed based on the state of the o-abstracted system estimates the current state of the plant. We construct a symbolic output feedback controller by composing these systems. By a relation-based approach, we proved that the controlled system approximately exhibits the desired behavior.

  18. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Science.gov (United States)

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  19. Photovoltaic concentrator optical system design: Solar energy engineering from physics to field

    Science.gov (United States)

    Coughenour, Blake Michael

    This dissertation describes the design, development, and field validation of a concentrator photovoltaic (CPV) solar energy system. The challenges of creating a highly efficient yet low-cost system architecture come from many sources. The solid-state physics of photovoltaic devices present fundamental limits to photoelectron conversion efficiency, while the electrical and thermal characteristics of widely available materials limit the design arena. Furthermore, the need for high solar spectral throughput, evenly concentrated sunlight, and tolerance to off-axis pointing places strict illumination requirements on the optical design. To be commercially viable, the cost associated with all components must be minimized so that when taken together, the absolute installed cost of the system in kWh is lower than any other solar energy method, and competitive with fossil fuel power generation. The work detailed herein focuses specifically on unique optical design and illumination concepts discovered when developing a viable commercial CPV system. By designing from the ground up with the fundamental physics of photovoltaic devices and the required system tolerances in mind, a select range of optical designs are determined and modeled. Component cost analysis, assembly effort, and development time frame further influence design choices to arrive at a final optical system design. When coupled with the collecting mirror, the final optical hardware unit placed at the focus generates more than 800W, yet is small and lightweight enough to hold in your hand. After fabrication and installation, the completed system's illumination, spectral, and thermal performance is validated with on-sun operational testing.

  20. Design of a website on nutrition and physical activity for adolescents: results from formative research

    Science.gov (United States)

    Teens do not meet guidelines for healthy eating and physical activity. The internet may be an effective method for delivering programs that help them adopt healthy behaviors. Our objective was to collect information to design content and structure for a teen-friendly web site promoting healthy eati...

  1. Advanced human body modelling to support designing products for physical interaction

    NARCIS (Netherlands)

    Moes, C.C.M.

    2004-01-01

    We are using many designed artefacts in our daily life. These artefacts are typically in physical interaction with the human body, and cause stresses and deformations inside the tissues. When these stresses exceed a given level, the proper physiological functioning of the tissues is limited, and erg

  2. Advanced human body modelling to support designing products for physical interaction

    NARCIS (Netherlands)

    Moes, C.C.M.

    2004-01-01

    We are using many designed artefacts in our daily life. These artefacts are typically in physical interaction with the human body, and cause stresses and deformations inside the tissues. When these stresses exceed a given level, the proper physiological functioning of the tissues is limited, and

  3. Design of video games for children's diet and physical activity behavior change

    Science.gov (United States)

    Serious video games (VG) offer new opportunities for promoting health related diet, and physical activity change among children. Games can be designed to use storylines, characters, and behavior change procedures, including modeling (e.g., engaging characters make changes themselves, and face and ov...

  4. Probabilistic Design and Management of Sustainable Concrete Infrastructure Using Multi-Physics Service Life Models

    DEFF Research Database (Denmark)

    Lepech, Michael; Geiker, Mette; Michel, Alexander

    cycles in the broader architecture, engineering, construction (AEC) industry. Specifically, a probabilistic design framework for sustainable concrete infrastructure and a multi-physics service life model for reinforced concrete are presented as important points of integration for innovation between...... design, consists of concrete service life models and life cycle assessment (LCA) models. Both types of models (service life and LCA) are formulated stochastically so that the service life and time(s) to repair, as well as total sustainability impact, are described by a probability distribution. A central...... component of this framework is a newly developed multi-physics service life model of reinforced concrete members subjected to chloride-induced corrosion. The corrosion model is based on stringent physical laws describing thermodynamics and kinetics of electrochemical processes including various...

  5. RetroFab: A Design Tool for Retrofitting Physical Interfaces using Actuators, Sensors and 3D Printing

    OpenAIRE

    2016-01-01

    We present RetroFab, an end-to-end design and fabrication environment that allows non-experts to retrofit physical interfaces. Our approach allows for changing the layout and behavior of physical interfaces. Unlike customizing software interfaces, physical interfaces are often challenging to adapt because of their rigidity. With RetroFab, a new physical interface is designed that serves as a proxy interface for the legacy controls that are now operated by actuators. RetroFab makes this concep...

  6. Analysis of boundary point (break point) in Linear Delay Model for nanoscale VLSI standard cell library characterization at PVT corners

    CERN Document Server

    Agarwal, Gaurav Kumar

    2014-01-01

    In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay is picked from Look Up Tables (LUT) rather than conventional SPICE simulations. But accuracy of this method depends upon the underlying delay model with which LUT was characterized. Non Linear Delay Model (NLDM) based LUTs are quite common in industries. These LUT requires huge amount to time during characterization because of huge number of SPICE simulations done at arbitrary points. To improve this people proposed various other delay models like alpha-power and piecewise linear delay models. Bulusu et al proposed Linear Delay Model(LDM) which reduces LUT generation time to 50 percent. LDM divides delay curve w.r.t input rise time(trin) into two different region one is linear and other is non-linear. This boundary point between linear and non- linear region was called break point (trb). Linear region will be done if we simulate at only two points. This advantage...

  7. An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

    CERN Document Server

    Mücke, M; Jacobsson, R

    2007-01-01

    Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that funct...

  8. Physical design of magnetic shielding for LEReC cooling section

    Energy Technology Data Exchange (ETDEWEB)

    Seletskiy, S. [Brookhaven National Lab. (BNL), Upton, NY (United States); Fedotov, A. [Brookhaven National Lab. (BNL), Upton, NY (United States); Gassner, D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Kayran, D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Mahler, G. [Brookhaven National Lab. (BNL), Upton, NY (United States); Meng, W. [Brookhaven National Lab. (BNL), Upton, NY (United States); Thieberger, P. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2016-04-05

    The goal of this note is to set basic parameters for the magnetic shielding of LEReC CS with required design attenuation. We considered physical design of magnetic shielding of LEReC cooling section. The schematic of this design along with the list of its basic parameters is shown. We are planning to use 2 layers of 1 mm thick cylindrical mu-metal shields with μ=11000. The radius of the first layer sitting on top of vacuum chamber is 63.5 mm. The second layer radius is 150 mm. Such shielding guarantees adequate transverse angles of electron beam trajectory in the CS.

  9. Human-centered design of a cyber-physical system for advanced response to Ebola (CARE).

    Science.gov (United States)

    Dimitrov, Velin; Jagtap, Vinayak; Skorinko, Jeanine; Chernova, Sonia; Gennert, Michael; Padir, Taşkin

    2015-01-01

    We describe the process towards the design of a safe, reliable, and intuitive emergency treatment unit to facilitate a higher degree of safety and situational awareness for medical staff, leading to an increased level of patient care during an epidemic outbreak in an unprepared, underdeveloped, or disaster stricken area. We start with a human-centered design process to understand the design challenge of working with Ebola treatment units in Western Africa in the latest Ebola outbreak, and show preliminary work towards cyber-physical technologies applicable to potentially helping during the next outbreak.

  10. Physics and engineering studies on the MITICA accelerator: comparison among possible design solutions

    Science.gov (United States)

    Agostinetti, P.; Antoni, V.; Cavenago, M.; Chitarin, G.; Pilan, N.; Marcuzzi, D.; Serianni, G.; Veltri, P.

    2011-09-01

    Consorzio RFX in Padova is currently using a comprehensive set of numerical and analytical codes, for the physics and engineering design of the SPIDER (Source for Production of Ion of Deuterium Extracted from RF plasma) and MITICA (Megavolt ITER Injector Concept Advancement) experiments, planned to be built at Consorzio RFX. This paper presents a set of studies on different possible geometries for the MITICA accelerator, with the objective to compare different design concepts and choose the most suitable one (or ones) to be further developed and possibly adopted in the experiment. Different design solutions have been discussed and compared, taking into account their advantages and drawbacks by both the physics and engineering points of view.

  11. Constructal law of design and evolution: Physics, biology, technology, and society

    Science.gov (United States)

    Bejan, Adrian; Lorente, Sylvie

    2013-04-01

    This is a review of the theoretical and applied progress made based on the Constructal law of design and evolution in nature, with emphasis on the last decade. The Constructal law is the law of physics that accounts for the natural tendency of all flow systems (animate and inanimate) to change into configurations that offer progressively greater flow access over time. The progress made with the Constructal law covers the broadest range of science, from heat and fluid flow and geophysics, to animal design, technology evolution, and social organization (economics, government). This review presents the state of this fast growing field, and draws attention to newly opened directions for original research. The Constructal law places the concepts of life, design, and evolution in physics.

  12. DAWN (Design Assistant Workstation) for advanced physical-chemical life support systems

    Science.gov (United States)

    Rudokas, Mary R.; Cantwell, Elizabeth R.; Robinson, Peter I.; Shenk, Timothy W.

    1989-01-01

    This paper reports the results of a project supported by the National Aeronautics and Space Administration, Office of Aeronautics and Space Technology (NASA-OAST) under the Advanced Life Support Development Program. It is an initial attempt to integrate artificial intelligence techniques (via expert systems) with conventional quantitative modeling tools for advanced physical-chemical life support systems. The addition of artificial intelligence techniques will assist the designer in the definition and simulation of loosely/well-defined life support processes/problems as well as assist in the capture of design knowledge, both quantitative and qualitative. Expert system and conventional modeling tools are integrated to provide a design workstation that assists the engineer/scientist in creating, evaluating, documenting and optimizing physical-chemical life support systems for short-term and extended duration missions.

  13. Physics-based enzyme design: predicting binding affinity and catalytic activity.

    Science.gov (United States)

    Sirin, Sarah; Pearlman, David A; Sherman, Woody

    2014-12-01

    Computational enzyme design is an emerging field that has yielded promising success stories, but where numerous challenges remain. Accurate methods to rapidly evaluate possible enzyme design variants could provide significant value when combined with experimental efforts by reducing the number of variants needed to be synthesized and speeding the time to reach the desired endpoint of the design. To that end, extending our computational methods to model the fundamental physical-chemical principles that regulate activity in a protocol that is automated and accessible to a broad population of enzyme design researchers is essential. Here, we apply a physics-based implicit solvent MM-GBSA scoring approach to enzyme design and benchmark the computational predictions against experimentally determined activities. Specifically, we evaluate the ability of MM-GBSA to predict changes in affinity for a steroid binder protein, catalytic turnover for a Kemp eliminase, and catalytic activity for α-Gliadin peptidase variants. Using the enzyme design framework developed here, we accurately rank the most experimentally active enzyme variants, suggesting that this approach could provide enrichment of active variants in real-world enzyme design applications.

  14. ACCELERATOR PHYSICS CHALLENGES IN THE DESIGN OF MULTI-BEND-ACHROMAT-BASED STORAGE RINGS

    Energy Technology Data Exchange (ETDEWEB)

    Borland, M.; Hettel, R.; Leemann, S. C.; Robin, D. S.

    2017-06-01

    With the recent success in commissioning of MAX IV, the multi-bend achromat (MBA) lattice has begun to deliver on its promise to usher in a new generation of higher-brightness synchrotron light sources. In this paper, we begin by reviewing the challenges, recent success, and lessons learned of the MAX-IV project. Drawing on these lessons, we then describe the physics challenges in even more ambitious rings and how these can be met. In addition, we touch on engineering issues and choices that are tightly linked with the physics design.

  15. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  16. PHYSICS

    CERN Multimedia

    P. Sphicas

    There have been three physics meetings since the last CMS week: “physics days” on March 27-29, the Physics/ Trigger week on April 23-27 and the most recent physics days on May 22-24. The main purpose of the March physics days was to finalize the list of “2007 analyses”, i.e. the few topics that the physics groups will concentrate on for the rest of this calendar year. The idea is to carry out a full physics exercise, with CMSSW, for select physics channels which test key features of the physics objects, or represent potential “day 1” physics topics that need to be addressed in advance. The list of these analyses was indeed completed and presented in the plenary meetings. As always, a significant amount of time was also spent in reviewing the status of the physics objects (reconstruction) as well as their usage in the High-Level Trigger (HLT). The major event of the past three months was the first “Physics/Trigger week” in Apri...

  17. Neural Computing in High Energy Physics

    Institute of Scientific and Technical Information of China (English)

    O.D.Joukov; N.D.Rishe

    2001-01-01

    Artifical neural networks (ANN) are now widely used successfully as tools for hith energy physics.The paper covers two aspects.First,mapping ANNs onto the proposed ring and linear systolic array provides an efficient implementation of VLSI-based architectures since in this case all connections among processing elements are local and regular,Second.it is discussed algorthmic organizing of such structures on the base of modular algebra whose use can provide an essential increase of system throughput.

  18. Design of heavy-ion APF-IH type linac for atomic physics and medical use

    Science.gov (United States)

    Hata, T.; Hattori, T.; Kashiwagi, H.; Takahashi, Y.; Yamamoto, K.; Matsui, S.; Dudu, D.; Osvath, E.; Vata, I.; Yamada, S.

    2002-04-01

    We have studied a compact heavy-ion linac for atomic physics and medical use. The design of the linac was based on using alternating-phase-focus (APF) and interdigital-H (IH) structures which give sufficient electric power efficiency. Thereby, it will be possible to design a small and high efficiency linac. The APF-IH linac was designed to accelerate ions from C 2+ to U 40+, from 30 to 300 keV/u and an operating frequency of 100 MHz. We made a half-scale cold model of this linac using orbit calculation and measured its RF characteristics. Then, we designed a APF-IH type linac using the results of the measurement.

  19. Design of heavy-ion APF-IH type linac for atomic physics and medical use

    Energy Technology Data Exchange (ETDEWEB)

    Hata, T. E-mail: hata@es.titech.ac.jp; Hattori, T.; Kashiwagi, H.; Takahashi, Y.; Yamamoto, K.; Matsui, S.; Dudu, D.; Osvath, E.; Vata, I.; Yamada, S

    2002-04-01

    We have studied a compact heavy-ion linac for atomic physics and medical use. The design of the linac was based on using alternating-phase-focus (APF) and interdigital-H (IH) structures which give sufficient electric power efficiency. Thereby, it will be possible to design a small and high efficiency linac. The APF-IH linac was designed to accelerate ions from C{sup 2+} to U{sup 40+}, from 30 to 300 keV/u and an operating frequency of 100 MHz. We made a half-scale cold model of this linac using orbit calculation and measured its RF characteristics. Then, we designed a APF-IH type linac using the results of the measurement.0.

  20. Design Impedance Mismatch Physical Unclonable Functions for IoT Security

    Directory of Open Access Journals (Sweden)

    Xiaomin Zheng

    2017-01-01

    Full Text Available We propose a new design, Physical Unclonable Function (PUF scheme, for the Internet of Things (IoT, which has been suffering from multiple-level security threats. As more and more objects interconnect on IoT networks, the identity of each thing is very important. To authenticate each object, we design an impedance mismatch PUF, which exploits random physical factors of the transmission line to generate a security unique private key. The characteristic impedance of the transmission line and signal transmission theory of the printed circuit board (PCB are also analyzed in detail. To improve the reliability, current feedback amplifier (CFA method is applied on the PUF. Finally, the proposed scheme is implemented and tested. The measure results show that impedance mismatch PUF provides better unpredictability and randomness.