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Sample records for vlsi neuromorphs possess

  1. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  2. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  3. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  4. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  5. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  6. A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.

    Science.gov (United States)

    Mill, R; Sheik, S; Indiveri, G; Denham, S L

    2011-10-01

    Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.

  7. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Science.gov (United States)

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  8. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  9. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  10. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  11. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  12. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  13. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  14. Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

    Science.gov (United States)

    Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; Del Giudice, Paolo

    2015-10-01

    Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

  15. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

    Directory of Open Access Journals (Sweden)

    Giacomo Indiveri

    2008-09-01

    Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  16. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    Science.gov (United States)

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.

  17. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  18. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  19. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  20. Large-scale neuromorphic computing systems

    Science.gov (United States)

    Furber, Steve

    2016-10-01

    Neuromorphic computing covers a diverse range of approaches to information processing all of which demonstrate some degree of neurobiological inspiration that differentiates them from mainstream conventional computing systems. The philosophy behind neuromorphic computing has its origins in the seminal work carried out by Carver Mead at Caltech in the late 1980s. This early work influenced others to carry developments forward, and advances in VLSI technology supported steady growth in the scale and capability of neuromorphic devices. Recently, a number of large-scale neuromorphic projects have emerged, taking the approach to unprecedented scales and capabilities. These large-scale projects are associated with major new funding initiatives for brain-related research, creating a sense that the time and circumstances are right for progress in our understanding of information processing in the brain. In this review we present a brief history of neuromorphic engineering then focus on some of the principal current large-scale projects, their main features, how their approaches are complementary and distinct, their advantages and drawbacks, and highlight the sorts of capabilities that each can deliver to neural modellers.

  1. Neuromorphic VLSI realization of the hippocampal formation.

    Science.gov (United States)

    Aggarwal, Anu

    2016-05-01

    The medial entorhinal cortex grid cells, aided by the subicular head direction cells, are thought to provide a matrix which is utilized by the hippocampal place cells for calculation of position of an animal during spatial navigation. The place cells are thought to function as an internal GPS for the brain and provide a spatiotemporal stamp on episodic memories. Several computational neuroscience models have been proposed to explain the place specific firing patterns of the cells of the hippocampal formation - including the GRIDSmap model for grid cells and Bayesian integration for place cells. In this work, we present design and measurement results from a first ever system of silicon circuits which successfully realize the function of the hippocampal formation of brain based on these models.

  2. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  3. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  4. Neuromorphic neural interfaces: from neurophysiological inspiration to biohybrid coupling with nervous systems

    Science.gov (United States)

    Broccard, Frédéric D.; Joshi, Siddharth; Wang, Jun; Cauwenberghs, Gert

    2017-08-01

    Objective. Computation in nervous systems operates with different computational primitives, and on different hardware, than traditional digital computation and is thus subjected to different constraints from its digital counterpart regarding the use of physical resources such as time, space and energy. In an effort to better understand neural computation on a physical medium with similar spatiotemporal and energetic constraints, the field of neuromorphic engineering aims to design and implement electronic systems that emulate in very large-scale integration (VLSI) hardware the organization and functions of neural systems at multiple levels of biological organization, from individual neurons up to large circuits and networks. Mixed analog/digital neuromorphic VLSI systems are compact, consume little power and operate in real time independently of the size and complexity of the model. Approach. This article highlights the current efforts to interface neuromorphic systems with neural systems at multiple levels of biological organization, from the synaptic to the system level, and discusses the prospects for future biohybrid systems with neuromorphic circuits of greater complexity. Main results. Single silicon neurons have been interfaced successfully with invertebrate and vertebrate neural networks. This approach allowed the investigation of neural properties that are inaccessible with traditional techniques while providing a realistic biological context not achievable with traditional numerical modeling methods. At the network level, populations of neurons are envisioned to communicate bidirectionally with neuromorphic processors of hundreds or thousands of silicon neurons. Recent work on brain-machine interfaces suggests that this is feasible with current neuromorphic technology. Significance. Biohybrid interfaces between biological neurons and VLSI neuromorphic systems of varying complexity have started to emerge in the literature. Primarily intended as a

  5. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  6. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  7. Dynamic Neural Fields as a Step Towards Cognitive Neuromorphic Architectures

    Directory of Open Access Journals (Sweden)

    Yulia eSandamirskaya

    2014-01-01

    Full Text Available Dynamic Field Theory (DFT is an established framework for modelling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF. Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analogue Very Large Scale Integration (VLSI device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

  8. Foldable neuromorphic memristive electronics

    KAUST Repository

    Ghoneim, Mohamed T.

    2014-07-01

    Neuromorphic computer will need folded architectural form factor to match brain cortex\\'s folded pattern for ultra-compact design. In this work, we show a state-of-the-art CMOS compatible pragmatic fabrication approach of building structurally foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench-protect-release-recycle process transform the silicon wafer with devices into a flexible and semi-transparent silicon fabric while recycling the remaining wafer for further use. This process unconditionally offers the ultra-large-scale-integration opportunity-increasingly critical for ultra-compact memory.

  9. A Review of Current Neuromorphic Approaches for Vision, Auditory, and Olfactory Sensors.

    Science.gov (United States)

    Vanarse, Anup; Osseiran, Adam; Rassau, Alexander

    2016-01-01

    Conventional vision, auditory, and olfactory sensors generate large volumes of redundant data and as a result tend to consume excessive power. To address these shortcomings, neuromorphic sensors have been developed. These sensors mimic the neuro-biological architecture of sensory organs using aVLSI (analog Very Large Scale Integration) and generate asynchronous spiking output that represents sensing information in ways that are similar to neural signals. This allows for much lower power consumption due to an ability to extract useful sensory information from sparse captured data. The foundation for research in neuromorphic sensors was laid more than two decades ago, but recent developments in understanding of biological sensing and advanced electronics, have stimulated research on sophisticated neuromorphic sensors that provide numerous advantages over conventional sensors. In this paper, we review the current state-of-the-art in neuromorphic implementation of vision, auditory, and olfactory sensors and identify key contributions across these fields. Bringing together these key contributions we suggest a future research direction for further development of the neuromorphic sensing field.

  10. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  11. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  12. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  13. Neuromorphic VLSI vision system for real-time texture segregation.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2008-10-01

    The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

  14. Neuromorphic atomic switch networks.

    Directory of Open Access Journals (Sweden)

    Audrius V Avizienis

    Full Text Available Efforts to emulate the formidable information processing capabilities of the brain through neuromorphic engineering have been bolstered by recent progress in the fabrication of nonlinear, nanoscale circuit elements that exhibit synapse-like operational characteristics. However, conventional fabrication techniques are unable to efficiently generate structures with the highly complex interconnectivity found in biological neuronal networks. Here we demonstrate the physical realization of a self-assembled neuromorphic device which implements basic concepts of systems neuroscience through a hardware-based platform comprised of over a billion interconnected atomic-switch inorganic synapses embedded in a complex network of silver nanowires. Observations of network activation and passive harmonic generation demonstrate a collective response to input stimulus in agreement with recent theoretical predictions. Further, emergent behaviors unique to the complex network of atomic switches and akin to brain function are observed, namely spatially distributed memory, recurrent dynamics and the activation of feedforward subnetworks. These devices display the functional characteristics required for implementing unconventional, biologically and neurally inspired computational methodologies in a synthetic experimental system.

  15. Neuromorphic UAS Collision Avoidance Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Using biologically-inspired neuromorphic optic flow algorithms is a novel approach in collision avoidance for UAS. Traditional computer vision algorithms rely on...

  16. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  17. Energy-Efficient Neuromorphic Classifiers.

    Science.gov (United States)

    Martí, Daniel; Rigotti, Mattia; Seok, Mingoo; Fusi, Stefano

    2016-10-01

    Neuromorphic engineering combines the architectural and computational principles of systems neuroscience with semiconductor electronics, with the aim of building efficient and compact devices that mimic the synaptic and neural machinery of the brain. The energy consumptions promised by neuromorphic engineering are extremely low, comparable to those of the nervous system. Until now, however, the neuromorphic approach has been restricted to relatively simple circuits and specialized functions, thereby obfuscating a direct comparison of their energy consumption to that used by conventional von Neumann digital machines solving real-world tasks. Here we show that a recent technology developed by IBM can be leveraged to realize neuromorphic circuits that operate as classifiers of complex real-world stimuli. Specifically, we provide a set of general prescriptions to enable the practical implementation of neural architectures that compete with state-of-the-art classifiers. We also show that the energy consumption of these architectures, realized on the IBM chip, is typically two or more orders of magnitude lower than that of conventional digital machines implementing classifiers with comparable performance. Moreover, the spike-based dynamics display a trade-off between integration time and accuracy, which naturally translates into algorithms that can be flexibly deployed for either fast and approximate classifications, or more accurate classifications at the mere expense of longer running times and higher energy costs. This work finally proves that the neuromorphic approach can be efficiently used in real-world applications and has significant advantages over conventional digital devices when energy consumption is considered.

  18. Neuromorphic meets neuromechanics, part I: the methodology and implementation

    Science.gov (United States)

    Niu, Chuanxin M.; Jalaleddini, Kian; Sohn, Won Joon; Rocamora, John; Sanger, Terence D.; Valero-Cuevas, Francisco J.

    2017-04-01

    Objective: One goal of neuromorphic engineering is to create ‘realistic’ robotic systems that interact with the physical world by adopting neuromechanical principles from biology. Critical to this is the methodology to implement the spinal circuitry responsible for the behavior of afferented muscles. At its core, muscle afferentation is the closed-loop behavior arising from the interactions among populations of muscle spindle afferents, alpha and gamma motoneurons, and muscle fibers to enable useful behaviors. Approach. We used programmable very- large-scale-circuit (VLSI) hardware to implement simple models of spiking neurons, skeletal muscles, muscle spindle proprioceptors, alpha-motoneuron recruitment, gamma motoneuron control of spindle sensitivity, and the monosynaptic circuitry connecting them. This multi-scale system of populations of spiking neurons emulated the physiological properties of a pair of antagonistic afferented mammalian muscles (each simulated by 1024 alpha- and gamma-motoneurones) acting on a joint via long tendons. Main results. This integrated system was able to maintain a joint angle, and reproduced stretch reflex responses even when driving the nonlinear biomechanics of an actual cadaveric finger. Moreover, this system allowed us to explore numerous values and combinations of gamma-static and gamma-dynamic gains when driving a robotic finger, some of which replicated some human pathological conditions. Lastly, we explored the behavioral consequences of adopting three alternative models of isometric muscle force production. We found that the dynamic responses to rate-coded spike trains produce force ramps that can be very sensitive to tendon elasticity, especially at high force output. Significance. Our methodology produced, to our knowledge, the first example of an autonomous, multi-scale, neuromorphic, neuromechanical system capable of creating realistic reflex behavior in cadaveric fingers. This research platform allows us to explore

  19. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  20. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  1. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  2. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  3. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  4. Neuromorphic opto-electronic integrated circuits for optical signal processing

    Science.gov (United States)

    Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

    2014-08-01

    The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

  5. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  6. Closed-loop neuromorphic benchmarks

    CSIR Research Space (South Africa)

    Stewart

    2015-11-01

    Full Text Available Benchmarks   Terrence C. Stewart 1* , Travis DeWolf 1 , Ashley Kleinhans 2 , Chris Eliasmith 1   1 University of Waterloo, Canada, 2 Council for Scientific and Industrial Research, South Africa   Submitted to Journal:   Frontiers in Neuroscience   Specialty... the study was exempt from ethical approval procedures.) Did the study presented in the manuscript involve human or animal subjects: No I v i w 1Closed-loop Neuromorphic Benchmarks Terrence C. Stewart 1,∗, Travis DeWolf 1, Ashley Kleinhans 2 and Chris...

  7. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  8. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  9. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  10. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  11. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  12. Parallel Evolutionary Optimization for Neuromorphic Network Training

    Energy Technology Data Exchange (ETDEWEB)

    Schuman, Catherine D [ORNL; Disney, Adam [University of Tennessee (UT); Singh, Susheela [North Carolina State University (NCSU), Raleigh; Bruer, Grant [University of Tennessee (UT); Mitchell, John Parker [University of Tennessee (UT); Klibisz, Aleksander [University of Tennessee (UT); Plank, James [University of Tennessee (UT)

    2016-01-01

    One of the key impediments to the success of current neuromorphic computing architectures is the issue of how best to program them. Evolutionary optimization (EO) is one promising programming technique; in particular, its wide applicability makes it especially attractive for neuromorphic architectures, which can have many different characteristics. In this paper, we explore different facets of EO on a spiking neuromorphic computing model called DANNA. We focus on the performance of EO in the design of our DANNA simulator, and on how to structure EO on both multicore and massively parallel computing systems. We evaluate how our parallel methods impact the performance of EO on Titan, the U.S.'s largest open science supercomputer, and BOB, a Beowulf-style cluster of Raspberry Pi's. We also focus on how to improve the EO by evaluating commonality in higher performing neural networks, and present the result of a study that evaluates the EO performed by Titan.

  13. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  14. Serendipitous offline learning in a neuromorphic robot

    CSIR Research Space (South Africa)

    Stewart, TC

    2016-02-01

    Full Text Available We demonstrate a hybrid neuromorphic learning paradigm that learns complex senso-rimotor mappings based on a small set of hard-coded reflex behaviors. A mobile robot is first controlled by a basic set of reflexive hand-designed behaviors. All sensor...

  15. Implementing robust neuromodulation in neuromorphic circuits

    OpenAIRE

    Castaños, Fernando; Franci, Alessio

    2016-01-01

    We introduce a methodology to implement the physiological transition {between distinct neuronal spiking modes} in electronic circuits composed of resistors, capacitors and transistors. The result is a simple neuromorphic device organized by the same geometry {and exhibiting the same input--output properties as} high-dimensional electrophysiological neuron models. {Preliminary} experimental results highlight the robustness of the approach in real-world applications.

  16. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  17. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  18. Toward exascale computing through neuromorphic approaches.

    Energy Technology Data Exchange (ETDEWEB)

    James, Conrad D.

    2010-09-01

    While individual neurons function at relatively low firing rates, naturally-occurring nervous systems not only surpass manmade systems in computing power, but accomplish this feat using relatively little energy. It is asserted that the next major breakthrough in computing power will be achieved through application of neuromorphic approaches that mimic the mechanisms by which neural systems integrate and store massive quantities of data for real-time decision making. The proposed LDRD provides a conceptual foundation for SNL to make unique advances toward exascale computing. First, a team consisting of experts from the HPC, MESA, cognitive and biological sciences and nanotechnology domains will be coordinated to conduct an exercise with the outcome being a concept for applying neuromorphic computing to achieve exascale computing. It is anticipated that this concept will involve innovative extension and integration of SNL capabilities in MicroFab, material sciences, high-performance computing, and modeling and simulation of neural processes/systems.

  19. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  20. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  1. Dynamic Adaptive Neural Network Arrays: A Neuromorphic Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

    2015-01-01

    Dynamic Adaptive Neural Network Array (DANNA) is a neuromorphic hardware implementation. It differs from most other neuromorphic projects in that it allows for programmability of structure, and it is trained or designed using evolutionary optimization. This paper describes the DANNA structure, how DANNA is trained using evolutionary optimization, and an application of DANNA to a very simple classification task.

  2. Modeling alternation to synchrony with inhibitory coupling: a neuromorphic VLSI approach.

    Science.gov (United States)

    Cymbalyuk, G S; Patel, G N; Calabrese, R L; DeWeerth, S P; Cohen, A H

    2000-10-01

    We developed an analog very large-scale integrated system of two mutually inhibitory silicon neurons that display several different stable oscillations. For example, oscillations can be synchronous with weak inhibitory coupling and alternating with relatively strong inhibitory coupling. All oscillations observed experimentally were predicted by bifurcation analysis of a corresponding mathematical model. The synchronous oscillations do not require special synaptic properties and are apparently robust enough to survive the variability and constraints inherent in this physical system. In biological experiments with oscillatory neuronal networks, blockade of inhibitory synaptic coupling can sometimes lead to synchronous oscillations. An example of this phenomenon is the transition from alternating to synchronous bursting in the swimming central pattern generator of lamprey when synaptic inhibition is blocked by strychnine. Our results suggest a simple explanation for the observed oscillatory transitions in the lamprey central pattern generator network: that inhibitory connectivity alone is sufficient to produce the observed transition.

  3. Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

    Science.gov (United States)

    2010-10-01

    Horiuchi, 2010), (d) we tested and published our initial work on using synaptic conductances to estimate sound azimuth based on interaural intensity...the interaural-level difference used in horizontal sound localization. In late 2008, we successfully demonstrated the use of our conductance-based...34 Binaural Spectral Cues for Ultrasonic Localization," Proc. International Symposium on Circuits and Systems, pp. 2110 - 2113, 2008 (DOI:10.1109/ISCAS

  4. Neuromorphic cognitive systems a learning and memory centered approach

    CERN Document Server

    Yu, Qiang; Hu, Jun; Tan Chen, Kay

    2017-01-01

    This book presents neuromorphic cognitive systems from a learning and memory-centered perspective. It illustrates how to build a system network of neurons to perform spike-based information processing, computing, and high-level cognitive tasks. It is beneficial to a wide spectrum of readers, including undergraduate and postgraduate students and researchers who are interested in neuromorphic computing and neuromorphic engineering, as well as engineers and professionals in industry who are involved in the design and applications of neuromorphic cognitive systems, neuromorphic sensors and processors, and cognitive robotics. The book formulates a systematic framework, from the basic mathematical and computational methods in spike-based neural encoding, learning in both single and multi-layered networks, to a near cognitive level composed of memory and cognition. Since the mechanisms for integrating spiking neurons integrate to formulate cognitive functions as in the brain are little understood, studies of neuromo...

  5. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  6. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  7. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  8. An Application Development Platform for Neuromorphic Computing

    Energy Technology Data Exchange (ETDEWEB)

    Dean, Mark [University of Tennessee (UT); Chan, Jason [University of Tennessee (UT); Daffron, Christopher [University of Tennessee (UT); Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT); Rose, Garrett [University of Tennessee (UT); Plank, James [University of Tennessee (UT); Birdwell, John Douglas [University of Tennessee (UT); Schuman, Catherine D [ORNL

    2016-01-01

    Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic computing systems developed as a hardware based approach to the implementation of neural networks. They feature highly adaptive and programmable structural elements, which model arti cial neural networks with spiking behavior. We design them to solve problems using evolutionary optimization. In this paper, we highlight the current hardware and software implementations of DANNA, including their features, functionalities and performance. We then describe the development of an Application Development Platform (ADP) to support efficient application implementation and testing of DANNA based solutions. We conclude with future directions.

  9. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  10. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  11. Finding a roadmap to achieve large neuromorphic hardware systems.

    Science.gov (United States)

    Hasler, Jennifer; Marr, Bo

    2013-01-01

    Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

  12. An Evolutionary Optimization Framework for Neural Networks and Neuromorphic Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Schuman, Catherine D [ORNL; Plank, James [University of Tennessee (UT); Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

    2016-01-01

    As new neural network and neuromorphic architectures are being developed, new training methods that operate within the constraints of the new architectures are required. Evolutionary optimization (EO) is a convenient training method for new architectures. In this work, we review a spiking neural network architecture and a neuromorphic architecture, and we describe an EO training framework for these architectures. We present the results of this training framework on four classification data sets and compare those results to other neural network and neuromorphic implementations. We also discuss how this EO framework may be extended to other architectures.

  13. Serendipitous Offline Learning in a Neuromorphic Robot.

    Science.gov (United States)

    Stewart, Terrence C; Kleinhans, Ashley; Mundy, Andrew; Conradt, Jörg

    2016-01-01

    We demonstrate a hybrid neuromorphic learning paradigm that learns complex sensorimotor mappings based on a small set of hard-coded reflex behaviors. A mobile robot is first controlled by a basic set of reflexive hand-designed behaviors. All sensor data is provided via a spike-based silicon retina camera (eDVS), and all control is implemented via spiking neurons simulated on neuromorphic hardware (SpiNNaker). Given this control system, the robot is capable of simple obstacle avoidance and random exploration. To train the robot to perform more complex tasks, we observe the robot and find instances where the robot accidentally performs the desired action. Data recorded from the robot during these times is then used to update the neural control system, increasing the likelihood of the robot performing that task in the future, given a similar sensor state. As an example application of this general-purpose method of training, we demonstrate the robot learning to respond to novel sensory stimuli (a mirror) by turning right if it is present at an intersection, and otherwise turning left. In general, this system can learn arbitrary relations between sensory input and motor behavior.

  14. A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

    Science.gov (United States)

    Qiao, Ning; Mostafa, Hesham; Corradi, Federico; Osswald, Marc; Stefanini, Fabio; Sumislawska, Dora; Indiveri, Giacomo

    2015-01-01

    Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

  15. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  16. Superconducting optoelectronic circuits for neuromorphic computing

    CERN Document Server

    Shainline, Jeffrey M; Mirin, Richard P; Nam, Sae Woo

    2016-01-01

    We propose a hybrid semiconductor-superconductor hardware platform for the implementation of neural networks and large-scale neuromorphic computing. The platform combines semiconducting few-photon light-emitting diodes with superconducting-nanowire single-photon detectors to behave as spiking neurons. These processing units are connected via a network of optical waveguides, and variable weights of connection can be implemented using several approaches. The use of light as a signaling mechanism overcomes the requirement for time-multiplexing that has limited the event rates of purely electronic platforms. The proposed processing units can operate at $20$ MHz with fully asynchronous activity, light-speed-limited latency, and power densities on the order of 1 mW/cm$^2$ for neurons with 700 connections operating at full speed at 2 K. The processing units achieve an energy efficiency of $\\approx 20$ aJ per synapse event. By leveraging multilayer photonics with low-temperature-deposited waveguides and superconducto...

  17. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  18. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  19. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  20. Finding a Roadmap to achieve Large Neuromorphic Hardware Systems

    Directory of Open Access Journals (Sweden)

    Jennifer eHasler

    2013-09-01

    Full Text Available Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

  1. A neuromorphic model of spatial lookahead planning.

    Science.gov (United States)

    Ivey, Richard; Bullock, Daniel; Grossberg, Stephen

    2011-04-01

    In order to create spatial plans in a complex and changing world, organisms need to rapidly adapt to novel configurations of obstacles that impede simple routes to goal acquisition. Some animals can mentally create successful multistep spatial plans in new visuo-spatial layouts that preclude direct, one-segment routes to goal acquisition. Lookahead multistep plans can, moreover, be fully developed before an animal executes any step in the plan. What neural computations suffice to yield preparatory multistep lookahead plans during spatial cognition of an obstructed two-dimensional scene? To address this question, we introduce a novel neuromorphic system for spatial lookahead planning in which a feasible sequence of actions is prepared before movement begins. The proposed system combines neurobiologically plausible mechanisms of recurrent shunting competitive networks, visuo-spatial diffusion, and inhibition-of-return. These processes iteratively prepare a multistep trajectory to the desired goal state in the presence of obstacles. The planned trajectory can be stored using a primacy gradient in a sequential working memory and enacted by a competitive queuing process. The proposed planning system is compared with prior planning models. Simulation results demonstrate system robustness to environmental variations. Notably, the model copes with many configurations of obstacles that lead other visuo-spatial planning models into selecting undesirable or infeasible routes. Our proposal is inspired by mechanisms of spatial attention and planning in primates. Accordingly, our simulation results are compared with neurophysiological and behavioral findings from relevant studies of spatial lookahead behavior.

  2. Neuromorphic Configurable Architecture for Robust Motion Estimation

    Directory of Open Access Journals (Sweden)

    Guillermo Botella

    2008-01-01

    Full Text Available The robustness of the human visual system recovering motion estimation in almost any visual situation is enviable, performing enormous calculation tasks continuously, robustly, efficiently, and effortlessly. There is obviously a great deal we can learn from our own visual system. Currently, there are several optical flow algorithms, although none of them deals efficiently with noise, illumination changes, second-order motion, occlusions, and so on. The main contribution of this work is the efficient implementation of a biologically inspired motion algorithm that borrows nature templates as inspiration in the design of architectures and makes use of a specific model of human visual motion perception: Multichannel Gradient Model (McGM. This novel customizable architecture of a neuromorphic robust optical flow can be constructed with FPGA or ASIC device using properties of the cortical motion pathway, constituting a useful framework for building future complex bioinspired systems running in real time with high computational complexity. This work includes the resource usage and performance data, and the comparison with actual systems. This hardware has many application fields like object recognition, navigation, or tracking in difficult environments due to its bioinspired and robustness properties.

  3. Superconducting Optoelectronic Circuits for Neuromorphic Computing

    Science.gov (United States)

    Shainline, Jeffrey M.; Buckley, Sonia M.; Mirin, Richard P.; Nam, Sae Woo

    2017-03-01

    Neural networks have proven effective for solving many difficult computational problems, yet implementing complex neural networks in software is computationally expensive. To explore the limits of information processing, it is necessary to implement new hardware platforms with large numbers of neurons, each with a large number of connections to other neurons. Here we propose a hybrid semiconductor-superconductor hardware platform for the implementation of neural networks and large-scale neuromorphic computing. The platform combines semiconducting few-photon light-emitting diodes with superconducting-nanowire single-photon detectors to behave as spiking neurons. These processing units are connected via a network of optical waveguides, and variable weights of connection can be implemented using several approaches. The use of light as a signaling mechanism overcomes fanout and parasitic constraints on electrical signals while simultaneously introducing physical degrees of freedom which can be employed for computation. The use of supercurrents achieves the low power density (1 mW /cm2 at 20-MHz firing rate) necessary to scale to systems with enormous entropy. Estimates comparing the proposed hardware platform to a human brain show that with the same number of neurons (1 011) and 700 independent connections per neuron, the hardware presented here may achieve an order of magnitude improvement in synaptic events per second per watt.

  4. Fast neuromorphic sound localization for binaural hearing aids.

    Science.gov (United States)

    Park, Paul K J; Ryu, Hyunsurk; Lee, Jun Haeng; Shin, Chang-Woo; Lee, Kyoo Bin; Woo, Jooyeon; Kim, Jun-Seok; Kang, Byung Chang; Liu, Shih-Chii; Delbruck, Tobi

    2013-01-01

    We report on the neuromorphic sound localization circuit which can enhance the perceptual sensation in a hearing aid system. All elements are simple leaky integrate-and-fire neuron circuits with different parameters optimized to suppress the impacts of synaptic circuit noises. The detection range and resolution of the proposed neuromorphic circuit are 500 us and 5 us, respectively. Our results show that, the proposed technique can localize a sound pulse with extremely narrow duration (∼ 1 ms) resulting in real-time response.

  5. A neuromorphic system for video object recognition.

    Science.gov (United States)

    Khosla, Deepak; Chen, Yang; Kim, Kyungnam

    2014-01-01

    Automated video object recognition is a topic of emerging importance in both defense and civilian applications. This work describes an accurate and low-power neuromorphic architecture and system for real-time automated video object recognition. Our system, Neuormorphic Visual Understanding of Scenes (NEOVUS), is inspired by computational neuroscience models of feed-forward object detection and classification pipelines for processing visual data. The NEOVUS architecture is inspired by the ventral (what) and dorsal (where) streams of the mammalian visual pathway and integrates retinal processing, object detection based on form and motion modeling, and object classification based on convolutional neural networks. The object recognition performance and energy use of the NEOVUS was evaluated by the Defense Advanced Research Projects Agency (DARPA) under the Neovision2 program using three urban area video datasets collected from a mix of stationary and moving platforms. These datasets are challenging and include a large number of objects of different types in cluttered scenes, with varying illumination and occlusion conditions. In a systematic evaluation of five different teams by DARPA on these datasets, the NEOVUS demonstrated the best performance with high object recognition accuracy and the lowest energy consumption. Its energy use was three orders of magnitude lower than two independent state of the art baseline computer vision systems. The dynamic power requirement for the complete system mapped to commercial off-the-shelf (COTS) hardware that includes a 5.6 Megapixel color camera processed by object detection and classification algorithms at 30 frames per second was measured at 21.7 Watts (W), for an effective energy consumption of 5.45 nanoJoules (nJ) per bit of incoming video. These unprecedented results show that the NEOVUS has the potential to revolutionize automated video object recognition toward enabling practical low-power and mobile video processing

  6. A Neuromorphic System for Video Object Recognition

    Directory of Open Access Journals (Sweden)

    Deepak eKhosla

    2014-11-01

    Full Text Available Automated video object recognition is a topic of emerging importance in both defense and civilian applications. This work describes an accurate and low-power neuromorphic architecture and system for real-time automated video object recognition. Our system, Neuormorphic Visual Understanding of Scenes (NEOVUS, is inspired by recent findings in computational neuroscience on feed-forward object detection and classification pipelines for processing and extracting relevant information from visual data. The NEOVUS architecture is inspired by the ventral (what and dorsal (where streams of the mammalian visual pathway and combines retinal processing, form-based and motion-based object detection, and convolutional neural nets based object classification. Our system was evaluated by the Defense Advanced Research Projects Agency (DARPA under the NEOVISION2 program on a variety of urban area video datasets collected from both stationary and moving platforms. The datasets are challenging as they include a large number of targets in cluttered scenes with varying illumination and occlusion conditions. The NEOVUS system was also mapped to commercially available off-the-shelf hardware. The dynamic power requirement for the system that includes a 5.6Mpixel retinal camera processed by object detection and classification algorithms at 30 frames per second was measured at 21.7 Watts (W, for an effective energy consumption of 5.4 nanoJoules (nJ per bit of incoming video. In a systematic evaluation of five different teams by DARPA on three aerial datasets, the NEOVUS demonstrated the best performance with the highest recognition accuracy and at least three orders of magnitude lower energy consumption than two independent state of the art computer vision systems. These unprecedented results show that the NEOVUS has the potential to revolutionize automated video object recognition towards enabling practical low-power and mobile video processing applications.

  7. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  8. Regenerative memory in time-delayed neuromorphic photonic systems

    CERN Document Server

    Romeira, B; Figueiredo, José M L; Barland, S; Javaloyes, J

    2015-01-01

    We investigate a regenerative memory based upon a time-delayed neuromorphic photonic oscillator and discuss the link with temporal localized structures. Our experimental implementation is based upon a optoelectronic system composed of a nanoscale nonlinear resonant tunneling diode coupled to a laser that we link to the paradigm of neuronal activity, the FitzHugh-Nagumo model with delayed feedback.

  9. Benchmarking neuromorphic vision: lessons learnt from computer vision.

    Science.gov (United States)

    Tan, Cheston; Lallee, Stephane; Orchard, Garrick

    2015-01-01

    Neuromorphic Vision sensors have improved greatly since the first silicon retina was presented almost three decades ago. They have recently matured to the point where they are commercially available and can be operated by laymen. However, despite improved availability of sensors, there remains a lack of good datasets, while algorithms for processing spike-based visual data are still in their infancy. On the other hand, frame-based computer vision algorithms are far more mature, thanks in part to widely accepted datasets which allow direct comparison between algorithms and encourage competition. We are presented with a unique opportunity to shape the development of Neuromorphic Vision benchmarks and challenges by leveraging what has been learnt from the use of datasets in frame-based computer vision. Taking advantage of this opportunity, in this paper we review the role that benchmarks and challenges have played in the advancement of frame-based computer vision, and suggest guidelines for the creation of Neuromorphic Vision benchmarks and challenges. We also discuss the unique challenges faced when benchmarking Neuromorphic Vision algorithms, particularly when attempting to provide direct comparison with frame-based computer vision.

  10. Recent Advances on Neuromorphic Systems Using Phase-Change Materials

    Science.gov (United States)

    Wang, Lei; Lu, Shu-Ren; Wen, Jing

    2017-05-01

    Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

  11. All-memristive neuromorphic computing with level-tuned neurons.

    Science.gov (United States)

    Pantazi, Angeliki; Woźniak, Stanisław; Tuma, Tomas; Eleftheriou, Evangelos

    2016-09-02

    In the new era of cognitive computing, systems will be able to learn and interact with the environment in ways that will drastically enhance the capabilities of current processors, especially in extracting knowledge from vast amount of data obtained from many sources. Brain-inspired neuromorphic computing systems increasingly attract research interest as an alternative to the classical von Neumann processor architecture, mainly because of the coexistence of memory and processing units. In these systems, the basic components are neurons interconnected by synapses. The neurons, based on their nonlinear dynamics, generate spikes that provide the main communication mechanism. The computational tasks are distributed across the neural network, where synapses implement both the memory and the computational units, by means of learning mechanisms such as spike-timing-dependent plasticity. In this work, we present an all-memristive neuromorphic architecture comprising neurons and synapses realized by using the physical properties and state dynamics of phase-change memristors. The architecture employs a novel concept of interconnecting the neurons in the same layer, resulting in level-tuned neuronal characteristics that preferentially process input information. We demonstrate the proposed architecture in the tasks of unsupervised learning and detection of multiple temporal correlations in parallel input streams. The efficiency of the neuromorphic architecture along with the homogenous neuro-synaptic dynamics implemented with nanoscale phase-change memristors represent a significant step towards the development of ultrahigh-density neuromorphic co-processors.

  12. All-memristive neuromorphic computing with level-tuned neurons

    Science.gov (United States)

    Pantazi, Angeliki; Woźniak, Stanisław; Tuma, Tomas; Eleftheriou, Evangelos

    2016-09-01

    In the new era of cognitive computing, systems will be able to learn and interact with the environment in ways that will drastically enhance the capabilities of current processors, especially in extracting knowledge from vast amount of data obtained from many sources. Brain-inspired neuromorphic computing systems increasingly attract research interest as an alternative to the classical von Neumann processor architecture, mainly because of the coexistence of memory and processing units. In these systems, the basic components are neurons interconnected by synapses. The neurons, based on their nonlinear dynamics, generate spikes that provide the main communication mechanism. The computational tasks are distributed across the neural network, where synapses implement both the memory and the computational units, by means of learning mechanisms such as spike-timing-dependent plasticity. In this work, we present an all-memristive neuromorphic architecture comprising neurons and synapses realized by using the physical properties and state dynamics of phase-change memristors. The architecture employs a novel concept of interconnecting the neurons in the same layer, resulting in level-tuned neuronal characteristics that preferentially process input information. We demonstrate the proposed architecture in the tasks of unsupervised learning and detection of multiple temporal correlations in parallel input streams. The efficiency of the neuromorphic architecture along with the homogenous neuro-synaptic dynamics implemented with nanoscale phase-change memristors represent a significant step towards the development of ultrahigh-density neuromorphic co-processors.

  13. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  14. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  15. A Re-configurable On-line Learning Spiking Neuromorphic Processor comprising 256 neurons and 128K synapses

    Directory of Open Access Journals (Sweden)

    Ning eQiao

    2015-04-01

    Full Text Available Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm 2 , and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

  16. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  17. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  18. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Directory of Open Access Journals (Sweden)

    McEwan Alistair

    2003-01-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  19. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  20. Neuromorphic elements and systems as the basis for the physical implementation of artificial intelligence technologies

    Science.gov (United States)

    Demin, V. A.; Emelyanov, A. V.; Lapkin, D. A.; Erokhin, V. V.; Kashkarov, P. K.; Kovalchuk, M. V.

    2016-11-01

    The instrumental realization of neuromorphic systems may form the basis of a radically new social and economic setup, redistributing roles between humans and complex technical aggregates. The basic elements of any neuromorphic system are neurons and synapses. New memristive elements based on both organic (polymer) and inorganic materials have been formed, and the possibilities of instrumental implementation of very simple neuromorphic systems with different architectures on the basis of these elements have been demonstrated.

  1. FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications

    Science.gov (United States)

    Liu, Ming; Yu, Hua; Wang, Wei

    In this paper, a novel field programmable analog arrays (FPAA) architecture, namely, NueroFPAA, is introduced to utilize nanodevices to build a programmable neuromorphic system. By using nanodevices as programmable components, the proposed FPAA can achieve high-density and low-power operations for neuromorphic applications. The routing and function blocks of the FPAA are specifically designed so that this proposed architecture can support large-scale neuromorphic design as well as various analog circuitries.

  2. Qualitative Functional Decomposition Analysis of Evolved Neuromorphic Flight Controllers

    Directory of Open Access Journals (Sweden)

    Sanjay K. Boddhu

    2012-01-01

    Full Text Available In the previous work, it was demonstrated that one can effectively employ CTRNN-EH (a neuromorphic variant of EH method methodology to evolve neuromorphic flight controllers for a flapping wing robot. This paper describes a novel frequency grouping-based analysis technique, developed to qualitatively decompose the evolved controllers into explainable functional control blocks. A summary of the previous work related to evolving flight controllers for two categories of the controller types, called autonomous and nonautonomous controllers, is provided, and the applicability of the newly developed decomposition analysis for both controller categories is demonstrated. Further, the paper concludes with appropriate discussion of ongoing work and implications for possible future work related to employing the CTRNN-EH methodology and the decomposition analysis techniques presented in this paper.

  3. Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Andreas Stöckel

    2017-08-01

    Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

  4. Six networks on a universal neuromorphic computing substrate

    Directory of Open Access Journals (Sweden)

    Thomas ePfeil

    2013-02-01

    Full Text Available In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality.

  5. Towards neuromorphic electronics: Memristors on foldable silicon fabric

    KAUST Repository

    Ghoneim, Mohamed T.

    2014-11-01

    The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex\\'s folded pattern for ultra-compact design.

  6. 3D CMOL Crossnet for Neuromorphic Network Applications

    Science.gov (United States)

    Ryan, Kevin; Tanachutiwat, Sansiri; Wang, Wei

    In this work, a novel 3D CMOL crossnet structure is introduced by combining two leading technological concepts for future nanoelectronic neuromorphic networks: CMOL crossnet and 3D integration. By implementing CMOL crossnet into the third dimension, the proposed 3D CMOL crossnet not only maintains the high-speed and high defect-tolerant properties of the CMOS-nano hybrid CMOL hardware system, but also provides efficient fabrication and assembly processes with a much higher density than the original CMOL crossnet. Furthermore, this study focuses on the development of multivalue synapses and efficient communication methods between CMOS and nanodevices. Preliminary results demonstrate that the structure can utilize the advantages of high performance synapses and stable analog CMOS somas in three dimensions. Therefore, the proposed 3D CMOL crossnet structure has a huge potential to become an efficient 3D hardware platform to build neuromorphic networks that are scalable to biological levels.

  7. Thermal memristor and neuromorphic networks for manipulating heat flow

    Science.gov (United States)

    Ben-Abdallah, Philippe

    2017-06-01

    A memristor is one of four fundamental two-terminal solid elements in electronics. In addition with the resistor, the capacitor and the inductor, this passive element relates the electric charges to current in solid state elements. Here we report the existence of a thermal analog for this element made with metal-insulator transition materials. We demonstrate that these memristive systems can be used to create thermal neurons opening so the way to neuromorphic networks for smart thermal management and information treatment.

  8. A neuromorphic network for generic multivariate data classification.

    Science.gov (United States)

    Schmuker, Michael; Pfeil, Thomas; Nawrot, Martin Paul

    2014-02-11

    Computational neuroscience has uncovered a number of computational principles used by nervous systems. At the same time, neuromorphic hardware has matured to a state where fast silicon implementations of complex neural networks have become feasible. En route to future technical applications of neuromorphic computing the current challenge lies in the identification and implementation of functional brain algorithms. Taking inspiration from the olfactory system of insects, we constructed a spiking neural network for the classification of multivariate data, a common problem in signal and data analysis. In this model, real-valued multivariate data are converted into spike trains using "virtual receptors" (VRs). Their output is processed by lateral inhibition and drives a winner-take-all circuit that supports supervised learning. VRs are conveniently implemented in software, whereas the lateral inhibition and classification stages run on accelerated neuromorphic hardware. When trained and tested on real-world datasets, we find that the classification performance is on par with a naïve Bayes classifier. An analysis of the network dynamics shows that stable decisions in output neuron populations are reached within less than 100 ms of biological time, matching the time-to-decision reported for the insect nervous system. Through leveraging a population code, the network tolerates the variability of neuronal transfer functions and trial-to-trial variation that is inevitably present on the hardware system. Our work provides a proof of principle for the successful implementation of a functional spiking neural network on a configurable neuromorphic hardware system that can readily be applied to real-world computing problems.

  9. Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

    OpenAIRE

    Wu, Xinyu; Saxena, Vishal; Zhu, Kehan

    2015-01-01

    A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable...

  10. Strategies of Clausal Possession

    Science.gov (United States)

    Langacker, Ronald W.

    2003-01-01

    Across languages, clauses expressing possession, location, and existence exhibit many similarities. To capture their evident affinity, it is often claimed that possessives derive--synclironically or diaclironically--from expressions of location/existence. This localist account obscures a basic contrast between two broad classes of possessive…

  11. Convolutional networks for fast, energy-efficient neuromorphic computing.

    Science.gov (United States)

    Esser, Steven K; Merolla, Paul A; Arthur, John V; Cassidy, Andrew S; Appuswamy, Rathinakumar; Andreopoulos, Alexander; Berg, David J; McKinstry, Jeffrey L; Melano, Timothy; Barch, Davis R; di Nolfo, Carmelo; Datta, Pallab; Amir, Arnon; Taba, Brian; Flickner, Myron D; Modha, Dharmendra S

    2016-10-11

    Deep networks are now able to achieve human-level performance on a broad spectrum of recognition tasks. Independently, neuromorphic computing has now demonstrated unprecedented energy-efficiency through a new chip architecture based on spiking neurons, low precision synapses, and a scalable communication network. Here, we demonstrate that neuromorphic computing, despite its novel architectural primitives, can implement deep convolution networks that (i) approach state-of-the-art classification accuracy across eight standard datasets encompassing vision and speech, (ii) perform inference while preserving the hardware's underlying energy-efficiency and high throughput, running on the aforementioned datasets at between 1,200 and 2,600 frames/s and using between 25 and 275 mW (effectively >6,000 frames/s per Watt), and (iii) can be specified and trained using backpropagation with the same ease-of-use as contemporary deep learning. This approach allows the algorithmic power of deep learning to be merged with the efficiency of neuromorphic processors, bringing the promise of embedded, intelligent, brain-inspired computing one step closer.

  12. An improved cortex-like neuromorphic system for target recognitions

    Science.gov (United States)

    Tsitiridis, Aristeidis; Yuen, Peter; Hong, Kan; Chen, Tong; Ibrahim, Izzati; Jackman, James; James, David; Richardson, Mark

    2010-10-01

    This paper reports on the enhancement of biologically-inspired machine vision through a rotation invariance mechanism. Research over the years has suggested that rotation invariance is one of the fundamental generic elements of object constancy, a known generic visual ability of the human brain. Cortex-like vision unlike conventional pixel based machine vision is achieved by mimicking neuromorphic mechanisms of the primates' brain. In this preliminary study, rotation invariance is implemented through histograms from Gabor features of an object. The performance of rotation invariance in the neuromorphic algorithm is assessed by the classification accuracies of a test data set which consists of image objects in five different orientations. It is found that a much more consistent classification result over these five different oriented data sets has been achieved by the integrated rotation invariance neuromorphic algorithm compared to the one without. In addition, the issue of varying aspect ratios of input images to these models is also addressed, in an attempt to create a robust algorithm against a wider variability of input data. The extension of the present achievement is to improve the recognition accuracies while incorporating it to a series of different real-world scenarios which would challenge the approach accordingly.

  13. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  14. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  15. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  16. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  17. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  18. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  19. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  20. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  1. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  2. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  3. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  4. Neuromorphic Computing – From Materials Research to Systems Architecture Roundtable

    Energy Technology Data Exchange (ETDEWEB)

    Schuller, Ivan K. [Univ. of California, San Diego, CA (United States); Stevens, Rick [Argonne National Lab. (ANL), Argonne, IL (United States); Univ. of Chicago, IL (United States); Pino, Robinson [Dept. of Energy (DOE) Office of Science, Washington, DC (United States); Pechan, Michael [Dept. of Energy (DOE) Office of Science, Washington, DC (United States)

    2015-10-29

    Computation in its many forms is the engine that fuels our modern civilization. Modern computation—based on the von Neumann architecture—has allowed, until now, the development of continuous improvements, as predicted by Moore’s law. However, computation using current architectures and materials will inevitably—within the next 10 years—reach a limit because of fundamental scientific reasons. DOE convened a roundtable of experts in neuromorphic computing systems, materials science, and computer science in Washington on October 29-30, 2015 to address the following basic questions: Can brain-like (“neuromorphic”) computing devices based on new material concepts and systems be developed to dramatically outperform conventional CMOS based technology? If so, what are the basic research challenges for materials sicence and computing? The overarching answer that emerged was: The development of novel functional materials and devices incorporated into unique architectures will allow a revolutionary technological leap toward the implementation of a fully “neuromorphic” computer. To address this challenge, the following issues were considered: The main differences between neuromorphic and conventional computing as related to: signaling models, timing/clock, non-volatile memory, architecture, fault tolerance, integrated memory and compute, noise tolerance, analog vs. digital, and in situ learning New neuromorphic architectures needed to: produce lower energy consumption, potential novel nanostructured materials, and enhanced computation Device and materials properties needed to implement functions such as: hysteresis, stability, and fault tolerance Comparisons of different implementations: spin torque, memristors, resistive switching, phase change, and optical schemes for enhanced breakthroughs in performance, cost, fault tolerance, and/or manufacturability.

  5. Nominalization of Possessive Sentences

    Science.gov (United States)

    Rugaleva, Anelja

    1977-01-01

    Nominalization of possessive sentences in Russian is discussed. It is maintained that all lexical surface items originate as terms in a situation model, and that their actualization as different parts of speech is language-specific. Language data are used to support a locative interpretation of the semantic model. (CHK)

  6. Thermal memristor and neuromorphic networks for manipulating heat flow

    Directory of Open Access Journals (Sweden)

    Philippe Ben-Abdallah

    2017-06-01

    Full Text Available A memristor is one of four fundamental two-terminal solid elements in electronics. In addition with the resistor, the capacitor and the inductor, this passive element relates the electric charges to current in solid state elements. Here we report the existence of a thermal analog for this element made with metal-insulator transition materials. We demonstrate that these memristive systems can be used to create thermal neurons opening so the way to neuromorphic networks for smart thermal management and information treatment.

  7. Computational intelligence and neuromorphic computing potential for cybersecurity applications

    Science.gov (United States)

    Pino, Robinson E.; Shevenell, Michael J.; Cam, Hasan; Mouallem, Pierre; Shumaker, Justin L.; Edwards, Arthur H.

    2013-05-01

    In today's highly mobile, networked, and interconnected internet world, the flow and volume of information is overwhelming and continuously increasing. Therefore, it is believed that the next frontier in technological evolution and development will rely in our ability to develop intelligent systems that can help us process, analyze, and make-sense of information autonomously just as a well-trained and educated human expert. In computational intelligence, neuromorphic computing promises to allow for the development of computing systems able to imitate natural neurobiological processes and form the foundation for intelligent system architectures.

  8. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  9. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  10. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  11. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  12. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  13. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  14. Memristor: A New Concept in Synchronization of Coupled Neuromorphic Circuits

    Directory of Open Access Journals (Sweden)

    Ch. K. Volos

    2014-10-01

    Full Text Available The existence of the memristor, as a fourth fundamental circuit element, by researchers at Hewlett Packard (HP labs in 2008, has attracted much interest since then. This occurs because the memristor opens up new functionalities in electronics and it has led to the interpretation of phenomena not only in electronic devices but also in biological systems. Furthermore, many research teams work on projects, which use memristors in neuromorphic devices to simulate learning, adaptive and spontaneous behavior while other teams on systems, which attempt to simulate the behavior of biological synapses. In this paper, the latest achievements and applications of this newly development circuit element are presented. Also, the basic features of neuromorphic circuits, in which the memristor can be used as an electrical synapse, are studied. In this direction, a flux-controlled memristor model is adopted for using as a coupling element between coupled electronic circuits, which simulate the behavior of neuron-cells. For this reason, the circuits which are chosen realize the systems of differential equations that simulate the well-known Hindmarsh-Rose and FitzHugh-Nagumo neuron models. Finally, the simulation results of the use of a memristor as an electric synapse present the effectiveness of the proposed method and many interesting dynamic phenomena concerning the behavior of coupled neuron-cells.

  15. Event-Driven Contrastive Divergence for Spiking Neuromorphic Systems

    Directory of Open Access Journals (Sweden)

    Emre eNeftci

    2014-01-01

    Full Text Available Restricted Boltzmann Machines (RBMs and Deep Belief Networks have been demonstrated to perform efficiently in variety of applications, such as dimensionality reduction, feature learning, and classification. Their implementation on neuromorphic hardware platforms emulating large-scale networks of spiking neurons can have significant advantages from the perspectives of scalability, power dissipation and real-time interfacing with the environment. However the traditional RBM architecture and the commonly used training algorithm known as Contrastive Divergence (CD are based on discrete updates and exact arithmetics which do not directly map onto a dynamical neural substrate. Here, we present an event-driven variation of CD to train a RBM constructed with Integrate & Fire (I&F neurons, that is constrained by the limitations of existing and near future neuromorphic hardware platforms. Our strategy is based on neural sampling, which allows us to synthesize a spiking neural network that samples from a target Boltzmann distribution. The reverberating activity of the network replaces the discrete steps of the CD algorithm, while Spike Time Dependent Plasticity (STDP carries out the weight updates in an online, asynchronous fashion.We demonstrate our approach by training an RBM composed of leaky I&F neurons with STDP synapses to learn a generative model of the MNIST hand-written digit dataset, and by testing it in recognition, generation and cue integration tasks. Our results contribute to a machine learning-driven approach for synthesizing networks of spiking neurons capable of carrying out practical, high-level functionality.

  16. Event-driven contrastive divergence for spiking neuromorphic systems.

    Science.gov (United States)

    Neftci, Emre; Das, Srinjoy; Pedroni, Bruno; Kreutz-Delgado, Kenneth; Cauwenberghs, Gert

    2013-01-01

    Restricted Boltzmann Machines (RBMs) and Deep Belief Networks have been demonstrated to perform efficiently in a variety of applications, such as dimensionality reduction, feature learning, and classification. Their implementation on neuromorphic hardware platforms emulating large-scale networks of spiking neurons can have significant advantages from the perspectives of scalability, power dissipation and real-time interfacing with the environment. However, the traditional RBM architecture and the commonly used training algorithm known as Contrastive Divergence (CD) are based on discrete updates and exact arithmetics which do not directly map onto a dynamical neural substrate. Here, we present an event-driven variation of CD to train a RBM constructed with Integrate & Fire (I&F) neurons, that is constrained by the limitations of existing and near future neuromorphic hardware platforms. Our strategy is based on neural sampling, which allows us to synthesize a spiking neural network that samples from a target Boltzmann distribution. The recurrent activity of the network replaces the discrete steps of the CD algorithm, while Spike Time Dependent Plasticity (STDP) carries out the weight updates in an online, asynchronous fashion. We demonstrate our approach by training an RBM composed of leaky I&F neurons with STDP synapses to learn a generative model of the MNIST hand-written digit dataset, and by testing it in recognition, generation and cue integration tasks. Our results contribute to a machine learning-driven approach for synthesizing networks of spiking neurons capable of carrying out practical, high-level functionality.

  17. Integration of nanoscale memristor synapses in neuromorphic computing architectures

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Legenstein, Robert; Deligeorgis, George; Prodromakis, Themistoklis

    2013-09-01

    Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

  18. A Robust Sound Perception Model Suitable for Neuromorphic Implementation

    Directory of Open Access Journals (Sweden)

    Martin eCoath

    2014-01-01

    Full Text Available We have recently demonstrated the emergence of dynamic feature sensitivity through exposure to formative stimuli in a real-time neuromorphic system implementing a hybrid analogue/digital network of spiking neurons. This network, inspired by models of auditory processing in mammals, includes several mutually connected layers with distance-dependent transmission delays and learning in the form of spike timing dependent plasticity, which effects stimulus-driven changes in the network connectivity.Here we present results that demonstrate that the network is robust to a range of variations in the stimulus pattern, such as are found in naturalistic stimuli and neural responses. This robustness is a property critical to the development of realistic, electronic neuromorphic systems.We analyse the variability of the response of the network to `noisy' stimuli which allows us to characterize the acuity in information-theoretic terms. This provides an objective basis for the quantitative comparison of networks, their connectivity patterns, and learning strategies, which can inform future design decisions. We also show, using stimuli derived from speech samples, that the principles are robust to other challenges, such as variable presentation rate, that would have to be met by systems deployed in the real world. Finally we demonstrate the potential applicability of the approach to real sounds.

  19. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  20. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  1. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  2. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  3. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  4. Schizophrenia or possession?

    Science.gov (United States)

    Irmak, M Kemal

    2014-06-01

    Schizophrenia is typically a life-long condition characterized by acute symptom exacerbations and widely varying degrees of functional disability. Some of its symptoms, such as delusions and hallucinations, produce great subjective psychological pain. The most common delusion types are as follows: "My feelings and movements are controlled by others in a certain way" and "They put thoughts in my head that are not mine." Hallucinatory experiences are generally voices talking to the patient or among themselves. Hallucinations are a cardinal positive symptom of schizophrenia which deserves careful study in the hope it will give information about the pathophysiology of the disorder. We thought that many so-called hallucinations in schizophrenia are really illusions related to a real environmental stimulus. One approach to this hallucination problem is to consider the possibility of a demonic world. Demons are unseen creatures that are believed to exist in all major religions and have the power to possess humans and control their body. Demonic possession can manifest with a range of bizarre behaviors which could be interpreted as a number of different psychotic disorders with delusions and hallucinations. The hallucination in schizophrenia may therefore be an illusion-a false interpretation of a real sensory image formed by demons. A local faith healer in our region helps the patients with schizophrenia. His method of treatment seems to be successful because his patients become symptom free after 3 months. Therefore, it would be useful for medical professions to work together with faith healers to define better treatment pathways for schizophrenia.

  5. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  6. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  7. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  8. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  9. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  10. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  11. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  12. Stochastic learning in oxide binary synaptic device for neuromorphic computing.

    Science.gov (United States)

    Yu, Shimeng; Gao, Bin; Fang, Zheng; Yu, Hongyu; Kang, Jinfeng; Wong, H-S Philip

    2013-01-01

    Hardware implementation of neuromorphic computing is attractive as a computing paradigm beyond the conventional digital computing. In this work, we show that the SET (off-to-on) transition of metal oxide resistive switching memory becomes probabilistic under a weak programming condition. The switching variability of the binary synaptic device implements a stochastic learning rule. Such stochastic SET transition was statistically measured and modeled for a simulation of a winner-take-all network for competitive learning. The simulation illustrates that with such stochastic learning, the orientation classification function of input patterns can be effectively realized. The system performance metrics were compared between the conventional approach using the analog synapse and the approach in this work that employs the binary synapse utilizing the stochastic learning. The feasibility of using binary synapse in the neurormorphic computing may relax the constraints to engineer continuous multilevel intermediate states and widens the material choice for the synaptic device design.

  13. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing

    Science.gov (United States)

    Wang, Zhongrui; Joshi, Saumil; Savel'Ev, Sergey E.; Jiang, Hao; Midya, Rivu; Lin, Peng; Hu, Miao; Ge, Ning; Strachan, John Paul; Li, Zhiyong; Wu, Qing; Barnell, Mark; Li, Geng-Lin; Xin, Huolin L.; Williams, R. Stanley; Xia, Qiangfei; Yang, J. Joshua

    2017-01-01

    The accumulation and extrusion of Ca2+ in the pre- and postsynaptic compartments play a critical role in initiating plastic changes in biological synapses. To emulate this fundamental process in electronic devices, we developed diffusive Ag-in-oxide memristors with a temporal response during and after stimulation similar to that of the synaptic Ca2+ dynamics. In situ high-resolution transmission electron microscopy and nanoparticle dynamics simulations both demonstrate that Ag atoms disperse under electrical bias and regroup spontaneously under zero bias because of interfacial energy minimization, closely resembling synaptic influx and extrusion of Ca2+, respectively. The diffusive memristor and its dynamics enable a direct emulation of both short- and long-term plasticity of biological synapses, representing an advance in hardware implementation of neuromorphic functionalities.

  14. Microfluidic Neurons, a New Way in Neuromorphic Engineering?

    Directory of Open Access Journals (Sweden)

    Timothée Levi

    2016-08-01

    Full Text Available This article describes a new way to explore neuromorphic engineering, the biomimetic artificial neuron using microfluidic techniques. This new device could replace silicon neurons and solve the issues of biocompatibility and power consumption. The biological neuron transmits electrical signals based on ion flow through their plasma membrane. Action potentials are propagated along axons and represent the fundamental electrical signals by which information are transmitted from one place to another in the nervous system. Based on this physiological behavior, we propose a microfluidic structure composed of chambers representing the intra and extracellular environments, connected by channels actuated by Quake valves. These channels are equipped with selective ion permeable membranes to mimic the exchange of chemical species found in the biological neuron. A thick polydimethylsiloxane (PDMS membrane is used to create the Quake valve membrane. Integrated electrodes are used to measure the potential difference between the intracellular and extracellular environments: the membrane potential.

  15. Advances in neuromorphic hardware exploiting emerging nanoscale devices

    CERN Document Server

    2017-01-01

    This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

  16. Stochastic Learning in Oxide Binary Synaptic Device for Neuromorphic Computing

    Directory of Open Access Journals (Sweden)

    Shimeng eYu

    2013-10-01

    Full Text Available Hardware implementation of neuromorphic computing is attractive as a computing paradigm beyond the conventional digital computing. In this work, we show that the SET (off-to-on transition of metal oxide resistance switching memory becomes probabilistic under a weak programming condition. The switching variability of the binary synaptic device implements a stochastic learning rule. Such stochastic SET transition was statistically measured and modeled for a simulation of a winner-take-all network for competitive learning. The simulation illustrates that with such stochastic learning, the orientation classification function of input patterns can be effectively realized. The system performance metrics were compared between the conventional approach using the analog synapse and the approach in this work that employs the binary synapse utilizing the stochastic learning. The feasibility of using binary synapse in the neurormorphic computing may relax the constraints to engineer continuous multilevel intermediate states and widens the material choice for the synaptic device design.

  17. Neuromorphic Continuous-Time State Space Pole Placement Adaptive Control

    Institute of Scientific and Technical Information of China (English)

    卢钊; 孙明伟

    2003-01-01

    A neuromorphic continuous-time state space pole assignment adaptive controller is proposed, which is particularly appropriate for controlling a large-scale time-variant state-space model due to the parallely distributed nature of neurocomputing. In our approach, Hopfield neural network is exploited to identify the parameters of a continuous-time state-space model, and a dedicated recurrent neural network is designed to compute pole placement feedback control law in real time. Thus the identification and the control computation are incorporated in the closed-loop, adaptive, real-time control system. The merit of this approach is that the neural networks converge to their solutions very quickly and simultaneously.

  18. Nanotube devices based crossbar architecture: toward neuromorphic computing.

    Science.gov (United States)

    Zhao, W S; Agnus, G; Derycke, V; Filoramo, A; Bourgoin, J-P; Gamrat, C

    2010-04-30

    Nanoscale devices such as carbon nanotube and nanowires based transistors, memristors and molecular devices are expected to play an important role in the development of new computing architectures. While their size represents a decisive advantage in terms of integration density, it also raises the critical question of how to efficiently address large numbers of densely integrated nanodevices without the need for complex multi-layer interconnection topologies similar to those used in CMOS technology. Two-terminal programmable devices in crossbar geometry seem particularly attractive, but suffer from severe addressing difficulties due to cross-talk, which implies complex programming procedures. Three-terminal devices can be easily addressed individually, but with limited gain in terms of interconnect integration. We show how optically gated carbon nanotube devices enable efficient individual addressing when arranged in a crossbar geometry with shared gate electrodes. This topology is particularly well suited for parallel programming or learning in the context of neuromorphic computing architectures.

  19. Neuromorphic model of magnocellular and parvocellular visual paths: spatial resolution

    Energy Technology Data Exchange (ETDEWEB)

    Aguirre, Rolando C [Departamento de Luminotecnia, Luz y Vision, FACET, Universidad Nacional de Tucuman, Tucuman (Argentina); Felice, Carmelo J [Departamento de BioingenierIa, FACET, Universidad Nacional de Tucuman Argentina, Tucuman (Argentina); Colombo, Elisa M [Departamento de Luminotecnia, Luz y Vision, FACET, Universidad Nacional de Tucuman, Tucuman (Argentina)

    2007-11-15

    Physiological studies of the human retina show the existence of at least two visual information processing channels, the magnocellular and the parvocellular ones. Both have different spatial, temporal and chromatic features. This paper focuses on the different spatial resolution of these two channels. We propose a neuromorphic model, so that they match the retina's physiology. Considering the Deutsch and Deutsch model (1992), we propose two configurations (one for each visual channel) of the connection between the retina's different cell layers. The responses of the proposed model have similar behaviour to those of the visual cells: each channel has an optimum response corresponding to a given stimulus size which decreases for larger or smaller stimuli. This size is bigger for the magno path than for the parvo path and, in the end, both channels produce a magnifying of the borders of a stimulus.

  20. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  1. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  2. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  3. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  4. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  5. Proprioceptive Feedback through a Neuromorphic Muscle Spindle Model

    Directory of Open Access Journals (Sweden)

    Lorenzo Vannucci

    2017-06-01

    Full Text Available Connecting biologically inspired neural simulations to physical or simulated embodiments can be useful both in robotics, for the development of a new kind of bio-inspired controllers, and in neuroscience, to test detailed brain models in complete action-perception loops. The aim of this work is to develop a fully spike-based, biologically inspired mechanism for the translation of proprioceptive feedback. The translation is achieved by implementing a computational model of neural activity of type Ia and type II afferent fibers of muscle spindles, the primary source of proprioceptive information, which, in mammals is regulated through fusimotor activation and provides necessary adjustments during voluntary muscle contractions. As such, both static and dynamic γ-motoneurons activities are taken into account in the proposed model. Information from the actual proprioceptive sensors (i.e., motor encoders is then used to simulate the spindle contraction and relaxation, and therefore drive the neural activity. To assess the feasibility of this approach, the model is implemented on the NEST spiking neural network simulator and on the SpiNNaker neuromorphic hardware platform and tested on simulated and physical robotic platforms. The results demonstrate that the model can be used in both simulated and real-time robotic applications to translate encoder values into a biologically plausible neural activity. Thus, this model provides a completely spike-based building block, suitable for neuromorphic platforms, that will enable the development of sensory-motor closed loops which could include neural simulations of areas of the central nervous system or of low-level reflexes.

  6. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  7. Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.

    Science.gov (United States)

    Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

    2009-01-01

    Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

  8. Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system

    Directory of Open Access Journals (Sweden)

    Daniel Brüderle

    2009-06-01

    Full Text Available Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

  9. Some Remarks on Portuguese Possessives

    Directory of Open Access Journals (Sweden)

    Małgorzata Wielgosz

    2013-01-01

    Full Text Available The linguistic description of possessives is controversial. In traditional grammar they are defined as carriers of the meaning of possession or belonging; however, this paper intends to prove that in many cases such a meaning does not appear, and therefore, the possessive semantics of adjectives and pronouns known as possessives is a myth. Moreover, this article’s aim is to show the importance of context in the interpretation of the real meaning of a possessive. in order to confirm these hypotheses, and given the scarcity of works concerning Portuguese possessives, studies on English, Spanish and Polish ones carried out by various authors have been analyzed. What is more, some data from Reference Corpus of Contemporary Portuguese (CRPC have been examined. First of all, two different classifications of possessives are presented. Then, some cases of possessor deletion are shown, special attention being paid to the forms of expressing inalienable possession. After that, some structural characteristics of possessives are described, as well as their function as determiners. Finally, the paper shows the role that cultural and situational contexts play in the interpretation of the meaning of possessives.

  10. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  11. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  12. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  13. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  14. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  15. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

    Science.gov (United States)

    Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

    2003-01-01

    Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

  16. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  17. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  18. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  19. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  20. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  1. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  2. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  3. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  4. Electrically configurable materials and devices for intelligent neuromorphic applications

    Science.gov (United States)

    Lai, Qianxi

    As miniaturization of advanced CMOS device is approaching its fundamental physical limit, emerging electrically configurable devices which can modify its function dynamically and adaptively can arm existing CMOS circuitry with more versatile function, and are essential for reconfigurable computing and intelligent neural circuit. Organic semiconductors have the flexibility to change its electrical properties by changing its dopant concentration. Controllable ionic doping in conductive polymers has been realized and utilized to make electrically configurable devices for intelligent neuromorphic applications. First, a nonvolatile organic memory made of dopant configurable polymers has been demonstrated and showed controllable and repeatable conductance switching and nonvolatile characteristics. A 16x16 crossbar network composed of configurable switching devices has been fabricated and has successfully demonstrated its application on associative memory which can memorize and recognize learned pattern even with extra or missing features. An organic/Si hybrid field configurable transistor (FCT) has been fabricated on a Si nanowire FET platform by integrating the dopant configurable polymer into the gate structure. The FCT can be precisely configured to desired nonvolatile analog state dynamically, repeatedly, and reversibly by controlling the concentration of ions dopants in the polymer with a gate voltage. The flexible configurability and plasticity of the FCT could facilitate field-programmable circuits for defect-tolerance and synapse-like devices for dynamic learning. Further investigation on this ion-doped polymer showed the voltage modulation of the ionic charge concentration and dipole moment concentration in the polymer which contributed to a new electric device-a memory capacitor. This ionic transport in the polymer can lead to the time-dependent electrical property of the FCT (a synaptic transistor), which has demonstrated the first time synapse-like spiking

  5. Digital neuromorphic processing for a simplified algorithm of ultrasonic reception

    Science.gov (United States)

    Qiang, Lin; Clarke, Chris

    2001-05-01

    Previously, most mammalian auditory systems research has concentrated on human sensory perception whose frequencies are lower than 20 kHz. The implementations almost always used analog VLSI design. Due to the complexity of the model, it is difficult to implement these algorithms using current digital technology. This paper introduces a simplified model of biosonic reception system in bats and its implementation in the ``Chiroptera Inspired Robotic CEphaloid'' (CIRCE) project. This model consists of bandpass filters, a half-wave rectifier, low-pass filters, automatic gain control, and spike generation with thresholds. Due to the real-time requirements of the system, the system employs Butterworth filters and advanced field programmable gate array (FPGA) architectures to provide a viable solution. The ultrasonic signal processing is implemented on a Xilinx FPGA Virtex II device in real time. In the system, 12-bit input echo signals from receivers are sampled at 1 M samples per second for a signal frequency range from 20 to 200 kHz. The system performs a 704-channel per ear auditory pipeline operating in real time. The output of the system is a coded time series of threshold crossing points. Comparing hardware implementation with fixed-point software, the system shows significant performance gains with no loss of accuracy.

  6. Neuromorphic Computing: A Post-Moore's Law Complementary Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Schuman, Catherine D [ORNL; Birdwell, John Douglas [University of Tennessee (UT); Dean, Mark [University of Tennessee (UT); Plank, James [University of Tennessee (UT); Rose, Garrett [University of Tennessee (UT)

    2016-01-01

    We describe our approach to post-Moore's law computing with three neuromorphic computing models that share a RISC philosophy, featuring simple components combined with a flexible and programmable structure. We envision these to be leveraged as co-processors, or as data filters to provide in situ data analysis in supercomputing environments.

  7. A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach.

    Science.gov (United States)

    Jimenez-Fernandez, Angel; Cerezuela-Escudero, Elena; Miro-Amarante, Lourdes; Dominguez-Moralse, Manuel Jesus; de Asis Gomez-Rodriguez, Francisco; Linares-Barranco, Alejandro; Jimenez-Moreno, Gabriel

    2017-04-01

    This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11141, and a system clock frequency of 27 MHz.

  8. Neuromorphic implementation of a software-defined camera that can see through fire and smoke in real-time

    Science.gov (United States)

    Cha, Jae H.; Abbott, A. Lynn; Szu, Harold H.; Willey, Jefferson; Landa, Joseph; Krapels, Keith A.

    2014-05-01

    Software-defined Cameras (SDC) based on Boltzmann's molecular thermodynamics can "see" through visually-degraded fields such as fire, fog, and dust in some situations. This capability is possible by means of unsupervised learning implemented on a neuromorphic algo-tecture. This paper describes the SDC algorithm design strategy with respect to nontrivial solutions, stability, and accuracy. An example neuromorphic learning algorithm is presented along with unsupervised learning stopping criteria.

  9. Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System

    Science.gov (United States)

    Milde, Moritz B.; Blum, Hermann; Dietmüller, Alexander; Sumislawska, Dora; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

    2017-01-01

    Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware. PMID:28747883

  10. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  11. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  12. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  13. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  14. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  15. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  16. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  17. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  18. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  19. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  20. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  1. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  2. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  3. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  4. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  5. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  6. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  7. Rhetoric, Possessive Individualism, and Beyond.

    Science.gov (United States)

    Hurlbert, C. Mark

    1988-01-01

    Traces the influence of late-capitalist political ideology on the rhetoric which formed the process/product distinction; notes their sharing of an ideology of "possessive individualism." Reveals "social individualism" as an emerging ideology which may adjudicate the disparity between the ideals of process pedagogy and its…

  8. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  9. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  10. Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications

    Science.gov (United States)

    Linn, E.; Menzel, S.; Ferch, S.; Waser, R.

    2013-09-01

    Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications.

  11. TiO2 based nanostructured memristor for RRAM and neuromorphic applications: a simulation approach

    Science.gov (United States)

    Dongale, T. D.; Patil, P. J.; Desai, N. K.; Chougule, P. P.; Kumbhar, S. M.; Waifalkar, P. P.; Patil, P. B.; Vhatkar, R. S.; Takale, M. V.; Gaikwad, P. K.; Kamat, R. K.

    2016-07-01

    We report simulation of nanostructured memristor device using piecewise linear and nonlinear window functions for RRAM and neuromorphic applications. The linear drift model of memristor has been exploited for the simulation purpose with the linear and non-linear window function as the mathematical and scripting basis. The results evidences that the piecewise linear window function can aptly simulate the memristor characteristics pertaining to RRAM application. However, the nonlinear window function could exhibit the nonlinear phenomenon in simulation only at the lower magnitude of control parameter. This has motivated us to propose a new nonlinear window function for emulating the simulation model of the memristor. Interestingly, the proposed window function is scalable up to f( x) = 1 and exhibits the nonlinear behavior at higher magnitude of control parameter. Moreover, the simulation results of proposed nonlinear window function are encouraging and reveals the smooth nonlinear change from LRS to HRS and vice versa and therefore useful for the neuromorphic applications.

  12. A light-stimulated neuromorphic device based on graphene hybrid phototransistor

    CERN Document Server

    Qin, Shuchao; Liu, Yujie; Wan, Qing; Wang, Xinran; Xu, Yongbing; Shi, Yi; Wang, Xiaomu; Zhang, Rong

    2016-01-01

    Neuromorphic chip refers to an unconventional computing architecture that is modelled on biological brains. It is ideally suited for processing sensory data for intelligence computing, decision-making or context cognition. Despite rapid development, conventional artificial synapses exhibit poor connection flexibility and require separate data acquisition circuitry, resulting in limited functionalities and significant hardware redundancy. Here we report a novel light-stimulated artificial synapse based on a graphene-nanotube hybrid phototransistor that can directly convert optical stimuli into a "neural image" for further neuronal analysis. Our optically-driven synapses involve multiple steps of plasticity mechanisms and importantly exhibit flexible tuning of both short- and long-term plasticity. Furthermore, our neuromorphic phototransistor can take multiple pre-synaptic light stimuli via wavelength-division multiplexing and allows advanced optical processing through charge-trap-mediated optical coupling. The...

  13. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  14. Characterization and compensation of network-level anomalies in mixed-signal neuromorphic modeling platforms.

    Science.gov (United States)

    Petrovici, Mihai A; Vogginger, Bernhard; Müller, Paul; Breitwieser, Oliver; Lundqvist, Mikael; Muller, Lyle; Ehrlich, Matthias; Destexhe, Alain; Lansner, Anders; Schüffny, René; Schemmel, Johannes; Meier, Karlheinz

    2014-01-01

    Advancing the size and complexity of neural network models leads to an ever increasing demand for computational resources for their simulation. Neuromorphic devices offer a number of advantages over conventional computing architectures, such as high emulation speed or low power consumption, but this usually comes at the price of reduced configurability and precision. In this article, we investigate the consequences of several such factors that are common to neuromorphic devices, more specifically limited hardware resources, limited parameter configurability and parameter variations due to fixed-pattern noise and trial-to-trial variability. Our final aim is to provide an array of methods for coping with such inevitable distortion mechanisms. As a platform for testing our proposed strategies, we use an executable system specification (ESS) of the BrainScaleS neuromorphic system, which has been designed as a universal emulation back-end for neuroscientific modeling. We address the most essential limitations of this device in detail and study their effects on three prototypical benchmark network models within a well-defined, systematic workflow. For each network model, we start by defining quantifiable functionality measures by which we then assess the effects of typical hardware-specific distortion mechanisms, both in idealized software simulations and on the ESS. For those effects that cause unacceptable deviations from the original network dynamics, we suggest generic compensation mechanisms and demonstrate their effectiveness. Both the suggested workflow and the investigated compensation mechanisms are largely back-end independent and do not require additional hardware configurability beyond the one required to emulate the benchmark networks in the first place. We hereby provide a generic methodological environment for configurable neuromorphic devices that are targeted at emulating large-scale, functional neural networks.

  15. Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity.

    Directory of Open Access Journals (Sweden)

    Mostafa Rahimi Azghadi

    Full Text Available Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.

  16. Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Iannella, Nicolangelo; Al-Sarawi, Said; Abbott, Derek

    2014-01-01

    Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.

  17. FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

    Science.gov (United States)

    Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar

    2013-09-01

    Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion.

  18. Analyzing the scaling of connectivity in neuromorphic hardware and in models of neural networks.

    Science.gov (United States)

    Partzsch, Johannes; Schüffny, René

    2011-06-01

    In recent years, neuromorphic hardware systems have significantly grown in size. With more and more neurons and synapses integrated in such systems, the neural connectivity and its configurability have become crucial design constraints. To tackle this problem, we introduce a generic extended graph description of connection topologies that allows a systematical analysis of connectivity in both neuromorphic hardware and neural network models. The unifying nature of our approach enables a close exchange between hardware and models. For an existing hardware system, the optimally matched network model can be extracted. Inversely, a hardware architecture may be fitted to a particular model network topology with our description method. As a further strength, the extended graph can be used to quantify the amount of configurability for a certain network topology. This is a hardware design variable that has widely been neglected, mainly because of a missing analysis method. To condense our analysis results, we develop a classification for the scaling complexity of network models and neuromorphic hardware, based on the total number of connections and the configurability. We find a gap between several models and existing hardware, making these hardware systems either impossible or inefficient to use for scaled-up network models. In this respect, our analysis results suggest models with locality in their connections as promising approach for tackling this scaling gap.

  19. Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines

    Science.gov (United States)

    Neftci, Emre O.; Augustine, Charles; Paul, Somnath; Detorakis, Georgios

    2017-01-01

    An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Gradient Back Propagation (BP) rule, often relies on the immediate availability of network-wide information stored with high-precision memory during learning, and precise operations that are difficult to realize in neuromorphic hardware. Remarkably, recent work showed that exact backpropagated gradients are not essential for learning deep representations. Building on these results, we demonstrate an event-driven random BP (eRBP) rule that uses an error-modulated synaptic plasticity for learning deep representations. Using a two-compartment Leaky Integrate & Fire (I&F) neuron, the rule requires only one addition and two comparisons for each synaptic weight, making it very suitable for implementation in digital or mixed-signal neuromorphic hardware. Our results show that using eRBP, deep representations are rapidly learned, achieving classification accuracies on permutation invariant datasets comparable to those obtained in artificial neural network simulations on GPUs, while being robust to neural and synaptic state quantizations during learning. PMID:28680387

  20. Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines.

    Science.gov (United States)

    Neftci, Emre O; Augustine, Charles; Paul, Somnath; Detorakis, Georgios

    2017-01-01

    An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Gradient Back Propagation (BP) rule, often relies on the immediate availability of network-wide information stored with high-precision memory during learning, and precise operations that are difficult to realize in neuromorphic hardware. Remarkably, recent work showed that exact backpropagated gradients are not essential for learning deep representations. Building on these results, we demonstrate an event-driven random BP (eRBP) rule that uses an error-modulated synaptic plasticity for learning deep representations. Using a two-compartment Leaky Integrate & Fire (I&F) neuron, the rule requires only one addition and two comparisons for each synaptic weight, making it very suitable for implementation in digital or mixed-signal neuromorphic hardware. Our results show that using eRBP, deep representations are rapidly learned, achieving classification accuracies on permutation invariant datasets comparable to those obtained in artificial neural network simulations on GPUs, while being robust to neural and synaptic state quantizations during learning.

  1. A robust and scalable neuromorphic communication system by combining synaptic time multiplexing and MIMO-OFDM.

    Science.gov (United States)

    Srinivasa, Narayan; Zhang, Deying; Grigorian, Beayna

    2014-03-01

    This paper describes a novel architecture for enabling robust and efficient neuromorphic communication. The architecture combines two concepts: 1) synaptic time multiplexing (STM) that trades space for speed of processing to create an intragroup communication approach that is firing rate independent and offers more flexibility in connectivity than cross-bar architectures and 2) a wired multiple input multiple output (MIMO) communication with orthogonal frequency division multiplexing (OFDM) techniques to enable a robust and efficient intergroup communication for neuromorphic systems. The MIMO-OFDM concept for the proposed architecture was analyzed by simulating large-scale spiking neural network architecture. Analysis shows that the neuromorphic system with MIMO-OFDM exhibits robust and efficient communication while operating in real time with a high bit rate. Through combining STM with MIMO-OFDM techniques, the resulting system offers a flexible and scalable connectivity as well as a power and area efficient solution for the implementation of very large-scale spiking neural architectures in hardware.

  2. 50 CFR 20.33 - Possession limit.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 6 2010-10-01 2010-10-01 false Possession limit. 20.33 Section 20.33... PLANTS (CONTINUED) MIGRATORY BIRD HUNTING Possession § 20.33 Possession limit. No person shall possess more migratory game birds taken in the United States than the possession limit or the...

  3. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  4. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  5. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  6. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  7. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  8. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  9. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  10. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  11. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  12. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  13. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  14. VLSI circuits implementing computational models of neocortical circuits.

    Science.gov (United States)

    Wijekoon, Jayawan H B; Dudek, Piotr

    2012-09-15

    This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.

  15. An analog VLSI chip emulating polarization vision of Octopus retina.

    Science.gov (United States)

    Momeni, Massoud; Titus, Albert H

    2006-01-01

    Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

  16. 50 CFR 648.145 - Possession limit.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Possession limit. 648.145 Section 648.145... Fishery § 648.145 Possession limit. (a) No person shall possess more than 25 black sea bass, in, or... that is not eligible for a black sea bass moratorium permit are subject to this possession limit....

  17. 50 CFR 648.125 - Possession limit.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Possession limit. 648.125 Section 648.125... § 648.125 Possession limit. (a) No person shall possess more than 10 scup in, or harvested from, the EEZ... moratorium permit are subject to this possession limit. The owner, operator, and crew of a charter or...

  18. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  19. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  20. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  1. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  2. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  3. Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.

    Science.gov (United States)

    Brink, S; Nease, S; Hasler, P

    2013-09-01

    Results are presented from several spiking network experiments performed on a novel neuromorphic integrated circuit. The networks are discussed in terms of their computational significance, which includes applications such as arbitrary spatiotemporal pattern generation and recognition, winner-take-all competition, stable generation of rhythmic outputs, and volatile memory. Analogies to the behavior of real biological neural systems are also noted. The alternatives for implementing the same computations are discussed and compared from a computational efficiency standpoint, with the conclusion that implementing neural networks on neuromorphic hardware is significantly more power efficient than numerical integration of model equations on traditional digital hardware.

  4. Large-Scale Simulations of Plastic Neural Networks on Neuromorphic Hardware.

    Science.gov (United States)

    Knight, James C; Tully, Philip J; Kaplan, Bernhard A; Lansner, Anders; Furber, Steve B

    2016-01-01

    SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Rather than using bespoke analog or digital hardware, the basic computational unit of a SpiNNaker system is a general-purpose ARM processor, allowing it to be programmed to simulate a wide variety of neuron and synapse models. This flexibility is particularly valuable in the study of biological plasticity phenomena. A recently proposed learning rule based on the Bayesian Confidence Propagation Neural Network (BCPNN) paradigm offers a generic framework for modeling the interaction of different plasticity mechanisms using spiking neurons. However, it can be computationally expensive to simulate large networks with BCPNN learning since it requires multiple state variables for each synapse, each of which needs to be updated every simulation time-step. We discuss the trade-offs in efficiency and accuracy involved in developing an event-based BCPNN implementation for SpiNNaker based on an analytical solution to the BCPNN equations, and detail the steps taken to fit this within the limited computational and memory resources of the SpiNNaker architecture. We demonstrate this learning rule by learning temporal sequences of neural activity within a recurrent attractor network which we simulate at scales of up to 2.0 × 104 neurons and 5.1 × 107 plastic synapses: the largest plastic neural network ever to be simulated on neuromorphic hardware. We also run a comparable simulation on a Cray XC-30 supercomputer system and find that, if it is to match the run-time of our SpiNNaker simulation, the super computer system uses approximately 45× more power. This suggests that cheaper, more power efficient neuromorphic systems are becoming useful discovery tools in the study of plasticity in large-scale brain models.

  5. A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.

    Science.gov (United States)

    Brüderle, Daniel; Petrovici, Mihai A; Vogginger, Bernhard; Ehrlich, Matthias; Pfeil, Thomas; Millner, Sebastian; Grübl, Andreas; Wendt, Karsten; Müller, Eric; Schwartz, Marc-Olivier; de Oliveira, Dan Husmann; Jeltsch, Sebastian; Fieres, Johannes; Schilling, Moritz; Müller, Paul; Breitwieser, Oliver; Petkov, Venelin; Muller, Lyle; Davison, Andrew P; Krishnamurthy, Pradeep; Kremkow, Jens; Lundqvist, Mikael; Muller, Eilif; Partzsch, Johannes; Scholze, Stefan; Zühl, Lukas; Mayr, Christian; Destexhe, Alain; Diesmann, Markus; Potjans, Tobias C; Lansner, Anders; Schüffny, René; Schemmel, Johannes; Meier, Karlheinz

    2011-05-01

    In this article, we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results.

  6. What can neuromorphic event-driven precise timing add to spike-based pattern recognition?

    Science.gov (United States)

    Akolkar, Himanshu; Meyer, Cedric; Clady, Zavier; Marre, Olivier; Bartolozzi, Chiara; Panzeri, Stefano; Benosman, Ryad

    2015-03-01

    This letter introduces a study to precisely measure what an increase in spike timing precision can add to spike-driven pattern recognition algorithms. The concept of generating spikes from images by converting gray levels into spike timings is currently at the basis of almost every spike-based modeling of biological visual systems. The use of images naturally leads to generating incorrect artificial and redundant spike timings and, more important, also contradicts biological findings indicating that visual processing is massively parallel, asynchronous with high temporal resolution. A new concept for acquiring visual information through pixel-individual asynchronous level-crossing sampling has been proposed in a recent generation of asynchronous neuromorphic visual sensors. Unlike conventional cameras, these sensors acquire data not at fixed points in time for the entire array but at fixed amplitude changes of their input, resulting optimally sparse in space and time-pixel individually and precisely timed only if new, (previously unknown) information is available (event based). This letter uses the high temporal resolution spiking output of neuromorphic event-based visual sensors to show that lowering time precision degrades performance on several recognition tasks specifically when reaching the conventional range of machine vision acquisition frequencies (30-60 Hz). The use of information theory to characterize separability between classes for each temporal resolution shows that high temporal acquisition provides up to 70% more information that conventional spikes generated from frame-based acquisition as used in standard artificial vision, thus drastically increasing the separability between classes of objects. Experiments on real data show that the amount of information loss is correlated with temporal precision. Our information-theoretic study highlights the potentials of neuromorphic asynchronous visual sensors for both practical applications and theoretical

  7. Synapse-Centric Mapping of Cortical Models to the SpiNNaker Neuromorphic Architecture.

    Science.gov (United States)

    Knight, James C; Furber, Steve B

    2016-01-01

    While the adult human brain has approximately 8.8 × 10(10) neurons, this number is dwarfed by its 1 × 10(15) synapses. From the point of view of neuromorphic engineering and neural simulation in general this makes the simulation of these synapses a particularly complex problem. SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Current solutions for simulating spiking neural networks on SpiNNaker are heavily inspired by work on distributed high-performance computing. However, while SpiNNaker shares many characteristics with such distributed systems, its component nodes have much more limited resources and, as the system lacks global synchronization, the computation performed on each node must complete within a fixed time step. We first analyze the performance of the current SpiNNaker neural simulation software and identify several problems that occur when it is used to simulate networks of the type often used to model the cortex which contain large numbers of sparsely connected synapses. We then present a new, more flexible approach for mapping the simulation of such networks to SpiNNaker which solves many of these problems. Finally we analyze the performance of our new approach using both benchmarks, designed to represent cortical connectivity, and larger, functional cortical models. In a benchmark network where neurons receive input from 8000 STDP synapses, our new approach allows 4× more neurons to be simulated on each SpiNNaker core than has been previously possible. We also demonstrate that the largest plastic neural network previously simulated on neuromorphic hardware can be run in real time using our new approach: double the speed that was previously achieved. Additionally this network contains two types of plastic synapse which previously had to be trained separately but, using our new approach, can be trained simultaneously.

  8. Synapse-centric mapping of cortical models to the SpiNNaker neuromorphic architecture

    Directory of Open Access Journals (Sweden)

    James Courtney Knight

    2016-09-01

    Full Text Available While the adult human brain has approximately 8.8x10^10 neurons, this number is dwarfed by its 1x10^15 synapses. From the point of view of neuromorphic engineering and neural simulation in general this makes the simulation of these synapses a particularly complex problem. SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Current solutions for simulating spiking neural networks on SpiNNaker are heavily inspired by work on distributed high-performance computing. However, while SpiNNaker shares many characteristics with such distributed systems, its component nodes have much more limited resources and, as the system lacks global synchronization, the computation performed on each node must complete within a fixed time step. We first analyze the performance of the current SpiNNaker neural simulation software and identify several problems that occur when it is used to simulate networks of the type often used to model the cortex which contain large numbers of sparsely connected synapses. We then present a new, more flexible approach for mapping the simulation of such networks to SpiNNaker which solves many of these problems. Finally we analyze the performance of our new approach using both benchmarks, designed to represent cortical connectivity, and larger, functional cortical models. In a benchmark network where neurons receive input from 8000 STDP synapses, our new approach allows more neurons to be simulated on each SpiNNaker core than has been previously possible. We also demonstrate that the largest plastic neural network previously simulated on neuromorphic hardware can be run in real time using our new approach: double the speed that was previously achieved. Additionally this network contains two types of plastic synapse which previously had to be trained separately but, using our new approach, can be trained simultaneously.

  9. Controllable spiking patterns in long-wavelength vertical cavity surface emitting lasers for neuromorphic photonics systems

    Energy Technology Data Exchange (ETDEWEB)

    Hurtado, Antonio, E-mail: antonio.hurtado@strath.ac.uk [Institute of Photonics, SUPA Department of Physics, University of Strathclyde, TIC Centre, 99 George Street, Glasgow G1 1RD (United Kingdom); Javaloyes, Julien [Departament de Fisica, Universitat de les Illes Balears, c/Valldemossa km 7.5, 07122 Mallorca (Spain)

    2015-12-14

    Multiple controllable spiking patterns are achieved in a 1310 nm Vertical-Cavity Surface Emitting Laser (VCSEL) in response to induced perturbations and for two different cases of polarized optical injection, namely, parallel and orthogonal. Furthermore, reproducible spiking responses are demonstrated experimentally at sub-nanosecond speed resolution and with a controlled number of spikes fired. This work opens therefore exciting research avenues for the use of VCSELs in ultrafast neuromorphic photonic systems for non-traditional computing applications, such as all-optical binary-to-spiking format conversion and spiking information encoding.

  10. Neuromorphic Computing, Architectures, Models, and Applications. A Beyond-CMOS Approach to Future Computing, June 29-July 1, 2016, Oak Ridge, TN

    Energy Technology Data Exchange (ETDEWEB)

    Potok, Thomas [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Schuman, Catherine [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Patton, Robert [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Hylton, Todd [Brain Corporation, San Diego, CA (United States); Li, Hai [Univ. of Pittsburgh, PA (United States); Pino, Robinson [US Dept. of Energy, Washington, DC (United States)

    2016-12-31

    The White House and Department of Energy have been instrumental in driving the development of a neuromorphic computing program to help the United States continue its lead in basic research into (1) Beyond Exascale—high performance computing beyond Moore’s Law and von Neumann architectures, (2) Scientific Discovery—new paradigms for understanding increasingly large and complex scientific data, and (3) Emerging Architectures—assessing the potential of neuromorphic and quantum architectures. Neuromorphic computing spans a broad range of scientific disciplines from materials science to devices, to computer science, to neuroscience, all of which are required to solve the neuromorphic computing grand challenge. In our workshop we focus on the computer science aspects, specifically from a neuromorphic device through an application. Neuromorphic devices present a very different paradigm to the computer science community from traditional von Neumann architectures, which raises six major questions about building a neuromorphic application from the device level. We used these fundamental questions to organize the workshop program and to direct the workshop panels and discussions. From the white papers, presentations, panels, and discussions, there emerged several recommendations on how to proceed.

  11. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  12. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  13. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  14. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  15. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  16. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  17. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  18. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  19. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  20. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  1. DEVELOPMENT OF NEUROMORPHIC SIFT OPERATOR WITH APPLICATION TO HIGH SPEED IMAGE MATCHING

    Directory of Open Access Journals (Sweden)

    M. Shankayi

    2015-12-01

    Full Text Available There was always a speed/accuracy challenge in photogrammetric mapping process, including feature detection and matching. Most of the researches have improved algorithm's speed with simplifications or software modifications which increase the accuracy of the image matching process. This research tries to improve speed without enhancing the accuracy of the same algorithm using Neuromorphic techniques. In this research we have developed a general design of a Neuromorphic ASIC to handle algorithms such as SIFT. We also have investigated neural assignment in each step of the SIFT algorithm. With a rough estimation based on delay of the used elements including MAC and comparator, we have estimated the resulting chip's performance for 3 scenarios, Full HD movie (Videogrammetry, 24 MP (UAV photogrammetry, and 88 MP image sequence. Our estimations led to approximate 3000 fps for Full HD movie, 250 fps for 24 MP image sequence and 68 fps for 88MP Ultracam image sequence which can be a huge improvement for current photogrammetric processing systems. We also estimated the power consumption of less than10 watts which is not comparable to current workflows.

  2. Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis.

    Science.gov (United States)

    Papadimitriou, Konstantinos I; Liu, Shih-Chii; Indiveri, Giacomo; Drakakis, Emmanuel M

    2014-01-01

    The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framework. The speed advantage of the proposed mathematical framework as an analysis tool is also demonstrated by a compelling comparative circuit analysis example of high order, where the GBCF and another well-known log-domain circuit analysis method are used for the determination of the input-output transfer function of the high (4(th)) order topology.

  3. A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers

    Energy Technology Data Exchange (ETDEWEB)

    Potok, Thomas E [ORNL; Schuman, Catherine D [ORNL; Young, Steven R [ORNL; Patton, Robert M [ORNL; Spedalieri, Federico [University of Southern California, Information Sciences Institute; Liu, Jeremy [University of Southern California, Information Sciences Institute; Yao, Ke-Thia [University of Southern California, Information Sciences Institute; Rose, Garrett [University of Tennessee (UT); Chakma, Gangotree [University of Tennessee (UT)

    2016-01-01

    Current Deep Learning models use highly optimized convolutional neural networks (CNN) trained on large graphical processing units (GPU)-based computers with a fairly simple layered network topology, i.e., highly connected layers, without intra-layer connections. Complex topologies have been proposed, but are intractable to train on current systems. Building the topologies of the deep learning network requires hand tuning, and implementing the network in hardware is expensive in both cost and power. In this paper, we evaluate deep learning models using three different computing architectures to address these problems: quantum computing to train complex topologies, high performance computing (HPC) to automatically determine network topology, and neuromorphic computing for a low-power hardware implementation. Due to input size limitations of current quantum computers we use the MNIST dataset for our evaluation. The results show the possibility of using the three architectures in tandem to explore complex deep learning networks that are untrainable using a von Neumann architecture. We show that a quantum computer can find high quality values of intra-layer connections and weights, while yielding a tractable time result as the complexity of the network increases; a high performance computer can find optimal layer-based topologies; and a neuromorphic computer can represent the complex topology and weights derived from the other architectures in low power memristive hardware. This represents a new capability that is not feasible with current von Neumann architecture. It potentially enables the ability to solve very complicated problems unsolvable with current computing technologies.

  4. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications.

    Science.gov (United States)

    Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

    2016-08-11

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure-Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron-Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  5. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    Directory of Open Access Journals (Sweden)

    Lucas Antón Pastur-Romay

    2016-08-01

    Full Text Available Over the past decade, Deep Artificial Neural Networks (DNNs have become the state-of-the-art algorithms in Machine Learning (ML, speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs. All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS, Quantitative Structure–Activity Relationship (QSAR research, protein structure prediction and genomics (and other omics data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  6. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  7. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  8. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  9. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  10. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  11. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  12. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  13. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  14. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  15. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  16. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  17. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  18. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  19. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  20. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  1. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  2. VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality

    Directory of Open Access Journals (Sweden)

    Stefan eScholze

    2011-10-01

    Full Text Available State-of-the-art large scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA delivers a factor 25-50 more event transmission rate than other current neuromorphic communication infrastructures.

  3. Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

    Science.gov (United States)

    Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

    2017-10-01

    Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

  4. Development of a neuromorphic control system for a lightweight humanoid robot

    Science.gov (United States)

    Folgheraiter, Michele; Keldibek, Amina; Aubakir, Bauyrzhan; Salakchinov, Shyngys; Gini, Giuseppina; Mauro Franchi, Alessio; Bana, Matteo

    2017-03-01

    A neuromorphic control system for a lightweight middle size humanoid biped robot built using 3D printing techniques is proposed. The control architecture consists of different modules capable to learn and autonomously reproduce complex periodic trajectories. Each module is represented by a chaotic Recurrent Neural Network (RNN) with a core of dynamic neurons randomly and sparsely connected with fixed synapses. A set of read-out units with adaptable synapses realize a linear combination of the neurons output in order to reproduce the target signals. Different experiments were conducted to find out the optimal initialization for the RNN’s parameters. From simulation results, using normalized signals obtained from the robot model, it was proven that all the instances of the control module can learn and reproduce the target trajectories with an average RMS error of 1.63 and variance 0.74.

  5. Neuromorphic Audio-Visual Sensor Fusion on a Sound-Localising Robot

    Directory of Open Access Journals (Sweden)

    Vincent Yue-Sek Chan

    2012-02-01

    Full Text Available This paper presents the first robotic system featuring audio-visual sensor fusion with neuromorphic sensors. We combine a pair of silicon cochleae and a silicon retina on a robotic platform to allow the robot to learn sound localisation through self-motion and visual feedback, using an adaptive ITD-based sound localisation algorithm. After training, the robot can localise sound sources (white or pink noise in a reverberant environment with an RMS error of 4 to 5 degrees in azimuth. In the second part of the paper, we investigate the source binding problem. An experiment is conducted to test the effectiveness of matching an audio event with a corresponding visual event based on their onset time. The results show that this technique can be quite effective, despite its simplicity.

  6. Interplay of multiple synaptic plasticity features in filamentary memristive devices for neuromorphic computing

    Science.gov (United States)

    La Barbera, Selina; Vincent, Adrien F.; Vuillaume, Dominique; Querlioz, Damien; Alibart, Fabien

    2016-12-01

    Bio-inspired computing represents today a major challenge at different levels ranging from material science for the design of innovative devices and circuits to computer science for the understanding of the key features required for processing of natural data. In this paper, we propose a detail analysis of resistive switching dynamics in electrochemical metallization cells for synaptic plasticity implementation. We show how filament stability associated to joule effect during switching can be used to emulate key synaptic features such as short term to long term plasticity transition and spike timing dependent plasticity. Furthermore, an interplay between these different synaptic features is demonstrated for object motion detection in a spike-based neuromorphic circuit. System level simulation presents robust learning and promising synaptic operation paving the way to complex bio-inspired computing systems composed of innovative memory devices.

  7. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  8. A neuromorphic architecture for object recognition and motion anticipation using burst-STDP.

    Directory of Open Access Journals (Sweden)

    Andrew Nere

    Full Text Available In this work we investigate the possibilities offered by a minimal framework of artificial spiking neurons to be deployed in silico. Here we introduce a hierarchical network architecture of spiking neurons which learns to recognize moving objects in a visual environment and determine the correct motor output for each object. These tasks are learned through both supervised and unsupervised spike timing dependent plasticity (STDP. STDP is responsible for the strengthening (or weakening of synapses in relation to pre- and post-synaptic spike times and has been described as a Hebbian paradigm taking place both in vitro and in vivo. We utilize a variation of STDP learning, called burst-STDP, which is based on the notion that, since spikes are expensive in terms of energy consumption, then strong bursting activity carries more information than single (sparse spikes. Furthermore, this learning algorithm takes advantage of homeostatic renormalization, which has been hypothesized to promote memory consolidation during NREM sleep. Using this learning rule, we design a spiking neural network architecture capable of object recognition, motion detection, attention towards important objects, and motor control outputs. We demonstrate the abilities of our design in a simple environment with distractor objects, multiple objects moving concurrently, and in the presence of noise. Most importantly, we show how this neural network is capable of performing these tasks using a simple leaky-integrate-and-fire (LIF neuron model with binary synapses, making it fully compatible with state-of-the-art digital neuromorphic hardware designs. As such, the building blocks and learning rules presented in this paper appear promising for scalable fully neuromorphic systems to be implemented in hardware chips.

  9. Virtual neurorobotics (VNR to accelerate development of plausible neuromorphic brain architectures

    Directory of Open Access Journals (Sweden)

    Philip H Goodman

    2007-11-01

    Full Text Available Traditional research in artificial intelligence and machine learning has viewed the brain as a specially adapted information-processing system. More recently the field of social robotics has been advanced to capture the important dynamics of human cognition and interaction. An overarching societal goal of this research is to incorporate the resultant knowledge about intelligence into technology for prosthetic, assistive, security, and decision support applications. However, despite many decades of investment in learning and classification systems, this paradigm has yet to yield truly “intelligent” systems. For this reason, many investigators are now attempting to incorporate more realistic neuromorphic properties into machine learning systems, encouraged by over two decades of neuroscience research that has provided parameters that characterize the brain’s interdependent genomic, proteomic, metabolomic, anatomic, and electrophysiological networks. Given the complexity of neural systems, developing tenable models to capture the essence of natural intelligence for real-time application requires that we discriminate features underlying information processing and intrinsic motivation from those reflecting biological constraints (such as maintaining structural integrity and transporting metabolic products. We propose herein a conceptual framework and an iterative method of virtual neurorobotics (VNR intended to rapidly forward-engineer and test progressively more complex putative neuromorphic brain prototypes for their ability to support intrinsically intelligent, intentional interaction with humans. The VNR system is based on the viewpoint that a truly intelligent system must be driven by emotion rather than programmed tasking, incorporating intrinsic motivation and intentionality. We report pilot results of a closed-loop, real-time interactive VNR system with a spiking neural brain, and provide a video demonstration as online supplemental

  10. Effect of Heterogeneity on Decorrelation Mechanisms in Spiking Neural Networks: A Neuromorphic-Hardware Study

    Science.gov (United States)

    Pfeil, Thomas; Jordan, Jakob; Tetzlaff, Tom; Grübl, Andreas; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

    2016-04-01

    High-level brain function, such as memory, classification, or reasoning, can be realized by means of recurrent networks of simplified model neurons. Analog neuromorphic hardware constitutes a fast and energy-efficient substrate for the implementation of such neural computing architectures in technical applications and neuroscientific research. The functional performance of neural networks is often critically dependent on the level of correlations in the neural activity. In finite networks, correlations are typically inevitable due to shared presynaptic input. Recent theoretical studies have shown that inhibitory feedback, abundant in biological neural networks, can actively suppress these shared-input correlations and thereby enable neurons to fire nearly independently. For networks of spiking neurons, the decorrelating effect of inhibitory feedback has so far been explicitly demonstrated only for homogeneous networks of neurons with linear subthreshold dynamics. Theory, however, suggests that the effect is a general phenomenon, present in any system with sufficient inhibitory feedback, irrespective of the details of the network structure or the neuronal and synaptic properties. Here, we investigate the effect of network heterogeneity on correlations in sparse, random networks of inhibitory neurons with nonlinear, conductance-based synapses. Emulations of these networks on the analog neuromorphic-hardware system Spikey allow us to test the efficiency of decorrelation by inhibitory feedback in the presence of hardware-specific heterogeneities. The configurability of the hardware substrate enables us to modulate the extent of heterogeneity in a systematic manner. We selectively study the effects of shared input and recurrent connections on correlations in membrane potentials and spike trains. Our results confirm that shared-input correlations are actively suppressed by inhibitory feedback also in highly heterogeneous networks exhibiting broad, heavy-tailed firing

  11. Virtual Neurorobotics (VNR) to Accelerate Development of Plausible Neuromorphic Brain Architectures.

    Science.gov (United States)

    Goodman, Philip H; Buntha, Sermsak; Zou, Quan; Dascalu, Sergiu-Mihai

    2007-01-01

    Traditional research in artificial intelligence and machine learning has viewed the brain as a specially adapted information-processing system. More recently the field of social robotics has been advanced to capture the important dynamics of human cognition and interaction. An overarching societal goal of this research is to incorporate the resultant knowledge about intelligence into technology for prosthetic, assistive, security, and decision support applications. However, despite many decades of investment in learning and classification systems, this paradigm has yet to yield truly "intelligent" systems. For this reason, many investigators are now attempting to incorporate more realistic neuromorphic properties into machine learning systems, encouraged by over two decades of neuroscience research that has provided parameters that characterize the brain's interdependent genomic, proteomic, metabolomic, anatomic, and electrophysiological networks. Given the complexity of neural systems, developing tenable models to capture the essence of natural intelligence for real-time application requires that we discriminate features underlying information processing and intrinsic motivation from those reflecting biological constraints (such as maintaining structural integrity and transporting metabolic products). We propose herein a conceptual framework and an iterative method of virtual neurorobotics (VNR) intended to rapidly forward-engineer and test progressively more complex putative neuromorphic brain prototypes for their ability to support intrinsically intelligent, intentional interaction with humans. The VNR system is based on the viewpoint that a truly intelligent system must be driven by emotion rather than programmed tasking, incorporating intrinsic motivation and intentionality. We report pilot results of a closed-loop, real-time interactive VNR system with a spiking neural brain, and provide a video demonstration as online supplemental material.

  12. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  13. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  14. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  15. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  16. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  17. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  18. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  19. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  20. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  1. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  2. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  3. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  4. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  5. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  6. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  7. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  8. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  9. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  10. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  11. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  12. A spiking neural network model of 3D perception for event-based neuromorphic stereo vision systems

    Science.gov (United States)

    Osswald, Marc; Ieng, Sio-Hoi; Benosman, Ryad; Indiveri, Giacomo

    2017-01-01

    Stereo vision is an important feature that enables machine vision systems to perceive their environment in 3D. While machine vision has spawned a variety of software algorithms to solve the stereo-correspondence problem, their implementation and integration in small, fast, and efficient hardware vision systems remains a difficult challenge. Recent advances made in neuromorphic engineering offer a possible solution to this problem, with the use of a new class of event-based vision sensors and neural processing devices inspired by the organizing principles of the brain. Here we propose a radically novel model that solves the stereo-correspondence problem with a spiking neural network that can be directly implemented with massively parallel, compact, low-latency and low-power neuromorphic engineering devices. We validate the model with experimental results, highlighting features that are in agreement with both computational neuroscience stereo vision theories and experimental findings. We demonstrate its features with a prototype neuromorphic hardware system and provide testable predictions on the role of spike-based representations and temporal dynamics in biological stereo vision processing systems. PMID:28079187

  13. A spiking neural network model of 3D perception for event-based neuromorphic stereo vision systems

    Science.gov (United States)

    Osswald, Marc; Ieng, Sio-Hoi; Benosman, Ryad; Indiveri, Giacomo

    2017-01-01

    Stereo vision is an important feature that enables machine vision systems to perceive their environment in 3D. While machine vision has spawned a variety of software algorithms to solve the stereo-correspondence problem, their implementation and integration in small, fast, and efficient hardware vision systems remains a difficult challenge. Recent advances made in neuromorphic engineering offer a possible solution to this problem, with the use of a new class of event-based vision sensors and neural processing devices inspired by the organizing principles of the brain. Here we propose a radically novel model that solves the stereo-correspondence problem with a spiking neural network that can be directly implemented with massively parallel, compact, low-latency and low-power neuromorphic engineering devices. We validate the model with experimental results, highlighting features that are in agreement with both computational neuroscience stereo vision theories and experimental findings. We demonstrate its features with a prototype neuromorphic hardware system and provide testable predictions on the role of spike-based representations and temporal dynamics in biological stereo vision processing systems.

  14. POSSESSION, REVIEW FROM CULTURAL AND PSYCHIATRY

    Directory of Open Access Journals (Sweden)

    Ni Ketut Sri Diniari

    2013-03-01

    Full Text Available Possession is a culture related syndrome, commonly found in Indonesia including Bali. We can see this event in religion and cultural ceremony and at other times at school, home, and in society. This syndrome consist of temporary loss of self identification and environment awareness; in several events a person acts as if he/she was controlled by other being, magic force, spirit or ‘other forces’. There are still several different opinions about trance-possession, whether it is related to certain culture or is a part of mental disorder. DSM-IV-TR and PPDGJ-III defined trance-possession as mental disorder (dissociative for involuntary possession, if it is not a common activity, and if it is not a part of religion or cultural event. (MEDICINA 2012;43:37-40.

  15. On topological spaces possessing uniformly distributed sequences

    CERN Document Server

    Bogachev, V I

    2007-01-01

    Two classes of topological spaces are introduced on which every probability Radon measure possesses a uniformly distributed sequence or a uniformly tight uniformly distributed sequence. It is shown that these classes are stable under multiplication by completely regular Souslin spaces

  16. Subself theory and reincarnation/possession.

    Science.gov (United States)

    Lester, David

    2004-12-01

    A subself model of the mind is used to account for multiple personality, possession, the spirit controls of mediums, reincarnation, and the auditory hallucinations of schizophrenics, with suggestions for empirical research.

  17. Exorcism and possession in psychotherapy practice.

    Science.gov (United States)

    Henderson, J

    1982-03-01

    There has been an evolution in the layman's concept of mental disorder. Medieval belief in possession by demons and witches gave way to a 19th century medical model and more recently classical psychoanalytic formulations. Concurrently professional helping endeavor has moved increasingly from a more traditionally medical to psychotherapeutic process, and from a classical psychotherapeutic process wherein the therapist remained to a degree unresponsive and detached to a more modern emphasis on such qualities as empathy, sensitivity, reliability, and optimism as ingredients of successful psychotherapeutic practice. Freud's account of Haizmann's demonological neurosis usefully formulates the possession concept in psychological terms. However, recent developments in psychotherapeutic practice argue for a validity in the possession model of psychological distress. The possessing forces of object relations psychology are of course not the possessing demons and witches of medieval times but the possessing good and bad objects of early intrapsychic life set up through processes of introjection and incorporation in response to frustration in the early infant-mother relationship. Points of similarity in this comparison should not obscure features of contrast--ther is no place for histrionic manipulation nor for a moralistic attitude in the practice of psychotherapy. A case is described to illustrate these points.

  18. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  19. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  20. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  1. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  2. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  3. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  4. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  5. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  6. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  7. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  8. The Failed Image and the Possessed

    DEFF Research Database (Denmark)

    Suhr, Christian

    2015-01-01

    This article asks if the recurrent queries regarding the value of images in visual anthropology could find new answers by exploring responses to visual media in neo-orthodox Islam. It proposes that the visual display of the photographic image shares a curious resemblance to the bodies of people...... possessed by invisible spirits called jinn. The image as a failed example or model of reality works like the possessed body as an amplifier of invisibility pointing towards that which cannot be seen, depicted visually, or represented in writing. This suggests a negative epistemology in which images obtain...

  9. High Fill-Factor Imagers for Neuromorphic Processing Enabled by Floating-Gate Circuits

    Directory of Open Access Journals (Sweden)

    Hasler Paul

    2003-01-01

    Full Text Available In neuromorphic modeling of the retina, it would be very nice to have processing capabilities at the focal plane while retaining the density of typical active pixel sensor (APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our transform imager technology and basic architecture that uses analog floating-gate devices to make it possible to have computational imagers with high pixel densities. This imager approach allows programmable focal-plane processing that can perform retinal and higher-level bioinspired computation. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting dataflow architecture can directly perform computation of spatial transforms, motion computations, and stereo computations. The core imager performs computations at the pixel plane, but still holds a fill factor greater than 40 percent—comparable to the high fill factors of APS imagers. Each pixel is composed of a photodiode sensor element and a multiplier. We present experimental results from several imager arrays built in 0.5 m process (up to in an area of 4 millimeter squared.

  10. Adaptive gain control for spike-based map communication in a neuromorphic vision system.

    Science.gov (United States)

    Meng, Yicong; Shi, Bertram E

    2008-06-01

    To support large numbers of model neurons, neuromorphic vision systems are increasingly adopting a distributed architecture, where different arrays of neurons are located on different chips or processors. Spike-based protocols are used to communicate activity between processors. The spike activity in the arrays depends on the input statistics as well as internal parameters such as time constants and gains. In this paper, we investigate strategies for automatically adapting these parameters to maintain a constant firing rate in response to changes in the input statistics. We find that under the constraint of maintaining a fixed firing rate, a strategy based upon updating the gain alone performs as well as an optimal strategy where both the gain and the time constant are allowed to vary. We discuss how to choose the time constant and propose an adaptive gain control mechanism whose operation is robust to changes in the input statistics. Our experimental results on a mobile robotic platform validate the analysis and efficacy of the proposed strategy.

  11. Quasiperiodic AlGaAs superlattices for neuromorphic networks and nonlinear control systems

    Energy Technology Data Exchange (ETDEWEB)

    Malyshev, K. V., E-mail: malyshev@bmstu.ru [Electronics and Laser Technology Department, Bauman Moscow State Technical University, Moscow 105005 (Russian Federation)

    2015-01-28

    The application of quasiperiodic AlGaAs superlattices as a nonlinear element of the FitzHugh–Nagumo neuromorphic network is proposed and theoretically investigated on the example of Fibonacci and figurate superlattices. The sequences of symbols for the figurate superlattices were produced by decomposition of the Fibonacci superlattices' symbolic sequences. A length of each segment of the decomposition was equal to the corresponding figurate number. It is shown that a nonlinear network based upon Fibonacci and figurate superlattices provides better parallel filtration of a half-tone picture; then, a network based upon traditional diodes which have cubic voltage-current characteristics. It was found that the figurate superlattice F{sup 0}{sub 11}(1) as a nonlinear network's element provides the filtration error almost twice less than the conventional “cubic” diode. These advantages are explained by a wavelike shape of the decreasing part of the quasiperiodic superlattice's voltage-current characteristic, which leads to multistability of the network's cell. This multistability promises new interesting nonlinear dynamical phenomena. A variety of wavy forms of voltage-current characteristics opens up new interesting possibilities for quasiperiodic superlattices and especially for figurate superlattices in many areas—from nervous system modeling to nonlinear control systems development.

  12. Spin-neurons: A possible path to energy-efficient neuromorphic computers

    Energy Technology Data Exchange (ETDEWEB)

    Sharad, Mrigank; Fan, Deliang; Roy, Kaushik [School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907 (United States)

    2013-12-21

    Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices. Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and “thresholding” operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that “spin-neurons” (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.

  13. Neuromorphic control of stepping pattern generation: a dynamic model with analog circuit implementation.

    Science.gov (United States)

    Yang, Zhijun; Cameron, Katherine; Lewinger, William; Webb, Barbara; Murray, Alan

    2012-03-01

    Animals such as stick insects can adaptively walk on complex terrains by dynamically adjusting their stepping motion patterns. Inspired by the coupled Matsuoka and resonate-and-fire neuron models, we present a nonlinear oscillation model as the neuromorphic central pattern generator (CPG) for rhythmic stepping pattern generation. This dynamic model can also be used to actuate the motoneurons on a leg joint with adjustable driving frequencies and duty cycles by changing a few of the model parameters while operating such that different stepping patterns can be generated. A novel mixed-signal integrated circuit design of this dynamic model is subsequently implemented, which, although simplified, shares the equivalent output performance in terms of the adjustable frequency and duty cycle. Three identical CPG models being used to drive three joints can make an arthropod leg of three degrees of freedom. With appropriate initial circuit parameter settings, and thus suitable phase lags among joints, the leg is expected to walk on a complex terrain with adaptive steps. The adaptation is associated with the circuit parameters mediated both by the higher level nervous system and the lower level sensory signals. The model is realized using a 0.3- complementary metal-oxide-semiconductor process and the results are reported.

  14. Spin-neurons: A possible path to energy-efficient neuromorphic computers

    Science.gov (United States)

    Sharad, Mrigank; Fan, Deliang; Roy, Kaushik

    2013-12-01

    Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices. Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and "thresholding" operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that "spin-neurons" (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.

  15. Real-time classification of datasets with hardware embedded neuromorphic neural networks.

    Science.gov (United States)

    Bako, Laszlo

    2010-05-01

    Neuromorphic artificial neural networks attempt to understand the essential computations that take place in the dense networks of interconnected neurons making up the central nervous systems in living creatures. This article demonstrates that artificial spiking neural networks--built to resemble the biological model--encoding information in the timing of single spikes, are capable of computing and learning clusters from realistic data. It shows how a spiking neural network based on spike-time coding can successfully perform unsupervised and supervised clustering on real-world data. A temporal encoding procedure of continuously valued data is developed, together with a hardware implementation oriented new learning rule set. Solutions that make use of embedded soft-core microcontrollers are investigated, to implement some of the most resource-consuming components of the artificial neural network. Details of the implementations are given, with benchmark application evaluation and test bench description. Measurement results are presented, showing real-time and adaptive data processing capabilities, comparing these to related findings in the specific literature.

  16. Quasiperiodic AlGaAs superlattices for neuromorphic networks and nonlinear control systems

    Science.gov (United States)

    Malyshev, K. V.

    2015-01-01

    The application of quasiperiodic AlGaAs superlattices as a nonlinear element of the FitzHugh-Nagumo neuromorphic network is proposed and theoretically investigated on the example of Fibonacci and figurate superlattices. The sequences of symbols for the figurate superlattices were produced by decomposition of the Fibonacci superlattices' symbolic sequences. A length of each segment of the decomposition was equal to the corresponding figurate number. It is shown that a nonlinear network based upon Fibonacci and figurate superlattices provides better parallel filtration of a half-tone picture; then, a network based upon traditional diodes which have cubic voltage-current characteristics. It was found that the figurate superlattice F011(1) as a nonlinear network's element provides the filtration error almost twice less than the conventional "cubic" diode. These advantages are explained by a wavelike shape of the decreasing part of the quasiperiodic superlattice's voltage-current characteristic, which leads to multistability of the network's cell. This multistability promises new interesting nonlinear dynamical phenomena. A variety of wavy forms of voltage-current characteristics opens up new interesting possibilities for quasiperiodic superlattices and especially for figurate superlattices in many areas—from nervous system modeling to nonlinear control systems development.

  17. A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems.

    Science.gov (United States)

    Wang, Zhongqiang; Ambrogio, Stefano; Balatti, Simone; Ielmini, Daniele

    2014-01-01

    Resistive (or memristive) switching devices based on metal oxides find applications in memory, logic and neuromorphic computing systems. Their small area, low power operation, and high functionality meet the challenges of brain-inspired computing aiming at achieving a huge density of active connections (synapses) with low operation power. This work presents a new artificial synapse scheme, consisting of a memristive switch connected to 2 transistors responsible for gating the communication and learning operations. Spike timing dependent plasticity (STDP) is achieved through appropriate shaping of the pre-synaptic and the post synaptic spikes. Experiments with integrated artificial synapses demonstrate STDP with stochastic behavior due to (i) the natural variability of set/reset processes in the nanoscale switch, and (ii) the different response of the switch to a given stimulus depending on the initial state. Experimental results are confirmed by model-based simulations of the memristive switching. Finally, system-level simulations of a 2-layer neural network and a simplified STDP model show random learning and recognition of patterns.

  18. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  19. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  20. POSSESSION VERSUS POSITION: STRATEGIC EVALUATION IN AFL

    Directory of Open Access Journals (Sweden)

    Darren M. O'Shaughnessy

    2006-12-01

    Full Text Available In sports like Australian Rules football and soccer, teams must battle to achieve possession of the ball in sufficient space to make optimal use of it. Ultimately the teams need to score, and to do that the ball must be brought into the area in front of goal - the place where the defence usually concentrates on shutting down space and opportunity time. Coaches would like to quantify the trade-offs between contested play in good positions and uncontested play in less promising positions, in order to inform their decision-making about where to put their players, and when to gamble on sending the ball to a contest rather than simply maintain possession. To evaluate football strategies, Champion Data has collected the on-ground locations of all 350,000 possessions and stoppages in the past two seasons of AFL (2004, 2005. By following each chain of play through to the next score, we can now reliably estimate the scoreboard "equity" of possessing the ball at any location, and measure the effect of having sufficient time to dispose of it effectively. As expected, winning the ball under physical pressure (through a "hard ball get" is far more difficult to convert into a score than winning it via a mark. We also analyse some equity gradients to show how getting the ball 20 metres closer to goal is much more important in certain areas of the ground than in others. We conclude by looking at the choices faced by players in possession wanting to maximise their likelihood of success

  1. Partial differential equations possessing Frobenius integrable decompositions

    Energy Technology Data Exchange (ETDEWEB)

    Ma, Wen-Xiu [Department of Mathematics, University of South Florida, Tampa, FL 33620-5700 (United States)]. E-mail: mawx@cas.usf.edu; Wu, Hongyou [Department of Mathematical Sciences, Northern Illinois University, DeKalb, IL 60115-2888 (United States)]. E-mail: wu@math.niu.edu; He, Jingsong [Department of Mathematics, University of Science and Technology of China, Hefei, Anhui 230026 (China)]. E-mail: jshe@ustc.edu.cn

    2007-04-16

    Frobenius integrable decompositions are introduced for partial differential equations. A procedure is provided for determining a class of partial differential equations of polynomial type, which possess specified Frobenius integrable decompositions. Two concrete examples with logarithmic derivative Baecklund transformations are given, and the presented partial differential equations are transformed into Frobenius integrable ordinary differential equations with cubic nonlinearity. The resulting solutions are illustrated to describe the solution phenomena shared with the KdV and potential KdV equations.

  2. A neuromorphic model of motor overflow in focal hand dystonia due to correlated sensory input

    Science.gov (United States)

    Sohn, Won Joon; Niu, Chuanxin M.; Sanger, Terence D.

    2016-10-01

    Objective. Motor overflow is a common and frustrating symptom of dystonia, manifested as unintentional muscle contraction that occurs during an intended voluntary movement. Although it is suspected that motor overflow is due to cortical disorganization in some types of dystonia (e.g. focal hand dystonia), it remains elusive which mechanisms could initiate and, more importantly, perpetuate motor overflow. We hypothesize that distinct motor elements have low risk of motor overflow if their sensory inputs remain statistically independent. But when provided with correlated sensory inputs, pre-existing crosstalk among sensory projections will grow under spike-timing-dependent-plasticity (STDP) and eventually produce irreversible motor overflow. Approach. We emulated a simplified neuromuscular system comprising two anatomically distinct digital muscles innervated by two layers of spiking neurons with STDP. The synaptic connections between layers included crosstalk connections. The input neurons received either independent or correlated sensory drive during 4 days of continuous excitation. The emulation is critically enabled and accelerated by our neuromorphic hardware created in previous work. Main results. When driven by correlated sensory inputs, the crosstalk synapses gained weight and produced prominent motor overflow; the growth of crosstalk synapses resulted in enlarged sensory representation reflecting cortical reorganization. The overflow failed to recede when the inputs resumed their original uncorrelated statistics. In the control group, no motor overflow was observed. Significance. Although our model is a highly simplified and limited representation of the human sensorimotor system, it allows us to explain how correlated sensory input to anatomically distinct muscles is by itself sufficient to cause persistent and irreversible motor overflow. Further studies are needed to locate the source of correlation in sensory input.

  3. Reward-based learning under hardware constraints - Using a RISC processor embedded in a neuromorphic substrate

    Directory of Open Access Journals (Sweden)

    Simon eFriedmann

    2013-09-01

    Full Text Available In this study, we propose and analyze in simulations a new, highly flexible method of imple-menting synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. Thestudy focuses on globally modulated STDP, as a special use-case of this method. Flexibility isachieved by embedding a general-purpose processor dedicated to plasticity into the wafer. Toevaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spiketrain learning task. A single layer of neurons is trained to fire at specific points in time withonly the reward as feedback. This model is simulated to measure its performance, i.e. the in-crease in received reward after learning. Using this performance as baseline, we then simulatethe model with various constraints imposed by the proposed implementation and compare theperformance. The simulated constraints include discretized synaptic weights, a restricted inter-face between analog synapses and embedded processor, and mismatch of analog circuits. Wefind that probabilistic updates can increase the performance of low-resolution weights, a simpleinterface between analog synapses and processor is sufficient for learning, and performance isinsensitive to mismatch. Further, we consider communication latency between wafer and theconventional control computer system that is simulating the environment. This latency increasesthe delay, with which the reward is sent to the embedded processor. Because of the time continu-ous operation of the analog synapses, delay can cause a deviation of the updates as compared tothe not delayed situation. We find that for highly accelerated systems latency has to be kept to aminimum. This study demonstrates the suitability of the proposed implementation to emulatethe selected reward modulated STDP learning rule. It is therefore an ideal candidate for imple-mentation in an upgraded version of the wafer-scale system developed within the BrainScaleSproject.

  4. Neural Mechanisms of Cortical Motion Computation Based on a Neuromorphic Sensory System.

    Directory of Open Access Journals (Sweden)

    Luma Issa Abdul-Kreem

    Full Text Available The visual cortex analyzes motion information along hierarchically arranged visual areas that interact through bidirectional interconnections. This work suggests a bio-inspired visual model focusing on the interactions of the cortical areas in which a new mechanism of feedforward and feedback processing are introduced. The model uses a neuromorphic vision sensor (silicon retina that simulates the spike-generation functionality of the biological retina. Our model takes into account two main model visual areas, namely V1 and MT, with different feature selectivities. The initial motion is estimated in model area V1 using spatiotemporal filters to locally detect the direction of motion. Here, we adapt the filtering scheme originally suggested by Adelson and Bergen to make it consistent with the spike representation of the DVS. The responses of area V1 are weighted and pooled by area MT cells which are selective to different velocities, i.e. direction and speed. Such feature selectivity is here derived from compositions of activities in the spatio-temporal domain and integrating over larger space-time regions (receptive fields. In order to account for the bidirectional coupling of cortical areas we match properties of the feature selectivity in both areas for feedback processing. For such linkage we integrate the responses over different speeds along a particular preferred direction. Normalization of activities is carried out over the spatial as well as the feature domains to balance the activities of individual neurons in model areas V1 and MT. Our model was tested using different stimuli that moved in different directions. The results reveal that the error margin between the estimated motion and synthetic ground truth is decreased in area MT comparing with the initial estimation of area V1. In addition, the modulated V1 cell activations shows an enhancement of the initial motion estimation that is steered by feedback signals from MT cells.

  5. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  6. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  7. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  8. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  9. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  10. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  11. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  12. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  13. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  14. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  15. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  16. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  17. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  18. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  19. A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks

    Science.gov (United States)

    Wang, Runchun M.; Hamilton, Tara J.; Tapson, Jonathan C.; van Schaik, André

    2015-01-01

    We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 226 (64M) synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted or delayed pre-synaptic spike to the post-synaptic neuron in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 236 (64G) synaptic adaptors on a current high-end FPGA platform. PMID:26041985

  20. A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing

    Science.gov (United States)

    van de Burgt, Yoeri; Lubberman, Ewout; Fuller, Elliot J.; Keene, Scott T.; Faria, Grégorio C.; Agarwal, Sapan; Marinella, Matthew J.; Alec Talin, A.; Salleo, Alberto

    2017-04-01

    The brain is capable of massively parallel information processing while consuming only ~1-100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. Here we describe an electrochemical neuromorphic organic device (ENODe) operating with a fundamentally different mechanism from existing memristors. ENODe switches at low voltage and energy (500 distinct, non-volatile conductance states within a ~1 V range, and achieves high classification accuracy when implemented in neural network simulations. Plastic ENODes are also fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with three-dimensional architectures, opening a path towards extreme interconnectivity comparable to the human brain.

  1. Highly compact (4F2) and well behaved nano-pillar transistor controlled resistive switching cell for neuromorphic system application.

    Science.gov (United States)

    Chen, Bing; Wang, Xinpeng; Gao, Bin; Fang, Zheng; Kang, Jinfeng; Liu, Lifeng; Liu, Xiaoyan; Lo, Guo-Qiang; Kwong, Dim-Lee

    2014-10-31

    To simplify the architecture of a neuromorphic system, it is extremely desirable to develop synaptic cells with the capacity of low operation power, high density integration, and well controlled synaptic behaviors. In this study, we develop a resistive switching device (ReRAM)-based synaptic cell, fabricated by the CMOS compatible nano-fabrication technology. The developed synaptic cell consists of one vertical gate-all-around Si nano-pillar transistor (1T) and one transition metal-oxide based resistive switching device (1R) stacked on top of the vertical transistor directly. Thanks to the vertical architecture and excellent controllability on the ON/OFF performance of the nano-pillar transistor, the 1T1R synaptic cell shows excellent characteristics such as extremely high-density integration ability with 4F(2) footprint, ultra-low operation current (<2 nA), fast switching speed (<10 ns), multilevel data storage and controllable synaptic switching, which are extremely desirable for simplifying the architecture of neuromorphic system.

  2. A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks.

    Science.gov (United States)

    Wang, Runchun M; Hamilton, Tara J; Tapson, Jonathan C; van Schaik, André

    2015-01-01

    We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 2(26) (64M) synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted or delayed pre-synaptic spike to the post-synaptic neuron in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 2(36) (64G) synaptic adaptors on a current high-end FPGA platform.

  3. A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks

    Directory of Open Access Journals (Sweden)

    Runchun Mark Wang

    2015-05-01

    Full Text Available We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP and Spike Timing Dependent Delay Plasticity (STDDP. We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 2^26 (64M synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted and/or delayed pre-synaptic spike to the target synapse in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 2^36 (64G synaptic adaptors on a current high-end FPGA platform.

  4. Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks

    Energy Technology Data Exchange (ETDEWEB)

    Oya, Takahide [Graduate School of Information Science and Technology, Hokkaido University, Kita 14, Nishi 9, Sapporo 060-0814 (Japan)]. E-mail: oya@sapiens-ei.eng.hokudai.ac.jp; Asai, Tetsuya [Graduate School of Information Science and Technology, Hokkaido University, Kita 14, Nishi 9, Sapporo 060-0814 (Japan); Amemiya, Yoshihito [Graduate School of Information Science and Technology, Hokkaido University, Kita 14, Nishi 9, Sapporo 060-0814 (Japan)

    2007-04-15

    Neuromorphic computing based on single-electron circuit technology is gaining prominence because of its massively increased computational efficiency and the increasing relevance of computer technology and nanotechnology [Likharev K, Mayr A, Muckra I, Tuerel O. CrossNets: High-performance neuromorphic architectures for CMOL circuits. Molec Electron III: Ann NY Acad Sci 1006;2003:146-63; Oya T, Schmid A, Asai T, Leblebici Y, Amemiya Y. On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron Expr 2;2005:76-80]. The maximum impact of these technologies will be strongly felt when single-electron circuits based on fault- and noise-tolerant neural structures can operate at room temperature. In this paper, inspired by stochastic resonance (SR) in an ensemble of spiking neurons [Collins JJ, Chow CC, Imhoff TT. Stochastic resonance without tuning. Nature 1995;376:236-8], we propose our design of a basic single-electron neural component and report how we examined its statistical results on a network.

  5. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  6. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  7. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  8. VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality.

    Science.gov (United States)

    Scholze, Stefan; Schiefer, Stefan; Partzsch, Johannes; Hartmann, Stephan; Mayr, Christian Georg; Höppner, Sebastian; Eisenreich, Holger; Henker, Stephan; Vogginger, Bernhard; Schüffny, Rene

    2011-01-01

    State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic communication infrastructures.

  9. Real-Time Biologically Inspired Action Recognition from Key Poses Using a Neuromorphic Architecture.

    Science.gov (United States)

    Layher, Georg; Brosch, Tobias; Neumann, Heiko

    2017-01-01

    Intelligent agents, such as robots, have to serve a multitude of autonomous functions. Examples are, e.g., collision avoidance, navigation and route planning, active sensing of its environment, or the interaction and non-verbal communication with people in the extended reach space. Here, we focus on the recognition of the action of a human agent based on a biologically inspired visual architecture of analyzing articulated movements. The proposed processing architecture builds upon coarsely segregated streams of sensory processing along different pathways which separately process form and motion information (Layher et al., 2014). Action recognition is performed in an event-based scheme by identifying representations of characteristic pose configurations (key poses) in an image sequence. In line with perceptual studies, key poses are selected unsupervised utilizing a feature-driven criterion which combines extrema in the motion energy with the horizontal and the vertical extendedness of a body shape. Per class representations of key pose frames are learned using a deep convolutional neural network consisting of 15 convolutional layers. The network is trained using the energy-efficient deep neuromorphic networks (Eedn) framework (Esser et al., 2016), which realizes the mapping of the trained synaptic weights onto the IBM Neurosynaptic System platform (Merolla et al., 2014). After the mapping, the trained network achieves real-time capabilities for processing input streams and classify input images at about 1,000 frames per second while the computational stages only consume about 70 mW of energy (without spike transduction). Particularly regarding mobile robotic systems, a low energy profile might be crucial in a variety of application scenarios. Cross-validation results are reported for two different datasets and compared to state-of-the-art action recognition approaches. The results demonstrate, that (I) the presented approach is on par with other key pose based

  10. Real-Time Biologically Inspired Action Recognition from Key Poses Using a Neuromorphic Architecture

    Science.gov (United States)

    Layher, Georg; Brosch, Tobias; Neumann, Heiko

    2017-01-01

    Intelligent agents, such as robots, have to serve a multitude of autonomous functions. Examples are, e.g., collision avoidance, navigation and route planning, active sensing of its environment, or the interaction and non-verbal communication with people in the extended reach space. Here, we focus on the recognition of the action of a human agent based on a biologically inspired visual architecture of analyzing articulated movements. The proposed processing architecture builds upon coarsely segregated streams of sensory processing along different pathways which separately process form and motion information (Layher et al., 2014). Action recognition is performed in an event-based scheme by identifying representations of characteristic pose configurations (key poses) in an image sequence. In line with perceptual studies, key poses are selected unsupervised utilizing a feature-driven criterion which combines extrema in the motion energy with the horizontal and the vertical extendedness of a body shape. Per class representations of key pose frames are learned using a deep convolutional neural network consisting of 15 convolutional layers. The network is trained using the energy-efficient deep neuromorphic networks (Eedn) framework (Esser et al., 2016), which realizes the mapping of the trained synaptic weights onto the IBM Neurosynaptic System platform (Merolla et al., 2014). After the mapping, the trained network achieves real-time capabilities for processing input streams and classify input images at about 1,000 frames per second while the computational stages only consume about 70 mW of energy (without spike transduction). Particularly regarding mobile robotic systems, a low energy profile might be crucial in a variety of application scenarios. Cross-validation results are reported for two different datasets and compared to state-of-the-art action recognition approaches. The results demonstrate, that (I) the presented approach is on par with other key pose based

  11. Predicative possession in Medieval Slavic Bible translations Predicative Possession in Early Biblical Slavic

    Directory of Open Access Journals (Sweden)

    Julia McAnallen

    2011-08-01

    Full Text Available Late Proto-Slavic (LPS had an inventory of three constructions for expressing predicative possession. Using the earliest Slavic Bible translations from Old Church Slavic (OCS, and to a lesser degree Old Czech, a number of conclusions can be drawn about the status of predicative possession for LPS. The verb iměti ‘have’ was the most frequent and least syntactically and semantically restricted predicative possessive construction (PPC. Existential PPCs with a dative possessor appear primarily with kinship relations, abstract possessums, and in a number of other fixed construction types; existential PPCs with the possessor in an u + genitive prepositional phrase primarily appear with concrete and countable possessums. Both existential PPCs call for an animate, most often pronominal, possessor. The u + genitive was the rarest type of PPC in LPS, though it had undoubtedly grammaticalized as a PPC.

  12. 50 CFR 20.38 - Possession of live birds.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 6 2010-10-01 2010-10-01 false Possession of live birds. 20.38 Section 20... WILDLIFE AND PLANTS (CONTINUED) MIGRATORY BIRD HUNTING Possession § 20.38 Possession of live birds. Every migratory game bird wounded by hunting and reduced to possession by the hunter shall be immediately...

  13. Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

    Science.gov (United States)

    Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

    2016-12-21

    One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

  14. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  15. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  16. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  17. Sound stream segregation: a neuromorphic approach to solve the ‘cocktail party problem’ in real-time

    Directory of Open Access Journals (Sweden)

    Chetan Singh Thakur

    2015-09-01

    Full Text Available The human auditory system has the ability to segregate complex auditory scenes into a foreground component and a background, allowing us to listen to specific speech sounds from a mixture of sounds. Selective attention plays a crucial role in this process, colloquially known as the ‘cocktail party effect’. It has not been possible to build a machine that can emulate this human ability in real-time. Here, we have developed a framework for the implementation of a neuromorphic sound segregation algorithm in a Field Programmable Gate Array (FPGA. This algorithm is based on the principles of temporal coherence and uses an attention signal to separate a target sound stream from background noise. Temporal coherence implies that auditory features belonging to the same sound source are coherently modulated and evoke highly correlated neural response patterns. The basis for this form of sound segregation is that responses from pairs of channels that are strongly positively correlated belong to the same stream, while channels that are uncorrelated or anti-correlated belong to different streams. In our framework, we have used a neuromorphic cochlea as a frontend sound analyser to extract spatial information of the sound input, which then passes through band pass filters that extract the sound envelope at various modulation rates. Further stages include feature extraction and mask generation, which is finally used to reconstruct the targeted sound. Using sample tonal and speech mixtures, we show that our FPGA architecture is able to segregate sound sources in real-time. The accuracy of segregation is indicated by the high signal-to-noise ratio (SNR of the segregated stream (90, 77 and 55 dB for simple tone, complex tone and speech, respectively as compared to the SNR of the mixture waveform (0 dB. This system may be easily extended for the segregation of complex speech signals, and may thus find various applications in electronic devices such as for

  18. Evolving spatio-temporal data machines based on the NeuCube neuromorphic framework: Design methodology and selected applications.

    Science.gov (United States)

    Kasabov, Nikola; Scott, Nathan Matthew; Tu, Enmei; Marks, Stefan; Sengupta, Neelava; Capecci, Elisa; Othman, Muhaini; Doborjeh, Maryam Gholami; Murli, Norhanifah; Hartono, Reggio; Espinosa-Ramos, Josafath Israel; Zhou, Lei; Alvi, Fahad Bashir; Wang, Grace; Taylor, Denise; Feigin, Valery; Gulyaev, Sergei; Mahmoud, Mahmoud; Hou, Zeng-Guang; Yang, Jie

    2016-06-01

    The paper describes a new type of evolving connectionist systems (ECOS) called evolving spatio-temporal data machines based on neuromorphic, brain-like information processing principles (eSTDM). These are multi-modular computer systems designed to deal with large and fast spatio/spectro temporal data using spiking neural networks (SNN) as major processing modules. ECOS and eSTDM in particular can learn incrementally from data streams, can include 'on the fly' new input variables, new output class labels or regression outputs, can continuously adapt their structure and functionality, can be visualised and interpreted for new knowledge discovery and for a better understanding of the data and the processes that generated it. eSTDM can be used for early event prediction due to the ability of the SNN to spike early, before whole input vectors (they were trained on) are presented. A framework for building eSTDM called NeuCube along with a design methodology for building eSTDM using this is presented. The implementation of this framework in MATLAB, Java, and PyNN (Python) is presented. The latter facilitates the use of neuromorphic hardware platforms to run the eSTDM. Selected examples are given of eSTDM for pattern recognition and early event prediction on EEG data, fMRI data, multisensory seismic data, ecological data, climate data, audio-visual data. Future directions are discussed, including extension of the NeuCube framework for building neurogenetic eSTDM and also new applications of eSTDM.

  19. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  20. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  1. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  2. New Metric Based Algorithm for Test Vector Generation in VLSI Testing

    Directory of Open Access Journals (Sweden)

    M. V. Atre

    1995-07-01

    Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.

  3. Spike-based VLSI modeling of the ILD system in the echolocating bat.

    Science.gov (United States)

    Horiuchi, T; Hynna, K

    2001-01-01

    The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.

  4. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  5. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  6. Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.

    Science.gov (United States)

    1984-10-01

    analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI

  7. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  8. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  9. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  10. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  11. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind; El cerebro humano en un ordenador

    Energy Technology Data Exchange (ETDEWEB)

    Pajuelo, L.

    2015-07-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  12. 20 CFR 404.1093 - Possession of the United States.

    Science.gov (United States)

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Possession of the United States. 404.1093... Income § 404.1093 Possession of the United States. In using the exclusions from gross income provided under section 931 of the Code (relating to income from sources within possessions of the United...

  13. 31 CFR 0.215 - Possession of weapons and explosives.

    Science.gov (United States)

    2010-07-01

    ... 31 Money and Finance: Treasury 1 2010-07-01 2010-07-01 false Possession of weapons and explosives... OF THE TREASURY EMPLOYEE RULES OF CONDUCT Rules of Conduct § 0.215 Possession of weapons and explosives. (a) Employees shall not possess firearms, explosives, or other dangerous or deadly weapons...

  14. 50 CFR 20.39 - Termination of possession.

    Science.gov (United States)

    2010-10-01

    ... WILDLIFE AND PLANTS (CONTINUED) MIGRATORY BIRD HUNTING Possession § 20.39 Termination of possession. Subject to all other requirements of this part, the possession of birds taken by any hunter shall be... consigned for transport by the Postal Service or a common carrier to some person other than the hunter. ...

  15. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  16. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  17. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  18. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  19. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  20. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  1. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  2. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  3. The digi-neocognitron: a digital neocognitron neural network model for VLSI.

    Science.gov (United States)

    White, B A; Elmasry, M I

    1992-01-01

    One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

  4. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  5. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  6. Dissociative trance and spirit possession: Challenges for cultures in transition.

    Science.gov (United States)

    Bhavsar, Vishal; Ventriglio, Antonio; Bhugra, Dinesh

    2016-12-01

    The cross-cultural validity of dissociative possession and trance disorders is a matter of some debate, limiting research and meaningful interpretation of prevalence data. Intimate to these concerns is the status of spirit possession categories studied in the social sciences, particularly anthropology. These two categories are phenomenologically related and display similar epidemiological associations. In India, dissociative and conversion disorders are fairly common in clinical settings. There is no doubt that there are true cultural variations in possession and trance disorders. A new framework may enable clinicians to better understand possession states and spirit possession. © 2016 The Authors. Psychiatry and Clinical Neurosciences © 2016 Japanese Society of Psychiatry and Neurology.

  7. Comparing Neuromorphic Solutions in Action: Implementing a Bio-Inspired Solution to a Benchmark Classification Task on Three Parallel-Computing Platforms.

    Science.gov (United States)

    Diamond, Alan; Nowotny, Thomas; Schmuker, Michael

    2015-01-01

    Neuromorphic computing employs models of neuronal circuits to solve computing problems. Neuromorphic hardware systems are now becoming more widely available and "neuromorphic algorithms" are being developed. As they are maturing toward deployment in general research environments, it becomes important to assess and compare them in the context of the applications they are meant to solve. This should encompass not just task performance, but also ease of implementation, speed of processing, scalability, and power efficiency. Here, we report our practical experience of implementing a bio-inspired, spiking network for multivariate classification on three different platforms: the hybrid digital/analog Spikey system, the digital spike-based SpiNNaker system, and GeNN, a meta-compiler for parallel GPU hardware. We assess performance using a standard hand-written digit classification task. We found that whilst a different implementation approach was required for each platform, classification performances remained in line. This suggests that all three implementations were able to exercise the model's ability to solve the task rather than exposing inherent platform limits, although differences emerged when capacity was approached. With respect to execution speed and power consumption, we found that for each platform a large fraction of the computing time was spent outside of the neuromorphic device, on the host machine. Time was spent in a range of combinations of preparing the model, encoding suitable input spiking data, shifting data, and decoding spike-encoded results. This is also where a large proportion of the total power was consumed, most markedly for the SpiNNaker and Spikey systems. We conclude that the simulation efficiency advantage of the assessed specialized hardware systems is easily lost in excessive host-device communication, or non-neuronal parts of the computation. These results emphasize the need to optimize the host-device communication architecture for

  8. Comparing neuromorphic solutions in action: implementing a bio-inspired solution to a benchmark classification task on three parallel-computing platforms

    Directory of Open Access Journals (Sweden)

    Alan eDiamond

    2016-01-01

    Full Text Available Neuromorphic computing employs models of neuronal circuits to solve computing problems. Neuromorphic hardware systems are now becoming more widely available and neuromorphic algorithms are being developed. As they are maturing towards deployment in general research environments, it becomes important to assess and compare them in the context of the applications they are meant to solve. This should encompass not just task performance, but also ease of implementation, speed of processing, scalability and power efficiency.Here, we report our practical experience of implementing a bio-inspired, spiking network for multivariate classification on three different platforms: the hybrid digital/analogue Spikey system, the digital spike-based SpiNNaker system, and GeNN, a meta-compiler for parallel GPU hardware. We assess performance using a standard hand-written digit classification task.We found that whilst a different implementation approach was required for each platform, classification performances remained in line. This suggests that all three implementations were able to exercise the model’s ability to solve the task rather than exposing inherent platform limits, although differences emerged when capacity was approached.With respect to execution speed and power consumption, we found that for each platform a large fraction of the computing time was spent outside of the neuromorphic device, on the host machine. Time was spent in a range of combinations of preparing the model, encoding suitable input spiking data, shifting data and decoding spike-encoded results. This is also where a large proportion of the total power was consumed, most markedly for the SpiNNaker and Spikey systems. We conclude that the simulation efficiency advantage of the assessed specialized hardware systems is easily lost in excessive host-device communication, or non-neuronal parts of the computation. These results emphasize the need to optimize the host-device communication

  9. Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

    Science.gov (United States)

    Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

    2012-01-01

    Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

  10. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

  11. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  12. VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.

    Science.gov (United States)

    Hoang, Linh; Yang, Zhi; Liu, Wentai

    2009-01-01

    An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.

  13. VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.

    Science.gov (United States)

    Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V

    2007-03-01

    A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

  14. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  15. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  16. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  17. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  18. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  19. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  20. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  1. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  2. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  3. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  4. Real-time motion detection using an analog VLSI zero-crossing chip

    Science.gov (United States)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  5. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  6. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    Science.gov (United States)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  7. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  8. Analyzing VLSI component test results of a GenRad GR125 tester

    Science.gov (United States)

    Zulaica, D.; Lee, C.-H.

    1995-06-01

    The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.

  9. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  10. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  11. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    Science.gov (United States)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  12. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  13. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  14. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  15. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  16. VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

    Science.gov (United States)

    Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

    2014-01-01

    Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

  17. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  18. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  19. Pre-Posed Possessive Constructions in Russian and Polish

    Science.gov (United States)

    Houle, Erik Richard

    2013-01-01

    In Contemporary Standard Russian (CSR) and Contemporary Standard Polish (CSP) nominal possession is conveyed by means of the adnominal genitive. In this construction the dependent follows the noun it modifies and is marked morphologically for possession in the genitive case. The head noun is marked morphologically for any one of the six…

  20. The Relationship between Social Capital and Weapon Possession on Campus

    Science.gov (United States)

    Messer, Rachel H.; Bradley, Kristopher I.; Calvi, Jessica L.; Kennison, Shelia M.

    2012-01-01

    The present research focused on the problem of how college officials might be able to predict weapon possession on college campuses. We hypothesized that measures of social capital (i.e., trust and participation in society) may be useful in identifying individuals who are likely to possess weapons on campuses. Prior research has shown that those…

  1. The Meaning of Cherished Personal Possessions for the Elderly

    Science.gov (United States)

    Sherman, Edmund; Newman, Evelyn S.

    1977-01-01

    In this exploratory study, 94 elderly persons, in seven senior service centers and one nursing home, were interviewed to identify and ascertain the meaning of cherished possessions in later years. Lack of cherished possessions was associated with low life satisfaction scores, a suggested indicator of poor adjustment to old age. (Author)

  2. 19 CFR 123.62 - Baggage in possession of traveler.

    Science.gov (United States)

    2010-04-01

    ... 19 Customs Duties 1 2010-04-01 2010-04-01 false Baggage in possession of traveler. 123.62 Section 123.62 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF HOMELAND SECURITY; DEPARTMENT... traveler. For baggage arriving in the actual possession of a traveler, his declaration shall be accepted in...

  3. A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-12-07

    A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

  4. High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug

    2006-07-24

    Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

  5. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  6. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    Science.gov (United States)

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-04

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.

  7. A Methodology for Mapping and Partitioning Arbitrary N—Dimensional Nested Loops into 2—Dimensional VLSI Arrays

    Institute of Scientific and Technical Information of China (English)

    刘弘; 王文红; 等

    1993-01-01

    A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.

  8. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  9. VLSI implementation of a bio-inspired olfactory spiking neural network.

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2012-07-01

    This paper presents a low-power, neuromorphic spiking neural network (SNN) chip that can be integrated in an electronic nose system to classify odor. The proposed SNN takes advantage of sub-threshold oscillation and onset-latency representation to reduce power consumption and chip area, providing a more distinct output for each odor input. The synaptic weights between the mitral and cortical cells are modified according to an spike-timing-dependent plasticity learning rule. During the experiment, the odor data are sampled by a commercial electronic nose (Cyranose 320) and are normalized before training and testing to ensure that the classification result is only caused by learning. Measurement results show that the circuit only consumed an average power of approximately 3.6 μW with a 1-V power supply to discriminate odor data. The SNN has either a high or low output response for a given input odor, making it easy to determine whether the circuit has made the correct decision. The measurement result of the SNN chip and some well-known algorithms (support vector machine and the K-nearest neighbor program) is compared to demonstrate the classification performance of the proposed SNN chip.The mean testing accuracy is 87.59% for the data used in this paper.

  10. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  11. VLSI Research

    Science.gov (United States)

    1984-04-01

    massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly

  12. Possession as an institute of civil law in Kosovo

    Directory of Open Access Journals (Sweden)

    Kaltrinë Haliti

    2016-03-01

    Full Text Available Social interest and main aim of this paper is to introduce a proper problematic of this institute, given that after the war in Kosovo, numerous usurpations have occurred. A vast number of related cases are pending to be solved which at first impression seem to be unimportant. However, having such cases unsolved which are deliberately categorized as proceedings of an urgent need by the legislator, frequently resulted with serious consequences as well as commission of major crimes. Today, the approach that obstruction of possession is a factual power over an item prevails, which provides a legal contribution pursuant to law and enjoys civil-legal protection. A crucial legal contribution of possession is its court protection in case of obstruction by unlawful self-judgment. Possession also enjoys independent protection of a right over an item. Given that possession itself is not a right whatsoever, herewith we may conclude that obstruction of possession constitutes infringement of no rights. However, should the obstruction to possession is committed violently, such possession constitutes the right’s infringement provided that every violent act is unlawful, and thus it is correctly protected by an interdict claim.

  13. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  14. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  15. Molecular Dynamics of Materials Possessing High Energy Content.

    Science.gov (United States)

    1988-01-26

    I -RI90 634 MOLECULAR DYNAMICS OF MATERIALS POSSESSING HIGH ENERGY 1/1 r CONTENTCU) COLUMBIA UNIV MENd YORK N J TURRO 26 JAN GO I RFOSR-TR-88-0168...Bolling Air Force Base, D.C. 2 61102F_ 2303 I B2 11 T,TL.E (Inciuoe Security Classification) Molecular Dynamics of Materials Possessing High Energy...York 10027 (212) 280-2175 TITLE: MOLECULAR DYNAMICS OF MATERIALS POSSESSING HIGH ENERGY CONTENT .. 0 0 88 2 ... "" ’% ,i u , . .. .. ....... ŝ" ;! ,i

  16. Must an inventor "possess" an invention to patent it?

    Science.gov (United States)

    Woessner, Warren D; Chadwick, Robin A

    2014-09-18

    The requirements for patenting inventions relating to biotechnology have become increasingly strict and complicated in recent years. Despite early patent rulings that there is no need for an inventor to "reduce to practice" an invention, the courts are now ruling that an inventor must "possess" his or her invention before filing for patent. This review discusses what such "possession" may mean and describes decisions in which courts have found that an inventor has met or failed the possession test before filing for patent protection. Copyright © 2014 Cold Spring Harbor Laboratory Press; all rights reserved.

  17. Isolation and synthesis of polyoxygenated dibenzofurans possessing biological activity.

    Science.gov (United States)

    Love, Brian E

    2015-06-01

    Reports from the past ten years describing the isolation and/or synthesis of bioactive dibenzofurans possessing three or more oxygen-containing substituents are reviewed. Dibenzofuranoquinones are included in the review.

  18. The concept possession hypothesis of self-consciousness.

    Science.gov (United States)

    Savanah, Stephane

    2012-06-01

    This paper presents the hypothesis that concept possession is sufficient and necessary for self-consciousness. If this is true it provides a yardstick for gauging the validity of different research paradigms in which claims for self-consciousness in animals or human infants are made: a convincing demonstration of concept possession in a research subject, such as a display of inferential reasoning, may be taken as conclusive evidence of self-consciousness. Intuitively, there appears to be a correlation between intelligence in animals (which presupposes concept possession) and the existence of self-consciousness. I present three discussions to support the hypothesis: an analogy between perception and conception, where both are self-specifying; an argument that any web of concepts will always include the self-concept; and a fresh interpretation of Bermũdez (1998) showing how his theory of non-conceptual content provides strong support for the concept possession hypothesis.

  19. 50 CFR 648.52 - Possession and landing limits.

    Science.gov (United States)

    2010-10-01

    ..., or possess more than 50 bu (17.6 hL) of in-shell scallops shoreward of the VMS Demarcation Line. Such....2 hL) of in-shell scallops seaward of the VMS demarcation line on a properly declared IFQ scallop... vessel may possess up to 50 bu (17.6 hL) of in-shell scallops seaward of the VMS demarcation line on...

  20. The possessions at Loudun: tracking the discourse of dissociation.

    Science.gov (United States)

    Stephenson, Craig E

    2017-09-01

    Embedded in the history of dissociation is the best known case of possession in European history, the 17(th) century possessions at Loudun, France (1632-1638). The exorcisms and the trial drew crowds from all over Europe, the outcome prefiguring the direction in which the Western science of mind would be carried. The published debate about the possessed and obsessed Ursuline nuns of Loudun spans four centuries. One can track how theorizing about dissociation changed over time, with psychological contributions by Jean Martin Charcot, Georges Gilles de la Tourette, Pierre Janet, Michel Foucault and Michel de Certeau. Freud's psychoanalytic notion of demonological neurosis emphasized defensive strategies and a diabolic parody of adulthood. Jung's concepts of demonism and possession highlighted dissociated complexes that assimilate the ego and unseat the self, rendering a life 'provisional'. Dissociation as possession provides a through-line in Jung's Collected Works, from his 1902 dissertation to one of the last essays he wrote, in 1961. Within the context of psychotherapy, therapists and patients work towards psychological containment, consciously reorienting themselves to the presence of unconscious factors, personifying, embodying and thereby incorporating images of dissociated Otherness into the experience of selfhood. © 2017, The Society of Analytical Psychology.

  1. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  2. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  3. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  4. A compact 3D VLSI classifier using bagging threshold network ensembles.

    Science.gov (United States)

    Bermak, A; Martinez, D

    2003-01-01

    A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

  5. A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.

    Science.gov (United States)

    Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

    2011-04-01

    Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.

  6. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  7. Deep sub-micron stud-via technology for superconductor VLSI circuits

    Science.gov (United States)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  8. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  9. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  10. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  11. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  12. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  13. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  14. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  15. Advances in VLSI testing at MultiGb per second rates

    Directory of Open Access Journals (Sweden)

    Topisirović Dragan

    2005-01-01

    Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

  16. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  17. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  18. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  19. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  20. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  1. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  2. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  3. Provable data possession for securing the data from untrusted server

    Directory of Open Access Journals (Sweden)

    S.Karthikeyan

    2015-03-01

    Full Text Available The model described for the use of Provable data Possession which allow the client to access the stored data at an Untrusted server that the server possesses the original data without retrieving it. This model executes the probabilistic proof of possession by random set of blocks which is derived from the server that dramatically reduces the cost of I/O. Sometimes the Client maintenance the constant amount of data which is used to verify the proof. The response protocol can transmit a small amount of data, which can minimize network communication. The two provably –Securer PDP Schemes presents more efficient schemes than previous solution .Even when compared with schemes that achieve weaker guarantees. It is the widely distributed storage systems. Using the experiment we can implement and verify the practicality of PDP and we can revel that the performance of the PDP that is bounded by disk I/O and that cannot be determined by computation.

  4. Emotional regulation, attachment to possessions and hoarding symptoms.

    Science.gov (United States)

    Phung, Philip J; Moulding, Richard; Taylor, Jasmine K; Nedeljkovic, Maja

    2015-10-01

    This study aimed to test which particular facets of emotion regulation (ER) are most linked to symptoms of hoarding disorder, and whether beliefs about emotional attachment to possessions (EA) mediate this relationship. A non-clinical sample of 150 participants (108 females) completed questionnaires of emotional tolerance (distress tolerance, anxiety sensitivity, negative urgency - impulsivity when experiencing negative emotions), depressed mood, hoarding, and beliefs about emotional attachment to possessions. While all emotional tolerance measures related to hoarding, when considered together and controlling for depression and age, anxiety sensitivity and urgency were the significant predictors. Anxiety sensitivity was fully mediated, and urgency partially mediated, via beliefs regarding emotional attachment to possessions. These findings provide further support for (1) the importance of anxiety sensitivity and negative urgency for hoarding symptoms, and (2) the view that individuals with HD symptoms may rely on items for emotion regulation, leading to stronger beliefs that items are integral to emotional wellbeing.

  5. The Relationship Between Underage Alcohol Possession and Future Criminal Behavior

    Directory of Open Access Journals (Sweden)

    Chris Barnum

    2012-01-01

    Full Text Available This study examines the relationship between underage alcohol possession and criminal behavior through a cohort, age, and period analysis. Utilizing the Age–Period Cohort Characteristic (APCC models method and national arrest data, while controlling for age and period effects, this study examined single-year age cohorts and determines that strict enforcement of PULA (Possession Under Legal Age laws decreases the likelihood of strongly correlated vandalism and assaults as young adults. The analysis indicates an increase in assaults and vandalism as cohort size increases, but little effect from single parent, resource deprivation.

  6. 32 CFR 552.128 - Requirements for possession and use.

    Science.gov (United States)

    2010-07-01

    ... RESERVATIONS AND NATIONAL CEMETERIES REGULATIONS AFFECTING MILITARY RESERVATIONS Control of Firearms, Ammunition and Other Dangerous Weapons on Fort Gordon § 552.128 Requirements for possession and use. All... installation, or after obtaining the weapon, except: (1) Firearms legally brought onto the installation for...

  7. The Feminist Thoughts Embodied in the Epics of Possession

    Institute of Scientific and Technical Information of China (English)

    吴艳玲

    2008-01-01

    In this paper,features of the feminist thoughts embodied in Possession analyzed and readers are led to a mythological world centered onthree female characters in three epics in order to state the feminist thoughys in the epics.Byatt's feminist thoughts are highlighted here.

  8. Dynamics of the spirit possession phenomenon in Eastern Tanzania

    Directory of Open Access Journals (Sweden)

    Marja-Liisa Swantz

    1976-01-01

    Full Text Available The discussion on the spirit possession phenomenon is related in this study to the more general question of the role of religious institutions as part in the development process of a people living in a limited geographical area of a wider national society. It is assumed that religion, like culture in general, has its specific institutional forms as result of the historical development of a society, but at the same time religion is a force shaping that history. People's cultural resources influence their social and economic development and form a potential creative element in it'. Some of the questions to be asked are: "How are specific religious practices related to the dynamics of change in the societies in question? What is the social and religious context in which the spirit possession phenomenon occurs in them? What social and economic relations get their expression in them? To what extent is spirit possession in this case a means of exerting values and creatively overcoming a crisis or conflict which the changing social and economic relations impose on the people? The established spirit possession cults are here seen as the institutional forms of religious experience. At the same time it becomes evident that there is institutionalization in process as well as deinstitutionalization of spirit possession where it occurs outside established institutional forms. Institution is taken as a socially shared form of behaviour the significance of which is commonly recognized by those who share it. By the term spirit possession cult is meant a ritual form of spirit possession of a group which is loosely organized and without strict membership. The context of the study is four ethnic groups in Eastern Tanzania, near the coast of the Indian Ocean. The general theme of the project is The Role of Culture in the Restructuring of Tanzanian Rural Areas. The restructuring refers to a villagisation programme carried out in the whole country. People are being

  9. Classification of correlated patterns with a configurable analog VLSI neural network of spiking neurons and self-regulating plastic synapses.

    Science.gov (United States)

    Giulioni, Massimilian; Pannunzi, Mario; Badoni, Davide; Dante, Vittorio; Del Giudice, Paolo

    2009-11-01

    We describe the implementation and illustrate the learning performance of an analog VLSI network of 32 integrate-and-fire neurons with spike-frequency adaptation and 2016 Hebbian bistable spike-driven stochastic synapses, endowed with a self-regulating plasticity mechanism, which avoids unnecessary synaptic changes. The synaptic matrix can be flexibly configured and provides both recurrent and external connectivity with address-event representation compliant devices. We demonstrate a marked improvement in the efficiency of the network in classifying correlated patterns, owing to the self-regulating mechanism.

  10. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  11. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  12. 基于GPU的VLSI的DRC加速系统%DRC Accelerated System of VLSI Based on GPU

    Institute of Scientific and Technical Information of China (English)

    池凤彬; 潘日华; 陈扉; 赵冬晖

    2007-01-01

    在超大规模集成电路(VLSI)设计流程中,设计规则检查(DRC)是关键一环.多年来,设计人员为DRC设计了许多硬件加速的方法,但是都局限于成本等诸多原因而不能得到推广.因此提出了基于GPU平台的DRC方法,大幅提高了DRC效率.

  13. Modeling latency code processing in the electric sense: from the biological template to its VLSI implementation.

    Science.gov (United States)

    Engelmann, Jacob; Walther, Tim; Grant, Kirsty; Chicca, Elisabetta; Gómez-Sena, Leonel

    2016-09-13

    electric image with high sensitivity over a broad working range. Since the network largely depends on spike timing, we finally discuss its suitability for implementation in robotic applications based on neuromorphic hardware.

  14. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  15. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  16. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  17. The Regulation of the Possession of Weapons at Gatherings

    Directory of Open Access Journals (Sweden)

    Pieter du Toit

    2013-12-01

    Full Text Available The Dangerous Weapons Act 15 of 2013 provides for certain prohibitions and restrictions in respect of the possession of a dangerous weapon and it repeals the Dangerous Weapons Act 71 of 1968 as well as the different Dangerous Weapons Acts in operation in the erstwhile TBVC States. The Act also amends the Regulation of Gatherings Act 205 of 1993 to prohibit the possession of any dangerous weapon at a gathering or demonstration. The Dangerous Weapons Act provides for a uniform system of law governing the use of dangerous weapons for the whole of South Africa and it furthermore no longer places the onus on the individual charged with the offence of the possession of a dangerous weapon to show that he or she did not have any intention of using the firearm for an unlawful purpose. The Act also defines the meaning of a dangerous weapon. According to our court’s interpretation of the Dangerous Weapons Act 71 of 1968 a dangerous weapon was regarded as an object used or intended to be used as a weapon even if it had not been designed for use as a weapon. The Act, however, requires the object to be capable of causing death or inflicting serious bodily harm if it were used for an unlawful purpose. The possession of a dangerous weapon, in circumstances which may raise a reasonable suspicion that the person intends to use it for an unlawful purpose, attracts criminal liability. The Act also provides a useful set of guidelines to assist courts to determine if a person charged with the offence of the possession of a dangerous weapon had indeed intended to use the weapon for an unlawful purpose. It seems, however, that the Act prohibits the possession of a dangerous weapon at gatherings, even if the person carrying the weapon does not intend to use it for an unlawful purpose. The state will, however, have to prove that the accused had the necessary control over the object and the intention to exercise such control, as well as that the object is capable of

  18. Possession and Immoveable Property: The History of Two Connected Concepts

    Directory of Open Access Journals (Sweden)

    César Carranza-Álvarez

    2010-11-01

    Full Text Available Possession and property are two different sides of the same coin. The two institutions have the same axis: the benefit, mainly economic, of a good. In countries like Colombia and Peru, important reforms have been introduced whose main effect has been the following one: the approach to these two institutions. In this article we will speak of these two institutions, today more than ever, connected.

  19. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  20. Foundations of Neuromorphic Computing

    Science.gov (United States)

    2013-05-01

    of the GPGPUs are the NVIDIA Tesla C1060 model which has 240 cores running at 1.3GHz providing 933 GFLOPs. The other half are the NVIDIA Tesla C2050...performance. Another reason for the lower performance of the neural network in selecting when to stop the car is that the training samples must come from...scaled model parking facility. A video camera monitored the incoming traffic (remote controlled cars ), and the system alerted an attendant when