Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

OpenAIRE

Massimiliano Giulioni; Federico Corradi; Vittorio Dante; Paolo del Giudice

2015-01-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a 'basin' of attraction compri...

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

Science.gov (United States)

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; Del Giudice, Paolo

2015-10-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

Neuromorphic walking gait control.

Science.gov (United States)

Still, Susanne; Hepp, Klaus; Douglas, Rodney J

2006-03-01

We present a neuromorphic pattern generator for controlling the walking gaits of four-legged robots which is inspired by central pattern generators found in the nervous system and which is implemented as a very large scale integrated (VLSI) chip. The chip contains oscillator circuits that mimic the output of motor neurons in a strongly simplified way. We show that four coupled oscillators can produce rhythmic patterns with phase relationships that are appropriate to generate all four-legged animal walking gaits. These phase relationships together with frequency and duty cycle of the oscillators determine the walking behavior of a robot driven by the chip, and they depend on a small set of stationary bias voltages. We give analytic expressions for these dependencies. This chip reduces the complex, dynamic inter-leg control problem associated with walking gait generation to the problem of setting a few stationary parameters. It provides a compact and low power solution for walking gait control in robots.

VLSI design

CERN Document Server

Einspruch, Norman G

1986-01-01

VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

VLSI design

CERN Document Server

Basu, D K

2014-01-01

Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

Science.gov (United States)

Indiveri, Giacomo

2008-09-03

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2008-09-01

Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Neuromorphic meets neuromechanics, part I: the methodology and implementation

Science.gov (United States)

Niu, Chuanxin M.; Jalaleddini, Kian; Sohn, Won Joon; Rocamora, John; Sanger, Terence D.; Valero-Cuevas, Francisco J.

2017-04-01

Objective: One goal of neuromorphic engineering is to create ‘realistic’ robotic systems that interact with the physical world by adopting neuromechanical principles from biology. Critical to this is the methodology to implement the spinal circuitry responsible for the behavior of afferented muscles. At its core, muscle afferentation is the closed-loop behavior arising from the interactions among populations of muscle spindle afferents, alpha and gamma motoneurons, and muscle fibers to enable useful behaviors. Approach. We used programmable very- large-scale-circuit (VLSI) hardware to implement simple models of spiking neurons, skeletal muscles, muscle spindle proprioceptors, alpha-motoneuron recruitment, gamma motoneuron control of spindle sensitivity, and the monosynaptic circuitry connecting them. This multi-scale system of populations of spiking neurons emulated the physiological properties of a pair of antagonistic afferented mammalian muscles (each simulated by 1024 alpha- and gamma-motoneurones) acting on a joint via long tendons. Main results. This integrated system was able to maintain a joint angle, and reproduced stretch reflex responses even when driving the nonlinear biomechanics of an actual cadaveric finger. Moreover, this system allowed us to explore numerous values and combinations of gamma-static and gamma-dynamic gains when driving a robotic finger, some of which replicated some human pathological conditions. Lastly, we explored the behavioral consequences of adopting three alternative models of isometric muscle force production. We found that the dynamic responses to rate-coded spike trains produce force ramps that can be very sensitive to tendon elasticity, especially at high force output. Significance. Our methodology produced, to our knowledge, the first example of an autonomous, multi-scale, neuromorphic, neuromechanical system capable of creating realistic reflex behavior in cadaveric fingers. This research platform allows us to explore

VLSI design

CERN Document Server

Chandrasetty, Vikram Arkalgud

2011-01-01

This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

VLSI in medicine

CERN Document Server

Einspruch, Norman G

1989-01-01

VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

VLSI electronics microstructure science

CERN Document Server

1982-01-01

VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

Neuromorphic Data Microscope

Energy Technology Data Exchange (ETDEWEB)

Naegle, John H.; Suppona, Roger A.; Aimone, James Bradley; James, Conrad D.; Follett, David R.; Townsend, Duncan C.M.; Follett, Pamela L.; Karpman, Gabe D.

2017-08-01

In 2016, Lewis Rhodes Labs, (LRL), shipped the first commercially viable Neuromorphic Processing Unit, (NPU), branded as a Neuromorphic Data Microscope (NDM). This product leverages architectural mechanisms derived from the sensory cortex of the human brain to efficiently implement pattern matching. LRL and Sandia National Labs have optimized this product for streaming analytics, and demonstrated a 1,000x power per operation reduction in an FPGA format. When reduced to an ASIC, the efficiency will improve to 1,000,000x. Additionally, the neuromorphic nature of the device gives it powerful computational attributes that are counterintuitive to those schooled in traditional von Neumann architectures. The Neuromorphic Data Microscope is the first of a broad class of brain-inspired, time domain processors that will profoundly alter the functionality and economics of data processing.

Foundations of Neuromorphic Computing

Science.gov (United States)

2013-05-01

paradigms: few sensors/complex computations and many sensors/simple computation. Challenges with Nano-enabled Neuromorphic Chips A wide variety of...FOUNDATIONS OF NEUROMORPHIC COMPUTING MAY 2013 FINAL TECHNICAL REPORT APPROVED FOR PUBLIC RELEASE; DISTRIBUTION...2009 – SEP 2012 4. TITLE AND SUBTITLE FOUNDATIONS OF NEUROMORPHIC COMPUTING 5a. CONTRACT NUMBER IN-HOUSE 5b. GRANT NUMBER N/A 5c. PROGRAM

VLSI electronics microstructure science

CERN Document Server

1981-01-01

VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

Energy-efficient neuromorphic classifiers

OpenAIRE

Martí, Daniel; Rigotti, Mattia; Seok, Mingoo; Fusi, Stefano

2015-01-01

Neuromorphic engineering combines the architectural and computational principles of systems neuroscience with semiconductor electronics, with the aim of building efficient and compact devices that mimic the synaptic and neural machinery of the brain. Neuromorphic engineering promises extremely low energy consumptions, comparable to those of the nervous system. However, until now the neuromorphic approach has been restricted to relatively simple circuits and specialized functions, rendering el...

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Lie group model neuromorphic geometric engine for real-time terrain reconstruction from stereoscopic aerial photos

Science.gov (United States)

Tsao, Thomas R.; Tsao, Doris

1997-04-01

In the 1980's, neurobiologist suggested a simple mechanism in primate visual cortex for maintaining a stable and invariant representation of a moving object. The receptive field of visual neurons has real-time transforms in response to motion, to maintain a stable representation. When the visual stimulus is changed due to motion, the geometric transform of the stimulus triggers a dual transform of the receptive field. This dual transform in the receptive fields compensates geometric variation in the stimulus. This process can be modelled using a Lie group method. The massive array of affine parameter sensing circuits will function as a smart sensor tightly coupled to the passive imaging sensor (retina). Neural geometric engine is a neuromorphic computing device simulating our Lie group model of spatial perception of primate's primal visual cortex. We have developed the computer simulation and experimented on realistic and synthetic image data, and performed a preliminary research of using analog VLSI technology for implementation of the neural geometric engine. We have benchmark tested on DMA's terrain data with their result and have built an analog integrated circuit to verify the computational structure of the engine. When fully implemented on ANALOG VLSI chip, we will be able to accurately reconstruct a 3D terrain surface in real-time from stereoscopic imagery.

Digital characterization of a neuromorphic IRFPA

Science.gov (United States)

Caulfield, John T.; Fisher, John; Zadnik, Jerome A.; Mak, Ernest S.; Scribner, Dean A.

1995-05-01

This paper reports on the performance of the Neuromorphic IRFPA, the first IRFPA designed and fabricated to conduct temporal and spatial processing on the focal plane. The Neuromorphic IRFPA's unique on-chip processing capability can perform retina-like functions such as lateral inhibition and contrast enhancement, spatial and temporal filtering, image compression and edge enhancement, and logarithmic response. Previously, all evaluations of the Neuromorphic IRFPA camera have been performed on the analog video output. In the work leading up to this paper, the Neuromorphic was integrated to a digital recorder to collect quantitative laboratory and field data. This paper describes the operation and characterization of specific on-chip processes such as spatial and temporal kernel size control. The use of Neuromorphic on-chip processing in future IRFPAs is analyzed as applied to improving SNR via adaptive nonuniformity, charge handling, and dynamic range problems.

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

Science.gov (United States)

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

Plasma processing for VLSI

CERN Document Server

Einspruch, Norman G

1984-01-01

VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

Energy-Efficient Neuromorphic Classifiers.

Science.gov (United States)

Martí, Daniel; Rigotti, Mattia; Seok, Mingoo; Fusi, Stefano

2016-10-01

Neuromorphic engineering combines the architectural and computational principles of systems neuroscience with semiconductor electronics, with the aim of building efficient and compact devices that mimic the synaptic and neural machinery of the brain. The energy consumptions promised by neuromorphic engineering are extremely low, comparable to those of the nervous system. Until now, however, the neuromorphic approach has been restricted to relatively simple circuits and specialized functions, thereby obfuscating a direct comparison of their energy consumption to that used by conventional von Neumann digital machines solving real-world tasks. Here we show that a recent technology developed by IBM can be leveraged to realize neuromorphic circuits that operate as classifiers of complex real-world stimuli. Specifically, we provide a set of general prescriptions to enable the practical implementation of neural architectures that compete with state-of-the-art classifiers. We also show that the energy consumption of these architectures, realized on the IBM chip, is typically two or more orders of magnitude lower than that of conventional digital machines implementing classifiers with comparable performance. Moreover, the spike-based dynamics display a trade-off between integration time and accuracy, which naturally translates into algorithms that can be flexibly deployed for either fast and approximate classifications, or more accurate classifications at the mere expense of longer running times and higher energy costs. This work finally proves that the neuromorphic approach can be efficiently used in real-world applications and has significant advantages over conventional digital devices when energy consumption is considered.

Progress in neuromorphic photonics

Science.gov (United States)

Ferreira de Lima, Thomas; Shastri, Bhavin J.; Tait, Alexander N.; Nahmias, Mitchell A.; Prucnal, Paul R.

2017-03-01

As society's appetite for information continues to grow, so does our need to process this information with increasing speed and versatility. Many believe that the one-size-fits-all solution of digital electronics is becoming a limiting factor in certain areas such as data links, cognitive radio, and ultrafast control. Analog photonic devices have found relatively simple signal processing niches where electronics can no longer provide sufficient speed and reconfigurability. Recently, the landscape for commercially manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. By bridging the mathematical prowess of artificial neural networks to the underlying physics of optoelectronic devices, neuromorphic photonics could breach new domains of information processing demanding significant complexity, low cost, and unmatched speed. In this article, we review the progress in neuromorphic photonics, focusing on photonic integrated devices. The challenges and design rules for optoelectronic instantiation of artificial neurons are presented. The proposed photonic architecture revolves around the processing network node composed of two parts: a nonlinear element and a network interface. We then survey excitable lasers in the recent literature as candidates for the nonlinear node and microring-resonator weight banks as the network interface. Finally, we compare metrics between neuromorphic electronics and neuromorphic photonics and discuss potential applications.

Network-driven design principles for neuromorphic systems

OpenAIRE

Partzsch, Johannes; Sch?ffny, Rene

2015-01-01

Synaptic connectivity is typically the most resource-demanding part of neuromorphic systems. Commonly, the architecture of these systems is chosen mainly on technical considerations. As a consequence, the potential for optimization arising from the inherent constraints of connectivity models is left unused. In this article, we develop an alternative, network-driven approach to neuromorphic architecture design. We describe methods to analyse performance of existing neuromorphic architectures i...

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Science.gov (United States)

McEwan, Alistair; van Schaik, André

2003-12-01

The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

Science.gov (United States)

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Coupling an aVLSI neuromorphic vision chip to a neurotrophic model of synaptic plasticity: the development of topography.

Science.gov (United States)

Elliott, Terry; Kramer, Jörg

2002-10-01

We couple a previously studied, biologically inspired neurotrophic model of activity-dependent competitive synaptic plasticity and neuronal development to a neuromorphic retina chip. Using this system, we examine the development and refinement of a topographic mapping between an array of afferent neurons (the retinal ganglion cells) and an array of target neurons. We find that the plasticity model can indeed drive topographic refinement in the presence of afferent activity patterns generated by a real-world device. We examine the resilience of the developing system to the presence of high levels of noise by adjusting the spontaneous firing rate of the silicon neurons.

Anthropomorphic reasoning about neuromorphic AGI safety

Science.gov (United States)

Jilk, David J.; Herd, Seth J.; Read, Stephen J.; O'Reilly, Randall C.

2017-11-01

One candidate approach to creating artificial general intelligence (AGI) is to imitate the essential computations of human cognition. This process is sometimes called 'reverse-engineering the brain' and the end product called 'neuromorphic.' We argue that, unlike with other approaches to AGI, anthropomorphic reasoning about behaviour and safety concerns is appropriate and crucial in a neuromorphic context. Using such reasoning, we offer some initial ideas to make neuromorphic AGI safer. In particular, we explore how basic drives that promote social interaction may be essential to the development of cognitive capabilities as well as serving as a focal point for human-friendly outcomes.

Network-driven design principles for neuromorphic systems

Directory of Open Access Journals (Sweden)

Johannes ePartzsch

2015-10-01

Full Text Available Synaptic connectivity is typically the most resource-demanding part of neuromorphic systems. Commonly, the architecture of these systems is chosen mainly on technical considerations. As a consequence, the potential for optimization arising from the inherent constraints of connectivity models is left unused. In this article, we develop an alternative, network-driven approach to neuromorphic architecture design. We describe methods to analyse performance of existing neuromorphic architectures in emulating certain connectivity models. Furthermore, we show step-by-step how to derive a neuromorphic architecture from a given connectivity model. For this, we introduce a generalized description for architectures with a synapse matrix, which takes into account shared use of circuit components for reducing total silicon area. Architectures designed with this approach are fitted to a connectivity model, essentially adapting to its connection density. They are guaranteeing faithful reproduction of the model on chip, while requiring less total silicon area. In total, our methods allow designers to implement more area-efficient neuromorphic systems and verify usability of the connectivity resources in these systems.

Network-driven design principles for neuromorphic systems.

Science.gov (United States)

Partzsch, Johannes; Schüffny, Rene

2015-01-01

Synaptic connectivity is typically the most resource-demanding part of neuromorphic systems. Commonly, the architecture of these systems is chosen mainly on technical considerations. As a consequence, the potential for optimization arising from the inherent constraints of connectivity models is left unused. In this article, we develop an alternative, network-driven approach to neuromorphic architecture design. We describe methods to analyse performance of existing neuromorphic architectures in emulating certain connectivity models. Furthermore, we show step-by-step how to derive a neuromorphic architecture from a given connectivity model. For this, we introduce a generalized description for architectures with a synapse matrix, which takes into account shared use of circuit components for reducing total silicon area. Architectures designed with this approach are fitted to a connectivity model, essentially adapting to its connection density. They are guaranteeing faithful reproduction of the model on chip, while requiring less total silicon area. In total, our methods allow designers to implement more area-efficient neuromorphic systems and verify usability of the connectivity resources in these systems.

Lithography for VLSI

CERN Document Server

Einspruch, Norman G

1987-01-01

VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

Neuromorphic sensory systems.

Science.gov (United States)

Liu, Shih-Chii; Delbruck, Tobi

2010-06-01

Biology provides examples of efficient machines which greatly outperform conventional technology. Designers in neuromorphic engineering aim to construct electronic systems with the same efficient style of computation. This task requires a melding of novel engineering principles with knowledge gleaned from neuroscience. We discuss recent progress in realizing neuromorphic sensory systems which mimic the biological retina and cochlea, and subsequent sensor processing. The main trends are the increasing number of sensors and sensory systems that communicate through asynchronous digital signals analogous to neural spikes; the improved performance and usability of these sensors; and novel sensory processing methods which capitalize on the timing of spikes from these sensors. Experiments using these sensors can impact how we think the brain processes sensory information. 2010 Elsevier Ltd. All rights reserved.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

Directory of Open Access Journals (Sweden)

Alistair McEwan

2003-06-01

Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Neuromorphic cognitive systems a learning and memory centered approach

CERN Document Server

Yu, Qiang; Hu, Jun; Tan Chen, Kay

2017-01-01

This book presents neuromorphic cognitive systems from a learning and memory-centered perspective. It illustrates how to build a system network of neurons to perform spike-based information processing, computing, and high-level cognitive tasks. It is beneficial to a wide spectrum of readers, including undergraduate and postgraduate students and researchers who are interested in neuromorphic computing and neuromorphic engineering, as well as engineers and professionals in industry who are involved in the design and applications of neuromorphic cognitive systems, neuromorphic sensors and processors, and cognitive robotics. The book formulates a systematic framework, from the basic mathematical and computational methods in spike-based neural encoding, learning in both single and multi-layered networks, to a near cognitive level composed of memory and cognition. Since the mechanisms for integrating spiking neurons integrate to formulate cognitive functions as in the brain are little understood, studies of neuromo...

Surface and interface effects in VLSI

CERN Document Server

Einspruch, Norman G

1985-01-01

VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

Foldable neuromorphic memristive electronics

KAUST Repository

Ghoneim, Mohamed T.

2014-07-01

Neuromorphic computer will need folded architectural form factor to match brain cortex\\'s folded pattern for ultra-compact design. In this work, we show a state-of-the-art CMOS compatible pragmatic fabrication approach of building structurally foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench-protect-release-recycle process transform the silicon wafer with devices into a flexible and semi-transparent silicon fabric while recycling the remaining wafer for further use. This process unconditionally offers the ultra-large-scale-integration opportunity-increasingly critical for ultra-compact memory.

VLSI Architectures for Computing DFT's

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

1986-01-01

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

Neuromorphic vision sensors and preprocessors in system applications

Science.gov (United States)

Kramer, Joerg; Indiveri, Giacomo

1998-09-01

A partial review of neuromorphic vision sensors that are suitable for use in autonomous systems is presented. Interfaces are being developed to multiplex the high- dimensional output signals of arrays of such sensors and to communicate them in standard formats to off-chip devices for higher-level processing, actuation, storage and display. Alternatively, on-chip processing stages may be implemented to extract sparse image parameters, thereby obviating the need for multiplexing. Autonomous robots are used to test neuromorphic vision chips in real-world environments and to explore the possibilities of data fusion from different sensing modalities. Examples of autonomous mobile systems that use neuromorphic vision chips for line tracking and optical flow matching are described.

Foldable neuromorphic memristive electronics

KAUST Repository

Ghoneim, Mohamed T.; Zidan, Mohammed A.; Salama, Khaled N.; Hussain, Muhammad Mustafa

2014-01-01

foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench

Dynamic Adaptive Neural Network Arrays: A Neuromorphic Architecture

Energy Technology Data Exchange (ETDEWEB)

Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

2015-01-01

Dynamic Adaptive Neural Network Array (DANNA) is a neuromorphic hardware implementation. It differs from most other neuromorphic projects in that it allows for programmability of structure, and it is trained or designed using evolutionary optimization. This paper describes the DANNA structure, how DANNA is trained using evolutionary optimization, and an application of DANNA to a very simple classification task.

Neuromorphic olfaction neuromorphic olfaction

CERN Document Server

Persaud, Krishna C; Marco, Santiago

2016-01-01

Engineering Aspects of Olfaction; Krishna C. PersaudStudy of the Coding Efficiency of Populations of OlfactoryReceptor Neurons and Olfactory Glomeruli; Agustín Gutiérrez-Gálvez and Santiago MarcoMimicking Biological Olfaction with Very Large ChemicalArrays; Mara Bernabei, Romeo Beccherelli, Emiliano Zampetti,Simone Pantalei, and Krishna C. PersaudThe Synthetic Moth: A Neuromorphic Approach towardArtificial Olfaction in Robots; Vasiliki Vouloutsi, Lucas L. Lopez-Serrano,Zenon Mathews, Alex Escuredo Chimeno, Andrey Ziyatdinov, Alexandre Perera i Lluna, Sergi Bermúdez i Badia, and Paul F. M. J. Verschure Reactive and Cognitive Search Strategies for Olfactory Robots; Dominique Martinez and Eduardo Martin MoraudPerformance of a Computational Model of the MammalianOlfactory System; Simon Benjaminsson, Pawel Herman, and Anders LansnerIndex.

Electro-optic techniques for VLSI interconnect

Science.gov (United States)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Multi-valued LSI/VLSI logic design

Science.gov (United States)

Santrakul, K.

A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

Memristor-Based Synapse Design and Training Scheme for Neuromorphic Computing Architecture

Science.gov (United States)

2012-06-01

system level built upon the conventional Von Neumann computer architecture [2][3]. Developing the neuromorphic architecture at chip level by...SCHEME FOR NEUROMORPHIC COMPUTING ARCHITECTURE 5a. CONTRACT NUMBER FA8750-11-2-0046 5b. GRANT NUMBER N/A 5c. PROGRAM ELEMENT NUMBER 62788F 6...creation of memristor-based neuromorphic computing architecture. Rather than the existing crossbar-based neuron network designs, we focus on memristor

VLSI implementations for image communications

CERN Document Server

Pirsch, P

1993-01-01

The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

An Investigation into Spike-Based Neuromorphic Approaches for Artificial Olfactory Systems

Directory of Open Access Journals (Sweden)

Anup Vanarse

2017-11-01

Full Text Available The implementation of neuromorphic methods has delivered promising results for vision and auditory sensors. These methods focus on mimicking the neuro-biological architecture to generate and process spike-based information with minimal power consumption. With increasing interest in developing low-power and robust chemical sensors, the application of neuromorphic engineering concepts for electronic noses has provided an impetus for research focusing on improving these instruments. While conventional e-noses apply computationally expensive and power-consuming data-processing strategies, neuromorphic olfactory sensors implement the biological olfaction principles found in humans and insects to simplify the handling of multivariate sensory data by generating and processing spike-based information. Over the last decade, research on neuromorphic olfaction has established the capability of these sensors to tackle problems that plague the current e-nose implementations such as drift, response time, portability, power consumption and size. This article brings together the key contributions in neuromorphic olfaction and identifies future research directions to develop near-real-time olfactory sensors that can be implemented for a range of applications such as biosecurity and environmental monitoring. Furthermore, we aim to expose the computational parallels between neuromorphic olfaction and gustation for future research focusing on the correlation of these senses.

Technology computer aided design simulation for VLSI MOSFET

CERN Document Server

Sarkar, Chandan Kumar

2013-01-01

Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

Parallel Evolutionary Optimization for Neuromorphic Network Training

Energy Technology Data Exchange (ETDEWEB)

Schuman, Catherine D [ORNL; Disney, Adam [University of Tennessee (UT); Singh, Susheela [North Carolina State University (NCSU), Raleigh; Bruer, Grant [University of Tennessee (UT); Mitchell, John Parker [University of Tennessee (UT); Klibisz, Aleksander [University of Tennessee (UT); Plank, James [University of Tennessee (UT)

2016-01-01

One of the key impediments to the success of current neuromorphic computing architectures is the issue of how best to program them. Evolutionary optimization (EO) is one promising programming technique; in particular, its wide applicability makes it especially attractive for neuromorphic architectures, which can have many different characteristics. In this paper, we explore different facets of EO on a spiking neuromorphic computing model called DANNA. We focus on the performance of EO in the design of our DANNA simulator, and on how to structure EO on both multicore and massively parallel computing systems. We evaluate how our parallel methods impact the performance of EO on Titan, the U.S.'s largest open science supercomputer, and BOB, a Beowulf-style cluster of Raspberry Pi's. We also focus on how to improve the EO by evaluating commonality in higher performing neural networks, and present the result of a study that evaluates the EO performed by Titan.

Finding a Roadmap to achieve Large Neuromorphic Hardware Systems

Directory of Open Access Journals (Sweden)

Jennifer eHasler

2013-09-01

Full Text Available Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks.

Science.gov (United States)

Walter, Florian; Röhrbein, Florian; Knoll, Alois

2015-12-01

The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. Copyright © 2015 Elsevier Ltd. All rights reserved.

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

An Evolutionary Optimization Framework for Neural Networks and Neuromorphic Architectures

Energy Technology Data Exchange (ETDEWEB)

Schuman, Catherine D [ORNL; Plank, James [University of Tennessee (UT); Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

2016-01-01

As new neural network and neuromorphic architectures are being developed, new training methods that operate within the constraints of the new architectures are required. Evolutionary optimization (EO) is a convenient training method for new architectures. In this work, we review a spiking neural network architecture and a neuromorphic architecture, and we describe an EO training framework for these architectures. We present the results of this training framework on four classification data sets and compare those results to other neural network and neuromorphic implementations. We also discuss how this EO framework may be extended to other architectures.

Parallel VLSI Architecture

Science.gov (United States)

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Understanding a Deep Learning Technique through a Neuromorphic System a Case Study with SpiNNaker Neuromorphic Platform

Directory of Open Access Journals (Sweden)

Sugiarto Indar

2018-01-01

Full Text Available Deep learning (DL has been considered as a breakthrough technique in the field of artificial intelligence and machine learning. Conceptually, it relies on a many-layer network that exhibits a hierarchically non-linear processing capability. Some DL architectures such as deep neural networks, deep belief networks and recurrent neural networks have been developed and applied to many fields with incredible results, even comparable to human intelligence. However, many researchers are still sceptical about its true capability: can the intelligence demonstrated by deep learning technique be applied for general tasks? This question motivates the emergence of another research discipline: neuromorphic computing (NC. In NC, researchers try to identify the most fundamental ingredients that construct intelligence behaviour produced by the brain itself. To achieve this, neuromorphic systems are developed to mimic the brain functionality down to cellular level. In this paper, a neuromorphic platform called SpiNNaker is described and evaluated in order to understand its potential use as a platform for a deep learning approach. This paper is a literature review that contains comparative study on algorithms that have been implemented in SpiNNaker.

Neuromorphic Modeling of Moving Target Detection in Insects

Science.gov (United States)

2007-12-31

Standard Form 298 (Rev. 8/98) Prescribed by ANSI Std. Z39, 18 Grants FA9550-04-1-0283 and FA9550-04-1-0294 Neuromorphic Modeling of Moving Target Detection...natural for neuromorphic sensory processing. We developed visual motion detection circuitry, including photodetectors, early vision, and models for both...Lincoln Labs 3DM2 run, Tanner Research reserved and utilized space corresponding to two MOSIS ’tiny chips ’ (2mm square each), each with three interconnected

Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

Science.gov (United States)

Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

2012-06-01

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

Convolutional networks for fast, energy-efficient neuromorphic computing.

Science.gov (United States)

Esser, Steven K; Merolla, Paul A; Arthur, John V; Cassidy, Andrew S; Appuswamy, Rathinakumar; Andreopoulos, Alexander; Berg, David J; McKinstry, Jeffrey L; Melano, Timothy; Barch, Davis R; di Nolfo, Carmelo; Datta, Pallab; Amir, Arnon; Taba, Brian; Flickner, Myron D; Modha, Dharmendra S

2016-10-11

Deep networks are now able to achieve human-level performance on a broad spectrum of recognition tasks. Independently, neuromorphic computing has now demonstrated unprecedented energy-efficiency through a new chip architecture based on spiking neurons, low precision synapses, and a scalable communication network. Here, we demonstrate that neuromorphic computing, despite its novel architectural primitives, can implement deep convolution networks that (i) approach state-of-the-art classification accuracy across eight standard datasets encompassing vision and speech, (ii) perform inference while preserving the hardware's underlying energy-efficiency and high throughput, running on the aforementioned datasets at between 1,200 and 2,600 frames/s and using between 25 and 275 mW (effectively >6,000 frames/s per Watt), and (iii) can be specified and trained using backpropagation with the same ease-of-use as contemporary deep learning. This approach allows the algorithmic power of deep learning to be merged with the efficiency of neuromorphic processors, bringing the promise of embedded, intelligent, brain-inspired computing one step closer.

Compact MOSFET models for VLSI design

CERN Document Server

Bhattacharyya, A B

2009-01-01

Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

Opto-VLSI-based reconfigurable free-space optical interconnects architecture

DEFF Research Database (Denmark)

Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

2007-01-01

is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

Recent Advances on Neuromorphic Systems Using Phase-Change Materials

Science.gov (United States)

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-05-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Recent Advances on Neuromorphic Systems Using Phase-Change Materials.

Science.gov (United States)

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-12-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Neuromorphic atomic switch networks.

Directory of Open Access Journals (Sweden)

Audrius V Avizienis

Full Text Available Efforts to emulate the formidable information processing capabilities of the brain through neuromorphic engineering have been bolstered by recent progress in the fabrication of nonlinear, nanoscale circuit elements that exhibit synapse-like operational characteristics. However, conventional fabrication techniques are unable to efficiently generate structures with the highly complex interconnectivity found in biological neuronal networks. Here we demonstrate the physical realization of a self-assembled neuromorphic device which implements basic concepts of systems neuroscience through a hardware-based platform comprised of over a billion interconnected atomic-switch inorganic synapses embedded in a complex network of silver nanowires. Observations of network activation and passive harmonic generation demonstrate a collective response to input stimulus in agreement with recent theoretical predictions. Further, emergent behaviors unique to the complex network of atomic switches and akin to brain function are observed, namely spatially distributed memory, recurrent dynamics and the activation of feedforward subnetworks. These devices display the functional characteristics required for implementing unconventional, biologically and neurally inspired computational methodologies in a synthetic experimental system.

All-memristive neuromorphic computing with level-tuned neurons

Science.gov (United States)

Pantazi, Angeliki; Woźniak, Stanisław; Tuma, Tomas; Eleftheriou, Evangelos

2016-09-01

In the new era of cognitive computing, systems will be able to learn and interact with the environment in ways that will drastically enhance the capabilities of current processors, especially in extracting knowledge from vast amount of data obtained from many sources. Brain-inspired neuromorphic computing systems increasingly attract research interest as an alternative to the classical von Neumann processor architecture, mainly because of the coexistence of memory and processing units. In these systems, the basic components are neurons interconnected by synapses. The neurons, based on their nonlinear dynamics, generate spikes that provide the main communication mechanism. The computational tasks are distributed across the neural network, where synapses implement both the memory and the computational units, by means of learning mechanisms such as spike-timing-dependent plasticity. In this work, we present an all-memristive neuromorphic architecture comprising neurons and synapses realized by using the physical properties and state dynamics of phase-change memristors. The architecture employs a novel concept of interconnecting the neurons in the same layer, resulting in level-tuned neuronal characteristics that preferentially process input information. We demonstrate the proposed architecture in the tasks of unsupervised learning and detection of multiple temporal correlations in parallel input streams. The efficiency of the neuromorphic architecture along with the homogenous neuro-synaptic dynamics implemented with nanoscale phase-change memristors represent a significant step towards the development of ultrahigh-density neuromorphic co-processors.

All-memristive neuromorphic computing with level-tuned neurons.

Science.gov (United States)

Pantazi, Angeliki; Woźniak, Stanisław; Tuma, Tomas; Eleftheriou, Evangelos

2016-09-02

In the new era of cognitive computing, systems will be able to learn and interact with the environment in ways that will drastically enhance the capabilities of current processors, especially in extracting knowledge from vast amount of data obtained from many sources. Brain-inspired neuromorphic computing systems increasingly attract research interest as an alternative to the classical von Neumann processor architecture, mainly because of the coexistence of memory and processing units. In these systems, the basic components are neurons interconnected by synapses. The neurons, based on their nonlinear dynamics, generate spikes that provide the main communication mechanism. The computational tasks are distributed across the neural network, where synapses implement both the memory and the computational units, by means of learning mechanisms such as spike-timing-dependent plasticity. In this work, we present an all-memristive neuromorphic architecture comprising neurons and synapses realized by using the physical properties and state dynamics of phase-change memristors. The architecture employs a novel concept of interconnecting the neurons in the same layer, resulting in level-tuned neuronal characteristics that preferentially process input information. We demonstrate the proposed architecture in the tasks of unsupervised learning and detection of multiple temporal correlations in parallel input streams. The efficiency of the neuromorphic architecture along with the homogenous neuro-synaptic dynamics implemented with nanoscale phase-change memristors represent a significant step towards the development of ultrahigh-density neuromorphic co-processors.

Artificial immune system algorithm in VLSI circuit configuration

Science.gov (United States)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

Hybrid VLSI/QCA Architecture for Computing FFTs

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Delay dynamics of neuromorphic optoelectronic nanoscale resonators: Perspectives and applications

Science.gov (United States)

Romeira, Bruno; Figueiredo, José M. L.; Javaloyes, Julien

2017-11-01

With the recent exponential growth of applications using artificial intelligence (AI), the development of efficient and ultrafast brain-like (neuromorphic) systems is crucial for future information and communication technologies. While the implementation of AI systems using computer algorithms of neural networks is emerging rapidly, scientists are just taking the very first steps in the development of the hardware elements of an artificial brain, specifically neuromorphic microchips. In this review article, we present the current state of the art of neuromorphic photonic circuits based on solid-state optoelectronic oscillators formed by nanoscale double barrier quantum well resonant tunneling diodes. We address, both experimentally and theoretically, the key dynamic properties of recently developed artificial solid-state neuron microchips with delayed perturbations and describe their role in the study of neural activity and regenerative memory. This review covers our recent research work on excitable and delay dynamic characteristics of both single and autaptic (delayed) artificial neurons including all-or-none response, spike-based data encoding, storage, signal regeneration and signal healing. Furthermore, the neural responses of these neuromorphic microchips display all the signatures of extended spatio-temporal localized structures (LSs) of light, which are reviewed here in detail. By taking advantage of the dissipative nature of LSs, we demonstrate potential applications in optical data reconfiguration and clock and timing at high-speeds and with short transients. The results reviewed in this article are a key enabler for the development of high-performance optoelectronic devices in future high-speed brain-inspired optical memories and neuromorphic computing.

Convolutional networks for fast, energy-efficient neuromorphic computing

Science.gov (United States)

Esser, Steven K.; Merolla, Paul A.; Arthur, John V.; Cassidy, Andrew S.; Appuswamy, Rathinakumar; Andreopoulos, Alexander; Berg, David J.; McKinstry, Jeffrey L.; Melano, Timothy; Barch, Davis R.; di Nolfo, Carmelo; Datta, Pallab; Amir, Arnon; Taba, Brian; Flickner, Myron D.; Modha, Dharmendra S.

2016-01-01

Deep networks are now able to achieve human-level performance on a broad spectrum of recognition tasks. Independently, neuromorphic computing has now demonstrated unprecedented energy-efficiency through a new chip architecture based on spiking neurons, low precision synapses, and a scalable communication network. Here, we demonstrate that neuromorphic computing, despite its novel architectural primitives, can implement deep convolution networks that (i) approach state-of-the-art classification accuracy across eight standard datasets encompassing vision and speech, (ii) perform inference while preserving the hardware’s underlying energy-efficiency and high throughput, running on the aforementioned datasets at between 1,200 and 2,600 frames/s and using between 25 and 275 mW (effectively >6,000 frames/s per Watt), and (iii) can be specified and trained using backpropagation with the same ease-of-use as contemporary deep learning. This approach allows the algorithmic power of deep learning to be merged with the efficiency of neuromorphic processors, bringing the promise of embedded, intelligent, brain-inspired computing one step closer. PMID:27651489

The Microchip Optera Project

National Research Council Canada - National Science Library

Moss, Cynthia; Horiuchi, Timothy K

2006-01-01

.... The long-term goal of this project is to build a tiny, low-power, neuromorphic VLSI-based model of an FM bat echolocation system that can be demonstrated in an aerial target capture task using a flying vehicle...

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Built-in self-repair of VLSI memories employing neural nets

Science.gov (United States)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Delay dynamics of neuromorphic optoelectronic nanoscale resonators: Perspectives and applications

OpenAIRE

Romeira, B.; Figueiredo, J. M. L.; Javaloyes, J.

2017-01-01

With the recent exponential growth of applications using artificial intelligence (AI), the development of efficient and ultrafast brain-like (neuromorphic) systems is crucial for future information and communication technologies. While the implementation of AI systems using computer algorithms of neural networks is emerging rapidly, scientists are just taking the very first steps in the development of the hardware elements of an artificial brain, specifically neuromorphic microchips. In this ...

Nonvolatile Memory Materials for Neuromorphic Intelligent Machines.

Science.gov (United States)

Jeong, Doo Seok; Hwang, Cheol Seong

2018-04-18

Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Neuromorphic Kalman filter implementation in IBM’s TrueNorth

Science.gov (United States)

Carney, R.; Bouchard, K.; Calafiura, P.; Clark, D.; Donofrio, D.; Garcia-Sciveres, M.; Livezey, J.

2017-10-01

Following the advent of a post-Moore’s law field of computation, novel architectures continue to emerge. With composite, multi-million connection neuromorphic chips like IBM’s TrueNorth, neural engineering has now become a feasible technology in this novel computing paradigm. High Energy Physics experiments are continuously exploring new methods of computation and data handling, including neuromorphic, to support the growing challenges of the field and be prepared for future commodity computing trends. This work details the first instance of a Kalman filter implementation in IBM’s neuromorphic architecture, TrueNorth, for both parallel and serial spike trains. The implementation is tested on multiple simulated systems and its performance is evaluated with respect to an equivalent non-spiking Kalman filter. The limits of the implementation are explored whilst varying the size of weight and threshold registers, the number of spikes used to encode a state, size of neuron block for spatial encoding, and neuron potential reset schemes.

VLSI signal processing technology

CERN Document Server

Swartzlander, Earl

1994-01-01

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

Nano lasers in photonic VLSI

NARCIS (Netherlands)

Hill, M.T.; Oei, Y.S.; Smit, M.K.

2007-01-01

We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

Smart vision chips: An overview

Science.gov (United States)

Koch, Christof

1994-01-01

This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

VLSI and system architecture-the new development of system 5G

Energy Technology Data Exchange (ETDEWEB)

Sakamura, K.; Sekino, A.; Kodaka, T.; Uehara, T.; Aiso, H.

1982-01-01

A research and development proposal is presented for VLSI CAD systems and for a hardware environment called system 5G on which the VLSI CAD systems run. The proposed CAD systems use a hierarchically organized design language to enable design of anything from basic architectures of VLSI to VLSI mask patterns in a uniform manner. The cad systems will eventually become intelligent cad systems that acquire design knowledge and perform automatic design of VLSI chips when the characteristic requirements of VLSI chip is given. System 5G will consist of superinference machines and the 5G communication network. The superinference machine will be built based on a functionally distributed architecture connecting inferommunication network. The superinference machine will be built based on a functionally distributed architecture connecting inference machines and relational data base machines via a high-speed local network. The transfer rate of the local network will be 100 mbps at the first stage of the project and will be improved to 1 gbps. Remote access to the superinference machine will be possible through the 5G communication network. Access to system 5G will use the 5G network architecture protocol. The users will access the system 5G using standardized 5G personal computers. 5G personal logic programming stations, very high intelligent terminals providing an instruction set that supports predicate logic and input/output facilities for audio and graphical information.

Neuromorphic elements and systems as the basis for the physical implementation of artificial intelligence technologies

Science.gov (United States)

Demin, V. A.; Emelyanov, A. V.; Lapkin, D. A.; Erokhin, V. V.; Kashkarov, P. K.; Kovalchuk, M. V.

2016-11-01

The instrumental realization of neuromorphic systems may form the basis of a radically new social and economic setup, redistributing roles between humans and complex technical aggregates. The basic elements of any neuromorphic system are neurons and synapses. New memristive elements based on both organic (polymer) and inorganic materials have been formed, and the possibilities of instrumental implementation of very simple neuromorphic systems with different architectures on the basis of these elements have been demonstrated.

Neuromorphic Deep Learning Machines

OpenAIRE

Neftci, E; Augustine, C; Paul, S; Detorakis, G

2017-01-01

An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Back Propagation (BP) rule, often relies on the immediate availability of network-wide...

Towards neuromorphic electronics: Memristors on foldable silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-11-01

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex\\'s folded pattern for ultra-compact design.

Toward exascale computing through neuromorphic approaches.

Energy Technology Data Exchange (ETDEWEB)

James, Conrad D.

2010-09-01

While individual neurons function at relatively low firing rates, naturally-occurring nervous systems not only surpass manmade systems in computing power, but accomplish this feat using relatively little energy. It is asserted that the next major breakthrough in computing power will be achieved through application of neuromorphic approaches that mimic the mechanisms by which neural systems integrate and store massive quantities of data for real-time decision making. The proposed LDRD provides a conceptual foundation for SNL to make unique advances toward exascale computing. First, a team consisting of experts from the HPC, MESA, cognitive and biological sciences and nanotechnology domains will be coordinated to conduct an exercise with the outcome being a concept for applying neuromorphic computing to achieve exascale computing. It is anticipated that this concept will involve innovative extension and integration of SNL capabilities in MicroFab, material sciences, high-performance computing, and modeling and simulation of neural processes/systems.

Las Vegas is better than determinism in VLSI and distributed computing

DEFF Research Database (Denmark)

Mehlhorn, Kurt; Schmidt, Erik Meineche

1982-01-01

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

Lithography requirements in complex VLSI device fabrication

International Nuclear Information System (INIS)

Wilson, A.D.

1985-01-01

Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

Handbook of VLSI chip design and expert systems

CERN Document Server

Schwarz, A F

1993-01-01

Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

VLSI micro- and nanophotonics science, technology, and applications

CERN Document Server

Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

2011-01-01

Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

VLSI 'smart' I/O module development

Science.gov (United States)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

A neuromorphic circuit mimicking biological short-term memory.

Science.gov (United States)

Barzegarjalali, Saeid; Parker, Alice C

2016-08-01

Research shows that the way we remember things for a few seconds is a different mechanism from the way we remember things for a longer time. Short-term memory is based on persistently firing neurons, whereas storing information for a longer time is based on strengthening the synapses or even forming new neural connections. Information about location and appearance of an object is segregated and processed by separate neurons. Furthermore neurons can continue firing using different mechanisms. Here, we have designed a biomimetic neuromorphic circuit that mimics short-term memory by firing neurons, using biological mechanisms to remember location and shape of an object. Our neuromorphic circuit has a hybrid architecture. Neurons are designed with CMOS 45nm technology and synapses are designed with carbon nanotubes (CNT).

VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality

Directory of Open Access Journals (Sweden)

Stefan eScholze

2011-10-01

Full Text Available State-of-the-art large scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an FPGA-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behaviour of neuromorphic benchmarks. The specialized, dedicated AER communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA delivers a factor 25-50 more event transmission rate than other current neuromorphic communication infrastructures.

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

Science.gov (United States)

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives

Science.gov (United States)

Sengupta, Abhronil; Roy, Kaushik

2018-03-01

“Spintronics” refers to the understanding of the physics of electron spin-related phenomena. While most of the significant advancements in this field has been driven primarily by memory, recent research has demonstrated that various facets of the underlying physics of spin transport and manipulation can directly mimic the functionalities of the computational primitives in neuromorphic computation, i.e., the neurons and synapses. Given the potential of these spintronic devices to implement bio-mimetic computations at very low terminal voltages, several spin-device structures have been proposed as the core building blocks of neuromorphic circuits and systems to implement brain-inspired computing. Such an approach is expected to play a key role in circumventing the problems of ever-increasing power dissipation and hardware requirements for implementing neuro-inspired algorithms in conventional digital CMOS technology. Perspectives on spin-enabled neuromorphic computing, its status, and challenges and future prospects are outlined in this review article.

Neuromorphic adaptive plastic scalable electronics: analog learning systems.

Science.gov (United States)

Srinivasa, Narayan; Cruz-Albrecht, Jose

2012-01-01

Decades of research to build programmable intelligent machines have demonstrated limited utility in complex, real-world environments. Comparing their performance with biological systems, these machines are less efficient by a factor of 1 million1 billion in complex, real-world environments. The Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) program is a multifaceted Defense Advanced Research Projects Agency (DARPA) project that seeks to break the programmable machine paradigm and define a new path for creating useful, intelligent machines. Since real-world systems exhibit infinite combinatorial complexity, electronic neuromorphic machine technology would be preferable in a host of applications, but useful and practical implementations still do not exist. HRL Laboratories LLC has embarked on addressing these challenges, and, in this article, we provide an overview of our project and progress made thus far.

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Science.gov (United States)

Qiao, Ning; Mostafa, Hesham; Corradi, Federico; Osswald, Marc; Stefanini, Fabio; Sumislawska, Dora; Indiveri, Giacomo

2015-01-01

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

Directory of Open Access Journals (Sweden)

V. I. Romanov

2016-01-01

Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

An efficient interpolation filter VLSI architecture for HEVC standard

Science.gov (United States)

Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

2015-12-01

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

Simulation of a spiking neuron circuit using carbon nanotube transistors

Energy Technology Data Exchange (ETDEWEB)

Najari, Montassar, E-mail: malnjar@jazanu.edu.sa [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); IKCE unit, Jazan University, Jazan (Saudi Arabia); El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); Jelliti, Sami, E-mail: sjelliti@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Hakami, Othman Mousa, E-mail: omhakami@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Faculty of Sciences, Jazan University, Jazan (Saudi Arabia)

2016-06-10

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

Simulation of a spiking neuron circuit using carbon nanotube transistors

International Nuclear Information System (INIS)

Najari, Montassar; El-Grour, Tarek; Jelliti, Sami; Hakami, Othman Mousa

2016-01-01

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

A neuromorphic controller for a robotic vehicle equipped with a dynamic vision sensor

OpenAIRE

Blum, Hermann; Dietmüller, Alexander; Milde, Moritz; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

2017-01-01

Neuromorphic electronic systems exhibit advantageous characteristics, in terms of low energy consumption and low response latency, which can be useful in robotic applications that require compact and low power embedded computing resources. However, these neuromorphic circuits still face significant limitations that make their usage challenging: these include low precision, variability of components, sensitivity to noise and temperature drifts, as well as the currently limited number of neuron...

FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

Science.gov (United States)

Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar

2013-09-01

Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion. Copyright © 2013 Elsevier Ltd. All rights reserved.

Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

CERN Document Server

2015-01-01

This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

The VLSI handbook

CERN Document Server

Chen, Wai-Kai

2007-01-01

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

Neuromorphic Computing, Architectures, Models, and Applications. A Beyond-CMOS Approach to Future Computing, June 29-July 1, 2016, Oak Ridge, TN

Energy Technology Data Exchange (ETDEWEB)

Potok, Thomas [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Schuman, Catherine [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Patton, Robert [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Hylton, Todd [Brain Corporation, San Diego, CA (United States); Li, Hai [Univ. of Pittsburgh, PA (United States); Pino, Robinson [US Dept. of Energy, Washington, DC (United States)

2016-12-31

The White House and Department of Energy have been instrumental in driving the development of a neuromorphic computing program to help the United States continue its lead in basic research into (1) Beyond Exascale—high performance computing beyond Moore’s Law and von Neumann architectures, (2) Scientific Discovery—new paradigms for understanding increasingly large and complex scientific data, and (3) Emerging Architectures—assessing the potential of neuromorphic and quantum architectures. Neuromorphic computing spans a broad range of scientific disciplines from materials science to devices, to computer science, to neuroscience, all of which are required to solve the neuromorphic computing grand challenge. In our workshop we focus on the computer science aspects, specifically from a neuromorphic device through an application. Neuromorphic devices present a very different paradigm to the computer science community from traditional von Neumann architectures, which raises six major questions about building a neuromorphic application from the device level. We used these fundamental questions to organize the workshop program and to direct the workshop panels and discussions. From the white papers, presentations, panels, and discussions, there emerged several recommendations on how to proceed.

Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

CERN Document Server

Pop, Paul; Madsen, Jan

2016-01-01

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

A Re-configurable On-line Learning Spiking Neuromorphic Processor comprising 256 neurons and 128K synapses

Directory of Open Access Journals (Sweden)

Ning eQiao

2015-04-01

Full Text Available Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm 2 , and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

Science.gov (United States)

Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

2018-02-01

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

Neuromorphic photonic networks using silicon photonic weight banks.

Science.gov (United States)

Tait, Alexander N; de Lima, Thomas Ferreira; Zhou, Ellen; Wu, Allie X; Nahmias, Mitchell A; Shastri, Bhavin J; Prucnal, Paul R

2017-08-07

Photonic systems for high-performance information processing have attracted renewed interest. Neuromorphic silicon photonics has the potential to integrate processing functions that vastly exceed the capabilities of electronics. We report first observations of a recurrent silicon photonic neural network, in which connections are configured by microring weight banks. A mathematical isomorphism between the silicon photonic circuit and a continuous neural network model is demonstrated through dynamical bifurcation analysis. Exploiting this isomorphism, a simulated 24-node silicon photonic neural network is programmed using "neural compiler" to solve a differential system emulation task. A 294-fold acceleration against a conventional benchmark is predicted. We also propose and derive power consumption analysis for modulator-class neurons that, as opposed to laser-class neurons, are compatible with silicon photonic platforms. At increased scale, Neuromorphic silicon photonics could access new regimes of ultrafast information processing for radio, control, and scientific computing.

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems

Directory of Open Access Journals (Sweden)

Fabio eStefanini

2014-08-01

Full Text Available Neuromorphic hardware offers an electronic substrate for the realization of asynchronousevent-based sensory-motor systems and large-scale spiking neural network architectures. Inorder to characterize these systems, configure them, and carry out modeling experiments, it isoften necessary to interface them to workstations. The software used for this purpose typicallyconsists of a large monolithic block of code highly specific to the hardware setup used. While thisapproach can lead to highly integrated hardware/software systems, it hampers the developmentof modular and neuromorphic infrastructures. To alleviate this problem, we propose PyNCS,an open-source front-end for the definition of neural network models that is interfaced to thehardware through a set of Python Application Programming Interfaces (APIs. The designof PyNCS promotes modularity, portability and expandability and separates implementationfrom hardware description. The high-level front-end that comes with PyNCS includes tools todefine neural network models as well as to create, monitor and analyze spiking data. Here wereport the design philosophy behind the PyNCS framework and describe its implementation.We demonstrate its functionality with two representative case studies, one using an event-based neuromorphic vision sensor, and one using a set of multi-neuron devices for carryingout a cognitive decision-making task involving state-dependent computation. PyNCS, alreadyapplicable to a wide range of existing spike-based neuromorphic setups, will accelerate thedevelopment of hybrid software/hardware neuromorphic systems, thanks to its code flexibility.The code developed is open-source and available online at https://github.com/inincs/pyNCS.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors.

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-12-11

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption.

Qualitative Functional Decomposition Analysis of Evolved Neuromorphic Flight Controllers

Directory of Open Access Journals (Sweden)

Sanjay K. Boddhu

2012-01-01

Full Text Available In the previous work, it was demonstrated that one can effectively employ CTRNN-EH (a neuromorphic variant of EH method methodology to evolve neuromorphic flight controllers for a flapping wing robot. This paper describes a novel frequency grouping-based analysis technique, developed to qualitatively decompose the evolved controllers into explainable functional control blocks. A summary of the previous work related to evolving flight controllers for two categories of the controller types, called autonomous and nonautonomous controllers, is provided, and the applicability of the newly developed decomposition analysis for both controller categories is demonstrated. Further, the paper concludes with appropriate discussion of ongoing work and implications for possible future work related to employing the CTRNN-EH methodology and the decomposition analysis techniques presented in this paper.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-01-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption. PMID:26656113

Parallel computation of nondeterministic algorithms in VLSI

Energy Technology Data Exchange (ETDEWEB)

Hortensius, P D

1987-01-01

This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines.

Science.gov (United States)

Neftci, Emre O; Augustine, Charles; Paul, Somnath; Detorakis, Georgios

2017-01-01

An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Gradient Back Propagation (BP) rule, often relies on the immediate availability of network-wide information stored with high-precision memory during learning, and precise operations that are difficult to realize in neuromorphic hardware. Remarkably, recent work showed that exact backpropagated gradients are not essential for learning deep representations. Building on these results, we demonstrate an event-driven random BP (eRBP) rule that uses an error-modulated synaptic plasticity for learning deep representations. Using a two-compartment Leaky Integrate & Fire (I&F) neuron, the rule requires only one addition and two comparisons for each synaptic weight, making it very suitable for implementation in digital or mixed-signal neuromorphic hardware. Our results show that using eRBP, deep representations are rapidly learned, achieving classification accuracies on permutation invariant datasets comparable to those obtained in artificial neural network simulations on GPUs, while being robust to neural and synaptic state quantizations during learning.

Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines

Directory of Open Access Journals (Sweden)

Emre O. Neftci

2017-06-01

Full Text Available An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Gradient Back Propagation (BP rule, often relies on the immediate availability of network-wide information stored with high-precision memory during learning, and precise operations that are difficult to realize in neuromorphic hardware. Remarkably, recent work showed that exact backpropagated gradients are not essential for learning deep representations. Building on these results, we demonstrate an event-driven random BP (eRBP rule that uses an error-modulated synaptic plasticity for learning deep representations. Using a two-compartment Leaky Integrate & Fire (I&F neuron, the rule requires only one addition and two comparisons for each synaptic weight, making it very suitable for implementation in digital or mixed-signal neuromorphic hardware. Our results show that using eRBP, deep representations are rapidly learned, achieving classification accuracies on permutation invariant datasets comparable to those obtained in artificial neural network simulations on GPUs, while being robust to neural and synaptic state quantizations during learning.

A digital implementation of neuron-astrocyte interaction for neuromorphic applications.

Science.gov (United States)

Nazari, Soheila; Faez, Karim; Amiri, Mahmood; Karami, Ehsan

2015-06-01

Recent neurophysiologic findings have shown that astrocytes play important roles in information processing and modulation of neuronal activity. Motivated by these findings, in the present research, a digital neuromorphic circuit to study neuron-astrocyte interaction is proposed. In this digital circuit, the firing dynamics of the neuron is described by Izhikevich model and the calcium dynamics of a single astrocyte is explained by a functional model introduced by Postnov and colleagues. For digital implementation of the neuron-astrocyte signaling, Single Constant Multiply (SCM) technique and several linear approximations are used for efficient low-cost hardware implementation on digital platforms. Using the proposed neuron-astrocyte circuit and based on the results of MATLAB simulations, hardware synthesis and FPGA implementation, it is demonstrated that the proposed digital astrocyte is able to change the firing patterns of the neuron through bidirectional communication. Utilizing the proposed digital circuit, it will be illustrated that information processing in synaptic clefts is strongly regulated by astrocyte. Moreover, our results suggest that the digital circuit of neuron-astrocyte crosstalk produces diverse neural responses and therefore enhances the information processing capabilities of the neuromorphic circuits. This is suitable for applications in reconfigurable neuromorphic devices which implement biologically brain circuits. Copyright © 2015 Elsevier Ltd. All rights reserved.

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

NASA Space Engineering Research Center for VLSI systems design

Science.gov (United States)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

A second generation 50 Mbps VLSI level zero processing system prototype

Science.gov (United States)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Six networks on a universal neuromorphic computing substrate

Directory of Open Access Journals (Sweden)

Thomas ePfeil

2013-02-01

Full Text Available In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality.

Six networks on a universal neuromorphic computing substrate.

Science.gov (United States)

Pfeil, Thomas; Grübl, Andreas; Jeltsch, Sebastian; Müller, Eric; Müller, Paul; Petrovici, Mihai A; Schmuker, Michael; Brüderle, Daniel; Schemmel, Johannes; Meier, Karlheinz

2013-01-01

In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality.

Neuromorphic transistor achieved by redox reaction of WO3 thin film

Science.gov (United States)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

Neuromorphic computing with nanoscale spintronic oscillators.

Science.gov (United States)

Torrejon, Jacob; Riou, Mathieu; Araujo, Flavio Abreu; Tsunegi, Sumito; Khalsa, Guru; Querlioz, Damien; Bortolotti, Paolo; Cros, Vincent; Yakushiji, Kay; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Stiles, Mark D; Grollier, Julie

2017-07-26

Neurons in the brain behave as nonlinear oscillators, which develop rhythmic activity and interact to process information. Taking inspiration from this behaviour to realize high-density, low-power neuromorphic computing will require very large numbers of nanoscale nonlinear oscillators. A simple estimation indicates that to fit 10 8 oscillators organized in a two-dimensional array inside a chip the size of a thumb, the lateral dimension of each oscillator must be smaller than one micrometre. However, nanoscale devices tend to be noisy and to lack the stability that is required to process data in a reliable way. For this reason, despite multiple theoretical proposals and several candidates, including memristive and superconducting oscillators, a proof of concept of neuromorphic computing using nanoscale oscillators has yet to be demonstrated. Here we show experimentally that a nanoscale spintronic oscillator (a magnetic tunnel junction) can be used to achieve spoken-digit recognition with an accuracy similar to that of state-of-the-art neural networks. We also determine the regime of magnetization dynamics that leads to the greatest performance. These results, combined with the ability of the spintronic oscillators to interact with each other, and their long lifetime and low energy consumption, open up a path to fast, parallel, on-chip computation based on networks of oscillators.

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Science.gov (United States)

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Emerging Applications for High K Materials in VLSI Technology

Science.gov (United States)

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Emerging Applications for High K Materials in VLSI Technology

Directory of Open Access Journals (Sweden)

Robert D. Clark

2014-04-01

Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

High-precision shape representation using a neuromorphic vision sensor with synchronous address-event communication interface

Science.gov (United States)

Belbachir, A. N.; Hofstätter, M.; Litzenberger, M.; Schön, P.

2009-10-01

A synchronous communication interface for neuromorphic temporal contrast vision sensors is described and evaluated in this paper. This interface has been designed for ultra high-speed synchronous arbitration of a temporal contrast image sensors pixels' data. Enabling high-precision timestamping, this system demonstrates its uniqueness for handling peak data rates and preserving the main advantage of the neuromorphic electronic systems, that is high and accurate temporal resolution. Based on a synchronous arbitration concept, the timestamping has a resolution of 100 ns. Both synchronous and (state-of-the-art) asynchronous arbiters have been implemented in a neuromorphic dual-line vision sensor chip in a standard 0.35 µm CMOS process. The performance analysis of both arbiters and the advantages of the synchronous arbitration over asynchronous arbitration in capturing high-speed objects are discussed in detail.

High-precision shape representation using a neuromorphic vision sensor with synchronous address-event communication interface

International Nuclear Information System (INIS)

Belbachir, A N; Hofstätter, M; Litzenberger, M; Schön, P

2009-01-01

A synchronous communication interface for neuromorphic temporal contrast vision sensors is described and evaluated in this paper. This interface has been designed for ultra high-speed synchronous arbitration of a temporal contrast image sensors pixels' data. Enabling high-precision timestamping, this system demonstrates its uniqueness for handling peak data rates and preserving the main advantage of the neuromorphic electronic systems, that is high and accurate temporal resolution. Based on a synchronous arbitration concept, the timestamping has a resolution of 100 ns. Both synchronous and (state-of-the-art) asynchronous arbiters have been implemented in a neuromorphic dual-line vision sensor chip in a standard 0.35 µm CMOS process. The performance analysis of both arbiters and the advantages of the synchronous arbitration over asynchronous arbitration in capturing high-speed objects are discussed in detail

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.

Science.gov (United States)

Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

2009-01-01

Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Serendipitous Offline Learning in a Neuromorphic Robot

Directory of Open Access Journals (Sweden)

Terrence C Stewart

2016-02-01

Full Text Available We demonstrate a hybrid neuromorphic learning paradigm that learns complex sensorimotor mappings based on a small set of hard-coded reflex behaviours. A mobile robot is first controlled by a basic set of reflexive hand-designed behaviours. All sensor data is provided via a spike-based silicon retina camera (eDVS, and all control is implemented via spiking neurons simulated on neuromorphic hardware (SpiNNaker. Given this control system, the robot is capable of simple obstacle avoidance and random exploration. To train the robot to perform more complex tasks, we observe the robot and find instances where he robot accidentally performs the desired action. Data recorded from the robot during these times is then used to update the neural control system, increasing the likelihood of the robot performing that task in the future, given a similar sensor state. As an example application of this general-purpose method of training, we demonstrate the robot learning to respond to novel sensory stimuli (a mirror by turning right if it is present at an intersection, and otherwise turning left. In general, this system can learn arbitrary relations between sensory input and motor behaviour.

Harnessing VLSI System Design with EDA Tools

CERN Document Server

Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

2012-01-01

This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system

Directory of Open Access Journals (Sweden)

Daniel Brüderle

2009-06-01

Full Text Available Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Trace-based post-silicon validation for VLSI circuits

CERN Document Server

Liu, Xiao

2014-01-01

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

An Adaptable Neuromorphic Model of Orientation Selectivity Based On Floating Gate Dynamics

Directory of Open Access Journals (Sweden)

Priti eGupta

2014-04-01

Full Text Available The biggest challenge that the neuromorphic community faces today is to build systems that can be considered truly cognitive. Adaptation and self-organization are the two basic principles that underlie any cognitive function that the brain performs. If we can replicate this behavior in hardware, we move a step closer to our goal of having cognitive neuromorphic systems. Adaptive feature selectivity is a mechanism by which nature optimizes resources so as to have greater acuity for more abundant features. Developing neuromorphic feature maps can help design generic machines that can emulate this adaptive behavior. Most neuromorphic models that have attempted to build self-organizing systems, follow the approach of modeling abstract theoretical frameworks in hardware. While this is good from a modeling and analysis perspective, it may not lead to the most efficient hardware. On the other hand, exploiting hardware dynamics to build adaptive systems rather than forcing the hardware to behave like mathematical equations, seems to be a more robust methodology when it comes to developing actual hardware for real world applications. In this paper we use a novel time-staggered Winner Take All circuit, that exploits the adaptation dynamics of floating gate transistors, to model an adaptive cortical cell that demonstrates Orientation Selectivity, a well-known biological phenomenon observed in the visual cortex. The cell performs competitive learning, refining its weights in response to input patterns resembling different oriented bars, becoming selective to a particular oriented pattern. Different analysis performed on the cell such as orientation tuning, application of abnormal inputs, response to spatial frequency and periodic patterns reveal close similarity between our cell and its biological counterpart. Embedded in a RC grid, these cells interact diffusively exhibiting cluster formation, making way for adaptively building orientation selective maps

Integrated neuron circuit for implementing neuromorphic system with synaptic device

Science.gov (United States)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

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Andreas Stöckel

2017-08-01

Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Directory of Open Access Journals (Sweden)

Sergio Saponara

2004-09-01

Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

A Knowledge Based Approach to VLSI CAD

Science.gov (United States)

1983-09-01

Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

OpenAIRE

Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

2018-01-01

Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

Optimized pulsed write schemes improve linearity and write speed for low-power organic neuromorphic devices

Science.gov (United States)

Keene, Scott T.; Melianas, Armantas; Fuller, Elliot J.; van de Burgt, Yoeri; Talin, A. Alec; Salleo, Alberto

2018-06-01

Neuromorphic devices are becoming increasingly appealing as efficient emulators of neural networks used to model real world problems. However, no hardware to date has demonstrated the necessary high accuracy and energy efficiency gain over CMOS in both (1) training via backpropagation and (2) in read via vector matrix multiplication. Such shortcomings are due to device non-idealities, particularly asymmetric conductance tuning in response to uniform voltage pulse inputs. Here, by formulating a general circuit model for capacitive ion-exchange neuromorphic devices, we show that asymmetric nonlinearity in organic electrochemical neuromorphic devices (ENODes) can be suppressed by an appropriately chosen write scheme. Simulations based upon our model suggest that a nonlinear write-selector could reduce the switching voltage and energy, enabling analog tuning via a continuous set of resistance states (100 states) with extremely low switching energy (~170 fJ · µm‑2). This work clarifies the pathway to neural algorithm accelerators capable of parallelism during both read and write operations.

A robust and scalable neuromorphic communication system by combining synaptic time multiplexing and MIMO-OFDM.

Science.gov (United States)

Srinivasa, Narayan; Zhang, Deying; Grigorian, Beayna

2014-03-01

This paper describes a novel architecture for enabling robust and efficient neuromorphic communication. The architecture combines two concepts: 1) synaptic time multiplexing (STM) that trades space for speed of processing to create an intragroup communication approach that is firing rate independent and offers more flexibility in connectivity than cross-bar architectures and 2) a wired multiple input multiple output (MIMO) communication with orthogonal frequency division multiplexing (OFDM) techniques to enable a robust and efficient intergroup communication for neuromorphic systems. The MIMO-OFDM concept for the proposed architecture was analyzed by simulating large-scale spiking neural network architecture. Analysis shows that the neuromorphic system with MIMO-OFDM exhibits robust and efficient communication while operating in real time with a high bit rate. Through combining STM with MIMO-OFDM techniques, the resulting system offers a flexible and scalable connectivity as well as a power and area efficient solution for the implementation of very large-scale spiking neural architectures in hardware.

Neuromorphic Computing – From Materials Research to Systems Architecture Roundtable

Energy Technology Data Exchange (ETDEWEB)

Schuller, Ivan K. [Univ. of California, San Diego, CA (United States); Stevens, Rick [Argonne National Lab. (ANL), Argonne, IL (United States); Univ. of Chicago, IL (United States); Pino, Robinson [Dept. of Energy (DOE) Office of Science, Washington, DC (United States); Pechan, Michael [Dept. of Energy (DOE) Office of Science, Washington, DC (United States)

2015-10-29

Computation in its many forms is the engine that fuels our modern civilization. Modern computation—based on the von Neumann architecture—has allowed, until now, the development of continuous improvements, as predicted by Moore’s law. However, computation using current architectures and materials will inevitably—within the next 10 years—reach a limit because of fundamental scientific reasons. DOE convened a roundtable of experts in neuromorphic computing systems, materials science, and computer science in Washington on October 29-30, 2015 to address the following basic questions: Can brain-like (“neuromorphic”) computing devices based on new material concepts and systems be developed to dramatically outperform conventional CMOS based technology? If so, what are the basic research challenges for materials sicence and computing? The overarching answer that emerged was: The development of novel functional materials and devices incorporated into unique architectures will allow a revolutionary technological leap toward the implementation of a fully “neuromorphic” computer. To address this challenge, the following issues were considered: The main differences between neuromorphic and conventional computing as related to: signaling models, timing/clock, non-volatile memory, architecture, fault tolerance, integrated memory and compute, noise tolerance, analog vs. digital, and in situ learning New neuromorphic architectures needed to: produce lower energy consumption, potential novel nanostructured materials, and enhanced computation Device and materials properties needed to implement functions such as: hysteresis, stability, and fault tolerance Comparisons of different implementations: spin torque, memristors, resistive switching, phase change, and optical schemes for enhanced breakthroughs in performance, cost, fault tolerance, and/or manufacturability.

Encoding neural and synaptic functionalities in electron spin: A pathway to efficient neuromorphic computing

Science.gov (United States)

Sengupta, Abhronil; Roy, Kaushik

2017-12-01

Present day computers expend orders of magnitude more computational resources to perform various cognitive and perception related tasks that humans routinely perform every day. This has recently resulted in a seismic shift in the field of computation where research efforts are being directed to develop a neurocomputer that attempts to mimic the human brain by nanoelectronic components and thereby harness its efficiency in recognition problems. Bridging the gap between neuroscience and nanoelectronics, this paper attempts to provide a review of the recent developments in the field of spintronic device based neuromorphic computing. Description of various spin-transfer torque mechanisms that can be potentially utilized for realizing device structures mimicking neural and synaptic functionalities is provided. A cross-layer perspective extending from the device to the circuit and system level is presented to envision the design of an All-Spin neuromorphic processor enabled with on-chip learning functionalities. Device-circuit-algorithm co-simulation framework calibrated to experimental results suggest that such All-Spin neuromorphic systems can potentially achieve almost two orders of magnitude energy improvement in comparison to state-of-the-art CMOS implementations.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

Science.gov (United States)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Advanced symbolic analysis for VLSI systems methods and applications

CERN Document Server

Shi, Guoyong; Tlelo Cuautle, Esteban

2014-01-01

This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

VLSI structures for track finding

International Nuclear Information System (INIS)

Dell'Orso, M.

1989-01-01

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

CERN Document Server

Williams, John

2008-01-01

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

Science.gov (United States)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

International Nuclear Information System (INIS)

Riggert, C; Ziegler, M; Kohlstedt, H; Schroeder, D; Krautschneider, W H

2014-01-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit. (paper)

Numerical analysis of electromigration in thin film VLSI interconnections

NARCIS (Netherlands)

Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

1995-01-01

Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

Heavy ion tests on programmable VLSI

International Nuclear Information System (INIS)

Provost-Grellier, A.

1989-11-01

The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems.

Science.gov (United States)

Stefanini, Fabio; Neftci, Emre O; Sheik, Sadique; Indiveri, Giacomo

2014-01-01

Neuromorphic hardware offers an electronic substrate for the realization of asynchronous event-based sensory-motor systems and large-scale spiking neural network architectures. In order to characterize these systems, configure them, and carry out modeling experiments, it is often necessary to interface them to workstations. The software used for this purpose typically consists of a large monolithic block of code which is highly specific to the hardware setup used. While this approach can lead to highly integrated hardware/software systems, it hampers the development of modular and reconfigurable infrastructures thus preventing a rapid evolution of such systems. To alleviate this problem, we propose PyNCS, an open-source front-end for the definition of neural network models that is interfaced to the hardware through a set of Python Application Programming Interfaces (APIs). The design of PyNCS promotes modularity, portability and expandability and separates implementation from hardware description. The high-level front-end that comes with PyNCS includes tools to define neural network models as well as to create, monitor and analyze spiking data. Here we report the design philosophy behind the PyNCS framework and describe its implementation. We demonstrate its functionality with two representative case studies, one using an event-based neuromorphic vision sensor, and one using a set of multi-neuron devices for carrying out a cognitive decision-making task involving state-dependent computation. PyNCS, already applicable to a wide range of existing spike-based neuromorphic setups, will accelerate the development of hybrid software/hardware neuromorphic systems, thanks to its code flexibility. The code is open-source and available online at https://github.com/inincs/pyNCS.

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems

Science.gov (United States)

Stefanini, Fabio; Neftci, Emre O.; Sheik, Sadique; Indiveri, Giacomo

2014-01-01

Neuromorphic hardware offers an electronic substrate for the realization of asynchronous event-based sensory-motor systems and large-scale spiking neural network architectures. In order to characterize these systems, configure them, and carry out modeling experiments, it is often necessary to interface them to workstations. The software used for this purpose typically consists of a large monolithic block of code which is highly specific to the hardware setup used. While this approach can lead to highly integrated hardware/software systems, it hampers the development of modular and reconfigurable infrastructures thus preventing a rapid evolution of such systems. To alleviate this problem, we propose PyNCS, an open-source front-end for the definition of neural network models that is interfaced to the hardware through a set of Python Application Programming Interfaces (APIs). The design of PyNCS promotes modularity, portability and expandability and separates implementation from hardware description. The high-level front-end that comes with PyNCS includes tools to define neural network models as well as to create, monitor and analyze spiking data. Here we report the design philosophy behind the PyNCS framework and describe its implementation. We demonstrate its functionality with two representative case studies, one using an event-based neuromorphic vision sensor, and one using a set of multi-neuron devices for carrying out a cognitive decision-making task involving state-dependent computation. PyNCS, already applicable to a wide range of existing spike-based neuromorphic setups, will accelerate the development of hybrid software/hardware neuromorphic systems, thanks to its code flexibility. The code is open-source and available online at https://github.com/inincs/pyNCS. PMID:25232314

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

Design of two easily-testable VLSI array multipliers

Energy Technology Data Exchange (ETDEWEB)

Ferguson, J.; Shen, J.P.

1983-01-01

Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

Regenerative memory in time-delayed neuromorphic photonic resonators

OpenAIRE

Romeira, B.; Avó, R.; Figueiredo, José M. L.; Barland, S.; Javaloyes, J.

2016-01-01

We investigate a photonic regenerative memory based upon a neuromorphic oscillator with a delayed self-feedback (autaptic) connection. We disclose the existence of a unique temporal response characteristic of localized structures enabling an ideal support for bits in an optical buffer memory for storage and reshaping of data information. We link our experimental implementation, based upon a nanoscale nonlinear resonant tunneling diode driving a laser, to the paradigm of neuronal activity, the...

Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

Science.gov (United States)

Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

2018-03-01

The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

Applications of VLSI circuits to medical imaging

International Nuclear Information System (INIS)

O'Donnell, M.

1988-01-01

In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

Noise-exploitation and adaptation in neuromorphic sensors

Science.gov (United States)

Hindo, Thamira; Chakrabartty, Shantanu

2012-04-01

Even though current micro-nano fabrication technology has reached integration levels where ultra-sensitive sensors can be fabricated, the sensing performance (resolution per joule) of synthetic systems are still orders of magnitude inferior to those observed in neurobiology. For example, the filiform hairs in crickets operate at fundamental limits of noise; auditory sensors in a parasitoid fly can overcome fundamental limitations to precisely localize ultra-faint acoustic signatures. Even though many of these biological marvels have served as inspiration for different types of neuromorphic sensors, the main focus these designs have been to faithfully replicate the biological functionalities, without considering the constructive role of "noise". In man-made sensors device and sensor noise are typically considered as a nuisance, where as in neurobiology "noise" has been shown to be a computational aid that enables biology to sense and operate at fundamental limits of energy efficiency and performance. In this paper, we describe some of the important noise-exploitation and adaptation principles observed in neurobiology and how they can be systematically used for designing neuromorphic sensors. Our focus will be on two types of noise-exploitation principles, namely, (a) stochastic resonance; and (b) noise-shaping, which are unified within our previously reported framework called Σ▵ learning. As a case-study, we describe the application of Σ▵ learning for the design of a miniature acoustic source localizer whose performance matches that of its biological counterpart(Ormia Ochracea).

Large-scale simulations of plastic neural networks on neuromorphic hardware

Directory of Open Access Journals (Sweden)

James Courtney Knight

2016-04-01

Full Text Available SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Rather than using bespoke analog or digital hardware, the basic computational unit of a SpiNNaker system is a general-purpose ARM processor, allowing it to be programmed to simulate a wide variety of neuron and synapse models. This flexibility is particularly valuable in the study of biological plasticity phenomena. A recently proposed learning rule based on the Bayesian Confidence Propagation Neural Network (BCPNN paradigm offers a generic framework for modeling the interaction of different plasticity mechanisms using spiking neurons. However, it can be computationally expensive to simulate large networks with BCPNN learning since it requires multiple state variables for each synapse, each of which needs to be updated every simulation time-step. We discuss the trade-offs in efficiency and accuracy involved in developing an event-based BCPNN implementation for SpiNNaker based on an analytical solution to the BCPNN equations, and detail the steps taken to fit this within the limited computational and memory resources of the SpiNNaker architecture. We demonstrate this learning rule by learning temporal sequences of neural activity within a recurrent attractor network which we simulate at scales of up to 20000 neurons and 51200000 plastic synapses: the largest plastic neural network ever to be simulated on neuromorphic hardware. We also run a comparable simulation on a Cray XC-30 supercomputer system and find that, if it is to match the run-time of our SpiNNaker simulation, the super computer system uses approximately more power. This suggests that cheaper, more power efficient neuromorphic systems are becoming useful discovery tools in the study of plasticity in large-scale brain models.

Memristive and neuromorphic behavior in a LixCoO2 nanobattery

Science.gov (United States)

Mai, V. H.; Moradpour, A.; Senzier, P. Auban; Pasquier, C.; Wang, K.; Rozenberg, M. J.; Giapintzakis, J.; Mihailescu, C. N.; Orfanidou, C. M.; Svoukis, E.; Breza, A.; Lioutas, Ch B.; Franger, S.; Revcolevschi, A.; Maroutian, T.; Lecoeur, P.; Aubert, P.; Agnus, G.; Salot, R.; Albouy, P. A.; Weil, R.; Alamarguy, D.; March, K.; Jomard, F.; Chrétien, P.; Schneegans, O.

2015-01-01

The phenomenon of resistive switching (RS), which was initially linked to non-volatile resistive memory applications, has recently also been associated with the concept of memristors, whose adjustable multilevel resistance characteristics open up unforeseen perspectives in cognitive computing. Herein, we demonstrate that the resistance states of LixCoO2 thin film-based metal-insulator-metal (MIM) solid-state cells can be tuned by sequential programming voltage pulses, and that these resistance states are dramatically dependent on the pulses input rate, hence emulating biological synapse plasticity. In addition, we identify the underlying electrochemical processes of RS in our MIM cells, which also reveal a nanobattery-like behavior, leading to the generation of electrical signals that bring an unprecedented new dimension to the connection between memristors and neuromorphic systems. Therefore, these LixCoO2-based MIM devices allow for a combination of possibilities, offering new perspectives of usage in nanoelectronics and bio-inspired neuromorphic circuits.

Neuromodulated Synaptic Plasticity on the SpiNNaker Neuromorphic System

Directory of Open Access Journals (Sweden)

Mantas Mikaitis

2018-02-01

Full Text Available SpiNNaker is a digital neuromorphic architecture, designed specifically for the low power simulation of large-scale spiking neural networks at speeds close to biological real-time. Unlike other neuromorphic systems, SpiNNaker allows users to develop their own neuron and synapse models as well as specify arbitrary connectivity. As a result SpiNNaker has proved to be a powerful tool for studying different neuron models as well as synaptic plasticity—believed to be one of the main mechanisms behind learning and memory in the brain. A number of Spike-Timing-Dependent-Plasticity(STDP rules have already been implemented on SpiNNaker and have been shown to be capable of solving various learning tasks in real-time. However, while STDP is an important biological theory of learning, it is a form of Hebbian or unsupervised learning and therefore does not explain behaviors that depend on feedback from the environment. Instead, learning rules based on neuromodulated STDP (three-factor learning rules have been shown to be capable of solving reinforcement learning tasks in a biologically plausible manner. In this paper we demonstrate for the first time how a model of three-factor STDP, with the third-factor representing spikes from dopaminergic neurons, can be implemented on the SpiNNaker neuromorphic system. Using this learning rule we first show how reward and punishment signals can be delivered to a single synapse before going on to demonstrate it in a larger network which solves the credit assignment problem in a Pavlovian conditioning experiment. Because of its extra complexity, we find that our three-factor learning rule requires approximately 2× as much processing time as the existing SpiNNaker STDP learning rules. However, we show that it is still possible to run our Pavlovian conditioning model with up to 1 × 104 neurons in real-time, opening up new research opportunities for modeling behavioral learning on SpiNNaker.

An Application Development Platform for Neuromorphic Computing

Energy Technology Data Exchange (ETDEWEB)

Dean, Mark [University of Tennessee (UT); Chan, Jason [University of Tennessee (UT); Daffron, Christopher [University of Tennessee (UT); Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT); Rose, Garrett [University of Tennessee (UT); Plank, James [University of Tennessee (UT); Birdwell, John Douglas [University of Tennessee (UT); Schuman, Catherine D [ORNL

2016-01-01

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic computing systems developed as a hardware based approach to the implementation of neural networks. They feature highly adaptive and programmable structural elements, which model arti cial neural networks with spiking behavior. We design them to solve problems using evolutionary optimization. In this paper, we highlight the current hardware and software implementations of DANNA, including their features, functionalities and performance. We then describe the development of an Application Development Platform (ADP) to support efficient application implementation and testing of DANNA based solutions. We conclude with future directions.

VLSI top-down design based on the separation of hierarchies

NARCIS (Netherlands)

Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

1986-01-01

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

VLSI Design with Alliance Free CAD Tools: an Implementation Example

Directory of Open Access Journals (Sweden)

Chávez-Bracamontes Ramón

2015-07-01

Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

Development of Radhard VLSI electronics for SSC calorimeters

International Nuclear Information System (INIS)

Dawson, J.W.; Nodulman, L.J.

1989-01-01

A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Directory of Open Access Journals (Sweden)

Rachmad Vidya Wicaksana Putra

2016-06-01

Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Event-Based Computation of Motion Flow on a Neuromorphic Analog Neural Platform.

Science.gov (United States)

Giulioni, Massimiliano; Lagorce, Xavier; Galluppi, Francesco; Benosman, Ryad B

2016-01-01

Estimating the speed and direction of moving objects is a crucial component of agents behaving in a dynamic world. Biological organisms perform this task by means of the neural connections originating from their retinal ganglion cells. In artificial systems the optic flow is usually extracted by comparing activity of two or more frames captured with a vision sensor. Designing artificial motion flow detectors which are as fast, robust, and efficient as the ones found in biological systems is however a challenging task. Inspired by the architecture proposed by Barlow and Levick in 1965 to explain the spiking activity of the direction-selective ganglion cells in the rabbit's retina, we introduce an architecture for robust optical flow extraction with an analog neuromorphic multi-chip system. The task is performed by a feed-forward network of analog integrate-and-fire neurons whose inputs are provided by contrast-sensitive photoreceptors. Computation is supported by the precise time of spike emission, and the extraction of the optical flow is based on time lag in the activation of nearby retinal neurons. Mimicking ganglion cells our neuromorphic detectors encode the amplitude and the direction of the apparent visual motion in their output spiking pattern. Hereby we describe the architectural aspects, discuss its latency, scalability, and robustness properties and demonstrate that a network of mismatched delicate analog elements can reliably extract the optical flow from a simple visual scene. This work shows how precise time of spike emission used as a computational basis, biological inspiration, and neuromorphic systems can be used together for solving specific tasks.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

Energy Technology Data Exchange (ETDEWEB)

Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

A robust sound perception model suitable for neuromorphic implementation.

Science.gov (United States)

Coath, Martin; Sheik, Sadique; Chicca, Elisabetta; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas

2013-01-01

We have recently demonstrated the emergence of dynamic feature sensitivity through exposure to formative stimuli in a real-time neuromorphic system implementing a hybrid analog/digital network of spiking neurons. This network, inspired by models of auditory processing in mammals, includes several mutually connected layers with distance-dependent transmission delays and learning in the form of spike timing dependent plasticity, which effects stimulus-driven changes in the network connectivity. Here we present results that demonstrate that the network is robust to a range of variations in the stimulus pattern, such as are found in naturalistic stimuli and neural responses. This robustness is a property critical to the development of realistic, electronic neuromorphic systems. We analyze the variability of the response of the network to "noisy" stimuli which allows us to characterize the acuity in information-theoretic terms. This provides an objective basis for the quantitative comparison of networks, their connectivity patterns, and learning strategies, which can inform future design decisions. We also show, using stimuli derived from speech samples, that the principles are robust to other challenges, such as variable presentation rate, that would have to be met by systems deployed in the real world. Finally we demonstrate the potential applicability of the approach to real sounds.

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications.

Science.gov (United States)

Bavandpour, Mohammad; Soleimani, Hamid; Linares-Barranco, Bernabé; Abbott, Derek; Chua, Leon O

2015-01-01

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n (2) memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach.

A Robust Sound Perception Model Suitable for Neuromorphic Implementation

Directory of Open Access Journals (Sweden)

Martin eCoath

2014-01-01

Full Text Available We have recently demonstrated the emergence of dynamic feature sensitivity through exposure to formative stimuli in a real-time neuromorphic system implementing a hybrid analogue/digital network of spiking neurons. This network, inspired by models of auditory processing in mammals, includes several mutually connected layers with distance-dependent transmission delays and learning in the form of spike timing dependent plasticity, which effects stimulus-driven changes in the network connectivity.Here we present results that demonstrate that the network is robust to a range of variations in the stimulus pattern, such as are found in naturalistic stimuli and neural responses. This robustness is a property critical to the development of realistic, electronic neuromorphic systems.We analyse the variability of the response of the network to `noisy' stimuli which allows us to characterize the acuity in information-theoretic terms. This provides an objective basis for the quantitative comparison of networks, their connectivity patterns, and learning strategies, which can inform future design decisions. We also show, using stimuli derived from speech samples, that the principles are robust to other challenges, such as variable presentation rate, that would have to be met by systems deployed in the real world. Finally we demonstrate the potential applicability of the approach to real sounds.

Neuromorphic optical sensor chip with color change-intensity change disambiguation

Science.gov (United States)

Fu, ZhenHong; Mao, Rui; Cartwright, Alexander N.; Titus, Albert H.

2010-02-01

In this paper, we describe the development of a novel, retina-like neuromorphic chip that has an array of two types of retina 'cells' arranged to mimic the fovea structure in certain animals. One of the two retina cell types performs irradiance detection and the other can perform color detection. Together, via the two parallel pathways the retina chip can perform color change intensity change disambiguation (CCICD). The irradiance detection cell has a wide-dynamic detection range that spans almost 3 orders of magnitude. The color detection cell has a buried double junction (BDJ) photodiode as the photoreceptor followed by two parallel logarithmic I-V convertors. The output from this is a color response which has at least a 50nm resolution for wavelengths from 400nm to 900nm. With these two cells, the array can perform color change -intensity change disambiguation (CCICD) to determine if a change in the output of the irradiance pathway is because of irradiance change, color change, or both. This biological retina-like neuromorphic sensor array is implemented in ON-SEMI 0.5μm technology, a standard CMOS fabrication process available at MOSIS.

Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.

Science.gov (United States)

Brink, S; Nease, S; Hasler, P

2013-09-01

Results are presented from several spiking network experiments performed on a novel neuromorphic integrated circuit. The networks are discussed in terms of their computational significance, which includes applications such as arbitrary spatiotemporal pattern generation and recognition, winner-take-all competition, stable generation of rhythmic outputs, and volatile memory. Analogies to the behavior of real biological neural systems are also noted. The alternatives for implementing the same computations are discussed and compared from a computational efficiency standpoint, with the conclusion that implementing neural networks on neuromorphic hardware is significantly more power efficient than numerical integration of model equations on traditional digital hardware. Copyright © 2013 Elsevier Ltd. All rights reserved.

VLSI architectures for modern error-correcting codes

CERN Document Server

Zhang, Xinmiao

2015-01-01

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

VLSI Design of Trusted Virtual Sensors

Directory of Open Access Journals (Sweden)

Macarena C. Martínez-Rodríguez

2018-01-01

Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

VLSI Design of Trusted Virtual Sensors.

Science.gov (United States)

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

Science.gov (United States)

Wang, Runchun M; Thakur, Chetan S; van Schaik, André

2018-01-01

This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

Event-Driven Contrastive Divergence for Spiking Neuromorphic Systems

Directory of Open Access Journals (Sweden)

Emre eNeftci

2014-01-01

Full Text Available Restricted Boltzmann Machines (RBMs and Deep Belief Networks have been demonstrated to perform efficiently in variety of applications, such as dimensionality reduction, feature learning, and classification. Their implementation on neuromorphic hardware platforms emulating large-scale networks of spiking neurons can have significant advantages from the perspectives of scalability, power dissipation and real-time interfacing with the environment. However the traditional RBM architecture and the commonly used training algorithm known as Contrastive Divergence (CD are based on discrete updates and exact arithmetics which do not directly map onto a dynamical neural substrate. Here, we present an event-driven variation of CD to train a RBM constructed with Integrate & Fire (I&F neurons, that is constrained by the limitations of existing and near future neuromorphic hardware platforms. Our strategy is based on neural sampling, which allows us to synthesize a spiking neural network that samples from a target Boltzmann distribution. The reverberating activity of the network replaces the discrete steps of the CD algorithm, while Spike Time Dependent Plasticity (STDP carries out the weight updates in an online, asynchronous fashion.We demonstrate our approach by training an RBM composed of leaky I&F neurons with STDP synapses to learn a generative model of the MNIST hand-written digit dataset, and by testing it in recognition, generation and cue integration tasks. Our results contribute to a machine learning-driven approach for synthesizing networks of spiking neurons capable of carrying out practical, high-level functionality.

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

Directory of Open Access Journals (Sweden)

Runchun M. Wang

2018-04-01

Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

Event-driven contrastive divergence for spiking neuromorphic systems.

Science.gov (United States)

Neftci, Emre; Das, Srinjoy; Pedroni, Bruno; Kreutz-Delgado, Kenneth; Cauwenberghs, Gert

2013-01-01

Restricted Boltzmann Machines (RBMs) and Deep Belief Networks have been demonstrated to perform efficiently in a variety of applications, such as dimensionality reduction, feature learning, and classification. Their implementation on neuromorphic hardware platforms emulating large-scale networks of spiking neurons can have significant advantages from the perspectives of scalability, power dissipation and real-time interfacing with the environment. However, the traditional RBM architecture and the commonly used training algorithm known as Contrastive Divergence (CD) are based on discrete updates and exact arithmetics which do not directly map onto a dynamical neural substrate. Here, we present an event-driven variation of CD to train a RBM constructed with Integrate & Fire (I&F) neurons, that is constrained by the limitations of existing and near future neuromorphic hardware platforms. Our strategy is based on neural sampling, which allows us to synthesize a spiking neural network that samples from a target Boltzmann distribution. The recurrent activity of the network replaces the discrete steps of the CD algorithm, while Spike Time Dependent Plasticity (STDP) carries out the weight updates in an online, asynchronous fashion. We demonstrate our approach by training an RBM composed of leaky I&F neurons with STDP synapses to learn a generative model of the MNIST hand-written digit dataset, and by testing it in recognition, generation and cue integration tasks. Our results contribute to a machine learning-driven approach for synthesizing networks of spiking neurons capable of carrying out practical, high-level functionality.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

Science.gov (United States)

Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

2003-01-01

Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

2008-01-21

In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

Synapse-centric mapping of cortical models to the SpiNNaker neuromorphic architecture

Directory of Open Access Journals (Sweden)

James Courtney Knight

2016-09-01

Full Text Available While the adult human brain has approximately 8.8x10^10 neurons, this number is dwarfed by its 1x10^15 synapses. From the point of view of neuromorphic engineering and neural simulation in general this makes the simulation of these synapses a particularly complex problem. SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Current solutions for simulating spiking neural networks on SpiNNaker are heavily inspired by work on distributed high-performance computing. However, while SpiNNaker shares many characteristics with such distributed systems, its component nodes have much more limited resources and, as the system lacks global synchronization, the computation performed on each node must complete within a fixed time step. We first analyze the performance of the current SpiNNaker neural simulation software and identify several problems that occur when it is used to simulate networks of the type often used to model the cortex which contain large numbers of sparsely connected synapses. We then present a new, more flexible approach for mapping the simulation of such networks to SpiNNaker which solves many of these problems. Finally we analyze the performance of our new approach using both benchmarks, designed to represent cortical connectivity, and larger, functional cortical models. In a benchmark network where neurons receive input from 8000 STDP synapses, our new approach allows more neurons to be simulated on each SpiNNaker core than has been previously possible. We also demonstrate that the largest plastic neural network previously simulated on neuromorphic hardware can be run in real time using our new approach: double the speed that was previously achieved. Additionally this network contains two types of plastic synapse which previously had to be trained separately but, using our new approach, can be trained simultaneously.

Proprioceptive Feedback through a Neuromorphic Muscle Spindle Model

Directory of Open Access Journals (Sweden)

Lorenzo Vannucci

2017-06-01

Full Text Available Connecting biologically inspired neural simulations to physical or simulated embodiments can be useful both in robotics, for the development of a new kind of bio-inspired controllers, and in neuroscience, to test detailed brain models in complete action-perception loops. The aim of this work is to develop a fully spike-based, biologically inspired mechanism for the translation of proprioceptive feedback. The translation is achieved by implementing a computational model of neural activity of type Ia and type II afferent fibers of muscle spindles, the primary source of proprioceptive information, which, in mammals is regulated through fusimotor activation and provides necessary adjustments during voluntary muscle contractions. As such, both static and dynamic γ-motoneurons activities are taken into account in the proposed model. Information from the actual proprioceptive sensors (i.e., motor encoders is then used to simulate the spindle contraction and relaxation, and therefore drive the neural activity. To assess the feasibility of this approach, the model is implemented on the NEST spiking neural network simulator and on the SpiNNaker neuromorphic hardware platform and tested on simulated and physical robotic platforms. The results demonstrate that the model can be used in both simulated and real-time robotic applications to translate encoder values into a biologically plausible neural activity. Thus, this model provides a completely spike-based building block, suitable for neuromorphic platforms, that will enable the development of sensory-motor closed loops which could include neural simulations of areas of the central nervous system or of low-level reflexes.

Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines

OpenAIRE

Neftci, Emre O.; Augustine, Charles; Paul, Somnath; Detorakis, Georgios

2017-01-01

An ongoing challenge in neuromorphic computing is to devise general and computationally efficient models of inference and learning which are compatible with the spatial and temporal constraints of the brain. One increasingly popular and successful approach is to take inspiration from inference and learning algorithms used in deep neural networks. However, the workhorse of deep learning, the gradient descent Gradient Back Propagation (BP) rule, often relies on the immediate availability of net...

Development of Neuromorphic Sift Operator with Application to High Speed Image Matching

Science.gov (United States)

Shankayi, M.; Saadatseresht, M.; Bitetto, M. A. V.

2015-12-01

There was always a speed/accuracy challenge in photogrammetric mapping process, including feature detection and matching. Most of the researches have improved algorithm's speed with simplifications or software modifications which increase the accuracy of the image matching process. This research tries to improve speed without enhancing the accuracy of the same algorithm using Neuromorphic techniques. In this research we have developed a general design of a Neuromorphic ASIC to handle algorithms such as SIFT. We also have investigated neural assignment in each step of the SIFT algorithm. With a rough estimation based on delay of the used elements including MAC and comparator, we have estimated the resulting chip's performance for 3 scenarios, Full HD movie (Videogrammetry), 24 MP (UAV photogrammetry), and 88 MP image sequence. Our estimations led to approximate 3000 fps for Full HD movie, 250 fps for 24 MP image sequence and 68 fps for 88MP Ultracam image sequence which can be a huge improvement for current photogrammetric processing systems. We also estimated the power consumption of less than10 watts which is not comparable to current workflows.

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications

International Nuclear Information System (INIS)

Linn, E; Ferch, S; Waser, R; Menzel, S

2013-01-01

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications. (paper)

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Science.gov (United States)

Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B. D.; Adam, G. C.; Likharev, K. K.; Strukov, D. B.

2015-05-01

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 1014 synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

A forecast-based STDP rule suitable for neuromorphic implementation.

Science.gov (United States)

Davies, S; Galluppi, F; Rast, A D; Furber, S B

2012-08-01

Artificial neural networks increasingly involve spiking dynamics to permit greater computational efficiency. This becomes especially attractive for on-chip implementation using dedicated neuromorphic hardware. However, both spiking neural networks and neuromorphic hardware have historically found difficulties in implementing efficient, effective learning rules. The best-known spiking neural network learning paradigm is Spike Timing Dependent Plasticity (STDP) which adjusts the strength of a connection in response to the time difference between the pre- and post-synaptic spikes. Approaches that relate learning features to the membrane potential of the post-synaptic neuron have emerged as possible alternatives to the more common STDP rule, with various implementations and approximations. Here we use a new type of neuromorphic hardware, SpiNNaker, which represents the flexible "neuromimetic" architecture, to demonstrate a new approach to this problem. Based on the standard STDP algorithm with modifications and approximations, a new rule, called STDP TTS (Time-To-Spike) relates the membrane potential with the Long Term Potentiation (LTP) part of the basic STDP rule. Meanwhile, we use the standard STDP rule for the Long Term Depression (LTD) part of the algorithm. We show that on the basis of the membrane potential it is possible to make a statistical prediction of the time needed by the neuron to reach the threshold, and therefore the LTP part of the STDP algorithm can be triggered when the neuron receives a spike. In our system these approximations allow efficient memory access, reducing the overall computational time and the memory bandwidth required. The improvements here presented are significant for real-time applications such as the ones for which the SpiNNaker system has been designed. We present simulation results that show the efficacy of this algorithm using one or more input patterns repeated over the whole time of the simulation. On-chip results show that

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Drift chamber tracking with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-10-01

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

Computational intelligence and neuromorphic computing potential for cybersecurity applications

Science.gov (United States)

Pino, Robinson E.; Shevenell, Michael J.; Cam, Hasan; Mouallem, Pierre; Shumaker, Justin L.; Edwards, Arthur H.

2013-05-01

In today's highly mobile, networked, and interconnected internet world, the flow and volume of information is overwhelming and continuously increasing. Therefore, it is believed that the next frontier in technological evolution and development will rely in our ability to develop intelligent systems that can help us process, analyze, and make-sense of information autonomously just as a well-trained and educated human expert. In computational intelligence, neuromorphic computing promises to allow for the development of computing systems able to imitate natural neurobiological processes and form the foundation for intelligent system architectures.

High-energy heavy ion testing of VLSI devices for single event ...

Indian Academy of Sciences (India)

Unknown

per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

The AMchip: A VLSI associative memory for track finding

International Nuclear Information System (INIS)

Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

1992-01-01

An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

Point DCT VLSI Architecture for Emerging HEVC Standard

OpenAIRE

Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

2012-01-01

This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

VLSI architecture and design for the Fermat Number Transform implementation

Energy Technology Data Exchange (ETDEWEB)

Pajayakrit, A.

1987-01-01

A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

Regenerative memory in time-delayed neuromorphic photonic resonators

Science.gov (United States)

Romeira, B.; Avó, R.; Figueiredo, José M. L.; Barland, S.; Javaloyes, J.

2016-01-01

We investigate a photonic regenerative memory based upon a neuromorphic oscillator with a delayed self-feedback (autaptic) connection. We disclose the existence of a unique temporal response characteristic of localized structures enabling an ideal support for bits in an optical buffer memory for storage and reshaping of data information. We link our experimental implementation, based upon a nanoscale nonlinear resonant tunneling diode driving a laser, to the paradigm of neuronal activity, the FitzHugh-Nagumo model with delayed feedback. This proof-of-concept photonic regenerative memory might constitute a building block for a new class of neuron-inspired photonic memories that can handle high bit-rate optical signals.

Neuromorphic VLSI vision system for real-time texture segregation.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

Using Software Technology to Specify Abstract Interfaces in VLSI Design.

Science.gov (United States)

1985-01-01

with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

Flexible Metal Oxide/Graphene Oxide Hybrid Neuromorphic Devices on Flexible Conducting Graphene Substrates

OpenAIRE

Wan, Chang Jin; Wang, Wei; Zhu, Li Qiang; Liu, Yang Hui; Feng, Ping; Liu, Zhao Ping; Shi, Yi; Wan, Qing

2016-01-01

Flexible metal oxide/graphene oxide hybrid multi-gate neuron transistors were fabricated on flexible graphene substrates. Dendritic integrations in both spatial and temporal modes were successfully emulated, and spatiotemporal correlated logics were obtained. A proof-of-principle visual system model for emulating lobula giant motion detector neuron was investigated. Our results are of great interest for flexible neuromorphic cognitive systems.

VLSI Technology for Cognitive Radio

Science.gov (United States)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

Science.gov (United States)

Shi, Cong; Luo, Gang

2018-04-01

This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

Directory of Open Access Journals (Sweden)

Di Wu

2010-01-01

Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

A multi coding technique to reduce transition activity in VLSI circuits

International Nuclear Information System (INIS)

Vithyalakshmi, N.; Rajaram, M.

2014-01-01

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

Science.gov (United States)

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

International Nuclear Information System (INIS)

Jian Haifang; Shi Yin

2009-01-01

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

Energy Technology Data Exchange (ETDEWEB)

Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-07-15

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

Design of a VLSI Decoder for Partially Structured LDPC Codes

Directory of Open Access Journals (Sweden)

Fabrizio Vacca

2008-01-01

of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

Event-Based Computation of Motion Flow on a Neuromorphic Analog Neural Platform

Directory of Open Access Journals (Sweden)

Massimiliano eGiulioni

2016-02-01

Full Text Available We demonstrate robust optical flow extraction with an analog neuromorphic multi-chip system. The task is performed by a feed-forward network of analog integrate-and-fire neurons whose inputs are provided by contrast-sensitive photoreceptors. Computation is supported by the precise time of spike emission and follows the basic theoretical principles presented in (Benosman et al. 2014: the extraction of the optical flow is based on time lag in the activation of nearby retinal neurons. The same basic principle is embedded in the architecture proposed by Barlow and Levick in 1965 to explain the spiking activity of the direction-selective ganglion cells in the rabbit's retina. Mimicking those cells our neuromorphic detectors encode the amplitude and the direction of the apparent visual motion in their output spiking pattern. We built a 3x3 test grid of independent detectors, each observing a different portion of the scene, so that our final output is a spike train encoding a 3x3 optical flow vector field. In this work we focus on the architectural aspects, and we demonstrate that a network of mismatched delicate analog elements can reliably extract the optical flow from a simple visual scene.

Formal verification an essential toolkit for modern VLSI design

CERN Document Server

Seligman, Erik; Kumar, M V Achutha Kiran

2015-01-01

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

DPL/Daedalus design environment (for VLSI)

Energy Technology Data Exchange (ETDEWEB)

Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

1981-01-01

The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

DEFF Research Database (Denmark)

Paaske, Erik; Pedersen, Steen; Sparsø, Jens

1991-01-01

Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

Directory of Open Access Journals (Sweden)

Fazal NOORBASHA

2012-08-01

Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

Fast-prototyping of VLSI

International Nuclear Information System (INIS)

Saucier, G.; Read, E.

1987-01-01

Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

Science.gov (United States)

Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

1991-01-01

A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

Multi-net optimization of VLSI interconnect

CERN Document Server

Moiseev, Konstantin; Wimer, Shmuel

2015-01-01

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

Energy Technology Data Exchange (ETDEWEB)

Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

1992-01-01

The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks

International Nuclear Information System (INIS)

Oya, Takahide; Asai, Tetsuya; Amemiya, Yoshihito

2007-01-01

Neuromorphic computing based on single-electron circuit technology is gaining prominence because of its massively increased computational efficiency and the increasing relevance of computer technology and nanotechnology [Likharev K, Mayr A, Muckra I, Tuerel O. CrossNets: High-performance neuromorphic architectures for CMOL circuits. Molec Electron III: Ann NY Acad Sci 1006;2003:146-63; Oya T, Schmid A, Asai T, Leblebici Y, Amemiya Y. On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron Expr 2;2005:76-80]. The maximum impact of these technologies will be strongly felt when single-electron circuits based on fault- and noise-tolerant neural structures can operate at room temperature. In this paper, inspired by stochastic resonance (SR) in an ensemble of spiking neurons [Collins JJ, Chow CC, Imhoff TT. Stochastic resonance without tuning. Nature 1995;376:236-8], we propose our design of a basic single-electron neural component and report how we examined its statistical results on a network

International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

CERN Document Server

Shirur, Yasha; Prasad, Rekha

2013-01-01

This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

Advances in neuromorphic hardware exploiting emerging nanoscale devices

CERN Document Server

2017-01-01

This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

Discrimination of Dynamic Tactile Contact by Temporally Precise Event Sensing in Spiking Neuromorphic Networks.

Science.gov (United States)

Lee, Wang Wei; Kukreja, Sunil L; Thakor, Nitish V

2017-01-01

This paper presents a neuromorphic tactile encoding methodology that utilizes a temporally precise event-based representation of sensory signals. We introduce a novel concept where touch signals are characterized as patterns of millisecond precise binary events to denote pressure changes. This approach is amenable to a sparse signal representation and enables the extraction of relevant features from thousands of sensing elements with sub-millisecond temporal precision. We also proposed measures adopted from computational neuroscience to study the information content within the spiking representations of artificial tactile signals. Implemented on a state-of-the-art 4096 element tactile sensor array with 5.2 kHz sampling frequency, we demonstrate the classification of transient impact events while utilizing 20 times less communication bandwidth compared to frame based representations. Spiking sensor responses to a large library of contact conditions were also synthesized using finite element simulations, illustrating an 8-fold improvement in information content and a 4-fold reduction in classification latency when millisecond-precise temporal structures are available. Our research represents a significant advance, demonstrating that a neuromorphic spatiotemporal representation of touch is well suited to rapid identification of critical contact events, making it suitable for dynamic tactile sensing in robotic and prosthetic applications.

American Sign Language Alphabet Recognition Using a Neuromorphic Sensor and an Artificial Neural Network

Directory of Open Access Journals (Sweden)

Miguel Rivera-Acosta

2017-09-01

Full Text Available This paper reports the design and analysis of an American Sign Language (ASL alphabet translation system implemented in hardware using a Field-Programmable Gate Array. The system process consists of three stages, the first being the communication with the neuromorphic camera (also called Dynamic Vision Sensor, DVS sensor using the Universal Serial Bus protocol. The feature extraction of the events generated by the DVS is the second part of the process, consisting of a presentation of the digital image processing algorithms developed in software, which aim to reduce redundant information and prepare the data for the third stage. The last stage of the system process is the classification of the ASL alphabet, achieved with a single artificial neural network implemented in digital hardware for higher speed. The overall result is the development of a classification system using the ASL signs contour, fully implemented in a reconfigurable device. The experimental results consist of a comparative analysis of the recognition rate among the alphabet signs using the neuromorphic camera in order to prove the proper operation of the digital image processing algorithms. In the experiments performed with 720 samples of 24 signs, a recognition accuracy of 79.58% was obtained.

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

Science.gov (United States)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

PLA realizations for VLSI state machines

Science.gov (United States)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

Science.gov (United States)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

A bidirectional brain-machine interface featuring a neuromorphic hardware decoder

Directory of Open Access Journals (Sweden)

Fabio Boi

2016-12-01

Full Text Available Bidirectional brain-machine interfaces (BMIs establish a two-way direct communication link4 between the brain and the external world. A decoder translates recorded neural activity into motor5 commands and an encoder delivers sensory information collected from the environment directly6 to the brain creating a closed-loop system. These two modules are typically integrated in bulky7 external devices. However, the clinical support of patients with severe motor and sensory deficits8 requires compact, low-power, and fully implantable systems that can decode neural signals to9 control external devices. As a first step toward this goal, we developed a modular bidirectional BMI10 setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented11 a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits.12 On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn13 to decode neural signals recorded from the brain into motor outputs controlling the movements14 of an external device. The modularity of the BMI allowed us to tune the individual components15 of the setup without modifying the whole system. In this paper we present the features of16 this modular BMI, and describe how we configured the network of spiking neuron circuits to17 implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm18 that connects bidirectionally the brain of an anesthetized rat with an external object. We show that19 the chip learned the decoding task correctly, allowing the interfaced brain to control the object’s20 trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is21 mature enough for the development of BMI modules that are sufficiently low-power and compact,22 while being highly computationally powerful and adaptive.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder.

Science.gov (United States)

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive.

Point DCT VLSI Architecture for Emerging HEVC Standard

Directory of Open Access Journals (Sweden)

Ashfaq Ahmed

2012-01-01

Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

National Research Council Canada - National Science Library

Altmeyer, Ronald

2002-01-01

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

Virtual Neurorobotics (VNR) to Accelerate Development of Plausible Neuromorphic Brain Architectures.

Science.gov (United States)

Goodman, Philip H; Buntha, Sermsak; Zou, Quan; Dascalu, Sergiu-Mihai

2007-01-01

Traditional research in artificial intelligence and machine learning has viewed the brain as a specially adapted information-processing system. More recently the field of social robotics has been advanced to capture the important dynamics of human cognition and interaction. An overarching societal goal of this research is to incorporate the resultant knowledge about intelligence into technology for prosthetic, assistive, security, and decision support applications. However, despite many decades of investment in learning and classification systems, this paradigm has yet to yield truly "intelligent" systems. For this reason, many investigators are now attempting to incorporate more realistic neuromorphic properties into machine learning systems, encouraged by over two decades of neuroscience research that has provided parameters that characterize the brain's interdependent genomic, proteomic, metabolomic, anatomic, and electrophysiological networks. Given the complexity of neural systems, developing tenable models to capture the essence of natural intelligence for real-time application requires that we discriminate features underlying information processing and intrinsic motivation from those reflecting biological constraints (such as maintaining structural integrity and transporting metabolic products). We propose herein a conceptual framework and an iterative method of virtual neurorobotics (VNR) intended to rapidly forward-engineer and test progressively more complex putative neuromorphic brain prototypes for their ability to support intrinsically intelligent, intentional interaction with humans. The VNR system is based on the viewpoint that a truly intelligent system must be driven by emotion rather than programmed tasking, incorporating intrinsic motivation and intentionality. We report pilot results of a closed-loop, real-time interactive VNR system with a spiking neural brain, and provide a video demonstration as online supplemental material.

Virtual neurorobotics (VNR to accelerate development of plausible neuromorphic brain architectures

Directory of Open Access Journals (Sweden)

Philip H Goodman

2007-11-01

Full Text Available Traditional research in artificial intelligence and machine learning has viewed the brain as a specially adapted information-processing system. More recently the field of social robotics has been advanced to capture the important dynamics of human cognition and interaction. An overarching societal goal of this research is to incorporate the resultant knowledge about intelligence into technology for prosthetic, assistive, security, and decision support applications. However, despite many decades of investment in learning and classification systems, this paradigm has yet to yield truly “intelligent” systems. For this reason, many investigators are now attempting to incorporate more realistic neuromorphic properties into machine learning systems, encouraged by over two decades of neuroscience research that has provided parameters that characterize the brain’s interdependent genomic, proteomic, metabolomic, anatomic, and electrophysiological networks. Given the complexity of neural systems, developing tenable models to capture the essence of natural intelligence for real-time application requires that we discriminate features underlying information processing and intrinsic motivation from those reflecting biological constraints (such as maintaining structural integrity and transporting metabolic products. We propose herein a conceptual framework and an iterative method of virtual neurorobotics (VNR intended to rapidly forward-engineer and test progressively more complex putative neuromorphic brain prototypes for their ability to support intrinsically intelligent, intentional interaction with humans. The VNR system is based on the viewpoint that a truly intelligent system must be driven by emotion rather than programmed tasking, incorporating intrinsic motivation and intentionality. We report pilot results of a closed-loop, real-time interactive VNR system with a spiking neural brain, and provide a video demonstration as online supplemental

An analog VLSI chip emulating polarization vision of Octopus retina.

Science.gov (United States)

Momeni, Massoud; Titus, Albert H

2006-01-01

Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks

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Runchun Mark Wang

2015-05-01

Full Text Available We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP and Spike Timing Dependent Delay Plasticity (STDDP. We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 2^26 (64M synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted and/or delayed pre-synaptic spike to the target synapse in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 2^36 (64G synaptic adaptors on a current high-end FPGA platform.

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications.

Science.gov (United States)

Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

2016-08-11

Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure-Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron-Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

Nanotube devices based crossbar architecture: toward neuromorphic computing

International Nuclear Information System (INIS)

Zhao, W S; Gamrat, C; Agnus, G; Derycke, V; Filoramo, A; Bourgoin, J-P

2010-01-01

Nanoscale devices such as carbon nanotube and nanowires based transistors, memristors and molecular devices are expected to play an important role in the development of new computing architectures. While their size represents a decisive advantage in terms of integration density, it also raises the critical question of how to efficiently address large numbers of densely integrated nanodevices without the need for complex multi-layer interconnection topologies similar to those used in CMOS technology. Two-terminal programmable devices in crossbar geometry seem particularly attractive, but suffer from severe addressing difficulties due to cross-talk, which implies complex programming procedures. Three-terminal devices can be easily addressed individually, but with limited gain in terms of interconnect integration. We show how optically gated carbon nanotube devices enable efficient individual addressing when arranged in a crossbar geometry with shared gate electrodes. This topology is particularly well suited for parallel programming or learning in the context of neuromorphic computing architectures.

Microfluidic Neurons, a New Way in Neuromorphic Engineering?

Directory of Open Access Journals (Sweden)

Timothée Levi

2016-08-01

Full Text Available This article describes a new way to explore neuromorphic engineering, the biomimetic artificial neuron using microfluidic techniques. This new device could replace silicon neurons and solve the issues of biocompatibility and power consumption. The biological neuron transmits electrical signals based on ion flow through their plasma membrane. Action potentials are propagated along axons and represent the fundamental electrical signals by which information are transmitted from one place to another in the nervous system. Based on this physiological behavior, we propose a microfluidic structure composed of chambers representing the intra and extracellular environments, connected by channels actuated by Quake valves. These channels are equipped with selective ion permeable membranes to mimic the exchange of chemical species found in the biological neuron. A thick polydimethylsiloxane (PDMS membrane is used to create the Quake valve membrane. Integrated electrodes are used to measure the potential difference between the intracellular and extracellular environments: the membrane potential.

Neuromorphic function learning with carbon nanotube based synapses

International Nuclear Information System (INIS)

Gacem, Karim; Filoramo, Arianna; Derycke, Vincent; Retrouvey, Jean-Marie; Chabi, Djaafar; Zhao, Weisheng; Klein, Jacques-Olivier

2013-01-01

The principle of using nanoscale memory devices as artificial synapses in neuromorphic circuits is recognized as a promising way to build ground-breaking circuit architectures tolerant to defects and variability. Yet, actual experimental demonstrations of the neural network type of circuits based on non-conventional/non-CMOS memory devices and displaying function learning capabilities remain very scarce. We show here that carbon-nanotube-based memory elements can be used as artificial synapses, combined with conventional neurons and trained to perform functions through the application of a supervised learning algorithm. The same ensemble of eight devices can notably be trained multiple times to code successively any three-input linearly separable Boolean logic function despite device-to-device variability. This work thus represents one of the very few demonstrations of actual function learning with synapses based on nanoscale building blocks. The potential of such an approach for the parallel learning of multiple and more complex functions is also evaluated. (paper)

Operation of a Fast-RICH Prototype with VLSI readout electronics

Energy Technology Data Exchange (ETDEWEB)

Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

1994-04-01

We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

Power efficient and high performance VLSI architecture for AES algorithm

Directory of Open Access Journals (Sweden)

K. Kalaiselvi

2015-09-01

Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

A neuromorphic architecture for object recognition and motion anticipation using burst-STDP.

Directory of Open Access Journals (Sweden)

Andrew Nere

Full Text Available In this work we investigate the possibilities offered by a minimal framework of artificial spiking neurons to be deployed in silico. Here we introduce a hierarchical network architecture of spiking neurons which learns to recognize moving objects in a visual environment and determine the correct motor output for each object. These tasks are learned through both supervised and unsupervised spike timing dependent plasticity (STDP. STDP is responsible for the strengthening (or weakening of synapses in relation to pre- and post-synaptic spike times and has been described as a Hebbian paradigm taking place both in vitro and in vivo. We utilize a variation of STDP learning, called burst-STDP, which is based on the notion that, since spikes are expensive in terms of energy consumption, then strong bursting activity carries more information than single (sparse spikes. Furthermore, this learning algorithm takes advantage of homeostatic renormalization, which has been hypothesized to promote memory consolidation during NREM sleep. Using this learning rule, we design a spiking neural network architecture capable of object recognition, motion detection, attention towards important objects, and motor control outputs. We demonstrate the abilities of our design in a simple environment with distractor objects, multiple objects moving concurrently, and in the presence of noise. Most importantly, we show how this neural network is capable of performing these tasks using a simple leaky-integrate-and-fire (LIF neuron model with binary synapses, making it fully compatible with state-of-the-art digital neuromorphic hardware designs. As such, the building blocks and learning rules presented in this paper appear promising for scalable fully neuromorphic systems to be implemented in hardware chips.

Carbon nanotube based VLSI interconnects analysis and design

CERN Document Server

Kaushik, Brajesh Kumar

2015-01-01

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

An analog VLSI real time optical character recognition system based on a neural architecture

International Nuclear Information System (INIS)

Bo, G.; Caviglia, D.; Valle, M.

1999-01-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

An analog VLSI real time optical character recognition system based on a neural architecture

Energy Technology Data Exchange (ETDEWEB)

Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

1999-03-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

Neuromorphic Audio-Visual Sensor Fusion on a Sound-Localising Robot

Directory of Open Access Journals (Sweden)

Vincent Yue-Sek Chan

2012-02-01

Full Text Available This paper presents the first robotic system featuring audio-visual sensor fusion with neuromorphic sensors. We combine a pair of silicon cochleae and a silicon retina on a robotic platform to allow the robot to learn sound localisation through self-motion and visual feedback, using an adaptive ITD-based sound localisation algorithm. After training, the robot can localise sound sources (white or pink noise in a reverberant environment with an RMS error of 4 to 5 degrees in azimuth. In the second part of the paper, we investigate the source binding problem. An experiment is conducted to test the effectiveness of matching an audio event with a corresponding visual event based on their onset time. The results show that this technique can be quite effective, despite its simplicity.

Compliance-Free, Digital SET and Analog RESET Synaptic Characteristics of Sub-Tantalum Oxide Based Neuromorphic Device.

Science.gov (United States)

Abbas, Yawar; Jeon, Yu-Rim; Sokolov, Andrey Sergeevich; Kim, Sohyeon; Ku, Boncheol; Choi, Changhwan

2018-01-19

A two terminal semiconducting device like a memristor is indispensable to emulate the function of synapse in the working memory. The analog switching characteristics of memristor play a vital role in the emulation of biological synapses. The application of consecutive voltage sweeps or pulses (action potentials) changes the conductivity of the memristor which is considered as the fundamental cause of the synaptic plasticity. In this study, a neuromorphic device using an in-situ growth of sub-tantalum oxide switching layer is fabricated, which exhibits the digital SET and analog RESET switching with an electroforming process without any compliance current (compliance free). The process of electroforming and SET is observed at the positive sweeps of +2.4 V and +0.86 V, respectively, while multilevel RESET is observed with the consecutive negative sweeps in the range of 0 V to -1.2 V. The movement of oxygen vacancies and gradual change in the anatomy of the filament is attributed to digital SET and analog RESET switching characteristics. For the Ti/Ta 2 O 3-x /Pt neuromorphic device, the Ti top and Pt bottom electrodes are considered as counterparts of the pre-synaptic input terminal and a post-synaptic output terminal, respectively.

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

Science.gov (United States)

Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

2016-01-01

Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure–Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods. PMID:27529225

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

Directory of Open Access Journals (Sweden)

Lucas Antón Pastur-Romay

2016-08-01

Full Text Available Over the past decade, Deep Artificial Neural Networks (DNNs have become the state-of-the-art algorithms in Machine Learning (ML, speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs. All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS, Quantitative Structure–Activity Relationship (QSAR research, protein structure prediction and genomics (and other omics data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

Vlsi implementation of flexible architecture for decision tree classification in data mining

Science.gov (United States)

Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

2017-07-01

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

Neuromorphic Configurable Architecture for Robust Motion Estimation

Directory of Open Access Journals (Sweden)

Guillermo Botella

2008-01-01

Full Text Available The robustness of the human visual system recovering motion estimation in almost any visual situation is enviable, performing enormous calculation tasks continuously, robustly, efficiently, and effortlessly. There is obviously a great deal we can learn from our own visual system. Currently, there are several optical flow algorithms, although none of them deals efficiently with noise, illumination changes, second-order motion, occlusions, and so on. The main contribution of this work is the efficient implementation of a biologically inspired motion algorithm that borrows nature templates as inspiration in the design of architectures and makes use of a specific model of human visual motion perception: Multichannel Gradient Model (McGM. This novel customizable architecture of a neuromorphic robust optical flow can be constructed with FPGA or ASIC device using properties of the cortical motion pathway, constituting a useful framework for building future complex bioinspired systems running in real time with high computational complexity. This work includes the resource usage and performance data, and the comparison with actual systems. This hardware has many application fields like object recognition, navigation, or tracking in difficult environments due to its bioinspired and robustness properties.

A Dataset for Visual Navigation with Neuromorphic Methods

Directory of Open Access Journals (Sweden)

Francisco eBarranco

2016-02-01

Full Text Available Standardized benchmarks in Computer Vision have greatly contributed to the advance of approaches to many problems in the field. If we want to enhance the visibility of event-driven vision and increase its impact, we will need benchmarks that allow comparison among different neuromorphic methods as well as comparison to Computer Vision conventional approaches. We present datasets to evaluate the accuracy of frame-free and frame-based approaches for tasks of visual navigation. Similar to conventional Computer Vision datasets, we provide synthetic and real scenes, with the synthetic data created with graphics packages, and the real data recorded using a mobile robotic platform carrying a dynamic and active pixel vision sensor (DAVIS and an RGB+Depth sensor. For both datasets the cameras move with a rigid motion in a static scene, and the data includes the images, events, optic flow, 3D camera motion, and the depth of the scene, along with calibration procedures. Finally, we also provide simulated event data generated synthetically from well-known frame-based optical flow datasets.

Neuromorphic Implementation of Attractor Dynamics in a Two-Variable Winner-Take-All Circuit with NMDARs: A Simulation Study.

Science.gov (United States)

You, Hongzhi; Wang, Da-Hui

2017-01-01

Neural networks configured with winner-take-all (WTA) competition and N-methyl-D-aspartate receptor (NMDAR)-mediated synaptic dynamics are endowed with various dynamic characteristics of attractors underlying many cognitive functions. This paper presents a novel method for neuromorphic implementation of a two-variable WTA circuit with NMDARs aimed at implementing decision-making, working memory and hysteresis in visual perceptions. The method proposed is a dynamical system approach of circuit synthesis based on a biophysically plausible WTA model. Notably, slow and non-linear temporal dynamics of NMDAR-mediated synapses was generated. Circuit simulations in Cadence reproduced ramping neural activities observed in electrophysiological recordings in experiments of decision-making, the sustained activities observed in the prefrontal cortex during working memory, and classical hysteresis behavior during visual discrimination tasks. Furthermore, theoretical analysis of the dynamical system approach illuminated the underlying mechanisms of decision-making, memory capacity and hysteresis loops. The consistence between the circuit simulations and theoretical analysis demonstrated that the WTA circuit with NMDARs was able to capture the attractor dynamics underlying these cognitive functions. Their physical implementations as elementary modules are promising for assembly into integrated neuromorphic cognitive systems.

Neuromorphic model of magnocellular and parvocellular visual paths: spatial resolution

International Nuclear Information System (INIS)

Aguirre, Rolando C; Felice, Carmelo J; Colombo, Elisa M

2007-01-01

Physiological studies of the human retina show the existence of at least two visual information processing channels, the magnocellular and the parvocellular ones. Both have different spatial, temporal and chromatic features. This paper focuses on the different spatial resolution of these two channels. We propose a neuromorphic model, so that they match the retina's physiology. Considering the Deutsch and Deutsch model (1992), we propose two configurations (one for each visual channel) of the connection between the retina's different cell layers. The responses of the proposed model have similar behaviour to those of the visual cells: each channel has an optimum response corresponding to a given stimulus size which decreases for larger or smaller stimuli. This size is bigger for the magno path than for the parvo path and, in the end, both channels produce a magnifying of the borders of a stimulus

A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System.

Science.gov (United States)

Zhang, Zhen; Ma, Cheng; Zhu, Rong

2017-08-23

Artificial Neural Networks (ANNs), including Deep Neural Networks (DNNs), have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA) architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP). The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO) real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System

Directory of Open Access Journals (Sweden)

Zhen Zhang

2017-08-01

Full Text Available Artificial Neural Networks (ANNs, including Deep Neural Networks (DNNs, have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP. The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

A novel configurable VLSI architecture design of window-based image processing method

Science.gov (United States)

Zhao, Hui; Sang, Hongshi; Shen, Xubang

2018-03-01

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Directory of Open Access Journals (Sweden)

Georgios Passas

2012-01-01

Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Sound stream segregation: a neuromorphic approach to solve the “cocktail party problem” in real-time

OpenAIRE

Thakur, Chetan Singh; Wang, Runchun M.; Afshar, Saeed; Hamilton, Tara J.; Tapson, Jonathan C.; Shamma, Shihab A.; van Schaik, André

2015-01-01

The human auditory system has the ability to segregate complex auditory scenes into a foreground component and a background, allowing us to listen to specific speech sounds from a mixture of sounds. Selective attention plays a crucial role in this process, colloquially known as the “cocktail party effect.” It has not been possible to build a machine that can emulate this human ability in real-time. Here, we have developed a framework for the implementation of a neuromorphic sound segregation ...

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

VLSI-based video event triggering for image data compression

Science.gov (United States)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

Science.gov (United States)

Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

2017-10-01

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Directory of Open Access Journals (Sweden)

T. Kalavathi Devi

2015-01-01

Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

Ab Initio Molecular-Dynamics Simulation of Neuromorphic Computing in Phase-Change Memory Materials.

Science.gov (United States)

Skelton, Jonathan M; Loke, Desmond; Lee, Taehoon; Elliott, Stephen R

2015-07-08

We present an in silico study of the neuromorphic-computing behavior of the prototypical phase-change material, Ge2Sb2Te5, using ab initio molecular-dynamics simulations. Stepwise changes in structural order in response to temperature pulses of varying length and duration are observed, and a good reproduction of the spike-timing-dependent plasticity observed in nanoelectronic synapses is demonstrated. Short above-melting pulses lead to instantaneous loss of structural and chemical order, followed by delayed partial recovery upon structural relaxation. We also investigate the link between structural order and electrical and optical properties. These results pave the way toward a first-principles understanding of phase-change physics beyond binary switching.

The qualified possession turn into ownership

Directory of Open Access Journals (Sweden)

Popov Danica

2011-01-01

Full Text Available Possession is prima facie evidence of ownership. Possession is ninetents of the law, means that possession is good against all other, except the true owner. The possession ripens into ownership if it is qualified and by effluxion of time. In Serbian law there are two kinds of adverse possession ripens into ownership. The first one is named ordinary and second one extraordinary adverse possession. Ordinary possession need to be legal, conscientious and genuine. Extraordinary possession is only conscientious, but in a wide sense. Adverse possession destroys the title of the owner and vests it in possessor. An occupation of land inconsistent with the right of the true owner: the possession of those against whom a right action has accured to the true owner. It is actual possession in the absence of possession by the rightful owner and without lawful title. If the adverse possession continues, the effect at the expiration of the prescribed period is that not only the remedy but the title of former owner is extinguished. The person in adverse possession gains a new possessory title which cannot, normally exceed in extent of duration the interest of the former owner.

An Energy Efficient Neuromorphic Computing System Using Real Time Sensing Method

DEFF Research Database (Denmark)

Farkhani, Hooman; Tohidi, Mohammad; Farkhani, Sadaf

2017-01-01

In spintronic-based neuromorphic computing systems (NCS), the switching of magnetic moment in a magnetic tunnel junction (MTJ) is used to mimic neuron firing. However, the stochastic switching behavior of the MTJ and process variations effect leads to extra stimulation time. This leads to extra...... energy consumption and delay of such NCSs. In this paper, a new real-time sensing (RTS) circuit is proposed to track the MTJ state and terminate stimulation phase immediately after MTJ switching. This leads to significant degradation in energy consumption and delay of NCS. The simulation results using...... a 65-nm CMOS technology and a 40-nm MTJ technology confirm that the energy consumption of a RTS-based NCS is improved by 50% in comparison with a typical NCS. Moreover, utilizing RTS circuit improves the overall speed of an NCS by 2.75x....

The human brain on a computer, the design neuromorphic chips aims to process information as does the mind

International Nuclear Information System (INIS)

Pajuelo, L.

2015-01-01

Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

Neuromorphic infrared focal plane performs sensor fusion on-plane local-contrast-enhancement spatial and temporal filtering

Science.gov (United States)

Massie, Mark A.; Woolaway, James T., II; Curzan, Jon P.; McCarley, Paul L.

1993-08-01

An infrared focal plane has been simulated, designed and fabricated which mimics the form and function of the vertebrate retina. The `Neuromorphic' focal plane has the capability of performing pixel-based sensor fusion and real-time local contrast enhancement, much like the response of the human eye. The device makes use of an indium antimonide detector array with a 3 - 5 micrometers spectral response, and a switched capacitor resistive network to compute a real-time 2D spatial average. This device permits the summation of other sensor outputs to be combined on-chip with the infrared detections of the focal plane itself. The resulting real-time analog processed information thus represents the combined information of many sensors with the advantage that analog spatial and temporal signal processing is performed at the focal plane. A Gaussian subtraction method is used to produce the pixel output which when displayed produces an image with enhanced edges, representing spatial and temporal derivatives in the scene. The spatial and temporal responses of the device are tunable during operation, permitting the operator to `peak up' the response of the array to spatial and temporally varying signals. Such an array adapts to ambient illumination conditions without loss of detection performance. This paper reviews the Neuromorphic infrared focal plane from initial operational simulations to detailed design characteristics, and concludes with a presentation of preliminary operational data for the device as well as videotaped imagery.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

Science.gov (United States)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device.

Science.gov (United States)

Park, Sangsu; Noh, Jinwoo; Choo, Myung-Lae; Sheri, Ahmad Muqeem; Chang, Man; Kim, Young-Bae; Kim, Chang Jung; Jeon, Moongu; Lee, Byung-Geun; Lee, Byoung Hun; Hwang, Hyunsang

2013-09-27

Efforts to develop scalable learning algorithms for implementation of networks of spiking neurons in silicon have been hindered by the considerable footprints of learning circuits, which grow as the number of synapses increases. Recent developments in nanotechnologies provide an extremely compact device with low-power consumption.In particular, nanoscale resistive switching devices (resistive random-access memory (RRAM)) are regarded as a promising solution for implementation of biological synapses due to their nanoscale dimensions, capacity to store multiple bits and the low energy required to operate distinct states. In this paper, we report the fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In addition, we first experimentally demonstrate the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point array of synapses and complementary metal-oxide-semiconductor neuron circuits. These developments open up possibilities for the development of ubiquitous ultra-dense, ultra-low-power cognitive computers.

Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device

International Nuclear Information System (INIS)

Park, Sangsu; Noh, Jinwoo; Choo, Myung-lae; Sheri, Ahmad Muqeem; Jeon, Moongu; Lee, Byung-Geun; Lee, Byoung Hun; Chang, Man; Kim, Young-Bae; Kim, Chang Jung; Hwang, Hyunsang

2013-01-01

Efforts to develop scalable learning algorithms for implementation of networks of spiking neurons in silicon have been hindered by the considerable footprints of learning circuits, which grow as the number of synapses increases. Recent developments in nanotechnologies provide an extremely compact device with low-power consumption. In particular, nanoscale resistive switching devices (resistive random-access memory (RRAM)) are regarded as a promising solution for implementation of biological synapses due to their nanoscale dimensions, capacity to store multiple bits and the low energy required to operate distinct states. In this paper, we report the fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In addition, we first experimentally demonstrate the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point array of synapses and complementary metal–oxide–semiconductor neuron circuits. These developments open up possibilities for the development of ubiquitous ultra-dense, ultra-low-power cognitive computers. (paper)

Stochastic learning in oxide binary synaptic device for neuromorphic computing.

Science.gov (United States)

Yu, Shimeng; Gao, Bin; Fang, Zheng; Yu, Hongyu; Kang, Jinfeng; Wong, H-S Philip

2013-01-01

Hardware implementation of neuromorphic computing is attractive as a computing paradigm beyond the conventional digital computing. In this work, we show that the SET (off-to-on) transition of metal oxide resistive switching memory becomes probabilistic under a weak programming condition. The switching variability of the binary synaptic device implements a stochastic learning rule. Such stochastic SET transition was statistically measured and modeled for a simulation of a winner-take-all network for competitive learning. The simulation illustrates that with such stochastic learning, the orientation classification function of input patterns can be effectively realized. The system performance metrics were compared between the conventional approach using the analog synapse and the approach in this work that employs the binary synapse utilizing the stochastic learning. The feasibility of using binary synapse in the neurormorphic computing may relax the constraints to engineer continuous multilevel intermediate states and widens the material choice for the synaptic device design.

An electron undulating ring for VLSI lithography

International Nuclear Information System (INIS)

Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

1985-01-01

The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

Convolving optically addressed VLSI liquid crystal SLM

Science.gov (United States)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

2D MoS2 Neuromorphic Devices for Brain-Like Computational Systems.

Science.gov (United States)

Jiang, Jie; Guo, Junjie; Wan, Xiang; Yang, Yi; Xie, Haipeng; Niu, Dongmei; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

2017-08-01

Hardware implementation of artificial synapses/neurons with 2D solid-state devices is of great significance for nanoscale brain-like computational systems. Here, 2D MoS 2 synaptic/neuronal transistors are fabricated by using poly(vinyl alcohol) as the laterally coupled, proton-conducting electrolytes. Fundamental synaptic functions, such as an excitatory postsynaptic current, paired-pulse facilitation, and a dynamic filter for information transmission of biological synapse, are successfully emulated. Most importantly, with multiple input gates and one modulatory gate, spiking-dependent logic operation/modulation, multiplicative neural coding, and neuronal gain modulation are also experimentally demonstrated. The results indicate that the intriguing 2D MoS 2 transistors are also very promising for the next-generation of nanoscale neuromorphic device applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Selective Attention in Multi-Chip Address-Event Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2009-06-01

Full Text Available Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the “Selective Attention Chip” (SAC, which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Selective attention in multi-chip address-event systems.

Science.gov (United States)

Bartolozzi, Chiara; Indiveri, Giacomo

2009-01-01

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Directory of Open Access Journals (Sweden)

HOO, C.-S.

2013-02-01

Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

Science.gov (United States)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

Energy Technology Data Exchange (ETDEWEB)

Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

1983-07-01

This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

Mechanical Dissociation of Retinal Neurons with Vibration

Science.gov (United States)

Motomura, Tamami; Hayashida, Yuki; Murayama, Nobuki

The neuromorphic device, which implements the functions of biological neural circuits by means of VLSI technology, has been collecting much attention in the engineering fields in the last decade. Concurrently, progress in neuroscience research has revealed the nonlinear computation in single neuron levels, suggesting that individual neurons are not merely the circuit elements but computational units. Thus, elucidating the properties of neuronal signal processing is thought to be an essential step for developing the next generation of neuromorphic devices. In the present study, we developed a method for dissociating single neurons from specific sublayers of mammalian retinas with using no proteolytic enzymes but rather combining tissue incubation in a low-Ca2+ medium and the vibro-dissociation technique developed for the slices of brains and spinal cords previously. Our method took shorter time of the procedure, and required less elaborated skill, than the conventional enzymatic method did; nevertheless it yielded enough number of the cells available for acute electrophysiological experiments. The isolated retinal neurons were useful for measuring the nonlinear membrane conductances as well as the spike firing properties under the perforated-patch whole-cell configuration. These neurons also enabled us to examine the effects of proteolytic enzymes on the membrane excitability in those cells.

An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

International Nuclear Information System (INIS)

Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

1995-01-01

A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

Diverse spike-timing-dependent plasticity based on multilevel HfO x memristor for neuromorphic computing

Science.gov (United States)

Lu, Ke; Li, Yi; He, Wei-Fan; Chen, Jia; Zhou, Ya-Xiong; Duan, Nian; Jin, Miao-Miao; Gu, Wei; Xue, Kan-Hao; Sun, Hua-Jun; Miao, Xiang-Shui

2018-06-01

Memristors have emerged as promising candidates for artificial synaptic devices, serving as the building block of brain-inspired neuromorphic computing. In this letter, we developed a Pt/HfO x /Ti memristor with nonvolatile multilevel resistive switching behaviors due to the evolution of the conductive filaments and the variation in the Schottky barrier. Diverse state-dependent spike-timing-dependent-plasticity (STDP) functions were implemented with different initial resistance states. The measured STDP forms were adopted as the learning rule for a three-layer spiking neural network which achieves a 75.74% recognition accuracy for MNIST handwritten digit dataset. This work has shown the capability of memristive synapse in spiking neural networks for pattern recognition application.

A novel VLSI processor for high-rate, high resolution spectroscopy

CERN Document Server

Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

2000-01-01

A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

International Nuclear Information System (INIS)

Jones, W.F.; Byars, L.G.; Casey, M.E.

1988-01-01

A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

Interplay of multiple synaptic plasticity features in filamentary memristive devices for neuromorphic computing

Science.gov (United States)

La Barbera, Selina; Vincent, Adrien F.; Vuillaume, Dominique; Querlioz, Damien; Alibart, Fabien

2016-12-01

Bio-inspired computing represents today a major challenge at different levels ranging from material science for the design of innovative devices and circuits to computer science for the understanding of the key features required for processing of natural data. In this paper, we propose a detail analysis of resistive switching dynamics in electrochemical metallization cells for synaptic plasticity implementation. We show how filament stability associated to joule effect during switching can be used to emulate key synaptic features such as short term to long term plasticity transition and spike timing dependent plasticity. Furthermore, an interplay between these different synaptic features is demonstrated for object motion detection in a spike-based neuromorphic circuit. System level simulation presents robust learning and promising synaptic operation paving the way to complex bio-inspired computing systems composed of innovative memory devices.

Spin-neurons: A possible path to energy-efficient neuromorphic computers

Energy Technology Data Exchange (ETDEWEB)

Sharad, Mrigank; Fan, Deliang; Roy, Kaushik [School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907 (United States)

2013-12-21

Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices. Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and “thresholding” operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that “spin-neurons” (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.

Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

CERN Document Server

Ramachandran, S

2007-01-01

Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

Science.gov (United States)

Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

2016-12-21

One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

Directory of Open Access Journals (Sweden)

Horiuchi Timothy

2003-01-01

Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

A High Performance VLSI Computer Architecture For Computer Graphics

Science.gov (United States)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

Predicative possession in Medieval Slavic Bible translations Predicative Possession in Early Biblical Slavic

Directory of Open Access Journals (Sweden)

Julia McAnallen

2011-08-01

Full Text Available Late Proto-Slavic (LPS had an inventory of three constructions for expressing predicative possession. Using the earliest Slavic Bible translations from Old Church Slavic (OCS, and to a lesser degree Old Czech, a number of conclusions can be drawn about the status of predicative possession for LPS. The verb iměti ‘have’ was the most frequent and least syntactically and semantically restricted predicative possessive construction (PPC. Existential PPCs with a dative possessor appear primarily with kinship relations, abstract possessums, and in a number of other fixed construction types; existential PPCs with the possessor in an u + genitive prepositional phrase primarily appear with concrete and countable possessums. Both existential PPCs call for an animate, most often pronominal, possessor. The u + genitive was the rarest type of PPC in LPS, though it had undoubtedly grammaticalized as a PPC.

The protection of possession

Directory of Open Access Journals (Sweden)

Popov Danica

2011-01-01

Full Text Available Protection in disputes for the protection of possession can be attained through the following actions a for dispossession (interdictum recuperande possessionis and b with an action for the disturbance of possession (interdictum retinendae possessionis. The general feature of these disputes is that there is only discussion on the facts and not a legal matters. Subject matter jurisdiction for the resolution of such disputes belongs to the court of general jurisdiction, while the dispute itself is a litigation. The special rule of proceedings of action for disturbance are: provisionality of the protection of possession; urgency in proceedings; initiation of the proceedings; limiting of objection; prescribing temporary measures; rendering a ruling in the form of order; appeals which may be filed within a short deadline and which does not have suspensive effect (do not delay the execution of the order; revision is not allowed etc.

High performance VLSI telemetry data systems

Science.gov (United States)

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-01-01

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

Sound stream segregation: a neuromorphic approach to solve the "cocktail party problem" in real-time.

Science.gov (United States)

Thakur, Chetan Singh; Wang, Runchun M; Afshar, Saeed; Hamilton, Tara J; Tapson, Jonathan C; Shamma, Shihab A; van Schaik, André

2015-01-01

The human auditory system has the ability to segregate complex auditory scenes into a foreground component and a background, allowing us to listen to specific speech sounds from a mixture of sounds. Selective attention plays a crucial role in this process, colloquially known as the "cocktail party effect." It has not been possible to build a machine that can emulate this human ability in real-time. Here, we have developed a framework for the implementation of a neuromorphic sound segregation algorithm in a Field Programmable Gate Array (FPGA). This algorithm is based on the principles of temporal coherence and uses an attention signal to separate a target sound stream from background noise. Temporal coherence implies that auditory features belonging to the same sound source are coherently modulated and evoke highly correlated neural response patterns. The basis for this form of sound segregation is that responses from pairs of channels that are strongly positively correlated belong to the same stream, while channels that are uncorrelated or anti-correlated belong to different streams. In our framework, we have used a neuromorphic cochlea as a frontend sound analyser to extract spatial information of the sound input, which then passes through band pass filters that extract the sound envelope at various modulation rates. Further stages include feature extraction and mask generation, which is finally used to reconstruct the targeted sound. Using sample tonal and speech mixtures, we show that our FPGA architecture is able to segregate sound sources in real-time. The accuracy of segregation is indicated by the high signal-to-noise ratio (SNR) of the segregated stream (90, 77, and 55 dB for simple tone, complex tone, and speech, respectively) as compared to the SNR of the mixture waveform (0 dB). This system may be easily extended for the segregation of complex speech signals, and may thus find various applications in electronic devices such as for sound segregation and

Real time track finding in a drift chamber with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-01-01

In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

International Nuclear Information System (INIS)

Seidl, Albert; Klose, Helmut; Svoboda, Mildos

2004-01-01

1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

DEFF Research Database (Denmark)

Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

1991-01-01

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

POSSESSION, REVIEW FROM CULTURAL AND PSYCHIATRY

Directory of Open Access Journals (Sweden)

Ni Ketut Sri Diniari

2013-03-01

Full Text Available Possession is a culture related syndrome, commonly found in Indonesia including Bali. We can see this event in religion and cultural ceremony and at other times at school, home, and in society. This syndrome consist of temporary loss of self identification and environment awareness; in several events a person acts as if he/she was controlled by other being, magic force, spirit or ‘other forces’. There are still several different opinions about trance-possession, whether it is related to certain culture or is a part of mental disorder. DSM-IV-TR and PPDGJ-III defined trance-possession as mental disorder (dissociative for involuntary possession, if it is not a common activity, and if it is not a part of religion or cultural event. (MEDICINA 2012;43:37-40.

The human brain on a computer, the design neuromorphic chips aims to process information as does the mind; El cerebro humano en un ordenador

Energy Technology Data Exchange (ETDEWEB)

Pajuelo, L.

2015-07-01

Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

Individual ball possession in soccer.

Directory of Open Access Journals (Sweden)

Daniel Link

Full Text Available This paper describes models for detecting individual and team ball possession in soccer based on position data. The types of ball possession are classified as Individual Ball Possession (IBC, Individual Ball Action (IBA, Individual Ball Control (IBC, Team Ball Possession (TBP, Team Ball Control (TBC und Team Playmaking (TPM according to different starting points and endpoints and the type of ball control involved. The machine learning approach used is able to determine how long the ball spends in the sphere of influence of a player based on the distance between the players and the ball together with their direction of motion, speed and the acceleration of the ball. The degree of ball control exhibited during this phase is classified based on the spatio-temporal configuration of the player controlling the ball, the ball itself and opposing players using a Bayesian network. The evaluation and application of this approach uses data from 60 matches in the German Bundesliga season of 2013/14, including 69,667 IBA intervals. The identification rate was F = .88 for IBA and F = .83 for IBP, and the classification rate for IBC was κ = .67. Match analysis showed the following mean values per match: TBP 56:04 ± 5:12 min, TPM 50:01 ± 7:05 min and TBC 17:49 ± 8:13 min. There were 836 ± 424 IBC intervals per match and their number was significantly reduced by -5.1% from the 1st to 2nd half. The analysis of ball possession at the player level indicates shortest accumulated IBC times for the central forwards (0:49 ± 0:43 min and the longest for goalkeepers (1:38 ± 0:58 min, central defenders (1:38 ± 1:09 min and central midfielders (1:27 ± 1:08 min. The results could improve performance analysis in soccer, help to detect match events automatically, and allow discernment of higher value tactical structures, which is based on individual ball possession.

Sound stream segregation: a neuromorphic approach to solve the “cocktail party problem” in real-time

Science.gov (United States)

Thakur, Chetan Singh; Wang, Runchun M.; Afshar, Saeed; Hamilton, Tara J.; Tapson, Jonathan C.; Shamma, Shihab A.; van Schaik, André

2015-01-01

The human auditory system has the ability to segregate complex auditory scenes into a foreground component and a background, allowing us to listen to specific speech sounds from a mixture of sounds. Selective attention plays a crucial role in this process, colloquially known as the “cocktail party effect.” It has not been possible to build a machine that can emulate this human ability in real-time. Here, we have developed a framework for the implementation of a neuromorphic sound segregation algorithm in a Field Programmable Gate Array (FPGA). This algorithm is based on the principles of temporal coherence and uses an attention signal to separate a target sound stream from background noise. Temporal coherence implies that auditory features belonging to the same sound source are coherently modulated and evoke highly correlated neural response patterns. The basis for this form of sound segregation is that responses from pairs of channels that are strongly positively correlated belong to the same stream, while channels that are uncorrelated or anti-correlated belong to different streams. In our framework, we have used a neuromorphic cochlea as a frontend sound analyser to extract spatial information of the sound input, which then passes through band pass filters that extract the sound envelope at various modulation rates. Further stages include feature extraction and mask generation, which is finally used to reconstruct the targeted sound. Using sample tonal and speech mixtures, we show that our FPGA architecture is able to segregate sound sources in real-time. The accuracy of segregation is indicated by the high signal-to-noise ratio (SNR) of the segregated stream (90, 77, and 55 dB for simple tone, complex tone, and speech, respectively) as compared to the SNR of the mixture waveform (0 dB). This system may be easily extended for the segregation of complex speech signals, and may thus find various applications in electronic devices such as for sound segregation

Sound stream segregation: a neuromorphic approach to solve the ‘cocktail party problem’ in real-time

Directory of Open Access Journals (Sweden)

Chetan Singh Thakur

2015-09-01

Full Text Available The human auditory system has the ability to segregate complex auditory scenes into a foreground component and a background, allowing us to listen to specific speech sounds from a mixture of sounds. Selective attention plays a crucial role in this process, colloquially known as the ‘cocktail party effect’. It has not been possible to build a machine that can emulate this human ability in real-time. Here, we have developed a framework for the implementation of a neuromorphic sound segregation algorithm in a Field Programmable Gate Array (FPGA. This algorithm is based on the principles of temporal coherence and uses an attention signal to separate a target sound stream from background noise. Temporal coherence implies that auditory features belonging to the same sound source are coherently modulated and evoke highly correlated neural response patterns. The basis for this form of sound segregation is that responses from pairs of channels that are strongly positively correlated belong to the same stream, while channels that are uncorrelated or anti-correlated belong to different streams. In our framework, we have used a neuromorphic cochlea as a frontend sound analyser to extract spatial information of the sound input, which then passes through band pass filters that extract the sound envelope at various modulation rates. Further stages include feature extraction and mask generation, which is finally used to reconstruct the targeted sound. Using sample tonal and speech mixtures, we show that our FPGA architecture is able to segregate sound sources in real-time. The accuracy of segregation is indicated by the high signal-to-noise ratio (SNR of the segregated stream (90, 77 and 55 dB for simple tone, complex tone and speech, respectively as compared to the SNR of the mixture waveform (0 dB. This system may be easily extended for the segregation of complex speech signals, and may thus find various applications in electronic devices such as for

50 CFR 20.38 - Possession of live birds.

Science.gov (United States)

2010-10-01

... 50 Wildlife and Fisheries 6 2010-10-01 2010-10-01 false Possession of live birds. 20.38 Section 20... WILDLIFE AND PLANTS (CONTINUED) MIGRATORY BIRD HUNTING Possession § 20.38 Possession of live birds. Every migratory game bird wounded by hunting and reduced to possession by the hunter shall be immediately killed...

Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

CERN Document Server

Williams, John Michael

2014-01-01

This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

VLSI implementation of a bio-inspired olfactory spiking neural network.

Science.gov (United States)

Hsieh, Hung-Yi; Tang, Kea-Tiong

2012-07-01

This paper presents a low-power, neuromorphic spiking neural network (SNN) chip that can be integrated in an electronic nose system to classify odor. The proposed SNN takes advantage of sub-threshold oscillation and onset-latency representation to reduce power consumption and chip area, providing a more distinct output for each odor input. The synaptic weights between the mitral and cortical cells are modified according to an spike-timing-dependent plasticity learning rule. During the experiment, the odor data are sampled by a commercial electronic nose (Cyranose 320) and are normalized before training and testing to ensure that the classification result is only caused by learning. Measurement results show that the circuit only consumed an average power of approximately 3.6 μW with a 1-V power supply to discriminate odor data. The SNN has either a high or low output response for a given input odor, making it easy to determine whether the circuit has made the correct decision. The measurement result of the SNN chip and some well-known algorithms (support vector machine and the K-nearest neighbor program) is compared to demonstrate the classification performance of the proposed SNN chip.The mean testing accuracy is 87.59% for the data used in this paper.

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Directory of Open Access Journals (Sweden)

Urard Pascal

2006-01-01

Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

A theoretical and experimental study of neuromorphic atomic switch networks for reservoir computing.

Science.gov (United States)

Sillin, Henry O; Aguilera, Renato; Shieh, Hsien-Hang; Avizienis, Audrius V; Aono, Masakazu; Stieg, Adam Z; Gimzewski, James K

2013-09-27

Atomic switch networks (ASNs) have been shown to generate network level dynamics that resemble those observed in biological neural networks. To facilitate understanding and control of these behaviors, we developed a numerical model based on the synapse-like properties of individual atomic switches and the random nature of the network wiring. We validated the model against various experimental results highlighting the possibility to functionalize the network plasticity and the differences between an atomic switch in isolation and its behaviors in a network. The effects of changing connectivity density on the nonlinear dynamics were examined as characterized by higher harmonic generation in response to AC inputs. To demonstrate their utility for computation, we subjected the simulated network to training within the framework of reservoir computing and showed initial evidence of the ASN acting as a reservoir which may be optimized for specific tasks by adjusting the input gain. The work presented represents steps in a unified approach to experimentation and theory of complex systems to make ASNs a uniquely scalable platform for neuromorphic computing.

A Low-Power High-Speed Spintronics-Based Neuromorphic Computing System Using Real Time Tracking Method

DEFF Research Database (Denmark)

Farkhani, Hooman; Tohidi, Mohammad; Farkhani, Sadaf

2018-01-01

In spintronic-based neuromorphic computing systems (NCS), the switching of magnetic moment in a magnetic tunnel junction (MTJ) is used to mimic neuron firing. However, the stochastic switching behavior of the MTJ and process variations effect lead to a significant increase in stimulation time...... of such NCSs. Moreover, current NCSs need an extra phase to read the MTJ state after stimulation which is in contrast with real neuron functionality in human body. In this paper, the read circuit is replaced with a proposed real-time sensing (RTS) circuit. The RTS circuit tracks the MTJ state during...... stimulation phase. As soon as switching happens, the RTS circuit terminates the MTJ current and stimulates the post neuron. Hence, the RTS circuit not only improves the energy consumption and speed, but also makes the operation of NCS similar to real neuron functionality. The simulation results in 65-nm CMOS...

50 CFR 648.164 - Possession restrictions.

Science.gov (United States)

2010-10-01

... Atlantic Bluefish Fishery § 648.164 Possession restrictions. (a) No person shall possess more than 15 bluefish in, or harvested from, the EEZ unless that person is the owner or operator of a fishing vessel issued a bluefish commercial permit or is issued a bluefish dealer permit. Persons aboard a vessel that...

Synchrony detection and amplification by silicon neurons with STDP synapses.

Science.gov (United States)

Bofill-i-petit, Adria; Murray, Alan F

2004-09-01

Spike-timing dependent synaptic plasticity (STDP) is a form of plasticity driven by precise spike-timing differences between presynaptic and postsynaptic spikes. Thus, the learning rules underlying STDP are suitable for learning neuronal temporal phenomena such as spike-timing synchrony. It is well known that weight-independent STDP creates unstable learning processes resulting in balanced bimodal weight distributions. In this paper, we present a neuromorphic analog very large scale integration (VLSI) circuit that contains a feedforward network of silicon neurons with STDP synapses. The learning rule implemented can be tuned to have a moderate level of weight dependence. This helps stabilise the learning process and still generates binary weight distributions. From on-chip learning experiments we show that the chip can detect and amplify hierarchical spike-timing synchrony structures embedded in noisy spike trains. The weight distributions of the network emerging from learning are bimodal.

Possession States: Approaches to Clinical Evaluation and Classification

Directory of Open Access Journals (Sweden)

S. McCormick

1992-01-01

Full Text Available The fields of anthropology and sociology have produced a large quantity of literature on possession states, physicians however rarely report on such phenomena. As a result clinical description of possession states has suffered, even though these states may be more common and less deviant than supposed. Both ICD-10 and DSM-IV may include specific criteria for possession disorders. The authors briefly review Western notions about possession and kindred states and present guidelines for evaluation and classification.

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1982-01-01

A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

Minimizing the effect of process mismatch in a neuromorphic system using spike-timing-dependent adaptation.

Science.gov (United States)

Cameron, Katherine; Murray, Alan

2008-05-01

This paper investigates whether spike-timing-dependent plasticity (STDP) can minimize the effect of mismatch within the context of a depth-from-motion algorithm. To improve noise rejection, this algorithm contains a spike prediction element, whose performance is degraded by analog very large scale integration (VLSI) mismatch. The error between the actual spike arrival time and the prediction is used as the input to an STDP circuit, to improve future predictions. Before STDP adaptation, the error reflects the degree of mismatch within the prediction circuitry. After STDP adaptation, the error indicates to what extent the adaptive circuitry can minimize the effect of transistor mismatch. The circuitry is tested with static and varying prediction times and chip results are presented. The effect of noisy spikes is also investigated. Under all conditions the STDP adaptation is shown to improve performance.

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Directory of Open Access Journals (Sweden)

I. Hameem Shanavas

2014-01-01

Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

Science.gov (United States)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

Bio-inspired optical rotation sensor

Science.gov (United States)

O'Carroll, David C.; Shoemaker, Patrick A.; Brinkworth, Russell S. A.

2007-01-01

Traditional approaches to calculating self-motion from visual information in artificial devices have generally relied on object identification and/or correlation of image sections between successive frames. Such calculations are computationally expensive and real-time digital implementation requires powerful processors. In contrast flies arrive at essentially the same outcome, the estimation of self-motion, in a much smaller package using vastly less power. Despite the potential advantages and a few notable successes, few neuromorphic analog VLSI devices based on biological vision have been employed in practical applications to date. This paper describes a hardware implementation in aVLSI of our recently developed adaptive model for motion detection. The chip integrates motion over a linear array of local motion processors to give a single voltage output. Although the device lacks on-chip photodetectors, it includes bias circuits to use currents from external photodiodes, and we have integrated it with a ring-array of 40 photodiodes to form a visual rotation sensor. The ring configuration reduces pattern noise and combined with the pixel-wise adaptive characteristic of the underlying circuitry, permits a robust output that is proportional to image rotational velocity over a large range of speeds, and is largely independent of either mean luminance or the spatial structure of the image viewed. In principle, such devices could be used as an element of a velocity-based servo to replace or augment inertial guidance systems in applications such as mUAVs.

Possession divestment by sales in later life.

Science.gov (United States)

Ekerdt, David J; Addington, Aislinn

2015-08-01

Residential relocation in later life is almost always a downsizing, with many possessions to be divested in a short period of time. This article examines older movers' capacities for selling things, and ways that selling attenuates people's ties to those things, thus accomplishing the human dis-possession of the material convoy. In qualitative interviews in 79 households in the Midwestern United States, older adults reported their experience with possession sales associated with residential relocation. Among this group, three-quarters of the households downsized by selling some belongings. Informal sales seemed the least fraught of all strategies, estate sales had mixed reviews, and garage sales were recalled as laborious. Sellers' efforts were eased by social relations and social networks as helpers and buyers came forward. As selling proceeded, sentiment about possessions waned as their materiality and economic value came to the fore, easing their detachment from the household. Possession selling is challenging because older adults are limited in the knowledge, skills, and efforts that they can apply to the recommodification of their belongings. Selling can nonetheless be encouraged as a divestment strategy as long as the frustrations and drawbacks are transparent, and the goal of ridding is kept in view. Copyright © 2015 Elsevier Inc. All rights reserved.

Quasiperiodic AlGaAs superlattices for neuromorphic networks and nonlinear control systems

Energy Technology Data Exchange (ETDEWEB)

Malyshev, K. V., E-mail: malyshev@bmstu.ru [Electronics and Laser Technology Department, Bauman Moscow State Technical University, Moscow 105005 (Russian Federation)

2015-01-28

The application of quasiperiodic AlGaAs superlattices as a nonlinear element of the FitzHugh–Nagumo neuromorphic network is proposed and theoretically investigated on the example of Fibonacci and figurate superlattices. The sequences of symbols for the figurate superlattices were produced by decomposition of the Fibonacci superlattices' symbolic sequences. A length of each segment of the decomposition was equal to the corresponding figurate number. It is shown that a nonlinear network based upon Fibonacci and figurate superlattices provides better parallel filtration of a half-tone picture; then, a network based upon traditional diodes which have cubic voltage-current characteristics. It was found that the figurate superlattice F{sup 0}{sub 11}(1) as a nonlinear network's element provides the filtration error almost twice less than the conventional “cubic” diode. These advantages are explained by a wavelike shape of the decreasing part of the quasiperiodic superlattice's voltage-current characteristic, which leads to multistability of the network's cell. This multistability promises new interesting nonlinear dynamical phenomena. A variety of wavy forms of voltage-current characteristics opens up new interesting possibilities for quasiperiodic superlattices and especially for figurate superlattices in many areas—from nervous system modeling to nonlinear control systems development.

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Directory of Open Access Journals (Sweden)

Ying-Lun Chen

2015-08-01

Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

Bio-inspired vision

International Nuclear Information System (INIS)

Posch, C

2012-01-01

Nature still outperforms the most powerful computers in routine functions involving perception, sensing and actuation like vision, audition, and motion control, and is, most strikingly, orders of magnitude more energy-efficient than its artificial competitors. The reasons for the superior performance of biological systems are subject to diverse investigations, but it is clear that the form of hardware and the style of computation in nervous systems are fundamentally different from what is used in artificial synchronous information processing systems. Very generally speaking, biological neural systems rely on a large number of relatively simple, slow and unreliable processing elements and obtain performance and robustness from a massively parallel principle of operation and a high level of redundancy where the failure of single elements usually does not induce any observable system performance degradation. In the late 1980's, Carver Mead demonstrated that silicon VLSI technology can be employed in implementing ''neuromorphic'' circuits that mimic neural functions and fabricating building blocks that work like their biological role models. Neuromorphic systems, as the biological systems they model, are adaptive, fault-tolerant and scalable, and process information using energy-efficient, asynchronous, event-driven methods. In this paper, some basics of neuromorphic electronic engineering and its impact on recent developments in optical sensing and artificial vision are presented. It is demonstrated that bio-inspired vision systems have the potential to outperform conventional, frame-based vision acquisition and processing systems in many application fields and to establish new benchmarks in terms of redundancy suppression/data compression, dynamic range, temporal resolution and power efficiency to realize advanced functionality like 3D vision, object tracking, motor control, visual feedback loops, etc. in real-time. It is argued that future artificial vision systems

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

OpenAIRE

Giacomo Indiveri

2008-01-01

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computation...

A 2-transistor/1-resistor artificial synapse capable of communication and stochastic learning in neuromorphic systems.

Science.gov (United States)

Wang, Zhongqiang; Ambrogio, Stefano; Balatti, Simone; Ielmini, Daniele

2014-01-01

Resistive (or memristive) switching devices based on metal oxides find applications in memory, logic and neuromorphic computing systems. Their small area, low power operation, and high functionality meet the challenges of brain-inspired computing aiming at achieving a huge density of active connections (synapses) with low operation power. This work presents a new artificial synapse scheme, consisting of a memristive switch connected to 2 transistors responsible for gating the communication and learning operations. Spike timing dependent plasticity (STDP) is achieved through appropriate shaping of the pre-synaptic and the post synaptic spikes. Experiments with integrated artificial synapses demonstrate STDP with stochastic behavior due to (i) the natural variability of set/reset processes in the nanoscale switch, and (ii) the different response of the switch to a given stimulus depending on the initial state. Experimental results are confirmed by model-based simulations of the memristive switching. Finally, system-level simulations of a 2-layer neural network and a simplified STDP model show random learning and recognition of patterns.

Using neuromorphic optical sensors for spacecraft absolute and relative navigation

Science.gov (United States)

Shake, Christopher M.

We develop a novel attitude determination system (ADS) for use on nano spacecraft using neuromorphic optical sensors. The ADS intends to support nano-satellite operations by providing low-cost, low-mass, low-volume, low-power, and redundant attitude determination capabilities with quick and straightforward onboard programmability for real time spacecraft operations. The ADS is experimentally validated with commercial-off-the-shelf optical devices that perform sensing and image processing on the same circuit board and are biologically inspired by insects' vision systems, which measure optical flow while navigating in the environment. The firmware on the devices is modified to both perform the additional biologically inspired task of tracking objects and communicate with a PC/104 form-factor embedded computer running Real Time Application Interface Linux used on a spacecraft simulator. Algorithms are developed for operations using optical flow, point tracking, and hybrid modes with the sensors, and the performance of the system in all three modes is assessed using a spacecraft simulator in the Advanced Autonomous Multiple Spacecraft (ADAMUS) laboratory at Rensselaer. An existing relative state determination method is identified to be combined with the novel ADS to create a self-contained navigation system for nano spacecraft. The performance of the method is assessed in simulation and found not to match the results from its authors using only conditions and equations already published. An improved target inertia tensor method is proposed as an update to the existing relative state method, but found not to perform as expected, but is presented for others to build upon.

22 CFR 72.14 - Nominal possession; property not normally taken into physical possession.

Science.gov (United States)

2010-04-01

... possession. (a) When a consular officer take articles of a decedent's personal property from a foreign... Department discharging the consular officer of any responsibility for the articles transferred. (b) A... effects; (2) Motor vehicles, airplanes or watercraft; (3) Toiletries, such as toothpaste or razors; (4...

Possessive Pronouns in European Portuguese and Old French

Directory of Open Access Journals (Sweden)

Matilde Miguel

2002-12-01

Full Text Available The aim of this paper is to bring European Portuguese (EP data into light, showing that, in spite of the lack of morphological evidence, the syntactic behaviour of possessives, across EP dialects, shows evidences for a tripartite possessive system (Cardinaletti, 1998; Cardinaletti & Starke, 1999. It will be argued that the syntactic position of possessives parallels the positions assumed for EP sentential subjects in non interrogative contexts: [Spec, AgrsP], [Spec, TP] and [Spec, VP]. As a matter of fact, depending on their syntactic properties and assuming, as null hypothesis, that the nominal head moves to Numb'º', possessives may occur in [Spec, AgrsNP], [Spec, NumbP] and [Spec, NP]. Furthermore, would it be so, this dialectal variation would be useful in order to understand the changes that have occurred in other romance languages in previous stages. It might be the case that the loss of weak possessive forms (“mien” in French parallels, among other things, the lack of sentential subjects in [Spec, TP].

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

Science.gov (United States)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

LEGAL SIGNIFICANCE AND PROTECTION OF POSSESSION IN THE REPUBLIC OF MACEDONIA

Directory of Open Access Journals (Sweden)

Vojo Belovski

2015-04-01

Full Text Available In this paper it will be discussed the legal significance and protection of possession in the Republic of Macedonia. Below it will be listed the kinds of possession, and finally the rules for possession termination will be explained. The possession is an indicator that the person who rules one item is also a right holder of that item. The possession itself occurs in two types specially authorized by a law and pure factual power behind which stands no right. The possession enjoys legal protection. Below in the paper it is processed the judicial protection of the possession which is given based on complaint for disturbance of possession and action to recover the possession. The important thing at the judicial protection is that the rulers’ protection is given to the last actual possession of the item, but it is not disputed the right of possession. Further in this paper it is included the protection of indirect possession where a complaint can be made by the indirect holder of the item, the judicial protection of possessory, possession protection of the heirs and permitted self – help for unauthorized harassment and revoking of the possession. With respect to the termination of the actual power of the item, listed and processed are the ways when the item failed, when the item was lost, when it is obvious that it won’t be returned, when the ruler had freely left it and when the item is not taken from him and the ruler hasn’t realized the right to possession.

Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

Science.gov (United States)

Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

1989-01-01

The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

The epistemological significance of possession entering the DSM.

Science.gov (United States)

Stephenson, Craig

2015-09-01

The discourse of the American Psychiatric Association's DSM reflects the inherently dialogic or contradictory nature of its stated mandate to demonstrate both 'nosological completeness' and cultural 'inclusiveness'. Psychiatry employs the dialogic discourse of the DSM in a one-sided, positivistic manner by identifying what it considers universal mental disease entities stripped of their cultural context. In 1992 the editors of the Diagnostic and Statistical Manual of Mental Disorders proposed to introduce possession into their revisions. A survey of the discussions about introducing 'possession' as a dissociative disorder to be listed in the DSM-IV indicates a missed epistemological break. Subsequently the editors of the DSM-5 politically 'recuperated' possession into its official discourse, without acknowledging the anarchic challenges that possession presents to psychiatry as a cultural practice. © The Author(s) 2015.

Subself theory and reincarnation/possession.

Science.gov (United States)

Lester, David

2004-12-01

A subself model of the mind is used to account for multiple personality, possession, the spirit controls of mediums, reincarnation, and the auditory hallucinations of schizophrenics, with suggestions for empirical research.

Effect of playing tactics on achieving score-box possessions in a random series of team possessions from Norwegian professional soccer matches.

Science.gov (United States)

Tenga, Albin; Holme, Ingar; Ronglan, Lars Tore; Bahr, Roald

2010-02-01

Methods of analysis that include an assessment of opponent interactions are thought to provide a more valid means of team match performance. The purpose of this study was to examine the effect of playing tactics on achieving score-box possession by assessing opponent interactions in Norwegian elite soccer matches. We analysed a random series of 1703 team possessions from 163 of 182 (90%) matches played in the professional men's league during the 2004 season. Multidimensional qualitative data obtained from ten ordered categorical variables were used. Offensive tactics were more effective in producing score-box possessions when playing against an imbalanced defence (28.5%) than against a balanced defence (6.5%) (P tactics on producing score-box possessions, and improves the validity of team match-performance analysis in soccer.

An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

Science.gov (United States)

Chandaliya, Mudit; Chaturvedi, Nitin; Gurunarayanan, S.

2018-03-01

The current microprocessors has shown a remarkable performance and memory capacity improvement since its innovation. However, due to power and thermal limitations, only a fraction of cores can operate at full frequency at any instant of time irrespective of the advantages of new technology generation. This phenomenon of under-utilization of microprocessor is called as dark silicon which leads to distraction in innovative computing. To overcome the limitation of utilization wall, IBM technologies explored and invented neurosynaptic system chips. It has opened a wide scope of research in the field of innovative computing, technology, material sciences, machine learning etc. In this paper, we first reviewed the diverse stages of research that have been influential in the innovation of neurosynaptic architectures. These, architectures focuses on the development of brain-like framework which is efficient enough to execute a broad set of computations in real time while maintaining ultra-low power consumption as well as area considerations in mind. We also reveal the inadvertent challenges and the opportunities of designing neuromorphic systems as presented by the existing technologies in the dark silicon era, which constitute the utmost area of research in future.

POSSESSION VERSUS POSITION: STRATEGIC EVALUATION IN AFL

Directory of Open Access Journals (Sweden)

Darren M. O'Shaughnessy

2006-12-01

Full Text Available In sports like Australian Rules football and soccer, teams must battle to achieve possession of the ball in sufficient space to make optimal use of it. Ultimately the teams need to score, and to do that the ball must be brought into the area in front of goal - the place where the defence usually concentrates on shutting down space and opportunity time. Coaches would like to quantify the trade-offs between contested play in good positions and uncontested play in less promising positions, in order to inform their decision-making about where to put their players, and when to gamble on sending the ball to a contest rather than simply maintain possession. To evaluate football strategies, Champion Data has collected the on-ground locations of all 350,000 possessions and stoppages in the past two seasons of AFL (2004, 2005. By following each chain of play through to the next score, we can now reliably estimate the scoreboard "equity" of possessing the ball at any location, and measure the effect of having sufficient time to dispose of it effectively. As expected, winning the ball under physical pressure (through a "hard ball get" is far more difficult to convert into a score than winning it via a mark. We also analyse some equity gradients to show how getting the ball 20 metres closer to goal is much more important in certain areas of the ground than in others. We conclude by looking at the choices faced by players in possession wanting to maximise their likelihood of success

Possession experiences in dissociative identity disorder: a preliminary study.

Science.gov (United States)

Ross, Colin A

2011-01-01

Dissociative trance disorder, which includes possession experiences, was introduced as a provisional diagnosis requiring further study in the Diagnostic and Statistical Manual of Mental Disorders (4th ed.). Consideration is now being given to including possession experiences within dissociative identity disorder (DID) in the Diagnostic and Statistical Manual of Mental Disorders (5th ed.), which is due to be published in 2013. In order to provide empirical data relevant to the relationship between DID and possession states, I analyzed data on the prevalence of trance, possession states, sleepwalking, and paranormal experiences in 3 large samples: patients with DID from North America; psychiatric outpatients from Shanghai, China; and a general population sample from Winnipeg, Canada. Trance, sleepwalking, paranormal, and possession experiences were much more common in the DID patients than in the 2 comparison samples. The study is preliminary and exploratory in nature because the samples were not matched in any way.

The Failed Image and the Possessed

DEFF Research Database (Denmark)

Suhr, Christian

2015-01-01

This article asks if the recurrent queries regarding the value of images in visual anthropology could find new answers by exploring responses to visual media in neo-orthodox Islam. It proposes that the visual display of the photographic image shares a curious resemblance to the bodies of people...... possessed by invisible spirits called jinn. The image as a failed example or model of reality works like the possessed body as an amplifier of invisibility pointing towards that which cannot be seen, depicted visually, or represented in writing. This suggests a negative epistemology in which images obtain...

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

Science.gov (United States)

Makhijani, Vinod B.; Przekwas, Andrzej J.

2002-10-01

This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

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N.R. Divya

2014-08-01

Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

Science.gov (United States)

Cho, Hwasuk; Son, Hyunwoo; Seong, Kihwan; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2018-02-01

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

The Impact of Banning Juvenile Gun Possession.

OpenAIRE

Marvell, Thomas B

2001-01-01

A 1994 federal law bans possession of handguns by persons under 18 years of age. Also in 1994, 11 states passed their own juvenile gun possession bans. Eighteen states had previously passed bans, 15 of them between 1975 and 1993. These laws were intended to reduce homicides, but arguments can be made that they have no effect on or that they even increase the homicide rate. This paper estimates the laws' impacts on various crime measures, primarily juvenile gun homicide victimizations and suic...

The goalkeeper influence on ball possession effectiveness in futsal

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Vicente-Vila Pedro

2016-06-01

Full Text Available The aim of this study was to identify which variables were the best predictors of success in futsal ball possession when controlling for space and task related indicators, situational variables and the participation of the goalkeeper as a regular field player or not (5 vs. 4 or 4 vs. 4. The sample consisted of 326 situations of ball possession corresponding to 31 matches played by a team from the Spanish Futsal League during the 2010–2011, 2011–2012 and 2012–2013 seasons. Multidimensional qualitative data obtained from 10 ordered categorical variables were used. Data were analysed using chi-square analysis and multiple logistic regression analysis. Overall, the highest ball possession effectiveness was achieved when the goalkeeper participated as a regular field player (p<0.01, the duration of the ball possession was less than 10 s (p<0.01, the ball possession ended in the penalty area (p<0.01 and the defensive pressure was low (p<0.01. The information obtained on the relative effectiveness of offensive playing tactics can be used to improve team’s goal-scoring and goal preventing abilities.

The expected value of possession in professional rugby league match-play.

Science.gov (United States)

Kempton, Thomas; Kennedy, Nicholas; Coutts, Aaron J

2016-01-01

This study estimated the expected point value for starting possessions in different field locations during rugby league match-play and calculated the mean expected points for each subsequent play during the possession. It also examined the origin of tries scored according to the method of gaining possession. Play-by-play data were taken from all 768 regular-season National Rugby League (NRL) matches during 2010-2013. A probabilistic model estimated the expected point outcome based on the net difference in points scored by a team in possession in a given situation. An iterative method was used to approximate the value of each situation based on actual scoring outcomes. Possessions commencing close to the opposition's goal-line had the highest expected point equity, which decreased as the location of the possession moved towards the team's own goal-line. Possessions following an opposition error, penalty or goal-line dropout had the highest likelihood of a try being scored on the set subsequent to their occurrence. In contrast, possessions that follow an opposition completed set or a restart were least likely to result in a try. The expected point values framework from our model has applications for informing playing strategy and assessing individual and team performance in professional rugby league.

Pathological spirit possession as a cultural interpretation of trauma-related symptoms.

Science.gov (United States)

Hecker, Tobias; Barnewitz, Eva; Stenmark, Hakon; Iversen, Valentina

2016-07-01

Spirit possession is a phenomenon frequently occurring in war-torn countries. It has been shown to be an idiom of distress entailing dissociative symptoms. However, its association with trauma exposure and trauma-related disorders remains unclear. This study aimed to explore subjective disease models and the relationship between pathological spirit possession and trauma-related disorders in the Eastern Democratic Republic of the Congo. Seventy-three (formerly) possessed persons (74% female, mean age = 34 years), referred by traditional and spiritual healers, were interviewed about their experiences of pathological spirit possession, trauma exposure, posttraumatic stress disorder (PTSD) symptoms, depressive symptoms, shame and guilt, psychotic symptoms, somatic complaints, and the impairment of psychosocial functioning. The most common disease model for pathological spirit possession was another person having sent the spirit, mostly a family member or a neighbor, out of jealousy or conflict over resources. Significant correlations were found between spirit possession over lifetime and PTSD symptom severity, feelings of shame and guilt, depressive symptoms, somatic complaints, and psychotic symptoms. Spirit possession during the preceding 4 weeks was associated with PTSD symptom severity, impairment of psychosocial functioning, and psychotic symptom severity. The results of this study indicate that pathological spirit possession is a broad explanatory framework for various subjectively unexplainable mental and physical health problems, including but not limited to trauma-related disorders. Understanding pathological spirit possession as a subjective disease model for various mental and physical health problems may help researchers and clinicians to develop culturally sensitive treatment approaches for affected individuals. (PsycINFO Database Record (c) 2016 APA, all rights reserved).

Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

Energy Technology Data Exchange (ETDEWEB)

Zhang, B

1999-07-01

This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

Mental illness complicated by the santeria belief in spirit possession.

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Alonso, L; Jeffrey, W D

1988-11-01

Santeria, a religious system that blends African and Catholic beliefs, is practiced by many Cuban Americans. One aspect of this system is the belief in spirit possession. Basic santeria beliefs and rituals, including the fiesta santera (a gathering at which some participants may become possessed), are briefly described, and four cases in which the patients' belief in possession played a role in their mental illness are presented. The belief in possession can complicate the diagnosis and treatment of mental illness, but it should not be considered a culture-bound syndrome. Rather, it may be a nonspecific symptom of a variety of mental illnesses and should be evaluated in the context of the patient's overall belief system and ability to carry out usual activities.

Dynamics of the spirit possession phenomenon in Eastern Tanzania

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Marja-Liisa Swantz

1976-01-01

Full Text Available The discussion on the spirit possession phenomenon is related in this study to the more general question of the role of religious institutions as part in the development process of a people living in a limited geographical area of a wider national society. It is assumed that religion, like culture in general, has its specific institutional forms as result of the historical development of a society, but at the same time religion is a force shaping that history. People's cultural resources influence their social and economic development and form a potential creative element in it'. Some of the questions to be asked are: "How are specific religious practices related to the dynamics of change in the societies in question? What is the social and religious context in which the spirit possession phenomenon occurs in them? What social and economic relations get their expression in them? To what extent is spirit possession in this case a means of exerting values and creatively overcoming a crisis or conflict which the changing social and economic relations impose on the people? The established spirit possession cults are here seen as the institutional forms of religious experience. At the same time it becomes evident that there is institutionalization in process as well as deinstitutionalization of spirit possession where it occurs outside established institutional forms. Institution is taken as a socially shared form of behaviour the significance of which is commonly recognized by those who share it. By the term spirit possession cult is meant a ritual form of spirit possession of a group which is loosely organized and without strict membership. The context of the study is four ethnic groups in Eastern Tanzania, near the coast of the Indian Ocean. The general theme of the project is The Role of Culture in the Restructuring of Tanzanian Rural Areas. The restructuring refers to a villagisation programme carried out in the whole country. People are being

CMOS VLSI Active-Pixel Sensor for Tracking

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Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Emotional regulation, attachment to possessions and hoarding symptoms.

Science.gov (United States)

Phung, Philip J; Moulding, Richard; Taylor, Jasmine K; Nedeljkovic, Maja

2015-10-01

This study aimed to test which particular facets of emotion regulation (ER) are most linked to symptoms of hoarding disorder, and whether beliefs about emotional attachment to possessions (EA) mediate this relationship. A non-clinical sample of 150 participants (108 females) completed questionnaires of emotional tolerance (distress tolerance, anxiety sensitivity, negative urgency - impulsivity when experiencing negative emotions), depressed mood, hoarding, and beliefs about emotional attachment to possessions. While all emotional tolerance measures related to hoarding, when considered together and controlling for depression and age, anxiety sensitivity and urgency were the significant predictors. Anxiety sensitivity was fully mediated, and urgency partially mediated, via beliefs regarding emotional attachment to possessions. These findings provide further support for (1) the importance of anxiety sensitivity and negative urgency for hoarding symptoms, and (2) the view that individuals with HD symptoms may rely on items for emotion regulation, leading to stronger beliefs that items are integral to emotional wellbeing. © 2015 Scandinavian Psychological Associations and John Wiley & Sons Ltd.

Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

CERN Document Server

Hu, Kai; Ho, Tsung-Yi

2017-01-01

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

Taking Possession: Rituals, Space and Authority

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Jennifer Mara DeSilva

2016-12-01

Full Text Available In early modern Europe authority over communities, both people and spaces, was visualized through ritual gestures and processions. Communities gathered to witness ceremonial entries that drew on accepted forms of gestures and speech identifying individuals and articulating their place in the urban power relationship. Ceremonial entries by rulers, ambassadors, bishops, and other office-holders drew on ritual acts projecting messages of possession in order to establish reputations of prestige and authority. This introductory essay draws on cultural anthropology and recent historiography to build a framework for understanding rituals of possession that went beyond the tradition triumphal entry to incorporate substitutes, new modes of prestigious display, and attend to conflicts. By “taking possession” of communities, offices, and spaces using accepted ritual forms, early moderns initiated conversations about authority and power that were far more flexible in their scope, practice, and participants than expected.

From distress to disease: a critique of the medicalisation of possession in DSM-5.

Science.gov (United States)

Padmanabhan, Divya

2017-12-01

This paper critiques the category of possession-form dissociative identity disorder as defined in the Diagnostic and Statistical Manual of Mental Disorders 5 (DSM-5) published in 2013 by the American Psychiatric Association (APA). The DSM as an index of psychiatry pathologises possession by categorising it as a form of dissociative identity disorder. Drawing upon ethnographic fieldwork, this paper argues that such a pathologisation medicalises possession, which is understood as a non-pathological condition in other contexts such as by those individuals who manifest possession at a temple in Kerala, South India. Through medicalising and further by creating distinctions between acceptable and pathological possession, the DSM converts a form of distress into a disease. This has both conceptual and pragmatic implications. The temple therefore becomes reduced to a culturally acceptable site for the manifestation of a mental illness in a form that is culturally available and possession is explained solely through a biomedical framework, denying alternative conceptualisations and theories which inform possession. By focussing on the DSM-5 classification of possession and the limitations of such a classification, this paper seeks to posit an alternative conceptualisation of possession by engaging with three primary areas which are significant in the DSM categorisation of possession: the DSM's conceptualisation of self in the singular, the distinction between pathological and non-pathological forms of possession, and the limitations of the DSM's equation of the condition of possession with the manifestation of possession. Finally, the paper briefly highlights alternative conceptualisations of possession, which emerged from the perspective of those seeking to heal possession at the Chottanikkara temple.

Traumatic Experience and Somatoform Dissociation Among Spirit Possession Practitioners in the Dominican Republic.

Science.gov (United States)

Schaffler, Yvonne; Cardeña, Etzel; Reijman, Sophie; Haluza, Daniela

2016-03-01

Recent studies in African contexts have revealed a strong association between spirit possession and severe trauma, with inclusion into a possession cult serving at times a therapeutic function. Research on spirit possession in the Dominican Republic has so far not included quantitative studies of trauma and dissociation. This study evaluated demographic variables, somatoform dissociative symptoms, and potentially traumatizing events in the Dominican Republic with a group of Vodou practitioners that either do or do not experience spirit possession. Inter-group comparisons revealed that in contrast to non-possessed participants (n = 38), those experiencing spirit possession (n = 47) reported greater somatoform dissociation, more problems with sleep, and previous exposure to mortal danger such as assaults, accidents, or diseases. The two groups did not differ significantly in other types of trauma. The best predictor variable for group classification was somatoform dissociation, although those items could also reflect the experience of followers during a possession episode. A factor analysis across variables resulted in three factors: having to take responsibility early on in life and taking on a professional spiritual role; traumatic events and pain; and distress/dissociation. In comparison with the non-possessed individuals, the possessed ones did not seem to overall have a remarkably more severe story of trauma and seemed to derive economic gains from possession practice.

Instar and outstar learning with memristive nanodevices

International Nuclear Information System (INIS)

Snider, Greg

2011-01-01

The instar and outstar synaptic models are among the oldest and most useful in the field of neural networks. In this paper we show how to approximate the behavior of instar and outstar synapses in neuromorphic electronic systems using memristive nanodevices and spiking neurons. Memristive nanodevices are especially attractive for this application since such devices are tiny, can be densely packed in crossbar-like structures and possess the long time constants, or memory, needed by the synaptic models.

50 CFR 92.6 - Use and possession of migratory birds.

Science.gov (United States)

2010-10-01

... 50 Wildlife and Fisheries 6 2010-10-01 2010-10-01 false Use and possession of migratory birds. 92... INTERIOR (CONTINUED) MISCELLANEOUS PROVISIONS MIGRATORY BIRD SUBSISTENCE HARVEST IN ALASKA General Provisions § 92.6 Use and possession of migratory birds. You may not sell, offer for sale, purchase, or offer...

Co-possession of phosphodiesterase type-5 inhibitors (PDE5-I) with nitrates.

Science.gov (United States)

Chang, Li-Ling; Ma, Mark; Allmen, Heather von; Henderson, Scott C; Harper, Kristine; Hornbuckle, Kenneth

2010-06-01

Estimate the proportion of phosphodiesterase type-5 inhibitor (PDE5-I) patients who co-possess nitrates and compare the proportion of tadalafil patients dispensed nitrates to a matched control group. Secondarily, examine the percentage of co-possession of PDE5-Is and nitrates where the products were dispensed on the same day or written by the same prescriber. Male patients aged 18+ years filling PDE5-I prescriptions between December 2003 and March 2006 were identified using a U.S. longitudinal prescription database (IMS Health LRx). Similar patients not dispensed a PDE5-I during this period were matched to the tadalafil-dispensed cohort using a propensity score approach. Co-possession, as a proxy for concurrent use, was defined as an overlap in time on therapy for a PDE5-I and nitrate and was compared for the three PDE5-Is and for tadalafil to the matched control group. Among 601,063 tadalafil patients, 3.31% were dispensed a nitrate during the study period, compared to 6.18% in control patients (n = 601,063). When co-possessed prescriptions were defined by overlapping exposure periods, the proportion of PDE5-I patients with co-possessed nitrates ranged from 1.44% (tadalafil) to 1.72% (vardenafil) and 2.13% (sildenafil). Co-possession percentages of PDE5-I prescriptions were 0.83% for tadalafil and 1.07% for sildenafil and vardenafil. The majority (54.29%) of co-possessed PDE5-I and nitrate prescriptions had the nitrate dispensed prior to the PDE5-I prescription identified in the study cohort. Keeping in mind the limitations of observational studies, these results suggest that co-dispensing of nitrates and PDE5-Is is low. Compared to control patients, the proportion of nitrate co-possession was lowest for patients filling tadalafil. Tadalafil patients also had the lowest co-possessed proportion among the three PDE5-I cohorts. While the majority of co-possessed drug pairs were prescribed by different providers, the highest percentage of co-prescribing from the same

Possession Zone as a Performance Indicator in Football. The Game of the Best Teams

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Claudio A. Casal

2017-07-01

Full Text Available Possession time in football has been widely discussed in research but few studies have analyzed the importance of the field area in which possession occurs. The objective of this study was to identify the existence of significant differences in the field zone of ball possession between successful and unsuccessful teams and to acknowledge if the match status modulates the possession model. To this end, 2,284 attacks were analyzed corresponding to the matches in the final phase of the UEFA Euro 2016 France, recording possession time and field zone in which possession occurred. Video recordings of matches were analyzed and coded post-event using notational analysis. We have found that successful offensive game patterns are different from unsuccessful ones. Specifically, field zone in which major possession occurs changes significantly between successful and unsuccessful teams (x2 = 15.72, p < 0.05 and through Welch’s T significant differences were detected in possession time between successful and unsuccessful teams (H = 24.289, p < 0.001. The former are characterized by longer possession times, preferably in the middle offensive zone, on the other hand, unsuccessful teams have shorter possession times and preferably on the middle defensive zone. Logistic regression also allowed us to identify that greater possession in the middle offensive zone is a good indicator of success in the offensive game, allowing us to predict a greater chance of victory in the match. Specifically, every time the teams achieve possession in the middle offensive zone, the chance of winning the match will increase 1.72 times and, the probability of winning the match making longer possessions in the middle offensive zone is 44.25%. Applying the Kruskal–Wallis test we have also been able to verify how match status modulates the teams possession time, specifically, when teams are winning they have longer possessions x2 = 92.628, p = 0.011. Results obtained are expected to

An Extreme Learning Machine-Based Neuromorphic Tactile Sensing System for Texture Recognition.

Science.gov (United States)

Rasouli, Mahdi; Chen, Yi; Basu, Arindam; Kukreja, Sunil L; Thakor, Nitish V

2018-04-01

Despite significant advances in computational algorithms and development of tactile sensors, artificial tactile sensing is strikingly less efficient and capable than the human tactile perception. Inspired by efficiency of biological systems, we aim to develop a neuromorphic system for tactile pattern recognition. We particularly target texture recognition as it is one of the most necessary and challenging tasks for artificial sensory systems. Our system consists of a piezoresistive fabric material as the sensor to emulate skin, an interface that produces spike patterns to mimic neural signals from mechanoreceptors, and an extreme learning machine (ELM) chip to analyze spiking activity. Benefiting from intrinsic advantages of biologically inspired event-driven systems and massively parallel and energy-efficient processing capabilities of the ELM chip, the proposed architecture offers a fast and energy-efficient alternative for processing tactile information. Moreover, it provides the opportunity for the development of low-cost tactile modules for large-area applications by integration of sensors and processing circuits. We demonstrate the recognition capability of our system in a texture discrimination task, where it achieves a classification accuracy of 92% for categorization of ten graded textures. Our results confirm that there exists a tradeoff between response time and classification accuracy (and information transfer rate). A faster decision can be achieved at early time steps or by using a shorter time window. This, however, results in deterioration of the classification accuracy and information transfer rate. We further observe that there exists a tradeoff between the classification accuracy and the input spike rate (and thus energy consumption). Our work substantiates the importance of development of efficient sparse codes for encoding sensory data to improve the energy efficiency. These results have a significance for a wide range of wearable, robotic

Neural Mechanisms of Cortical Motion Computation Based on a Neuromorphic Sensory System

Science.gov (United States)

Abdul-Kreem, Luma Issa; Neumann, Heiko

2015-01-01

The visual cortex analyzes motion information along hierarchically arranged visual areas that interact through bidirectional interconnections. This work suggests a bio-inspired visual model focusing on the interactions of the cortical areas in which a new mechanism of feedforward and feedback processing are introduced. The model uses a neuromorphic vision sensor (silicon retina) that simulates the spike-generation functionality of the biological retina. Our model takes into account two main model visual areas, namely V1 and MT, with different feature selectivities. The initial motion is estimated in model area V1 using spatiotemporal filters to locally detect the direction of motion. Here, we adapt the filtering scheme originally suggested by Adelson and Bergen to make it consistent with the spike representation of the DVS. The responses of area V1 are weighted and pooled by area MT cells which are selective to different velocities, i.e. direction and speed. Such feature selectivity is here derived from compositions of activities in the spatio-temporal domain and integrating over larger space-time regions (receptive fields). In order to account for the bidirectional coupling of cortical areas we match properties of the feature selectivity in both areas for feedback processing. For such linkage we integrate the responses over different speeds along a particular preferred direction. Normalization of activities is carried out over the spatial as well as the feature domains to balance the activities of individual neurons in model areas V1 and MT. Our model was tested using different stimuli that moved in different directions. The results reveal that the error margin between the estimated motion and synthetic ground truth is decreased in area MT comparing with the initial estimation of area V1. In addition, the modulated V1 cell activations shows an enhancement of the initial motion estimation that is steered by feedback signals from MT cells. PMID:26554589

Neural Mechanisms of Cortical Motion Computation Based on a Neuromorphic Sensory System.

Directory of Open Access Journals (Sweden)

Luma Issa Abdul-Kreem

Full Text Available The visual cortex analyzes motion information along hierarchically arranged visual areas that interact through bidirectional interconnections. This work suggests a bio-inspired visual model focusing on the interactions of the cortical areas in which a new mechanism of feedforward and feedback processing are introduced. The model uses a neuromorphic vision sensor (silicon retina that simulates the spike-generation functionality of the biological retina. Our model takes into account two main model visual areas, namely V1 and MT, with different feature selectivities. The initial motion is estimated in model area V1 using spatiotemporal filters to locally detect the direction of motion. Here, we adapt the filtering scheme originally suggested by Adelson and Bergen to make it consistent with the spike representation of the DVS. The responses of area V1 are weighted and pooled by area MT cells which are selective to different velocities, i.e. direction and speed. Such feature selectivity is here derived from compositions of activities in the spatio-temporal domain and integrating over larger space-time regions (receptive fields. In order to account for the bidirectional coupling of cortical areas we match properties of the feature selectivity in both areas for feedback processing. For such linkage we integrate the responses over different speeds along a particular preferred direction. Normalization of activities is carried out over the spatial as well as the feature domains to balance the activities of individual neurons in model areas V1 and MT. Our model was tested using different stimuli that moved in different directions. The results reveal that the error margin between the estimated motion and synthetic ground truth is decreased in area MT comparing with the initial estimation of area V1. In addition, the modulated V1 cell activations shows an enhancement of the initial motion estimation that is steered by feedback signals from MT cells.

The Regulation of the Possession of Weapons at Gatherings

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Pieter du Toit

2013-12-01

Full Text Available The Dangerous Weapons Act 15 of 2013 provides for certain prohibitions and restrictions in respect of the possession of a dangerous weapon and it repeals the Dangerous Weapons Act 71 of 1968 as well as the different Dangerous Weapons Acts in operation in the erstwhile TBVC States. The Act also amends the Regulation of Gatherings Act 205 of 1993 to prohibit the possession of any dangerous weapon at a gathering or demonstration. The Dangerous Weapons Act provides for a uniform system of law governing the use of dangerous weapons for the whole of South Africa and it furthermore no longer places the onus on the individual charged with the offence of the possession of a dangerous weapon to show that he or she did not have any intention of using the firearm for an unlawful purpose. The Act also defines the meaning of a dangerous weapon. According to our court’s interpretation of the Dangerous Weapons Act 71 of 1968 a dangerous weapon was regarded as an object used or intended to be used as a weapon even if it had not been designed for use as a weapon. The Act, however, requires the object to be capable of causing death or inflicting serious bodily harm if it were used for an unlawful purpose. The possession of a dangerous weapon, in circumstances which may raise a reasonable suspicion that the person intends to use it for an unlawful purpose, attracts criminal liability. The Act also provides a useful set of guidelines to assist courts to determine if a person charged with the offence of the possession of a dangerous weapon had indeed intended to use the weapon for an unlawful purpose. It seems, however, that the Act prohibits the possession of a dangerous weapon at gatherings, even if the person carrying the weapon does not intend to use it for an unlawful purpose. The state will, however, have to prove that the accused had the necessary control over the object and the intention to exercise such control, as well as that the object is capable of

Digital possessions after a romantic break up

NARCIS (Netherlands)

Herron, Daniel; Moncur, Wendy; van den Hoven, Elise

2016-01-01

With technology becoming more pervasive in everyday life, it is common for individuals to use digital media to support the enactment and maintenance of romantic relationships. Partners in a relationship may create digital possessions frequently. However, after a relationship ends, individuals

Are symptoms of spirit possessed patients covered by the DSM-IV or DSM-5 criteria for possession trance disorder? A mixed-method explorative study in Uganda

NARCIS (Netherlands)

van Duijl, M.; Kleyn, W.; de Jong, J.

2013-01-01

Introduction and aims As in many cultures, spirit possession is a common idiom of distress in Uganda. The DSM-IV contains experimental research criteria for dissociative and possession trance disorder (DTD and PTD), which are under review for the DSM-5. In the current proposed categories of the

Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

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Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

2012-01-01

Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

Science.gov (United States)

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

Directory of Open Access Journals (Sweden)

B. SENTHILKUMAR

2015-05-01

Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

"Satan has afflicted me!" Jinn-possession and mental illness in the Qur'an.

Science.gov (United States)

Islam, F; Campbell, R A

2014-02-01

Mental health stigma in Muslim communities may be partly due to a commonly held belief among some Muslims about the supernatural causes of mental illness (i.e. jinn-possession brought on by one's sinful life). A thematic analysis was carried out on four English translations and the Arabic text of the Qur'an to explore whether the connection between jinn-possession and insanity exists within the Muslim holy book. No connection between spirit-possession and madness or mental illness was found. Pagans taunted and labelled people as jinn-possessed only to ostracize and scapegoat. Linking the labelling of people as jinn-possession to a pagan practice may be used to educate Muslims, so they can reassess their community's stigma towards the mentally ill.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Science.gov (United States)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

Are symptoms of spirit possessed patients covered by the DSM-IV or DSM-5 criteria for possession trance disorder? A mixed-method explorative study in Uganda.

Science.gov (United States)

van Duijl, Marjolein; Kleijn, Wim; de Jong, Joop

2013-09-01

As in many cultures, spirit possession is a common idiom of distress in Uganda. The DSM-IV contains experimental research criteria for dissociative and possession trance disorder (DTD and PTD), which are under review for the DSM-5. In the current proposed categories of the DSM-5, PTD is subsumed under dissociative identity disorder (DID) and DTD under dissociative disorders not elsewhere classified. Evaluation of these criteria is currently urgently required. This study explores the match between local symptoms of spirit possession in Uganda and experimental research criteria for PTD in the DSM-IV and proposed criteria for DID in the DSM-5. A mixed-method approach was used combining qualitative and quantitative research methods. Local symptoms were explored of 119 spirit possessed patients, using illness narratives and a cultural dissociative symptoms' checklist. Possible meaningful clusters of symptoms were inventoried through multiple correspondence analysis. Finally, local symptoms were compared with experimental criteria for PTD in the DSM-IV and proposed criteria for DID in the DSM-5. Illness narratives revealed different phases of spirit possession, with passive-influence experiences preceding the actual possession states. Multiple correspondence analysis of symptoms revealed two dimensions: 'passive' and 'active' symptoms. Local symptoms, such as changes in consciousness, shaking movements, and talking in a voice attributed to spirits, match with DSM-IV-PTD and DSM-5-DID criteria. Passive-influence experiences, such as feeling influenced or held by powers from outside, strange dreams, and hearing voices, deserve to be more explicitly described in the proposed criteria for DID in the DSM-5. The suggested incorporation of PTD in DID in the DSM-5 and the envisioned separation of DTD and PTD in two distinctive categories have disputable aspects.

The Regulation of the Possession of Weapons at Gatherings | du Toit

African Journals Online (AJOL)

The Act also amends the Regulation of Gatherings Act 205 of 1993 to prohibit the possession of any dangerous weapon at a gathering or demonstration. ... (b) possession of dangerous weapons during the participation in any religious or cultural activities or lawful sport, recreation or entertainment or (c) legitimate collection, ...

The Secret Prover : Proving Possession of Arbitrary Files While not Giving Them Away

NARCIS (Netherlands)

Teepe, Wouter

2005-01-01

The Secret Prover is a Java application which allows a user (A) to prove to another user (B), that A possesses a file. If B also possesses this file B will get convinced, and if B does not possess this file B will gain no information on (the contents of) this file. This is the first implementation

Feature interpretability and the positions of 2nd person possessives in Brazilian Portuguese

Directory of Open Access Journals (Sweden)

Bruna Karla Pereira

2016-12-01

Full Text Available Interpretability and valuation of φ-features (Chomsky, 2001; Pesetsky and Torrego, 2007 have played a central role in the investigation of language universals. With regard to that, in standard Brazilian Portuguese (BP, as well as in other Romance languages, possessives have uninterpretable number features, which are valued via nominal agreement. However, dialects of BP, especially the one spoken in Minas Gerais, have shown that 2nd person possessives, in postnominal position, do not have number agreement with the noun. In order to account for these facts, I will argue that, in this grammar, number features on 2nd person possessives are reanalyzed as being: (i associated with the person (rather than the noun and (ii interpretable. From the first postulation, ‘seu’ is expected to be the possessive for 2nd person singular, and ‘seus’ for 2nd person plural. From the second postulation, no number concord is expected to be triggered on the possessive. In addition, based on Danon (2011 and Norris (2014, I will argue that cardinals divide BP DPs into two domains in that phrases located above NumP are marked with the plural morpheme, while phrases below it are unmarked. In this sense, because prenominal possessives precede cardinals (NumP, they must be marked with the plural morpheme for nominal agreement; whereas postnominal possessives, which follow NumP, must be unmarked. Free from the plural marking associated with nominal agreement, postnominal 2nd person possessives favor the reanalysis of the morpheme ‘-s’ as indicating the number associated with person features.

Criminalization of 'Possession of Unexplained Property' and the ...

African Journals Online (AJOL)

Worku_Y

government operating costs, increases government spending for wages and ... revenues by plundering revenue generating agencies such as tax collection, ..... a) the assets under the ownership or possession of himself and his family; and.

Constitutional Law: Right of Privacy--Possession of Marijuana

Science.gov (United States)

Rohrer, David E.

1976-01-01

The Alaska Supreme Court in Ravin v. State accepted the defendant's contention that the prohibition of possession of marihuana infringed on his constitutional right to privacy. The significance of the case is discussed. (LBH)

Investigating the Impact of Possession-Way of a Smartphone on Action Recognition

Directory of Open Access Journals (Sweden)

Zae Myung Kim

2016-06-01

Full Text Available For the past few decades, action recognition has been attracting many researchers due to its wide use in a variety of applications. Especially with the increasing number of smartphone users, many studies have been conducted using sensors within a smartphone. However, a lot of these studies assume that the users carry the device in specific ways such as by hand, in a pocket, in a bag, etc. This paper investigates the impact of providing an action recognition system with the information of the possession-way of a smartphone, and vice versa. The experimental dataset consists of five possession-ways (hand, backpack, upper-pocket, lower-pocket, and shoulder-bag and two actions (walking and running gathered by seven users separately. Various machine learning models including recurrent neural network architectures are employed to explore the relationship between the action recognition and the possession-way recognition. The experimental results show that the assumption of possession-ways of smartphones do affect the performance of action recognition, and vice versa. The results also reveal that a good performance is achieved when both actions and possession-ways are recognized simultaneously.

Resistive Random Access Memory from Materials Development fnd Engineering to Novel Encryption and Neuromorphic Applications

Science.gov (United States)

Beckmann, Karsten

Resistive random access memory (ReRAM or RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance state of ReRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse properties. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. I have developed two processes based on 100 and 300mm wafer platforms to demonstrate functional HfO2 based ReRAM devices. The first process is designed for a rapid materials engineering and device characterization, while the second is an advanced hybrid ReRAM/CMOS combination based on the IBM 65nm 10LPe process technology. The 100mm wafer efforts were used to show impacts of etch processes on ReRAM switching performance and the need for a rigorous structural evaluation of ReRAM devices before starting materials development. After an etch development, a bottom electrode comparison between the inert materials Pt, Ru and W was performed where Ru showed superior results with respect to yield and resilience against environmental impacts such as humidity over a 2-month period. A comparison of amorphous and crystalline devices showed no statistical difference in the performance with respect to random telegraph noise. This demonstrates, that the forming process fundamentally alters the crystallographic structure within and around the filament. The 300mm wafer development efforts were aimed towards implementing ReRAM in the FEOL, combined with CMOS, to yield a seamless process flow of 1 transistor 1 ReRAM structures (1T1R). This technology was customized with custom-developed tungsten metal 1 (M1) and dual tungsten/copper via 1 (V1) structures, within which the ReRAM stack is embedded. The ReRAM itself consists of an inert W bottom electrode, HfO2 based active switching layer, a Ti oxygen scavenger

O olhar dos psiquiatras brasileiros sobre os fenômenos de transe e possessão Brazilian psychiatrists’ approaches on trance and possession phenomena

Directory of Open Access Journals (Sweden)

Angélica A. Silva de Almeida

2007-01-01

Full Text Available CONTEXTO: Os fenômenos de transe e possessão despertaram o interesse da comunidade psiquiátrica brasileira, gerando posturas diversificadas. OBJETIVOS: Descrever e analisar como os fenômenos de transe e possessão foram tratados pelos psiquiatras brasileiros: seu impacto na teoria, na pesquisa e na prática clínica entre 1900 e 1950. MÉTODO: Análise de artigos científicos e leigos, teses e livros sobre transes e possessões produzidos pelos psiquiatras brasileiros entre 1900 e 1950. RESULTADOS: Identificam-se duas correntes de pensamento entre os psiquiatras. A primeira, vinculada às Faculdades de Medicina do Rio de Janeiro e São Paulo, sob forte influência de autores franceses, deteve-se mais na periculosidade do espiritismo para a saúde mental. Defendia a adoção de medidas repressivas com o poder público. O segundo grupo de psiquiatras, ligado às Faculdades de Medicina da Bahia e Pernambuco, embora não desconsiderasse o caráter patológico ou "primitivo" dos fenômenos de transe e possessão, apresentou uma visão mais antropológica e culturalista. Considerando tais fenômenos como manifestações étnicas ou culturais, alguns defenderam o controle médico e a educação do povo para o abandono dessas práticas "primitivas". Outros não consideravam os fenômenos mediúnicos como desencadeadores da loucura, mas manifestações não-patológicas de um universo cultural, além de não vinculá-los ao atraso cultural da população. CONCLUSÕES: As religiões mediúnicas foram objeto de estudo por longo período, resultando hipóteses e práticas diferenciadas por parte da comunidade psiquiátrica brasileira, constituindo-se oportunidade privilegiada para o estudo do impacto dos fatores socioculturais na atividade psiquiátrica.BACKGROUND: Trance and possession experiences have raised interest among Brazilian psychiatrists resulting in a variety of approaches. OBJECTIVES: To describe and analyze how Brazilian psychiatrists

CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

International Nuclear Information System (INIS)

Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

1996-01-01

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Directory of Open Access Journals (Sweden)

Jen-Chih Kuo

2003-12-01

Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

Is a 4-bit synaptic weight resolution enough? - Constraints on enabling spike-timing dependent plasticity in neuromorphic hardware

Directory of Open Access Journals (Sweden)

Thomas ePfeil

2012-07-01

Full Text Available Large-scale neuromorphic hardware systems typically bear the trade-off be-tween detail level and required chip resources. Especially when implementingspike-timing-dependent plasticity, reduction in resources leads to limitations ascompared to floating point precision. By design, a natural modification that savesresources would be reducing synaptic weight resolution. In this study, we give anestimate for the impact of synaptic weight discretization on different levels, rangingfrom random walks of individual weights to computer simulations of spiking neuralnetworks. The FACETS wafer-scale hardware system offers a 4-bit resolution ofsynaptic weights, which is shown to be sufficient within the scope of our networkbenchmark. Our findings indicate that increasing the resolution may not even beuseful in light of further restrictions of customized mixed-signal synapses. In ad-dition, variations due to production imperfections are investigated and shown tobe uncritical in the context of the presented study. Our results represent a generalframework for setting up and configuring hardware-constrained synapses. We sug-gest how weight discretization could be considered for other backends dedicatedto large-scale simulations. Thus, our proposition of a good hardware verificationpractice may rise synergy effects between hardware developers and neuroscientists.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Directory of Open Access Journals (Sweden)

Yuan-Jyun Chang

2016-12-01

Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Stability properties of solutions to nonlinear models possessing a sign-undefined metric

International Nuclear Information System (INIS)

Barashenkov, I.V.

1983-01-01

Multicomponent field systems possessing a sign-undefined internal space metric, in particular models with a noncompact global invariance group are investigated. It is shown that the energy cannot have even a conditional relative minimum. It is demonstrated, nevertheless, that the corresponding nonlinear equations of motion are permitted to possess stable particle-like solutions

Themes in Spirit Possession in Ugandan Christianity | James ...

African Journals Online (AJOL)

. This paper discerns a number of common themes that run through many of these experiences. In particular, sex as a motif for deviance and evil is noted as a common feature of many of the possession stories and all contact with spirits is seen ...

20 CFR 404.1093 - Possession of the United States.

Science.gov (United States)

2010-04-01

... DISABILITY INSURANCE (1950- ) Employment, Wages, Self-Employment, and Self-Employment Income Self-Employment... figuring your net earnings from self-employment, the term possession of the United States shall be deemed...

Stability properties of solutions to nonlinear models possessing a sign-undefined metric

International Nuclear Information System (INIS)

Barashenkov, I.V.

1983-01-01

Multicomponent field systems possessing a sign-undefined internal space metric, in particular models with a noncompact global invariance group, are investigated. It is shown that the energy cannot have even a conditional relative minimum. It is demonstrated, nevertheless, that the corresponding nonlinear equations of motion are permitted to possess stable particle-like solutions. (Auth.)

Descending with Angels: Jinn Possession, Islamic Exorcism, and Psychiatry

DEFF Research Database (Denmark)

Suhr, Christian

What is it like to be a Muslim possessed by a jinn spirit? How do you find refuge from madness and evil in a place like Denmark? In this book I explore some of the ways in which Muslims in the West have sought to protect themselves. Over several years I followed Muslim patients being treated.......” In the book I analyze how these broader social and political issues are paralleled in the invisible dynamics of jinn possession and psychosis, proposing new theoretical perspectives on religious and psychiatric healing as ritual practices for dealing with the invisible in human life....... hypervisible in public discourse through intensive state monitoring, surveillance, and media coverage. Yet their religion of Islam remains poorly understood and is frequently identified by politicians, commentators, and even healthcare specialists as the underlying invisible cause of “integration problems...

Gun Possession among Massachusetts Batterer Intervention Program Enrollees

Science.gov (United States)

Rothman, Emily F.; Johnson, Renee M.; Hemenway, David

2006-01-01

Batterers with access to firearms present a serious lethal threat to their partners. The purpose of this exploratory study is to estimate the prevalence of and risk markers for gun possession among Massachusetts men enrolled in batterer intervention programs. The authors found that 1.8% of the men reported having a gun in or around their home.…

Neuromorphic circuits impart a sense of touch

Science.gov (United States)

Bartolozzi, Chiara

2018-06-01

The sense of touch is the ability to perceive consistency, texture, and shape of objects that we manipulate, and the forces we exchange with them. Touch is a source of information that we effortlessly decode to smoothly and naturally grasp and manipulate objects, maintain our posture while walking, or avoid stumbling into obstacles, allowing us to plan, adapt, and correct actions in an ever-changing external world. As such, artificial devices, such as robots or prostheses, that aim to accomplish similar tasks must possess artificial tactile-sensing systems. On page 998 of this issue, Kim et al. (1) report on a “neuromorphic” tactile sensory system based on organic, flexible, electronic circuits that can measure the force applied on the sensing regions. The encoding of the signal is similar to that used by human nerves that are sensitive to tactile stimuli (mechanoreceptors), so the device outputs can substitute for them and communicate with other nerves (e.g., residual nerve fibers of amputees or motor neurons). The proposed system exploits organic electronics that allow for three-dimensional printing of flexible structures that conform to large curved surfaces, as required for placing sensors on robots (2) and prostheses.

Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

Science.gov (United States)

Pin, Francois G.; Watanabe, Yutaka

1993-01-01

Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

Licenses for possessing and applying radioactive sources, materials, etc

International Nuclear Information System (INIS)

Anon.

1977-01-01

Commercial and governmental institutions have been licensed by Dutch authorities to possess and apply radioactive sources, materials, etc. A summary is given and the list is subdivided into a number of sections such as radioactive sources, radioactive materials, X-ray equipment and technetium-generators

46 CFR 308.504 - Definition of territories and possessions.

Science.gov (United States)

2010-10-01

... 46 Shipping 8 2010-10-01 2010-10-01 false Definition of territories and possessions. 308.504 Section 308.504 Shipping MARITIME ADMINISTRATION, DEPARTMENT OF TRANSPORTATION EMERGENCY OPERATIONS WAR RISK INSURANCE War Risk Cargo Insurance I-Introduction § 308.504 Definition of territories and...

Reward-based learning under hardware constraints - Using a RISC processor embedded in a neuromorphic substrate

Directory of Open Access Journals (Sweden)

Simon eFriedmann

2013-09-01

Full Text Available In this study, we propose and analyze in simulations a new, highly flexible method of imple-menting synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. Thestudy focuses on globally modulated STDP, as a special use-case of this method. Flexibility isachieved by embedding a general-purpose processor dedicated to plasticity into the wafer. Toevaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spiketrain learning task. A single layer of neurons is trained to fire at specific points in time withonly the reward as feedback. This model is simulated to measure its performance, i.e. the in-crease in received reward after learning. Using this performance as baseline, we then simulatethe model with various constraints imposed by the proposed implementation and compare theperformance. The simulated constraints include discretized synaptic weights, a restricted inter-face between analog synapses and embedded processor, and mismatch of analog circuits. Wefind that probabilistic updates can increase the performance of low-resolution weights, a simpleinterface between analog synapses and processor is sufficient for learning, and performance isinsensitive to mismatch. Further, we consider communication latency between wafer and theconventional control computer system that is simulating the environment. This latency increasesthe delay, with which the reward is sent to the embedded processor. Because of the time continu-ous operation of the analog synapses, delay can cause a deviation of the updates as compared tothe not delayed situation. We find that for highly accelerated systems latency has to be kept to aminimum. This study demonstrates the suitability of the proposed implementation to emulatethe selected reward modulated STDP learning rule. It is therefore an ideal candidate for imple-mentation in an upgraded version of the wafer-scale system developed within the BrainScaleSproject.

Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

Science.gov (United States)

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

Optics in neural computation

Science.gov (United States)

Levene, Michael John

multiplexing works based on an unconventional, but very intuitive, analysis of the optical far-field. A more detailed analysis based on a path-integral interpretation of the Born approximation is also derived. The capacity of shift multiplexing is compared with that of angle and wavelength multiplexing. The last part of this thesis deals with the role of optics in neuromorphic engineering. Up until now, most neuromorphic engineering has involved one or a few VLSI circuits emulating early sensory systems. However, optical interconnects will be required in order to push towards more ambitious goals, such as the simulation of early visual cortex. I describe a preliminary approach to designing such a system, and show how shift multiplexing can be used to simultaneously store and implement the immense interconnections required by such a project.

Whose name is it anyway? Varying patterns of possessive usage in eponymous neurodegenerative diseases

Directory of Open Access Journals (Sweden)

Michael R. MacAskill

2013-04-01

Full Text Available There has been long-standing debate over whether use of the possessive form of the names of eponymous neurological disorders should be abandoned. Which view has actually predominated in practice? We empirically assessed current and historical usage in the scientific literature. The PubMed database was queried for the percentage of titles published each year from 1960–2012 which contained the possessive form of Parkinson’s (PD, Alzheimer’s (AD, Huntington’s (HD, Wilson’s (WD, and Gaucher’s (GD diseases (e.g. Huntington’s disease or chorea vs Huntington disease or chorea. Down syndrome (DS, well known for its changes in terminology, was used as a reference. The possessive form was nearly universal in all conditions from 1960 until the early 1970s. In both DS and GD it then declined at an approximately constant rate of 2 percentage points per year to drop below 15%. The possessive forms of both PD and AD began to decline at the same time but stabilised and have since remained above 80%, with a similar but more volatile pattern in HD. WD, meanwhile, is intermediate between the DS/GD and PD/AD/HD patterns, with a slower decline to its current value of approximately 60%. Declining possessive form usage in GD and DS papers has been remarkably uniform over time and has nearly reached completion. PD and AD appear stable in remaining predominantly possessive. The larger volume of papers published in those fields and their possibly greater public recognition and involvement may make that unlikely to change in the short-term. In a secondary analysis restricted to PD, we found that practices have switched dramatically several times in each of three US-published general neurology journals. Meanwhile, in two UK-published journals, and in the specialist title “Movement Disorders”, the possessive form has been maintained consistently. The use of eponyms in neurology shows systematic variation across time, disorders, and journals.

Gun possession among American youth: a discovery-based approach to understand gun violence.

Science.gov (United States)

Ruggles, Kelly V; Rajan, Sonali

2014-01-01

To apply discovery-based computational methods to nationally representative data from the Centers for Disease Control and Preventions' Youth Risk Behavior Surveillance System to better understand and visualize the behavioral factors associated with gun possession among adolescent youth. Our study uncovered the multidimensional nature of gun possession across nearly five million unique data points over a ten year period (2001-2011). Specifically, we automated odds ratio calculations for 55 risk behaviors to assemble a comprehensive table of associations for every behavior combination. Downstream analyses included the hierarchical clustering of risk behaviors based on their association "fingerprint" to 1) visualize and assess which behaviors frequently co-occur and 2) evaluate which risk behaviors are consistently found to be associated with gun possession. From these analyses, we identified more than 40 behavioral factors, including heroin use, using snuff on school property, having been injured in a fight, and having been a victim of sexual violence, that have and continue to be strongly associated with gun possession. Additionally, we identified six behavioral clusters based on association similarities: 1) physical activity and nutrition; 2) disordered eating, suicide and sexual violence; 3) weapon carrying and physical safety; 4) alcohol, marijuana and cigarette use; 5) drug use on school property and 6) overall drug use. Use of computational methodologies identified multiple risk behaviors, beyond more commonly discussed indicators of poor mental health, that are associated with gun possession among youth. Implications for prevention efforts and future interdisciplinary work applying computational methods to behavioral science data are described.

Gun possession among American youth: a discovery-based approach to understand gun violence.

Directory of Open Access Journals (Sweden)

Kelly V Ruggles

Full Text Available OBJECTIVE: To apply discovery-based computational methods to nationally representative data from the Centers for Disease Control and Preventions' Youth Risk Behavior Surveillance System to better understand and visualize the behavioral factors associated with gun possession among adolescent youth. RESULTS: Our study uncovered the multidimensional nature of gun possession across nearly five million unique data points over a ten year period (2001-2011. Specifically, we automated odds ratio calculations for 55 risk behaviors to assemble a comprehensive table of associations for every behavior combination. Downstream analyses included the hierarchical clustering of risk behaviors based on their association "fingerprint" to 1 visualize and assess which behaviors frequently co-occur and 2 evaluate which risk behaviors are consistently found to be associated with gun possession. From these analyses, we identified more than 40 behavioral factors, including heroin use, using snuff on school property, having been injured in a fight, and having been a victim of sexual violence, that have and continue to be strongly associated with gun possession. Additionally, we identified six behavioral clusters based on association similarities: 1 physical activity and nutrition; 2 disordered eating, suicide and sexual violence; 3 weapon carrying and physical safety; 4 alcohol, marijuana and cigarette use; 5 drug use on school property and 6 overall drug use. CONCLUSIONS: Use of computational methodologies identified multiple risk behaviors, beyond more commonly discussed indicators of poor mental health, that are associated with gun possession among youth. Implications for prevention efforts and future interdisciplinary work applying computational methods to behavioral science data are described.

The effect of playing tactics and situational variables on achieving score-box possessions in a professional soccer team.

Science.gov (United States)

Lago-Ballesteros, Joaquin; Lago-Peñas, Carlos; Rey, Ezequiel

2012-01-01

The aim of this study was to analyse the influence of playing tactics, opponent interaction and situational variables on achieving score-box possessions in professional soccer. The sample was constituted by 908 possessions obtained by a team from the Spanish soccer league in 12 matches played during the 2009-2010 season. Multidimensional qualitative data obtained from 12 ordered categorical variables were used. Sampled matches were registered by the AMISCO PRO system. Data were analysed using chi-square analysis and multiple logistic regression analysis. Of 908 possessions, 303 (33.4%) produced score-box possessions, 477 (52.5%) achieved progression and 128 (14.1%) failed to reach any sort of progression. Multiple logistic regression showed that, for the main variable "team possession type", direct attacks and counterattacks were three times more effective than elaborate attacks for producing a score-box possession (P tactics on producing score-box possessions.

10 CFR 70.20a - General license to possess special nuclear material for transport.

Science.gov (United States)

2010-01-01

... 10 Energy 2 2010-01-01 2010-01-01 false General license to possess special nuclear material for transport. 70.20a Section 70.20a Energy NUCLEAR REGULATORY COMMISSION (CONTINUED) DOMESTIC LICENSING OF... transport. (a) A general license is issued to any person to possess formula quantities of strategic special...

19 CFR 7.2 - Insular possessions of the United States other than Puerto Rico.

Science.gov (United States)

2010-04-01

... than Puerto Rico. 7.2 Section 7.2 Customs Duties U.S. CUSTOMS AND BORDER PROTECTION, DEPARTMENT OF... NAVAL STATION § 7.2 Insular possessions of the United States other than Puerto Rico. (a) Insular possessions of the United States other than Puerto Rico are also American territory but, because those insular...

50 CFR 600.1204 - Shark finning; possession at sea and landing of shark fins.

Science.gov (United States)

2010-10-01

... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Shark finning; possession at sea and landing of shark fins. 600.1204 Section 600.1204 Wildlife and Fisheries FISHERY CONSERVATION AND... PROVISIONS Shark Finning § 600.1204 Shark finning; possession at sea and landing of shark fins. (a)(1) No...

Schizophrenia-The spirit possessed 23 year old male from rural ...

African Journals Online (AJOL)

A case of a twenty-three year old rural Ghanaian male suffering from schizophrenia and presenting as “possessed by spirits” is reported. Treatment, and outcome by physical means with chlorpromazine; and implications for further research are discussed.

Relationship between length of A-bomb survivor's health handbook possession and mortality risk

International Nuclear Information System (INIS)

Otani, Keiko; Ohtaki, Megu; Satoh, Kenichi; Tonda, Tetsuji

2012-01-01

The title handbook was first issued to support the health of A-bomb survivors by Japan MHLW in 1957, and about 220 thousands possess it in 2010. Its major supports contain free medicare, 2 periodic and 2 optional medical examinations/year and other various benefits. This study was performed to elucidate the relationship in the title for evaluation of its life prolonging effect on Hiroshima survivors. The length of handbook possession was defined the period from acquiring it to death. The cohort was 17,335 (7,607 men) registered survivors who had had the handbook for 1 year or more, and before Nov. 1965 or later, until Dec. 2010. Causes of death event were classified to be the cerebrovascular, cardiac and cancerous disease, and others were censored. The objective variable was mortality risk, and predictors were the exposed dose, age at the exposure, chronological age and length of handbook possession. Risk of cerebrovascular or cardiac death was estimated by the model of exponential function, and of cancer death, of power function based on multi-stage theory of carcinogenesis. Results revealed that the cerebrovascular mortality of women and men was 8.1 and 7.2%, respectively; cardiac, 8.7 and 7.2%; and cancerous, 10.1 and 14.9%. Significant reduction of relative risk of cerebrovascular death, about 4% per 1 year handbook possession, was observed in men alone; negative correlations of period effect were seen in cerebrovascular and cardiac death of women; and positive correlation between cancer death and exposed dose was observed. The prophylaxis and continuous treatment of cerebrovascular disease due to the handbook possession were thought effective in men. (T.T.)

Demonic possessions and mental illness: discussion of selected cases in late medieval hagiographical literature.

Science.gov (United States)

Espí Forcén, Carlos; Espí Forcén, Fernando

2014-01-01

During the Middle Ages, demonic possession constituted an explanation for an erratic behavior in society. Exorcism was the treatment generally applied to demoniacs and seems to have caused some alleviation in the suffering of mentally distressed people. We have selected and analyzed some cases of demonic possession from thirteenth-century hagiographical literature. In the description of demoniacs we have been able to find traits of psychotic, mood, neurotic, personality disorders and epilepsy. The exorcisms analyzed in our article are the result of literary invention more than the description of a contemporary event. Nevertheless, the writers were witnesses of their time, transferred their knowledge about exorcism and possession in their narrative and presumably incorporated their actual experience with demoniacs.

Spiking Neural Classifier with Lumped Dendritic Nonlinearity and Binary Synapses: A Current Mode VLSI Implementation and Analysis.

Science.gov (United States)

Bhaduri, Aritra; Banerjee, Amitava; Roy, Subhrajit; Kar, Sougata; Basu, Arindam

2018-03-01

We present a neuromorphic current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown previously in software simulations that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with fewer synaptic resources than conventional algorithms. We show that even in real analog systems with manufacturing imperfections (CV of 23.5% and 14.4% for dendritic branch gains and leaks respectively), this network is able to produce comparable results with fewer synaptic resources. The chip fabricated in [Formula: see text]m complementary metal oxide semiconductor has eight dendrites per cell and uses two opposing cells per class to cancel common-mode inputs. The chip can operate down to a [Formula: see text] V and dissipates 19 nW of static power per neuronal cell and [Formula: see text] 125 pJ/spike. For two-class classification problems of high-dimensional rate encoded binary patterns, the hardware achieves comparable performance as software implementation of the same with only about a 0.5% reduction in accuracy. On two UCI data sets, the IC integrated circuit has classification accuracy comparable to standard machine learners like support vector machines and extreme learning machines while using two to five times binary synapses. We also show that the system can operate on mean rate encoded spike patterns, as well as short bursts of spikes. To the best of our knowledge, this is the first attempt in hardware to perform classification exploiting dendritic properties and binary synapses.

Computational Cognition and Robust Decision Making

Science.gov (United States)

2013-03-06

much more powerful neuromorphic chips than current state of the art. L. Chua 10 DISTRIBUTION STATEMENT A – Unclassified, Unlimited Distribution 2...Cognition Program DARPA (Gill Pratt) • Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) Program IARPA (Brad Minnery...2012 - Four projects at SNU and KAIST co-funded with AOARD DARPA SyNAPSE Program: - Design, fabrication, and demonstration of neuromorphic

New families of conservative systems on $S^2$ possessing an integral of fourth degree in momenta

OpenAIRE

Selivanova, Elena N.

1997-01-01

There is a well-known example of integrable conservative system on $S^2$, the case of Kovalevskaya in the dynamics of a rigid body, possessing an integral of fourth degree in momenta. Goryachev proposed a one-parameter family of examples of conservative systems on $S^2$ possessing an integral of fourth degree in momenta which includes the case of Kovalevskaya. In this paper we proposed new examples of conservative systems on $S^2$ possessing an integral of fourth degree in momenta.

Prepositions in Use: Prepositions of Standard, Prepositions of Possession and Prepositions of Accompaniment

Directory of Open Access Journals (Sweden)

Naji Masned AlQbailat

2016-08-01

Full Text Available The current research paper attempted at investigating the use of prepositions of standard, prepositions of possession and prepositions of accompaniment by some Jordanian learners of English. A total of 53 Jordanian English Majors participated in the study from the department of English language at Princess Alia University College. In collecting the needed data for the purpose of the study, the researchers employed fifteen items of a multiple choice test. The results of the study showed that Jordanian learners of English encountered moderate difficulty in learning the three aforesaid usages of prepositions. This difficulty is ascribed mainly to first language interference more than intralingual interference. It was also found that prepositions of standard are the most difficult to learn by the participants, followed by prepositions of accompaniment and prepositions of possession respectively.       Keywords: First language Interference, Intralingual Interference, Prepositions of Standard, Prepositions of Accompaniment, Prepositions of Possession

Association between socio-economic status and childhood undernutrition in Bangladesh; a comparison of possession score and poverty index.

Science.gov (United States)

Mohsena, Masuda; Mascie-Taylor, C G Nicholas; Goto, Rie

2010-10-01

To determine how much of the variation in nutritional status of Bangladeshi children under 5 years old can be attributed to the socio-economic status of the family. Nutritional status used reference Z-scores of weight-for-age (WAZ), height-for-age (HAZ) and weight-for-height (WHZ). A 'possession score' was generated based on ownership of a radio, television, bicycle, motorcycle and telephone, and the availability of electricity, with categories of 0 to 4+ possessions. A five-point (quintile) 'poverty index' was created using principal component analysis. The Bangladesh Demographic and Health Survey 2004 was the source of data. A sample of 4891 children aged <5 years was obtained. Some 57.8 % of the sample was either stunted, wasted or underweight (7.7 % were stunted, wasted and underweight). Of those stunted (48.4 %), 25.7 % were also underweight. Underweight and wasting prevalences were 40.7 % and 14.3 %, respectively. Mean WAZ, HAZ and WHZ did not differ by sex. Children of mothers with no education or no possessions were, on average, about 1 sd more underweight and stunted than those with higher educated mothers or with 4+ possessions. The possession score provided much greater discrimination of undernutrition than the poverty index. Nearly 50 % of children from households with no possessions were stunted, wasted or underweight (only 27 % in the poorest quintile), compared with only 3-6 % of children from households with 4+ possessions (over 13 % in the richest quintile). Maternal education and possession score were the main predictors of a child's nutritional status. Possession score was a much better indicator of undernutrition than the poverty index.

27 CFR 479.105 - Transfer and possession of machine guns.

Science.gov (United States)

2010-04-01

... a department, agency, or political subdivision thereof; or any lawful transfer or lawful possession... distribution to any department or agency of the United States or any State or political subdivision thereof, or... entities expressing a need for a particular model or interest in seeing a demonstration of a particular...

Rulings in Argentinean and Colombian courts decriminalize possession of small amounts of narcotics.

Science.gov (United States)

Cozac, David

2009-12-01

Two recent court decisions in South America have reflected a growing backlash in the region against the so-called, U.S.-led "war on drugs". In Argentina, the Supreme Court of Justice ruled unanimously on 25 August 2009 that the second paragraph of Article 14 of the country's drug control legislation, which punishes the possession of drugs for personal consumption, was unconstitutional. In Colombia, the Supreme Court of Justice ruled on 8 July 2009 that the possession of illegal drugs for personal use was not a criminal offence.

50 CFR 648.322 - Skate allocation, possession, and landing provisions.

Science.gov (United States)

2010-10-01

... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Skate allocation, possession, and landing provisions. 648.322 Section 648.322 Wildlife and Fisheries FISHERY CONSERVATION AND MANAGEMENT, NATIONAL OCEANIC AND ATMOSPHERIC ADMINISTRATION, DEPARTMENT OF COMMERCE FISHERIES OF THE NORTHEASTERN UNITED STATES Management Measures for the NE Skate...

Adducin family proteins possess different nuclear export potentials.

Science.gov (United States)

Liu, Chia-Mei; Hsu, Wen-Hsin; Lin, Wan-Yi; Chen, Hong-Chen

2017-05-10

The adducin (ADD) family proteins, namely ADD1, ADD2, and ADD3, are actin-binding proteins that play important roles in the stabilization of membrane cytoskeleton and cell-cell junctions. All the ADD proteins contain a highly conserved bipartite nuclear localization signal (NLS) at the carboxyl termini, but only ADD1 can localize to the nucleus. The reason for this discrepancy is not clear. To avoid the potential effect of cell-cell junctions on the distribution of ADD proteins, HA epitope-tagged ADD proteins and mutants were transiently expressed in NIH3T3 fibroblasts and their distribution in the cytoplasm and nucleus was examined by immunofluorescence staining. Several nuclear proteins were identified to interact with ADD1 by mass spectrometry, which were further verified by co-immunoprecipitation. In this study, we found that ADD1 was detectable both in the cytoplasm and nucleus, whereas ADD2 and ADD3 were detected only in the cytoplasm. However, ADD2 and ADD3 were partially (~40%) sequestered in the nucleus by leptomycin B, a CRM1/exportin1 inhibitor. Upon the removal of leptomycin B, ADD2 and ADD3 re-distributed to the cytoplasm. These results indicate that ADD2 and ADD3 possess functional NLS and are quickly transported to the cytoplasm upon entering the nucleus. Indeed, we found that ADD2 and ADD3 possess much higher potential to counteract the activity of the NLS derived from Simian virus 40 large T-antigen than ADD1. All the ADD proteins appear to contain multiple nuclear export signals mainly in their head and neck domains. However, except for the leucine-rich motif ( 377 FEALMRMLDWLGYRT 391 ) in the neck domain of ADD1, no other classic nuclear export signal was identified in the ADD proteins. In addition, the nuclear retention of ADD1 facilitates its interaction with RNA polymerase II and zinc-finger protein 331. Our results suggest that ADD2 and ADD3 possess functional NLS and shuttle between the cytoplasm and nucleus. The discrepancy in the

48 CFR 52.236-11 - Use and Possession Prior to Completion.

Science.gov (United States)

2010-10-01

... possession or use shall not be deemed an acceptance of any work under the contract. (b) While the Government... adjustment shall be made in the contract price or the time of completion, and the contract shall be modified...

Global mental health and trauma exposure: the current evidence for the relationship between traumatic experiences and spirit possession.

Science.gov (United States)

Hecker, Tobias; Braitmayer, Lars; van Duijl, Marjolein

2015-01-01

We present a literature review on trauma exposure and spirit possession in low- and middle-income countries (LMICs). Despite the World Health Organization's objective of culturally appropriate mental health care in the Mental Health Action Plan 2013-2020, and the recommendations of the Inter-Agency Standing Committee to consider local idioms of distress and to collaborate with local resources, this topic still receives very little attention. Pathological spirit possession is commonly defined as involuntary, uncontrollable, and occurring outside of ritual settings. It is often associated with stigmatization, suffering, and dysfunctional behavior. While spirit possession has been discussed as an idiom of distress in anthropological literature, recent quantitative studies have presented support for a strong relationship between traumatic experiences and pathological possession states. The aim of this review was to investigate this relationship systematically in LMICs, in view of the debate on how to address the mental health gap in LMICs. Twenty-one articles, published in peer-reviewed English-language journals between 1994 and 2013, were identified and analyzed with regard to prevalence of possessive trance disorders, patients' sociodemographic characteristics, and its relation to traumatic experiences. The review and analysis of 917 patients with symptoms of possessive trance disorders from 14 LMICs indicated that it is a phenomenon occurring worldwide and with global relevance. This literature review suggests a strong relationship between trauma exposure and spirit possession with high prevalence rates found especially in postwar areas in African countries. More attention for possessive trance disorders in mental health and psychosocial intervention programs in humanitarian emergency settings as well as in societies in transition in LMICs is needed and justified by the results of this systematic literature review.

31 CFR 601.5 - Penalty for unauthorized control or possession.

Science.gov (United States)

2010-07-01

... CURRENCY AND OTHER SECURITIES § 601.5 Penalty for unauthorized control or possession. The Secretary of the... heretofore adopted for the printing of paper currency or other obligations or securities of the United States, is and will be subject to the provisions of 18 U.S.C. 474A which provides, in part, that it is...

Global mental health and trauma exposure: the current evidence for the relationship between traumatic experiences and spirit possession

Science.gov (United States)

Hecker, Tobias; Braitmayer, Lars; van Duijl, Marjolein

2015-01-01

Background We present a literature review on trauma exposure and spirit possession in low- and middle-income countries (LMICs). Despite the World Health Organization's objective of culturally appropriate mental health care in the Mental Health Action Plan 2013–2020, and the recommendations of the Inter-Agency Standing Committee to consider local idioms of distress and to collaborate with local resources, this topic still receives very little attention. Pathological spirit possession is commonly defined as involuntary, uncontrollable, and occurring outside of ritual settings. It is often associated with stigmatization, suffering, and dysfunctional behavior. While spirit possession has been discussed as an idiom of distress in anthropological literature, recent quantitative studies have presented support for a strong relationship between traumatic experiences and pathological possession states. Objective The aim of this review was to investigate this relationship systematically in LMICs, in view of the debate on how to address the mental health gap in LMICs. Methods Twenty-one articles, published in peer-reviewed English-language journals between 1994 and 2013, were identified and analyzed with regard to prevalence of possessive trance disorders, patients’ sociodemographic characteristics, and its relation to traumatic experiences. Results The review and analysis of 917 patients with symptoms of possessive trance disorders from 14 LMICs indicated that it is a phenomenon occurring worldwide and with global relevance. This literature review suggests a strong relationship between trauma exposure and spirit possession with high prevalence rates found especially in postwar areas in African countries. Conclusions More attention for possessive trance disorders in mental health and psychosocial intervention programs in humanitarian emergency settings as well as in societies in transition in LMICs is needed and justified by the results of this systematic literature review

Global mental health and trauma exposure: the current evidence for the relationship between traumatic experiences and spirit possession

Directory of Open Access Journals (Sweden)

Tobias Hecker

2015-11-01

Full Text Available Background: We present a literature review on trauma exposure and spirit possession in low- and middle-income countries (LMICs. Despite the World Health Organization's objective of culturally appropriate mental health care in the Mental Health Action Plan 2013–2020, and the recommendations of the Inter-Agency Standing Committee to consider local idioms of distress and to collaborate with local resources, this topic still receives very little attention. Pathological spirit possession is commonly defined as involuntary, uncontrollable, and occurring outside of ritual settings. It is often associated with stigmatization, suffering, and dysfunctional behavior. While spirit possession has been discussed as an idiom of distress in anthropological literature, recent quantitative studies have presented support for a strong relationship between traumatic experiences and pathological possession states. Objective: The aim of this review was to investigate this relationship systematically in LMICs, in view of the debate on how to address the mental health gap in LMICs. Methods: Twenty-one articles, published in peer-reviewed English-language journals between 1994 and 2013, were identified and analyzed with regard to prevalence of possessive trance disorders, patients’ sociodemographic characteristics, and its relation to traumatic experiences. Results: The review and analysis of 917 patients with symptoms of possessive trance disorders from 14 LMICs indicated that it is a phenomenon occurring worldwide and with global relevance. This literature review suggests a strong relationship between trauma exposure and spirit possession with high prevalence rates found especially in postwar areas in African countries. Conclusions: More attention for possessive trance disorders in mental health and psychosocial intervention programs in humanitarian emergency settings as well as in societies in transition in LMICs is needed and justified by the results of this

Male homosexuality and spirit possession in Brazil.

Science.gov (United States)

Fry, P

1985-01-01

This paper examines the relationship between male homosexuality and the Afro-Brazilian possession cults in Belém do Parà. After a discussion of the literature follows a description of the cults' beliefs, rites and social organization. Male sex roles are then discussed and the two categories, bicha and man, analyzed. It is noted that there is no term which is equivalent to the western category of "homosexual" in this taxonomic system. After putting forward folk explanations for the presence of many bichas in the cults, an analysis is put forward of the social rewards available to bichas within these cults, and the structural relationship between homosexuality and these regions in terms of their congruent marginality vis-à-vis "normal society."

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.

Science.gov (United States)

Yousefzadeh, Amirreza; Jablonski, Miroslaw; Iakymchuk, Taras; Linares-Barranco, Alejandro; Rosado, Alfredo; Plana, Luis A; Temple, Steve; Serrano-Gotarredona, Teresa; Furber, Steve B; Linares-Barranco, Bernabe

2017-10-01

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

Dissociative trance disorder: clinical and Rorschach findings in ten persons reporting demon possession and treated by exorcism.

Science.gov (United States)

Ferracuti, S; Sacco, R; Lazzari, R

1996-06-01

Although dissociative trance disorders, especially possession disorder, are probably more common than is usually though, precise clinical data are lacking. Ten persons undergoing exorcisms for devil trance possession state were studied with the Dissociative Disorders Diagnostic Schedule and the Rorschach test. These persons had many traits in common with dissociative identity disorder patients. They were overwhelmed by paranormal experiences. Despite claiming possession by a demon, most of them managed to maintain normal social functioning. Rorschach findings showed that these persons had a complex personality organization: Some of them displayed a tendency to oversimplify stimulus perception whereas others seemed more committed to psychological complexity. Most had severe impairment of reality testing, and 6 of the participants had an extratensive coping stile. In this group of persons reporting demon possession, dissociative trance disorder seems to be a distinct clinical manifestation of a dissociative continuum, sharing some features with dissociative identity disorder.

Se soigner ou soigner les autres  ? Dimensions thérapeutiques d’un culte de possession vietnamien Healing Myself, Healing Others : Therapeutic Skills of a Vietnamese Possession Cult

Directory of Open Access Journals (Sweden)

Claire Chauvet

2012-10-01

Full Text Available Les médiums des esprits des Quatre Palais, en articulation avec d’autres spécialistes religieux, participent à l’espace thérapeutique vietnamien. Ils contribuent de longue date, et ce malgré les aléas de l’histoire, à prendre en charge les maladies par le biais de la pratique rituelle et, plus généralement, par le biais des interventions des esprits. Si ces dimensions thérapeutiques ne constituent qu’un aspect du culte, à côté des enjeux religieux, politiques et territoriaux, les requêtes de guérison sont parmi les principales requêtes formulées aux esprits. Cet article examine les dimensions thérapeutiques de la pratique du culte qui s’articulent autour de deux pôles : pratiquer la possession pour soigner les autres ou pour se soigner soi-même. C’est, en effet, la santé, avec l’harmonie au sein de la vie familiale, la réussite dans le commerce ou les études, que les disciples viennent chercher auprès des esprits et de leurs intermédiaires. Par ailleurs, comme pour de nombreux cultes de possession, la maladie est très souvent à l’origine du processus qui mène à la pratique médiumnique. Certains médiums, ainsi que quelques esprits, ont à cet effet des pouvoirs spécialisés dans la guérison. Enfin, l’article envisage certaines transformations du rôle social des médiums.Spirits mediums of the Four Palaces have been taking part for a long time, along with other religious specialists, in the Vietnamese therapeutic area. They have helped, and still do despite historical upheavals, taking care of different kind of illnesses through rituals and, more generally, through spirits’ interventions. If healing is only one side of the worship, beside religious, political and territorial issues, it is one of the main issues addressed to the spirits. This paper investigates healing dimensions of the worship which are of two kinds : performing spirit possession in order to cure others or in order to cure

Review: Lisa Mackenrodt, Swahili Spirit Possession and Islamic Healing in Contemporary Tanzania: The Jinn Fly on Friday (2011 Buchbesprechung: Lisa Mackenrodt, Swahili Spirit Possession and Islamic Healing in Contemporary Tanzania: The Jinn Fly on Friday (2011

Directory of Open Access Journals (Sweden)

Jigal Beez

2013-01-01

Full Text Available Review of the monograph:Lisa Mackenrodt, Swahili Spirit Possession and Islamic Healing in Contemporary Tanzania: The Jinn Fly on Friday, Hamburg: Verlag Dr. Kovač, 2011, ISBN 978-3-8300-5806-9, 216 pagesBesprechung der Monographie:Lisa Mackenrodt, Swahili Spirit Possession and Islamic Healing in Contemporary Tanzania: The Jinn Fly on Friday, Hamburg: Verlag Dr. Kovač, 2011, ISBN 978-3-8300-5806-9, 216 Seiten

32 CFR 552.122 - Personnel not authorized to possess or retain personal weapons.

Science.gov (United States)

2010-07-01

... THE ARMY MILITARY RESERVATIONS AND NATIONAL CEMETERIES REGULATIONS AFFECTING MILITARY RESERVATIONS... person who has been convicted in any court of the possession, use, or sale of marijuana, dangerous or...

Does possession of assets increase women's participation in reproductive decision-making? Perceptions of Nigerian women.

Science.gov (United States)

Omeje, Joachim C; Oshi, Sarah N; Oshi, Daniel C

2011-01-01

This study is based on a population-based, descriptive questionnaire survey, the objective of which was to elicit the perceptions of women in south-eastern Nigeria on whether possession of economic/household assets by women enhanced their capacity to negotiate reproductive issues with their husbands. The findings show that the respondents believed that possession of economic/household assets by women in their communities might not necessarily increase their negotiation power in their reproductive decision-making. Other factors tend to attenuate the effects of women's possession of economic/household assets on their reproductive bargaining power. Notable among these may be social norms that implicitly arrogate control of the assets owned by the conjugal couple to the man, even when they are bought by the women. Planners of reproductive health intervention projects, policy-makers and researchers need to be aware of such sociocultural specific phenomena, which do not fit with widely held international beliefs.

Hierarchical remote data possession checking method based on massive cloud files

Directory of Open Access Journals (Sweden)

Ma Haifeng

2017-06-01

Full Text Available Cloud storage service enables users to migrate their data and applications to the cloud, which saves the local data maintenance and brings great convenience to the users. But in cloud storage, the storage servers may not be fully trustworthy. How to verify the integrity of cloud data with lower overhead for users has become an increasingly concerned problem. Many remote data integrity protection methods have been proposed, but these methods authenticated cloud files one by one when verifying multiple files. Therefore, the computation and communication overhead are still high. Aiming at this problem, a hierarchical remote data possession checking (hierarchical-remote data possession checking (H-RDPC method is proposed, which can provide efficient and secure remote data integrity protection and can support dynamic data operations. This paper gives the algorithm descriptions, security, and false negative rate analysis of H-RDPC. The security analysis and experimental performance evaluation results show that the proposed H-RDPC is efficient and reliable in verifying massive cloud files, and it has 32–81% improvement in performance compared with RDPC.

27 CFR 478.40 - Manufacture, transfer, and possession of semiautomatic assault weapons.

Science.gov (United States)

2010-04-01

... 27 Alcohol, Tobacco Products and Firearms 3 2010-04-01 2010-04-01 false Manufacture, transfer, and... COMMERCE IN FIREARMS AND AMMUNITION Administrative and Miscellaneous Provisions § 478.40 Manufacture, transfer, and possession of semiautomatic assault weapons. (a) Prohibition. No person shall manufacture...

Assessment of Accounting Competencies Possessed by Postgraduate University Business Education Students to Handle Entrepreneurship Business Challenges in Nigeria

Science.gov (United States)

Okoro, James

2014-01-01

University Business Education graduates, by the nature of their programme, ought to possess relevant accounting competencies for successful entrepreneurship but casual observation and empirical reports indicate that they are not doing well in this aspect. Therefore, this study assessed the accounting competencies possessed by university…

On the co-variation between form and function of adnominal possessive modifiers in Dutch and English

DEFF Research Database (Denmark)

Rijkhoff, Jan

2009-01-01

in the noun phrase (section 3); a tentative explanation is given in section 4. The more general point this paper wants to make is that functional modifier categories like CLASSIFYING MODIFIER or QUALIFYING MODIFIER can be characterized in grammatical terms and, furthermore, that important grammatical...... that the remarkable variation in the grammatical properties of this possessive construction directly correlates with the kind of modifier function it has in the noun phrase. It is first shown that lexical possessive modifiers with van ‘of’ (“adnominal possessives” for short) are used to express most of the modifier...... functions recognized in a semantic, five-layered model of the noun phrase (section 2). I will then argue that the values for certain grammatical parameters (here subsumed under the labels MODIFICATION, PREDICATION, REFERENCE) correlate with the kind of modifier function the adnominal possessive has...

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

Science.gov (United States)

Carvajal, Gonzalo; Figueroa, Miguel

2014-07-01

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

Assessment of Management Competencies Possessed by Postgraduate University Business Education Students to Handle Entrepreneurship Business Challenges in Nigeria

Science.gov (United States)

Okoro, James

2015-01-01

University Business Education graduates, by the nature of their programme, ought to possess relevant management competencies for successful entrepreneurship but casual observation and empirical reports indicate that they are not doing well in this aspect. Therefore, this study assessed the management competencies possessed by the university…

Can the DSM-5 differentiate between nonpathological possession and dissociative identity disorder? A case study from an Afro-Brazilian religion.

Science.gov (United States)

Delmonte, Romara; Lucchetti, Giancarlo; Moreira-Almeida, Alexander; Farias, Miguel

2016-01-01

The aim of this article is to examine whether the diagnostic criteria of the Diagnostic and Statistical Manual of Mental Disorders, Fifth Edition (DSM-5), are able to differentiate between nonpathological religious possession and dissociative identity disorder (DID). We use the case study of an individual who leads an Afro-Brazilian religious group (Umbanda), focusing on her personal development and possession experiences from early childhood to the present, spanning a period of more than 40 years, and examine these data following DSM-5 criteria for DID (300.14). Her experiences of possession can be broken into 2 distinct stages. In the 1st stage (childhood and early adulthood), she displayed intrusive thoughts and a lack of control over possession states, which were associated with a heightened state of anxiety, loneliness, amnesia, and family conflict (meeting all 5 criteria for DID). In the 2nd stage (late 20s up to the present), she regularly experienced possession states but felt in control of their onset and found them religiously meaningful. In this 2nd stage, she only fulfilled 3 criteria for DID. We question the accuracy of diagnosing this individual with DID in her earlier life and suggest that the DSM-5 criteria fail to address the ambiguity of affect surrounding possession experiences (positive at the individual level, negative at the interpersonal level) and lack a clearer acknowledgment of the prevalence of possession and other unusual experiences in general populations.

CHRISTIAN SYMBOLISM IN FYODOR DOSTOEVSKY'S NOVEL "THE POSSESSED" ("DEMONS"

Directory of Open Access Journals (Sweden)

Sergei Leonidovich Sharakov

2013-11-01

Full Text Available The article raises a question of Christian symbolism in Fyodor Dostoevsky’s novel The Possessed (Demons. The introductory part identifies the purpose of a symbol in Christian poetics through the parallel with ancient symbolism. The author makes a conclusion that the functional role of a symbol in the ancient world and Christian tradition is different. Therefore, the ancient symbol involves a number of interrelated categories, such as fate, intuition or conjecture, inspiration, and predictions. Christian symbolism is based on the idea of redemption and moral innocence. Methodologically, the article is based on a cultural and historical approach, as well as on the comparative academic tradition. The overview of Dostoyevsky’s pre-materials for The Possessed (Demons enables us to suggest the use of Christian symbolism in this novel. Hence, the objective of the study is to investigate a composition of images and symbols in this piece of writing, with a special focus on the image of a chronicler since the storyline of the novel is developed through his perception. We make a supposition that there are several levels of Gospel perception in the artistic vision or consciousness of the chronicler, that form the basis of the symbolical composition of the novel. The article sequentially examines the examples of Christian symbolism, including the connection of ideas, characters and storylines of the novel with the Gospel. Then it gives evidence and reasons for the thesis that the Gospel gives the characters of the novel the grounds for shaping their destiny.

Possessão e inversão da subalternidade: com a palavra, Pombagira das Rosas

Directory of Open Access Journals (Sweden)

Sônia Regina Corrêa Lages

2012-01-01

Full Text Available Este artigo é decorrente de uma pesquisa de campo que analisou a possessão na religião afro-brasileira da Umbanda no terreiro de Umbanda Caboclo Pena Branca, na cidade de Juiz de Fora, MG. No presente recorte é apresentada a narrativa da Pombagira das Rosas, com o propósito de observar a relação de alteridade que se estabelece entre a médium e a entidade. A partir de um quadro conceitual definido por Michael De Certeau, as narrativas são analisadas buscando compreender de que forma a possessão se articula com a realidade histórica das mulheres no Brasil e com a trajetória pessoal da mulher médium que incorpora o referido espírito, redefinindo seu cotidiano. A intenção é focalizar na voz subalterna da entidade as dinâmicas individuais e coletivas que, fazendo uso do imaginário nacional sobre a entidade, possibilitam compreender a possessão como significando solidariedade social.

The possession game? A comparative analysis of ball retention and team success in European and international football, 2007-2010.

Science.gov (United States)

Collet, Christian

2013-01-01

Possession is thought of as central to success in modern football, but questions remain about its impact on positive team outcomes (Bate, 1988; Hughes & Franks, 2005; Pollard & Reep, 1997; Stanhope, 2001). Recent studies (e.g. Bloomfield, Polman, & O'Donoghue, 2005; Carling, Williams, & Reilly, 2005; James, Mellallieu, & Holley, 2002; Jones, James, & Mellalieu, 2004; Lago, 2009; Lago & Martin, 2007; Lago-Peñas & Dellal, 2010; Lago-Peñas, Lago-Ballesteros, Dellal, & Gómez, 2010; Taylor, Mellalieu, & James, 2005; Tucker, Mellalieu, James, & Taylor, 2005) that have examined these questions have often been constrained by an exclusive focus on English or Spanish domestic play. Using data from five European leagues, UEFA and FIFA tournaments, the study found that while possession time and passing predicted aggregated team success in domestic league play, both variables were poor predictors at the individual match level once team quality and home advantage were accounted for. In league play, the effect of greater possession was consistently negative; in the Champions League, it had virtually no impact. In national team tournaments, possession failed to reach significance when offensive factors were accounted for. Much of the success behind the 'possession game' was thus a function of elite teams confined in geographic and competitive space. That ball hegemony was not consistently tied to success suggests that a nuanced approach to possession is needed to account for variant strategic environments (e.g. James et al., 2002) and compels match analysts to re-examine the metric's overall value.

Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

Directory of Open Access Journals (Sweden)

Andrew G. Dempster

2007-01-01

Full Text Available It has recently been shown that the n-dimensional reduced adder graph (RAG-n technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG-n technique can be applied to these algorithms. This RAG-n DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp-z algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

Directory of Open Access Journals (Sweden)

Dempster Andrew G

2007-01-01

Full Text Available It has recently been shown that the -dimensional reduced adder graph (RAG- technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG- technique can be applied to these algorithms. This RAG- DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp- algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

Science.gov (United States)

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

75 FR 58993 - Migratory Bird Hunting; Late Seasons and Bag and Possession Limits for Certain Migratory Game Birds

Science.gov (United States)

2010-09-24

... Part V Department of the Interior Fish and Wildlife Service 50 CFR Part 20 Migratory Bird Hunting; Late Seasons and Bag and Possession Limits for Certain Migratory Game Birds; Final Rule #0;#0;Federal...-1231-9BPP-L2] RIN 1018-AX06 Migratory Bird Hunting; Late Seasons and Bag and Possession Limits for...

Experiences of possession and paranormal phenomena among women in the general population: are they related to traumatic stress and dissociation?

Science.gov (United States)

Sar, Vedat; Alioğlu, Firdevs; Akyüz, Gamze

2014-01-01

This study sought to determine the prevalence of experiences of possession and paranormal phenomena (PNP) in the general population and their possible relations to each other and to traumatic stress and dissociation. The study was conducted on a representative female sample recruited from a town in central eastern Turkey. The Dissociative Disorders Interview Schedule, the posttraumatic stress disorder (PTSD) and borderline personality disorder sections of the Structured Clinical Interviews for DSM-IV Axis-I and Personality Disorders, and the Childhood Abuse and Neglect Questionnaire were administered to 628 women. Of these, 127 (20.2%) women reported at least 1 type of PNP and 13 (2.1%) women reported possession. Women with a dissociative disorder reported all types of possession and PNP (except telepathy) more frequently than those without. Whereas women with a trauma history in childhood and adulthood or PTSD reported possession more frequently than those without, PNP were associated with childhood trauma only. Factor analysis yielded 4 dimensions: possession by and/or contact with nonhuman entities, extrasensory communications, possession by a human entity, and precognition. These factors correlated with number of secondary features of dissociative identity disorder and Schneiderian symptoms. Latent class analysis identified 3 groups. The most traumatized group, with predominantly dissociative and trauma-related disorders, had the highest scores on all factors. Notwithstanding their presence in healthy individuals, possession and PNP were associated with trauma and dissociation in a subgroup of affected participants. Both types of experience seem to be normal human capacities of experiencing that may be involved in response to traumatic stress. Given the small numbers, this study should be considered preliminary.

Immobilized cells of Candida rugosa possessing fumarase activity

Energy Technology Data Exchange (ETDEWEB)

Yang, L.; Zhone, L.

1980-01-01

Immobilized cells of C. rugosa that possessed fumarase activity were prepared by different methods; the most active immobilized cells were entrapped in polyacrylamide gels. The effects of pH temperature, and divalent cations on the fumarase activity of both immobilized and native cells were the same. Mn/sup 2 +/, Mg/sup 2 +/, Ca/sup 2 +/, and Fe/sup 2 +/ did not protect the immobilized enzyme against thermal inactivation. The activity of immobilized fumarase remained constant during 91 days of storage of 4-6 degrees. The immobilized cell column was used for the continuous production of L-malic acid from 1M fumarate at 30 degrees and pH 8.5. The immobilized column operated steadily for 2 months. Half life of the immobilized fumarase at 30 degrees was 95 days.

Competences possessed and required by European graduates. REFLEX Report to HEFCE No 4

OpenAIRE

Little, Brenda; Braun, Edith; Tang, Win-Yee

2008-01-01

The report is based on the results of a major international study of graduate employment some five years after graduation. It presents an analysis of graduates' perceptions of what competences they need to do their current jobs and whether they possess these competences.

Resolution No. 96/03 About possession of ionic smoke detectors

International Nuclear Information System (INIS)

2004-01-01

The resolution states that: first: all the entities of the country having Ionic smoke detectors in use are to be communicated to the National Center for Nuclear safety in correspondence with the format that is shown in the annex to the present. This formation must be updated every three years. Second: Entities possessing Ionic smoke detectors in use, must be corresponding management as radioactive waste of such detectors in the term of one year from the entry into force of this resolution with the center of protection and of radiation hygiene purposes ensure safe and proper management as radioactive material into disuse. Third: Importing entities, distributors, and that made the Assembly of ionic smoke detectors, continue to be governed by the provisions of the resolution No.. 25/98 of this Ministry, R ules for the authorization of practices associated the employment of las radiation ionizing . Fourth: Entities in which ionic smoke detectors are installed must complete information according to the annex to the present format and send it to the National Center for Nuclear safety within a period of 30 days from the installation of such detectors. Fifth: Entities that possess Ionic smoke detectors and decide to continue using them should not be the evacuation of the same with the center of protection and hygiene of radiation, for the purpose of ensuring a safe and proper management as radioactive material in disuse, notifying this Act to the National Center for Nuclear safety.

Unravelling the spirits’ message: a study of help-seeking steps and explanatory models among patients suffering from spirit possession in Uganda

Science.gov (United States)

2014-01-01

As in many cultures, also in Uganda spirit possession is a common idiom of distress associated with traumatic experiences. In the DSM-IV and -5, possession trance disorders can be classified as dissociative disorders. Dissociation in Western countries is associated with complicated, time-consuming and costly therapies. Patients with spirit possession in SW Uganda, however, often report partial or full recovery after treatment by traditional healers. The aim of this study is to explore how the development of symptoms concomitant help-seeking steps, and explanatory models (EM) eventually contributed to healing of patients with spirit possession in SW Uganda. Illness narratives of 119 patients with spirit possession referred by traditional healers were analysed using a mixed-method approach. Treatments of two-thirds of the patients were unsuccessful when first seeking help in the medical sector. Their initially physical symptoms subsequently developed into dissociative possession symptoms. After an average of two help-seeking steps, patients reached a healing place where 99% of them found satisfactory EM and effective healing. During healing sessions, possessing agents were summoned to identify themselves and underlying problems were addressed. Often-mentioned explanations were the following: neglect of rituals and of responsibilities towards relatives and inheritance, the call to become a healer, witchcraft, grief, and land conflicts. The results demonstrate that traditional healing processes of spirit possession can play a role in restoring connections with the supra-, inter-, intra-, and extra-human worlds. It does not always seem necessary to address individual traumatic experiences per se, which is in line with other research in this field. The study leads to additional perspectives on treatment of trauma-related dissociation in Western countries and on developing effective mental health services in low -and middle-income countries. PMID:24940355

Unravelling the spirits' message: a study of help-seeking steps and explanatory models among patients suffering from spirit possession in Uganda.

Science.gov (United States)

van Duijl, Marjolein; Kleijn, Wim; de Jong, Joop

2014-01-01

As in many cultures, also in Uganda spirit possession is a common idiom of distress associated with traumatic experiences. In the DSM-IV and -5, possession trance disorders can be classified as dissociative disorders. Dissociation in Western countries is associated with complicated, time-consuming and costly therapies. Patients with spirit possession in SW Uganda, however, often report partial or full recovery after treatment by traditional healers. The aim of this study is to explore how the development of symptoms concomitant help-seeking steps, and explanatory models (EM) eventually contributed to healing of patients with spirit possession in SW Uganda. Illness narratives of 119 patients with spirit possession referred by traditional healers were analysed using a mixed-method approach. Treatments of two-thirds of the patients were unsuccessful when first seeking help in the medical sector. Their initially physical symptoms subsequently developed into dissociative possession symptoms. After an average of two help-seeking steps, patients reached a healing place where 99% of them found satisfactory EM and effective healing. During healing sessions, possessing agents were summoned to identify themselves and underlying problems were addressed. Often-mentioned explanations were the following: neglect of rituals and of responsibilities towards relatives and inheritance, the call to become a healer, witchcraft, grief, and land conflicts. The results demonstrate that traditional healing processes of spirit possession can play a role in restoring connections with the supra-, inter-, intra-, and extra-human worlds. It does not always seem necessary to address individual traumatic experiences per se, which is in line with other research in this field. The study leads to additional perspectives on treatment of trauma-related dissociation in Western countries and on developing effective mental health services in low -and middle-income countries.

Logarithmic residues of analytic Banach algebra valued functions possessing a simply meromorphic inverse

NARCIS (Netherlands)

H. Bart (Harm); T. Ehrhardt; B. Silbermann

2001-01-01

textabstractA logarithmic residue is a contour integral of a logarithmic derivative (left or right) of an analytic Banach algebra valued function. For functions possessing a meromorphic inverse with simple poles only, the logarithmic residues are identified as the sums of idempotents. With the help

19 CFR 7.3 - Duty-free treatment of goods imported from insular possessions of the United States other than...

Science.gov (United States)

2010-04-01

... INSULAR POSSESSIONS AND GUANTANAMO BAY NAVAL STATION § 7.3 Duty-free treatment of goods imported from...) The goods became a new and different article of commerce as a result of production or manufacture... possession or the United States results from the original commercial transaction between the importer and the...

Effects of Offense, Defense, and Ball Possession on Mobility Performance in Wheelchair Basketball

NARCIS (Netherlands)

de Witte, Annemarie M. H.; Berger, Monique A. M.; Hoozemans, Marco J. M.; Veeger, Dirkjan H. E. J.; van der Woude, Lucas H. V.

2017-01-01

The aim of this study was to determine to what extent mobility performance is influenced by offensive or defensive situations and ball possession and to what extent these actions are different for the field positions. From video analysis, the relative duration of the various wheelchair movements

Effects of offense, defense, and ball possession on mobility performance in wheelchair basketball

NARCIS (Netherlands)

De Witte, Annemarie M.H.; Berger, Monique A.M.; Hoozemans, Marco J.M.; Veeger, H.E.J.; van der Woude, Lucas H.V.

2017-01-01

The aim of this study was to determine to what extent mobility performance is influenced by offensive or defensive situations and ball possession and to what extent these actions are different for the field positions. From video analysis, the relative duration of the various wheelchair movements

A mosaic adenovirus possessing serotype Ad5 and serotype Ad3 knobs exhibits expanded tropism

International Nuclear Information System (INIS)

Takayama, Koichi; Reynolds, Paul N.; Short, Joshua J.; Kawakami, Yosuke; Adachi, Yasuo; Glasgow, Joel N.; Rots, Marianne G.; Krasnykh, Victor; Douglas, Joanne T.; Curiel, David T.

2003-01-01

The efficiency of cancer gene therapy with recombinant adenoviruses based on serotype 5 (Ad5) has been limited partly because of variable, and often low, expression by human primary cancer cells of the primary cellular-receptor which recognizes the knob domain of the fiber protein, the coxsackie and adenovirus receptor (CAR). As a means of circumventing CAR deficiency, Ad vectors have been retargeted by utilizing chimeric fibers possessing knob domains of alternate Ad serotypes. We have reported that ovarian cancer cells possess a primary receptor for Ad3 to which the Ad3 knob binds independently of the CAR-Ad5 knob interaction. Furthermore, an Ad5-based chimeric vector, designated Ad5/3, containing a chimeric fiber proteins possessing the Ad3 knob, demonstrates CAR-independent tropism by virtue of targeting the Ad3 receptor. Based on these findings, we hypothesized that a mosaic virus possessing both the Ad5 knob and the Ad3 knob on the same virion could utilize either primary receptor, resulting in expanded tropism. In this study, we generated a dual-knob mosaic virus by coinfection of 293 cells with Ad5-based and Ad5/3-based vectors. Characterization of the resultant virions confirmed the incorporation of both Ad5 and Ad3 knobs in the same particle. Furthermore, this mosaic virus was able to utilize either receptor, CAR and the Ad3 receptor, for virus attachment to cells. Enhanced Ad infectivity with the mosaic virus was shown in a panel of cell lines, with receptor profiles ranging from CAR-dominant to Ad3 receptor-dominant. Thus, this mosaic virus strategy may offer the potential to improve Ad-based gene therapy approaches by infectivity enhancement and tropism expansion

Radiation protective agents possessing anti-oxidative properties

Energy Technology Data Exchange (ETDEWEB)

Anzai, Kazunori; Ueno, Emi; Yoshida, Akira; Furuse, Masako; Ikota, Nobuo [National Inst. of Radiological Sciences, Research Center for Radiation Safety, Chiba, Chiba (Japan)

2005-11-15

The purpose of studies is to see mechanisms of radiation protection of agents possessing anti-oxidative properties because the initial step resulting in radiation hazard is the formation of radicals by water radiolysis. Agents were commercially available or synthesized proxyl derivatives (spin prove agents), commercially available spin-trapping agents, edaravone and TMG (a tocopherol glycoside). Mice and cultured cells were X-irradiated by Shimadzu Pantak HF-320 or 320S. Survivals of cells were determined by colony assay and of mice, to which the agents were given intraperitoneally before or after X-irradiation, within 30 days post irradiation. Plasma and marrow concentrations of proxyls were estimated by electron spin resonance (ESR) spectrometry. Mechanisms of their radiation protective effects were shown different from agent to agent. TMG was found effective even post irradiation, which suggests a possibility for a new drug development. Some (spin trapping agents and TMG), virtually ineffective at the cell level, were found effective in the whole body, suggesting the necessity of studies on their disposition and metabolism. (S.I.)

Radiation protective agents possessing anti-oxidative properties

International Nuclear Information System (INIS)

Anzai, Kazunori; Ueno, Emi; Yoshida, Akira; Furuse, Masako; Ikota, Nobuo

2005-01-01

The purpose of studies is to see mechanisms of radiation protection of agents possessing anti-oxidative properties because the initial step resulting in radiation hazard is the formation of radicals by water radiolysis. Agents were commercially available or synthesized proxyl derivatives (spin prove agents), commercially available spin-trapping agents, edaravone and TMG (a tocopherol glycoside). Mice and cultured cells were X-irradiated by Shimadzu Pantak HF-320 or 320S. Survivals of cells were determined by colony assay and of mice, to which the agents were given intraperitoneally before or after X-irradiation, within 30 days post irradiation. Plasma and marrow concentrations of proxyls were estimated by electron spin resonance (ESR) spectrometry. Mechanisms of their radiation protective effects were shown different from agent to agent. TMG was found effective even post irradiation, which suggests a possibility for a new drug development. Some (spin trapping agents and TMG), virtually ineffective at the cell level, were found effective in the whole body, suggesting the necessity of studies on their disposition and metabolism. (S.I.)

What does it mean to be possessed by a spirit or demon? Some ...

African Journals Online (AJOL)

The visible growth in possession and exorcism in Southern Africa can, amongst others, be attributed to the general impression in Christianity that, since Jesus was a successful exorcist, his followers should follow his example. Historical Jesus research generally endorses a view of Jesus as exorcist, which probably also ...

Provable Data Possession of Resource-constrained Mobile Devices in Cloud Computing

OpenAIRE

Jian Yang; Haihang Wang; Jian Wang; Chengxiang Tan; Dingguo Yu

2011-01-01

Benefited from cloud storage services, users can save their cost of buying expensive storage and application servers, as well as deploying and maintaining applications. Meanwhile they lost the physical control of their data. So effective methods are needed to verify the correctness of the data stored at cloud servers, which are the research issues the Provable Data Possession (PDP) faced. The most important features in PDP are: 1) supporting for public, unlimited numbers of times of verificat...

Controlling Underwater Robots with Electronic Nervous Systems

Directory of Open Access Journals (Sweden)

Joseph Ayers

2010-01-01

Full Text Available We are developing robot controllers based on biomimetic design principles. The goal is to realise the adaptive capabilities of the animal models in natural environments. We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration electronic neuron (aVLSI networks. DTM networks are realised using neurons based on a 1-D or 2-D Map with two additional parameters that define silent, spiking and bursting regimes. Electronic neurons (ENs based on Hindmarsh–Rose (HR dynamics can be instantiated in analogue VLSI and exhibit similar behaviour to those based on discrete components. We have constructed locomotor central pattern generators (CPGs with aVLSI networks that can be modulated to select different behaviours on the basis of selective command input. The two technologies can be fused by interfacing the signals from the DTM circuits directly to the aVLSI CPGs. Using DTMs, we have been able to simulate complex sensory fusion for rheotaxic behaviour based on both hydrodynamic and optical flow senses. We will illustrate aspects of controllers for ambulatory biomimetic robots. These studies indicate that it is feasible to fabricate an electronic nervous system controller integrating both aVLSI CPGs and layered DTM exteroceptive reflexes.

Breaking The Millisecond Barrier On SpiNNaker: Implementing Asynchronous Event-Based Plastic Models With Microsecond Resolution

Directory of Open Access Journals (Sweden)

Xavier eLagorce

2015-06-01

Full Text Available Spike-based neuromorphic sensors such as retinas and cochleas, change the way in which the world is sampled. Instead of producing data sampled at a constant rate, these sensors output spikes that are asynchronous and event driven. The event-based nature of neuromorphic sensors implies a complete paradigm shift in current perception algorithms towards those that emphasize the importance of precise timing. The spikes produced by these sensors usually have a time resolution in the order of microseconds. This high temporal resolution is a crucial factor in learning tasks. It is also widely used in the field of biological neural networks. Sound localization for instance relies on detecting time lags between the two ears which, in the barn owl, reaches a temporal resolution of 5 microseconds. Current available neuromorphic computation platforms such as SpiNNaker often limit their users to a time resolution in the order of milliseconds that is not compatible with the asynchronous outputs of neuromorphic sensors. To overcome these limitations and allow for the exploration of new types of neuromorphic computing architectures, we introduce a novel software framework on the SpiNNaker platform. This framework allows for simulations of spiking networks and plasticity mechanisms using a completely asynchronous and event-based scheme running with a microsecond time resolution. Results on two example networks using this new implementation are presented.

26 CFR 1.937-3 - Income effectively connected with the conduct of a trade or business in a possession.

Science.gov (United States)

2010-04-01

... operates an active financing business from offices in, Possession I. Interests in G are owned by D, a bona... of a trade or business in a possession. 1.937-3 Section 1.937-3 Internal Revenue INTERNAL REVENUE... United States § 1.937-3 Income effectively connected with the conduct of a trade or business in a...

What does it mean to be possessed by a spirit or demon? Some ...

African Journals Online (AJOL)

2015-07-08

Jul 8, 2015 ... Commons Attribution. License. .... Klass (2003:3) I therefore want to ask the question: 'What is actually .... help to categorise possession in terms of possible causal ... control of life. .... a social structure, the complex formed by all his [her] social ... a way to cope with stressful experiences and, together with.

7 CFR 330.300 - Soil from foreign countries or Territories or possessions. 1

Science.gov (United States)

2010-01-01

... 7 Agriculture 5 2010-01-01 2010-01-01 false Soil from foreign countries or Territories or possessions. 1 330.300 Section 330.300 Agriculture Regulations of the Department of Agriculture (Continued) ANIMAL AND PLANT HEALTH INSPECTION SERVICE, DEPARTMENT OF AGRICULTURE FEDERAL PLANT PEST REGULATIONS; GENERAL; PLANT PESTS; SOIL, STONE, AND QUARRY...

How Risky Is Marijuana Possession? Considering the Role of Age, Race, and Gender

Science.gov (United States)

Nguyen, Holly; Reuter, Peter

2012-01-01

Arrest rates per capita for possession of marijuana have increased threefold over the last 20 years and now constitute the largest single arrest offense category. Despite the increase in arrest numbers, rates of use have remained stable during much of the same period. This article presents the first estimates of the arrest probabilities for…

Power, slavery, and spirit possession in East Africa: A few reflections

Directory of Open Access Journals (Sweden)

Beatrice Nicolini

2014-02-01

Full Text Available Spirit possession and its relationship with power aims to offer here a better understanding not only of East African societies, but, most of all, of their historical role in numerous political and military conflicts and also within peace-building processes that represent a continuation of a topic of longstanding concern in East African history. The relationships between religions, local cultures and institutional powers throughout contemporary East African history will be re-read through regional and transnational, as well as international dynamics.

THE RELATIONSHIP BETWEEN RESEARCH AND TEACHING: THE CHART OF POSSESSIVE PRONOUNS IN PORTUGUESE

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Leonardo Lennertz Marcotulio

2016-01-01

Full Text Available The aim of this article is to investigate the relationship between research and teaching, concerning the rearrangements operated in the chart of possessive pronouns,  observing in which way sociolinguistic studies have been applied to the teaching of Portuguese through the didactic material prepared for High School and the courses of Portuguese as a Foreign Language.