Netlist Oriented Sensitivity Evaluation (NOSE)
2017-03-01
similar Boolean Algebra techniques, demonstrate how alternative netlist implementations can alter sensitivity University of Southern California...13 Approved for public release; distribution unlimited. SCOAP Controllability Metrics: The basic process: Set PIs to 1...progress from PIs to POs, add 1 to account for logic depth. SCOAP Observability Metric: The basic process: After controllabilities computed
NetList(+): A simple interface language for chip design
Wuu, Tzyh-Yung
1991-04-01
NetList (+) is a design specification language developed at MOSIS for rapid turn-around cell-based ASIC prototyping. By using NetList (+), a uniform representation is achieved for the specification, simulation, and physical description of a design. The goal is to establish an interfacing methodology between design specification and independent computer aided design tools. Designers need only to specify a system by writing a corresponding netlist. This netlist is used for both functional simulation and timing simulation. The same netlist is also used to derive the low level physical tools to generate layout. Another goal of using NetList (+) is to generate parts of a design by running it through different kinds of placement and routing (P and R) tools. For example some parts of a design will be generated by standard cell P and R tools. Other parts may be generated by a layout tiler; i.e., datapath compiler, RAM/ROM generator, or PLA generator. Finally all different parts of a design can be integrated by general block P and R tools as a single chip. The NetList (+) language can actually act as an interface among tools. Section 2 shows a flowchart to illustrate the NetList (+) system and its relation with other related design tools. Section 3 shows how to write a NetList (+) description from the block diagram of a circuit. In section 4 discusses how to prepare a cell library or several cell libraries for a design system. Section 5 gives a few designs by NetList (+) and shows their simulation and layout results.
Einspruch, Norman G
1986-01-01
VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special
Basu, D K
2014-01-01
Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...
Triple Modular Redundancy verification via heuristic netlist analysis
Directory of Open Access Journals (Sweden)
Giovanni Beltrame
2015-08-01
Full Text Available Triple Modular Redundancy (TMR is a common technique to protect memory elements for digital processing systems subject to radiation effects (such as in space, high-altitude, or near nuclear sources. This paper presents an approach to verify the correct implementation of TMR for the memory elements of a given netlist (i.e., a digital circuit specification using heuristic analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour even for large designs. This is achieved by applying a divide et impera approach, splitting the circuit into smaller submodules without loss of generality, instead of applying formal verification to the whole netlist at once. The methodology has been applied to a production netlist of the LEON2-FT processor that had reported errors during radiation testing, successfully showing a number of unprotected memory elements, namely 351 flip-flops.
Chandrasetty, Vikram Arkalgud
2011-01-01
This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic
Einspruch, Norman G; Gildenblat, Gennady Sh
1987-01-01
VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec
VLSI electronics microstructure science
1982-01-01
VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t
Kemeny, Sabrina E.
1994-01-01
Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional
Towards a more accurate extraction of the SPICE netlist from MAGIC based layouts
Energy Technology Data Exchange (ETDEWEB)
Geronimo, G.D.
1998-08-01
The extraction of the SPICE netlist form MAGIC based layouts is investigated. It is assumed that the layout is fully coherent with the corresponding mask representation. The process of the extraction can be made in three steps: (1) extraction of .EXT file from layout, through MAGIC command extract; (2) extraction of the netlist from .EXT file through ext2spice extractor; and (3) correction of the netlist through ext2spice.corr program. Each of these steps introduces some approximations, most of which can be optimized, and some errors, most of which can be corrected. Aim of this work is the description of each step, of the approximations and errors on each step, and of the corresponding optimizations and corrections to be made in order to improve the accuracy of the extraction. The HP AMOS14TB 0.5 {micro}m process with linear capacitor and silicide block options and the corresponding SCN3MLC{_}SUBM.30.tech27 technology file will be used in the following examples.
VLSI electronics microstructure science
1981-01-01
VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi
Einspruch, Norman G
1989-01-01
VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The
Energy Technology Data Exchange (ETDEWEB)
Hojat, S.
1986-01-01
The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.
DEFF Research Database (Denmark)
Rasmussen, Ole Steen
This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....
VLSI Universal Noiseless Coder
Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi
1989-01-01
Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.
Einspruch, Norman G
1984-01-01
VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section
Verweij, Jan F.
1993-01-01
Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was
Latent geometry of bipartite networks
Kitsak, Maksim; Papadopoulos, Fragkiskos; Krioukov, Dmitri
2017-03-01
Despite the abundance of bipartite networked systems, their organizing principles are less studied compared to unipartite networks. Bipartite networks are often analyzed after projecting them onto one of the two sets of nodes. As a result of the projection, nodes of the same set are linked together if they have at least one neighbor in common in the bipartite network. Even though these projections allow one to study bipartite networks using tools developed for unipartite networks, one-mode projections lead to significant loss of information and artificial inflation of the projected network with fully connected subgraphs. Here we pursue a different approach for analyzing bipartite systems that is based on the observation that such systems have a latent metric structure: network nodes are points in a latent metric space, while connections are more likely to form between nodes separated by shorter distances. This approach has been developed for unipartite networks, and relatively little is known about its applicability to bipartite systems. Here, we fully analyze a simple latent-geometric model of bipartite networks and show that this model explains the peculiar structural properties of many real bipartite systems, including the distributions of common neighbors and bipartite clustering. We also analyze the geometric information loss in one-mode projections in this model and propose an efficient method to infer the latent pairwise distances between nodes. Uncovering the latent geometry underlying real bipartite networks can find applications in diverse domains, ranging from constructing efficient recommender systems to understanding cell metabolism.
Einspruch, Norman G
1987-01-01
VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.
Chen, Wai-Kai
2009-01-01
Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.
Grandcanonical projection of bipartite networks
Saracco, Fabio; Gabrielli, Andrea; Squartini, Tiziano
2016-01-01
Bipartite networks are currently regarded as providing a major insight into the organization of real-world systems, unveiling the mechanisms shaping the interactions occurring between distinct groups of nodes. One of the major problems encountered when dealing with bipartite networks is obtaining a (monopartite) projection over the layer of interest which preserves as much as possible the information encoded into the original bipartite structure. In the present paper we propose an algorithm to obtain statistically-validated projections of bipartite networks. The criterion adopted to quantify the similarity of nodes rests upon the similarity of their neighborhoods: in order for any two nodes to be linked, a significantly-large number of neighbors must be shared. Naturally, assessing the statistical significance of nodes similarity requires the definition of a proper statistical benchmark: here we consider two recently-proposed null models for bipartite networks, opportunely defined through the exponential rand...
Latent geometry of bipartite networks
Kitsak, Maksim; Krioukov, Dmitri
2016-01-01
Despite the abundance of bipartite networked systems, their organizing principles are less studied, compared to unipartite networks. Bipartite networks are often analyzed after projecting them onto one of the two sets of nodes. As a result of the projection, nodes of the same set are linked together if they have at least one neighbor in common in the bipartite network. Even though these projections allow one to study bipartite networks using tools developed for unipartite networks, one-mode projections lead to significant loss of information and artificial inflation of the projected network with fully connected subgraphs. Here we pursue a different approach for analyzing bipartite systems that is based on the observation that such systems have a latent metric structure: network nodes are points in a latent metric space, while connections are more likely to form between nodes separated by shorter distances. This approach has been developed for unipartite networks, and relatively little is known about its appli...
Lami, Ludovico; Huber, Marcus
2016-09-01
We introduce a 3-parameter class of maps (1) acting on a bipartite system which are a natural generalisation of the depolarizing channel (and include it as a special case). Then, we find the exact regions of the parameter space that alternatively determine a positive, completely positive, entanglement-breaking, or entanglement-annihilating map. This model displays a much richer behaviour than the one shown by a simple depolarizing channel, yet it stays exactly solvable. As an example of this richness, positive partial transposition but not entanglement-breaking maps is found in Theorem 2. A simple example of a positive yet indecomposable map is provided (see the Remark at the end of Section IV). The study of the entanglement-annihilating property is fully addressed by Theorem 7. Finally, we apply our results to solve the problem of the entanglement annihilation caused in a bipartite system by a tensor product of local depolarizing channels. In this context, a conjecture posed in the work of Filippov [J. Russ. Laser Res. 35, 484 (2014)] is affirmatively answered, and the gaps that the imperfect bounds of Filippov and Ziman [Phys. Rev. A 88, 032316 (2013)] left open are closed. To arrive at this result, we furthermore show how the Hadamard product between quantum states can be implemented via local operations.
Directory of Open Access Journals (Sweden)
Urard Pascal
2006-01-01
Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.
Very Large Scale Integration (VLSI).
Yeaman, Andrew R. J.
Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…
Topological Minors in Bipartite Graphs
Institute of Scientific and Technical Information of China (English)
Camino BALBUENA; Martín CER.A; Pedro GARC(I)A-V(A)ZQUEZ; Juan Carlos VALENZUELA
2011-01-01
For a bipartite graph G on m and n vertices,respectively,in its vertices classes,and for integers s and t such that 2 ≤ s ≤ t,0≤ m-s≤ n-t,andm,+n≤ 2s+t-1,we prove that if G has at least mn- (2(m - s) + n - t) edges then it contains a subdivision of the complete bipartite K(s,t) with s vertices in the m-class and t vertices in the n-class.Furthermore,we characterize the corresponding extremal bipartite graphs with mn- (2(m - s) + n - t + 1) edges for this topological Turan type problem.
McKenzie, Neil
1989-12-01
We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.
Chen, Wai-Kai
2007-01-01
Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.
VLSI signal processing technology
Swartzlander, Earl
1994-01-01
This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in...
VLSI Architectures for Computing DFT's
Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.
1986-01-01
Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.
Fractal and multifractal analyses of bipartite networks.
Liu, Jin-Long; Wang, Jian; Yu, Zu-Guo; Xie, Xian-Hua
2017-03-31
Bipartite networks have attracted considerable interest in various fields. Fractality and multifractality of unipartite (classical) networks have been studied in recent years, but there is no work to study these properties of bipartite networks. In this paper, we try to unfold the self-similarity structure of bipartite networks by performing the fractal and multifractal analyses for a variety of real-world bipartite network data sets and models. First, we find the fractality in some bipartite networks, including the CiteULike, Netflix, MovieLens (ml-20m), Delicious data sets and (u, v)-flower model. Meanwhile, we observe the shifted power-law or exponential behavior in other several networks. We then focus on the multifractal properties of bipartite networks. Our results indicate that the multifractality exists in those bipartite networks possessing fractality. To capture the inherent attribute of bipartite network with two types different nodes, we give the different weights for the nodes of different classes, and show the existence of multifractality in these node-weighted bipartite networks. In addition, for the data sets with ratings, we modify the two existing algorithms for fractal and multifractal analyses of edge-weighted unipartite networks to study the self-similarity of the corresponding edge-weighted bipartite networks. The results show that our modified algorithms are feasible and can effectively uncover the self-similarity structure of these edge-weighted bipartite networks and their corresponding node-weighted versions.
Fractal and multifractal analyses of bipartite networks
Liu, Jin-Long; Wang, Jian; Yu, Zu-Guo; Xie, Xian-Hua
2017-01-01
Bipartite networks have attracted considerable interest in various fields. Fractality and multifractality of unipartite (classical) networks have been studied in recent years, but there is no work to study these properties of bipartite networks. In this paper, we try to unfold the self-similarity structure of bipartite networks by performing the fractal and multifractal analyses for a variety of real-world bipartite network data sets and models. First, we find the fractality in some bipartite networks, including the CiteULike, Netflix, MovieLens (ml-20m), Delicious data sets and (u, v)-flower model. Meanwhile, we observe the shifted power-law or exponential behavior in other several networks. We then focus on the multifractal properties of bipartite networks. Our results indicate that the multifractality exists in those bipartite networks possessing fractality. To capture the inherent attribute of bipartite network with two types different nodes, we give the different weights for the nodes of different classes, and show the existence of multifractality in these node-weighted bipartite networks. In addition, for the data sets with ratings, we modify the two existing algorithms for fractal and multifractal analyses of edge-weighted unipartite networks to study the self-similarity of the corresponding edge-weighted bipartite networks. The results show that our modified algorithms are feasible and can effectively uncover the self-similarity structure of these edge-weighted bipartite networks and their corresponding node-weighted versions. PMID:28361962
Fractal and multifractal analyses of bipartite networks
Liu, Jin-Long; Wang, Jian; Yu, Zu-Guo; Xie, Xian-Hua
2017-03-01
Bipartite networks have attracted considerable interest in various fields. Fractality and multifractality of unipartite (classical) networks have been studied in recent years, but there is no work to study these properties of bipartite networks. In this paper, we try to unfold the self-similarity structure of bipartite networks by performing the fractal and multifractal analyses for a variety of real-world bipartite network data sets and models. First, we find the fractality in some bipartite networks, including the CiteULike, Netflix, MovieLens (ml-20m), Delicious data sets and (u, v)-flower model. Meanwhile, we observe the shifted power-law or exponential behavior in other several networks. We then focus on the multifractal properties of bipartite networks. Our results indicate that the multifractality exists in those bipartite networks possessing fractality. To capture the inherent attribute of bipartite network with two types different nodes, we give the different weights for the nodes of different classes, and show the existence of multifractality in these node-weighted bipartite networks. In addition, for the data sets with ratings, we modify the two existing algorithms for fractal and multifractal analyses of edge-weighted unipartite networks to study the self-similarity of the corresponding edge-weighted bipartite networks. The results show that our modified algorithms are feasible and can effectively uncover the self-similarity structure of these edge-weighted bipartite networks and their corresponding node-weighted versions.
Synaptic dynamics in analog VLSI.
Bartolozzi, Chiara; Indiveri, Giacomo
2007-10-01
Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.
VLSI implementations for image communications
Pirsch, P
1993-01-01
The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits
Butterfly Effect: Peeling Bipartite Networks
Sariyuce, A Erdem
2016-01-01
Affiliation, or two-mode, networks, such as actor-movie, document-keyword, or user-product are prevalent in a lot of applications. The networks can be most naturally modeled as bipartite graphs, but most graph mining algorithms and implementations are designed to work on the classic, unipartite graphs. Subsequently, studies on affiliation networks are conducted on the co-occurrence graphs (e.g., co-authors and co-purchase networks), which projects the bipartite structure to a unipartite structure by connecting two entities if they share an affiliation. Despite their convenience, co-occurrence networks come at a cost of loss of information and an explosion in graph sizes. In this paper, we study the dense subgraph discovery problem on bipartite graphs. We propose peeling algorithms to find many dense substructures and a hierarchy among them. Our peeling algorithms are based on the butterfly subgraphs (2,2-bicliques). Experiments show that we can identify much denser structures compared to the state-of-the-art ...
VLSI mixed signal processing system
Alvarez, A.; Premkumar, A. B.
1993-01-01
An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.
Fundamentals of Microelectronics Processing (VLSI).
Takoudis, Christos G.
1987-01-01
Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)
The Link Prediction Problem in Bipartite Networks
Kunegis, Jérôme; Albayrak, Sahin
2010-01-01
We define and study the link prediction problem in bipartite networks, specializing general link prediction algorithms to the bipartite case. In a graph, a link prediction function of two vertices denotes the similarity or proximity of the vertices. Common link prediction functions for general graphs are defined using paths of length two between two nodes. Since in a bipartite graph adjacency vertices can only be connected by paths of odd lengths, these functions do not apply to bipartite graphs. Instead, a certain class of graph kernels (spectral transformation kernels) can be generalized to bipartite graphs when the positive-semidefinite kernel constraint is relaxed. This generalization is realized by the odd component of the underlying spectral transformation. This construction leads to several new link prediction pseudokernels such as the matrix hyperbolic sine, which we examine for rating graphs, authorship graphs, folksonomies, document--feature networks and other types of bipartite networks.
Bone-scintigraphy in painful bipartite patella
Energy Technology Data Exchange (ETDEWEB)
Iossifidis, A. [Orthopaedic Academic Unit, St. Thomas` Hospital, London (United Kingdom); Brueton, R.N. [Orthopaedic Academic Unit, St. Thomas` Hospital, London (United Kingdom); Nunan, T.O. [Dept. of Nuclear Medicine, St. Thomas` Hospital, London (United Kingdom)
1995-10-01
Although, the use of technetium scintigraphy in the assessment of anterior knee pain has been described, no reference has been made to the scintigraphic appearances of painful bipartite patella. We report the scintigraphic-appearances of painful bipartite patella in 25-year-old man a 2 1/2 years history of unexplained patellar pain. Painful bipartite patella is a rare cause of chronic post-traumatic patellar pain. Bone scintigraphy, by demonstrating increased uptake by the painful accessory bipartite fragment, appears to be an imaging method of choice in the diagnosis of this condition. (orig./MG)
The Fifth NASA Symposium on VLSI Design
1993-01-01
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.
A Design Methodology for Optoelectronic VLSI
2007-01-01
it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a
Effect of attachment strategies on bipartite networks
DEFF Research Database (Denmark)
Ganguly, N.; Saha, S.; Maiti, A.
2013-01-01
Bipartite systems show remarkable variations in their topological asymptotic properties, e. g., in their degree distribution. Such variations depend on the underlying growth dynamics. A scenario of particular importance is when the two partitions of the bipartite structure do not grow at an equal...
VLSI Watermark Implementations and Applications
Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly
2008-01-01
This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
VLSI Processor For Vector Quantization
Tawel, Raoul
1995-01-01
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
Bipartite flocking for multi-agent systems
Fan, Ming-Can; Zhang, Hai-Tao; Wang, Miaomiao
2014-09-01
This paper addresses the bipartite flock control problem where a multi-agent system splits into two clusters upon internal or external excitations. Using structurally balanced signed graph theory, LaSalle's invariance principle and Barbalat's Lemma, we prove that the proposed algorithm guarantees a bipartite flocking behavior. In each of the two disjoint clusters, all individuals move with the same direction. Meanwhile, every pair of agents in different clusters moves with opposite directions. Moreover, all agents in the two separated clusters approach a common velocity magnitude, and collision avoidance among all agents is ensured as well. Finally, the proposed bipartite flock control method is examined by numerical simulations. The bipartite flocking motion addressed by this paper has its references in both natural collective motions and human group behaviors such as predator-prey and panic escaping scenarios.
Bipartite Graphs of Large Clique-Width
Korpelainen, Nicholas; Lozin, Vadim V.
Recently, several constructions of bipartite graphs of large clique-width have been discovered in the literature. In the present paper, we propose a general framework for developing such constructions and use it to obtain new results on this topic.
Eigenvalues and expansion of bipartite graphs
DEFF Research Database (Denmark)
Høholdt, Tom; Janwa, Heeralal
2012-01-01
We prove lower bounds on the largest and second largest eigenvalue of the adjacency matrix of bipartite graphs and give necessary and sufficient conditions for equality. We give several examples of classes that are optimal with respect to the bouns. We prove that BIBD-graphs are characterized by ...... by their eigenvalues. Finally we present a new bound on the expansion coefficient of (c,d)-regular bipartite graphs and compare that with aclassical bound....
Surface and interface effects in VLSI
Einspruch, Norman G
1985-01-01
VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import
Implementing neural architectures using analog VLSI circuits
Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.
1989-05-01
Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.
VLSI implementation of neural networks.
Wilamowski, B M; Binfet, J; Kaynak, M O
2000-06-01
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.
Complex VLSI Feature Comparison for Commercial Microelectronics Verification
2014-03-27
verification of untrusted circuits using industry-standard and custom software. The process developed under TRUST and implemented at the AFRL Mixed Signal...79 5.2.3 SCR and Other Netlists . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.4 Additional Tools...Reliability of Integrated Circuits LVS layout versus schematic MOSIS the Metal Oxide Semiconductor Implementation Service MSDC Mixed Signal Design
An exact exponential time algorithm for counting bipartite cliques
DEFF Research Database (Denmark)
Kutzkov, Konstantin
2012-01-01
We present a simple exact algorithm for counting bicliques of given size in a bipartite graph on n vertices. We achieve running time of O(1.249^n), improving upon known exact algorithms for finding and counting bipartite cliques.......We present a simple exact algorithm for counting bicliques of given size in a bipartite graph on n vertices. We achieve running time of O(1.249^n), improving upon known exact algorithms for finding and counting bipartite cliques....
Sharma, Hrishikesh
2011-01-01
Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...
Measuring the entanglement of bipartite pure states
Sancho, J M
2000-01-01
The problem of the experimental determination of the amount of entanglement of a bipartite pure state is addressed. We show that measuring a single observable does not suffice to determine the entanglement of a given unknown pure state of two particles. Possible minimal local measuring strategies are discussed and a comparison is made on the basis of their best achievable precision.
Dynamic Matchings in Convex Bipartite Graphs
DEFF Research Database (Denmark)
Brodal, Gerth Stølting; Georgiadis, Loukas; Hansen, Kristoffer Arnsfelt
2007-01-01
We consider the problem of maintaining a maximum matching in a convex bipartite graph G = (V,E) under a set of update operations which includes insertions and deletions of vertices and edges. It is not hard to show that it is impossible to maintain an explicit representation of a maximum matching...
Three cases of bipartition of the atlas
Hummel, Edze; de Groot, Jan C.
2013-01-01
BACKGROUND CONTEXT: A bipartite atlas is a rare coincidental finding, and it is reported in only 0.1% of the general population. It is a congenital disorder characterized by incomplete fusion of the anterior and the posterior arches of C1, and it is important to differentiate it from a Jefferson fra
A coherent VLSI design environment
Penfield, Paul, Jr.
1988-05-01
The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.
Associative Pattern Recognition In Analog VLSI Circuits
Tawel, Raoul
1995-01-01
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Compact MOSFET models for VLSI design
Bhattacharyya, A B
2009-01-01
Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.
Alexander, George
1984-01-01
Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…
On bipartite graphs of defect at most 4
Feria-Purón, Ramiro
2010-01-01
We consider the bipartite version of the degree/diameter problem, namely, given natural numbers {\\Delta} \\geq 2 and D \\geq 2, find the maximum number Nb({\\Delta},D) of vertices in a bipartite graph of maximum degree {\\Delta} and diameter D. In this context, the Moore bipartite bound Mb({\\Delta},D) represents an upper bound for Nb({\\Delta},D). Bipartite graphs of maximum degree {\\Delta}, diameter D and order Mb({\\Delta},D), called Moore bipartite graphs, turned out to be very rare. Therefore, it is very interesting to investigate bipartite graphs of maximum degree {\\Delta} \\geq 2, diameter D \\geq 2 and order Mb({\\Delta},D) - \\epsilon with small \\epsilon > 0, that is, bipartite ({\\Delta},D,-\\epsilon)-graphs. The parameter \\epsilon is called the defect. This paper considers bipartite graphs of defect at most 4, and presents all the known such graphs. Bipartite graphs of defect 2 have been studied in the past; if {\\Delta} \\geq 3 and D \\geq 3, they may only exist for D = 3. However, when \\epsilon > 2 bipartite ({\\...
Bipartite and Multipartite Entanglement of Gaussian States
Adesso, G; Adesso, Gerardo; Illuminati, Fabrizio
2005-01-01
In this chapter we review the characterization of entanglement in Gaussian states of continuous variable systems. For two-mode Gaussian states, we discuss how their bipartite entanglement can be accurately quantified in terms of the global and local amounts of mixedness, and efficiently estimated by direct measurements of the associated purities. For multimode Gaussian states endowed with local symmetry with respect to a given bipartition, we show how the multimode block entanglement can be completely and reversibly localized onto a single pair of modes by local, unitary operations. We then analyze the distribution of entanglement among multiple parties in multimode Gaussian states. We introduce the continuous-variable tangle to quantify entanglement sharing in Gaussian states and we prove that it satisfies the Coffman-Kundu-Wootters monogamy inequality. Nevertheless, we show that pure, symmetric three-mode Gaussian states, at variance with their discrete-variable counterparts, allow a promiscuous sharing of ...
Perioperative management of facial bipartition surgery
Directory of Open Access Journals (Sweden)
Caruselli M
2015-11-01
Full Text Available Marco Caruselli,1 Michael Tsapis,1,2 Fabrice Ughetto,1 Gregoire Pech-Gourg,3 Dario Galante,4 Olivier Paut1 1Anesthesia and Intensive Care Unit, La Timone Children’s Hospital, 2Pediatric Transport Team, SAMU 13, La Timone Hospital, 3Pediatric Neurosurgery Unit, La Timone Children’s Hospital, Marseille, France; 4Anesthesia and Intensive Care Unit, University Hospital Ospedali Riuniti of Foggia, Foggia, Italy Abstract: Severe craniofacial malformations, such as Crouzon, Apert, Saethre-Chotzen, and Pfeiffer syndromes, are very rare conditions (one in 50,000/100,000 live births that often require corrective surgery. Facial bipartition is the more radical corrective surgery. It is a high-risk intervention and needs complex perioperative management and a multidisciplinary approach. Keywords: craniofacial surgery, facial bipartition surgery, craniofacial malformations, pediatric anesthesia
Universality in bipartite mean field spin glasses
Genovese, Giuseppe
2011-01-01
In this work we give a proof of full universality with respect to the choice of the statistical distribution of the quenched noise, for many models of bipartite spin glasses. By using Guerra's interpolation tecnique we estimate the difference between the free energy of the gaussian model and the ones derived by a general class of random interactions, and check how it vanishes in the thermodynamic limit.
Online Assignment Algorithms for Dynamic Bipartite Graphs
Sahai, Ankur
2011-01-01
This paper analyzes the problem of assigning weights to edges incrementally in a dynamic complete bipartite graph consisting of producer and consumer nodes. The objective is to minimize the overall cost while satisfying certain constraints. The cost and constraints are functions of attributes of the edges, nodes and online service requests. Novelty of this work is that it models real-time distributed resource allocation using an approach to solve this theoretical problem. This paper studies v...
Complete Bipartite Anonymity for Location Privacy
Institute of Scientific and Technical Information of China (English)
董恺; 顾涛; 陶先平; 吕建
2014-01-01
Users are vulnerable to privacy risks when providing their location information to location-based services (LBS). Existing work sacrifices the quality of LBS by degrading spatial and temporal accuracy for ensuring user privacy. In this paper, we propose a novel approach, Complete Bipartite Anonymity (CBA), aiming to achieve both user privacy and quality of service. The theoretical basis of CBA is that: if the bipartite graph of k nearby users’ paths can be transformed into a complete bipartite graph, then these users achieve k-anonymity since the set of “end points connecting to a specific start point in a graph”is an equivalence class. To achieve CBA, we design a Collaborative Path Confusion (CPC) protocol which enables nearby users to discover and authenticate each other without knowing their real identities or accurate locations, predict the encounter location using users’ moving pattern information, and generate fake traces obfuscating the real ones. We evaluate CBA using a real-world dataset, and compare its privacy performance with existing path confusion approach. The results show that CBA enhances location privacy by increasing the chance for a user confusing his/her path with others by 4 to 16 times in low user density areas. We also demonstrate that CBA is secure under the trace identification attack.
An evolving model of online bipartite networks
Zhang, Chu-Xu; Zhang, Zi-Ke; Liu, Chuang
2013-12-01
Understanding the structure and evolution of online bipartite networks is a significant task since they play a crucial role in various e-commerce services nowadays. Recently, various attempts have been tried to propose different models, resulting in either power-law or exponential degree distributions. However, many empirical results show that the user degree distribution actually follows a shifted power-law distribution, the so-called Mandelbrot’s law, which cannot be fully described by previous models. In this paper, we propose an evolving model, considering two different user behaviors: random and preferential attachment. Extensive empirical results on two real bipartite networks, Delicious and CiteULike, show that the theoretical model can well characterize the structure of real networks for both user and object degree distributions. In addition, we introduce a structural parameter p, to demonstrate that the hybrid user behavior leads to the shifted power-law degree distribution, and the region of power-law tail will increase with the increment of p. The proposed model might shed some lights in understanding the underlying laws governing the structure of real online bipartite networks.
Community detection for networks with unipartite and bipartite structure
Chang, Chang; Tang, Chao
2013-01-01
Finding community structures in networks is important in network science, technology, and applications. To date, most algorithms that aim to find community structures only focus either on unipartite or bipartite networks. A unipartite network consists of one set of nodes and a bipartite network consists of two nonoverlapping sets of nodes with only links joining the nodes in different sets. However, a third type of network exists, defined here as the mixture network. Just like a bipartite net...
Cohen-Macaulay-ness in codimension for bipartite graphs
2013-01-01
Let $G$ be an unmixed bipartite graph of dimension $d-1$. Assume that $K_{n,n}$, with $n\\ge 2$, is a maximal complete bipartite subgraph of $G$ of minimum dimension. Then $G$ is Cohen-Macaulay in codimension $d-n+1$. This generalizes a characterization of Cohen-Macaulay bipartite graphs by Herzog and Hibi and a result of Cook and Nagel on unmixed Buchsbaum graphs. Furthermore, we show that any unmixed bipartite graph $G$ which is Cohen-Macaulay in codimension $t$, is obtained from a Cohen-Mac...
VLSI 'smart' I/O module development
Kirk, Dan
The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.
Harnessing VLSI System Design with EDA Tools
Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj
2012-01-01
This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...
VLSI Microsystem for Rapid Bioinformatic Pattern Recognition
Fang, Wai-Chi; Lue, Jaw-Chyng
2009-01-01
A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).
Leak detection utilizing analog binaural (VLSI) techniques
Hartley, Frank T. (Inventor)
1995-01-01
A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Generating Weighted Test Patterns for VLSI Chips
Siavoshi, Fardad
1990-01-01
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
Non-Markovian dynamics for bipartite systems
2008-01-01
We analyze the appearance of non-Markovian effects in the dynamics of a bipartite system coupled to a reservoir, which can be described within a class of non-Markovian equations given by a generalized Lindblad structure. A novel master equation, which we term quantum Bloch-Boltzmann equation, is derived, describing both motional and internal states of a test particle in a quantum framework. When due to the preparation of the system or to decoherence effects one of the two degrees of freedom i...
Epidemic spreading with immunization on bipartite networks
Tanimoto, Shinji
2011-01-01
Bipartite networks are composed of two types of nodes and there are no links between nodes of the same type. Thus the study of epidemic spread and control on such networks is relevant to sexually transmitted diseases (STDs). When entire populations of two types cannot be immunized and the effect of immunization is not perfect, we have to consider the targeted immunization with immunization rates. We derive the epidemic thresholds of SIR and SIS models with immunization and illustrate the results with STDs on heterosexual contact networks.
The Bipartite Swapping Trick on Graph Homomorphisms
Zhao, Yufei
2011-01-01
We provide an upper bound to the number of graph homomorphisms from $G$ to $H$, where $H$ is a fixed graph with certain properties, and $G$ varies over all $N$-vertex, $d$-regular graphs. This result generalizes a recently resolved conjecture of Alon and Kahn on the number of independent sets. We build on the work of Galvin and Tetali, who studied the number of graph homomorphisms from $G$ to $H$ when $H$ is bipartite. We also apply our techniques to graph colorings and stable set polytopes.
HAMILTONIAN DECOMPOSITION OF COMPLETE BIPARTITE r-HYPERGRAPHS
Institute of Scientific and Technical Information of China (English)
吉日木图; 王建方
2001-01-01
In [1] the concepts of paths and cycles of a hypergraph were introduced. In this paper, we give the concepts for bipartite hypergraph and Hamiltonian paths and cycles of a hypergraph,and prove that the complete bipartite 3-hypergraph with q vertices in each part is Hamiltonian decomposable where q is a prime.
A SUFFICIENT CONDITION FOR HAMILTONIAN CYCLES IN BIPARTITE TOURNAMENTS
Institute of Scientific and Technical Information of China (English)
无
2007-01-01
In this paper, we present a new sufficient condition on degrees for a bipartite tournament to be Hamiltonian, that is, if an n × n bipartite tournament T satisfies the condition W(n - 3), then T is Hamiltonian, except for four exceptional graphs. This result is shown to be best possible in a sense.
Quadriceps tendon rupture through a superolateral bipartite patella.
Woods, G William; O'Connor, Daniel P; Elkousy, Hussein A
2007-10-01
We report a case of a quadriceps tendon rupture through a bipartite patella. Although quadriceps tendon ruptures and patella fractures are common, rupture through a bipartite patella fragment is rare. This case was managed similar to a quadriceps rupture with an excellent result.
Jiang, P C; Chen, H
2006-01-01
VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.
Measuring and Modeling Bipartite Graphs with Community Structure
Aksoy, Sinan; Pinar, Ali
2016-01-01
Network science is a powerful tool for analyzing complex systems in fields ranging from sociology to engineering to biology. This paper is focused on generative models of bipartite graphs, also known as two-way graphs. We propose two generative models that can be easily tuned to reproduce the characteristics of real-world networks, not just qualitatively, but quantitatively. The measurements we consider are the degree distributions and the bipartite clustering coefficient, which we refer to as the metamorphosis coefficient. We define edge, node, and degreewise metamorphosis coefficients, enabling a more detailed understand of the bipartite community structure. Our proposed bipartite Chung-Lu model is able to reproduce real-world degree distributions, and our proposed bipartite "BTER" model reproduces both the degree distributions as well as the degreewise metamorphosis coefficients. We demonstrate the effectiveness of these models on several real-world data sets.
Connectivity and Nestedness in Bipartite Networks from Community Ecology
Energy Technology Data Exchange (ETDEWEB)
Corso, Gilberto [Departamento de Biofisica e Farmacologia, Centro de Biociencias, Universidade Federal do Rio Grande do Norte, UFRN - Campus Universitario, Lagoa Nova, CEP 59078 972, Natal, RN (Brazil); De Araujo, A I Levartoski [Instituto Federal de Educacao, Ciencia e Tecnologia do Ceara Av. Treze de Maio, 2081 - Benfica CEP 60040-531 - Fortaleza, CE (Brazil); De Almeida, Adriana M, E-mail: corso@cb.ufrn.br [Departamento de Botanica, Ecologia e Zoologia, Centro de Biociencias, Universidade Federal do Rio Grande do Norte, UFRN - Campus Universitario, Lagoa Nova, CEP 59078 972, Natal, RN (Brazil)
2011-03-01
Bipartite networks and the nestedness concept appear in two different contexts in theoretical ecology: community ecology and islands biogeography. From a mathematical perspective nestedness is a pattern in a bipartite network. There are several nestedness indices in the market, we used the index {nu}. The index {nu} is found using the relation {nu} = 1 - {tau} where {tau} is the temperature of the adjacency matrix of the bipartite network. By its turn {tau} is defined with help of the Manhattan distance of the occupied elements of the adjacency matrix of the bipartite network. We prove that the nestedness index {nu} is a function of the connectivities of the bipartite network. In addition we find a concise way to find {nu} which avoid cumbersome algorithm manupulation of the adjacency matrix.
Analogue VLSI for probabilistic networks and spike-time computation.
Murray, A
2001-02-01
The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.
Parallel optimization algorithms and their implementation in VLSI design
Lee, G.; Feeley, J. J.
1991-01-01
Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.
Trends and challenges in VLSI technology scaling towards 100 nm
Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram
Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm
Reaction-contingency based bipartite Boolean modelling
2013-01-01
Background Intracellular signalling systems are highly complex, rendering mathematical modelling of large signalling networks infeasible or impractical. Boolean modelling provides one feasible approach to whole-network modelling, but at the cost of dequantification and decontextualisation of activation. That is, these models cannot distinguish between different downstream roles played by the same component activated in different contexts. Results Here, we address this with a bipartite Boolean modelling approach. Briefly, we use a state oriented approach with separate update rules based on reactions and contingencies. This approach retains contextual activation information and distinguishes distinct signals passing through a single component. Furthermore, we integrate this approach in the rxncon framework to support automatic model generation and iterative model definition and validation. We benchmark this method with the previously mapped MAP kinase network in yeast, showing that minor adjustments suffice to produce a functional network description. Conclusions Taken together, we (i) present a bipartite Boolean modelling approach that retains contextual activation information, (ii) provide software support for automatic model generation, visualisation and simulation, and (iii) demonstrate its use for iterative model generation and validation. PMID:23835289
Statistically validated networks in bipartite complex systems.
Directory of Open Access Journals (Sweden)
Michele Tumminello
Full Text Available Many complex systems present an intrinsic bipartite structure where elements of one set link to elements of the second set. In these complex systems, such as the system of actors and movies, elements of one set are qualitatively different than elements of the other set. The properties of these complex systems are typically investigated by constructing and analyzing a projected network on one of the two sets (for example the actor network or the movie network. Complex systems are often very heterogeneous in the number of relationships that the elements of one set establish with the elements of the other set, and this heterogeneity makes it very difficult to discriminate links of the projected network that are just reflecting system's heterogeneity from links relevant to unveil the properties of the system. Here we introduce an unsupervised method to statistically validate each link of a projected network against a null hypothesis that takes into account system heterogeneity. We apply the method to a biological, an economic and a social complex system. The method we propose is able to detect network structures which are very informative about the organization and specialization of the investigated systems, and identifies those relationships between elements of the projected network that cannot be explained simply by system heterogeneity. We also show that our method applies to bipartite systems in which different relationships might have different qualitative nature, generating statistically validated networks in which such difference is preserved.
Statistically validated networks in bipartite complex systems
Tumminello, Michele; Lillo, Fabrizio; Piilo, Jyrki; Mantegna, Rosario N
2010-01-01
Many complex systems present an intrinsic bipartite nature and are often described and modeled in terms of networks [1-5]. Examples include movies and actors [1, 2, 4], authors and scientific papers [6-9], email accounts and emails [10], plants and animals that pollinate them [11, 12]. Bipartite networks are often very heterogeneous in the number of relationships that the elements of one set establish with the elements of the other set. When one constructs a projected network with nodes from only one set, the system heterogeneity makes it very difficult to identify preferential links between the elements. Here we introduce an unsupervised method to statistically validate each link of the projected network against a null hypothesis taking into account the heterogeneity of the system. We apply our method to three different systems, namely the set of clusters of orthologous genes (COG) in completely sequenced genomes [13, 14], a set of daily returns of 500 US financial stocks, and the set of world movies of the ...
Stability of the bipartite matching model
Bušić, Ana; Mairesse, Jean
2010-01-01
We consider the bipartite matching model of customers and servers introduced by Caldentey, Kaplan, and Weiss (Adv. Appl. Probab., 2009). Customers and servers play symmetrical roles. There is a finite set C resp. S, of customer, resp. server, classes. Time is discrete and at each time step, one customer and one server arrive in the system according to a joint probability measure on CxS, independently of the past. Also, at each time step, pairs of matched customer and server, if they exist, depart from the system. Authorized matchings are given by a fixed bipartite graph. A matching policy is chosen, which decides how to match when there are several possibilities. Customers/servers that cannot be matched are stored in a buffer. The evolution of the model can be described by a discrete time Markov chain. We study its stability under various admissible matching policies including: ML (Match the Longest), MS (Match the Shortest), FIFO (match the oldest), priorities. There exist natural necessary conditions for st...
Sexually Transmitted Diseases on Bipartite Graph
Wen, Luo-Sheng; Zhong, Jiang; Yang, Xiao-Fan
2009-01-01
We study the susceptible-infected-susceptible (SIS) epidemic model on bipartite graph. According to the difference of sex conception in western and oriental nations, we construct the Barabási Albert-Barabási Albert (BA-BA) model and Barabási-Albert Homogeneity (BA-HO) model for sexually transmitted diseases (STDs). Applying the rate equation approach, the positive equilibria of both models are given analytically. We find that the ratio between infected females and infected males is distinctly different in both models and the infected density in the BA-HO model is much less than that in the BA-BA model. These results explain that the countries with small ratio have less infected density than those with large ratio. Our numerical simulations verify these theoretical results.
Online Assignment Algorithms for Dynamic Bipartite Graphs
Sahai, Ankur
2011-01-01
This paper analyzes the problem of assigning weights to edges incrementally in a dynamic complete bipartite graph consisting of producer and consumer nodes. The objective is to minimize the overall cost while satisfying certain constraints. The cost and constraints are functions of attributes of the edges, nodes and online service requests. Novelty of this work is that it models real-time distributed resource allocation using an approach to solve this theoretical problem. This paper studies variants of this assignment problem where the edges, producers and consumers can disappear and reappear or their attributes can change over time. Primal-Dual algorithms are used for solving these problems and their competitive ratios are evaluated.
Verifying the Quantumness of Bipartite Correlations
Carmeli, Claudio; Heinosaari, Teiko; Karlsson, Antti; Schultz, Jussi; Toigo, Alessandro
2016-06-01
Entanglement is at the heart of most quantum information tasks, and therefore considerable effort has been made to find methods of deciding the entanglement content of a given bipartite quantum state. Here, we prove a fundamental limitation to deciding if an unknown state is entangled or not: we show that any quantum measurement which can answer this question for an arbitrary state necessarily gives enough information to identify the state completely. We also extend our treatment to other classes of correlated states by considering the problem of deciding if a state has negative partial transpose, is discordant, or is fully classically correlated. Remarkably, only the question related to quantum discord can be answered without resorting to full state tomography.
Sexually Transmitted Diseases on Bipartite Graph
Institute of Scientific and Technical Information of China (English)
WEN Luo-Sheng; ZHONG Jiang; YANG Xiao-Fan
2009-01-01
We study the susceptible-infected-susceptible (SIS) epidemic model on bipartite graph. According to the dif-ference of sex conception in western and oriental nations, we construct the Barabasi Albert-Barabasi Albert (BA-BA) model and Barabasi-Albert Homogeneity (BA-HO) model for sexually transmitted diseases (STDs). Applying the rate equation approach, the positive equilibria of both models are given analytically. We lind that the ratio between infected females and infected males is distinctly different in both models and the infected den-sity in the BA-HO model is much less than that in the BA-BA model. These results explain that the countries with small ratio have less infected density than those with large ratio. Our numerical simulations verify these theoretical results.
Relativistic quantum correlations in bipartite fermionic states
Indian Academy of Sciences (India)
S KHAN; N A KHAN
2016-10-01
The influences of relative motion, the size of the wave packet and the average momentum of the particles on different types of correlations present in bipartite quantum states are investigated. In particular, the dynamics of the quantum mutual information, the classical correlation and the quantum discord on the spincorrelations of entangled fermions are studied. In the limit of small average momentum, regardless of the size of the wave packet and the rapidity, the classical and the quantum correlations are equally weighted. On the otherhand, in the limit of large average momentum, the only correlations that exist in the system are the quantum correlations. For every value of the average momentum, the quantum correlations maximize at an optimal size of the wave packet. It is shown that after reaching a minimum value, the revival of quantum discord occurs with increasing rapidity.
Hot multiboundary wormholes from bipartite entanglement
Marolf, Donald; Peach, Alex; Ross, Simon F
2015-01-01
We analyze the 1+1 CFT states dual to hot (time-symmetric) 2+1 multiboundary AdS wormholes. These are black hole geometries with high local temperature, $n \\ge 1$ asymptotically-AdS$_3$ regions, and arbitrary internal topology. The dual state at $t=0$ is defined on $n$ circles. We show these to be well-described by sewing together tensor networks corresponding to thermofield double states. As a result, the entanglement is spatially localized and bipartite: away from particular boundary points ("vertices") any small connected region $A$ of the boundary CFT is entangled only with another small connected region $B$, where $B$ may lie on a different circle or may be a different part of the same circle. We focus on the pair-of-pants case, from which more general cases may be constructed. We also discuss finite-temperature corrections, where we note that the states involve a code subspace in each circle.
Stability of similarity measurements for bipartite networks
Liu, Jian-Guo; Pan, Xue; Guo, Qiang; Zhou, Tao
2015-01-01
Similarity is a fundamental measure in network analyses and machine learning algorithms, with wide applications ranging from personalized recommendation to socio-economic dynamics. We argue that an effective similarity measurement should guarantee the stability even under some information loss. With six bipartite networks, we investigate the stabilities of fifteen similarity measurements by comparing the similarity matrixes of two data samples which are randomly divided from original data sets. Results show that, the fifteen measurements can be well classified into three clusters according to their stabilities, and measurements in the same cluster have similar mathematical definitions. In addition, we develop a top-$n$-stability method for personalized recommendation, and find that the unstable similarities would recommend false information to users, and the performance of recommendation would be largely improved by using stable similarity measurements. This work provides a novel dimension to analyze and eval...
VLSI Circuits for High Speed Data Conversion
1994-05-16
Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp
Self arbitrated VLSI asynchronous sequential circuits
Whitaker, S.; Maki, G.
1990-01-01
A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.
Single Spin Logic Implementation of VLSI Adders
Shukla, Soumitra
2011-01-01
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.
An Analog VLSI Saccadic Eye Movement System
1994-01-01
In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...
Communication Protocols Augmentation in VLSI Design Applications
Directory of Open Access Journals (Sweden)
Kanhu Charan Padhy
2015-05-01
Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
VLSI binary multiplier using residue number systems
Energy Technology Data Exchange (ETDEWEB)
Barsi, F.; Di Cola, A.
1982-01-01
The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.
Wavelength-encoded OCDMA system using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal
2007-07-01
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
Technology computer aided design simulation for VLSI MOSFET
Sarkar, Chandan Kumar
2013-01-01
Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and
The VLSI-PLM Board: Design, Construction, and Testing
1989-03-01
Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The
Bilinear Interpolation Image Scaling Processor for VLSI
Directory of Open Access Journals (Sweden)
Ms. Pawar Ashwini Dilip
2014-05-01
Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process
VLSI circuits for high speed data conversion
Wooley, Bruce A.
1994-05-01
The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.
Bipartite quantum systems: on the realignment criterion and beyond
Energy Technology Data Exchange (ETDEWEB)
Lupo, Cosmo; Aniello, Paolo [Dipartimento di Scienze Fisiche dell' Universita di Napoli ' Federico II' , via Cintia, I-80126 Napoli (Italy); Scardicchio, Antonello [Princeton Center for Theoretical Physics and Department of Physics, Princeton University, Princeton, NJ 08544 (United States)], E-mail: lupo@na.infn.it, E-mail: aniello@na.infn.it, E-mail: ascardic@princeton.edu
2008-10-17
Inspired by the 'computable cross norm' or 'realignment' criterion, we propose a new point of view about the characterization of the states of bipartite quantum systems. We consider a Schmidt decomposition of a bipartite density operator. The corresponding Schmidt coefficients, or the associated symmetric polynomials, are regarded as quantities that can be used to characterize bipartite quantum states. In particular, starting from the realignment criterion, a family of necessary conditions for the separability of bipartite quantum states are derived. We conjecture that these conditions, which are weaker than the parent criterion, can be strengthened in such a way to obtain a new family of criteria that are independent of the original one. This conjecture is supported by numerical examples for the low dimensional cases. These ideas can be applied to the study of quantum channels, leading to a relation between the rate of contraction of a map and its ability to preserve entanglement.
Randomizing bipartite networks: the case of the World Trade Web
Saracco, Fabio; Gabrielli, Andrea; Squartini, Tiziano
2015-01-01
Within the last fifteen years, network theory has been successfully applied both to natural sciences and to socioeconomic disciplines. In particular, bipartite networks have been recognized to provide a particularly insightful representation of many systems, ranging from mutualistic networks in ecology to trade networks in economy, whence the need of a pattern detection-oriented analysis in order to identify statistically-significant structural properties. Such an analysis rests upon the definition of suitable null models, i.e. upon the choice of the portion of network structure to be preserved while randomizing everything else. However, quite surprisingly, little work has been done so far to define null models for real bipartite networks. The aim of the present work is to fill this gap, extending a recently-proposed method to randomize monopartite networks to bipartite networks. While the proposed formalism is perfectly general, we apply our method to the binary, undirected, bipartite representation of the W...
A degree condition for maximal cycles in bipartite digraphs
Adamus, Janusz
2011-01-01
We prove a sharp Ore-type criterion for hamiltonicity of balanced bipartite digraphs: A bipartite digraph D, with colour classes of cardinality N, is hamiltonian if, for every pair of vertices u and v from opposite colour classes of D such that the arc u->v is not in D, the sum of the positive half-degree of u and the negative half-degree of v is greater than or equal to N+2.
The 1992 4th NASA SERC Symposium on VLSI Design
Whitaker, Sterling R.
1992-01-01
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.
Interaction of algorithm and implementation for analog VLSI stereo vision
Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.
1991-07-01
Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.
Burnett, Scott E; Stojanowski, Christopher M; Mahakkanukrauh, Pasuk
2015-03-01
Carpal bone bipartition is a developmental variant resulting in the division of a normally singular carpal into two distinct segments. Cases involving the scaphoid are best known, though many other carpals can be affected, including the trapezoid. Six new examples of bipartite trapezoids, identified in African and Asian anatomical and archeological samples, are reported here and compared with the eight previously known. While the site of bipartition is consistent, the resulting segments exhibit variability in their articulations with neighboring carpals. Five of the six affected trapezoids were identified in African or African-derived samples, yielding a significantly higher frequency (0.323%) of bipartite trapezoid than seen in anatomical or archeological series of European origin. Bilateral bipartite trapezoids in archeological remains from the Mid Holocene site of Gobero (Niger) are potentially the oldest bipartite carpals yet identified in humans. Their discovery may indicate that trapezoid bipartition is a condition that has been present in African populations since prehistoric times, though more data are needed. Because bipartite carpals may be symptomatic and can occur as part of syndromes, the significant population variation in frequency identified here has potential utility in both anatomical and clinical contexts. However, a comparison of the morphological appearance of bipartite trapezoids with the suggested criteria for bipartite scaphoid diagnosis indicates that these criteria are not equally applicable to other carpals. Fortunately, due to the rarity of fracture, identification of the bipartite trapezoid and separating it from pathological conditions is considerably easier than diagnosing a bipartite scaphoid.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...
NASA Space Engineering Research Center for VLSI System Design
1993-01-01
This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.
Design and Verification of High-Speed VLSI Physical Design
Institute of Scientific and Technical Information of China (English)
Dian Zhou; Rui-Ming Li
2005-01-01
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.
Competition for popularity in bipartite networks
Beguerisse Díaz, Mariano; Porter, Mason A.; Onnela, Jukka-Pekka
2010-12-01
We present a dynamical model for rewiring and attachment in bipartite networks. Edges are placed between nodes that belong to catalogs that can either be fixed in size or growing in size. The model is motivated by an empirical study of data from the video rental service Netflix, which invites its users to give ratings to the videos available in its catalog. We find that the distribution of the number of ratings given by users and that of the number of ratings received by videos both follow a power law with an exponential cutoff. We also examine the activity patterns of Netflix users and find bursts of intense video-rating activity followed by long periods of inactivity. We derive ordinary differential equations to model the acquisition of edges by the nodes over time and obtain the corresponding time-dependent degree distributions. We then compare our results with the Netflix data and find good agreement. We conclude with a discussion of how catalog models can be used to study systems in which agents are forced to choose, rate, or prioritize their interactions from a large set of options.
Hot multiboundary wormholes from bipartite entanglement
Marolf, Donald; Maxfield, Henry; Peach, Alex; Ross, Simon
2015-11-01
We analyze the 1+1 CFT states dual to hot (time-symmetric) 2+1 multiboundary AdS wormholes. These are black hole geometries with high local temperature, n≥slant 1 asymptotically-AdS3 regions, and arbitrary internal topology. The dual state at t = 0 is defined on n circles. We show these to be well-described by sewing together tensor networks corresponding to thermofield double states. As a result, the entanglement is spatially localized and bipartite: away from particular boundary points (‘vertices’) any small connected region A of the boundary CFT is entangled only with another small connected region B, where B may lie on a different circle or may be a different part of the same circle. We focus on the pair-of-pants case, from which more general cases may be constructed. We also discuss finite-temperature corrections, where we note that the states involve a code subspace in each circle.
VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network
Directory of Open Access Journals (Sweden)
Mohd Asyraf Mansor
2016-09-01
Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.
VLSI Design of a Turbo Decoder
Fang, Wai-Chi
2007-01-01
A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.
Analog VLSI neural network integrated circuits
Kub, F. J.; Moon, K. K.; Just, E. A.
1991-01-01
Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.
Relaxation Based Electrical Simulation for VLSI Circuits
Directory of Open Access Journals (Sweden)
S. Rajkumar
2012-06-01
Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.
Multi-net optimization of VLSI interconnect
Moiseev, Konstantin; Wimer, Shmuel
2015-01-01
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...
PLA realizations for VLSI state machines
Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.
1990-01-01
A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.
Localization in random bipartite graphs: Numerical and empirical study
Slanina, František
2017-05-01
We investigate adjacency matrices of bipartite graphs with a power-law degree distribution. Motivation for this study is twofold: first, vibrational states in granular matter and jammed sphere packings; second, graphs encoding social interaction, especially electronic commerce. We establish the position of the mobility edge and show that it strongly depends on the power in the degree distribution and on the ratio of the sizes of the two parts of the bipartite graph. At the jamming threshold, where the two parts have the same size, localization vanishes. We found that the multifractal spectrum is nontrivial in the delocalized phase, but still near the mobility edge. We also study an empirical bipartite graph, namely, the Amazon reviewer-item network. We found that in this specific graph the mobility edge disappears, and we draw a conclusion from this fact regarding earlier empirical studies of the Amazon network.
Bipartite Consensus Control of Multiagent Systems on Coopetition Networks
Directory of Open Access Journals (Sweden)
Jiangping Hu
2014-01-01
Full Text Available Cooperation and competition are two typical interactional relationships in natural and engineering networked systems. Some complex behaviors can emerge through local interactions within the networked systems. This paper focuses on the coexistence of competition and cooperation (i.e., coopetition at the network level and, simultaneously, the collective dynamics on such coopetition networks. The coopetition network is represented by a directed signed graph. The collective dynamics on the coopetition network is described by a multiagent system. We investigate two bipartite consensus strategies for multiagent systems such that all the agents converge to a final state characterized by identical modulus but opposite sign. Under a weak connectivity assumption that the coopetition network has a spanning tree, some sufficient conditions are derived for bipartite consensus of multiagent systems with the help of a structural balance theory. Finally, simulation results are provided to demonstrate the bipartite consensus formation.
The management of the painful bipartite patella: a systematic review.
McMahon, Samuel E; LeRoux, Johannes A; Smith, Toby O; Hing, Caroline B
2016-09-01
This study aimed to identify the most effective method for the treatment of the symptomatic bipartite patella. A systematic review of the literature was completed, and all studies assessing the management of a bipartite patella were included. Owing to the paucity of randomised controlled trials, a narrative review of 22 studies was completed. A range of treatments were assessed: conservative measures, open and arthroscopic fixation or excision and soft tissue release and excision. All of the methods provided results ranging from good to excellent, with acceptable complication rates. This is a poorly answered treatment question. No firm guidance can be given as to the most appropriate method of treating the symptomatic bipartite patella. This study suggests that there are a number of effective treatments with acceptable complication rates and it may be that treatments that conserve the patella are more appropriate for larger fragments. IV.
Two classes of bipartite networks: nested biological and social systems.
Burgos, Enrique; Ceva, Horacio; Hernández, Laura; Perazzo, R P J; Devoto, Mariano; Medan, Diego
2008-10-01
Bipartite graphs have received some attention in the study of social networks and of biological mutualistic systems. A generalization of a previous model is presented, that evolves the topology of the graph in order to optimally account for a given contact preference rule between the two guilds of the network. As a result, social and biological graphs are classified as belonging to two clearly different classes. Projected graphs, linking the agents of only one guild, are obtained from the original bipartite graph. The corresponding evolution of its statistical properties is also studied. An example of a biological mutualistic network is analyzed in detail, and it is found that the model provides a very good fitting of all the main statistical features. The model also provides a proper qualitative description of the same features observed in social webs, suggesting the possible reasons underlying the difference in the organization of these two kinds of bipartite networks.
Non-bipartite Graphs with Third Largest Laplacian Eigenvalue Less Than Three
Institute of Scientific and Technical Information of China (English)
Xiao Dong ZHANG; Rong LUO
2006-01-01
All bipartite graphs whose third largest Laplacian eigenvalue is less than 3 have been characterized by Zhang. In this paper, all connected non-bipartite graphs with third largest Laplacian eigenvalue less than three are determined.
Bipartite Fuzzy Stochastic Differential Equations with Global Lipschitz Condition
Directory of Open Access Journals (Sweden)
Marek T. Malinowski
2016-01-01
Full Text Available We introduce and analyze a new type of fuzzy stochastic differential equations. We consider equations with drift and diffusion terms occurring at both sides of equations. Therefore we call them the bipartite fuzzy stochastic differential equations. Under the Lipschitz and boundedness conditions imposed on drifts and diffusions coefficients we prove existence of a unique solution. Then, insensitivity of the solution under small changes of data of equation is examined. Finally, we mention that all results can be repeated for solutions to bipartite set-valued stochastic differential equations.
Bipartition Polynomials, the Ising Model, and Domination in Graphs
Directory of Open Access Journals (Sweden)
Dod Markus
2015-05-01
Full Text Available This paper introduces a trivariate graph polynomial that is a common generalization of the domination polynomial, the Ising polynomial, the matching polynomial, and the cut polynomial of a graph. This new graph polynomial, called the bipartition polynomial, permits a variety of interesting representations, for instance as a sum ranging over all spanning forests. As a consequence, the bipartition polynomial is a powerful tool for proving properties of other graph polynomials and graph invariants. We apply this approach to show that, analogously to the Tutte polynomial, the Ising polynomial introduced by Andrén and Markström in [3], can be represented as a sum over spanning forests.
MINIMUM CONGESTION SPANNING TREES IN BIPARTITE AND RANDOM GRAPHS
Institute of Scientific and Technical Information of China (English)
M.L Ostrovskii
2011-01-01
The first problem considered in this article reads: is it possible to find upper estimates for the spanning tree congestion in bipartite graphs, which are better than those for general graphs? It is proved that there exists a bipartite version of the known graph with spanning tree congestion of order n3/2, where n is the number of vertices. The second problem is to estimate spanning tree congestion of random graphs. It is proved that the standard model of random graphs cannot be used to find graphs whose spanning tree congestion has order greater than n3/2.
VLSI digital demodulator co-processor
Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.
A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.
VLSI micro- and nanophotonics science, technology, and applications
Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati
2011-01-01
Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe
A radial basis function neurocomputer implemented with analog VLSI circuits
Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul
1992-01-01
An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.
NASA Space Engineering Research Center for VLSI systems design
1991-01-01
This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.
Handbook of VLSI chip design and expert systems
Schwarz, A F
1993-01-01
Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.
AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT
Directory of Open Access Journals (Sweden)
Y. Y. Lankevich
2015-01-01
Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.
Purification and correlated measurements of bipartite mixed states
Bouda, J; Bouda, Jan; Buzek, Vladimir
2001-01-01
We prove that all purifications of a non-factorable state (i.e., the state which cannot be expressed in a form $\\rho_{AB}=\\rho_A\\otimes\\rho_B$) are entangled. We also show that for any bipartite state there exists a pair of measurements which are correlated on this state if and only if the state is non-factorable.
Quantum Correlations Relativity for Continuous-Variables Bipartite Systems
Dugic, M; Jeknic-Dugic, J
2011-01-01
Based on the so-called Entanglement Relativity, we point out relativity of the more general non-classical (quantum) correlations for the continuous-variables bipartite systems. Our observation points out that quantum processing resources based on the non-classical correlations (non-zero quantum discord) are ubiquitous in such systems.
Virus spread in complete bi-partite graphs
Omic, J.S.; Kooij, R.E.; Mieghem, P. van
2007-01-01
In this paper we study the spread of viruses on the complete bi-partite graph Km,n. Using mean field theory we first show that the epidemic threshold for this type of graph satifies Tc = 1/√MN, hence, confirming previous results from literature. Next, we find an expression for the average number of
Optimal values of bipartite entanglement in a tripartite system
Energy Technology Data Exchange (ETDEWEB)
Sahoo, Shaon, E-mail: shaon.sahoo@gmail.com [Department of Physics, Indian Institute of Science, Bangalore 560012 (India); Solid State and Structural Chemistry Unit, Indian Institute of Science, Bangalore 560012 (India)
2015-01-23
For a general tripartite system in some pure state, an observer possessing any two parts will see them in a mixed state. By the consequence of Hughston–Jozsa–Wootters theorem, each basis set of local measurement on the third part will correspond to a particular decomposition of the bipartite mixed state into a weighted sum of pure states. It is possible to associate an average bipartite entanglement (S{sup ¯}) with each of these decompositions. The maximum value of S{sup ¯} is called the entanglement of assistance (E{sub A}) while the minimum value is called the entanglement of formation (E{sub F}). An appropriate choice of the basis set of local measurement will correspond to an optimal value of S{sup ¯}; we find here a generic optimality condition for the choice of the basis set. In the present context, we analyze the tripartite states W and GHZ and show how they are fundamentally different. - Highlights: • We study optimal values of bipartite entanglement in a tripartite system. • Using the Hughston–Jozsa–Wootters theorem, an optimality condition is derived. • This condition will help us study mixed bipartite states using ancilla.
Virus spread in complete bi-partite graphs
Omic, J.S.; Kooij, R.E.; Mieghem, P. van
2007-01-01
In this paper we study the spread of viruses on the complete bi-partite graph Km,n. Using mean field theory we first show that the epidemic threshold for this type of graph satifies Tc = 1/√MN, hence, confirming previous results from literature. Next, we find an expression for the average number of
Schur complements of matrices with acyclic bipartite graphs
DEFF Research Database (Denmark)
Britz, Thomas Johann; Olesky, D.D.; van den Driessche, P.
2005-01-01
Bipartite graphs are used to describe the generalized Schur complements of real matrices having nos quare submatrix with two or more nonzero diagonals. For any matrix A with this property, including any nearly reducible matrix, the sign pattern of each generalized Schur complement is shown to be ...
Directory of Open Access Journals (Sweden)
Geraldine H. Chang
2014-01-01
Full Text Available Objective. To present a unique case report of a Lisfranc fracture in a patient with a bipartite medial cuneiform and to evaluate the prevalence of the bipartite medial cuneiform in a retrospective review of 1000 magnetic resonance (MR imaging studies of the foot. Materials and Methods. Case report followed by a retrospective review of 1000 MR imaging studies of the foot for the presence or absence of a bipartite medial cuneiform. Results. The incidence of the bipartite medial cuneiform is 0.1%. Conclusion. A bipartite medial cuneiform is a rare finding but one with both clinical and surgical implications.
CMOS VLSI Layout and Verification of a SIMD Computer
Zheng, Jianqing
1996-01-01
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
An efficient interpolation filter VLSI architecture for HEVC standard
Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang
2015-12-01
The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.
A special purpose silicon compiler for designing supercomputing VLSI systems
Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.
1991-01-01
Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
刘彦佩
2001-01-01
This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.
Artificial immune system algorithm in VLSI circuit configuration
Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd
2017-08-01
In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.
Hybrid VLSI/QCA Architecture for Computing FFTs
Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew
2003-01-01
A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.
Tungsten and other refractory metals for VLSI applications II
Energy Technology Data Exchange (ETDEWEB)
Broadbent, E.K.
1987-01-01
This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.
An Interactive Multimedia Learning Environment for VLSI Built with COSMOS
Angelides, Marios C.; Agius, Harry W.
2002-01-01
This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…
Sports injury to a bipartite medial cuneiform in a child.
Eves, Timothy B; Ahmad, Mudussar A; Oddy, Michael J
2014-01-01
We report the case of an 11-year-old boy who had sustained a soccer injury to his mid-foot. Plain radiography did not reveal any fracture to account for the severity of his symptoms or his inability to bear weight. Magnetic resonance imaging was undertaken and demonstrated the medial cuneiform to be a bipartite bone consisting of 2 ossicles connected by a synchondrosis. No acute fracture or diastasis of the bipartite bone was demonstrated; however, significant bone marrow edema was noted, corresponding to the site of the injury and his clinical point bony tenderness. This anatomic variant should be considered as a rare differential diagnosis in the skeletally immature foot. The injury was treated nonoperatively with a non-weightbearing cast and pneumatic walker immobilization, with successful resolution of his symptoms and a return to sports activity by 4 months after injury.
SCORE LISTS IN (h, k)-BIPARTITE HYPERTOURNAMENTS
Institute of Scientific and Technical Information of China (English)
无
2007-01-01
Given non-negative integers m,n,h and k with m ≥ h ＞ 1 and n ≥ k ＞ 1, an (h, k)-bipartite hypertournament on m + n vertices is a triple (U, V, A), where U and V are two sets of vertices with |U| = m and |V| = n, and A is a set of (h + k)-tuples of vertices,called arcs, with at most h vertices from U and at most k vertices from V, such that for any h + k subsets U1 ∪ V1 of U ∪ V, A contains exactly one of the (h + k)! (h + k)-tuples whose entries belong to U1 ∪ V1. Necessary and sufficient conditions for a pair of non-decreasing sequences of non-negative integers to be the losing score lists or score lists of some(h, k)-bipartite hypertournament are obtained.
Analysis of ground state in random bipartite matching
Shi, Gui-Yuan; Liao, Hao; Zhang, Yi-Cheng
2015-01-01
In human society, a lot of social phenomena can be concluded into a mathematical problem called the bipartite matching, one of the most well known model is the marriage problem proposed by Gale and Shapley. In this article, we try to find out some intrinsic properties of the ground state of this model and thus gain more insights and ideas about the matching problem. We apply Kuhn-Munkres Algorithm to find out the numerical ground state solution of the system. The simulation result proves the previous theoretical analysis using replica method. In the result, we also find out the amount of blocking pairs which can be regarded as a representative of the system stability. Furthermore, we discover that the connectivity in the bipartite matching problem has a great impact on the stability of the ground state, and the system will become more unstable if there were more connections between men and women.
An MDL approach to efficiently discover communities in bipartite network
Institute of Scientific and Technical Information of China (English)
徐开阔; 曾春秋; 元昌安; 李川; 唐常杰
2014-01-01
An minimum description length (MDL) criterion is proposed to choose a good partition for a bipartite network. A heuristic algorithm based on combination theory is presented to approach the optimal partition. As the heuristic algorithm automatically searches for the number of partitions, no user intervention is required. Finally, experiments are conducted on various datasets, and the results show that our method generates higher quality results than the state-of-art methods, cross-association and bipartite, recursively induced modules. Experiment results also show the good scalability of the proposed algorithm. The method is applied to traditional Chinese medicine (TCM) formula and Chinese herbal network whose community structure is not well known, and found that it detects significant and it is informative community division.
Emergent bipartiteness in a society of knights and knaves
Del Genio, Charo I
2011-01-01
We propose a simple model of a social network based on so-called knights-and-knaves puzzles. The model describes the formation of networks between two classes of agents where links are formed by agents introducing their neighbors to others of their own class. We show that if the proportion of knights and knaves is within a certain range, the network self-organizes to a perfectly bipartite state. However, if the excess of one of the two classes is greater than a threshold value, bipartiteness is not observed. We offer a detailed theoretical analysis for the behaviour of the model, investigate its behavior in the thermodynamic limit, and argue that it provides a simple example of a topology-driven model whose behaviour is strongly reminiscent of a first-order phase transitions far from equilibrium.
Mixed-integer vertex covers on bipartite graphs
Gerards, A.M.H.; Conforti, M.; Zambelli, G.; Fischetti, M.; Williamson, D.P.
2007-01-01
Let $A$ be the edge-node incidence matrix of a bipartite graph $G = (U, V ; E)$, $I$ be a subset of the nodes of $G$, and $b$ be a vector such that $2b$ is integral. We consider the following mixed-integer set: $X(G, b, I) = {x : Ax ≥ b, x ≥ 0, x_i$ integer for all $i ∈ I}$
Correlation/Communication complexity of generating bipartite states
Jain, Rahul; Shi, Yaoyun; Wei, Zhaohui; Zhang, Shengyu
2012-01-01
We study the correlation complexity (or equivalently, the communication complexity) of generating a bipartite quantum state $\\rho$. When $\\rho$ is a pure state, we completely characterize the complexity for approximately generating $\\rho$ by a corresponding approximate rank, closing a gap left in Ambainis, Schulman, Ta-Shma, Vazirani and Wigderson (SIAM Journal on Computing, 32(6):1570-1585, 2003). When $\\rho$ is a classical distribution $P(x,y)$, we tightly characterize the complexity of gen...
Classicality from zero discord for continuous-variables bipartite systems
Arsenijevic, M; Dugic, M
2012-01-01
Quantum information resources quantified by non-zero discord are ubiquitous for the continuous-variables bipartite systems. Complementary to this, we investigate the zero-discord-defined classicality for the different structures (decompositions into subsystems) of such systems. We point out complexity and subtlety of the task and we construct a model-structure closely resembling the classical systems not supporting quantum information processing.
Degree of Entanglement for Some Bipartite Entangled Bosonic Systems
Institute of Scientific and Technical Information of China (English)
LIANG Xian-Ting
2004-01-01
We calculate the degree of entanglement for some bipartite entangled states of continuous variables.These states include common two-mode squeezed vacuum state, thermal vacuum state of a free single particle (where the fictitious tilde system is regarded as another particle), and the squeezed vacuum state of two coupling harmonic oscillators.The degree of entanglement for these quantum systems are shown clearly by using the technique of integration within an ordered product of operators.
Exact fluctuation-entanglement relation for bipartite pure states
Villaruel, Aura Mae B
2015-01-01
We identify a subsystem fluctuation (variance) that measures entanglement in an arbitrary bipartite pure state. This fluctuation is of an observable that generalizes the notion of polarization to an arbitrary N-level subsystem. We express this polarization fluctuation in terms of the order-2 Renyi entanglement entropy and a generalized concurrence. The fluctuation-entanglement relation presented here establishes a framework for experimentally measuring entanglement using Stern-Gerlach-type state selectors.
Complexity of Products of Some Complete and Complete Bipartite Graphs
Directory of Open Access Journals (Sweden)
S. N. Daoud
2013-01-01
Full Text Available The number of spanning trees in graphs (networks is an important invariant; it is also an important measure of reliability of a network. In this paper, we derive simple formulas of the complexity, number of spanning trees, of products of some complete and complete bipartite graphs such as cartesian product, normal product, composition product, tensor product, and symmetric product, using linear algebra and matrix analysis techniques.
Sequential scheme for locally discriminating bipartite unitary operations without inverses
Li, Lvzhou
2017-08-01
Local distinguishability of bipartite unitary operations has recently received much attention. A nontrivial and interesting question concerning this subject is whether there is a sequential scheme for locally discriminating between two bipartite unitary operations, because a sequential scheme usually represents the most economic strategy for discrimination. An affirmative answer to this question was given in the literature, however with two limitations: (i) the unitary operations to be discriminated were limited to act on d ⊗d , i.e., a two-qudit system, and (ii) the inverses of the unitary operations were assumed to be accessible, although this assumption may be unrealizable in experiment. In this paper, we improve the result by removing the two limitations. Specifically, we show that any two bipartite unitary operations acting on dA⊗dB can be locally discriminated by a sequential scheme, without using the inverses of the unitary operations. Therefore, this paper enhances the applicability and feasibility of the sequential scheme for locally discriminating unitary operations.
Implementation of bipartite or remote unitary gates with repeater nodes
Yu, Li; Nemoto, Kae
2016-08-01
We propose some protocols to implement various classes of bipartite unitary operations on two remote parties with the help of repeater nodes in-between. We also present a protocol to implement a single-qubit unitary with parameters determined by a remote party with the help of up to three repeater nodes. It is assumed that the neighboring nodes are connected by noisy photonic channels, and the local gates can be performed quite accurately, while the decoherence of memories is significant. A unitary is often a part of a larger computation or communication task in a quantum network, and to reduce the amount of decoherence in other systems of the network, we focus on the goal of saving the total time for implementing a unitary including the time for entanglement preparation. We review some previously studied protocols that implement bipartite unitaries using local operations and classical communication and prior shared entanglement, and apply them to the situation with repeater nodes without prior entanglement. We find that the protocols using piecewise entanglement between neighboring nodes often require less total time compared to preparing entanglement between the two end nodes first and then performing the previously known protocols. For a generic bipartite unitary, as the number of repeater nodes increases, the total time could approach the time cost for direct signal transfer from one end node to the other. We also prove some lower bounds of the total time when there are a small number of repeater nodes. The application to position-based cryptography is discussed.
Finding All Allowed Edges in a Bipartite Graph
Tassa, Tamir
2011-01-01
We consider the problem of finding all allowed edges in a bipartite graph $G=(V,E)$, i.e., all edges that are included in some maximum matching. We show that given any maximum matching in the graph, it is possible to perform this computation in linear time $O(n+m)$ (where $n=|V|$ and $m=|E|$). Hence, the time complexity of finding all allowed edges reduces to that of finding a single maximum matching, which is $O(n^{1/2}m)$ [Hopcroft and Karp 1973], or $O((n/\\log n)^{1/2}m)$ for dense graphs with $m=\\Theta(n^2)$ [Alt et al. 1991]. This time complexity improves upon that of the best known algorithms for the problem, which is $O(nm)$ ([Costa 1994] for bipartite graphs, and [Carvalho and Cheriyan 2005] for general graphs). Other algorithms for solving that problem are randomized algorithms due to [Rabin and Vazirani 1989] and [Cheriyan 1997], the runtime of which is $\\tilde{O}(n^{2.376})$. Our algorithm, apart from being deterministic, improves upon that time complexity for bipartite graphs when $m=O(n^r)$ and $...
Bipartite-Oriented Distributed Graph Partitioning for Big Learning
Institute of Scientific and Technical Information of China (English)
陈榕; 陈海波; 臧斌宇; 施佳鑫
2015-01-01
Many machine learning and data mining (MLDM) problems like recommendation, topic modeling, and medical diagnosis can be modeled as computing on bipartite graphs. However, most distributed graph-parallel systems are oblivious to the unique characteristics in such graphs and existing online graph partitioning algorithms usually cause excessive repli-cation of vertices as well as significant pressure on network communication. This article identifies the challenges and oppor-tunities of partitioning bipartite graphs for distributed MLDM processing and proposes BiGraph, a set of bipartite-oriented graph partitioning algorithms. BiGraph leverages observations such as the skewed distribution of vertices, discriminated computation load and imbalanced data sizes between the two subsets of vertices to derive a set of optimal graph partition-ing algorithms that result in minimal vertex replication and network communication. BiGraph has been implemented on PowerGraph and is shown to have a performance boost up to 17.75X (from 1.16X) for four typical MLDM algorithms, due to reducing up to 80%vertex replication, and up to 96%network traﬃc.
THE MAXIMUM AND MINIMUM DEGREES OF RANDOM BIPARTITE MULTIGRAPHS
Institute of Scientific and Technical Information of China (English)
Chen Ailian; Zhang Fuji; Li Hao
2011-01-01
In this paper the authors generalize the classic random bipartite graph model, and define a model of the random bipartite multigraphs as follows: let m=m(n) be a positive integer-valued function on n and (n, m; {pk}) the probability space consisting of all the labeled bipartite multigraphs with two vertex sets A={a1,a2,...,an} and B= {b1, b2,..., bm}, in which the numbers taibj of the edges between any two vertices ai∈A and bj∈B are identically distributed independent random variables with distribution P{taibj}=k}=pk, k=0, 1, 2,..., where pk≥0 and ∑ pk=1. They obtain that Xc,d,A, the number of vertices in A with degree between c and d of Gn,m∈ (n, m;{Pk}) has asymptotically Poisson distribution, and answer the following two questions about the space (n,m; {pk}) with {pk} having geometric distribution, binomial distribution and Poisson distribution, respectively. Under which condition for {Pk} can there be a function D(n) such that almost every random multigraph Gnm∈ (n, m; {pk}) has maximum degree D(n) in A? under which condition for {pk} has almost every multigraph Gn,m∈ (n,m;{pk}) a unique vertex of maximum degree in A?
Toward edge minability for role mining in bipartite networks
Dong, Lijun; Wang, Yi; Liu, Ran; Pi, Benjie; Wu, Liuyi
2016-11-01
Bipartite network models have been extensively used in information security to automatically generate role-based access control (RBAC) from dataset. This process is called role mining. However, not all the topologies of bipartite networks are suitable for role mining; some edges may even reduce the quality of role mining. This causes unnecessary time consumption as role mining is NP-hard. Therefore, to promote the quality of role mining results, the capability that an edge composes roles with other edges, called the minability of edge, needs to be identified. We tackle the problem from an angle of edge importance in complex networks; that is an edge easily covered by roles is considered to be more important. Based on this idea, the k-shell decomposition of complex networks is extended to reveal the different minability of edges. By this way, a bipartite network can be quickly purified by excluding the low-minability edges from role mining, and thus the quality of role mining can be effectively improved. Extensive experiments via the real-world datasets are conducted to confirm the above claims.
Maximum Bipartite Matching Size And Application to Cuckoo Hashing
Kanizo, Yossi; Keslassy, Isaac
2010-01-01
Cuckoo hashing with a stash is a robust high-performance hashing scheme that can be used in many real-life applications. It complements cuckoo hashing by adding a small stash storing the elements that cannot fit into the main hash table due to collisions. However, the exact required size of the stash and the tradeoff between its size and the memory over-provisioning of the hash table are still unknown. We settle this question by investigating the equivalent maximum matching size of a random bipartite graph, with a constant left-side vertex degree $d=2$. Specifically, we provide an exact expression for the expected maximum matching size and show that its actual size is close to its mean, with high probability. This result relies on decomposing the bipartite graph into connected components, and then separately evaluating the distribution of the matching size in each of these components. In particular, we provide an exact expression for any finite bipartite graph size and also deduce asymptotic results as the nu...
Grand canonical validation of the bipartite international trade network
Straka, Mika J.; Caldarelli, Guido; Saracco, Fabio
2017-08-01
Devising strategies for economic development in a globally competitive landscape requires a solid and unbiased understanding of countries' technological advancements and similarities among export products. Both can be addressed through the bipartite representation of the International Trade Network. In this paper, we apply the recently proposed grand canonical projection algorithm to uncover country and product communities. Contrary to past endeavors, our methodology, based on information theory, creates monopartite projections in an unbiased and analytically tractable way. Single links between countries or products represent statistically significant signals, which are not accounted for by null models such as the bipartite configuration model. We find stable country communities reflecting the socioeconomic distinction in developed, newly industrialized, and developing countries. Furthermore, we observe product clusters based on the aforementioned country groups. Our analysis reveals the existence of a complicated structure in the bipartite International Trade Network: apart from the diversification of export baskets from the most basic to the most exclusive products, we observe a statistically significant signal of an export specialization mechanism towards more sophisticated products.
Data mechanics and coupling geometry on binary bipartite networks.
Directory of Open Access Journals (Sweden)
Hsieh Fushing
Full Text Available We quantify the notion of pattern and formalize the process of pattern discovery under the framework of binary bipartite networks. Patterns of particular focus are interrelated global interactions between clusters on its row and column axes. A binary bipartite network is built into a thermodynamic system embracing all up-and-down spin configurations defined by product-permutations on rows and columns. This system is equipped with its ferromagnetic energy ground state under Ising model potential. Such a ground state, also called a macrostate, is postulated to congregate all patterns of interest embedded within the network data in a multiscale fashion. A new computing paradigm for indirect searching for such a macrostate, called Data Mechanics, is devised by iteratively building a surrogate geometric system with a pair of nearly optimal marginal ultrametrics on row and column spaces. The coupling measure minimizing the Gromov-Wasserstein distance of these two marginal geometries is also seen to be in the vicinity of the macrostate. This resultant coupling geometry reveals multiscale block pattern information that characterizes multiple layers of interacting relationships between clusters on row and on column axes. It is the nonparametric information content of a binary bipartite network. This coupling geometry is then demonstrated to shed new light and bring resolution to interaction issues in community ecology and in gene-content-based phylogenetics. Its implied global inferences are expected to have high potential in many scientific areas.
Bipartite Diametrical Graphs of Diameter 4 and Extreme Orders
Directory of Open Access Journals (Sweden)
Salah Al-Addasi
2008-01-01
in which this upper bound is attained, this graph can be viewed as a generalization of the Rhombic Dodecahedron. Then we show that for any ≥2, the graph (2,2 is the unique (up to isomorphism bipartite diametrical graph of diameter 4 and partite sets of cardinalities 2 and 2, and hence in particular, for =3, the graph (6,8 which is just the Rhombic Dodecahedron is the unique (up to isomorphism bipartite diametrical graph of such a diameter and cardinalities of partite sets. Thus we complete a characterization of -graphs of diameter 4 and cardinality of the smaller partite set not exceeding 6. We prove that the neighborhoods of vertices of the larger partite set of (2,2 form a matroid whose basis graph is the hypercube . We prove that any -graph of diameter 4 is bipartite self complementary, thus in particular (2,2. Finally, we study some additional properties of (2,2 concerning the order of its automorphism group, girth, domination number, and when being Eulerian.
Advanced symbolic analysis for VLSI systems methods and applications
Shi, Guoyong; Tlelo Cuautle, Esteban
2014-01-01
This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Directory of Open Access Journals (Sweden)
Chávez-Bracamontes Ramón
2015-07-01
Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding
VLSI physical design analyzer: A profiling and data mining tool
Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi
2015-03-01
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Embedded Processor Based Automatic Temperature Control of VLSI Chips
Directory of Open Access Journals (Sweden)
Narasimha Murthy Yayavaram
2009-01-01
Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.
A novel 3D algorithm for VLSI floorplanning
Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira
2013-01-01
3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.
VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION
Directory of Open Access Journals (Sweden)
John Moses C
2014-05-01
Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.
VLSI design for fault-dictionary based testability
Miller, Charles D.
The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.
Opto-VLSI-based tunable single-mode fiber laser.
Xiao, Feng; Alameh, Kamal; Lee, Tongtak
2009-10-12
A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.
VLSI neural system architecture for finite ring recursive reduction.
Zhang, D; Jullien, G A
1996-12-01
The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.
Trace-based post-silicon validation for VLSI circuits
Liu, Xiao
2014-01-01
This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...
A systematic method for configuring VLSI networks of spiking neurons.
Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney
2011-10-01
An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.
Opto-VLSI-based N × M wavelength selective switch.
Xiao, Feng; Alameh, Kamal
2013-07-29
In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.
Digital VLSI algorithms and architectures for support vector machines.
Anguita, D; Boni, A; Ridella, S
2000-06-01
In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.
VLSI circuits for bidirectional interface to peripheral and visceral nerves.
Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V
2015-08-01
This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel
2015-01-01
This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
2011-01-01
Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...
Design of a VLSI Decoder for Partially Structured LDPC Codes
Directory of Open Access Journals (Sweden)
Fabrizio Vacca
2008-01-01
of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.
Diseño digital : una perspectiva VLSI-CMOS
Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel
1996-01-01
Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
Experimental Demonstration of Largeness in Bipartite Entanglement Sudden Death
Institute of Scientific and Technical Information of China (English)
PENG Liang; HUANG Yun-Feng; LI Li; LIU Bi-Heng; LI Chuan-Feng; GUO Guang-Can
2011-01-01
Quantum coherence is the most distinct feature of quantum mechanics.However,inevitable decoherence processes will finlly destroy it and make the"Schr(o)dinger's cat" invisible in our classical world. In this "quantumto-classical transition",the so-called "largeness" plays a critical role. We experimentally study the largeness phenomena in the bipartite entanglement decay process through a depolarizing channel with two-photon entangled states generated from a spontaneous parametric down-conversion source.Our experiment demonstrates how the speed of entanglement decay and the time when "entanglement sudden death" happens depend on the size of the system exposed to the environment noise.
Correlation/Communication complexity of generating bipartite states
Jain, Rahul; Wei, Zhaohui; Zhang, Shengyu
2012-01-01
We study the correlation complexity (or equivalently, the communication complexity) of generating a bipartite quantum state $\\rho$. When $\\rho$ is a pure state, we completely characterize the complexity for approximately generating $\\rho$ by a corresponding approximate rank, closing a gap left in Ambainis, Schulman, Ta-Shma, Vazirani and Wigderson (SIAM Journal on Computing, 32(6):1570-1585, 2003). When $\\rho$ is a classical distribution $P(x,y)$, we tightly characterize the complexity of generating $P$ by the psd-rank, a measure recently proposed by Fiorini, Massar, Pokutta, Tiwary and de Wolf (STOC 2012). We also present a characterization of the complexity of generating a general quantum state $\\rho$.
Entanglement-fluctuation relation for bipartite pure states
Villaruel, Aura Mae B.; Paraan, Francis N. C.
2016-08-01
We identify subsystem fluctuations (variances) that measure entanglement in an arbitrary bipartite pure state. These fluctuations are of observables that generalize the notion of polarization to an arbitrary N -level subsystem. We express this polarization fluctuation in terms of subsystem purity and other entanglement measures. The derived entanglement-fluctuation relation is evaluated for the ground states of a one-dimensional free-fermion gas and the Affleck-Kennedy-Lieb-Tasaki spin chain. Our results provide a framework for experimentally measuring entanglement using Stern-Gerlach-type state selectors.
Bipartite opinion forming: Towards consensus over coopetition networks
Hou, Bo; Chen, Yao; Liu, Guangbin; Sun, Fuchun; Li, Hongbo
2015-12-01
Within the framework of signed graph and multi-agent systems, this paper investigates the distributed bipartite opinion forming problem over coopetition networks. Several sufficient algebraic and geometric topology conditions that guarantee consensus, regardless of the magnitudes of individual coupling strengths among the agents, have been derived by exploring the interaction direction patterns. All the criteria presented do not require the global knowledge of the coupling weights of the entire network, and thus are easier to check. The effectiveness of the theoretical results are illustrated by numerical examples.
Influence of Bipartite Qubit Coupling on Geometric Phase
Institute of Scientific and Technical Information of China (English)
XING Lei; LIANG Mai-Lin
2006-01-01
The geometric phase of the bipartite Heisenberg spin-1/2 system with one spin driven by rotating magnetic field is investigated. It is found that in the one-site drive case, the intersubsystem coupling can be equivalent to a static quasi-magnetic field in the parameter space. This perspective has satisfactorily explained the irregular asymptote effect of geometric phase. We discuss the property of the two-site magnetic drive spin system and discover that a stationary state with no geometric phase shift is generated.
Magnetic resonance imaging features of asymptomatic bipartite patella
Energy Technology Data Exchange (ETDEWEB)
O' Brien, J., E-mail: juliemobrien@gmail.com [Department of Radiology, Adelaide and Meath Incorporating National Children' s Hospital, Tallaght, Dublin 24 (Ireland); Murphy, C.; Halpenny, D.; McNeill, G.; Torreggiani, W.C. [Department of Radiology, Adelaide and Meath Incorporating National Children' s Hospital, Tallaght, Dublin 24 (Ireland)
2011-06-15
Objective: The purpose of our study was to describe the magnetic resonance imaging (MRI) features of bipartite patella in asymptomatic patients. Materials and methods: The study was prospective in type and performed following institutional ethical committees approval. In total, 25 subjects were recruited into the study and informed consent obtained in each case. The local radiology database was utilised in conjunction with a clinical questionnaire to identify patients who had asymptomatic bipartite patella. Any patient with a history of trauma or symptomatic disease was excluded from the study. MRI imaging was performed in each case on a 1.5 T system using a dedicated knee coil and a standardised knee protocol. The images obtained were then analysed by two musculoskeletal radiologists in consensus. Results: Of the 25 subjects, there were 8 females and 17 males. The mean age was 34.6 years. All but one of the bipartite fragments were located on the superolateral aspect of the patella. In 23 cases, one fragment was identified. The average transverse diameter of the fragment was 12.8 mm. The average distance between the fragment and the adjacent patella in the axial plane was 1.46 mm. In addition, the cartilage overlying the patella and accessory fragment was intact in all cases. The average thickness of the patella cartilage at its border to the fragment was 2.4 mm with an average ratio of the cartilage thickness of the fragment as compared with the cartilage thickness of the patella of 0.72. There was no evidence of high signal or bone marrow oedema on fluid sensitive sequences within either the patella or the fragment in any of the patients. Fluid was identified in the cleft between the patella and the fragment in the majority of cases. Conclusions: Asymptomatic bipartite patella is characterised by intact but thinned cartilage along the border between the patella and the fragment, fluid between the cleft and a lack of any bone marrow oedema or high signal within
Discord as a quantum resource for bi-partite communication
Energy Technology Data Exchange (ETDEWEB)
Chrzanowski, Helen M.; Assad, Syed M.; Symul, Thomas; Lam, Ping Koy [Centre for Quantum Computation and Communication Technology, Department of Quantum Science, The Australian National University (Australia); Gu, Mile; Modi, Kavan; Vedral, Vlatko [Centre for Quantum Technologies, National University of Singapore (Singapore); Ralph, Timothy C. [Centre for Quantum Computation and Communication Technology, Department of Physics, University of Queensland (Australia)
2014-12-04
Coherent interactions that generate negligible entanglement can still exhibit unique quantum behaviour. This observation has motivated a search beyond entanglement for a complete description of all quantum correlations. Quantum discord is a promising candidate. Here, we experimentally demonstrate that under certain measurement constraints, discord between bipartite systems can be consumed to encode information that can only be accessed by coherent quantum interactions. The inability to access this information by any other means allows us to use discord to directly quantify this ‘quantum advantage’.
Optimal two qubit gate for generation of random bipartite entanglement
Znidaric, M
2007-01-01
We study protocols for generation of random pure states consisting of repeated applications of two qubit transformations. Necessary number of steps needed in order to generate states displaying bipartite entanglement typical of random states is obtained. We also find the optimal two qubit gate for which the convergence is the fastest. Perhaps surprisingly, applying the same good two qubit gate in addition to a random single qubit rotations at each step leads to a faster generation of entanglement than applying a random two qubit transformation at each step.
VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.
1983-10-01
34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being
Co-clustering Analysis of Weblogs Using Bipartite Spectral Projection Approach
DEFF Research Database (Denmark)
Xu, Guandong; Zong, Yu; Dolog, Peter
2010-01-01
and content preference simultaneously. In this paper we will present an algorithm using bipartite spectral clustering to co-cluster Web users and pages. The usage data of users visiting Web sites is modeled as a bipartite graph and the spectral clustering is then applied to the graph representation of usage...
Excision of Painful Bipartite Patella: Good Long-term Outcome in Young Adults
Parviainen, Mickael; Pihlajamäki, Harri K.
2008-01-01
Excision of the accessory bipartite fragment is widely used, but its long-term outcome is not known. We evaluated the outcome after surgical excision of a symptomatic accessory bipartite or multipartite patella fragment in young adult men performing their compulsory military service and determined the incidence of painful bipartite patellae in this group of skeletally mature adults. We followed 25 of 32 patients for a minimum of 10 years (mean, 15 years; range, 10–22 years). The incidence of painful, surgically treated bipartite patella was 9.2 per 100,000 recruits. Patients’ median age at surgery was 20 years. There were 19 superolateral and six lateral bipartite fragments. Other radiographic findings were rare. At followup, the Kujala score mean was 95 points (range, 75–100 points), and osteoarthrotic changes (Kellgren-Lawrence Grade 1) were seen in two knees. No reoperations related to bipartite patella occurred during the followup. Symptomatic bipartite patella is rare and does not seem primarily associated with anatomic deviations, but when incapacitating pain persists despite nonoperative treatment, surgical excision seems to yield reasonable functional outcome and quick recovery with no apparent adverse sequelae. Our data suggest there is no reason to avoid this technically undemanding procedure for treating persistent symptoms of bipartite patella in young adults. Level of Evidence: Level IV, therapeutic study. See the Guidelines for Authors for a complete description of levels of evidence. PMID:18607662
A Family of Bipartite |Cardinality Matching Problems Solvable in O(n\\^2) Time
DEFF Research Database (Denmark)
Clausen, Jens; Krarup, J.
1995-01-01
For a given, unweighted bipartite graph G with 2n non isolated vertices, we consider the so called bipartite cardinality matching problem (BCMP) for which the time complexity of the fastest exact algorithm available is O(n/sup 5/2/ ). We devise a greedy algorithm which either finds a perfect matc...
Mutually Unbiased Maximally Entangled Bases for the Bipartite System Cd⊗ C^{dk}
Nan, Hua; Tao, Yuan-Hong; Wang, Tian-Jiao; Zhang, Jun
2016-10-01
The construction of maximally entangled bases for the bipartite system Cd⊗ Cd is discussed firstly, and some mutually unbiased bases with maximally entangled bases are given, where 2≤ d≤5. Moreover, we study a systematic way of constructing mutually unbiased maximally entangled bases for the bipartite system Cd⊗ C^{dk}.
Dirac plasmons in bipartite lattices of metallic nanoparticles
Jebb Sturges, Thomas; Woollacott, Claire; Weick, Guillaume; Mariani, Eros
2015-03-01
We study theoretically ‘graphene-like’ plasmonic metamaterials constituted by two-dimensional arrays of metallic nanoparticles, including perfect honeycomb structures with and without inversion symmetry, as well as generic bipartite lattices. The dipolar interactions between localized surface plasmons (LSPs) in different nanoparticles gives rise to collective plasmons (CPs) that extend over the whole lattice. We study the band structure of CPs and unveil its tunability with the orientation of the dipole moments associated with the LSPs. Depending on the dipole orientation, we identify a phase diagram of gapless or gapped phases in the CP dispersion. We show that the gapless phases in the phase diagram are characterized by CPs behaving as massless chiral Dirac particles, in analogy with electrons in graphene. When the inversion symmetry of the honeycomb structure is broken, CPs are described as gapped chiral Dirac modes with an energy-dependent Berry phase. We further relax the geometric symmetry of the honeycomb structure by analysing generic bipartite hexagonal lattices. In this case we study the evolution of the phase diagram and unveil the emergence of a sequence of topological phase transitions when one hexagonal sublattice is progressively shifted with respect to the other.
Perfect Matchings via Uniform Sampling in Regular Bipartite Graphs
Goel, Ashish; Khanna, Sanjeev
2008-01-01
In this paper we further investigate the well-studied problem of finding a perfect matching in a regular bipartite graph. The first non-trivial algorithm, with running time $O(mn)$, dates back to K\\"{o}nig's work in 1916 (here $m=nd$ is the number of edges in the graph, $2n$ is the number of vertices, and $d$ is the degree of each node). The currently most efficient algorithm takes time $O(m)$, and is due to Cole, Ost, and Schirra. We improve this running time to $O(\\min\\{m, \\frac{n^{2.5}\\ln n}{d}\\})$; this minimum can never be larger than $O(n^{1.75}\\sqrt{\\ln n})$. We obtain this improvement by proving a uniform sampling theorem: if we sample each edge in a $d$-regular bipartite graph independently with a probability $p = O(\\frac{n\\ln n}{d^2})$ then the resulting graph has a perfect matching with high probability. The proof involves a decomposition of the graph into pieces which are guaranteed to have many perfect matchings but do not have any small cuts. We then establish a correspondence between potential ...
ORTHOGONAL(g,f)-FACTORIZATIONS OF BIPARTITE GRAPHS
Institute of Scientific and Technical Information of China (English)
无
2001-01-01
Abstract Let G be a bipartite graph with vertex set V(G) and edge set E(G), and let g and f be two positive integer-valued functions defined on V(G) such that g(x)≤f(x) for every vertex x of V(G). Then a (g, f)-factor of G is a spanning subgraph H of G such that g(x)≤dH(x) ≤f(x) for each x∈V(H). A (g, f)-factorization of G is a partition of E(G) into edge-disjoint (g, f)-factors. Let F = {F1, F2,…, Fm } and H be a factorization and a subgraph of G, respectively. If Fi. 1≤i≤m, has exactly one edge in common with H, then it is said that F is orthogonal to H. It is proved that every bipartite (mg + m - 1. mf - m + 1 )-graph G has a (g, f)-factorization orthogonal to k vertex disjoint m-subgraphs of G if k/2≤g(x) for all x∈V(G). Furthermore, it is showed that the results in this paper are best possible.
PENENTUAN MATCHING MAKSIMUM PADA GRAF BIPARTIT BERBOBOT MENGGUNAKAN METODE HUNGARIAN
Directory of Open Access Journals (Sweden)
Muchammad Abrori
2012-06-01
Full Text Available Matching is a part of graph theory that discuss to make a pair, that can be used to solve many problems; one of them is the assignment problem. The assignment problem is to make a pair problem for n as the employees and for n as the duties, therefore each employee gets one duty, and each duty is given exactly for each employee. The assignment problem can be solved by determining the matching in weighted bipartite graph through Hungarian Method. It can be determined from the alternating tree of a formed edge. If there is augmenting path, that augmenting path is used to form the more number of matching. If the formed path is alternating path, therefore the process is labeling the new node until finding the augmenting vertices. This matching is called as the perfect matching with the number of maximum weighed side in weighted bipartite graphs. The result matching is the solution for the assignment problem by giving an employee with a duty.
Imaging with polycrystalline mercuric iodide detectors using VLSI readout
Energy Technology Data Exchange (ETDEWEB)
Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J
1999-06-01
Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.
VLSI implementations of threshold logic-a comprehensive survey.
Beiu, V; Quintana, J M; Avedillo, M J
2003-01-01
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
Crystal growth and evaluation of silicon for VLSI and ULSI
Eranna, Golla
2014-01-01
PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.
1992-01-01
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.
VLSI architectures for modern error-correcting codes
Zhang, Xinmiao
2015-01-01
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI
VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER
Directory of Open Access Journals (Sweden)
Joseph Gladwin Sekar
2013-01-01
Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.
Formal verification an essential toolkit for modern VLSI design
Seligman, Erik; Kumar, M V Achutha Kiran
2015-01-01
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific
Low-power Analog VLSI Implementation of Wavelet Transform
Institute of Scientific and Technical Information of China (English)
ZHANG Jiang-hong
2009-01-01
For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.
VLSI implementation of a fairness ATM buffer system
DEFF Research Database (Denmark)
Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard
1996-01-01
This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...
An adaptive, lossless data compression algorithm and VLSI implementations
Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu
1993-01-01
This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.
A VLSI Algorithm for Calculating the Treee to Tree Distance
Institute of Scientific and Technical Information of China (English)
徐美瑞; 刘小林
1993-01-01
Given two ordered,labeled trees βand α，to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.
Perfect Matchings in \\~O(n^{1.5}) Time in Regular Bipartite Graphs
Goel, Ashish
2009-01-01
We consider the well-studied problem of finding a perfect matching in d-regular bipartite graphs with 2n vertices and m = nd edges. While the best-known algorithm for general bipartite graphs (due to Hopcroft and Karp) takes O(m\\sqrt{n}) time, in regular bipartite graphs, a perfect matching is known to be computable in O(m) time. Very recently, the O(m) bound was improved to O(min{m, n^{2.5} log n/d}) expected time, an expression that is bounded by \\~O(n^{1.75}). In this paper, we present an \\~O(n^{1.5}) expected time algorithm for finding a perfect matching in regular bipartite graphs. To obtain this result, we prove a correspondence theorem between cuts and Hall's theorem "witnesses" for a perfect matching in a bipartite graph. We then design and analyze a two-stage sampling scheme that reduces the problem of finding a perfect matching in regular bipartite graphs to the same problem on arbitrary bipartite graphs with O(n log n) edges.
Markovian Classicality from Zero Discord for Bipartite Quantum Systems
Arsenijevic, M; Dugic, M
2012-01-01
Modern quantum information theory provides new tools for investigating the decoherence-induced "classicality" of open quantum systems. Recent observation that almost all quantum states bear non-classical correlations [A. Ferraro {\\it et al}, Phys. Rev. A {\\bf 81}, 052318 (2010)] distinguishes the zero-discord classicality essentially as a pathology of the Markovian bipartite-systems realm. Nevertheless, we formally construct such a classical model and its variant that represents a matter-of-principle formal proof, i.e. a sufficient condition for the, otherwise not obvious, existence of the Markovian zero-discord classicality. A need for the more elaborate and more systematic search for the alternative such models reveals we are still learning about the very meaning of "classicality" in the realm of open quantum systems.
Markovian Zero-Discord Classicality for Bipartite Quantum Systems
Arsenijevic, M; Dugic, M
2012-01-01
Recent observation that almost all quantum states bear nonclassical correlations [A. Ferraro et al, Phys. Rev. A 81, 052318 (2010)] distinguishes the zero-discord classicality essentially as a rareness of the Markovian bipartite systems realm. This seems to be in contrast with decoherence-theory established classicality where classical states are robust and unavoidable. Nevertheless, we formally construct such a classical model and its variant that represents a matter-of-principle formal proof, i.e. a sufficient condition for the, otherwise not obvious, existence of the Markovian zero-discord classicality. Rigorous analysis suggests there is no alternative to classical model, aside approximate model which follows from relaxing rigid quantum information constraints on classical model. A need for the more elaborate and more systematic search for the alternative such models (if there any) reveals we are still learning about the very meaning of "classicality" in the realm of open quantum systems.
All pure bipartite entangled states can be self-tested
Coladangelo, Andrea; Goh, Koon Tong; Scarani, Valerio
2017-05-01
Quantum technologies promise advantages over their classical counterparts in the fields of computation, security and sensing. It is thus desirable that classical users are able to obtain guarantees on quantum devices, even without any knowledge of their inner workings. That such classical certification is possible at all is remarkable: it is a consequence of the violation of Bell inequalities by entangled quantum systems. Device-independent self-testing refers to the most complete such certification: it enables a classical user to uniquely identify the quantum state shared by uncharacterized devices by simply inspecting the correlations of measurement outcomes. Self-testing was first demonstrated for the singlet state and a few other examples of self-testable states were reported in recent years. Here, we address the long-standing open question of whether every pure bipartite entangled state is self-testable. We answer it affirmatively by providing explicit self-testing correlations for all such states.
No-signaling, perfect bipartite dichotomic correlations and local randomness
Seevinck, M P
2011-01-01
The no-signaling constraint on bi-partite correlations is reviewed. It is shown that in order to obtain non-trivial Bell-type inequalities that discern no-signaling correlations from more general ones, one must go beyond considering expectation values of products of observables only. A new set of nontrivial no-signaling inequalities is derived which have a remarkably close resemblance to the CHSH inequality, yet are fundamentally different. A set of inequalities by Roy and Singh and Avis et al., which is claimed to be useful for discerning no-signaling correlations, is shown to be trivially satisfied by any correlation whatsoever. Finally, using the set of newly derived no-signaling inequalities a result with potential cryptographic consequences is proven: if different parties use identical devices, then, once they have perfect correlations at spacelike separation between dichotomic observables, they know that because of no-signaling the local marginals cannot but be completely random.
Entanglement dynamics of a pure bipartite system in dissipative environments
Energy Technology Data Exchange (ETDEWEB)
Tahira, Rabia; Ikram, Manzoor; Azim, Tasnim; Suhail Zubairy, M [Centre for Quantum Physics, COMSATS Institute of Information Technology, Islamabad (Pakistan)
2008-10-28
We investigate the phenomenon of sudden death of entanglement in a bipartite system subjected to dissipative environments with arbitrary initial pure entangled state between two atoms. We find that in a vacuum reservoir the presence of the state where both atoms are in excited states is a necessary condition for the sudden death of entanglement. Otherwise entanglement remains for an infinite time and decays asymptotically with the decay of individual qubits. For pure 2-qubit entangled states in a thermal environment, we observe that the sudden death of entanglement always happens. The sudden death time of the entangled states is related to the temperature of the reservoir and the initial preparation of the entangled states.
Extreme edge-friendly indices of complete bipartite graphs
Directory of Open Access Journals (Sweden)
Wai Chee Shiu
2016-09-01
Full Text Available Let G=(V,E be a simple graph. An edge labeling f:E to {0,1} induces a vertex labeling f^+:V to Z_2 defined by $f^+(vequiv sumlimits_{uvin E} f(uvpmod{2}$ for each $v in V$, where Z_2={0,1} is the additive group of order 2. For $iin{0,1}$, let e_f(i=|f^{-1}(i| and v_f(i=|(f^+^{-1}(i|. A labeling f is called edge-friendly if $|e_f(1-e_f(0|le 1$. I_f(G=v_f(1-v_f(0 is called the edge-friendly index of G under an edge-friendly labeling f. Extreme values of edge-friendly index of complete bipartite graphs will be determined.
Spin-1 Dirac-Weyl fermions protected by bipartite symmetry
Energy Technology Data Exchange (ETDEWEB)
Lin, Zeren [College of Chemistry and Molecular Engineering, Peking University, Beijing 100871 (China); School of Physics, Peking University, Beijing 100871 (China); Liu, Zhirong, E-mail: LiuZhiRong@pku.edu.cn [College of Chemistry and Molecular Engineering, Peking University, Beijing 100871 (China); Center for Nanochemistry, Beijing National Laboratory for Molecular Sciences (BNLMS), Peking University, Beijing 100871 (China)
2015-12-07
We propose that bipartite symmetry allows spin-1 Dirac-Weyl points, a generalization of the spin-1/2 Dirac points in graphene, to appear as topologically protected at the Fermi level. In this spirit, we provide methodology to construct spin-1 Dirac-Weyl points of this kind in a given 2D space group and get the classification of the known spin-1 systems in the literature. We also apply the workflow to predict two new systems, P3m1-9 and P31m-15, to possess spin-1 at K/K′ in the Brillouin zone of hexagonal lattice. Their stability under various strains is investigated and compared with that of T{sub 3}, an extensively studied model of ultracold atoms trapped in optical lattice with spin-1 also at K/K′.
$E_{6}$ and the bipartite entanglement of three qutrits
Duff, M J
2007-01-01
Recent investigations have established an analogy between the entropy of four-dimensional supersymmetric black holes in string theory and entanglement in quantum information theory. Examples include: (1) N=2 STU black holes and the tripartite entanglement of three qubits (2-state systems), where the common symmetry is [SL(2)]^3 and (2) N=8 black holes and the tripartite entanglement of seven qubits where the common symmetry is E_7 which contains [SL(2)]^7. Here we present another example: N=8 black holes (or black strings) in five dimensions and the bipartite entanglement of three qutrits (3-state systems), where the common symmetry is E_6 which contains [SL(3)]^3. Both the black hole (or black string) entropy and the entanglement measure are provided by the Cartan cubic E_6 invariant. Similar analogies exist for ``magic'' N=2 supergravity black holes in both four and five dimensions.
Conflicting attachment and the growth of bipartite networks
Yin, Chung; Weitz, Joshua S
2015-01-01
Simple growth mechanisms have been proposed to explain the emergence of seemingly universal network structures. The widely-studied model of preferential attachment assumes that new nodes are more likely to connect to highly connected nodes. Preferential attachment explains the emergence of scale-free degree distributions within complex networks. Yet, it is incompatible with many network systems, particularly bipartite systems in which two distinct types of agents interact. For example, the addition of new links in a host-parasite system corresponds to the infection of hosts by parasites. Increasing connectivity is beneficial to a parasite and detrimental to a host. Therefore, the overall network connectivity is subject to conflicting pressures. Here, we propose a stochastic network growth model of conflicting attachment, inspired by a particular kind of parasite-host interactions: that of viruses interacting with microbial hosts. The mechanism of network growth includes conflicting preferences to network dens...
Entanglement dynamics of bipartite system in squeezed vacuum reservoirs
Bougouffa, Smail
2010-01-01
Entanglement plays a crucial role in quantum information protocols, thus the dynamical behavior of entangled states is of a great importance. In this paper we suggest a useful scheme that permits a direct measure of entanglement in a two-qubit cavity system. It is realized in the cavity-QED technology utilizing atoms as fying qubits. To quantify entanglement we use the concurrence. We derive the conditions, which assure that the state remains entangled in spite of the interaction with the reservoir. The phenomenon of sudden death entanglement (ESD) in a bipartite system subjected to squeezed vacuum reservoir is examined. We show that the sudden death time of the entangled states depends on the initial preparation of the entangled state and the parameters of the squeezed vacuum reservoir.
Entanglement dynamics of a bipartite system in squeezed vacuum reservoirs
Energy Technology Data Exchange (ETDEWEB)
Bougouffa, Smail [Department of Physics, Faculty of Science, Taibah University, PO Box 30002, Madinah (Saudi Arabia); Hindi, Awatif, E-mail: sbougouffa@taibahu.edu.sa, E-mail: sbougouffa@hotmail.com [Physics Department, College of Science, PO Box 22452, King Saud University, Riyadh 11495 (Saudi Arabia)
2011-02-15
Entanglement plays a crucial role in quantum information protocols; thus the dynamical behavior of entangled states is of great importance. In this paper, we suggest a useful scheme that permits a direct measure of entanglement in a two-qubit cavity system. It is realized through cavity-QED technology utilizing atoms as flying qubits. To quantify entanglement we use the concurrence. We derive the conditions that ensure that the state remains entangled in spite of the interaction with the reservoir. The phenomenon of entanglement sudden death in a bipartite system subjected to a squeezed vacuum reservoir is examined. We show that the sudden death time of the entangled states depends on the initial preparation of the entangled state and the parameters of the squeezed vacuum reservoir.
Topological collective plasmons in bipartite chains of metallic nanoparticles
Downing, Charles A
2016-01-01
We study a bipartite linear chain constituted by spherical metallic nanoparticles, where each nanoparticle supports a localized surface plasmon. The near-field dipolar interaction between the localized surface plasmons gives rise to collective plasmons, which are extended over the whole nanoparticle array. We derive analytically the spectrum and the eigenstates of the collective plasmonic excitations. At the edge of the Brillouin zone, the spectrum is of a pseudo-relativistic nature similar to that present in the electronic band structure of polyacetylene. We find the effective Dirac Hamiltonian for the collective plasmons and show that the corresponding spinor eigenstates represent one-dimensional Dirac-like massive bosonic excitations. Therefore, the plasmonic lattice exhibits similar effects to those found for electrons in one-dimensional Dirac materials, such as the ability for transmission with highly suppressed backscattering due to Klein tunnelling. We also show that the system is governed by a nontriv...
Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.
Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David
2005-11-01
A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.
Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips
Institute of Scientific and Technical Information of China (English)
WANGJun
2004-01-01
Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.
De Bruyn, Alexandre; Harimalala, Mireille; Hoareau, Murielle; Ranomenjanahary, Sahondramalala; Reynaud, Bernard; Lefeuvre, Pierre; Lett, Jean-Michel
2015-06-01
Here, we describe for the first time the complete genome sequence of a new bipartite begomovirus in Madagascar isolated from the weed Asystasia gangetica (Acanthaceae), for which we propose the tentative name asystasia mosaic Madagascar virus (AMMGV). DNA-A and -B nucleotide sequences of AMMGV were only distantly related to known begomovirus sequence and shared highest nucleotide sequence identity of 72.9 % (DNA-A) and 66.9 % (DNA-B) with a recently described bipartite begomovirus infecting Asystasia sp. in West Africa. Phylogenetic analysis demonstrated that this novel virus from Madagascar belongs to a new lineage of Old World bipartite begomoviruses.
Testing interconnected VLSI circuits in the Big Viterbi Decoder
Onyszchuk, I. M.
1991-01-01
The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.
New VLSI complexity results for threshold gate comparison
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1996-12-31
The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.
A VLSI design concept for parallel iterative algorithms
Directory of Open Access Journals (Sweden)
C. C. Sun
2009-05-01
Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.
A fast neural-network algorithm for VLSI cell placement.
Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail
1998-12-01
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Directory of Open Access Journals (Sweden)
Cavallaro Joseph R
2006-01-01
Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.
Opto-VLSI-based reconfigurable free-space optical interconnects architecture
DEFF Research Database (Denmark)
Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;
2007-01-01
is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....
Real-time simulation of biologically realistic stochastic neurons in VLSI.
Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie
2010-09-01
Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.
Pop, Paul; Madsen, Jan
2016-01-01
This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...
Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo; Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems
2015-01-01
This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...
Daminelli, Simone; Thomas, Josephine Maria; Durán, Claudio; Vittorio Cannistraci, Carlo
2015-11-01
Bipartite networks are powerful descriptions of complex systems characterized by two different classes of nodes and connections allowed only across but not within the two classes. Unveiling physical principles, building theories and suggesting physical models to predict bipartite links such as product-consumer connections in recommendation systems or drug-target interactions in molecular networks can provide priceless information to improve e-commerce or to accelerate pharmaceutical research. The prediction of nonobserved connections starting from those already present in the topology of a network is known as the link-prediction problem. It represents an important subject both in many-body interaction theory in physics and in new algorithms for applied tools in computer science. The rationale is that the existing connectivity structure of a network can suggest where new connections can appear with higher likelihood in an evolving network, or where nonobserved connections are missing in a partially known network. Surprisingly, current complex network theory presents a theoretical bottle-neck: a general framework for local-based link prediction directly in the bipartite domain is missing. Here, we overcome this theoretical obstacle and present a formal definition of common neighbour index and local-community-paradigm (LCP) for bipartite networks. As a consequence, we are able to introduce the first node-neighbourhood-based and LCP-based models for topological link prediction that utilize the bipartite domain. We performed link prediction evaluations in several networks of different size and of disparate origin, including technological, social and biological systems. Our models significantly improve topological prediction in many bipartite networks because they exploit local physical driving-forces that participate in the formation and organization of many real-world bipartite networks. Furthermore, we present a local-based formalism that allows to intuitively
Bipartite patella causing knee pain in young adults: a report of 5 cases.
Vaishya, Raju; Chopra, Surender; Vijay, Vipul; Vaish, Abhishek
2015-04-01
We report on 5 patients who underwent arthroscopic excision or open reduction and internal fixation for bipartite patella. All patients presented with refractory anterior knee pain. The diagnosis of bipartite patella was made using radiography, and confirmed with magnetic resonance imaging or computed tomographic arthrography. All 5 patients achieved complete resolution of symptoms after surgery, and remained pain-free after a mean followup period of 13 months.
HellRank: A Hellinger-based Centrality Measure for Bipartite Social Networks
Taheri, Seyed Mohammad; Mahyar, Hamidreza; Firouzi, Mohammad; K., Elahe Ghalebi; Grosu, Radu; Movaghar, Ali
2016-01-01
Measuring centrality in a social network, especially in bipartite mode, poses several challenges such as requirement of full knowledge of the network topology and lack of properly detection of top-k behavioral representative users. In this paper, to overcome the aforementioned challenging issues, we propose an accurate centrality measure, called HellRank, to identify central nodes in bipartite social networks. HellRank is based on the Hellinger distance between two nodes on the same side of a...
Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.
Mustafa, Haithem; Xiao, Feng; Alameh, Kamal
2011-10-24
A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.
CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation
Directory of Open Access Journals (Sweden)
Hussein CHIBLE,
2013-10-01
Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented
POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS
Directory of Open Access Journals (Sweden)
D. I. Cheremisinov
2013-01-01
Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.
VLSI technology for smaller, cheaper, faster return link systems
Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John
1994-01-01
Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.
Cascaded VLSI Chips Help Neural Network To Learn
Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.
1993-01-01
Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.
Efficient VLSI architecture for training radial basis function networks.
Fan, Zhe-Cheng; Hwang, Wen-Jyi
2013-03-19
This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.
Abdelhalim, K; Smolyakov, V; Genov, R
2011-10-01
A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.
Event-driven neural integration and synchronicity in analog VLSI.
Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert
2012-01-01
Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.
Modeling selective attention using a neuromorphic analog VLSI device.
Indiveri, G
2000-12-01
Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.
Analog VLSI implementation of resonate-and-fire neuron.
Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo
2006-12-01
We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.
VLSI-based Video Event Triggering for Image Data Compression
Williams, Glenn L.
1994-01-01
Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
1992-01-01
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
VLSI design techniques for floating-point computation
Energy Technology Data Exchange (ETDEWEB)
Bose, B. K.
1988-01-01
The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.
Efficient VLSI Architecture for Training Radial Basis Function Networks
Directory of Open Access Journals (Sweden)
Wen-Jyi Hwang
2013-03-01
Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Carbon nanotube based VLSI interconnects analysis and design
Kaushik, Brajesh Kumar
2015-01-01
The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.
Realistic model of compact VLSI FitzHugh-Nagumo oscillators
Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel
2014-02-01
In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.
Power Efficient Sub-Array in Reconfigurable VLSI Meshes
Institute of Scientific and Technical Information of China (English)
Ji-Gang Wu; Thambipillai Srikanthan
2005-01-01
Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.
Replacing design rules in the VLSI design cycle
Hurley, Paul; Kryszczuk, Krzysztof
2012-03-01
We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.
Parallel optical interconnects utilizing VLSI/FLC spatial light modulators
Genco, Sheryl M.
1991-12-01
Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
P4k-1-factorization of complete bipartite graphs
Institute of Scientific and Technical Information of China (English)
DU; Beiliang; WANG; Jian
2005-01-01
Let Km,n be a complete bipartite graph with two partite sets having m and n vertices, respectively. A Pv-factorization of Km,n is a set of edge-disjoint Pv-factors of Km,n which partition the set of edges of Km,n. When v is an even number,Wang and Ushio gave a necessary and sufficient condition for the existence of Pv-factorization of Km,n. When v is an odd number, Ushio in 1993 proposed a conjecture. However, up to now we only know that Ushio Conjecture is true for v=3. In this paper wewill show that Ushio Conjecture is true when v=4k-1. That is, we shall prove that a necessary and sufficient condition for the existence of a P4k-1-factorization of Km,n is (1) (2k-1)m≤2kn, (2) (2k-1)n ≤2km, (3) m+n ≡0 (mod 4k-1), (4) (4k-1)mn/[2(2k-1)(m+n)] is an integer.integer.
Partial recovery of lost entanglement in bipartite entanglement transformations
Bandyopadhyay, S; Vatan, F; Roychowdhury, Vwani; Vatan, Farrokh
2002-01-01
We show that partial recovery of the entanglement lost in a bipartite pure state entanglement transformations is almost always possible irrespective of the dimension. Let $\\ket{\\psi}$ and $\\ket{\\vph}$ be $n\\times n$ states and $\\ket{\\psi} \\longrightarrow \\ket{\\vph}$ under local operations. We ask whether there exists $k\\times k$ states, $\\ket{\\chi}$ and $\\ket{\\omega}$, $k E(\\ket{\\chi})$, $E$ being the entropy of entanglement such that $\\ket{\\psi}\\otimes\\ket{\\chi} \\longrightarrow \\ket{\\vph}\\otimes\\ket{\\omega}$ under LOCC. We show that for almost all pairs of comparable states recovery is achievable by $2\\times 2$ states, no matter how large the dimension of the parent states are. For other cases we show that the dimension of the auxiliary entangled state depends on the presence of equalities in the majorization relations of the parent states. We identify those states and show that recovery is still possible using states in $k\\times k$, $2
Conditional Mutual Information of Bipartite Unitaries and Scrambling
Ding, Dawei; Walter, Michael
2016-01-01
One way to diagnose chaos in bipartite unitary channels is via the negativity of the tripartite information of the corresponding Choi state, which for certain choices of the subsystems reduces to the negative conditional mutual information (CMI). We study this quantity from a quantum information-theoretic perspective to clarify its role in diagnosing scrambling. When the CMI is zero, we find that the channel has a special normal form consisting of local channels between individual inputs and outputs. However, we find that arbitrarily low CMI does not imply arbitrary proximity to a channel of this form, although it does imply a type of approximate recoverability of one of the inputs. When the CMI is maximal, we find that the residual channel from an individual input to an individual output is completely depolarizing when the other inputs are maximally mixed. However, we again find that this result is not robust. We also extend some of these results to the multipartite case and to the case of Haar-random pure i...
Bipartite entanglement in spin-1/2Heisenberg model
Institute of Scientific and Technical Information of China (English)
HU Ming-Liang; TIAN Dong-Ping
2008-01-01
The bipartite entanglement of the two-and three-spin Heisenberg model was investigated by using the concept of negativity.It is found that for the ground-state entanglement of the two-spin model,the negativity always decreases as B increases if A Δ＜y-1,and it may keep a steady value of 0.5in the region of B＜J[(Δ+1)2-y2]1/2if Δ＞y-1,while for that of the three-spin model,the negativity exhibits square wave structures if y=0 or Δ=0.For thermal states,there are two areas showing entanglement,namely,the main region and the sub-region.The main region exists only when Δ＞Δc(Δc1=and(y2-1)/2for the 2-and 3-spin model respectively)and extends in terms of B and T as Δ increases,while the sub-region survives only when y≠0 and shrinks in terms of B and T as Δ increases.
Better Bounds for Incremental Frequency Allocation in Bipartite Graphs
Chrobak, Marek; Sgall, Jiří
2011-01-01
We study frequency allocation in wireless networks. A wireless network is modeled by an undirected graph, with vertices corresponding to cells. In each vertex we have a certain number of requests, and each of those requests must be assigned a different frequency. Edges represent conflicts between cells, meaning that frequencies in adjacent vertices must be different as well. The objective is to minimize the total number of used frequencies. The offline version of the problem is known to be NP-hard. In the incremental version, requests for frequencies arrive over time and the algorithm is required to assign a frequency to a request as soon as it arrives. Competitive incremental algorithms have been studied for several classes of graphs. For paths, the optimal (asymptotic) ratio is known to be 4/3, while for hexagonal-cell graphs it is between 1.5 and 1.9126. For k-colorable graphs, the ratio of (k+1)/2 can be achieved. In this paper, we prove nearly tight bounds on the asymptotic competitive ratio for bipartit...
The spectrum of path factorization of bipartite multigraphs
Institute of Scientific and Technical Information of China (English)
2007-01-01
LetλKm,nbe a bipartite multigraph with two partite sets having m and n vertices, respectively.A Pv-factorization ofλKm,nis a set of edge-disjoint Pv-factors ofλKm,nwhich partition the set of edges ofλKm,n.When v is an even number,Ushio,Wang and the second author of the paper gave a necessary and sufficient condition for the existence of a Pv-factorization ofλKm,n.When v is an odd number,we have proposed a conjecture.Very recently,we have proved that the conjecture is true when v=4k-1.In this paper we shall show that the conjecture is true when v = 4k + 1,and then the conjecture is true.That is,we will prove that the necessary and sufficient conditions for the existence of a P4k+1-factorization ofλKm,nare（1）2km≤（2k+1）n,（2）2kn≤（2k+1）m,（3）m+n≡0（mod 4k+1）,（4）λ（4k+1）mn/[4k（m+n）]is an integer.
The spectrum of path factorization of bipartite multigraphs
Institute of Scientific and Technical Information of China (English)
Jian WANG; Bei-liang DU
2007-01-01
Let λKm,n be a bipartite multigraph with two partite sets having m and n vertices,respectively. A Pv-factorization of λKm,n is a set of edge-disjoint Pv-factors of λKm,n which partition the set of edges of λKm,n. When v is an even number, Ushio, Wang and the second author of the paper gave a necessary and sufficient condition for the existence of a Pv-factorization of λK When v is an odd number, we have proposed a conjecture. Very recently, we have proved that the conjecture is true when v ＝ 4k - 1. In this paper we shall show that the conjecture is true when v ＝ 4k + 1, and then the conjecture is true. That is, we will prove that the necessary and sufficient conditions for the existence of a P4k+1-factorization of λKm,n are (1) 2km ≤ (2k + 1)n, (2) 2kn ≤ (2k + 1)m, (3) m + n ≡0 (mod 4k + 1), (4) λ(4k + 1)mn/[4k(m + n)] is an integer.
Kp,q-factorization of complete bipartite graphs
Institute of Scientific and Technical Information of China (English)
DU; Beiliang; WANG; Jian
2004-01-01
Let Km,n be a completebipartite graph with two partite sets having m and n vertices,respectively. A Kp,q-factorization of Km,n is a set ofedge-disjoint Kp,q-factors of Km,n which partition theset of edges of Km,n. When p=1 and q is a prime number,Wang, in his paper "On K1,k-factorizations of a completebipartite graph" (Discrete Math, 1994, 126: 359-364),investigated the K1,q-factorization of Km,n and gave asufficient condition for such a factorization to exist. In the paper"K1,k-factorizations of complete bipartite graphs" (DiscreteMath, 2002, 259: 301-306), Du and Wang extended Wang's resultto the case that q is any positive integer. In this paper, we give a sufficient condition for Km,n to have aKp,q-factorization. As a special case, it is shown that theMartin's BAC conjecture is true when p:q=k:(k+1) for any positiveinteger k.
Topological collective plasmons in bipartite chains of metallic nanoparticles
Downing, Charles A.; Weick, Guillaume
2017-03-01
We study a bipartite linear chain constituted by spherical metallic nanoparticles, where each nanoparticle supports a localized surface plasmon. The near-field dipolar interaction between the localized surface plasmons gives rise to collective plasmons, which are extended over the whole nanoparticle array. We derive analytically the spectrum and the eigenstates of the collective plasmonic excitations. At the edge of the Brillouin zone, the spectrum is of a pseudorelativistic nature similar to that present in the electronic band structure of polyacetylene. We find the effective Dirac Hamiltonian for the collective plasmons and show that the corresponding spinor eigenstates represent one-dimensional Dirac-like massive bosonic excitations. Therefore, the plasmonic lattice exhibits similar effects to those found for electrons in one-dimensional Dirac materials, such as the ability for transmission with highly suppressed backscattering due to Klein tunneling. We also show that the system is governed by a nontrivial Zak phase, which predicts the manifestation of edge states in the chain. When two dimerized chains with different topological phases are connected, we find the appearance of the bosonic version of a Jackiw-Rebbi midgap state. We further investigate the radiative and nonradiative lifetimes of the collective plasmonic excitations and comment on the challenges for experimental realization of the topological effects found theoretically.
Evolutionary matching-pennies game on bipartite regular networks
Szabó, György; Varga, Levente; Borsos, István
2014-04-01
Evolutionary games are studied here with two types of players located on a chessboard or on a bipartite random regular graph. Each player's income comes from matching-pennies games played with the four neighbors. The players can modify their own strategies according to a myopic strategy update resembling the Glauber dynamics for the kinetic Ising model. This dynamical rule drives the system into a stationary state where the two strategies are present with the same probability without correlations between the nearest neighbors while a weak correlation is induced between the second and the third neighbors. In stationary states, the deviation from the detailed balance is quantified by the evaluation of entropy production. Finally, our analysis is extended to evolutionary games where the uniform pair interactions are composed of an anticoordination game and a weak matching-pennies game. This system preserves the Ising type order-disorder transitions at a critical noise level decreasing with the strength of the matching-pennies component for both networks.
Identifying online user reputation of user-object bipartite networks
Liu, Xiao-Lu; Liu, Jian-Guo; Yang, Kai; Guo, Qiang; Han, Jing-Ti
2017-02-01
Identifying online user reputation based on the rating information of the user-object bipartite networks is important for understanding online user collective behaviors. Based on the Bayesian analysis, we present a parameter-free algorithm for ranking online user reputation, where the user reputation is calculated based on the probability that their ratings are consistent with the main part of all user opinions. The experimental results show that the AUC values of the presented algorithm could reach 0.8929 and 0.8483 for the MovieLens and Netflix data sets, respectively, which is better than the results generated by the CR and IARR methods. Furthermore, the experimental results for different user groups indicate that the presented algorithm outperforms the iterative ranking methods in both ranking accuracy and computation complexity. Moreover, the results for the synthetic networks show that the computation complexity of the presented algorithm is a linear function of the network size, which suggests that the presented algorithm is very effective and efficient for the large scale dynamic online systems.
The Random Walk Model Based on Bipartite Network
Directory of Open Access Journals (Sweden)
Zhang Man-Dun
2016-01-01
Full Text Available With the continuing development of the electronic commerce and growth of network information, there is a growing possibility for citizens to be confused by the information. Though the traditional technology of information retrieval have the ability to relieve the overload of information in some extent, it can not offer a targeted personality service based on user’s interests and activities. In this context, the recommendation algorithm arose. In this paper, on the basis of conventional recommendation, we studied the scheme of random walk based on bipartite network and the application of it. We put forward a similarity measurement based on implicit feedback. In this method, a uneven character vector is imported(the weight of item in the system. We put forward a improved random walk pattern which make use of partial or incomplete neighbor information to create recommendation information. In the end, there is an experiment in the real data set, the recommendation accuracy and practicality are improved. We promise the reality of the result of the experiment
Fitness landscapes, memetic algorithms, and greedy operators for graph bipartitioning.
Merz, P; Freisleben, B
2000-01-01
The fitness landscape of the graph bipartitioning problem is investigated by performing a search space analysis for several types of graphs. The analysis shows that the structure of the search space is significantly different for the types of instances studied. Moreover, with increasing epistasis, the amount of gene interactions in the representation of a solution in an evolutionary algorithm, the number of local minima for one type of instance decreases and, thus, the search becomes easier. We suggest that other characteristics besides high epistasis might have greater influence on the hardness of a problem. To understand these characteristics, the notion of a dependency graph describing gene interactions is introduced. In particular, the local structure and the regularity of the dependency graph seems to be important for the performance of an algorithm, and in fact, algorithms that exploit these properties perform significantly better than others which do not. It will be shown that a simple hybrid multi-start local search exploiting locality in the structure of the graphs is able to find optimum or near optimum solutions very quickly. However, if the problem size increases or the graphs become unstructured, a memetic algorithm (a genetic algorithm incorporating local search) is shown to be much more effective.
Bipartite structure of the inactive mouse X chromosome.
Deng, Xinxian; Ma, Wenxiu; Ramani, Vijay; Hill, Andrew; Yang, Fan; Ay, Ferhat; Berletch, Joel B; Blau, Carl Anthony; Shendure, Jay; Duan, Zhijun; Noble, William S; Disteche, Christine M
2015-08-07
In mammals, one of the female X chromosomes and all imprinted genes are expressed exclusively from a single allele in somatic cells. To evaluate structural changes associated with allelic silencing, we have applied a recently developed Hi-C assay that uses DNase I for chromatin fragmentation to mouse F1 hybrid systems. We find radically different conformations for the two female mouse X chromosomes. The inactive X has two superdomains of frequent intrachromosomal contacts separated by a boundary region. Comparison with the recently reported two-superdomain structure of the human inactive X shows that the genomic content of the superdomains differs between species, but part of the boundary region is conserved and located near the Dxz4/DXZ4 locus. In mouse, the boundary region also contains a minisatellite, Ds-TR, and both Dxz4 and Ds-TR appear to be anchored to the nucleolus. Genes that escape X inactivation do not cluster but are located near the periphery of the 3D structure, as are regions enriched in CTCF or RNA polymerase. Fewer short-range intrachromosomal contacts are detected for the inactive alleles of genes subject to X inactivation compared with the active alleles and with genes that escape X inactivation. This pattern is also evident for imprinted genes, in which more chromatin contacts are detected for the expressed allele. By applying a novel Hi-C method to map allelic chromatin contacts, we discover a specific bipartite organization of the mouse inactive X chromosome that probably plays an important role in maintenance of gene silencing.
Inductive Model Generation for Text Classification Using a Bipartite Heterogeneous Network
Institute of Scientific and Technical Information of China (English)
Rafael Geraldeli Rossi; Alneu de Andrade Lopes; Thiago de Paulo Faleiros; Solange Oliveira Rezende
2014-01-01
Algorithms for numeric data classification have been applied for text classification. Usually the vector space model is used to represent text collections. The characteristics of this representation such as sparsity and high dimensionality sometimes impair the quality of general-purpose classifiers. Networks can be used to represent text collections, avoiding the high sparsity and allowing to model relationships among different objects that compose a text collection. Such network-based representations can improve the quality of the classification results. One of the simplest ways to represent textual collections by a network is through a bipartite heterogeneous network, which is composed of objects that represent the documents connected to objects that represent the terms. Heterogeneous bipartite networks do not require computation of similarities or relations among the objects and can be used to model any type of text collection. Due to the advantages of representing text collections through bipartite heterogeneous networks, in this article we present a text classifier which builds a classification model using the structure of a bipartite heterogeneous network. Such an algorithm, referred to as IMBHN (Inductive Model Based on Bipartite Heterogeneous Network), induces a classification model assigning weights to ob jects that represent the terms for each class of the text collection. An empirical evaluation using a large amount of text collections from different domains shows that the proposed IMBHN algorithm produces significantly better results than k-NN, C4.5, SVM, and Naive Bayes algorithms.
Influence of scrotal bipartition on spermatogenesis yield and sertoli cell efficiency in sheep
Directory of Open Access Journals (Sweden)
Ramon T.G.A. Rodrigues
2016-04-01
Full Text Available Abstract With the objective to assess the effect of scrotal bipartition on spermatogenesis in sheep, the testes were used from 12 crossbred rams of sheep farms in the municipality of Patos, Paraíba, Brazil, distributed into two groups: GI with six rams with scrotal bipartition, and GII with six rams without scrotal bipartition. The testicular biometry was measured and the testes were collected, fixed in Bouin and fragments were processed to obtain histological slides. The spermatogenesis yield and the Sertoli cell efficiency was estimated by counting the cells of the spermatogenetic line at stage one of the seminiferous epithelium cycle and the Sertoli cells. The results were submitted to analysis of variance with the ASSISTAT v.7.6 program and the mean values were compared by the Student-Newman-Keuls test (SNK at 5% significance. The testicular biometric parameters did not show statistical difference (p>0.05 between the groups. The meiotic, spermatogenetic and Sertoli cell efficiency were higher in bipartitioned rams (p0.05 between GI and GII. The results indicated that there is superiority in the spermatogenetic parameters of bi-partitioned rams, suggesting that these sheep present, as reported in goats, indication of better reproductive indices.
Totally Bipartite/ABipartite Leonard pairs and Leonard triples of Bannai/Ito type
Brown, George M F
2011-01-01
This paper is about three classes of objects: Leonard pairs, Leonard triples, and the finite-dimensional irreducible modules for an algebra $\\mathcal{A}$. Let $\\K$ denote an algebraically closed field of characteristic zero. Let $V$ denote a vector space over $\\K$ with finite positive dimension. A Leonard pair on $V$ is an ordered pair of linear transformations in End$(V)$ such that for each of these transformations there exists a basis for $V$ with respect to which the matrix representing that transformation is diagonal and the matrix representing the other transformation is irreducible tridiagonal. Whenever the tridiagonal matrices are bipartite, the Leonard pair is said to be totally bipartite. A mild weakening yields a type of Leonard pair said to be totally almost bipartite. A Leonard pair is said to be totally B/AB whenever it is totally bipartite or totally almost bipartite. The notion of a Leonard triple and the corresponding notion of totally B/AB are similarly defined. There are families of Leonard ...
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
LIU; Yanpei(
2001-01-01
［1］Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.［2］Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.［3］Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.［4］Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.［5］Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.［6］Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.［7］Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.［8］Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.［9］Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.［10］Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.［11］Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.［12］Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.［13］Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.
Energy Technology Data Exchange (ETDEWEB)
Bateman, Nicholas W. [Women' s Health Integrated Research Center at Inova Health System, Gynecologic Cancer Center of Excellence, Annandale 22003, VA (United States); The John P. Murtha Cancer Center, Walter Reed National Military Medical Center, 8901 Wisconsin Avenue, Bethesda 20889, MD (United States); Shoji, Yutaka [Department of Obstetrics, Gynecology and Reproductive Biology, Michigan State University, Grand Rapids 49503, MI (United States); Conrads, Kelly A.; Stroop, Kevin D. [Women' s Health Integrated Research Center at Inova Health System, Gynecologic Cancer Center of Excellence, Annandale 22003, VA (United States); Hamilton, Chad A. [Women' s Health Integrated Research Center at Inova Health System, Gynecologic Cancer Center of Excellence, Annandale 22003, VA (United States); The John P. Murtha Cancer Center, Walter Reed National Military Medical Center, 8901 Wisconsin Avenue, Bethesda 20889, MD (United States); Gynecologic Oncology Service, Department of Obstetrics and Gynecology, Walter Reed National Military Medical Center, 8901 Wisconsin Ave, MD, Bethesda, 20889 (United States); Department of Obstetrics and Gynecology, Uniformed Services University of the Health Sciences, Bethesda 20814, MD (United States); Darcy, Kathleen M. [Women' s Health Integrated Research Center at Inova Health System, Gynecologic Cancer Center of Excellence, Annandale 22003, VA (United States); The John P. Murtha Cancer Center, Walter Reed National Military Medical Center, 8901 Wisconsin Avenue, Bethesda 20889, MD (United States); Maxwell, George L. [Department of Obstetrics and Gynecology, Inova Fairfax Hospital, Falls Church, VA 22042 (United States); Risinger, John I. [Department of Obstetrics, Gynecology and Reproductive Biology, Michigan State University, Grand Rapids 49503, MI (United States); and others
2016-01-01
AT-rich interactive domain-containing protein 1A (ARID1A) is a recently identified nuclear tumor suppressor frequently altered in solid tumor malignancies. We have identified a bipartite-like nuclear localization sequence (NLS) that contributes to nuclear import of ARID1A not previously described. We functionally confirm activity using GFP constructs fused with wild-type or mutant NLS sequences. We further show that cyto-nuclear localized, bipartite NLS mutant ARID1A exhibits greater stability than nuclear-localized, wild-type ARID1A. Identification of this undescribed functional NLS within ARID1A contributes vital insights to rationalize the impact of ARID1A missense mutations observed in patient tumors. - Highlights: • We have identified a bipartite nuclear localization sequence (NLS) in ARID1A. • Confirmation of the NLS was performed using GFP constructs. • NLS mutant ARID1A exhibits greater stability than wild-type ARID1A.
Leke, Walter N; Khatabi, Behnam; Fondong, Vincent N; Brown, Judith K
2016-08-01
The complete genome sequence was determined and characterized for a previously unreported bipartite begomovirus from fluted pumpkin (Telfairia occidentalis, family Cucurbitaceae) plants displaying mosaic symptoms in Cameroon. The DNA-A and DNA-B components were ~2.7 kb and ~2.6 kb in size, and the arrangement of viral coding regions on the genomic components was like those characteristic of other known bipartite begomoviruses originating in the Old World. While the DNA-A component was more closely related to that of chayote yellow mosaic virus (ChaYMV), at 78 %, the DNA-B component was more closely related to that of soybean chlorotic blotch virus (SbCBV), at 64 %. This newly discovered bipartite Old World virus is herein named telfairia mosaic virus (TelMV).
Identifying common components across biological network graphs using a bipartite data model.
Baker, Ej; Culpepper, C; Philips, C; Bubier, J; Langston, M; Chesler, Ej
2014-01-01
The GeneWeaver bipartite data model provides an efficient means to evaluate shared molecular components from sets derived across diverse species, disease states and biological processes. In order to adapt this model for examining related molecular components and biological networks, such as pathway or gene network data, we have developed a means to leverage the bipartite data structure to extract and analyze shared edges. Using the Pathway Commons database we demonstrate the ability to rapidly identify shared connected components among a diverse set of pathways. In addition, we illustrate how results from maximal bipartite discovery can be decomposed into hierarchical relationships, allowing shared pathway components to be mapped through various parent-child relationships to help visualization and discovery of emergent kernel driven relationships. Interrogating common relationships among biological networks and conventional GeneWeaver gene lists will increase functional specificity and reliability of the shared biological components. This approach enables self-organization of biological processes through shared biological networks.
Bi-partite and global entanglement in a many-particle system with collective spin coupling
Unanyan, R G; Fleischhauer, M
2004-01-01
Bipartite and global entanglement are analyzed for the ground state of a system of $N$ spin 1/2 particles interacting via a collective spin-spin coupling described by the Lipkin-Meshkov-Glick (LMG) Hamiltonian. Under certain conditions which includes the special case of a super-symmetry, the ground state can be constructed analytically. In the case of an anti-ferromagnetic coupling and for an even number of particles this state undergoes a smooth crossover as a function of the continuous anisotropy parameter $\\gamma $ from a separable ($\\gamma =\\infty $) to a maximally entangled many-particle state ($\\gamma =0$). From the analytic expression for the ground state, bipartite and global entanglement are calculated. In the thermodynamic limit a discontinuous change of the scaling behavior of the bipartite entanglement is found at the isotropy point $\\gamma =0$. For $% \\gamma =0$ the entanglement grows logarithmically with the system size with no upper bound, for $\\gamma \
BIPARTITE PATELLA IN 35-YEAR-OLD FITNESS INSTRUCTOR: A CASE REPORT
Zabierek, Jakub; Kwapisz, Adam; Domzalski, Marcin E
2016-01-01
Background and Purpose The patella plays an important role in knee biomechanics and provides anterior coverage of the knee joint. One to two percent of the population has an anatomical variant of patella called a bipartite patella that usually does not case pain. However, occasionally after injury or overuse during sport it can be a source of anterior knee pain. The purpose of this case report was to present a rare variant of bipartite patella and highlight conservative treatment of this condition. Study Design Case Report Case Description A 35-year-old female patient presented with persistent bilateral non-traumatic anterior knee pain of a six-year duration that was enhanced by strenuous kinds of sport activity. Standard radiographs and MRI revealed the presence of bipartite patella with medial pole cartilage edema bilaterally. Conservative care including physical therapy, extracorporeal shock wave therapy (ESWT), and viscosupplementation was utilized. Outcome After treatment VAS decreased to 0/10 from 5/10 in the left knee and 1/10 from 5/10 in the right knee. The Kujala Scores improved after treatment to 100 and 95 for the left and right knees respectively. The subject returned to full sport activity and work as a fitness instructor without pain and limitations. Discussion This case describes a rare finding of bilateral medial bipartite patella and the successful use of physical therapy with viscosupplementation in patellar pain caused by bipartite patella. It also supports the use of Extra Corporeal Shock Wave Therapy in bipartite patella pain as a supplement for therapy. Level of Evidence 4 PMID:27757290
Unique patellofemoral alignment in a patient with a symptomatic bipartite patella.
Ishikawa, Masakazu; Adachi, Nobuo; Deie, Masataka; Nakamae, Atsuo; Nakasa, Tomoyuki; Kamei, Goki; Takazawa, Kobun; Ochi, Mitsuo
2016-01-01
A symptomatic bipartite patella is rarely seen in athletic adolescents or young adults in daily clinical practice. To date, only a limited number of studies have focused on patellofemoral alignment. The current study revealed a unique patellofemoral alignment in a patient with a symptomatic bipartite patella. Twelve patients with 12 symptomatic bipartite patellae who underwent arthroscopic vastus lateralis release (VLR) were investigated (10 males and two females, age: 15.7±4.4years). The radiographic data of contralateral intact and affected knees were reviewed retrospectively. From the lateral- and skyline-view imaging, the following parameters were measured: the congruence angle (CA), the lateral patellofemoral angle (LPA), and the Caton-Deschamps index (CDI). As an additional parameter, the bipartite fragment angle (BFA) was evaluated against the main part of the patella in the skyline view. Compared with the contralateral side, the affected patellae were significantly medialized and laterally tilted (CA: P=0.019; LPA: P=0.016), although there was no significant difference in CDI (P=0.877). This patellar malalignment was found to significantly change after VLR (CA: P=0.001; LPA: P=0.003) and the patellar height was significantly lower than in the preoperative condition (P=0.016). In addition, the BFA significantly shifted to a higher degree after operation (P=0.001). Patients with symptomatic bipartite patellae presented significantly medialized and laterally tilted patellae compared with the contralateral intact side. This malalignment was corrected by VLR, and the alignment of the bipartite fragment was also significantly changed. Level IV, case series. Copyright © 2015 Elsevier B.V. All rights reserved.
Return to activity among athletes with a symptomatic bipartite patella: a systematic review.
Matic, George T; Flanigan, David C
2015-09-01
A bipartite patella is typically rare, but can become symptomatic during overuse activities such as those performed during athletic events. Therefore, this anomaly typically presents in the young, athletic population, often inhibiting athletic activities. Multiple treatment options exist, with nonsurgical management frequently adopted as the initial treatment of choice. To determine the most effective intervention in returning athletes with symptomatic bipartite patella to their prior activity levels. A systematic review of the literature was performed using PRISMA guidelines to identify studies reporting outcomes of athletes' ability to return to activity following treatment for a symptomatic bipartite patella. The type of intervention, type of bipartite classification, outcomes, and complications were recorded. Twenty articles with a total of 125 patients and 130 knees were identified and included in this review. A total of 105 athletes made a full return to athletic activity following treatment for their painful bipartite patella. One hundred athletes (85.5%) that underwent surgical treatment were able to make a full return to their sport without symptoms, although this varied by surgical procedure performed. Excision of the painful fragment produced the best results in returning athletes to sport, with 91% returning without symptoms and nine percent returning but with residual symptoms. Surgical treatments for symptomatic bipartite patellae are successful at returning athletes to their same level of play, and best outcomes are with excision of the fragment. These results are limited, however, due to the poor quality of original data given the rarity of the anomaly and the underrepresented conservative treatment group. Copyright © 2015 Elsevier B.V. All rights reserved.
Constant fan-in digital neural networks are VLSI-optimal
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1995-12-31
The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
High-energy heavy ion testing of VLSI devices for single event upsets and latch up
Indian Academy of Sciences (India)
S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra
2005-08-01
Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts
Scheibler, Robin; Chebira, Amina
2011-01-01
We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.
A rare cause of cervical spinal stenosis: posterior arch hypoplasia in a bipartite atlas
Energy Technology Data Exchange (ETDEWEB)
Atasoy, C. [Emek, Kirim Caddesi, Ankara (Turkey); Department of Radiology, Ankara University School of Medicine (Turkey); Fitoz, S.; Karan, B.; Erden, I.; Akyar, S. [Department of Radiology, Ankara University School of Medicine (Turkey)
2002-03-01
We describe CT and MRI of a previously unreported combination of atlantoaxial anomalies consisting of posterior arch hypoplasia in a bipartite atlas with an os odontoideum, in a 30-year-old woman presenting with neck and left arm pain. MRI showed the os odontoideum, marked stenosis of the spinal canal at the level of the atlas, with cord compression and evidence of myelopathy. CT revealed a bipartite atlas with midline clefts in anterior and posterior arches, thickening in the anterior arch and hypoplasia of the posterior arch with incurving of both hemiarches. Flexion and extension radiographs demonstrated atlantoaxial instability. (orig.)
Transformation of bipartite non-maximally entangled states into a tripartiteWstate in cavity QED
Indian Academy of Sciences (India)
ZANG XUE-PING; YANG MING; DU CHAO-QUN; WANG MIN; FANG SHU-DONG; CAO ZHUO-LIANG
2016-05-01
We present two schemes for transforming bipartite non-maximally entangled states into a W state in cavity QED system, by using highly detuned interactions and the resonant interactions between two-level atoms and a single-mode cavity field. A tri-atom W state can be generated by adjusting the interaction times between atoms and the cavity mode. These schemes demonstrate that two bipartite non-maximally entangled states can be merged into a maximally entangled W state. So the scheme can, in some sense, be regarded as an entanglement concentration process. The experimental feasibility of the schemes is also discussed.
Ordering non-bipartite unicyclic graphs with pendant vertices by the least Q-eigenvalue
Directory of Open Access Journals (Sweden)
Shu-Guang Guo
2016-05-01
Full Text Available Abstract A unicyclic graph is a connected graph whose number of edges is equal to the number of vertices. Fan et al. (Discrete Math. 313:903-909, 2013 and Liu et al. (Electron. J. Linear Algebra 26:333-344, 2013 determined, independently, the unique unicyclic graph whose least Q-eigenvalue attains the minimum among all non-bipartite unicyclic graphs of order n with k pendant vertices. In this paper, we extend their results and determine the first three non-bipartite unicyclic graphs of order n with k pendant vertices ordering by least Q-eigenvalue.
Bipartite and Tripartite Entanglement in a Three-Qubit Heisenberg Model
Institute of Scientific and Technical Information of China (English)
REN Jie; ZHU Shi-Qun
2006-01-01
The bipartite and tripartite entanglement in a three-qubit Heisenberg XY model with a nonuniformmagnetic field is studied. There are two or four peaks in the concurrence of the bipartite entanglement when the amplitudes of the magnetic fields are differently distributed between the three qubits. It is very interesting to note that there is no tangle of tripartite entanglement between the three qubits when the amplitudes of the magnetic fields are varied. However, the variation of the magnetic field direction can induce the tangle. The tangle is periodic about the angle between the magnetic field and the z axis of the spin.
Brunner, R.; Akis, R.; Ferry, D. K.; Kuchar, F.; Meisels, R.
2008-07-01
We discuss a quantum system coupled to the environment, composed of an open array of billiards (dots) in series. Beside pointer states occurring in individual dots, we observe sets of robust states which arise only in the array. We define these new states as bipartite pointer states, since they cannot be described in terms of simple linear combinations of robust single-dot states. The classical existence of bipartite pointer states is confirmed by comparing the quantum-mechanical and classical results. The ability of the robust states to create “offspring” indicates that quantum Darwinism is in action.
Traumatic separation of a type I patella bipartite in a sportsman
DEFF Research Database (Denmark)
Ottesen, Casper Smedegaard; Barfod, Kristoffer Weisskirchner; Holck, Kim
2014-01-01
fibrocartilage was found on both parts of the patella. Asymptomatic patella bi-partite was found on X-ray imaging of the patient's left knee, and he was diagnosed to have traumatic separation of a type I patella bipartite. The diagnosis was confirmed by surgical and radiological findings.......This is a case report of a 44-year-old sportsman who experi-enced acute onset of strong pain and loss of ability to extend his right knee during a game of beach volley. X-ray imaging showed a patella in two parts with rounded edges and with a diastasis of more than 2 cm. Intra-operatively atrophic...
Bipartite Networks of Wikipediaʼs Articles and Authors: a Meso-level Approach
DEFF Research Database (Denmark)
Jesus, Rut; Hansen-Schwartz, Martin; Jørgensen, Sune Lehmann
2009-01-01
This exploratory study investigates the bipartite network of articles linked by common editors in Wikipedia, 'The Free Encyclopedia that Anyone Can Edit'. We use the articles in the categories (to depth three) of Physics and Philosophy and extract and focus on significant editors (at least 7 or 10...... edits per each article). We construct a bipartite network, and from it, overlapping cliques of densely connected articles and editors. We cluster these densely connected cliques into larger modules to study examples of larger groups that display how volunteer editors flock around articles driven...
Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects
Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan
2016-03-01
In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.
Adaptive WTA with an analog VLSI neuromorphic learning chip.
Häfliger, Philipp
2007-03-01
In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.
VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement
Directory of Open Access Journals (Sweden)
Jigar Shah
2012-07-01
Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
Directory of Open Access Journals (Sweden)
D.Yammenavar
2011-08-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.
Design and Analog VLSI Implementation of Artificial Neural Network
Directory of Open Access Journals (Sweden)
Prof. Bapuray.D.Yammenavar
2011-07-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.
Efficient VLSI architecture of CAVLC decoder with power optimized
Institute of Scientific and Technical Information of China (English)
CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min
2009-01-01
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
A bioinspired collision detection algorithm for VLSI implementation
Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.
2005-06-01
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.
High performance genetic algorithm for VLSI circuit partitioning
Dinu, Simona
2016-12-01
Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.
Parallel VLSI design for the fast -D DWT core algorithm
Institute of Scientific and Technical Information of China (English)
WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong
2007-01-01
By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.
Directory of Open Access Journals (Sweden)
Sidorenko V. P.
2012-08-01
Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.
Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.
Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak
2007-07-23
In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.
The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits
Energy Technology Data Exchange (ETDEWEB)
Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))
1993-08-01
An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.
Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)
Institute of Scientific and Technical Information of China (English)
周涛; 吴行军; 白国强; 陈弘毅
2003-01-01
Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors
Directory of Open Access Journals (Sweden)
S. K. Nandy
1994-01-01
Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.
Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute
Williams, John
2008-01-01
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the
A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level
Institute of Scientific and Technical Information of China (English)
胡谋
1992-01-01
A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.
A class of inequalities inducing new separability criteria for bipartite quantum systems
Energy Technology Data Exchange (ETDEWEB)
Aniello, Paolo; Lupo, Cosmo [Dipartimento di Scienze Fisiche dell' Universita di Napoli ' Federico II' , via Cintia I-80126 Napoli (Italy)], E-mail: aniello@na.infn.it, E-mail: lupo@na.infn.it
2008-09-05
Inspired by the realignment or computable cross norm criterion, we present a new result about the characterization of quantum entanglement. Precisely, an interesting class of inequalities satisfied by all separable states of a bipartite quantum system is derived. These inequalities induce new separability criteria that generalize the realignment criterion.
Thyberg, Mikael; Arvidsson, Patrik; Thyberg, Ingrid; Nordenfelt, Lennart
2015-01-01
To argue for and propose bipartite concepts of functioning and disability, to tally with the structure of the ICF classification list, concepts of social models and clinical needs. The ICF concepts are discussed in relation to the history of ideas regarding disability concepts and the needs for such concepts in interdisciplinary rehabilitation. Bipartite concepts are presented; they refer to actual functioning, simply body functions/structures and participation, including functioning in standardized environments. Participation refers to actually performed "activities", with "activities" simply denoting things that people may do. Bipartite concepts are congruent with the ICF classification and the structure of social models of disability, suitable for clinical and interdisciplinary use and easy to understand. The issue of standardized environments represents a methodological issue rather than the conceptual issue of defining functioning and disability. An individual perspective on activity and activity limitations, i.e. the middle part of the tripartite ICF concept, is somewhat similar to concepts of traditional language that were regarded as too generalizing already in 1912, when the interactional concept of "disability in a social sense" was introduced in rehabilitation practices. Bipartite concepts of functioning and disability are recommended for interdisciplinary use of the ICF. The ICF classification is useful, but the ICF concept of activities in an individual perspective is confusing. We suggest a use of the term "activities" simply to denote things that people may do and "participation" to denote actually performed activities. Estimations of ability should be explicit about how they are related to environmental factors.
Institute of Scientific and Technical Information of China (English)
DONG Ping; LIN Ji-Cheng; YANG Ming; CAO Zhuo-Liang
2006-01-01
We propose a probabilistic scheme for realizing teleportation of bipartite photonic states using linear optical elements where only requires a two-photon Bell state used as quantum channel. It reduces the requirement of the entanglement of quantum channel, but requires an additional photon and an auxiliary maximally entangled photon pair locally.
Institute of Scientific and Technical Information of China (English)
Guo Qin
2007-01-01
A density matrix is usually obtained by solving the Bloch equation, however only a few Hamiltonians' density matrices can be analytically derived. The density matrix for two interacting particles with kinetic coupling is hard to derive by the usual method due to this coupling; this paper solves this problem by using the bipartite entangled state representation.
A simple model of bipartite cooperation for ecological and organizational networks.
Saavedra, Serguei; Reed-Tsochas, Felix; Uzzi, Brian
2009-01-22
In theoretical ecology, simple stochastic models that satisfy two basic conditions about the distribution of niche values and feeding ranges have proved successful in reproducing the overall structural properties of real food webs, using species richness and connectance as the only input parameters. Recently, more detailed models have incorporated higher levels of constraint in order to reproduce the actual links observed in real food webs. Here, building on previous stochastic models of consumer-resource interactions between species, we propose a highly parsimonious model that can reproduce the overall bipartite structure of cooperative partner-partner interactions, as exemplified by plant-animal mutualistic networks. Our stochastic model of bipartite cooperation uses simple specialization and interaction rules, and only requires three empirical input parameters. We test the bipartite cooperation model on ten large pollination data sets that have been compiled in the literature, and find that it successfully replicates the degree distribution, nestedness and modularity of the empirical networks. These properties are regarded as key to understanding cooperation in mutualistic networks. We also apply our model to an extensive data set of two classes of company engaged in joint production in the garment industry. Using the same metrics, we find that the network of manufacturer-contractor interactions exhibits similar structural patterns to plant-animal pollination networks. This surprising correspondence between ecological and organizational networks suggests that the simple rules of cooperation that generate bipartite networks may be generic, and could prove relevant in many different domains, ranging from biological systems to human society.
Modeling one-mode projection of bipartite networks by tagging vertex information
Qiao, Jian; Meng, Ying-Ying; Chen, Hsinchun; Huang, Hong-Qiao; Li, Guo-Ying
2016-09-01
Traditional one-mode projection models are less informative than their original bipartite networks. Hence, using such models cannot control the projection's structure freely. We proposed a new method for modeling the one-mode projection of bipartite networks, which thoroughly breaks through the limitations of the available one-mode projecting methods by tagging the vertex information of bipartite networks in their one-mode projections. We designed a one-mode collaboration network model by using the method presented in this paper. The simulation results show that our model matches three real networks very well and outperforms the available collaboration network models significantly, which reflects the idea that our method is ideal for modeling one-mode projection models of bipartite graphs and that our one-mode collaboration network model captures the crucial mechanisms of the three real systems. Our study reveals that size growth, individual aging, random collaboration, preferential collaboration, transitivity collaboration and multi-round collaboration are the crucial mechanisms of collaboration networks, and the lack of some of the crucial mechanisms is the main reason that the other available models do not perform as well as ours.
Practical and theoretical improvements for bipartite matching using the pseudoflow algorithm
Chandran, Bala G
2011-01-01
We show that the pseudoflow algorithm for maximum flow is particularly efficient for the bipartite matching problem both in theory and in practice. We develop several implementations of the pseudoflow algorithm for bipartite matching, and compare them over a wide set of benchmark instances to state-of-the-art implementations of push-relabel and augmenting path algorithms that are specifically designed to solve these problems. The experiments show that the pseudoflow variants are in most cases faster than the other algorithms. We also show that one particular implementation---the matching pseudoflow algorithm---is theoretically efficient. For a graph with $n$ nodes, $m$ arcs, $n_1$ the size of the smaller set in the bipartition, and the maximum matching value $\\kappa \\leq n_1$, the algorithm's complexity given input in the form of adjacency lists is $O(\\min{n_1\\kappa,m} + \\sqrt{\\kappa}\\min{\\kappa^2,m})$. Similar algorithmic ideas are shown to work for an adaptation of Hopcroft and Karp's bipartite matching alg...
Directory of Open Access Journals (Sweden)
Raf Guns
2016-09-01
Full Text Available Purpose: This study aims to answer the question to what extent different types of networks can be used to predict future co-authorship among authors. Design/methodology/approach: We compare three types of networks: unweighted networks, in which a link represents a past collaboration; weighted networks, in which links are weighted by the number of joint publications; and bipartite author-publication networks. The analysis investigates their relation to positive stability, as well as their potential in predicting links in future versions of the co-authorship network. Several hypotheses are tested. Findings: Among other results, we find that weighted networks do not automatically lead to better predictions. Bipartite networks, however, outperform unweighted networks in almost all cases. Research limitations: Only two relatively small case studies are considered. Practical implications: The study suggests that future link prediction studies on co-occurrence networks should consider using the bipartite network as a training network. Originality/value: This is the first systematic comparison of unweighted, weighted, and bipartite training networks in link prediction.
Bipartite qutrit local realist inequalities and the robustness of their quantum mechanical violation
Das, Debarshi; Datta, Shounak; Goswami, Suchetana; Majumdar, A. S.; Home, Dipankar
2017-10-01
Distinct from the type of local realist inequality (known as the Collins-Gisin-Linden-Massar-Popescu or CGLMP inequality) usually used for bipartite qutrit systems, we formulate a new set of local realist inequalities for bipartite qutrits by generalizing Wigner's argument that was originally formulated for the bipartite qubit singlet state. This treatment assumes existence of the overall joint probability distributions in the underlying stochastic hidden variable space for the measurement outcomes pertaining to the relevant trichotomic observables, satisfying the locality condition and yielding the measurable marginal probabilities. Such generalized Wigner inequalities (GWI) do not reduce to Bell-CHSH type inequalities by clubbing any two outcomes, and are violated by quantum mechanics (QM) for both the bipartite qutrit isotropic and singlet states using trichotomic observables defined by six-port beam splitter as well as by the spin-1 component observables. The efficacy of GWI is then probed in these cases by comparing the QM violation of GWI with that obtained for the CGLMP inequality. This comparison is done by incorporating white noise in the singlet and isotropic qutrit states. It is found that for the six-port beam splitter observables, QM violation of GWI is more robust than that of the CGLMP inequality for singlet qutrit states, while for isotropic qutrit states, QM violation of the CGLMP inequality is more robust. On the other hand, for the spin-1 component observables, QM violation of GWI is more robust for both the types of states considered.
On An Extremal Problem In The Class Of Bipartite 1-Planar Graphs
Directory of Open Access Journals (Sweden)
Czap Július
2016-02-01
Full Text Available A graph G = (V, E is called 1-planar if it admits a drawing in the plane such that each edge is crossed at most once. In this paper, we study bipartite 1-planar graphs with prescribed numbers of vertices in partite sets. Bipartite 1-planar graphs are known to have at most 3n − 8 edges, where n denotes the order of a graph. We show that maximal-size bipartite 1-planar graphs which are almost balanced have not significantly fewer edges than indicated by this upper bound, while the same is not true for unbalanced ones. We prove that the maximal possible size of bipartite 1-planar graphs whose one partite set is much smaller than the other one tends towards 2n rather than 3n. In particular, we prove that if the size of the smaller partite set is sublinear in n, then |E| = (2 + o(1n, while the same is not true otherwise.
The study of entanglement and teleportation of the harmonic oscillator bipartite coherent states
Directory of Open Access Journals (Sweden)
A Rabeie and
2015-01-01
Full Text Available In this paper, we reproduce the harmonic oscillator bipartite coherent states with imperfect cloning of coherent states. We show that if these entangled coherent states are embedded in a vacuum environment, their entanglement is degraded but not totally lost . Also, the optimal fidelity of these states is worked out for investigating their teleportation
A fast lightstripe rangefinding system with smart VLSI sensor
Gruss, Andrew; Carley, L. Richard; Kanade, Takeo
1989-01-01
The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.
A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar
Fang, W.
1994-01-01
For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.
Fully-depleted silicon-on-sapphire and its application to advanced VLSI design
Offord, Bruce W.
1992-01-01
In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.
VLSI chip-set for data compression using the Rice algorithm
Venbrux, J.; Liu, N.
1990-01-01
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
Synthesis of on-chip control circuits for mVLSI biochips
DEFF Research Database (Denmark)
Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin
2017-01-01
them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A
1999-01-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
Bayoumi, Magdy
As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.
1999-05-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
Richstein, James K.
1993-12-01
Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.
Kirk, David Blair
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for
CMOS VLSI Active-Pixel Sensor for Tracking
Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie
2004-01-01
An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The
Advanced plasma etching processes for dielectric materials in VLSI technology
Wang, Juan Juan
Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the
Exact and Scaling Form of the Bipartite Fidelity of the Infinite XXZ Chain
Weston, Robert
2012-01-01
We find an exact expression for the bipartite fidelity f=|'|^2, where |vac> is the vacuum eigenstate of an infinite-size antiferromagnetic XXZ chain and |vac>' is the vacuum eigenstate of an infinite-size XXZ chain which is split in two. We consider the quantity -ln(f) which has been put forward as a measure of quantum entanglement, and show that the large correlation length xi behaviour is consistent with a general conjecture -ln(f) ~ c/8 ln(xi), where c is the central charge of the UV conformal field theory (with c=1 for the XXZ chain). This behaviour is a natural extension of the existing conformal field theory prediction of -ln(f) ~ c/8 ln(L) for a length L bipartite system with 0<< L <
Cheng, Wei; Xu, Fang; Li, Hua; Wang, Gang
2014-04-01
Given the density matrix of a bipartite quantum state, could we decide whether it is separable, free entangled, or PPT entangled? Here, we give a negative answer to this question by providing a lot of concrete examples of density matrices, some of which are well known. We find that both separability and distillability are dependent on the decomposition of the density matrix. To be more specific, we show that if a given matrix is considered as the density operators of different composite systems, their entanglement properties might be different. In the case of density matrices, we can look them as both and bipartite quantum states and show that their entanglement properties (i.e., separable, free entangled, or PPT entangled) are completely irrelevant to each other.
Bipartite hallucal sesamoid bones: relationship with hallux valgus and metatarsal index
Energy Technology Data Exchange (ETDEWEB)
Munuera, Pedro V.; Dominguez, Gabriel [University of Seville, Department of Podiatrics, Seville (Spain); Centro Docente de Fisioterapia y Podologia, Departamento de Podologia, Seville (Spain); Reina, Maria; Trujillo, Piedad [Centro Docente de Fisioterapia y Podologia, Departamento de Podologia, Seville (Spain)
2007-11-15
The objective was to relate the incidence of the partition of the hallucal sesamoid bones to the size of the first metatarsal and the hallux valgus deformity. In a sample of 474 radiographs, the frequency of appearance of bipartite sesamoids was studied. The length and relative protrusion of the first metatarsal, and the hallux abductus angle, were measured and compared between the feet with and without sesamoid partition. The results showed that 14.6% of the feet studied had at least one partite sesamoid, that the sesamoid most frequently divided was the medial, and that unilateral partition was the most common. No difference was found in the incidence of partite sesamoids between men and women, or between left and right feet. Protrusion and length of the first metatarsal are greater in feet with partite sesamoids than in feet without this condition. A significantly higher incidence of bipartite medial sesamoid was obtained in feet with hallux valgus compared with normal feet. (orig.)
Inference of Extreme Synchrony with an Entropy Measure on a Bipartite Network
Sato, Aki-Hiro
2012-01-01
This article proposes a method to quantify the structure of a bipartite graph with a network entropy from a statistical--physical point of view. The network entropy of a bipartite graph with random links is computed from numerical simulation. As an application of the proposed method to analyze collective behavior, the affairs in which participants quote and trade in the foreign exchange market are quantified. The network entropy per node is found to correspond to the macroeconomic situation. A finite mixture of Gumbel distributions is used to fit with the empirical distribution for the minimum values of network entropy per node in each week. The mixture of Gumbel distributions with parameter estimates by segmentation procedure is verified by Kolmogorov--Smirnov test. The finite mixture of Gumbel distributions can extrapolate the probability of extreme events that have never been observed.
A polynomial algorithm for finding (g, f)-colorings orthogonal to stars in bipartite graphs
Institute of Scientific and Technical Information of China (English)
LIU; Guizhen; DENG; Xiaotie
2005-01-01
Let G be a bipartite graph with vertex set V(G) and edge set E(G), and let g and f be two nonnegative integer-valued functions defined on V(G) such that g(x) ≤f(x)for every vertex x of V(G). A(g,f)-coloring of G is a generalized edge-coloring in which each color appears at each vertex x at least g(x) and at most f(x) times. In this paper a polynomial algorithm to find a(g, f)-coloring of a bipartite graph with some constraints using the minimum number of colors is given. Furthermore, we show that the results in this paper are best possible.
On the Bipartite Consensus for Generic Linear Multiagent Systems With Input Saturation.
Qin, Jiahu; Fu, Weiming; Zheng, Wei Xing; Gao, Huijun
2016-10-11
The bipartite consensus problem for a group of homogeneous generic linear agents with input saturation under directed interaction topology is examined. It is established that if each agent is asymptotically null controllable with bounded controls and the interaction topology described by a signed digraph is structurally balanced and contains a spanning tree, then the semi-global bipartite consensus can be achieved for the linear multiagent system by a linear feedback controller with the control gain being designed via the low gain feedback technique. The convergence analysis of the proposed control strategy is performed by means of the Lyapunov method which can also specify the convergence rate. At last, the validity of the theoretical findings is demonstrated by two simulation examples.
Competition ability dependence on uniqueness in some collaboration-competition bipartite networks
Liu, Ai-Fen; Fu, Chun-Hua; He, Da-Ren
2010-01-01
Recently, our group quantitatively defined two quantities, "competition ability" and "uniqueness" (Chin. Phys. Lett. 26 (2009) 058901) for a kind of cooperation-competition bipartite networks, where "producers" produce some "products" and "output" them to a "market" to make competition. Factories, universities or restaurants can serve as the examples. In the letter we presented an analytical conclusion that the competition ability was linearly dependent on the uniqueness in the trivial cases, where both the "input quality" and "competition gain" obey normal distributions. The competition between Chinese regional universities was taken as examples. In this article we discuss the abnormal cases where competition gains show the distributions near to power laws. In addition, we extend the study onto all the cooperation-competition bipartite networks and therefore redefine the competition ability. The empirical investigation of the competition ability dependence on the uniqueness in 15 real world collaboration-com...
Co-clustering Analysis of Weblogs Using Bipartite Spectral Projection Approach
DEFF Research Database (Denmark)
Xu, Guandong; Zong, Yu; Dolog, Peter
2010-01-01
and content preference simultaneously. In this paper we will present an algorithm using bipartite spectral clustering to co-cluster Web users and pages. The usage data of users visiting Web sites is modeled as a bipartite graph and the spectral clustering is then applied to the graph representation of usage...... data. The proposed approach is evaluated by experiments performed on real datasets, and the impact of using various clustering algorithms is also investigated. Experimental results have demonstrated the employed method can effectively reveal the subset aggregates of Web users and pages which......Web clustering is an approach for aggregating Web objects into various groups according to underlying relationships among them. Finding co-clusters of Web objects is an interesting topic in the context of Web usage mining, which is able to capture the underlying user navigational interest...
Liu, Dang-Zheng
2009-01-01
Consider the model of bipartite entanglement for a random pure state emerging in quantum information and quantum chaos, corresponding to the fixed trace Laguerre unitary ensemble (LUE) in Random Matrix Theory. We focus on correlation functions of Schmidt eigenvalues for the model and prove universal limits of the correlation functions in the bulk and also at the soft and hard edges of the spectrum, as these for the LUE. Further we consider the bounded trace LUE and obtain the same universal limits.
Inferring monopartite projections of bipartite networks: an entropy-based approach
Saracco, Fabio; Straka, Mika J.; Di Clemente, Riccardo; Gabrielli, Andrea; Caldarelli, Guido; Squartini, Tiziano
2017-05-01
Bipartite networks are currently regarded as providing a major insight into the organization of many real-world systems, unveiling the mechanisms driving the interactions occurring between distinct groups of nodes. One of the most important issues encountered when modeling bipartite networks is devising a way to obtain a (monopartite) projection on the layer of interest, which preserves as much as possible the information encoded into the original bipartite structure. In the present paper we propose an algorithm to obtain statistically-validated projections of bipartite networks, according to which any two nodes sharing a statistically-significant number of neighbors are linked. Since assessing the statistical significance of nodes similarity requires a proper statistical benchmark, here we consider a set of four null models, defined within the exponential random graph framework. Our algorithm outputs a matrix of link-specific p-values, from which a validated projection is straightforwardly obtainable, upon running a multiple hypothesis testing procedure. Finally, we test our method on an economic network (i.e. the countries-products World Trade Web representation) and a social network (i.e. MovieLens, collecting the users’ ratings of a list of movies). In both cases non-trivial communities are detected: while projecting the World Trade Web on the countries layer reveals modules of similarly-industrialized nations, projecting it on the products layer allows communities characterized by an increasing level of complexity to be detected; in the second case, projecting MovieLens on the films layer allows clusters of movies whose affinity cannot be fully accounted for by genre similarity to be individuated.
Bipartite entanglement in systems of identical particles: the partial transposition criterion
Benatti, F; Marzolino, U
2012-01-01
We study bipartite entanglement in systems of N identical bosons distributed in M different modes. For such systems, a definition of separability not related to any a priori Hilbert space tensor product structure is needed and can be given in terms of commuting subalgebras of observables. Using this generalized notion of separability, we classify the states for which partial transposition turns out to be a necessary and sufficient condition for entanglement detection.
SibRank: Signed bipartite network analysis for neighbor-based collaborative ranking
Shams, Bita; Haratizadeh, Saman
2016-09-01
Collaborative ranking is an emerging field of recommender systems that utilizes users' preference data rather than rating values. Unfortunately, neighbor-based collaborative ranking has gained little attention despite its more flexibility and justifiability. This paper proposes a novel framework, called SibRank that seeks to improve the state of the art neighbor-based collaborative ranking methods. SibRank represents users' preferences as a signed bipartite network, and finds similar users, through a novel personalized ranking algorithm in signed networks.
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
We introduce the bipartite entangled states to present a quantum mechanical version of complex wavelet transform. Using the technique of integral within an ordered product of operators we show that the complex wavelet transform can be studied in terms of various quantum state vectors in two-mode Fock space. In this way the creterion for mother wavelet can be examined quantum-mechanically and therefore more deeply.
Realization of Bipartite Positive-Operator-Value Measurements of Two-Photon Polarization States
Institute of Scientific and Technical Information of China (English)
LIN Qing
2009-01-01
In this letter, we propose a scheme of a special quantum optical Fredkin gate assisted by optical manip-ulations and postselection from the coincidence measurements, and then modify it with cross-Kerr nonlinearities to be suitable for the realization of all possible positive operator-valued measurements of bipartite polarization states.This scheme is feasible in the lab with the current experimental technology.
Distillation of bi-partite entanglement from W state with cavity QED
Institute of Scientific and Technical Information of China (English)
Deng Li; Chen Ai-Xi; Chen De-Hai; Huang Ke-Lin
2008-01-01
Following the theoretical protocol described by Fortescue and Lo [Fortescue B and Lo H K 2007 Phys. Rev. Lett. 98 260501], we present a scheme in which one can distill maximally entangled bi-partite states from a tri-partite W state with cavity QED. Our scheme enables the concrete physical system to realize its protocol. In our scheme, the rate distillation also asymptotically approaches one. Based on the present cavity QED techniques, we discuss the experimental feasibility.
EPR Entangled States for Bipartite Kinematics and New Bosonic Representation of SU（2） Algebra
Institute of Scientific and Technical Information of China (English)
FANHong-Yi; CHENJun-Hua
2003-01-01
We find that the Einstein-Podolsky-Rosen (EPR) entangled state representation descr/bing bipartite kinematics is closely related to a new Bose operator realization of SU(2) Lie algebra. By virtue of the new realization some ttamiltonian eigenfunction equation can be directly converted to the generalized confluent equation in the EPR entangled state representation and its solution is obtainable. This thus provides a new approach for studying dynamics of angular momentum systems.
EPR Entangled States for Bipartite Kinematics and New Bosonic Representation of SU(2) Algebra
Institute of Scientific and Technical Information of China (English)
FAN Hong-Yi; CHEN Jun-Hua
2003-01-01
We find that the Einstein-Podolsky-Rosen (EPR) entangled state representation describing bipartite kinematics is closely related to a new Bose operator realization of SU(2) Lie algebra. By virtue of the new realization some Hamiltonian eigenfunction equation can be directly converted to the generalized confluent equation in the EPR entangled state representation and its solution is obtainable. This thus provides a new approach for studying dynamics of angular momentum systems.
Some Congruence Properties of a Restricted Bipartition Function cN(n
Directory of Open Access Journals (Sweden)
Nipen Saikia
2016-01-01
Full Text Available Let cN(n denote the number of bipartitions (λ,μ of a positive integer n subject to the restriction that each part of μ is divisible by N. In this paper, we prove some congruence properties of the function cN(n for N=7, 11, and 5l, for any integer l≥1, by employing Ramanujan’s theta-function identities.
Number of Spanning Trees of Different Products of Complete and Complete Bipartite Graphs
Directory of Open Access Journals (Sweden)
S. N. Daoud
2014-01-01
Full Text Available Spanning trees have been found to be structures of paramount importance in both theoretical and practical problems. In this paper we derive new formulas for the complexity, number of spanning trees, of some products of complete and complete bipartite graphs such as Cartesian product, normal product, composition product, tensor product, symmetric product, and strong sum, using linear algebra and matrix theory techniques.
Bipartite entanglement in a two-qubit Heisenberg XXZ chain under an inhomogeneous magnetic field
Institute of Scientific and Technical Information of China (English)
QIN Meng; TIAN Dong-Ping
2009-01-01
This paper investigates the bipartite entanglement of a two-qubit Heisenberg XXZ chain under an inhomogeneous magnetic field. By the concept of negativity, we find that the inhomogeneity of the magnetic field may induce entanglement and the critical magnetic field is independent of Jz. We also find that the entanglement is symmetric with respect to a zero magnetic field. The anisotropy parameter Jz may enhance the entanglement.
Institute of Scientific and Technical Information of China (English)
YUAN Hong-Chun; QI Kai-Guo
2005-01-01
We mostly investigate two schemes. One is to teleport a multi-mode W-type entangled coherent state using a peculiar bipartite entangled state as the quantum channel different from other proposals. Based on our formalism,teleporting multi-mode coherent state or squeezed state is also possible. Another is that the tripartite entangled state is used as the quantum channel of controlled teleportation of an arbitrary and unknown continuous variable in the case of three participators.
Detecting the bipartite World Trade Web evolution across 2007: a motifs-based analysis
Saracco, Fabio; Gabrielli, Andrea; Squartini, Tiziano
2015-01-01
In the present paper we employ the theoretical tools developed in network theory, in order to shed light on the response of world wide trade to the financial crisis of 2007. In particular, we have explored the evolution of the bipartite country-product World Trade Web across the years 1995-2010, monitoring the behaviour of the system both before and after 2007. Remarkably, our results indicate that, from 2003 on, the abundances of a recently-defined class of bipartite motifs assume values progressively closer to the ones predicted by a null model which preserves only basic features of the observed structure, completely randomizing the rest. In other words, as 2007 approaches the World Trade Web becomes more and more compatible with the picture of a bipartite network where correlations between countries and products are progressively lost. Moreover, the trends characterizing the z-scores of the considered family of motifs suggest that the most evident modification in the structure of the world trade network ca...
Bipartite graphs as models of population structures in evolutionary multiplayer games.
Directory of Open Access Journals (Sweden)
Jorge Peña
Full Text Available By combining evolutionary game theory and graph theory, "games on graphs" study the evolutionary dynamics of frequency-dependent selection in population structures modeled as geographical or social networks. Networks are usually represented by means of unipartite graphs, and social interactions by two-person games such as the famous prisoner's dilemma. Unipartite graphs have also been used for modeling interactions going beyond pairwise interactions. In this paper, we argue that bipartite graphs are a better alternative to unipartite graphs for describing population structures in evolutionary multiplayer games. To illustrate this point, we make use of bipartite graphs to investigate, by means of computer simulations, the evolution of cooperation under the conventional and the distributed N-person prisoner's dilemma. We show that several implicit assumptions arising from the standard approach based on unipartite graphs (such as the definition of replacement neighborhoods, the intertwining of individual and group diversity, and the large overlap of interaction neighborhoods can have a large impact on the resulting evolutionary dynamics. Our work provides a clear example of the importance of construction procedures in games on graphs, of the suitability of bigraphs and hypergraphs for computational modeling, and of the importance of concepts from social network analysis such as centrality, centralization and bipartite clustering for the understanding of dynamical processes occurring on networked population structures.
Information Filtering via Clustering Coefficients of User-Object Bipartite Networks
Guo, Qiang; Leng, Rui; Shi, Kerui; Liu, Jian-Guo
The clustering coefficient of user-object bipartite networks is presented to evaluate the overlap percentage of neighbors rating lists, which could be used to measure interest correlations among neighbor sets. The collaborative filtering (CF) information filtering algorithm evaluates a given user's interests in terms of his/her friends' opinions, which has become one of the most successful technologies for recommender systems. In this paper, different from the object clustering coefficient, users' clustering coefficients of user-object bipartite networks are introduced to improve the user similarity measurement. Numerical results for MovieLens and Netflix data sets show that users' clustering effects could enhance the algorithm performance. For MovieLens data set, the algorithmic accuracy, measured by the average ranking score, can be improved by 12.0% and the diversity could be improved by 18.2% and reach 0.649 when the recommendation list equals to 50. For Netflix data set, the accuracy could be improved by 14.5% at the optimal case and the popularity could be reduced by 13.4% comparing with the standard CF algorithm. Finally, we investigate the sparsity effect on the performance. This work indicates the user clustering coefficients is an effective factor to measure the user similarity, meanwhile statistical properties of user-object bipartite networks should be investigated to estimate users' tastes.
Perfect Matchings in O(n \\log n) Time in Regular Bipartite Graphs
Goel, Ashish; Khanna, Sanjeev
2009-01-01
In this paper we consider the well-studied problem of finding a perfect matching in a d-regular bipartite graph on 2n nodes with m=nd edges. The best-known algorithm for general bipartite graphs (due to Hopcroft and Karp) takes time O(m\\sqrt{n}). In regular bipartite graphs, however, a matching is known to be computable in O(m) time (due to Cole, Ost and Schirra). In a recent line of work by Goel, Kapralov and Khanna the O(m) time algorithm was improved first to \\tilde O(min{m, n^{2.5}/d}) and then to \\tilde O(min{m, n^2/d}). It was also shown that the latter algorithm is optimal up to polylogarithmic factors among all algorithms that use non-adaptive uniform sampling to reduce the size of the graph as a first step. In this paper, we give a randomized algorithm that finds a perfect matching in a d-regular graph and runs in O(n\\log n) time (both in expectation and with high probability). The algorithm performs an appropriately truncated random walk on a modified graph to successively find augmenting paths. Our...
A generalization of Hopcroft-Karp algorithm for semi-matchings and covers in bipartite graphs
Katrenic, Ján
2011-01-01
The aim of the paper is to study a generalized problem of the classical matching problem in bipartite graphs. A {\\em semi-matching} in a bipartite graph $G = (U \\cup V, E)$ is a set of edges $M \\subseteq E$ such that each vertex in $U$ is incident to at most one edge in $M$. An $(f,g)$-cover in a bipartite graph $G=(U \\cup V,E)$ is a set of edges $M \\subseteq E$ such that each vertex $u\\in U$ is incident with at most $f(u)$ edges from $M$, and each vertex $v\\in V$ in incident with at most $g(v)$ edges from $M$. We provide an algorithm which finds a maximum semi-matching in running time $O(\\sqrt{n} m)$ and solves the general $(f,g)$-cover in running time $O(m^{3/2})$. Semi-matchings and $(f,g)$-covers have various applications in load balancing and routing problems.
Online Vertex-Weighted Bipartite Matching and Single-bid Budgeted Allocations
Aggarwal, Gagan; Karande, Chinmay; Mehta, Aranyak
2010-01-01
We study the following vertex-weighted online bipartite matching problem: $G(U, V, E)$ is a bipartite graph. The vertices in $U$ have weights and are known ahead of time, while the vertices in $V$ arrive online in an arbitrary order and have to be matched upon arrival. The goal is to maximize the sum of weights of the matched vertices in $U$. When all the weights are equal, this reduces to the classic \\emph{online bipartite matching} problem for which Karp, Vazirani and Vazirani gave an optimal $\\left(1-\\frac{1}{e}\\right)$-competitive algorithm in their seminal work~\\cite{KVV90}. Our main result is an optimal $\\left(1-\\frac{1}{e}\\right)$-competitive randomized algorithm for general vertex weights. We use \\emph{random perturbations} of weights by appropriately chosen multiplicative factors. Our solution constitutes the first known generalization of the algorithm in~\\cite{KVV90} in this model and provides new insights into the role of randomization in online allocation problems. It also effectively solves the p...
Harrison, R R; Koch, C
1999-10-01
Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.
A cost-effective methodology for the design of massively-parallel VLSI functional units
Venkateswaran, N.; Sriram, G.; Desouza, J.
1993-01-01
In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.
Xiao, Feng; Alameh, Kamal; Lee, Yong Tak
2009-12-07
A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.
VLSI architectures for computing multiplications and inverses in GF(2-m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.
1983-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
VLSI architectures for computing multiplications and inverses in GF(2m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.
1985-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam
2011-12-01
Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.
Energy Technology Data Exchange (ETDEWEB)
Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)
2014-01-31
The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.
Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications
Directory of Open Access Journals (Sweden)
P. Mohan Krishna
2014-04-01
Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.
Las Vegas is better than determinism in VLSI and distributed computing
DEFF Research Database (Denmark)
Mehlhorn, Kurt; Schmidt, Erik Meineche
1982-01-01
to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...
International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking
Shirur, Yasha; Prasad, Rekha
2013-01-01
This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.
Current-mode subthreshold MOS circuits for analog VLSI neural systems
Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.
1991-03-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Current-mode subthreshold MOS circuits for analog VLSI neural systems.
Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K
1991-01-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris; Verbauwhede, Ingrid
2007-01-01
Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...
The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter
2001-09-01
December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60
Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.
Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz
2010-01-01
Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.
VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.
Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram
2010-01-01
In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.
Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W
2006-01-01
We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.
Directory of Open Access Journals (Sweden)
Rachmad Vidya Wicaksana Putra
2016-06-01
Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
REGIONAL WEBGIS USER ACCESS PATTERNS BASED ON A WEIGHTED BIPARTITE NETWORK
Directory of Open Access Journals (Sweden)
R. Li
2015-07-01
Full Text Available With the rapid development of geographic information services, Web Geographic Information Systems (WebGIS have become an indispensable part of everyday life; correspondingly, map search engines have become extremely popular with users and WebGIS sites receive a massive volume of requests for access. These WebGIS users and the content accessed have regional characteristics; to understand regional patterns, we mined regional WebGIS user access patterns based on a weighted bipartite network. We first established a weighted bipartite network model for regional user access to a WebGIS. Then, based on the massive user WebGIS access logs, we clustered geographic information accessed and thereby identified hot access areas. Finally we quantitatively analyzed the access interests of regional users and the visitation volume characteristics of regional user access to these hot access areas in terms of user access permeability, user usage rate, and user access viscosity. Our research results show that regional user access to WebGIS is spatially aggregated, and the hot access areas that regional users accessed are associated with specific periods of time. Most regional user contact with hot accessed areas is variable and intermittent but for some users, their access to certain areas is continuous as it is associated with ongoing or recurrent objectives. The weighted bipartite network model for regional user WebGIS access provides a valid analysis method for studying user behaviour in WebGIS and the proposed access pattern exhibits access interest of regional user is spatiotemporal aggregated and presents a heavy-tailed distribution. Understanding user access patterns is good for WebGIS providers and supports better operational decision-making, and helpful for developers when optimizing WebGIS system architecture and deployment, so as to improve the user experience and to expand the popularity of WebGIS.
Regional Webgis User Access Patterns Based on a Weighted Bipartite Network
Li, R.; Shen, Y.; Huang, W.; Wu, H.
2015-07-01
With the rapid development of geographic information services, Web Geographic Information Systems (WebGIS) have become an indispensable part of everyday life; correspondingly, map search engines have become extremely popular with users and WebGIS sites receive a massive volume of requests for access. These WebGIS users and the content accessed have regional characteristics; to understand regional patterns, we mined regional WebGIS user access patterns based on a weighted bipartite network. We first established a weighted bipartite network model for regional user access to a WebGIS. Then, based on the massive user WebGIS access logs, we clustered geographic information accessed and thereby identified hot access areas. Finally we quantitatively analyzed the access interests of regional users and the visitation volume characteristics of regional user access to these hot access areas in terms of user access permeability, user usage rate, and user access viscosity. Our research results show that regional user access to WebGIS is spatially aggregated, and the hot access areas that regional users accessed are associated with specific periods of time. Most regional user contact with hot accessed areas is variable and intermittent but for some users, their access to certain areas is continuous as it is associated with ongoing or recurrent objectives. The weighted bipartite network model for regional user WebGIS access provides a valid analysis method for studying user behaviour in WebGIS and the proposed access pattern exhibits access interest of regional user is spatiotemporal aggregated and presents a heavy-tailed distribution. Understanding user access patterns is good for WebGIS providers and supports better operational decision-making, and helpful for developers when optimizing WebGIS system architecture and deployment, so as to improve the user experience and to expand the popularity of WebGIS.
Institute of Scientific and Technical Information of China (English)
Qin Meng; Tian Dong-Ping
2009-01-01
This paper investigates bipartite entanglement of a two-qubit system with anisotropic couplings under all inhomogeneous magnetic field.This work is mainly to investigate the characteristics of a Heisenberg XYZ chain and obtains some meaningful results.By the concept of negativity,it finds that the inhomogeneity of magnetic field may induce entanglement and the critical magnetic field is independent of Jz.The inhomogeneous magnetic field can increase the value of critical magnetic field Bc.It also finds that the magnetic field not only suppresses the entanglement but also can induce it to revival for some time.
Geometric measure of quantum discord for an arbitrary state of a bipartite quantum system
Hassan, Ali Saif M; Joag, Pramod S
2010-01-01
Quantum discord, as introduced by Olliver and Zurek [Phys. Rev. Lett. \\textbf{88}, 017901 (2001)], is a measure of the discrepancy between quantum versions of two classically equivalent expressions for mutual information. Dakic, Vedral, and Brukner [arXiv:1004.0190 (2010)] introduced a geometric measure of quantum discord and derived an explicit formula for any two-qubit state. Luo and Fu [Phys. Rev. A \\textbf{82}, 034302 (2010)] introduced another form for geometric measure of quantum discord. We find an exact formula for the geometric measure of quantum discord for an arbitrary state of a $m\\times n$ bipartite quantum system.
Robust tripartite-to-bipartite entanglement localization by weak measurements and reversal
Yao, Chunmei; Ma, Zhi-Hao; Chen, Zhi-Hua; Serafini, Alessio
2012-08-01
We propose a robust and efficient approach for tripartite-to-bipartite entanglement localization. By using weak measurements and quantum measurement reversal, an almost maximal entangled state shared by two parties can be generated with the assistance of the third party by local quantum operations and classical communication from a W-like state. We show that this approach works well in the presence of losses and phase diffusion. Our method provides an active way to fight against decoherence, and might help for quantum communication and distributed quantum computation.
Complete genome sequences of two novel bipartite begomoviruses infecting common bean in Cuba.
Chang-Sidorchuk, Lidia; González-Alvarez, Heidy; Navas-Castillo, Jesús; Fiallo-Olivé, Elvira; Martínez-Zubiaur, Yamila
2017-05-01
The common bean is a host for a large number of begomoviruses (genus Begomovirus, family Geminiviridae) in the New World. Based on the current taxonomic criteria established for the genus Begomovirus, two new members of this genus infecting common bean (Phaseolus vulgaris) in Cuba are herein reported. The cloned bipartite genomes, composed of DNA-A and DNA-B, showed the typical organization of the New World begomoviruses. We propose the names common bean severe mosaic virus and common bean mottle virus for the new begomovirus species.
Kumar, Asutosh; Dhar, Himadri Shekhar; Prabhu, R.; Sen(De), Aditi; Sen, Ujjwal
2017-05-01
Monogamy is a nonclassical property that limits the distribution of quantum correlation among subparts of a multiparty system. We show that monogamy scores for different quantum correlation measures are bounded above by functions of genuine multipartite entanglement for a large majority of pure multiqubit states. The bound is universal for all three-qubit pure states. We derive necessary conditions to characterize the states that violate the bound, which can also be observed by numerical simulation for a small set of states, generated Haar uniformly. The results indicate that genuine multipartite entanglement restricts the distribution of bipartite quantum correlations in a multiparty system.
Bipartite entanglement entropy in massive two-dimensional quantum field theory.
Doyon, Benjamin
2009-01-23
Recently, Cardy, Castro Alvaredo, and the author obtained the first exponential correction to saturation of the bipartite entanglement entropy at large region lengths in massive two-dimensional integrable quantum field theory. It depends only on the particle content of the model, and not on the way particles scatter. Based on general analyticity arguments for form factors, we propose that this result is universal, and holds for any massive two-dimensional model (also out of integrability). We suggest a link of this result with counting pair creations far in the past.
Strong monogamy of bipartite and genuine multipartite entanglement: the Gaussian case.
Adesso, Gerardo; Illuminati, Fabrizio
2007-10-12
We demonstrate the existence of general constraints on distributed quantum correlations, which impose a trade-off on bipartite and multipartite entanglement at once. For all N-mode Gaussian states under permutation invariance, we establish exactly a monogamy inequality, stronger than the traditional one, that by recursion defines a proper measure of genuine N-partite entanglement. Strong monogamy holds as well for subsystems of arbitrary size, and the emerging multipartite entanglement measure is found to be scale invariant. We unveil its operational connection with the optimal fidelity of continuous variable teleportation networks.
Assadi, Leila; Jafarpour, Mojtaba
2016-07-01
We use concurrence to study bipartite entanglement, Meyer-Wallach measure and its generalizations to study multi-partite entanglement and MABK and SASA inequalities to study the non-local properties of the 4-qubit entangled graph states, quantitatively. Then, we present 3 classifications, each one in accordance with one of the aforementioned properties. We also observe that the classification according to multipartite entanglement does exactly coincide with that according to nonlocal properties, but does not match with that according to bipartite entanglement. This observation signifies the fact that non-locality and multipartite entanglement enjoy the same basic underlying principles, while bipartite entanglement may not reveal the non-locality issue in its entirety.
Lanza, Val F; Baquero, Fernando; de la Cruz, Fernando; Coque, Teresa M
2017-01-15
AcCNET (Accessory genome Constellation Network) is a Perl application that aims to compare accessory genomes of a large number of genomic units, both at qualitative and quantitative levels. Using the proteomes extracted from the analysed genomes, AcCNET creates a bipartite network compatible with standard network analysis platforms. AcCNET allows merging phylogenetic and functional information about the concerned genomes, thus improving the capability of current methods of network analysis. The AcCNET bipartite network opens a new perspective to explore the pangenome of bacterial species, focusing on the accessory genome behind the idiosyncrasy of a particular strain and/or population.
Naparstek, Oshri; Leshem, Amir
2013-01-01
In this paper we analyze the expected time complexity of the auction algorithm for the matching problem on random bipartite graphs. We prove that the expected time complexity of the auction algorithm for bipartite matching is $O\\left(\\frac{N\\log^2(N)}{\\log\\left(Np\\right)}\\right)$ on sequential machines. This is equivalent to other augmenting path algorithms such as the HK algorithm. Furthermore, we show that the algorithm can be implemented on parallel machines with $O(\\log(N))$ processors an...
Juswardy, Budi; Xiao, Feng; Alameh, Kamal
2009-03-16
This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.
Directory of Open Access Journals (Sweden)
Md Mobarok Hossain Rubel
2016-07-01
Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.
Directory of Open Access Journals (Sweden)
Miss. Rachana R. Patil
2015-01-01
Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology
Directory of Open Access Journals (Sweden)
Feilong Tang
2010-01-01
Full Text Available Mobile and wireless networks are the integrant infrastructure of mobile and pervasive computing that aims at providing transparent and preferred information and services for people anytime anywhere. In such environments, end-to-end network bandwidth is crucial to improve user's transparent experience when providing on-demand services such as mobile video playing. As a result, powerful computing power is required for networked nodes, especially for routers. General-purpose processors cannot meet such requirements due to their limited processing ability, and poor programmability and scalability. Intel's network processor IXP is specially designed for fast packet processing to achieve a broad bandwidth. IXP provides a large number of registers to reduce the number of memory accesses. Registers in an IXP are physically partitioned as two banks so that two source operands in an instruction have to come from the two banks respectively, which makes the IXP register allocation tricky and different from conventional ones. In this paper, we investigate an approach for efficiently generating balanced bipartite graph and register allocation algorithms for the dual-bank register allocation in IXPs. The paper presents a graph uniform 2-way partition algorithm (FPT, which provides an optimal solution to the graph partition, and a heuristic algorithm for generating balanced bipartite graph. Finally, we design a framework for IXP register allocation. Experimental results demonstrate the framework and the algorithms are efficient in register allocation for IXP network processors.
Simple Markov-chain algorithms for generating bipartite graphs and tournaments
Energy Technology Data Exchange (ETDEWEB)
Kannan, R.; Vempala, S. [Carnegie Mellon Univ., Pittsburgh, PA (United States); Tetali, P. [Georgia Institute of Technology, Atlanta, GA (United States)
1997-06-01
We consider two problems: randomly generating labeled bipartite graphs with a given degree sequence and randomly generating labeled tournaments with a given score sequence. We analyze simple Markov chains for both problems. For the first problem, we cannot prove that our chain is rapidly mixing in general, but in the (near-) regular case, i.e. when all the degrees are (almost) equal, we give a proof of rapid mixing. Our methods also apply to the corresponding problem for general (nonbipartite) regular graphs which was studied earlier by several researchers. One significant difference in our approach is that our chain has one state for every graph (or bipartite graph) with the given degree sequence; in particular, there are no auxiliary states as in the chain used by Jerrum and Sinclair. For the problem of generating tournaments, we are able to prove that our Markov chain on tournaments is rapidly mixing, if the score sequence is near-regular. The proof techniques we use for the two problems are similar.
Li, Yinan; Wang, Xin; Duan, Runyao
2017-05-01
A bipartite subspace S is called strongly positive-partial-transpose (PPT) unextendible if for every positive integer k , there is no PPT operator supporting on the orthogonal complement of S⊗k. We show that a subspace is strongly PPT unextendible if it contains a PPT-definite operator (a positive semidefinite operator whose partial transpose is positive definite). Based on these, we are able to propose a simple criterion for verifying whether a set of bipartite orthogonal quantum states is indistinguishable by PPT operations in the many-copy scenario. Utilizing this criterion, we further point out that any entangled pure state and its orthogonal complement cannot be distinguished by PPT operations in the many-copy scenario. On the other hand, we investigate that the minimum dimension of strongly PPT-unextendible subspaces in an m ⊗n system is m +n -1 , which involves a generalization of the result that non-positive-partial-transpose subspaces can be as large as any entangled subspace [N. Johnston, Phys. Rev. A 87, 064302 (2013), 10.1103/PhysRevA.87.064302].
Extensive mis-splicing of a bi-partite plant mitochondrial group II intron.
Elina, Helen; Brown, Gregory G
2010-01-01
Expression of the seed plant mitochondrial nad5 gene involves two trans-splicing events that remove fragmented group II introns and join the small, central exon c to exons b and d. We show that in both monocot and eudicot plants, extensive mis-splicing of the bi-partite intron 2 takes place, resulting in the formation of aberrantly spliced products in which exon c is joined to various sites within exon b. These mis-spliced products accumulate to levels comparable to or greater than that of the correctly spliced mRNA. We suggest that mis-splicing may result from folding constraints imposed on intron 2 by base-pairing between exon a and a portion of the bi-partite intron 3 downstream of exon c. Consistent with this hypothesis, we find that mis-splicing does not occur in Oenothera mitochondria, where intron 3 is further fragmented such that the predicted base-pairing region is not covalently linked to exon c. Our findings suggest that intron fragmentation may lead to mis-splicing, which may be corrected by further intron fragmentation.
Improving Accuracy and Scalability of Personal Recommendation Based on Bipartite Network Projection
Directory of Open Access Journals (Sweden)
Fengjing Yin
2014-01-01
Full Text Available Bipartite network projection method has been recently employed for personal recommendation. It constructs a bipartite network between users and items. Treating user taste for items as resource in the network, we allocate the resource via links between user nodes and item nodes. However, the taste model employed by existing algorithms cannot differentiate “dislike” and “unrated” cases implied by user ratings. Moreover, the distribution of resource is solely based on node degrees, ignoring the different transfer rates of the links. To enhance the performance, this paper devises a negative-aware and rating-integrated algorithm on top of the baseline algorithm. It enriches the current user taste model to encompass “like,” “dislike,” and “unrated” information from users. Furthermore, in the resource distribution stage, we propose to initialize the resource allocation according to user ratings, which also determines the resource transfer rates on links afterward. Additionally, we also present a scalable implementation in the MapReduce framework by parallelizing the algorithm. Extensive experiments conducted on real data validate the effectiveness and efficiency of the proposed algorithms.
Some Applications of Spanning Trees in Complete and Complete Bipartite Graphs
Directory of Open Access Journals (Sweden)
S. N. Daoud
2012-01-01
Full Text Available Problem statement: The number of spanning trees τ(G in graphs (networks is an important invariant, it is also an important measure of reliability of a network. Approach: Using linear algebra and matrix analysis techniques to evaluate the associated determinants. Results: In this study we derive simple formulas for the number of spanning trees of complete graph Kn and complete bipartite graph Kn,m and some of their applications. A large number of theorems of number of the spanning trees of known operations on complete graph Kn and complete bipartite graph Kn,m are obtained. Conclusion: The evaluation of number of spanning trees is not only interesting from a mathematical (computational perspective, but also, it is an important measure of reliability of a network and designing electrical circuits. Some computationally hard problems such as the travelling salesman problem can be solved approximately by using spanning trees. Due to the high dependence of the network design and reliability on the graph theory we introduced the following important theorems and lemmas and their proofs.
A mathematical model for generating bipartite graphs and its application to protein networks
Energy Technology Data Exchange (ETDEWEB)
Nacher, J C [Department of Complex Systems, Future University-Hakodate (Japan); Ochiai, T [Faculty of Engineering, Toyama Prefectural University (Japan); Hayashida, M; Akutsu, T [Bioinformatics Center, Institute for Chemical Research, Kyoto University (Japan)
2009-12-04
Complex systems arise in many different contexts from large communication systems and transportation infrastructures to molecular biology. Most of these systems can be organized into networks composed of nodes and interacting edges. Here, we present a theoretical model that constructs bipartite networks with the particular feature that the degree distribution can be tuned depending on the probability rate of fundamental processes. We then use this model to investigate protein-domain networks. A protein can be composed of up to hundreds of domains. Each domain represents a conserved sequence segment with specific functional tasks. We analyze the distribution of domains in Homo sapiens and Arabidopsis thaliana organisms and the statistical analysis shows that while (a) the number of domain types shared by k proteins exhibits a power-law distribution, (b) the number of proteins composed of k types of domains decays as an exponential distribution. The proposed mathematical model generates bipartite graphs and predicts the emergence of this mixing of (a) power-law and (b) exponential distributions. Our theoretical and computational results show that this model requires (1) growth process and (2) copy mechanism.
Directory of Open Access Journals (Sweden)
Zafar Yusuf
2007-01-01
Full Text Available Abstract Whitefly-transmitted geminiviruses (genus Begomovirus are phytopathogens that cause heavy losses to crops worldwide. Efforts to engineer resistance against these viruses are focused mainly on silencing of complementary-sense virus genes involved in virus replication. Here we have targeted a virion-sense gene (AV2 to develop resistance against Tomato leaf curl New Delhi virus, a bipartite begomovirus prevalent throughout the Indian subcontinent. We show that tobacco plants transformed with an antisense construct targeting this gene are resistant to the virus. Following challenged with the virus, transgenic plants remained symptomless, although viral DNA could be detected in some plants by PCR. This is the first report of transgenic resistance against a bipartite begomovirus obtained by targeting a virion-sense gene. The relatively conserved nature of the gene suggests that the technology may be useful to develop broad-spectrum resistance which is required because of the fact that plants are often infected with multiple begomoviruses in the field.
VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network
Hsieh, Hung-Yi; Tang, Kea-Tiong
2011-11-01
This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.
Fey, D; Kasche, B; Burkert, C; Tschäche, O
1998-01-10
A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.
VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders
Directory of Open Access Journals (Sweden)
Georgios Passas
2012-01-01
Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.
New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Directory of Open Access Journals (Sweden)
M. V. Atre
1995-07-01
Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.
Spike-based VLSI modeling of the ILD system in the echolocating bat.
Horiuchi, T; Hynna, K
2001-01-01
The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.
Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.
Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert
2004-01-01
Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.
VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.
1985-08-01
purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be
Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.
1984-10-01
analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI
VLSI Structure for an All Digital Receiver for CDMA PABX Handset
Institute of Scientific and Technical Information of China (English)
ZhouShidong; BiGuangguo
1995-01-01
In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.
Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
Directory of Open Access Journals (Sweden)
Ankush S. Patharkar
2014-07-01
Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S.
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.
Vlsi implementation of flexible architecture for decision tree classification in data mining
Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak
2017-07-01
The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.
Lari, Behzad
2011-01-01
This is a thesis submitted to university of Pune, India, for the Ph.D. degree. This work deals with entanglement production in two qubit, two qutrit and three qubit systems, entanglement in indistinguishable fermionic systems, quantum discord in a Heisenberg chain and geometric measure of quantum discord in an arbitrary state of a bipartite quantum system.
Distinct evolutionary histories of the DNA-A and DNA-B components of bipartite begomoviruses
Directory of Open Access Journals (Sweden)
Nawaz-ul-Rehman Muhammad
2010-04-01
Full Text Available Abstract Background Viruses of the genus Begomovirus (family Geminiviridae have genomes consisting of either one or two genomic components. The component of bipartite begomoviruses known as DNA-A is homologous to the genomes of all geminiviruses and encodes proteins required for replication, control of gene expression, overcoming host defenses, encapsidation and insect transmission. The second component, referred to as DNA-B, encodes two proteins with functions in intra- and intercellular movement in host plants. The origin of the DNA-B component remains unclear. The study described here was initiated to investigate the relationship between the DNA-A and DNA-B components of bipartite begomoviruses with a view to unraveling their evolutionary histories and providing information on the possible origin of the DNA-B component. Results Comparative phylogenetic and exhaustive pairwise sequence comparison of all DNA-A and DNA-B components of begomoviruses demonstrates that the two molecules have very distinct molecular evolutionary histories and likely are under very different evolutionary pressures. The analysis highlights that component exchange has played a far greater role in diversification of begomoviruses than previously suspected, although there are distinct differences in the apparent ability of different groups of viruses to utilize this "sexual" mechanism of genetic exchange. Additionally we explore the hypothesis that DNA-B originated as a satellite that was captured by the monopartite progenitor of all extant bipartite begomoviruses and subsequently evolved to become the integral (essential genome component that we recognize today. The situation with present-day satellites associated with begomoviruses provides some clues to the processes and selection pressures that may have led to the "domestication" of a wild progenitor of the DNA-B component. Conclusions The analysis has highlighted the greater genetic variation of DNA-B components, in
Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2011-03-01
Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.
Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene
2004-05-01
We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.
Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.
Yu, Theodore; Cauwenberghs, Gert
2010-06-01
We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.
On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
Lin, Meng-Chun; Dung, Lan-Rong
2008-02-01
This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.
Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.
Mitra, S; Fusi, S; Indiveri, G
2009-02-01
Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.
Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing
Khachab, Nabil Ibrahim
1990-01-01
The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.
New VLSI smart sensor for collision avoidance inspired by insect vision
Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran
1995-01-01
An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.
VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces
Wooley, Bruce A.
1991-04-01
The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.
A multi coding technique to reduce transition activity in VLSI circuits
Vithyalakshmi, N.; Rajaram, M.
2014-02-01
Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.
The digi-neocognitron: a digital neocognitron neural network model for VLSI.
White, B A; Elmasry, M I
1992-01-01
One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.
Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2010-06-01
Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design
VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems
Energy Technology Data Exchange (ETDEWEB)
Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)
2009-07-15
The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.
Formal Methods for Reverse Engineering Gate-Level Netlists
2013-12-18
is not very much prior CHAPTER 1. INTRODUCTION 5 work in this area. Mohnke and Malik [26] present a BDD -based approach for comparing two combinational...fact, when the vertices represent delta events, our approach can identify corresponding signals even if they are implemented with opposite polarities in
Bayesian latent feature modeling for modeling bipartite networks with overlapping groups
DEFF Research Database (Denmark)
Jørgensen, Philip H.; Mørup, Morten; Schmidt, Mikkel Nørgaard;
2016-01-01
Bi-partite networks are commonly modelled using latent class or latent feature models. Whereas the existing latent class models admit marginalization of parameters specifying the strength of interaction between groups, existing latent feature models do not admit analytical marginalization...... of the parameters accounting for the interaction strength within the feature representation. We propose a new binary latent feature model that admits analytical marginalization of interaction strengths such that model inference reduces to assigning nodes to latent features. We propose a constraint inspired...... to the infinite relational model and the infinite Bernoulli mixture model. We find that the model provides a new latent feature representation of structure while in link-prediction performing close to existing models. Our current extension of the notion of communities and collapsed inference to binary latent...
Bipartite Producer-Consumer Networks and the Size Distribution of Firms
Dahui, W; Zengru, D; Dahui, Wang; Li, Zhou; Zengru, Di
2005-01-01
A bipartite producer-consumer network is constructed to describe the industrial structure. The edges from consumer to producer represent the choices of the consumer for the final products and the degree of producer can represent its market share. So the size distribution of firms can be characterized by producer's degree distribution. The probability for a producer receiving a new consumption is determined by its competency described by initial attractiveness and the self-reinforcing mechanism in the competition described by preferential attachment. The cases with constant total consumption and with growing market are studied. The following results are obtained: 1, Without market growth and a uniform initial attractiveness $a$, the final distribution of firm sizes is Gamma distribution for $a>1$ and is exponential for $a=1$. If $a<1$, the distribution is power in small size and exponential in upper tail; 2, For a growing market, the size distribution of firms obeys the power law. The exponent is affected b...
Neural Correlates of Phrase Rhythm: An EEG Study of Bipartite vs. Rondo Sonata Form
Directory of Open Access Journals (Sweden)
Antonio Fernández-Caballero
2017-04-01
Full Text Available This paper introduces the neural correlates of phrase rhythm. In short, phrase rhythm is the rhythmic aspect of phrase construction and the relationships between phrases. For the sake of establishing the neural correlates, a musical experiment has been designed to induce music-evoked stimuli related to phrase rhythm. Brain activity is monitored through electroencephalography (EEG by using a brain–computer interface. The power spectral value of each EEG channel is estimated to obtain how power variance distributes as a function of frequency. Our experiment shows statistical differences in theta and alpha bands in the phrase rhythm variations of two classical sonatas, one in bipartite form and the other in rondo form.
The complete nucleotide sequence of a new bipartite begomovirus from Brazil infecting Abutilon.
Paprotka, T; Metzler, V; Jeske, H
2010-05-01
The complete nucleotide sequence of Abutilon mosaic Brazil virus (AbMBV), a new bipartite begomovirus from Bahia, Brazil, is described and analyzed phylogenetically. Its DNA A is most closely related to those of Sida-infecting begomoviruses from Brazil and forms a phylogenetic cluster with pepper- and Euphorbia-infecting begomoviruses from Central America. The DNA B component forms a cluster with different Sida- and okra-infecting begomoviruses from Brazil. Both components are distinct from those of the classical Abutilon mosaic virus originating from the West Indies. AbMBV is transmissible to Nicotiana benthamiana and Malva parviflora by biolistics of rolling-circle amplification products and induces characteristic mosaic and vein-clearing symptoms in M. parviflora.
Jeon, Gyuhyeon
2016-01-01
A common form of competition is one where judges grade contestants' performances which are then compiled to determine the final ranking of the contestants. Unlike in another common form of competition where two contestants play a head-to-head match to produce a winner as in football or basketball, the objectivity of judges are prone to be questioned, potentially undermining the public's trust in the fairness of the competition. In this work we show, by modeling the judge--contestant competition as a weighted bipartite network, how we can identify biased scores and measure their impact on our inference of the network structure. Analyzing the prestigious International Chopin Piano Competition of 2015 with a well-publicized scoring controversy as an example, we show that even a single statistically uncharacteristic score can be enough to gravely distort our inference of the community structure, demonstrating the importance of detecting and eliminating biases. In the process we also find that there does not exist...
Modeling discrete combinatorial systems as alphabetic bipartite networks: theory and applications.
Choudhury, Monojit; Ganguly, Niloy; Maiti, Abyayananda; Mukherjee, Animesh; Brusch, Lutz; Deutsch, Andreas; Peruani, Fernando
2010-03-01
Genes and human languages are discrete combinatorial systems (DCSs), in which the basic building blocks are finite sets of elementary units: nucleotides or codons in a DNA sequence, and letters or words in a language. Different combinations of these finite units give rise to potentially infinite numbers of genes or sentences. This type of DCSs can be represented as an alphabetic bipartite network (ABN) where there are two kinds of nodes, one type represents the elementary units while the other type represents their combinations. Here, we extend and generalize recent analytical findings for ABNs derived in [Peruani, Europhys. Lett. 79, 28001 (2007)] and empirically investigate two real world systems in terms of ABNs, the codon gene and the phoneme-language network. The one-mode projections onto the elementary basic units are also studied theoretically as well as in real world ABNs. We propose the use of ABNs as a means for inferring the mechanisms underlying the growth of real world DCSs.
Controlling coherence via tuning of the population imbalance in a bipartite optical lattice
di Liberto, Marco Fedele
2015-03-01
The control of transport properties is a key tool at the basis of many technologically relevant effects in condensed matter. The clean and precisely controlled environment of ultracold atoms in optical lattices allows one to prepare simplified but instructive models, which can help to better understand the underlying physical mechanisms. Here we show that by tuning a structural deformation of the unit cell in a bipartite optical lattice, one can induce a phase transition from a superfluid into various Mott insulating phases forming a shell structure in the superimposed harmonic trap. The Mott shells are identified via characteristic features in the visibility of Bragg maxima in momentum spectra. The experimental findings are explained by Gutzwiller mean-field and quantum Monte Carlo calculations. Our system bears similarities with the loss of coherence in cuprate superconductors, known to be associated with the doping induced buckling of the oxygen octahedra surrounding the copper sites.
Energy Technology Data Exchange (ETDEWEB)
Tahira, Rabia; Ikram, Manzoor; Zubairy, M Suhail [Centre for Quantum Physics, COMSATS Institute of Information Technology, Islamabad (Pakistan); Bougouffa, Smail [Department of Physics, Faculty of Science, Taibah University, PO Box 30002, Madinah (Saudi Arabia)
2010-02-14
We investigate the phenomenon of sudden death of entanglement in a high-dimensional bipartite system subjected to dissipative environments with an arbitrary initial pure entangled state between two fields in the cavities. We find that in a vacuum reservoir, the presence of the state where one or more than one (two) photons in each cavity are present is a necessary condition for the sudden death of entanglement. Otherwise entanglement remains for infinite time and decays asymptotically with the decay of individual qubits. For pure two-qubit entangled states in a thermal environment, we observe that sudden death of entanglement always occurs. The sudden death time of the entangled states is related to the number of photons in the cavities, the temperature of the reservoir and the initial preparation of the entangled states.
Properties and construction of extreme bipartite states having positive partial transpose
Chen, Lin
2012-01-01
We investigate the set E of extreme points of the compact convex set of PPT states (i.e., the states having positive semidefinite partial transpose) of a bipartite MxN quantum system. Let E(M,N,r) denote the subset of E consisting of states of rank r which are supported on MxN. We show that for M,N>2 the sets E(M,N,M+N-2) are nonempty. On the other hand we show that for M,N>3 the sets E(M,N,N+1) are empty. It is known that the set E(M,N,MN) is empty, and we show that also the set E(M,N,MN-1) is empty. We divide the set of all states into the good and the bad states (the definition is too technical to be given here). We show that the good states have many good properties.
Dell'Anno, F; Illuminati, F; Anno, Fabio Dell'; Siena, Silvio De; Illuminati, Fabrizio
2004-01-01
Extending the scheme developed for a single mode of the electromagnetic field in the preceding paper ``Structure of multiphoton quantum optics. I. Canonical formalism and homodyne squeezed states'', we introduce two-mode nonlinear canonical transformations depending on two heterodyne mixing angles. They are defined in terms of hermitian nonlinear functions that realize heterodyne superpositions of conjugate quadratures of bipartite systems. The canonical transformations diagonalize a class of Hamiltonians describing non degenerate and degenerate multiphoton processes. We determine the coherent states associated to the canonical transformations, which generalize the non degenerate two--photon squeezed states. Such heterodyne multiphoton squeezed are defined as the simultaneous eigenstates of the transformed, coupled annihilation operators. They are generated by nonlinear unitary evolutions acting on two-mode squeezed states. They are non Gaussian, highly non classical, entangled states. For a quadratic nonline...
Romero, K M F; Parreira, J E; Souza, L A M; Wreszinski, W F
2007-01-01
We study and compare the information loss of a large class of gaussian bipartite systems. It includes the usual Caldeira-Leggett type model as well as Anosov models (parametric oscillators, the inverted oscillator environment, etc), which exhibit instability, one of the most important characteristics of chaotic systems. We establish a rigorous connection between the quantum Lyapunov exponents and coherence loss. We show that in the case of unstable environments, coherence loss is completely determined by the upper quantum Lyapunov exponent, a behavior dramatically different to that of the Caldeira-Leggett type model. For this class of systems we have been able to prove a long standing conjecture that for information loss the complexity of even a few (one) degrees of freedom is far more effective in destroying quantum coherence than stable many-body environments.
Quantum Discord and Entanglement of Quasi-Werner States Based on Bipartite Entangled Coherent States
Mishra, Manoj K.; Maurya, Ajay K.; Prakash, Hari
2016-06-01
Present work is an attempt to compare quantum discord and quantum entanglement of quasi-Werner states formed with the four bipartite entangled coherent states (ECS) used recently for quantum teleportation of a qubit encoded in superposed coherent state. Out of these, the quasi-Werner states based on maximally ECS due to its invariant nature under local operation is independent of measurement basis and mean photon numbers, while for quasi-Werner states based on non-maximally ECS, it depends upon measurement basis as well as on mean photon number. However, for large mean photon numbers since non-maximally ECS becomes almost maximally entangled therefore dependence of quantum discord for non-maximally ECS based quasi-Werner states on the measurement basis disappears.
Institute of Scientific and Technical Information of China (English)
无
2007-01-01
As an important tool for heuristic design of NP-hard problems, backbone analysis has become a hot spot in theoretical computer science in recent years. Due to the difficulty in the research on computational complexity of the backbone, many researchers analyzed the backbone by statistic ways. Aiming to increase the backbone size which is usually very small by the existing methods, the unique optimal solution instance construction (UOSIC) is proposed for the graph bi-partitioning problem (GBP). Also, we prove by using the UOSIC that it is NP-hard to obtain the backbone, i.e. no algorithm exists to obtain the backbone of a GBP in polynomial time under the assumption that P ( NP. Our work expands the research area of computational complexity of the backbone. And the UOSIC provides a new way for heuristic design of NP-hard problems.
Chains of Quasi-Classical Informations for Bipartite Correlations and the Role of Twin Observables
Herbut, F
2002-01-01
Having the quantum correlations in a general bipartite state in mind, the information accessible by simultaneous measurement on both subsystems is shown never to exceed the information accessible by measurement on one subsystem, which, in turn is proved not to exceed the von Neumann mutual information. A particular pair of (opposite- subsystem) observables are shown to be responsible both for the amount of quasi-classical correlations and for that of the purely quantum entanglement in the pure-state case: the former via simultaneous subsystem measurements, and the latter through the entropy of coherence or of incompatibility, which is defined for the general case. The observables at issue are so-called twin observables. A general definition of the latter is given in terms of their detailed properties.
Weight Identification of a Weighted Bipartite Graph Complex Dynamical Network with Coupling Delay
Directory of Open Access Journals (Sweden)
Jia Zhen
2010-01-01
Full Text Available Abstract We propose a network model, a weighted bipartite complex dynamical network with coupling delay, and present a scheme for identifying the weights of the network. Based on adaptive synchronization technique, weight trackers are designed for identifying the edge weights between nodes of the network by monitoring the dynamical evolution of the synchronous networks with drive-response structure. The conclusion is proved theoretically by Lyapunovs stability theory and LaSalle's invariance principle. Compared with the similar works, taking into consideration the structural characteristics of the network, the tracking devices designed in our paper are more effective and more easy to implement. Finally, numerical simulations show the effectiveness of the proposed method.
The aggregate path coupling method for the Potts model on bipartite graph
Hernández, José C.; Kovchegov, Yevgeniy; Otto, Peter T.
2017-02-01
In this paper, we derive the large deviation principle for the Potts model on the complete bipartite graph Kn,n as n increases to infinity. Next, for the Potts model on Kn,n, we provide an extension of the method of aggregate path coupling that was originally developed in the work of Kovchegov, Otto, and Titus [J. Stat. Phys. 144(5), 1009-1027 (2011)] for the mean-field Blume-Capel model and in Kovchegov and Otto [J. Stat. Phys. 161(3), 553-576 (2015)] for a general mean-field setting that included the generalized Curie-Weiss-Potts model analyzed in the work of Jahnel et al. [Markov Process. Relat. Fields 20, 601-632 (2014)]. We use the aggregate path coupling method to identify and determine the threshold value βs separating the rapid and slow mixing regimes for the Glauber dynamics of the Potts model on Kn,n.
Modeling the spread of vector-borne diseases on bipartite networks.
Directory of Open Access Journals (Sweden)
Donal Bisanzio
Full Text Available BACKGROUND: Vector-borne diseases for which transmission occurs exclusively between vectors and hosts can be modeled as spreading on a bipartite network. METHODOLOGY/PRINCIPAL FINDINGS: In such models the spreading of the disease strongly depends on the degree distribution of the two classes of nodes. It is sufficient for one of the classes to have a scale-free degree distribution with a slow enough decay for the network to have asymptotically vanishing epidemic threshold. Data on the distribution of Ixodes ricinus ticks on mice and lizards from two independent studies are well described by a scale-free distribution compatible with an asymptotically vanishing epidemic threshold. The commonly used negative binomial, instead, cannot describe the right tail of the empirical distribution. CONCLUSIONS/SIGNIFICANCE: The extreme aggregation of vectors on hosts, described by the power-law decay of the degree distribution, makes the epidemic threshold decrease with the size of the network and vanish asymptotically.
New bipartition model of neutral particle transport in the HL-2A divertor region
Institute of Scientific and Technical Information of China (English)
DENG Bai-quan; YAN Jian-cheng; PENG Li-lin
2005-01-01
A new bipartition neutral transport model has been developed for simulation of the hydrogenic neutral particle transport in the vicinity of HL-2A divertor target plate. The numerical calculation results on the basis of this model are fairly consistent with the results obtained with the "multi-generation method". One possible application of this model is to provide a source term originating from neutral transport calculation for any other edge plasma transport code, for instance, B-2 code, which has been used to simulate edge plasma transport of the HL-2A divertor configuration. Especially it can be utilized to quickly classify the plasma in divertor region as high or low recycling regime.
ODONTOID PROCESS HYPOPLASIA AND BIPARTITE ATLAS ASSOCIATED WITH ATLANTO-AXIAL INSTABILITY
Directory of Open Access Journals (Sweden)
Luis Miguel Sousa Marques
Full Text Available ABSTRACT Surgical treatment of craniocervical junction pathology has evolved considerably in recent years with the implementation of short fixation techniques rather than long occipito-cervical fixation (sub-axial. It is often difficult and sometimes misleading to determine the particular bone and vascular features (high riding vertebral artery, for instance using only the conventional images in three orthogonal planes (axial, sagittal and coronal. The authors describe a rare clinical case of congenital malformation of the craniovertebral junction consisting of hypoplasia/agenesis of the odontoid process and bipartite atlas associated with atlantoaxial instability which was diagnosed late in life in a patient with a previous history of rheumatologic disease. The authors refer to the diagnostic process, including new imaging techniques, and three-dimensional multiplanar reconstruction. The authors also discuss the surgical technique and possible alternatives.
A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
Yang, Yuning; Kamboh, Awais M; Mason, Andrew J
2014-04-30
This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.
Hoang, Linh; Yang, Zhi; Liu, Wentai
2009-01-01
An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.
A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.
Mill, R; Sheik, S; Indiveri, G; Denham, S L
2011-10-01
Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.
VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.
Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V
2007-03-01
A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.
Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En
2015-08-13
A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
Knowledge-based synthesis of custom VLSI physical design tools: First steps
Setliff, Dorothy E.; Rutenbar, Rob A.
A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
Directory of Open Access Journals (Sweden)
V.Sri Sai Harsha
2015-09-01
Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.
Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.
2002-04-01
A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit
2016-09-01
The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
VLSI design of 3D display processing chip for binocular stereo displays
Institute of Scientific and Technical Information of China (English)
Ge Chenyang; Zheng Nanning
2010-01-01
In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.
Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
Directory of Open Access Journals (Sweden)
HOO, C.-S.
2013-02-01
Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
P.A.HarshaVardhini
2012-04-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
M.Madhavi Latha
2012-05-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation
Massengill, Lloyd W.
1991-03-01
A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.
Real-time motion detection using an analog VLSI zero-crossing chip
Bair, Wyeth; Koch, Christof
1991-07-01
The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.
VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Li, Kang; Yu, Juebang; Li, Jian
In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT
Liu, Kai; Li, YunSong; Belyaev, Eugeniy
2010-08-01
The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA
Directory of Open Access Journals (Sweden)
Nishi Pandey
2015-10-01
Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family
Analyzing VLSI component test results of a GenRad GR125 tester
Zulaica, D.; Lee, C.-H.
1995-06-01
The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard
Institute of Scientific and Technical Information of China (English)
Li Zhang; Don Xie; Di Wu
2006-01-01
The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris
2011-01-01
This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.
Design of a reliable and self-testing VLSI datapath using residue coding techniques
Sayers, I. L.; Kinniment, D. J.; Chester, E. G.
1986-05-01
The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.
An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips
Deutsch, L. J.
1985-01-01
A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.
Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.
Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System
Directory of Open Access Journals (Sweden)
Horiuchi Timothy
2003-01-01
Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.
VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.
Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip
2014-01-01
Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.
A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.
Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo
2013-09-01
Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj
1993-01-01
Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.