WorldWideScience

Sample records for vlsi layout automation

  1. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  2. Antenna arrays: waveguide layout designing automation

    OpenAIRE

    Anamova, R. R.

    2014-01-01

    Waveguide layout designing automation in the large-sized phased antenna arrays is studied. A new methodology of the automation and algorithms based on the flexible connection routing method are suggested. Results are realized in the software module WDS (Waveguide Design Solution) based on SolidWorks system. This module gives an opportunity to decrease design and engineering time and costs.

  3. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  4. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  5. Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.

    Science.gov (United States)

    Stanojevich, Bob Srbislav

    This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at

  6. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  7. Automated Layout Generation of Analogue and Mixed-Signal ASIC's

    DEFF Research Database (Denmark)

    Bloch, Rene

    search for better solutions can be guided into new and more prosperous areas of the search space. This feature also provides the designer with the ability to easily try out several implementation options, thus exploring the solution space, which are especially important in the early stages of the design...... is generated using a full-custom layout style and is based on a library of CMOS process independent device generators. The placement for the analogue circuit is derived using the interactive floorplan optimization algorithm described above. This ensures that a high degree of user control is implemented...

  8. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  9. An algorithm for automated layout of process description maps drawn in SBGN.

    Science.gov (United States)

    Genc, Begum; Dogrusoz, Ugur

    2016-01-01

    Evolving technology has increased the focus on genomics. The combination of today's advanced techniques with decades of molecular biology research has yielded huge amounts of pathway data. A standard, named the Systems Biology Graphical Notation (SBGN), was recently introduced to allow scientists to represent biological pathways in an unambiguous, easy-to-understand and efficient manner. Although there are a number of automated layout algorithms for various types of biological networks, currently none specialize on process description (PD) maps as defined by SBGN. We propose a new automated layout algorithm for PD maps drawn in SBGN. Our algorithm is based on a force-directed automated layout algorithm called Compound Spring Embedder (CoSE). On top of the existing force scheme, additional heuristics employing new types of forces and movement rules are defined to address SBGN-specific rules. Our algorithm is the only automatic layout algorithm that properly addresses all SBGN rules for drawing PD maps, including placement of substrates and products of process nodes on opposite sides, compact tiling of members of molecular complexes and extensively making use of nested structures (compound nodes) to properly draw cellular locations and molecular complex structures. As demonstrated experimentally, the algorithm results in significant improvements over use of a generic layout algorithm such as CoSE in addressing SBGN rules on top of commonly accepted graph drawing criteria. An implementation of our algorithm in Java is available within ChiLay library (https://github.com/iVis-at-Bilkent/chilay). ugur@cs.bilkent.edu.tr or dogrusoz@cbio.mskcc.org Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press.

  10. Lean line layouts in highly automated machining environments : ensuring consideration to important aspects when designing line layouts

    OpenAIRE

    Vallander, Karolina; Lindblom, Malin

    2014-01-01

    In order to create a machining line layout that supports the principles of lean a systematic approach is needed to ensure that a wide range of factors are taken into consideration. Despite this, many companies today design new layouts mainly considering delivery times of machines and equipment, and available space in the factory. A combined literature and case study has aimed to identify the most important factors in a lean line layout and a supporting structure to apply these in the design o...

  11. Towards an automated system for the verification and diagnosis of intelligent VLSI circuits

    Science.gov (United States)

    Velazco, Raoul; Ziade, Haissam

    The main features of a system designed to cope with both the verification and diagnosis of Very Large Scale Integration (VLSI) intelligent circuits are detailed. The system is composed of a validation program generator, the GAPT (French Acronym for automatic generation of test programs) software and a microprocessor dedicated verification system, the TEMAC functional tester. GAPT/TEMAC tools allow an easy implementation of a top down diagnosis procedure. Each diagnosis action is composed of symptom analysis, malfunction hypothesis statement, sequence generation, execution, and result evaluation. It was successfully used in various microprocessor qualification/validation experiments. The system capabilities and the diagnosis procedure are illustrated by an actual 68000 microprocessor diagnosis experiment.

  12. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  13. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  14. A Tool for the Automated Design and Evaluation of Habitat Interior Layouts

    Science.gov (United States)

    Simon, Matthew A.; Wilhite, Alan W.

    2013-01-01

    The objective of space habitat design is to minimize mass and system size while providing adequate space for all necessary equipment and a functional layout that supports crew health and productivity. Unfortunately, development and evaluation of interior layouts is often ignored during conceptual design because of the subjectivity and long times required using current evaluation methods (e.g., human-in-the-loop mockup tests and in-depth CAD evaluations). Early, more objective assessment could prevent expensive design changes that may increase vehicle mass and compromise functionality. This paper describes a new interior design evaluation method to enable early, structured consideration of habitat interior layouts. This interior layout evaluation method features a comprehensive list of quantifiable habitat layout evaluation criteria, automatic methods to measure these criteria from a geometry model, and application of systems engineering tools and numerical methods to construct a multi-objective value function measuring the overall habitat layout performance. In addition to a detailed description of this method, a C++/OpenGL software tool which has been developed to implement this method is also discussed. This tool leverages geometry modeling coupled with collision detection techniques to identify favorable layouts subject to multiple constraints and objectives (e.g., minimize mass, maximize contiguous habitable volume, maximize task performance, and minimize crew safety risks). Finally, a few habitat layout evaluation examples are described to demonstrate the effectiveness of this method and tool to influence habitat design.

  15. A System for Automated Extraction of Metadata from Scanned Documents using Layout Recognition and String Pattern Search Models.

    Science.gov (United States)

    Misra, Dharitri; Chen, Siyuan; Thoma, George R

    2009-01-01

    One of the most expensive aspects of archiving digital documents is the manual acquisition of context-sensitive metadata useful for the subsequent discovery of, and access to, the archived items. For certain types of textual documents, such as journal articles, pamphlets, official government records, etc., where the metadata is contained within the body of the documents, a cost effective method is to identify and extract the metadata in an automated way, applying machine learning and string pattern search techniques.At the U. S. National Library of Medicine (NLM) we have developed an automated metadata extraction (AME) system that employs layout classification and recognition models with a metadata pattern search model for a text corpus with structured or semi-structured information. A combination of Support Vector Machine and Hidden Markov Model is used to create the layout recognition models from a training set of the corpus, following which a rule-based metadata search model is used to extract the embedded metadata by analyzing the string patterns within and surrounding each field in the recognized layouts.In this paper, we describe the design of our AME system, with focus on the metadata search model. We present the extraction results for a historic collection from the Food and Drug Administration, and outline how the system may be adapted for similar collections. Finally, we discuss some ongoing enhancements to our AME system.

  16. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  17. Optimal Stack Layout in a Sea Container Terminal with Automated Lifting Vehicles

    NARCIS (Netherlands)

    D. Roy (Debjit); A. Gupta (Akash); S. Parhi (Sampanna); M.B.M. de Koster (René)

    2014-01-01

    textabstractContainer terminal performance is largely determined by its design decisions, which include the number and type of quay cranes (QCs), stack cranes (SCs), transport vehicles, vehicle travel path, and stack layout. The terminal design process is complex because it is affected by factors

  18. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  19. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  20. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  1. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  2. The Design and Production of a Procedure Training Aid Using the Procedure Learning Format and the Computer Automated Page Layout (PLA) Routine.

    Science.gov (United States)

    1983-12-01

    problem by developing the computer automated page layout system ( lu aW Sy-Wa, 1LM) which significantly reduces the time and effort riquired to produce...draws lines between related pictures and between labels and pictures types headers and footers The author: resolves layout problems that cannot be...BLD974PISAD Ste thog al iDm GOTOPAE MCKU *Toc wer ac atinanSrsoFeEaesplc e Stecal exactg al tioemrechie 00S TO PAPE MOKU e Toc whr eac action an

  3. Three-Dimensional Circuit Layouts.

    Science.gov (United States)

    1984-06-01

    the models of VLSI layout theory renders the vertices of our circuits as unit-side squares or cubes . 4. Our method of extending the two-dimensional...model assumes isometry in all 4$ dimensions: a unit of height is eqivalent to a unit of width. It is worthwhile placing these assumptions in perspective...2,13]. 4. Aside from clerical simplification, the isometry assumption acknowledges the potential problem of cross-talk between parallel runs of wire

  4. A Holistic Approach to Automated Synthesis of Mixed-technology Digital MEMS Sensors Part 1: Layout Synthesis of MEMS Component with Distributed Mechanical Dynamics

    Directory of Open Access Journals (Sweden)

    Chenxu ZHAO

    2010-06-01

    Full Text Available This contribution presents a novel, holistic methodology for automated optimal layout synthesis of MEMS systems embedded in electronic control circuitry from user-defined high-level performance specifications and design constraints. The proposed approach is based on simulation-based optimization where the genetic-based synthesis of both mechanical layouts and associated electronic control loops is coupled with calculations of optimal design parameters. The underlying MEMS models include distributed mechanical dynamics described by partial differential equations to enable accurate performance prediction of critical mechanical components. The proposed genetic-based synthesis technique has been implemented in SystemC-A and named SystemC-AGNES. A practical case study of an automated design of a capacitive MEMS accelerometer with Sigma-Delta control demonstrates the operation of the SystemC-AGNES platform. This Part 1 of the paper focuses on the layout synthesis of mechanical components, while the full synthesis methodology including automated and optimal electronic control loop synthesis is outlined in Part 2.

  5. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  6. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  7. Design and simulation of integration system between automated material handling system and manufacturing layout in the automotive assembly line

    Science.gov (United States)

    Seha, S.; Zamberi, J.; Fairu, A. J.

    2017-10-01

    Material handling system (MHS) is an important part for the productivity plant and has recognized as an integral part of today’s manufacturing system. Currently, MHS has growth tremendously with its technology and equipment type. Based on the case study observation, the issue involving material handling system contribute to the reduction of production efficiency. This paper aims to propose a new design of integration between material handling and manufacturing layout by investigating the influences of layout and material handling system. A method approach tool using Delmia Quest software is introduced and the simulation result is used to assess the influences of the integration between material handling system and manufacturing layout in the performance of automotive assembly line. The result show, the production of assembly line output increases more than 31% from the current system. The source throughput rate average value went up to 252 units per working hour in model 3 and show the effectiveness of the pick-to-light system as efficient storage equipment. Thus, overall result shows, the application of AGV and the pick-to-light system gave a large significant effect in the automotive assembly line. Moreover, the change of layout also shows a large significant improvement to the performance.

  8. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  9. TECHNOLOGY MAPPING TOOL FOR VLSI CAD

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2017-01-01

    Full Text Available Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic circuit specification into a gate (i.e., netlist specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus.

  10. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...

  11. Course Layout

    OpenAIRE

    2005-01-01

    present roll Presentation roll Interactive Media Element This is an interactive diagram of a MATLAB course layout covering 16 topics in 4 different main areas: Basics of MATLAB, Numerical Methods in MATLAB, Symbolic Manipulations in MATLAB, Mathematical Modeling in MATLAB and Simulink AE2440 Introduction to Digital Computation

  12. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  13. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  14. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  15. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  16. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  17. Facade Layout Symmetrization

    KAUST Repository

    Jiang, Haiyong

    2016-04-11

    We present an automatic algorithm for symmetrizing facade layouts. Our method symmetrizes a given facade layout while minimally modifying the original layout. Based on the principles of symmetry in urban design, we formulate the problem of facade layout symmetrization as an optimization problem. Our system further enhances the regularity of the final layout by redistributing and aligning boxes in the layout. We demonstrate that the proposed solution can generate symmetric facade layouts efficiently. © 2015 IEEE.

  18. Symmetrization of Facade Layouts

    KAUST Repository

    Jiang, Haiyong

    2016-02-26

    We present an automatic approach for symmetrizing urban facade layouts. Our method can generate a symmetric layout through minimally modifying the original input layout. Based on the principles of symmetry in urban design, we formulate facade layout symmetrization as an optimization problem. Our method further enhances the regularity of the final layout by redistributing and aligning elements in the layout. We demonstrate that the proposed solution can effectively generate symmetric facade layouts.

  19. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1986-12-10

    structure of the described circuits. One such language is ^ FP (a variation of the Functional Programming language FP) [ Sheeran 83] that describes...86] [Lipton 82] [ Sheeran 83] [Suzuki 85] [UW/NW 84] Bamji, C, Hauck, C. and Allen, J. A Design by Example Regular Structure Generator. In 22nd...Automation Conference, pages 467-474. IEEE, 1982. Mary Sheeran . \\i.FP - An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing La

  20. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  1. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  2. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  3. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  4. Declarative Descriptions for VLSI Generators

    Science.gov (United States)

    1986-06-01

    will review languages in each category. Sheeran [ Sheeran 83] proposes a structured hierarchical design language, IL, FP (a variation of the...IEEE, 1982. [ Sheeran 83] Mary Sheeran . p& FP -An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing Laboratory, November, 1983

  5. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  6. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  7. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-03-31

    We would like to acknowledge the contributions by Flavio Rose of MIT when we first studied this problem. The three of us originally produced a O(1V13...Rinehart and Winston, New York, 1976. 18] Charles E. Leiserson, Flavio M. Rose, and James B. Saxe, "Optimizing synchronous circuitry by retiming... Flavio M. Rose, Models for VLSI CircuiLs, Masters Thesis, Department of Electrical En- gineering and Computer Science, Massachusetts Institute of

  8. Layouts of Expander Graphs

    OpenAIRE

    Dujmović, Vida; Sidiropoulos, Anastasios; Wood, David R.

    2015-01-01

    Bourgain and Yehudayoff recently constructed $O(1)$-monotone bipartite expanders. By combining this result with a generalisation of the unraveling method of Kannan, we construct 3-monotone bipartite expanders, which is best possible. We then show that the same graphs admit 3-page book embeddings, 2-queue layouts, 4-track layouts, and have simple thickness 2. All these results are best possible.

  9. Reconfigurable layout problem

    NARCIS (Netherlands)

    Meng, G.; Heragu, S.S.; Heragu, S.S.; Zijm, Willem H.M.

    2004-01-01

    This paper addresses the reconfigurable layout problem, which differs from traditional, robust and dynamic layout problems mainly in two aspects: first, it assumes that production data are available only for the current and upcoming production period. Second, it considers queuing performance

  10. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  11. Analysis on flexible manufacturing system layout using arena simulation software

    Science.gov (United States)

    Fadzly, M. K.; Saad, Mohd Sazli; Shayfull, Z.

    2017-09-01

    Flexible manufacturing system (FMS) was defined as highly automated group technology machine cell, consisting of a group of processing stations interconnected by an automated material handling and storage system, and controlled by an integrated computer system. FMS can produce parts or products are in the mid-volume, mid-variety production range. The layout system in FMS is an important criterion to design the FMS system to produce a part or product. This facility layout of an FMS involves the positioning of cells within given boundaries, so as to minimize the total projected travel time between cells. Defining the layout includes specifying the spatial coordinates of each cell, its orientation in either a horizontal or vertical position, and the location of its load or unloads point. There are many types of FMS layout such as In-line, loop ladder and robot centered cell layout. The research is concentrating on the design and optimization FMS layout. The final conclusion can be summarized that the objective to design and optimisation of FMS layout for this study is successful because the FMS In-line layout is the best layout based on effective time and cost using ARENA simulation software.

  12. Automatic page composition with nested sub-layouts

    Science.gov (United States)

    Hunter, Andrew

    2013-03-01

    This paper provides an overview of a system for the automatic composition of publications. The system first composes nested hierarchies of contents, then applies layout engines at branch points in the hierarchies to explore layout options, and finally selects the best overall options for the finished publications. Although the system has been developed as a general platform for automated publishing, this paper describes its application to the composition and layout of a magazine-like publication for social content from Facebook. The composition process works by assembling design fragments that have been populated with text and images from the Facebook social network. The fragments constitute a design language for a publication. Each design fragment is a nested mutable sub-layout that has no specific size or shape until after it has been laid-out. The layout process balances the space requirements of the fragment's internal contents with its external context in the publication. The mutability of sub-layouts requires that their layout options must be kept open until all the other contents that share the same space have been considered. Coping with large numbers of options is one of the greatest challenges in layout automation. Most existing layout methods work by rapidly elimination design options rather than by keeping options open. A further goal of this publishing system is to confirm that a custom publication can be generated quickly by the described methods. In general, the faster that publications can be created, the greater the opportunities for the technology.

  13. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  14. INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS

    OpenAIRE

    KÖlzer, J.; Otto, J.

    1989-01-01

    Chip verification and failure analysis during the design evaluation of very large scale integrated (VLSI) devices call for highly accurate internal analysis methods. After having characterized the first silicon by automated functional testing, classification and statistical analysis can be carried out : In this way a rough electrical evaluation of the material under investigation can be made. Further clues to a faulty device behavior can only be obtained by internal measurements. Serious malf...

  15. Full custom VLSI - A technology for high performance computing

    Science.gov (United States)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  16. Extended Bulgarian keyboard layouts

    OpenAIRE

    Zinoviev, Anton

    2009-01-01

    The old Bulgarian keyboard standard BDS 5237-78 was developed for use mostly on typewriter machines. The wide distribution of the computers forced the update of this standard. On one hand this is because of the need to support symbols such as the Bulgarian quotation marks, the Cyrillic letter I with grave accent, the long dash, etc. On the other hand the so called "phonetic layout" became popular and this layout is not standartized by BDS. In this work we are analyzing the possibilities to im...

  17. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  18. Design and Simulation Plant Layout Using Systematic Layout Planning

    Science.gov (United States)

    Suhardini, D.; Septiani, W.; Fauziah, S.

    2017-12-01

    This research aims to design the factory layout of PT. Gunaprima Budiwijaya in order to increase production capacity. The problem faced by this company is inappropriate layout causes cross traffic on the production floor. The re-layout procedure consist of these three steps: analysing the existing layout, designing plant layout based on SLP and evaluation and selection of alternative layout using Simulation Pro model version 6. Systematic layout planning is used to re-layout not based on the initial layout. This SLP produces four layout alternatives, and each alternative will be evaluated based on two criteria, namely cost of material handling using Material Handling Evaluation Sheet (MHES) and processing time by simulation. The results showed that production capacity is increasing as much as 37.5% with the addition of the machine and the operator, while material handling cost was reduced by improvement of the layout. The use of systematic layout planning method reduces material handling cost of 10,98% from initial layout or amounting to Rp1.229.813,34.

  19. VLSI-distributed architectures for smart cameras

    Science.gov (United States)

    Wolf, Wayne H.

    2001-03-01

    Smart cameras use video/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing power and memory along with image sensors. CMOS sensors are rapidly improving in performance, allowing us to integrate sensors, logic, and memory on the same chip. As we become able to build chips with hundreds of millions of transistors, we will be able to include powerful multiprocessors on the same chip as the image sensors. We call these image sensor/multiprocessor systems image processors. Second, VLSI allows us to put a large number of these powerful sensor/processor systems on a single scene. VLSI factories will produce large quantities of these image processors, making it cost-effective to use a large number of them in a single location. Image processors will be networked into distributed cameras that use many sensors as well as the full computational resources of all the available multiprocessors. Multiple cameras make a number of image recognition tasks easier: we can select the best view of an object, eliminate occlusions, and use 3D information to improve the accuracy of object recognition. This paper outlines approaches to distributed camera design: architectures for image processors and distributed cameras; algorithms to run on distributed smart cameras, and applications of which VLSI distributed camera systems.

  20. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  1. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  2. Use of polyimides in VLSI fabrication

    Science.gov (United States)

    Wilson, A. M.

    The functional requirements of overcoats and multilevel insulators for very large scale integrated circuits (VLSI) are outlined. The moisture barrier properties of polyimide films are reviewed. Polyimide performance vs plasma enhanced chemically vapor deposited (CVD) silicon nitride overcoats are compared. The topological and via forming advantages of polyimides vs plasma enhanced CVD silicon oxide as a multilevel insulator are cited. The temperature and voltage field induced electronic charge transport and trapping at oxide interfaces is cited as the most serious limitation to the use of polyimides as multilevel insulators on VLSI chips.

  3. Automatic page layout using genetic algorithms for electronic albuming

    Science.gov (United States)

    Geigel, Joe; Loui, Alexander C. P.

    2000-12-01

    In this paper, we describe a flexible system for automatic page layout that makes use of genetic algorithms for albuming applications. The system is divided into two modules, a page creator module which is responsible for distributing images amongst various album pages, and an image placement module which positions images on individual pages. Final page layouts are specified in a textual form using XML for printing or viewing over the Internet. The system makes use of genetic algorithms, a class of search and optimization algorithms that are based on the concepts of biological evolution, for generating solutions with fitness based on graphic design preferences supplied by the user. The genetic page layout algorithm has been incorporated into a web-based prototype system for interactive page layout over the Internet. The prototype system is built using client-server architecture and is implemented in java. The system described in this paper has demonstrated the feasibility of using genetic algorithms for automated page layout in albuming and web-based imaging applications. We believe that the system adequately proves the validity of the concept, providing creative layouts in a reasonable number of iterations. By optimizing the layout parameters of the fitness function, we hope to further improve the quality of the final layout in terms of user preference and computation speed.

  4. Alpine Pixel Detector Layout

    CERN Document Server

    Delebecque, P; The ATLAS collaboration; Geffroy, N; Massol, N; Rambure, T; Todorov, T

    2013-01-01

    A description of an optimized layout of pixel sensors based on a stave that combines both barrel and endcap module orientations. The mechanical stiffness of the structure is provided by carbon fiber shells spaced by carbon foam. The cooling of the modules is provided by two-phase $CO_{2}$ flowing in a thin titanium pipe glued inside the carbon fiber foam. The electrical services of all modules are provided by a single stave flex. This layout eliminates the need for separate barrel and endcap detector structures, and therefore the barrel services material in front of the endcap. The transition from barrel to endcap module orientation is optimized separately for each layer in order to minimize the active pixel area and the traversed material. The sparse module spacing in the endcap part of the stave allows for multiple fixation points, and for a stiff overall structure composed only of staves interconnected by stiff disks.

  5. Layout of LHCb

    CERN Multimedia

    CERN AC

    1998-01-01

    This diagram shows the layout for the LHCb detector, which will be part of the LHC project at CERN. The main purpose of this detector is to look for rare decays of a heavy quark known as 'bottom', a version of the down quark that is found in protons and neutrons. In particular, decays by a process known as 'CP violation' will be studied to investigate Nature's preference for matter over antimatter.

  6. Structure completion for facade layouts

    KAUST Repository

    Fan, Lubin

    2014-11-19

    (Figure Presented) We present a method to complete missing structures in facade layouts. Starting from an abstraction of the partially observed layout as a set of shapes, we can propose one or multiple possible completed layouts. Structure completion with large missing parts is an ill-posed problem. Therefore, we combine two sources of information to derive our solution: the observed shapes and a database of complete layouts. The problem is also very difficult, because shape positions and attributes have to be estimated jointly. Our proposed solution is to break the problem into two components: a statistical model to evaluate layouts and a planning algorithm to generate candidate layouts. This ensures that the completed result is consistent with the observation and the layouts in the database.

  7. NUMERICAL SIMULATION OF DIGITAL VLSI TOTAL DOSE FUNCTIONAL FAILURES

    Directory of Open Access Journals (Sweden)

    O. A. Kalashnikov

    2016-10-01

    Full Text Available The technique for numerical simulation of digital VLSI total dose failures is presented, based on fuzzy logic sets theory. It assumes transfer from boolean logic model of a VLSI with values {0,1} to fuzzy model with continuous interval [0,1], and from boolean logic functions to continuous minimax functions. The technique is realized as a calculation system and allows effective estimating of digital VLSI radiation behavior without experimental investigation.

  8. Auditory Spatial Layout

    Science.gov (United States)

    Wightman, Frederic L.; Jenison, Rick

    1995-01-01

    All auditory sensory information is packaged in a pair of acoustical pressure waveforms, one at each ear. While there is obvious structure in these waveforms, that structure (temporal and spectral patterns) bears no simple relationship to the structure of the environmental objects that produced them. The properties of auditory objects and their layout in space must be derived completely from higher level processing of the peripheral input. This chapter begins with a discussion of the peculiarities of acoustical stimuli and how they are received by the human auditory system. A distinction is made between the ambient sound field and the effective stimulus to differentiate the perceptual distinctions among various simple classes of sound sources (ambient field) from the known perceptual consequences of the linear transformations of the sound wave from source to receiver (effective stimulus). Next, the definition of an auditory object is dealt with, specifically the question of how the various components of a sound stream become segregated into distinct auditory objects. The remainder of the chapter focuses on issues related to the spatial layout of auditory objects, both stationary and moving.

  9. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  10. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  11. Layout and composition for animation

    CERN Document Server

    Ghertner, Ed

    2012-01-01

    This essential, hands-on guide is filled with examples of what a composition should look like and example of poorly designed layouts. Spot potential problems before they cost time and money, and adapt creative solutions for your own projects with this invaluable resource for beginner and intermediate artists.  With Beauty and the Beast examples and Simpson character layouts, readers will learn how to develop character layout and background layout as well as strengthen composition  styles with a creative toolset of trick shot examples and inspirational case studies. A companion website will

  12. VLSI Architectures For Syntactic Image Analysis

    Science.gov (United States)

    Chiang, Y. P.; Fu, K. S.

    1984-01-01

    Earley's algorithm has been commonly used for the parsing of general context-free languages and error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). In this paper we present a parallel Earley's recognition algorithm in terms of "x*" operation. By restricting the input context-free grammar to be X-free, we are able to implement this parallel algorithm on a triangular shape VLSI array. This system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n+1 system time. We also present an error-correcting recognition algorithm. The parallel error-correcting recognition algorithm has also been im-plemented on a triangular VLSI array. This array recognizes an erroneous string length n in time 2n+1 and gives the correct error count. Applications of the proposed VLSI architectures to image analysis are illus-trated by examples.

  13. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  14. Optimization of a furniture factory layout

    Directory of Open Access Journals (Sweden)

    Tadej Kanduč

    2015-03-01

    Full Text Available This paper deals with the problem of optimizing a factory floor layout in a Slovenian furniture factory. First, the current state of the manufacturing system is analyzed by constructing a discrete event simulation (DES model that reflects the manufacturing processes. The company produces over 10,000 different products, and their manufacturing processes include approximately 30,000 subprocesses. Therefore, manually constructing a model to include every subprocess is not feasible. To overcome this problem, a method for automated model construction was developed to construct a DES model based on a selection of manufacturing orders and relevant subprocesses. The obtained simulation model provided insight into the manufacturing processes and enable easy modification of model parameters for optimizing the manufacturing processes. Finally, the optimization problem was solved: the total distance the products had to traverse between machines was minimized by devising an optimal machine layout. With the introduction of certain simplifications, the problem was best described as a quadratic assignment problem. A novel heuristic method based on force-directed graph drawing algorithms was developed. Optimizing the floor layout resulted in a significant reduction of total travel distance for the products.

  15. A Notation for Describing Multiple Views of VLSI Circuits

    Science.gov (United States)

    1988-06-01

    leaf In the functional programming language pFP cells or abstract objects) and a set of relations among [ Sheeran 83] the behavior specification implies a...A raduate VLSI design class has employed the notation in the design of modules com- [ Sheeran 83] M. Sheeran , "jvFP - An Algebraic VLSI prising a

  16. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  17. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  18. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  19. Investigation on repository layouts

    Energy Technology Data Exchange (ETDEWEB)

    Tanai, Kenji [Tokai, Works, Japan Nuclear Cycle Development Inst., Tokai, Ibaraki (Japan); Iwasa, Kengo; Hasegawa, Hiroshi [Head Office, Japan Nuclear Cycle Development Inst., Tokai, Ibaraki (Japan); Gouke, Mitsuo; Horita, Masakuni [Shimizu Corp., Tokyo (Japan); Noda, Masaru [Ohbayashi Corp., Tokyo (Japan)

    1999-11-01

    This report consists of three items : (1) Study of the repository configuration, (2) Study of the surface facilities configuration for construction, operation and backfilling, (3) Planning schedule. In the repository configuration, the basic factors influencing the design of the repository configuration are presented, and the results of studies of various possible repository configurations are presented for both hard and soft rock systems. Here, the minimum conditions regarding geological environment required to guide design are assumed, because it is difficult to determine the repository configuration without considering specific conditions of a disposal site. In the surface facility configuration, it is illustrated based on the results of construction, operation, backfilling studies for underground disposal facility and EIS report of CANADA. In the schedule, the overall schedule corresponding to the repository layout is outlined in link with the milestone of disposal schedule set forth in the government's basic policy. The assumptions and the basic conditions are summarized to examine the General Schedule from start of construction to closure of a repository. This summary is based on the technologies to be used for construction, operation and closure of a repository. The basic national policies form the framework for this review of the general schedule. (author)

  20. Artwork Analysis Tools for VLSI Circuits.

    Science.gov (United States)

    1980-06-01

    derived frcm the art- work.i~nFo :.- Is zr Code DI t pecal Sculnfv CLA a uPICAT OP T0416 PA*6WM Dine Bftee AMA& -’M Artwork Analysis Tools for VLSI Circuits... code of the program and in pre-generated bit tables. The design rules thcmselves are not input directly into the checker. The rules were interpreted...circuit simulation is swich -level sintulation. In this type, transistors are modeled as switches that are either on or off. Fixed delays are a%.ociated

  1. Computing layouts with deformable templates

    KAUST Repository

    Peng, Chihan

    2014-07-27

    In this paper, we tackle the problem of tiling a domain with a set of deformable templates. A valid solution to this problem completely covers the domain with templates such that the templates do not overlap. We generalize existing specialized solutions and formulate a general layout problem by modeling important constraints and admissible template deformations. Our main idea is to break the layout algorithm into two steps: a discrete step to lay out the approximate template positions and a continuous step to refine the template shapes. Our approach is suitable for a large class of applications, including floorplans, urban layouts, and arts and design. Copyright © ACM.

  2. Practical Aspects of CMOS Layout

    DEFF Research Database (Denmark)

    Stassen, Flemming

    1996-01-01

    The topics covered in these notes are the practical aspects and limitations of layout, when random process variations result in electrical parameters, which are not constant but rather statistically distributed.The focus is on design methods for reducing or eliminating the effects. The notes cover...... three aspects:1) to introduce layout structures robust to process variations2) to present simplistic models for analog building blocks with the aim of analysing consequences of parameter variations3) to present the basic noise considerations which guide the layout of supply structures etc....

  3. Design & layout of recreation facilities

    Science.gov (United States)

    Howard R. Orr

    1971-01-01

    Design and layout of recreation facilities is a problem solving process that must be divorced from the emotionalism that has shrouded outdoor recreation and must deal deliberately with the growing information concerning people and natural resources.

  4. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  5. COMPUTER AIDED SELECTION OF PLANT LAYOUT

    African Journals Online (AJOL)

    COMPUTER AIDED SELECTION OF PLANT LAYOUT. Daniel Kita w. Mechanical Engineering Department. Addis Ababa University. ABSTRACT. This paper deals with the fundamental concepts of plant layout, in which the need for plant layout, the systematic and logical approaches to the problems, layout solutions and the ...

  6. Preliminary Design Through Graphs: A Tool for Automatic Layout Distribution

    Directory of Open Access Journals (Sweden)

    Carlo Biagini

    2015-02-01

    Full Text Available Diagrams are essential in the preliminary stages of design for understanding distributive aspects and assisting the decision-making process. By drawing a schematic graph, designers can visualize in a synthetic way the relationships between many aspects: functions and spaces, distribution of layouts, space adjacency, influence of traffic flows within a facility layout, and so on. This process can be automated through the use of modern Information and Communication Technologies tools (ICT that allow the designers to manage a large quantity of information. The work that we will present is part of an on-going research project into how modern parametric software influences decision-making on the basis of automatic and optimized layout distribution. The method involves two phases: the first aims to define the ontological relation between spaces, with particular reference to a specific building typology (rules of aggregation of spaces; the second entails the implementation of these rules through the use of specialist software. The generation of ontological relations begins with the collection of data from historical manuals and analyses of case studies. These analyses aim to generate a “relationship matrix” based on preferences of space adjacency. The phase of implementing the previously defined rules is based on the use of Grasshopper to analyse and visualize different layout configurations. The layout is generated by simulating a process involving the collision of spheres, which represents specific functions of the design program. The spheres are attracted or rejected as a function of the relationships matrix, as defined above. The layout thus obtained will remain in a sort of abstract state independent of information about the exterior form, but will still provide a useful tool for the decision-making process. In addition, preliminary results gathered through the analysis of case studies will be presented. These results provide a good variety

  7. Offshore wind farm electrical cable layout optimization

    Science.gov (United States)

    Pillai, A. C.; Chick, J.; Johanning, L.; Khorasanchi, M.; de Laleu, V.

    2015-12-01

    This article explores an automated approach for the efficient placement of substations and the design of an inter-array electrical collection network for an offshore wind farm through the minimization of the cost. To accomplish this, the problem is represented as a number of sub-problems that are solved in series using a combination of heuristic algorithms. The overall problem is first solved by clustering the turbines to generate valid substation positions. From this, a navigational mesh pathfinding algorithm based on Delaunay triangulation is applied to identify valid cable paths, which are then used in a mixed-integer linear programming problem to solve for a constrained capacitated minimum spanning tree considering all realistic constraints. The final tree that is produced represents the solution to the inter-array cable problem. This method is applied to a planned wind farm to illustrate the suitability of the approach and the resulting layout that is generated.

  8. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  9. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  10. Optimization-Based Layout Design

    Directory of Open Access Journals (Sweden)

    K. Abdel-Malek

    2005-01-01

    Full Text Available The layout problem is of importance to ergonomists, vehicle/cockpit packaging engineers, designers of manufacturing assembly lines, designers concerned with the placement of levers, knobs, controls, etc. in the reachable workspace of a human, and also to users of digital human modeling code, where digital prototyping has become a valuable tool. This paper proposes a hybrid optimization method (gradient-based optimization and simulated annealing to obtain the layout design. We implemented the proposed algorithm for a project at Oral-B Laboratories, where a manufacturing cell involves an operator who handles three objects, some with the left hand, others with the right hand.

  11. Princeton VLSI Project: Semi-Annual Report.

    Science.gov (United States)

    1982-11-01

    version currently implemented) plus the type virtual, used to name bounding boxes and having no physical reality in the fabricated circuit. For example...type vitual . The relationship of the rectangle bounding a newly * created cell to any other rectangle of the layout can be specified in the standard

  12. Cache-oblivious mesh layouts

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Sung-Eui [Univ. of North Carolina, Chapel Hill, NC (United States); Lindstrom, Peter [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Pascucci, Valerio [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Manocha, Dinesh [Univ. of North Carolina, Chapel Hill, NC (United States)

    2005-07-01

    We present a novel method for computing cache-oblivious layouts of large meshes that improve the performance of interactive visualization and geometric processing algorithms. Given that the mesh is accessed in a reasonably coherent manner, we assume no particular data access patterns or cache parameters of the memory hierarchy involved in the computation. Furthermore, our formulation extends directly to computing layouts of multi-resolution and bounding volume hierarchies of large meshes. We develop a simple and practical cache-oblivious metric for estimating cache misses. Computing a coherent mesh layout is reduced to a combinatorial optimization problem. We designed and implemented an out-of-core multilevel minimization algorithm and tested its performance on unstructured meshes composed of tens to hundreds of millions of triangles. Our layouts can significantly reduce the number of cache misses. We have observed 2-20 times speedups in view-dependent rendering, collision detection, and isocontour extraction without any modification of the algorithms or runtime applications.

  13. HOLA: Human-like Orthogonal Network Layout.

    Science.gov (United States)

    Kieffer, Steve; Dwyer, Tim; Marriott, Kim; Wybrow, Michael

    2016-01-01

    Over the last 50 years a wide variety of automatic network layout algorithms have been developed. Some are fast heuristic techniques suitable for networks with hundreds of thousands of nodes while others are multi-stage frameworks for higher-quality layout of smaller networks. However, despite decades of research currently no algorithm produces layout of comparable quality to that of a human. We give a new "human-centred" methodology for automatic network layout algorithm design that is intended to overcome this deficiency. User studies are first used to identify the aesthetic criteria algorithms should encode, then an algorithm is developed that is informed by these criteria and finally, a follow-up study evaluates the algorithm output. We have used this new methodology to develop an automatic orthogonal network layout method, HOLA, that achieves measurably better (by user study) layout than the best available orthogonal layout algorithm and which produces layouts of comparable quality to those produced by hand.

  14. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  15. Multilevel VLSI interconnection—an optimum approach?

    Science.gov (United States)

    Srikrishnan, K. V.; Totta, P. A.

    1986-04-01

    The wirability of circuit elements is a key ingredient in the success of the very large scale integration technology. Multilevel wiring eliminates the need to use extensive areas of the silicon surface simply for wiring channels. Increasing the number of wiring planes significantly improves the possibility of achieving the goals of the VLSI, i.e. the interconnection of the maximum number of devices in the smallest possible area. Extensive modeling has shown the need to optimize the wiring pitch, number of wiring planes and electrical properties of the materials used (e.g-low resistivity for conductors and low dielectric constant for insulators). The choice of the interconnection technology is also influenced by other factors. Some of these areas: cost and reliability objectives; in house expertise and practice; new process/equipment availability and a desire to maintain process commonality. The selected strategy is sometimes an optimum approach for an individual situation which is not universally optimum. In IBM, for example, two different but successful multilevel wiring technologies are being used extensively. The first is used for bipolar circuits; it is a three-level metallization design, with sputtered SiO2 as the insulator. The second, for FET devices, has two-levels of metal and polyimide as the insulator. Both technologies use area array input/output terminal connections and lift off line definition. The process/material set of each is reviewed to emphasize the mechanics of reaching an ``optimum'' solution for the individual applications.

  16. Design automation, languages, and simulations

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume covers a broad range of topics relevant to design automation, languages, and simulations. These include a collaborative framework that coordinates distributed design activities through the Internet, an overview of the Verilog hardware description language and its use in a design environment, hardware/software co-design, syst

  17. Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

    CERN Document Server

    Shen, Ruijing; Yu, Hao

    2012-01-01

    Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have  become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and ...

  18. Computational Design of Urban Layouts

    KAUST Repository

    Wonka, Peter

    2015-10-07

    A fundamental challenge in computational design is to compute layouts by arranging a set of shapes. In this talk I will present recent urban modeling projects with applications in computer graphics, urban planning, and architecture. The talk will look at different scales of urban modeling (streets, floorplans, parcels). A common challenge in all these modeling problems are functional and aesthetic constraints that should be respected. The talk also highlights interesting links to geometry processing problems, such as field design and quad meshing.

  19. DESIGN OF KEYBOARD LAYOUT USING CADWORK

    OpenAIRE

    Udosen, U. J.

    2007-01-01

    CADWORK has been employed for the design of a keyboard layout and compared with QWERTY keyboard layout evaluated by CADWORK heuristics. The time simulated by CADWORK to type a document supplied as data using the QWERTY layout was 647.79 TMU while that obtained when using the layout designed by CADWORK was 604.69 TMU. From the standpoint of ergonomic considerations, a keyboard layout which permits the operator to type more efficiently is to be preferred in order to reduce the medical problem ...

  20. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  1. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  2. Formal Hierarchical Multilevel Verification of Synchronous MOS VLSI Designs,

    Science.gov (United States)

    1987-11-01

    description of digital systems appear in Johnson [Johnson] (though in a much less accessible form). Other researchers, [ Sheeran , Johnson], use the same...Snepscheut, "Hot-Clock nMOS," Proc of the 1985 Chapel Hil Conference on VLSI. Henry Fuchs, Editor. Computer Science Press 1985 [ Sheeran ] Mary Sheeran

  3. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  4. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...

  5. Generating and exploring good building layouts

    KAUST Repository

    Bao, Fan

    2013-07-01

    Good building layouts are required to conform to regulatory guidelines, while meeting certain quality measures. While different methods can sample the space of such good layouts, there exists little support for a user to understand and systematically explore the samples. Starting from a discrete set of good layouts, we analytically characterize the local shape space of good layouts around each initial layout, compactly encode these spaces, and link them to support transitions across the different local spaces. We represent such transitions in the form of a portal graph. The user can then use the portal graph, along with the family of local shape spaces, to globally and locally explore the space of good building layouts. We use our framework on a variety of different test scenarios to showcase an intuitive design, navigation, and exploration interface. Copyright © ACM. Copyright © ACM 2013.

  6. Patch layout generation by detecting feature networks

    KAUST Repository

    Cao, Yuanhao

    2015-02-01

    The patch layout of 3D surfaces reveals the high-level geometric and topological structures. In this paper, we study the patch layout computation by detecting and enclosing feature loops on surfaces. We present a hybrid framework which combines several key ingredients, including feature detection, feature filtering, feature curve extension, patch subdivision and boundary smoothing. Our framework is able to compute patch layouts through concave features as previous approaches, but also able to generate nice layouts through smoothing regions. We demonstrate the effectiveness of our framework by comparing with the state-of-the-art methods.

  7. AmbiguityVis: Visualization of Ambiguity in Graph Layouts.

    Science.gov (United States)

    Wang, Yong; Shen, Qiaomu; Archambault, Daniel; Zhou, Zhiguang; Zhu, Min; Yang, Sixiao; Qu, Huamin

    2016-01-01

    Node-link diagrams provide an intuitive way to explore networks and have inspired a large number of automated graph layout strategies that optimize aesthetic criteria. However, any particular drawing approach cannot fully satisfy all these criteria simultaneously, producing drawings with visual ambiguities that can impede the understanding of network structure. To bring attention to these potentially problematic areas present in the drawing, this paper presents a technique that highlights common types of visual ambiguities: ambiguous spatial relationships between nodes and edges, visual overlap between community structures, and ambiguity in edge bundling and metanodes. Metrics, including newly proposed metrics for abnormal edge lengths, visual overlap in community structures and node/edge aggregation, are proposed to quantify areas of ambiguity in the drawing. These metrics and others are then displayed using a heatmap-based visualization that provides visual feedback to developers of graph drawing and visualization approaches, allowing them to quickly identify misleading areas. The novel metrics and the heatmap-based visualization allow a user to explore ambiguities in graph layouts from multiple perspectives in order to make reasonable graph layout choices. The effectiveness of the technique is demonstrated through case studies and expert reviews.

  8. Economics of wind farm layout

    Energy Technology Data Exchange (ETDEWEB)

    Germain, A.C. [Wind Energy Resource Specialist, Oakland, CA (United States); Bain, D.A. [Oregon Office of Energy, Portland, OR (United States)

    1997-12-31

    The life cycle cost of energy (COE) is the primary determinant of the economic viability of a wind energy generation facility. The cost of wind turbines and associated hardware is counterbalanced by the energy which can be generated. This paper focuses on the turbine layout design process, considering the cost and energy capture implications of potential spacing options from the viewpoint of a practicing project designer. It is argued that lateral spacings in the range of 1.5 to 5 diameters are all potentially optimal, but only when matched to wind resource characteristics and machine design limits. The effect of wakes on energy capture is quantified while the effect on turbine life and maintenance cost is discussed qualitatively. Careful optimization can lower COE and project designers are encouraged to integrate the concepts in project designs.

  9. Staking Terraces Online: A Terrace Layout Program

    Science.gov (United States)

    Terrace construction in Missouri exceeded 3 million feet at a cost of over $8 million in 2008. Up to 50 % of the total construction and design time is spent on the terrace layout itself. A web-based computer program, MOTERR, has been developed to design terrace layouts. The program utilizes digital ...

  10. Interactive Graph Layout of a Million Nodes

    Directory of Open Access Journals (Sweden)

    Peng Mi

    2016-12-01

    Full Text Available Sensemaking of large graphs, specifically those with millions of nodes, is a crucial task in many fields. Automatic graph layout algorithms, augmented with real-time human-in-the-loop interaction, can potentially support sensemaking of large graphs. However, designing interactive algorithms to achieve this is challenging. In this paper, we tackle the scalability problem of interactive layout of large graphs, and contribute a new GPU-based force-directed layout algorithm that exploits graph topology. This algorithm can interactively layout graphs with millions of nodes, and support real-time interaction to explore alternative graph layouts. Users can directly manipulate the layout of vertices in a force-directed fashion. The complexity of traditional repulsive force computation is reduced by approximating calculations based on the hierarchical structure of multi-level clustered graphs. We evaluate the algorithm performance, and demonstrate human-in-the-loop layout in two sensemaking case studies. Moreover, we summarize lessons learned for designing interactive large graph layout algorithms on the GPU.

  11. Layout Optimisation of Wave Energy Converter Arrays

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé; Nava, Vincenzo; Topper, Mathew B. R.

    2017-01-01

    This paper proposes an optimisation strategy for the layout design of wave energy converter (WEC) arrays. Optimal layouts are sought so as to maximise the absorbed power given a minimum q-factor, the minimum distance between WECs, and an area of deployment. To guarantee an efficient optimisation...

  12. Noise-margin limitations on gallium-arsenide VLSI

    Science.gov (United States)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  13. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  14. VLSI architectures for the new (T,L) algorithm

    Science.gov (United States)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  15. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    and Smoliar [Fran7g], Rowson [Rows80, Gordon [Gord8lJ, Cardelli and Plotkin [Card8l1, Hafer and Parker (Hafe83I, and Sheeran [Shee84] have all suggested...Software 1, 4 (October 1984), pp. 10-26. •.’ Y .. , ;,, ..- , .. r ,- ’..-.... -. -.. ,.:.%.. -. 149 ISbeeS4I. Sheeran , M., "mFP, a Language for VLSI

  16. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  17. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  18. Aesthetic role of transparency and layering in the creation of photo layouts

    Science.gov (United States)

    Ortiz Segovia, Maria V.; Damera-Venkata, Niranjan; O'Brien-Strain, Eamonn; Fan, Jian; Lim, Suk Hwan; Liu, Sam; Liu, Jerry; Lin, Qian; Allebach, Jan P.

    2011-03-01

    Even though technology has allowed us to measure many different aspects of images, it is still a challenge to objectively measure their aesthetic appeal. A more complex challenge is presented when an arrangement of images is to be analyzed, such as in a photo-book page. Several approaches have been proposed to measure the appeal of a document layout that, in general, make use of geometric features such as the position and size of a single object relative to the overall layout. Fewer efforts have been made to include in a metric the influence of the content and composition of images in the layout. Many of the aesthetic characteristics that graphic designers and artists use in their daily work have been either left out of the analysis or only roughly approximated in an effort to materialize the concepts. Moreover, graphic design tools such as transparency and layering play an important role in the professional creation of layouts for documents such as posters and flyers. The main goal of our study is to apply similar techniques within an automated photo-layout generation tool. Among other design techniques, the tool makes use of layering and transparency in the layout to produce a professional-looking arrangement of the pictures. Two series of experiments with people from different levels of expertise with graphic design provided us with the tools to make the results of our system more appealing. In this paper, we discuss the results of our experiments in the context of distinct graphic design concepts.

  19. Luminaire layout: Design and implementation

    Science.gov (United States)

    Both, A. J.

    1994-01-01

    The information contained in this report was presented during the discussion regarding guidelines for PAR uniformity in greenhouses. The data shows a lighting uniformity analysis in a research greenhouse for rose production at the Cornell University campus. The luminaire layout was designed using the computer program Lumen-Micro. After implementation of the design, accurate measurements were taken in the greenhouse and the uniformity analysis for both the design and implementation were compared. A study of several supplemental lighting installations resulted in the following recommendations: include only the actual growing area in the lighting uniformity analysis; for growing areas up to 20 square meters, take four measurements per square meter; for growing areas above 20 square meters, take one measurement per square meter; use one of the uniformity criteria and frequency graphs to compare lighting uniformity amongst designs; and design for uniformity criterion of a least 0.75 and the fraction within +/- 15% of the average PAR value should be close to one.

  20. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  1. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  2. Layout optimization using the homogenization method

    Science.gov (United States)

    Suzuki, Katsuyuki; Kikuchi, Noboru

    1993-01-01

    A generalized layout problem involving sizing, shape, and topology optimization is solved by using the homogenization method for three-dimensional linearly elastic shell structures in order to seek a possibility of establishment of an integrated design system of automotive car bodies, as an extension of the previous work by Bendsoe and Kikuchi. A formulation of a three-dimensional homogenized shell, a solution algorithm, and several examples of computing the optimum layout are presented in this first part of the two articles.

  3. Design and analysis of reconfigurable layout systems

    OpenAIRE

    Heragu, Sunderesh; Zijm, Willem H.M.; Meng, Gang; Heragu, S.S.; van Ommeren, Jan C.W.; VAN HOUTUM, Geert-Jan

    2001-01-01

    In this paper, we present a framework for determining the layout in a manufacturing environment characterized by constantly changing product volumes and mix. Much of the production equipment is assumed to be relatively light weight and therefore their location can be easily changed to suit the current production environment. The framework allows several alternate layouts to be developed and evaluated with respect to deterministic (material flow and machine relocation) criteria as well as stoc...

  4. Computer aided selection of plant layout | Kitaw | Zede Journal

    African Journals Online (AJOL)

    This paper deals with the fundamental concepts of plant layout, in which the need for plant layout, the systematic and logical approaches to the problems, layout solutions and the objectives of plant layout are discussed. Further the approaches and the scoring techniques of the two available computer rout ines are ...

  5. 48 CFR 52.236-17 - Layout of Work.

    Science.gov (United States)

    2010-10-01

    ... 48 Federal Acquisition Regulations System 2 2010-10-01 2010-10-01 false Layout of Work. 52.236-17... Layout of Work. As prescribed in 36.517, insert the following clause in solicitations and contracts when... need for accurate work layout and for siting verification during work performance: Layout of Work (APR...

  6. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  7. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  8. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  9. Space station automation study: Automation requriements derived from space manufacturing concepts,volume 2

    Science.gov (United States)

    1984-01-01

    Automation reuirements were developed for two manufacturing concepts: (1) Gallium Arsenide Electroepitaxial Crystal Production and Wafer Manufacturing Facility, and (2) Gallium Arsenide VLSI Microelectronics Chip Processing Facility. A functional overview of the ultimate design concept incoporating the two manufacturing facilities on the space station are provided. The concepts were selected to facilitate an in-depth analysis of manufacturing automation requirements in the form of process mechanization, teleoperation and robotics, sensors, and artificial intelligence. While the cost-effectiveness of these facilities was not analyzed, both appear entirely feasible for the year 2000 timeframe.

  10. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  11. An optimization tool for satellite equipment layout

    Science.gov (United States)

    Qin, Zheng; Liang, Yan-gang; Zhou, Jian-ping

    2018-01-01

    Selection of the satellite equipment layout with performance constraints is a complex task which can be viewed as a constrained multi-objective optimization and a multiple criteria decision making problem. The layout design of a satellite cabin involves the process of locating the required equipment in a limited space, thereby satisfying various behavioral constraints of the interior and exterior environments. The layout optimization of satellite cabin in this paper includes the C.G. offset, the moments of inertia and the space debris impact risk of the system, of which the impact risk index is developed to quantify the risk to a satellite cabin of coming into contact with space debris. In this paper an optimization tool for the integration of CAD software as well as the optimization algorithms is presented, which is developed to automatically find solutions for a three-dimensional layout of equipment in satellite. The effectiveness of the tool is also demonstrated by applying to the layout optimization of a satellite platform.

  12. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  13. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  14. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  15. VLSI design for reliability. Final report, September-November 1989

    Energy Technology Data Exchange (ETDEWEB)

    Hajj, I.N.; Najm, F.N.; Yang, P.

    1990-05-01

    This report contains the results of supplementary work done related to the reliability analysis of Application Specific Very Large Scale Integrated (ASIC VLSI) CMOS circuits. The major work is currently being carried out under Task N-9-5716. The main goal of both tasks is to determine the electromigration susceptibility of VLSI circuits. Electromigration is a major reliability problem caused by the transport of atoms in a metal line due to the electron flow. Under persistent current stress, electromigration can cause deformations of the metal lines which may result in shorts or open circuits. The failure rate due to electromigration depends on the current density in the metal lines and is usually expressed as a median-time-to-failure (MTF). This work focuses on the electromigration problem in the power and ground busses. To estimate the bust MTF, an estimate of the current waveform in each branch of the bus is required. In general, the MTF is dependent on the shape of the current waveform, and not simply on its time-average. However, a very large number of such waveform shapes are possible, depending on what inputs are applied to the circuit. This is especially true for complementary metal oxide semiconductors circuits, which draw current only during switching.

  16. Discrete optimization in architecture architectural & urban layout

    CERN Document Server

    Zawidzki, Machi

    2016-01-01

    This book presents three projects that demonstrate the fundamental problems of architectural design and urban composition – the layout design, evaluation and optimization. Part I describes the functional layout design of a residential building, and an evaluation of the quality of a town square (plaza). The algorithm for the functional layout design is based on backtracking using a constraint satisfaction approach combined with coarse grid discretization. The algorithm for the town square evaluation is based on geometrical properties derived directly from its plan. Part II introduces a crowd-simulation application for the analysis of escape routes on floor plans, and optimization of a floor plan for smooth crowd flow. The algorithms presented employ agent-based modeling and cellular automata.

  17. Layout Optimisation of Wave Energy Converter Arrays

    Directory of Open Access Journals (Sweden)

    Pau Mercadé Ruiz

    2017-08-01

    Full Text Available This paper proposes an optimisation strategy for the layout design of wave energy converter (WEC arrays. Optimal layouts are sought so as to maximise the absorbed power given a minimum q-factor, the minimum distance between WECs, and an area of deployment. To guarantee an efficient optimisation, a four-parameter layout description is proposed. Three different optimisation algorithms are further compared in terms of performance and computational cost. These are the covariance matrix adaptation evolution strategy (CMA, a genetic algorithm (GA and the glowworm swarm optimisation (GSO algorithm. The results show slightly higher performances for the latter two algorithms; however, the first turns out to be significantly less computationally demanding.

  18. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  19. Summary of workshop on the application of VLSI for robotic sensing

    Science.gov (United States)

    Brooks, T.; Wilcox, B.

    1984-01-01

    It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

  20. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  1. Final Report: ATLAS Phase-2 Tracker Upgrade Layout Task Force

    CERN Document Server

    Clark, A; The ATLAS collaboration; Hessey, N; Mättig, P; Styles, N; Wells, P; Burdin, S; Cornelissen, T; Todorov, T; Vankov, P; Watson, I; Wenig, S

    2012-01-01

    he mandate of the Upgrade Layout Task Force was to develop a benchmark layout proposal for the ATLAS Phase-2 Upgrade Letter of Intent (LOI), due in late 2012. The work described in this note has evolved from simulation and design studies made using an earlier "UTOPIA" upgrade tracker layout, and experience gained from the current ATLAS Inner Detector during the first years of data taking. The layout described in this document, called the LoI-layout, will be used as a benchmark layout for the LoI and will be used for simulation and engineering studies described in the LoI.

  2. Customisation of Indico pages - Layout and Menus

    CERN Multimedia

    CERN. Geneva; Ferreira, Pedro

    2017-01-01

    In this tutorial you are going to learn how to customize the layout of your Indico pages (for example you can change the color of the background images or change the logo) and the menus on your Indico pages  (for example you can add or hide certain blocks, or change their name and order).  

  3. Connection Facility Layout Model of Subway Stations

    Directory of Open Access Journals (Sweden)

    Liya Yao

    2015-01-01

    Full Text Available As the key node of public transportation system, subway station has many functions such as attracting and distributing passengers and guiding the transfer from various traffic modes to subway. However, the poor facility scale and layout around subway stations in practice usually cause the inconvenience of transfer and low transfer efficiency, which causes the declination of travel efficiency and even loose of subway passengers. Taking subway stations as the study objects, this paper has emphasis on the connection characters between various traffic modes and subway stations. Considering the attraction region, the total transfer time, transfer distance, and connection cost were selected to form the efficiency index of connection layout of subway stations. Data envelopment analysis (DEA model is applied in the quantization of traffic resource consumption and output. At last, connection facility layout model of subway stations was established with the aim of improving the transfer efficiency. Meaningful results were obtained from the connection layout model of subway stations, which guide the planning and designing of the transfer facilities around subway stations.

  4. Terrace Layout Using a Computer Assisted System

    Science.gov (United States)

    Development of a web-based terrace design tool based on the MOTERR program is presented, along with representative layouts for conventional and parallel terrace systems. Using digital elevation maps and geographic information systems (GIS), this tool utilizes personal computers to rapidly construct ...

  5. Computerized Facilities Layout Design | Mulugeta | Zede Journal

    African Journals Online (AJOL)

    Facilities are crucial as they usually represent the largest and the most expensive assets of an organization. Determining location of machines, workstations, and other facilities are layout problems in a manufacturing plant. Different computerized algorithms have been developed to optimize the flow of materials within a ...

  6. Directional layouts in central lowland Maya settlement

    DEFF Research Database (Denmark)

    Bevan, Andrew; Jobbová, Eva; Helmke, Christophe

    2013-01-01

    based on nearest neighbour bearings and successive grid offsets e in order to explore possible rectilinear organisation in settlement layouts despite the presence of uneven and irregular patterns of archaeological dating and recovery. The results suggest a grid-like distribution of houseplots and...

  7. Concept Layout Model of Transportation Terminals

    Directory of Open Access Journals (Sweden)

    Li-ya Yao

    2012-01-01

    Full Text Available Transportation terminal is the key node in transport systems. Efficient terminals can improve operation of passenger transportation networks, adjust the layout of public transportation networks, provide a passenger guidance system, and regulate the development of commercial forms, as well as optimize the assembly and distribution of modern logistic modes, among others. This study aims to clarify the relationship between the function and the structure of transportation terminals and establish the function layout design. The mapping mechanism of demand, function, and structure was analyzed, and a quantitative relationship between function and structure was obtained from a design perspective. Passenger demand and terminal structure were decomposed into several demand units and structural elements following the principle of reverse engineering. The relationship maps between these two kinds of elements were then analyzed. Function-oriented concept layout model of transportation terminals was established using the previous method. Thus, a technique in planning and design of transportation structures was proposed. Meaningful results were obtained from the optimization of transportation terminal facilities, which guide the design of the functional layout of transportation terminals and improve the development of urban passenger transportation systems.

  8. Interactive layout mechanisms for image database retrieval

    Energy Technology Data Exchange (ETDEWEB)

    MacCuish, J.; McPherson, A.; Barros, J.; Kelly, P.

    1996-01-29

    In this paper we present a user interface, CANDID Camera, for image retrieval using query-by-example technology. Included in the interface are several new layout algorithms based on multidimensional scaling techniques that visually display global and local relationships between images within a large image database. We use the CANDID project algorithms to create signatures of the images, and then measure the dissimilarity between the signatures. The layout algorithms are of two types. The first are those that project the all-pairs dissimilarities to two dimensions, presenting a many-to-many relationship for a global view of the entire database. The second are those that relate a query image to a small set of matched images for a one-to-many relationship that provides a local inspection of the image relationships. Both types are based on well-known multidimensional scaling techniques that have been modified and used together for efficiency and effectiveness. They include nonlinear projection and classical projection. The global maps are hybrid algorithms using classical projection together with nonlinear projection. We have developed several one-to-many layouts based on a radial layout, also using modified nonlinear and classical projection.

  9. Intersection layout, traffic volumes and accidents.

    NARCIS (Netherlands)

    Poppe, F.

    1988-01-01

    This paper reports on the accident research carried out as a part of a large project started in 1983. For this accident research an inventory was made of a large number of intersections.Recorded were layout features, accident data and estimates of traffic volumes. Attention will be given to the

  10. Design and analysis of reconfigurable layout systems

    NARCIS (Netherlands)

    Heragu, Sunderesh; Zijm, Willem H.M.; Meng, Gang; Heragu, S.S.; van Ommeren, Jan C.W.; van Houtum, Geert-Jan

    2001-01-01

    In this paper, we present a framework for determining the layout in a manufacturing environment characterized by constantly changing product volumes and mix. Much of the production equipment is assumed to be relatively light weight and therefore their location can be easily changed to suit the

  11. Piecewise Linear Approach for Timing Simulation of VLSI (Very-Large-Scale-Integrated) Circuits on Serial and Parallel Computers.

    Science.gov (United States)

    1987-12-01

    328 S % 33880E ° PIECEWISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS Ongky Tejayadi UNIVE,’RSITY OF ILL...APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS 12. PERSONAL AUTHOR(S) Tejayadi, Ongky 13a. TYPE OF REPO~Z J,..-13b...PIECE’WISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS BY ONGKY TEJAYADI B.S., University of Illinois

  12. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  13. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  14. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  15. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  16. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    Science.gov (United States)

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are

  17. Automatic Constraint Detection for 2D Layout Regularization.

    Science.gov (United States)

    Jiang, Haiyong; Nan, Liangliang; Yan, Dong-Ming; Dong, Weiming; Zhang, Xiaopeng; Wonka, Peter

    2016-08-01

    In this paper, we address the problem of constraint detection for layout regularization. The layout we consider is a set of two-dimensional elements where each element is represented by its bounding box. Layout regularization is important in digitizing plans or images, such as floor plans and facade images, and in the improvement of user-created contents, such as architectural drawings and slide layouts. To regularize a layout, we aim to improve the input by detecting and subsequently enforcing alignment, size, and distance constraints between layout elements. Similar to previous work, we formulate layout regularization as a quadratic programming problem. In addition, we propose a novel optimization algorithm that automatically detects constraints. We evaluate the proposed framework using a variety of input layouts from different applications. Our results demonstrate that our method has superior performance to the state of the art.

  18. Automatic Constraint Detection for 2D Layout Regularization

    KAUST Repository

    Jiang, Haiyong

    2015-09-18

    In this paper, we address the problem of constraint detection for layout regularization. As layout we consider a set of two-dimensional elements where each element is represented by its bounding box. Layout regularization is important for digitizing plans or images, such as floor plans and facade images, and for the improvement of user created contents, such as architectural drawings and slide layouts. To regularize a layout, we aim to improve the input by detecting and subsequently enforcing alignment, size, and distance constraints between layout elements. Similar to previous work, we formulate the layout regularization as a quadratic programming problem. In addition, we propose a novel optimization algorithm to automatically detect constraints. In our results, we evaluate the proposed framework on a variety of input layouts from different applications, which demonstrates our method has superior performance to the state of the art.

  19. Silicon Compilation Using a Lisp-Based Layout Language.

    Science.gov (United States)

    1986-06-01

    The ISPS Comguter Descrigtion Language March 1978. Capello , P. R., et. a]. editors, VLSI Signal Processing, IEEE Press, 1984. Carter, T.M., Davis, A...Denyer, P.5., Murray, A.F., and Renshaw, D., "FIRST: Prospect and Retrospect", In Capello , 1984, pp. 252-264. Denyer, P. and Renshaw, D., VLSI...Gray, 19851, pp. 131-140. Lyon, R.F., USSP@ A Bit-Serial Multigrocessor for Signal Processing, in Capello , 1984, pp. 64-75. Naval Postgraduate School

  20. Wind Farm Layout Optimization using Population Distributed Genetic Algorithms

    OpenAIRE

    Tangen, Helene

    2016-01-01

    Wind turbine technology is a promising source of renewable energy. However, the potential of wind turbine technology can not be utilized unless the wind farm layout is efficient. The challenge with wind farm layout optimization is that finding the optimal layout in the huge search space of different layouts is hard, if not impossible, to do analytically. Genetic algorithm techniques have been applied in many fields to solve non-linear optimization problems, and has shown promising results whe...

  1. EFFECTIVE MYANMAR KEY LAYOUT DESIGN ANALYZING FOR ANDROID SOFT KEYBOARD

    OpenAIRE

    NANDAR PWINT OO; NI LAR THEIN

    2012-01-01

    In mobile phone soft keyboard layout, some Myanmar characters are behind the keyboard layout scene and it is needed to switch with some control key. For mobile phone text entry system, optimizing the fit between technology and the user is critical for realizing the potential benefits of assistive technology. It is a necessarytask to try out the effective key layout design that can enhance the text entry speed. Moreover, there is also weak in analyzing of key layout design for Myanmar Language...

  2. A Multi-Objective Optimization Framework for Offshore Wind Farm Layouts and Electric Infrastructures

    Directory of Open Access Journals (Sweden)

    Silvio Rodrigues

    2016-03-01

    Full Text Available Current offshore wind farms (OWFs design processes are based on a sequential approach which does not guarantee system optimality because it oversimplifies the problem by discarding important interdependencies between design aspects. This article presents a framework to integrate, automate and optimize the design of OWF layouts and the respective electrical infrastructures. The proposed framework optimizes simultaneously different goals (e.g., annual energy delivered and investment cost which leads to efficient trade-offs during the design phase, e.g., reduction of wake losses vs collection system length. Furthermore, the proposed framework is independent of economic assumptions, meaning that no a priori values such as the interest rate or energy price, are needed. The proposed framework was applied to the Dutch Borssele areas I and II. A wide range of OWF layouts were obtained through the optimization framework. OWFs with similar energy production and investment cost as layouts designed with standard sequential strategies were obtained through the framework, meaning that the proposed framework has the capability to create different OWF layouts that would have been missed by the designers. In conclusion, the proposed multi-objective optimization framework represents a mind shift in design tools for OWFs which allows cost savings in the design and operation phases.

  3. FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2016-03-01

    Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

  4. Rapid virtual prototyping of complex photonic integrated circuits using layout-aware schematic-driven design methodology

    Science.gov (United States)

    Mingaleev, S.; Richter, A.; Sokolov, E.; Savitzki, S.; Polatynski, A.; Farina, J.; Koltchanov, I.

    2017-02-01

    We present our versatile simulation framework for the schematic-driven and layout-aware design of photonic integrated circuits (PICs) realizing a fast and user-friendly design flow for large-scale PICs comprising passive and active building blocks (BBs). We show how the seamless interaction of circuit simulation with photonic layout design tools allows to specify and utilize directly physical locations and orientations of BBs of standardized process design kits (PDKs). We demonstrate how to combine graphical schematic capture and automated waveguide routing, and discuss by means of typical design applications how an optimized design flow can speed-up the virtual prototyping of complex PICs and optoelectronic applications.

  5. 48 CFR 36.517 - Layout of work.

    Science.gov (United States)

    2010-10-01

    ... 48 Federal Acquisition Regulations System 1 2010-10-01 2010-10-01 false Layout of work. 36.517... CONTRACTING CONSTRUCTION AND ARCHITECT-ENGINEER CONTRACTS Contract Clauses 36.517 Layout of work. The contracting officer shall insert the clause at 52.236-17, Layout of Work, in solicitations and contracts when...

  6. Pure JavaScript Storyline Layout Algorithm

    Energy Technology Data Exchange (ETDEWEB)

    2017-10-02

    This is a JavaScript library for a storyline layout algorithm. Storylines are adept at communicating complex change by encoding time on the x-axis and using the proximity of lines in the y direction to represent interaction between entities. The library in this disclosure takes as input a list of objects containing an id, time, and state. The output is a data structure that can be used to conveniently render a storyline visualization. Most importantly, the library computes the y-coordinate of the entities over time that decreases layout artifacts including crossings, wiggles, and whitespace. This is accomplished through multi-objective, multi-stage optimization problem, where the output of one stage produces input and constraints for the next stage.

  7. Layout of personnel accommodations for the SOFIA

    Science.gov (United States)

    Daughters, David M.; Bruich, J. G.; Arceneaux, Gregory P.; Zirretta, Jason; Caton, William B.

    2000-06-01

    The NASA Stratospheric Observatory for Infrared Astronomy (SOFIA) Observatory is based upon a refurbished and heavily modified Boeing 747 SP aircraft. The Observatory, which provides accommodations for the Deutsches Zentrum Fur Luftund Raumfahrt 2.5 m telescope, science investigator teams, scientific instruments, mission crew and support systems. The US contractor team has removed most of the aircraft original furnishings and designed a new Layout of Personnel Accommodations (LOPA) tailored to SOFIA's needs.

  8. Inverse procedural modeling of facade layouts

    KAUST Repository

    Wu, Feng

    2014-07-27

    In this paper, we address the following research problem: How can we generate a meaningful split grammar that explains a given facade layout? To evaluate if a grammar is meaningful, we propose a cost function based on the description length and minimize this cost using an approximate dynamic programming framework. Our evaluation indicates that our framework extracts meaningful split grammars that are competitive with those of expert users, while some users and all competing automatic solutions are less successful. Copyright © ACM.

  9. Probabilistic Graph Layout for Uncertain Network Visualization.

    Science.gov (United States)

    Schulz, Christoph; Nocaj, Arlind; Goertler, Jochen; Deussen, Oliver; Brandes, Ulrik; Weiskopf, Daniel

    2017-01-01

    We present a novel uncertain network visualization technique based on node-link diagrams. Nodes expand spatially in our probabilistic graph layout, depending on the underlying probability distributions of edges. The visualization is created by computing a two-dimensional graph embedding that combines samples from the probabilistic graph. A Monte Carlo process is used to decompose a probabilistic graph into its possible instances and to continue with our graph layout technique. Splatting and edge bundling are used to visualize point clouds and network topology. The results provide insights into probability distributions for the entire network-not only for individual nodes and edges. We validate our approach using three data sets that represent a wide range of network types: synthetic data, protein-protein interactions from the STRING database, and travel times extracted from Google Maps. Our approach reveals general limitations of the force-directed layout and allows the user to recognize that some nodes of the graph are at a specific position just by chance.

  10. V3 CMS tracker layout Detector Break-up

    CERN Document Server

    Caner, Alessandra

    1996-01-01

    This note reports on the detector and channel break-up of the CMS V3 tracker layout. A compilation of alternative layouts is also tabulated to allow for cost estimates as a function of layout configurations. The information is organized in a modular fashion: for each configuration, the break-up of 25 cm ( 'one wheel') of barrel is reported. The forward detectors ( 'disks') are described individually as a function of equipped annuli. The total number of channels, the area and the bare cost of the provisional V3 layout are estimated. This note will be updated as the V3 layout evolves.

  11. A REDESIGN LAYOUT TO INCREASE PRODUCTIVITY OF A COMPANY

    Directory of Open Access Journals (Sweden)

    Vincentia Kitriastika

    2013-06-01

    Full Text Available This project is conducted in Company X, a passenger cars wheel producing company located in Sunter, North Jakarta. With a view of increasing the productivity of the company, the focus of this project will be redesigned the layout of the factory. The main problem encountered is that the goods are not produced in single location, causing a considerable hindrance in terms of time and distance, and hence efficiency. The redesigning layout process will use SLP method and flow analysis while supported by analysis of assembly line balancing to optimize the layout. Regarding the evaluation process, ARENA software will be used to simulate and identify the bottleneck in the production process, and comparing the layout alternatives to decide the best layout. The best chosen layout according to the simulation and SLP method that supported with flow analysis and assembly line balancing will be used as the master draft layout that will be proposed to Company X.

  12. Study on workshop layout of a motorcycle company based on systematic layout planning (SLP)

    Science.gov (United States)

    Zhou, Kang-Qu; Zhang, Rui-Juan; Wang, Ying-Dong; Wang, Bing-Jie

    2010-08-01

    The method of SLP has been applied in a motorcycle company's layout planning. In this layout design, the related graphics have been used to illuminate the logistics and non-logistics relationships of every workshop to get the integrated relationships of workshops and preliminary plans. Comparing the two preliminary plans including logistics efficiency, space utilization, management conveniences, etc, an improvement solution is proposed. Through the improvement solution, the productivity has been increased by 18% and the production capacity is able to make 1600 engines each day.

  13. Space station automation study: Automation requirements derived from space manufacturing concepts. Volume 1: Executive summary

    Science.gov (United States)

    1984-01-01

    The electroepitaxial process and the Very Large Scale Integration (VLSI) circuits (chips) facilities were chosen because each requires a very high degree of automation, and therefore involved extensive use of teleoperators, robotics, process mechanization, and artificial intelligence. Both cover a raw materials process and a sophisticated multi-step process and are therfore highly representative of the kinds of difficult operation, maintenance, and repair challenges which can be expected for any type of space manufacturing facility. Generic areas were identified which will require significant further study. The initial design will be based on terrestrial state-of-the-art hard automation. One hundred candidate missions were evaluated on the basis of automation portential and availability of meaning ful knowldege. The design requirements and unconstrained design concepts developed for the two missions are presented.

  14. Draft layout of the HPLWR power plant

    Energy Technology Data Exchange (ETDEWEB)

    Koehly, C. [Karlsruhe Inst. of Tech., Karlsruhe (Germany); Starflinger, J. [IKE, Univ. of Stuttgart (Germany); Schulenberg, T.; Brandauer, M.; Lemasson, D.; Velluet, R. [Karlsruhe Inst. of Tech., Karlsruhe (Germany); Herbell, H. [EnBW Kernkraft GmbH, Kernkraftwerk Philippsburg (Germany)

    2011-07-01

    The High Performance Light Water Reactor (HPLWR) is a Supercritical Water Cooled Reactor designed by a consortium of European partners in the 6th European Framework Programme. This paper describes a potential layout of the reactor building including the containment with the reactor and with the required safety systems, the turbine building with turbines, condensers, feedwater pumps and preheaters, and the start-up system. Design details are given for selected key components to estimate their size. Compared with a conventional power plant of similar power output, the HPLWR power plant can be designed significantly smaller. (author)

  15. ATLAS ITk Layout Design and Optimisation

    CERN Document Server

    Calace, Noemi; The ATLAS collaboration

    2016-01-01

    Detector design studies are a very crucial activity for the ATLAS Collaboration, in preparation for the future High Luminosity LHC (HL-LHC) planned to start in 2026. One of the key activities is the design and prototyping of a new Inner Tracker (ITk), fully made of silicon, able to meet the requirements HL-LHC environment assuring at the same time very high tracking performance. A dedicated design process started from Letter of Intent (LoI) layouts is still ongoing to establish the design ATLAS ITk tracker.

  16. Hierarchically organized layout for visualization of biochemical pathways.

    Science.gov (United States)

    Tsay, Jyh-Jong; Wu, Bo-Liang; Jeng, Yu-Sen

    2010-01-01

    Many complex pathways are described as hierarchical structures in which a pathway is recursively partitioned into several sub-pathways, and organized hierarchically as a tree. The hierarchical structure provides a natural way to visualize the global structure of a complex pathway. However, none of the previous research on pathway visualization explores the hierarchical structures provided by many complex pathways. In this paper, we aim to develop algorithms that can take advantages of hierarchical structures, and give layouts that explore the global structures as well as local structures of pathways. We present a new hierarchically organized layout algorithm to produce layouts for hierarchically organized pathways. Our algorithm first decomposes a complex pathway into sub-pathway groups along the hierarchical organization, and then partition each sub-pathway group into basic components. It then applies conventional layout algorithms, such as hierarchical layout and force-directed layout, to compute the layout of each basic component. Finally, component layouts are joined to form a final layout of the pathway. Our main contribution is the development of algorithms for decomposing pathways and joining layouts. Experiment shows that our algorithm is able to give comprehensible visualization for pathways with hierarchies, cycles as well as complex structures. It clearly renders the global component structures as well as the local structure in each component. In addition, it runs very fast, and gives better visualization for many examples from previous related research. 2009 Elsevier B.V. All rights reserved.

  17. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  18. Hydrauliikka- ja pneumatiikkalaboratorion layout ja inventaario

    OpenAIRE

    Uusi-Pohjola, Jarkko

    2016-01-01

    Seinäjoen ammattikorkeakoulun tarjosi opinnäytetyötä. Tarve tuli materiaalitekniikan laboratorion uudelleenjärjestelystä, sekä siellä sijaitsevista Festo Didactic Learnline hydrauliikka- ja pneumatiikkaharjoitustyöpisteiden inventaariosta. Opiskelijoiden harjoituskäyttöön tarkoitettu hydrauliikan ja pneumatiikan simulointiohjelmisto Festo FluidSimin tilalle tuli uusi ohjelmisto, Automation Studio Educational Edition. Automation Studio -ohjelmasta tuli tehdä käyttöönottoa helpottava ohje. ...

  19. Evolutionary optimization technique for site layout planning

    KAUST Repository

    El Ansary, Ayman M.

    2014-02-01

    Solving the site layout planning problem is a challenging task. It requires an iterative approach to satisfy design requirements (e.g. energy efficiency, skyview, daylight, roads network, visual privacy, and clear access to favorite views). These design requirements vary from one project to another based on location and client preferences. In the Gulf region, the most important socio-cultural factor is the visual privacy in indoor space. Hence, most of the residential houses in this region are surrounded by high fences to provide privacy, which has a direct impact on other requirements (e.g. daylight and direction to a favorite view). This paper introduces a novel technique to optimally locate and orient residential buildings to satisfy a set of design requirements. The developed technique is based on genetic algorithm which explores the search space for possible solutions. This study considers two dimensional site planning problems. However, it can be extended to solve three dimensional cases. A case study is presented to demonstrate the efficiency of this technique in solving the site layout planning of simple residential dwellings. © 2013 Elsevier B.V. All rights reserved.

  20. A parallel VLSI architecture for a digital filter using a number theoretic transform

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1983-01-01

    The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

  1. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  2. STORE LAYOUT FOR VIRTUAL RETAILING: A LITERATURE REVIEW

    Directory of Open Access Journals (Sweden)

    Ilyas Masudin

    2014-12-01

    Full Text Available The progress of online shopping worldwide has impacted significantly to business processes as well as customers’ behavior in shopping. Thus, research in online retailing especially in virtual store layout has been made by researchers in numerous numbers. This article attempts to explore prior research in virtual layout retails to identify the research in virtual retailing in term of the variables involved in designing the virtual store layout.

  3. Procedural facade variations from a single layout

    KAUST Repository

    Bao, Fan

    2013-01-01

    We introduce a framework to generate many variations of a facade design that look similar to a given facade layout. Starting from an input image, the facade is hierarchically segmented and labeled with a collection of manual and automatic tools. The user can then model constraints that should be maintained in any variation of the input facade design. Subsequently, facade variations are generated for different facade sizes, where multiple variations can be produced for a certain size. Computing such new facade variations has many unique challenges, and we propose a new algorithm based on interleaving heuristic search and quadratic programming. In contrast to most previous work, we focus on the generation of new design variations and not on the automatic analysis of the input\\'s structure. Adding a modeling step with the user in the loop ensures that our results routinely are of high quality. © 2013 ACM.

  4. A quantitative model for designing keyboard layout.

    Science.gov (United States)

    Shieh, K K; Lin, C C

    1999-02-01

    This study analyzed the quantitative relationship between keytapping times and ergonomic principles in typewriting skills. Keytapping times and key-operating characteristics of a female subject typing on the Qwerty and Dvorak keyboards for six weeks each were collected and analyzed. The results showed that characteristics of the typed material and the movements of hands and fingers were significantly related to keytapping times. The most significant factors affecting keytapping times were association frequency between letters, consecutive use of the same hand or finger, and the finger used. A regression equation for relating keytapping times to ergonomic principles was fitted to the data. Finally, a protocol for design of computerized keyboard layout based on the regression equation was proposed.

  5. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...... dies can be cut from a given wafer, and each cutting plan must respect various constraints on where the cuts may be placed. We present an exact algorithm for solving the minimum cutting plan problem, given a floorplan of the dies. The algorithm is based on delayed column generation, where the pricing...... problem becomes a maximum vertex-weighted clique problem in which each clique consists of cutting compatible dies. The resulting branch-and-price algorithm is able to solve realistic cutting problems to optimality in a couple of seconds....

  6. Underground design Laxemar, Layout D2

    Energy Technology Data Exchange (ETDEWEB)

    2009-11-15

    Laxemar candidate area is located in the province of Smaaland, some 320 km south of Stockholm. The area is located close to the shoreline of the Baltic Sea and is within the municipality of Oskarshamn, and immediately west of the Oskarshamn nuclear power plant and the Central interim storage facility for spent fuel (Clab). The easternmost part (Simpevarp subarea) includes the Simpevarp peninsula, which hosts the power plants and the Clab facility. The island of Aespoe, containing the Aespoe Hard Rock Laboratory is located some three kilometres northeast of the central parts of Laxemar. The Laxemar subarea covers some 12.5 km2, compared with the Simepvarp subarea, which is approximately 6.6 km2. The Laxemar candidate area has been investigated in stages, referred to as the initial site investigations (ISI) and the complete site investigations (CSI). These investigations commenced in 2002 and were completed in 2008. During the site investigations, several studies and design steps (D0, D1 and D2) were carried out to ensure that sufficient space was available for the 6,000-canister layout within the target volume at a depth of approximately 500 m. The findings from design Step D2 for the underground facilities including the access ramp, shafts, rock caverns in a Central Area, transport tunnels, and deposition tunnels and deposition holes are contained in this report. The layout for these underground excavations at the deposition horizon requires an area of 5.7 km2, and the total rock volume to be excavated is 3,008 x 103 m3 using a total tunnel length of approximately 115 km. The behaviour of the underground openings associated with this layout is expected to be similar to the behaviour of other underground openings in the Scandinavian shield at similar depths. The dominant mode of instability is expected to be structurally controlled wedge failure. Stability of the openings will be achieved with traditional underground rock support and by orienting the openings

  7. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  8. Selecting a pharmacy layout design using a weighted scoring system.

    Science.gov (United States)

    McDowell, Alissa L; Huang, Yu-Li

    2012-05-01

    A weighted scoring system was used to select a pharmacy layout redesign. Facilities layout design techniques were applied at a local hospital pharmacy using a step-by-step design process. The process involved observing and analyzing the current situation, observing the current available space, completing activity flow charts of the pharmacy processes, completing communication and material relationship charts to detail which areas in the pharmacy were related to one another and how they were related, researching applications in other pharmacies or in scholarly works that could be beneficial, numerically defining space requirements for areas within the pharmacy, measuring the available space within the pharmacy, developing a set of preliminary designs, and modifying preliminary designs so they were all acceptable to the pharmacy staff. To select a final layout that could be implemented in the pharmacy, those layouts were compared via a weighted scoring system. The weighted aspect further allowed additional emphasis on categories based on their effect on pharmacy performance. The results produced a beneficial layout design as determined through simulated models of the pharmacy operation that more effectively allocated and strategically located space to improve transportation distances and materials handling, employee utilization, and ergonomics. Facilities layout designs for a hospital pharmacy were evaluated using a weighted scoring system to identify a design that was superior to both the current layout and alternative layouts in terms of feasibility, cost, patient safety, employee safety, flexibility, robustness, transportation distance, employee utilization, objective adherence, maintainability, usability, and environmental impact.

  9. DSS 13 phase 2 pedestal room microwave layout

    Science.gov (United States)

    Cwik, T.; Chen, J. C.

    1991-01-01

    The design and predicted performance is described of the microwave layout for three band operation of the beam waveguide antenna Deep Space Station 13. Three pedestal room microwave candidate layout designs were produced for simultaneous X/S and X/Ka band operation. One of the three designs was chosen based on given constraints, and for this design the microwave performance was estimated.

  10. Layout Of Antennas And Cables In A Large Array

    Science.gov (United States)

    Logan, Ronald T., Jr.

    1995-01-01

    Layout devised to minimize total land area occupied by large phased array of antennas and to minimize total length of cables in array. In original intended application, array expanded version of array of paraboloidal-dish microwave communication antennas of Deep Space Network. Layout also advantageous for other phased arrays of antennas and antenna elements, including notably printed-circuit microwave antenna arrays.

  11. Layout Geometry in Encoding and Retrieval of Spatial Memory

    Science.gov (United States)

    Mou, Weimin; Liu, Xianyun; McNamara, Timothy P.

    2009-01-01

    Two experiments investigated whether the spatial reference directions that are used to specify objects' locations in memory can be solely determined by layout geometry. Participants studied a layout of objects from a single viewpoint while their eye movements were recorded. Subsequently, participants used memory to make judgments of relative…

  12. Layout and cabling considerations for a large communications antenna array

    Science.gov (United States)

    Logan, R. T., Jr.

    1993-01-01

    Layout considerations for a large deep space communications antenna array are discussed. A fractal geometry for the antenna layout is described that provides optimal packing of antenna elements, efficient cable routing, and logical division of the array into identical sub-arrays.

  13. Mental Layout Extrapolations Prime Spatial Processing of Scenes

    Science.gov (United States)

    Gottesman, Carmela V.

    2011-01-01

    Four experiments examined whether scene processing is facilitated by layout representation, including layout that was not perceived but could be predicted based on a previous partial view (boundary extension). In a priming paradigm (after Sanocki, 2003), participants judged objects' distances in photographs. In Experiment 1, full scenes (target),…

  14. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  15. Target aligned heliostat field layout for non-flat terrrain

    CSIR Research Space (South Africa)

    Buck, R

    2012-05-01

    Full Text Available The layout for a solar tower test facility for CSIR, Pretoria, is described. The solar tower system is designed for 400kWth receiver outlet power. The heliostat field layout takes into account both the real (non-flat) topography of the terrain...

  16. Optimization of machining fixture layout for tolerance requirements ...

    African Journals Online (AJOL)

    Dimensional accuracy of workpart under machining is strongly influenced by the layout of the fixturing elements like locators and clamps. Setup or geometrical errors in locators result in overall machining error of the feature under consideration. Therefore it is necessary to ensure that the layout is optimized for the desired ...

  17. Layout as Political Expression: Visual Literacy and the Peruvian Press.

    Science.gov (United States)

    Barnhurst, Kevin G.

    Newspaper layout and design studies ignore politics, and most studies of newspaper politics ignore visual design. News layout is generally thought to be a set of neutral, efficient practices. This study suggests that the political position of Peruvian newspapers parallels their visual presentation of terrorism. The liberal "La Republica"…

  18. Simulation Modeling of a Facility Layout in Operations Management Classes

    Science.gov (United States)

    Yazici, Hulya Julie

    2006-01-01

    Teaching quantitative courses can be challenging. Similarly, layout modeling and lean production concepts can be difficult to grasp in an introductory OM (operations management) class. This article describes a simulation model developed in PROMODEL to facilitate the learning of layout modeling and lean manufacturing. Simulation allows for the…

  19. The Offshore Wind Farm Array Cable Layout Problem

    DEFF Research Database (Denmark)

    Bauer, Joanna; Lysgaard, Jens

    2014-01-01

    In an offshore wind farm (OWF), the turbines are connected to a transformer by cable routes that cannot cross each other. Finding the minimum cost array cable layout thus amounts to a vehicle routing problem with the additional constraints that the routes must be embedded in the plane. For this p......In an offshore wind farm (OWF), the turbines are connected to a transformer by cable routes that cannot cross each other. Finding the minimum cost array cable layout thus amounts to a vehicle routing problem with the additional constraints that the routes must be embedded in the plane....... For this problem, both exact and heuristic methods are of interest. We optimize cable layouts for real-world OWFs by a hop-indexed integer programming formulation, and develop a heuristic for computing layouts based on the Clarke and Wright savings heuristic for vehicle routing. Our heuristic computes layouts...

  20. Topology-optimized metasurfaces: impact of initial geometric layout.

    Science.gov (United States)

    Yang, Jianji; Fan, Jonathan A

    2017-08-15

    Topology optimization is a powerful iterative inverse design technique in metasurface engineering and can transform an initial layout into a high-performance device. With this method, devices are optimized within a local design phase space, making the identification of suitable initial geometries essential. In this Letter, we examine the impact of initial geometric layout on the performance of large-angle (75 deg) topology-optimized metagrating deflectors. We find that when conventional metasurface designs based on dielectric nanoposts are used as initial layouts for topology optimization, the final devices have efficiencies around 65%. In contrast, when random initial layouts are used, the final devices have ultra-high efficiencies that can reach 94%. Our numerical experiments suggest that device topologies based on conventional metasurface designs may not be suitable to produce ultra-high-efficiency, large-angle metasurfaces. Rather, initial geometric layouts with non-trivial topologies and shapes are required.

  1. Optimal Control Surface Layout for an Aeroservoelastic Wingbox

    Science.gov (United States)

    Stanford, Bret K.

    2017-01-01

    This paper demonstrates a technique for locating the optimal control surface layout of an aeroservoelastic Common Research Model wingbox, in the context of maneuver load alleviation and active utter suppression. The combinatorial actuator layout design is solved using ideas borrowed from topology optimization, where the effectiveness of a given control surface is tied to a layout design variable, which varies from zero (the actuator is removed) to one (the actuator is retained). These layout design variables are optimized concurrently with a large number of structural wingbox sizing variables and control surface actuation variables, in order to minimize the sum of structural weight and actuator weight. Results are presented that demonstrate interdependencies between structural sizing patterns and optimal control surface layouts, for both static and dynamic aeroelastic physics.

  2. On the impact of layout quality to understanding UML diagrams

    DEFF Research Database (Denmark)

    Störrle, Harald

    2011-01-01

    Practical experience suggests that use and understanding of UML diagrams is greatly affected by the quality of their layout. However, existing experimental evidence for this effect is been weak and inconclusive. In this paper, we explore two explanations. Firstly, we observe that the visual...... qualities of diagrams are more prominent in earlier life cycle phases so that the impact of layout quality should be more apparent in models and diagram types used there, an aspect not studied in previous research. Secondly, in practice, good layouts use many different heuristics simultaneously whereas...... previous research considered them in isolation only. In this paper, we report the results of a series of controlled experiments using compound layouts on requirements analysis models. With very high significance, we find a notable impact of the layout quality measured by different aspects of cognitive load....

  3. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  4. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    OpenAIRE

    T. Kalavathi Devi; Sakthivel Palaniappan

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the powe...

  5. A generic algorithm for layout of biological networks.

    Science.gov (United States)

    Schreiber, Falk; Dwyer, Tim; Marriott, Kim; Wybrow, Michael

    2009-11-12

    Biological networks are widely used to represent processes in biological systems and to capture interactions and dependencies between biological entities. Their size and complexity is steadily increasing due to the ongoing growth of knowledge in the life sciences. To aid understanding of biological networks several algorithms for laying out and graphically representing networks and network analysis results have been developed. However, current algorithms are specialized to particular layout styles and therefore different algorithms are required for each kind of network and/or style of layout. This increases implementation effort and means that new algorithms must be developed for new layout styles. Furthermore, additional effort is necessary to compose different layout conventions in the same diagram. Also the user cannot usually customize the placement of nodes to tailor the layout to their particular need or task and there is little support for interactive network exploration. We present a novel algorithm to visualize different biological networks and network analysis results in meaningful ways depending on network types and analysis outcome. Our method is based on constrained graph layout and we demonstrate how it can handle the drawing conventions used in biological networks. The presented algorithm offers the ability to produce many of the fundamental popular drawing styles while allowing the exibility of constraints to further tailor these layouts.

  6. Task-specific performance effects with different numeric keypad layouts.

    Science.gov (United States)

    Armand, Jenny T; Redick, Thomas S; Poulsen, Joan R

    2014-07-01

    Two commonly used keypad arrangements are the telephone and calculator layouts. The purpose of this study was to determine if entering different types of numeric information was quicker and more accurate with the telephone or the calculator layout on a computer keyboard numeric keypad. Fifty-seven participants saw a 10-digit numeric stimulus to type with a computer number keypad as quickly and as accurately as possible. Stimuli were presented in either a numerical [1,234,567,890] or phone [(123) 456-7890] format. The results indicated that participants' memory of the layout for the arrangement of keys on a telephone was significantly better than the layout of a calculator. In addition, the results showed that participants were more accurate when entering stimuli using the calculator keypad layout. Critically, participants' response times showed an interaction of stimulus format and keypad layout: participants were specifically slowed when entering numeric stimuli using a telephone keypad layout. Responses made using the middle row of keys were faster and more accurate than responses using the top and bottom row of keys. Implications for keypad design and cell phone usage are discussed. Copyright © 2013 Elsevier Ltd and The Ergonomics Society. All rights reserved.

  7. A generic algorithm for layout of biological networks

    Directory of Open Access Journals (Sweden)

    Dwyer Tim

    2009-11-01

    Full Text Available Abstract Background Biological networks are widely used to represent processes in biological systems and to capture interactions and dependencies between biological entities. Their size and complexity is steadily increasing due to the ongoing growth of knowledge in the life sciences. To aid understanding of biological networks several algorithms for laying out and graphically representing networks and network analysis results have been developed. However, current algorithms are specialized to particular layout styles and therefore different algorithms are required for each kind of network and/or style of layout. This increases implementation effort and means that new algorithms must be developed for new layout styles. Furthermore, additional effort is necessary to compose different layout conventions in the same diagram. Also the user cannot usually customize the placement of nodes to tailor the layout to their particular need or task and there is little support for interactive network exploration. Results We present a novel algorithm to visualize different biological networks and network analysis results in meaningful ways depending on network types and analysis outcome. Our method is based on constrained graph layout and we demonstrate how it can handle the drawing conventions used in biological networks. Conclusion The presented algorithm offers the ability to produce many of the fundamental popular drawing styles while allowing the exibility of constraints to further tailor these layouts.

  8. Fast grid layout algorithm for biological networks with sweep calculation.

    Science.gov (United States)

    Kojima, Kaname; Nagasaki, Masao; Miyano, Satoru

    2008-06-15

    Properly drawn biological networks are of great help in the comprehension of their characteristics. The quality of the layouts for retrieved biological networks is critical for pathway databases. However, since it is unrealistic to manually draw biological networks for every retrieval, automatic drawing algorithms are essential. Grid layout algorithms handle various biological properties such as aligning vertices having the same attributes and complicated positional constraints according to their subcellular localizations; thus, they succeed in providing biologically comprehensible layouts. However, existing grid layout algorithms are not suitable for real-time drawing, which is one of requisites for applications to pathway databases, due to their high-computational cost. In addition, they do not consider edge directions and their resulting layouts lack traceability for biochemical reactions and gene regulations, which are the most important features in biological networks. We devise a new calculation method termed sweep calculation and reduce the time complexity of the current grid layout algorithms through its encoding and decoding processes. We conduct practical experiments by using 95 pathway models of various sizes from TRANSPATH and show that our new grid layout algorithm is much faster than existing grid layout algorithms. For the cost function, we introduce a new component that penalizes undesirable edge directions to avoid the lack of traceability in pathways due to the differences in direction between in-edges and out-edges of each vertex. Java implementations of our layout algorithms are available in Cell Illustrator. masao@ims.u-tokyo.ac.jp Supplementary data are available at Bioinformatics online.

  9. Optimal lay-out design for coal stockpiles

    Energy Technology Data Exchange (ETDEWEB)

    Oberrisser, H. [Voest-Alpine Materials Handling GmbH and Co KG, Zeltweg (Austria)

    2006-07-01

    This article reviews current 'state of the art' concepts regarding lay-out and equipment for coal terminals. It groups these ideas into a workable set of guidelines for the coal mine or stockyard operator. The article concludes with four appropriate cases. The selection of the best suitable layout of the stockpile and equipment for coal storage and coal terminals is determined by a number of important criteria. A detailed analysis of process relevant requirements as well as an economic and ecological evaluation will result either in a conventional longitudinal or in a circular coal pile layout. (orig.)

  10. Neighboring Structure Visualization on a Grid-based Layout.

    Science.gov (United States)

    Marcou, G; Horvath, D; Varnek, A

    2017-10-01

    Here, we describe an algorithm to visualize chemical structures on a grid-based layout in such a way that similar structures are neighboring. It is based on structure reordering with the help of the Hilbert Schmidt Independence Criterion, representing an empirical estimate of the Hilbert-Schmidt norm of the cross-covariance operator. The method can be applied to any layout of bi- or three-dimensional shape. The approach is demonstrated on a set of dopamine D5 ligands visualized on squared, disk and spherical layouts. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. Optimization of offshore wind farm layout in restricted zones

    DEFF Research Database (Denmark)

    Hou, Peng; Hu, Weihao; Chen, Cong

    2016-01-01

    In this research, an optimization method for offshore wind farm layout design is proposed. With the purpose of maximizing the energy production of the wind farm, the wind turbine (WT) positions are optimized. Due to the limitations of seabed conditions, marine traffic limitations or shipwrecks, etc...... with multiple adaptive methods (PSO-MAM) is adopted. The simulation results indicate that the proposed method can find a layout which outperforms a baseline layout of a reference wind farm (RWF) by increasing the energy yield by 3.84%....

  12. Analysis of ocular surface area for comfortable VDT workstation layout.

    Science.gov (United States)

    Sotoyama, M; Jonai, H; Saito, S; Villanueva, M B

    1996-06-01

    This paper proposes a comfortable visual display terminal (VDT) workstation layout based on an analysis of ocular surface area (OSA). A large OSA induces eye irritation and eye fatigue because the eye surface is highly sensitive to various stimuli. The authors considered that OSA must be one of the useful indices of visual ergonomics and applied it to evaluate VDT workstation layout. Each subject was asked to perform a word processing task using four different VDT workstation layouts. It was found that the main factor affecting OSA was not cathode ray tube (CRT) height itself but the distance between the CRT and keyboard. Thus the following workstation layout is recommended to realize comfortable VDT operation: (1) the desk height should be adjusted to the user's height; and (2) the CRT display should be set closer to the keyboard to provide a smaller OSA.

  13. Optimal Material Layout - Applied on Reinforced Concrete Slabs

    DEFF Research Database (Denmark)

    Dollerup, Niels; Jepsen, Michael S.; Damkilde, Lars

    2015-01-01

    This paper introduces a general, finite-element-based optimisation tool for improving the material layout of concrete structures. The application presented is general and exemplified by material optimisation of reinforced concrete slabs. By utilising the optimisation tool, it is possible to deter......This paper introduces a general, finite-element-based optimisation tool for improving the material layout of concrete structures. The application presented is general and exemplified by material optimisation of reinforced concrete slabs. By utilising the optimisation tool, it is possible...... to determine the optimal material layout of a slab in the ultimate load state, based on simple inputs such as outer geometry, boundary conditions, multiple load cases and design domains. The material layout of the optimal design can either be fully orthotropic or isotropic, or a combination with a predefined......, a number of reinforced concrete slab examples validate the method described and show the potential of saving large amounts of material in constructions....

  14. Learning Layouts for Single-Page Graphic Designs.

    Science.gov (United States)

    O'Donovan, Peter; Agarwala, Aseem; Hertzmann, Aaron

    2014-08-01

    This paper presents an approach for automatically creating graphic design layouts using a new energy-based model derived from design principles. The model includes several new algorithms for analyzing graphic designs, including the prediction of perceived importance, alignment detection, and hierarchical segmentation. Given the model, we use optimization to synthesize new layouts for a variety of single-page graphic designs. Model parameters are learned with Nonlinear Inverse Optimization (NIO) from a small number of example layouts. To demonstrate our approach, we show results for applications including generating design layouts in various styles, retargeting designs to new sizes, and improving existing designs. We also compare our automatic results with designs created using crowdsourcing and show that our approach performs slightly better than novice designers.

  15. Designing robust layout in cellular manufacturing systems with uncertain demands

    Directory of Open Access Journals (Sweden)

    Kamran Forghani

    2013-04-01

    Full Text Available In this paper, a new robust approach is presented to handle demand uncertainty in cell formation and layout design process. Unlike the scenario based approaches, which use predefined scenarios to represent data uncertainty, in this paper, an interval approach is implemented to address data uncertainty for the part demands, which is more realistic and practical. The objective is to minimize the total inter- and intra-cell material handling cost. The proposed model gives machine cells and determines inter-and intra-cell layouts in such a way that the decision maker can control the robustness of the layout against the level of conservatism. An illustrative example is solved by CPLEX 10 to demonstrate the performance of the proposed method. The results reveal that when the level of conservatism is changed the optimal layout can vary, significantly.

  16. Learning and optimization with cascaded VLSI neural network building-block chips

    Science.gov (United States)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  17. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  18. Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

    Directory of Open Access Journals (Sweden)

    S. Jayanthy

    2012-01-01

    Full Text Available As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG method based on a modified Fanout Oriented (FAN to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

  19. A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

    Science.gov (United States)

    Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

    2010-01-01

    We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

  20. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  1. Estimating perception of scene layout properties from global image features.

    Science.gov (United States)

    Ross, Michael G; Oliva, Aude

    2010-01-08

    The relationship between image features and scene structure is central to the study of human visual perception and computer vision, but many of the specifics of real-world layout perception remain unknown. We do not know which image features are relevant to perceiving layout properties, or whether those features provide the same information for every type of image. Furthermore, we do not know the spatial resolutions required for perceiving different properties. This paper describes an experiment and a computational model that provides new insights on these issues. Humans perceive the global spatial layout properties such as dominant depth, openness, and perspective, from a single image. This work describes an algorithm that reliably predicts human layout judgments. This model's predictions are general, not specific to the observers it trained on. Analysis reveals that the optimal spatial resolutions for determining layout vary with the content of the space and the property being estimated. Openness is best estimated at high resolution, depth is best estimated at medium resolution, and perspective is best estimated at low resolution. Given the reliability and simplicity of estimating the global layout of real-world environments, this model could help resolve perceptual ambiguities encountered by more detailed scene reconstruction schemas.

  2. Global scene layout modulates contextual learning in change detection.

    Science.gov (United States)

    Conci, Markus; Müller, Hermann J

    2014-01-01

    Change in the visual scene often goes unnoticed - a phenomenon referred to as "change blindness." This study examined whether the hierarchical structure, i.e., the global-local layout of a scene can influence performance in a one-shot change detection paradigm. To this end, natural scenes of a laid breakfast table were presented, and observers were asked to locate the onset of a new local object. Importantly, the global structure of the scene was manipulated by varying the relations among objects in the scene layouts. The very same items were either presented as global-congruent (typical) layouts or as global-incongruent (random) arrangements. Change blindness was less severe for congruent than for incongruent displays, and this congruency benefit increased with the duration of the experiment. These findings show that global layouts are learned, supporting detection of local changes with enhanced efficiency. However, performance was not affected by scene congruency in a subsequent control experiment that required observers to localize a static discontinuity (i.e., an object that was missing from the repeated layouts). Our results thus show that learning of the global layout is particularly linked to the local objects. Taken together, our results reveal an effect of "global precedence" in natural scenes. We suggest that relational properties within the hierarchy of a natural scene are governed, in particular, by global image analysis, reducing change blindness for local objects through scene learning.

  3. Global scene layout modulates contextual learning in change detection

    Directory of Open Access Journals (Sweden)

    Markus eConci

    2014-02-01

    Full Text Available Change in the visual scene often goes unnoticed – a phenomenon referred to as ‘change blindness’. This study examined whether the hierarchical structure, i.e., the global-local layout of a scene can influence performance in a one-shot change detection paradigm. To this end, natural scenes of a laid breakfast table were presented, and observers were asked to locate the onset of a new local object. Importantly, the global structure of the scene was manipulated by varying the relations among objects in the scene layouts. The very same items were either presented as global-congruent (typical layouts or as global-incongruent (random arrangements. Change blindness was less severe for congruent than for incongruent displays, and this congruency benefit increased with the duration of the experiment. These findings show that global layouts are learned, supporting detection of local changes with enhanced efficiency. However, performance was not affected by scene congruency in a subsequent control experiment that required observers to localize a static discontinuity (i.e., an object that was missing from the repeated layouts. Our results thus show that learning of the global layout is particularly linked to the local objects. Taken together, our results reveal an effect of global precedence in natural scenes. We suggest that relational properties within the hierarchy of a natural scene are governed, in particular, by global image analysis, reducing change blindness for local objects through scene learning.

  4. Scalable force directed graph layout algorithms using fast multipole methods

    KAUST Repository

    Yunis, Enas Abdulrahman

    2012-06-01

    We present an extension to ExaFMM, a Fast Multipole Method library, as a generalized approach for fast and scalable execution of the Force-Directed Graph Layout algorithm. The Force-Directed Graph Layout algorithm is a physics-based approach to graph layout that treats the vertices V as repelling charged particles with the edges E connecting them acting as springs. Traditionally, the amount of work required in applying the Force-Directed Graph Layout algorithm is O(|V|2 + |E|) using direct calculations and O(|V| log |V| + |E|) using truncation, filtering, and/or multi-level techniques. Correct application of the Fast Multipole Method allows us to maintain a lower complexity of O(|V| + |E|) while regaining most of the precision lost in other techniques. Solving layout problems for truly large graphs with millions of vertices still requires a scalable algorithm and implementation. We have been able to leverage the scalability and architectural adaptability of the ExaFMM library to create a Force-Directed Graph Layout implementation that runs efficiently on distributed multicore and multi-GPU architectures. © 2012 IEEE.

  5. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    Science.gov (United States)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  6. Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits

    OpenAIRE

    Georgiev, Zdravko

    2013-01-01

    The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and analyse the impact of the NBTI. Other tools able to analyse the NBTI, are often on very low design le...

  7. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  8. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  9. 32 CFR 553.7 - Design and layout of Army national cemeteries.

    Science.gov (United States)

    2010-07-01

    ... 32 National Defense 3 2010-07-01 2010-07-01 true Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

  10. Automatic yield-line analysis of slabs using discontinuity layout optimization.

    Science.gov (United States)

    Gilbert, Matthew; He, Linwei; Smith, Colin C; Le, Canh V

    2014-08-08

    The yield-line method of analysis is a long established and extremely effective means of estimating the maximum load sustainable by a slab or plate. However, although numerous attempts to automate the process of directly identifying the critical pattern of yield-lines have been made over the past few decades, to date none has proved capable of reliably analysing slabs of arbitrary geometry. Here, it is demonstrated that the discontinuity layout optimization (DLO) procedure can successfully be applied to such problems. The procedure involves discretization of the problem using nodes inter-connected by potential yield-line discontinuities, with the critical layout of these then identified using linear programming. The procedure is applied to various benchmark problems, demonstrating that highly accurate solutions can be obtained, and showing that DLO provides a truly systematic means of directly and reliably automatically identifying yield-line patterns. Finally, since the critical yield-line patterns for many problems are found to be quite complex in form, a means of automatically simplifying these is presented.

  11. SIMPLIFIED MATHEMATICAL MODEL OF SMALL SIZED UNMANNED AIRCRAFT VEHICLE LAYOUT

    Directory of Open Access Journals (Sweden)

    2016-01-01

    Full Text Available Strong reduction of new aircraft design period using new technology based on artificial intelligence is the key problem mentioned in forecasts of leading aerospace industry research centers. This article covers the approach to devel- opment of quick aerodynamic design methods based on artificial intelligence neural system. The problem is being solved for the classical scheme of small sized unmanned aircraft vehicle (UAV. The principal parts of the method are the mathe- matical model of layout, layout generator of this type of aircraft is built on aircraft neural networks, automatic selection module for cleaning variety of layouts generated in automatic mode, robust direct computational fluid dynamics method, aerodynamic characteristics approximators on artificial neural networks.Methods based on artificial neural networks have intermediate position between computational fluid dynamics methods or experiments and simplified engineering approaches. The use of ANN for estimating aerodynamic characteris-tics put limitations on input data. For this task the layout must be presented as a vector with dimension not exceeding sev-eral hundred. Vector components must include all main parameters conventionally used for layouts description and com- pletely replicate the most important aerodynamics and structural properties.The first stage of the work is presented in the paper. Simplified mathematical model of small sized UAV was developed. To estimate the range of geometrical parameters of layouts the review of existing vehicle was done. The result of the work is the algorithm and computer software for generating the layouts based on ANN technolo-gy. 10000 samples were generated and the dataset containig geometrical and aerodynamic characteristics of layoutwas created.

  12. An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location information.

    Science.gov (United States)

    Kojima, Kaname; Nagasaki, Masao; Miyano, Satoru

    2010-06-18

    Graph drawing is one of the important techniques for understanding biological regulations in a cell or among cells at the pathway level. Among many available layout algorithms, the spring embedder algorithm is widely used not only for pathway drawing but also for circuit placement and www visualization and so on because of the harmonized appearance of its results. For pathway drawing, location information is essential for its comprehension. However, complex shapes need to be taken into account when torus-shaped location information such as nuclear inner membrane, nuclear outer membrane, and plasma membrane is considered. Unfortunately, the spring embedder algorithm cannot easily handle such information. In addition, crossings between edges and nodes are usually not considered explicitly. We proposed a new grid-layout algorithm based on the spring embedder algorithm that can handle location information and provide layouts with harmonized appearance. In grid-layout algorithms, the mapping of nodes to grid points that minimizes a cost function is searched. By imposing positional constraints on grid points, location information including complex shapes can be easily considered. Our layout algorithm includes the spring embedder cost as a component of the cost function. We further extend the layout algorithm to enable dynamic update of the positions and sizes of compartments at each step. The new spring embedder-based grid-layout algorithm and a spring embedder algorithm are applied to three biological pathways; endothelial cell model, Fas-induced apoptosis model, and C. elegans cell fate simulation model. From the positional constraints, all the results of our algorithm satisfy location information, and hence, more comprehensible layouts are obtained as compared to the spring embedder algorithm. From the comparison of the number of crossings, the results of the grid-layout-based algorithm tend to contain more crossings than those of the spring embedder algorithm due to

  13. A flexible layout design method for passive micromixers.

    Science.gov (United States)

    Deng, Yongbo; Liu, Zhenyu; Zhang, Ping; Liu, Yongshun; Gao, Qingyong; Wu, Yihui

    2012-10-01

    This paper discusses a flexible layout design method of passive micromixers based on the topology optimization of fluidic flows. Being different from the trial and error method, this method obtains the detailed layout of a passive micromixer according to the desired mixing performance by solving a topology optimization problem. Therefore, the dependence on the experience of the designer is weaken, when this method is used to design a passive micromixer with acceptable mixing performance. Several design disciplines for the passive micromixers are considered to demonstrate the flexibility of the layout design method for passive micromixers. These design disciplines include the approximation of the real 3D micromixer, the manufacturing feasibility, the spacial periodic design, and effects of the Péclet number and Reynolds number on the designs obtained by this layout design method. The capability of this design method is validated by several comparisons performed between the obtained layouts and the optimized designs in the recently published literatures, where the values of the mixing measurement is improved up to 40.4% for one cycle of the micromixer.

  14. The Influence of Environmental Spatial Layout on Perceived Lightness

    Science.gov (United States)

    Kanari, Kei; Inagami, Makoto; Kaneko, Hirohiko

    2011-01-01

    It is obvious that perceived lightness of a surface depends on the surrounding luminance distribution in 2D and 3D. These effects are usually explained by the mechanisms at relatively low level of visual system. However, there seems to be a relation between the illuminance and spatial layout of the scene regardless of the surrounding luminance distribution. If this is valid, perceived lightness of a surface in the scene could be influenced by the spatial layout in the scene. In this research, we investigated the relation between the perceived lightness of surface and the spatial layout of the scene. The subject matched the lightness of test patch presented on a natural picture with various spatial layout to that of comparison stimulus presented on a uniform gray background. The mean luminance of the surround stimuli were the same and the local contrast between the text patch and the surround was kept constant. Results showed that the perceived lightness of a stimulus depended on the spatial structure presented in the background. This result indicates that the spatial layout of the scene is related to the illuminance of that and influenced on perceived lightness.

  15. Genetic Algorithm (GA)-Based Inclinometer Layout Optimization.

    Science.gov (United States)

    Liang, Weijie; Zhang, Ping; Chen, Xianping; Cai, Miao; Yang, Daoguo

    2015-04-17

    This paper presents numerical simulation results of an airflow inclinometer with sensitivity studies and thermal optimization of the printed circuit board (PCB) layout for an airflow inclinometer based on a genetic algorithm (GA). Due to the working principle of the gas sensor, the changes of the ambient temperature may cause dramatic voltage drifts of sensors. Therefore, eliminating the influence of the external environment for the airflow is essential for the performance and reliability of an airflow inclinometer. In this paper, the mechanism of an airflow inclinometer and the influence of different ambient temperatures on the sensitivity of the inclinometer will be examined by the ANSYS-FLOTRAN CFD program. The results show that with changes of the ambient temperature on the sensing element, the sensitivity of the airflow inclinometer is inversely proportional to the ambient temperature and decreases when the ambient temperature increases. GA is used to optimize the PCB thermal layout of the inclinometer. The finite-element simulation method (ANSYS) is introduced to simulate and verify the results of our optimal thermal layout, and the results indicate that the optimal PCB layout greatly improves (by more than 50%) the sensitivity of the inclinometer. The study may be useful in the design of PCB layouts that are related to sensitivity improvement of gas sensors.

  16. Vertical Object Layout and Compression for Fixed Heaps

    Science.gov (United States)

    Titzer, Ben L.; Palsberg, Jens

    Research into embedded sensor networks has placed increased focus on the problem of developing reliable and flexible software for microcontroller-class devices. Languages such as nesC [10] and Virgil [20] have brought higher-level programming idioms to this lowest layer of software, thereby adding expressiveness. Both languages are marked by the absence of dynamic memory allocation, which removes the need for a runtime system to manage memory. While nesC offers code modules with statically allocated fields, arrays and structs, Virgil allows the application to allocate and initialize arbitrary objects during compilation, producing a fixed object heap for runtime. This paper explores techniques for compressing fixed object heaps with the goal of reducing the RAM footprint of a program. We explore table-based compression and introduce a novel form of object layout called vertical object layout. We provide experimental results that measure the impact on RAM size, code size, and execution time for a set of Virgil programs. Our results show that compressed vertical layout has better execution time and code size than table-based compression while achieving more than 20% heap reduction on 6 of 12 benchmark programs and 2-17% heap reduction on the remaining 6. We also present a formalization of vertical object layout and prove tight relationships between three styles of object layout.

  17. SpicyNodes: radial layout authoring for the general public.

    Science.gov (United States)

    Douma, Michael; Ligierko, Grzegorz; Ancuta, Ovidiu; Gritsai, Pavel; Liu, Sean

    2009-01-01

    Trees and graphs are relevant to many online tasks such as visualizing social networks, product catalogs, educational portals, digital libraries, the semantic web, concept maps and personalized information management. SpicyNodes is an information-visualization technology that builds upon existing research on radial tree layouts and graph structures. Users can browse a tree, clicking from node to node, as well as successively viewing a node, immediately related nodes and the path back to the "home" nodes. SpicyNodes' layout algorithms maintain balanced layouts using a hybrid mixture of a geometric layout (a succession of spanning radial trees) and force-directed layouts to minimize overlapping nodes, plus several other improvements over prior art. It provides XML-based API and GUI authoring tools. The goal of the SpicyNodes project is to implement familiar principles of radial maps and focus+context with an attractive and inviting look and feel in an open system that is accessible to virtually any Internet user.

  18. Production layout improvement in emergency services: a participatory approach.

    Science.gov (United States)

    Zanatta, Mateus; Amaral, Fernando Gonçalves

    2012-01-01

    Volunteer fire department is a service that responds emergency situations in places where there are no military emergency services. These services need to respond quickly, because time is often responsible for the operation success besides work environment and setup time interfere with the prompt response to these calls and care efficiency. The layout design is one factor that interferes with the quick setup. In this case, the spaces arrangement can result in excessive or unnecessary movements; also the equipment provision may hinder the selection and collection of these or even create movement barriers for the workers. This work created a new layout for the emergency assistance service, considering the human factors related to work through the task analysis and workers participation on the alternatives of improvement. The results showed an alternate layout with corridors and minimization of unusable sites, allowing greater flexibility and new possibilities of requirements.

  19. How the global layout of the mask influences masking strength.

    Science.gov (United States)

    Ghose, Tandra; Hermens, Frouke; Herzog, Michael H

    2012-12-10

    In visual backward masking, the perception of a target is influenced by a trailing mask. Masking is usually explained by local interactions between the target and the mask representations. However, recently it has been shown that the global spatial layout of the mask rather than its local structure determines masking strength (Hermens & Herzog, 2007). Here, we varied the mask layout by spatial, luminance, and temporal cues. We presented a vernier target followed by a mask with 25 elements. Performance deteriorated when the length of the two mask elements neighboring the target vernier was doubled. However, when the length of every second mask element was doubled, performance improved. When the luminance of the neighboring elements was doubled, performance also deteriorated but no improvement in performance was observed when every second element had a double luminance. For temporal manipulations, a complex nonmonotonic masking function was observed. Hence, changes in the mask layout by spatial, luminance, and temporal cues lead to highly different results.

  20. Analysis of Sequence Diagram Layout in Advanced UML Modelling Tools

    Directory of Open Access Journals (Sweden)

    Ņikiforova Oksana

    2016-05-01

    Full Text Available System modelling using Unified Modelling Language (UML is the task that should be solved for software development. The more complex software becomes the higher requirements are stated to demonstrate the system to be developed, especially in its dynamic aspect, which in UML is offered by a sequence diagram. To solve this task, the main attention is devoted to the graphical presentation of the system, where diagram layout plays the central role in information perception. The UML sequence diagram due to its specific structure is selected for a deeper analysis on the elements’ layout. The authors research represents the abilities of modern UML modelling tools to offer automatic layout of the UML sequence diagram and analyse them according to criteria required for the diagram perception.

  1. Joint Graph Layouts for Visualizing Collections of Segmented Meshes

    KAUST Repository

    Ren, Jing

    2017-09-12

    We present a novel and efficient approach for computing joint graph layouts and then use it to visualize collections of segmented meshes. Our joint graph layout algorithm takes as input the adjacency matrices for a set of graphs along with partial, possibly soft, correspondences between nodes of different graphs. We then use a two stage procedure, where in the first step, we extend spectral graph drawing to include a consistency term so that a collection of graphs can be handled jointly. Our second step extends metric multi-dimensional scaling with stress majorization to the joint layout setting, while using the output of the spectral approach as initialization. Further, we discuss a user interface for exploring a collection of graphs. Finally, we show multiple example visualizations of graphs stemming from collections of segmented meshes and we present qualitative and quantitative comparisons with previous work.

  2. Complete PCB design using OrCAD capture and layout

    CERN Document Server

    Mitzner, Kraig

    2011-01-01

    This book provides instruction on how to use the OrCAD design suite to design and manufacture printed circuit boards. The book is written for both students and practicing engineers who need a quick tutorial on how to use the software and who need in-depth knowledge of the capabilities and limitations of the software package. There are two goals the book aims to reach:The primary goal is to show the reader how to design a PCB using OrCAD Capture and OrCAD Layout. Capture is used to build the schematic diagram of the circuit, and Layout is used to design the circuit board so that

  3. Urban pattern: Layout design by hierarchical domain splitting

    KAUST Repository

    Yang, Yongliang

    2013-11-01

    We present a framework for generating street networks and parcel layouts. Our goal is the generation of high-quality layouts that can be used for urban planning and virtual environments. We propose a solution based on hierarchical domain splitting using two splitting types: streamline-based splitting, which splits a region along one or multiple streamlines of a cross field, and template-based splitting, which warps pre-designed templates to a region and uses the interior geometry of the template as the splitting lines. We combine these two splitting approaches into a hierarchical framework, providing automatic and interactive tools to explore the design space.

  4. Collimator Layouts for HL-LHC in the Experimental Insertions

    CERN Document Server

    Bruce, R; Esposito, Luigi Salvatore; Jowett, John; Lechner, Anton; Quaranta, Elena; Redaelli, Stefano; Schaumann, Michaela; Skordis, Eleftherios; Eleanor Steele, G; Garcia Morales, H; Kwee-Hinzmann, Regina

    2015-01-01

    This paper presents the layout of collimators for HL-LHC in the experimental insertions. On the incoming beam, we propose to install additional tertiary collimators to protect potential new aperture bottlenecks in cells 4 and 5, which in addition reduce the experimental background. For the outgoing beam, the layout of the present LHC with three physics debris absorbers gives sufficient protection for highluminosity proton operation. However, collisional processes for heavy ions cause localized beam losses with the potential to quench magnets. To alleviate these losses, an installation of dispersion suppressor collimators is proposed.

  5. Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI.

    Science.gov (United States)

    1987-06-01

    Verlag Lecture Notes 201, 1985. [She84] M. Sheeran , "muFP, a language for VLSI design", Proc. 1984 ACM Conference on LISP and Functional Programming...fMeshkinpour8S5 and Sheeran (Sheeran84] extended Backus’ Fl? language with operators to handle sequential circuits. 2 Brief Introduction to vFP vFP...Spring 1913, pp. 274-277. (201 Sheeran , M., "muFP, a Language for VLSI Design." Proc 1984 ACM Conference on LU and Functional Programming. August [4

  6. Microscale Adaptive Optics: Wave-Front Control with a mu-Mirror Array and a VLSI Stochastic Gradient Descent Controller.

    Science.gov (United States)

    Weyrauch, T; Vorontsov, M A; Bifano, T G; Hammer, J A; Cohen, M; Cauwenberghs, G

    2001-08-20

    The performance of adaptive systems that consist of microscale on-chip elements [microelectromechanical mirror (mu-mirror) arrays and a VLSI stochastic gradient descent microelectronic control system] is analyzed. The mu-mirror arrays with 5 x 5 and 6 x 6 actuators were driven with a control system composed of two mixed-mode VLSI chips implementing model-free beam-quality metric optimization by the stochastic parallel perturbative gradient descent technique. The adaptation rate achieved was near 6000 iterations/s. A secondary (learning) feedback loop was used to control system parameters during the adaptation process, further increasing the adaptation rate.

  7. An effective timing characterization method for an accuracy-proved VLSI standard cell library

    Science.gov (United States)

    Jianhua, Jiang; Man, Liang; Lei, Wang; Yumei, Zhou

    2014-02-01

    This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

  8. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  9. High-performance fault-tolerant VLSI systems using micro rollback

    Science.gov (United States)

    Tamir, Yuval; Tremblay, Marc

    1990-01-01

    A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.

  10. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  11. Creating a Single South African Keyboard Layout to Promote ...

    African Journals Online (AJOL)

    R.B. Ruthven

    Abstract: In this case study, a description is given of a keyboard layout designed to address the input needs of South African languages, specifically Venda, a language which would otherwise be impossible to type on a computer. In creating this keyboard, the designer, Translate.org.za, uses a practical intervention that ...

  12. Multiple Regression in a Two-Way Layout.

    Science.gov (United States)

    Lindley, Dennis V.

    This paper discusses Bayesian m-group regression where the groups are arranged in a two-way layout into m rows and n columns, there still being a regression of y on the x's within each group. The mathematical model is then provided as applied to the case where the rows correspond to high schools and the columns to colleges: the predictor variables…

  13. FORMALIZED PROJECT METHODOLOGY OF EFFECTIVE LAYOUT PLANNING FOR INNOVATIVE UNIVERSITY

    Directory of Open Access Journals (Sweden)

    Alexey I. Sirotkin

    2015-01-01

    Full Text Available The article deals with the university’s effective use of its premises as part of the concept of exercising ownership powers by Ministry of Education and Science of the Russian Federation in relation to property of its affiliates. To solve this problem, the applicability of formalized project methodology of effective layout planning for innovative university is analyzed.

  14. CONTROLLABILITY OF TRADITIONAL NEIGHBORHOOD AND ITS SIMPLIFIED LAYOUT

    Directory of Open Access Journals (Sweden)

    M. Salim Ferwati

    2010-03-01

    Full Text Available Street hierarchy, as a way of presenting intended information, conforms to social rules that underlay architectural and urban designs to create public, semi-public, and semi-private. These social rules have the responsibility to convey necessary information about place to outsiders as well as to insiders. This research looks at urban spaces as physical structures that represent foci of attention of users and that are collectively a part of the social pattern framework. The argument of this study is that connectivity and forms of streets house certain social rules that intended to serve users, so that any changes in the street layout lead to changes in its social rules. As a case study, the complexity of a walled Arab neighborhood was examined through Sur Lawatyia, located in Muscat Governorate, Oman. By replacing the curvilinear and broken streets of this neighborhood with straight ones; a simplified street layout was derived. Then, a comparison of both street layouts was carried out through mapping, tabulation, charts, correlation test, and with reliance on the method of measurement of street control values introduced by Hillier and Hanson in 1984. The result was that the simple form is far short to be the representation of the space syntax of the traditional street layout.

  15. Brayton Isotope Power System (BIPS) design layout summary

    Energy Technology Data Exchange (ETDEWEB)

    1976-06-15

    A summary of the Brayton Isotope Power Systems (BIPS) design layout drawings is presented. These drawings were generated in compliance with Task 3 (Preliminary Design of the BIPS Ground Demonstration System) of Phase I of the ERDA sponsored BIPS contract E(04-3)-1123.

  16. Generation of printed circuit board layout and artwork | Debretsion ...

    African Journals Online (AJOL)

    Printed circuit board (PCB) design plays an important role on equipment performance and reliability. Constraint imposed on PCB size under severe environmental condition is focused. Guidelines for layout planning, its speedy execution, component· placements, and future growth/modifications have been addressed.

  17. FOOD safety and hygiene - Systematic layout planning of food processes

    NARCIS (Netherlands)

    Van Donk, DP; Gaalman, G

    2004-01-01

    Hygiene and food safety have been dealt with from different fields of science such as biology and health, and from different angles such as HACCP and GMP. Little systematically ordered knowledge is available for the analysis of a layout, taking hygienic factors into account. HACCP and GMP are

  18. Creating a single South African keyboard layout to promote language

    African Journals Online (AJOL)

    In this case study, a description is given of a keyboard layout designed to address the input needs of South African languages, specifically Venda, a language which would otherwise be impossible to type on a computer. In creating this keyboard, the designer, Translate.org.za, uses a practical intervention that transforms ...

  19. Why multicamp layouts? | BR | African Journal of Range and Forage ...

    African Journals Online (AJOL)

    Although it has become standard practice in Southern Africa to recommend grazing systems based on a maximum of five camps, there are indications that the use of multicamp layouts, employing a greater number of camps per herd, may increase the efficiency of animal production from natural veld. The basic advantage of ...

  20. Representing Spatial Layout According to Intrinsic Frames of Reference.

    Science.gov (United States)

    Xie, Chaoxiang; Li, Shiyi; Tao, Weidong; Wei, Yiping; Sun, Hong-Jin

    2017-01-01

    Mou and McNamara have suggested that object locations are represented according to intrinsic reference frames. In three experiments, we investigated the limitations of intrinsic reference frames as a mean to represent object locations in spatial memory. Participants learned the locations of seven or eight common objects in a rectangular room and then made judgments of relative direction based on their memory of the layout. The results of all experiments showed that when all objects were positioned regularly, judgments of relative direction were faster or more accurate for novel headings that were aligned with the primary intrinsic structure than for other novel headings; however, when one irregularly positioned object was added to the layout, this advantage was eliminated. The experiments further indicated that with a single view at study, participants could represent the layout from either an egocentric orientation or a different orientation, according to experimental instructions. Together, these results suggest that environmental reference frames and intrinsic axes can influence performance for novel headings, but their role in spatial memory depends on egocentric experience, layout regularity, and instructions.

  1. Product Category Layout and Organization: Retail Placement of Food Products

    NARCIS (Netherlands)

    Herpen, van E.

    2016-01-01

    This article discusses the placement of food products in retail stores, in particular how the placement of food products can influence how consumers perceive the store in general and these products in particular. It reviews the overall layout of the store, assortment organization, and shelf

  2. An Evolutionary Approach for Robust Layout Synthesis of MEMS

    DEFF Research Database (Denmark)

    Fan, Zhun; Wang, Jiachuan; Goodman, Erik

    2005-01-01

    assumptions and treated with multiobjective genetic algorithm (MOGA), a special type of evolutionary computing approaches. Case study based on layout synthesis of a comb-driven MEM resonator shows that the approach proposed in this paper can lead to design results that meet the target performance and are less...

  3. Genetic algorithms for construction site layout in project planning

    NARCIS (Netherlands)

    Mawdesley, Michael J.; Al-Jibouri, Saad H.S.; Yang, Hongbo

    2002-01-01

    Construction site layout is concerned with the existence, positioning, and timing of the temporary facilities that are used to carry out a construction project. Typically these problems are very complicated to formulate and difficult to solve. They are, however, very important to virtually any

  4. Proximity search heuristics for wind farm optimal layout

    DEFF Research Database (Denmark)

    Fischetti, Martina; Monaci, Michele

    2016-01-01

    A heuristic framework for turbine layout optimization in a wind farm is proposed that combines ad-hoc heuristics and mixed-integer linear programming. In our framework, large-scale mixed-integer programming models are used to iteratively refine the current best solution according to the recently...

  5. Optimal Plant Layout Design for Process-focused Systems

    OpenAIRE

    Khoshnevisan, M.; Bhattacharya, S.; Smarandache, F.

    2003-01-01

    In this paper we have proposed a semi-heuristic optimization algorithm for designing optimal plant layouts in process-focused manufacturing/service facilities. Being a semi-heuristic search, our algorithm is likely to be more efficient in terms of computer CPU engagement time as it tends to converge on the global optimum faster than the traditional CRAFT algorithm - a pure heuristic.

  6. Integrated quadratic assignment and continuous facility layout problem

    Directory of Open Access Journals (Sweden)

    Mohammad Mohammadi

    2012-10-01

    Full Text Available In this paper, an integrated layout model has been considered to incorporate intra and inter-department layout. In the proposed model, the arrangement of facilities within the departments is obtained through the QAP and from the other side the continuous layout problem is implemented to find the position and orientation of rectangular shape departments on the planar area. First, a modified version of QAP with fewer binary variables is presented. Afterward the integrated model is formulated based on the developed QAP. In order to evaluate material handling cost precisely, the actual position of machines within the departments (instead of center of departments is considered. Moreover, other design factors such as aisle distance, single or multi row intra-department layout and orientation of departments have been considered. The mathematical model is formulated as mixed-integer programming (MIP to minimize total material handling cost. Also due to the complexity of integrated model a heuristic method has been developed to solve large scale problems in a reasonable computational time. Finally, several illustrative numerical examples are selected from the literature to test the model and evaluate the heuristic.

  7. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  8. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  9. Improved Differential Evolution Based on Stochastic Ranking for Robust Layout Synthesis of MEMS Components

    DEFF Research Database (Denmark)

    Fan, Zhun; Liu, Jinchao; Sørensen, Torben

    2009-01-01

    This paper introduces an improved differential evolution (DE) algorithm for robust layout synthesis of microelectromechanical system components subject to inherent geometric uncertainties. A case study of the layout synthesis of a combdriven microresonator shows that the approach proposed...

  10. Library Automation

    OpenAIRE

    Dhakne, B. N.; Giri, V. V; Waghmode, S. S.

    2010-01-01

    New technologies library provides several new materials, media and mode of storing and communicating the information. Library Automation reduces the drudgery of repeated manual efforts in library routine. By use of library automation collection, Storage, Administration, Processing, Preservation and communication etc.

  11. Rearrangement of the layout of the welding equipment of a company in the metal mechanical sector using the Systematic Layout Planning method (SLP

    Directory of Open Access Journals (Sweden)

    Silvio Alexsandro Turati

    2016-06-01

    Full Text Available The correct physical layout is relevant to the operational efficiency of the company. This study proposes rearranging the layout of the welding equipment of a company in the metal mechanical sector, which is located in Araras/SP, aiming to improve the production workflow. The Systematic Layout Planning method (SLP was used, with the field research divided into steps: obtaining detailed information about the process and the product; meetings with stakeholders; determining inter-related activities; analyzing space requirements; developing a new layout. The new layout has space allocated for the purchasing of new machinery, the existing machinery has been redistributed by specialty, and the unloading of raw materials has been transferred to the shed, maximizing the use of overhead cranes and keeping the stock close to the warehouse. In addition, forklift traffic flow has decreased; new movement corridors were demarcated; and painting areas were isolated. In conclusion, the SLP method proved efficient in creating a layout.

  12. Human Factors Evaluations of Two-Dimensional Spacecraft Conceptual Layouts

    Science.gov (United States)

    Kennedy, Kriss J.; Toups, Larry D.; Rudisill, Marianne

    2010-01-01

    Much of the human factors work done in support of the NASA Constellation lunar program has been with low fidelity mockups. These volumetric replicas of the future lunar spacecraft allow researchers to insert test subjects from the engineering and astronaut population and evaluate the vehicle design as the test subjects perform simulations of various operational tasks. However, lunar outpost designs must be evaluated without the use of mockups, creating a need for evaluation tools that can be performed on two-dimension conceptual spacecraft layouts, such as floor plans. A tool based on the Cooper- Harper scale was developed and applied to one lunar scenario, enabling engineers to select between two competing floor plan layouts. Keywords: Constellation, human factors, tools, processes, habitat, outpost, Net Habitable Volume, Cooper-Harper.

  13. Dish layouts analysis method for concentrative solar power plant.

    Science.gov (United States)

    Xu, Jinshan; Gan, Shaocong; Li, Song; Ruan, Zhongyuan; Chen, Shengyong; Wang, Yong; Gui, Changgui; Wan, Bin

    2016-01-01

    Designs leading to maximize the use of sun radiation of a given reflective area without increasing the expense on investment are important to solar power plants construction. We here provide a method that allows one to compute shade area at any given time as well as the total shading effect of a day. By establishing a local coordinate system with the origin at the apex of a parabolic dish and z-axis pointing to the sun, neighboring dishes only with [Formula: see text] would shade onto the dish when in tracking mode. This procedure reduces the required computational resources, simplifies the calculation and allows a quick search for the optimum layout by considering all aspects leading to optimized arrangement: aspect ratio, shifting and rotation. Computer simulations done with information on dish Stirling system as well as DNI data released from NREL, show that regular-spacing is not an optimal layout, shifting and rotating column by certain amount can bring more benefits.

  14. Typography and layout of technical reports - Survey of current practices

    Science.gov (United States)

    Pinelli, T. E.; Cordle, V. M.; Mccullough, R.

    1985-01-01

    As part of a review of the NASA Langley Research Center scientific and technical information program, 50 technical reports from industry, research institutions, and government agencies were systematically examined and analyzed to determine current usage and practice in regard to (1) typography, including composition method, type style, type size, and margin treatment; (2) graphic design, including layout and imposition of material on the page; and (3) physical media, including paper, ink, and binding methods. The results indicate that approximately 50 percent of the reports were typeset, 70 percent used Roman (serif) type, 80 percent used 10- or 11-point type for text, 60 percent used a ragged right-hand margin, slightly more than half used paragraph indentation, 75 percent used a single-column layout, 65 percent had one or more figures or tables placed perpendicular to (not aligned with) the text, and perfect binding was the most frequently used binding method.

  15. Status and new layout of the ATLAS pixel detector

    CERN Document Server

    Netchaeva, P

    2002-01-01

    The ATLAS pixel detector is based on a set of radiation-hard electronics chips able to resist a dose of 500 kGy. The implementation of these chips in the DMILL technology did not give the expected results. Re-design of the radiation-hard chips in Deep SubMicron technology is ongoing, but has implied a one and a half year delay in an already tight schedule. Major layout changes have therefore been necessary to allow installation of the ATLAS pixel detector at LHC start-up. This paper illustrates the status of the ATLAS pixel project, die motivations for the new layout, the way this should be implemented and the prototype fabrication and testing. (4 refs).

  16. Analysis tools for the interplay between genome layout and regulation.

    Science.gov (United States)

    Bouyioukos, Costas; Elati, Mohamed; Képès, François

    2016-06-06

    Genome layout and gene regulation appear to be interdependent. Understanding this interdependence is key to exploring the dynamic nature of chromosome conformation and to engineering functional genomes. Evidence for non-random genome layout, defined as the relative positioning of either co-functional or co-regulated genes, stems from two main approaches. Firstly, the analysis of contiguous genome segments across species, has highlighted the conservation of gene arrangement (synteny) along chromosomal regions. Secondly, the study of long-range interactions along a chromosome has emphasised regularities in the positioning of microbial genes that are co-regulated, co-expressed or evolutionarily correlated. While one-dimensional pattern analysis is a mature field, it is often powerless on biological datasets which tend to be incomplete, and partly incorrect. Moreover, there is a lack of comprehensive, user-friendly tools to systematically analyse, visualise, integrate and exploit regularities along genomes. Here we present the Genome REgulatory and Architecture Tools SCAN (GREAT:SCAN) software for the systematic study of the interplay between genome layout and gene expression regulation. SCAN is a collection of related and interconnected applications currently able to perform systematic analyses of genome regularities as well as to improve transcription factor binding sites (TFBS) and gene regulatory network predictions based on gene positional information. We demonstrate the capabilities of these tools by studying on one hand the regular patterns of genome layout in the major regulons of the bacterium Escherichia coli. On the other hand, we demonstrate the capabilities to improve TFBS prediction in microbes. Finally, we highlight, by visualisation of multivariate techniques, the interplay between position and sequence information for effective transcription regulation.

  17. Optimal Bangla Keyboard Layout using Data Mining Technique

    OpenAIRE

    Kamruzzaman, S. M.; Alam, Md. Hijbul; Masum, Abdul Kadar Muhammad; Hassan, Md Mahadi

    2010-01-01

    This paper presents an optimal Bangla Keyboard Layout, which distributes the load equally on both hands so that maximizing the ease and minimizing the effort. Bangla alphabet has a large number of letters, for this it is difficult to type faster using Bangla keyboard. Our proposed keyboard will maximize the speed of operator as they can type with both hands parallel. Here we use the association rule of data mining to distribute the Bangla characters in the keyboard. First, we analyze the freq...

  18. Productivity Improvement- Application of TPM and layout design

    OpenAIRE

    Hossein, Md. Mohsarraf

    2011-01-01

    In this thesis, with a discussion on concepts and principles of total productive maintenance(TPM), overall equipment effectiveness (OEE), efficient layout design, maintenance activitiesand scope of development, a detailed report is provided on real scenario of a drilling pipes andaccessory manufacturing factory Driconeq Production AB, Sweden. Total ProductiveMaintenance (TPM) is a maintenance program which involves a newly defined concept formaintaining plants and equipment. That is why, TPM ...

  19. Doublet vs. FODO structure: beam dynamics and layout

    CERN Document Server

    Eshraqi, M; CERN. Geneva. BE Department

    2010-01-01

    A FoDo (singlet) structure is designed for the CERN Superconducting Proton LINAC. This architecture is compared to the baseline (doublet) architecture of SPL on the basis of its beam dynamics performance and the required investment. The sensitivity of both layouts to quadrupole gradient errors and misalignment is checked and a correction scheme for beam steering is proposed. Finally a single quad beam dilution scheme is studied and designed for the pilot beam dump.

  20. Multi-objective Mixed Integer Programming approach for facility layout design by considering closeness ratings, material handling, and re-layout cost

    Science.gov (United States)

    Purnomo, Muhammad Ridwan Andi; Satrio Wiwoho, Yoga

    2016-01-01

    Facility layout becomes one of production system factor that should be managed well, as it is designated for the location of production. In managing the layout, designing the layout by considering the optimal layout condition that supports the work condition is essential. One of the method for facility layout optimization is Mixed Integer Programming (MIP). In this study, the MIP is solved using Lingo 9.0 software and considering quantitative and qualitative objectives to be achieved simultaneously: minimizing material handling cost, maximizing closeness rating, and minimizing re-layout cost. The research took place in Rekayasa Wangdi as a make to order company, focusing on the making of concrete brick dough stirring machine with 10 departments involved. The result shows an improvement in the new layout for 333,72 points of objective value compared with the initial layout. As the conclusion, the proposed MIP is proven to be used to model facility layout problem under multi objective consideration for a more realistic look.

  1. CiSE: a circular spring embedder layout algorithm.

    Science.gov (United States)

    Dogrusoz, Ugur; Belviranli, Mehmet E; Dilek, Alptug

    2013-06-01

    We present a new algorithm for automatic layout of clustered graphs using a circular style. The algorithm tries to determine optimal location and orientation of individual clusters intrinsically within a modified spring embedder. Heuristics such as reversal of the order of nodes in a cluster and swap of neighboring node pairs in the same cluster are employed intermittently to further relax the spring embedder system, resulting in reduced inter-cluster edge crossings. Unlike other algorithms generating circular drawings, our algorithm does not require the quotient graph to be acyclic, nor does it sacrifice the edge crossing number of individual clusters to improve respective positioning of the clusters. Moreover, it reduces the total area required by a cluster by using the space inside the associated circle. Experimental results show that the execution time and quality of the produced drawings with respect to commonly accepted layout criteria are quite satisfactory, surpassing previous algorithms. The algorithm has also been successfully implemented and made publicly available as part of a compound and clustered graph editing and layout tool named CHISIO.

  2. Camera Layout Design for the Upper Stage Thrust Cone

    Science.gov (United States)

    Wooten, Tevin; Fowler, Bart

    2010-01-01

    Engineers in the Integrated Design and Analysis Division (EV30) use a variety of different tools to aid in the design and analysis of the Ares I vehicle. One primary tool in use is Pro-Engineer. Pro-Engineer is a computer-aided design (CAD) software that allows designers to create computer generated structural models of vehicle structures. For the Upper State thrust cone, Pro-Engineer was used to assist in the design of a layout for two camera housings. These cameras observe the separation between the first and second stage of the Ares I vehicle. For the Ares I-X, one standard speed camera was used. The Ares I design calls for two separate housings, three cameras, and a lighting system. With previous design concepts and verification strategies in mind, a new layout for the two camera design concept was developed with members of the EV32 team. With the new design, Pro-Engineer was used to draw the layout to observe how the two camera housings fit with the thrust cone assembly. Future analysis of the camera housing design will verify the stability and clearance of the camera with other hardware present on the thrust cone.

  3. Lower-Temperature Subsurface Layout and Ventilation Concepts

    Energy Technology Data Exchange (ETDEWEB)

    Christine L. Linden; Edward G. Thomas

    2001-06-20

    This analysis combines work scope identified as subsurface facility (SSF) low temperature (LT) Facilities System and SSF LT Ventilation System in the Technical Work Plan for Subsurface Design Section FY 01 Work Activities (CRWMS M&O 2001b, pp. 6 and 7, and pp. 13 and 14). In accordance with this technical work plan (TWP), this analysis is performed using AP-3.10Q, Analyses and Models. It also incorporates the procedure AP-SI.1Q, Software Management. The purpose of this analysis is to develop an overall subsurface layout system and the overall ventilation system concepts that address a lower-temperature operating mode for the Monitored Geologic Repository (MGR). The objective of this analysis is to provide a technical design product that supports the lower-temperature operating mode concept for the revision of the system description documents and to provide a basis for the system description document design descriptions. The overall subsurface layout analysis develops and describes the overall subsurface layout, including performance confirmation facilities (also referred to as Test and Evaluation Facilities) for the Site Recommendation design. This analysis also incorporates current program directives for thermal management.

  4. Ant colony optimization for solving university facility layout problem

    Science.gov (United States)

    Mohd Jani, Nurul Hafiza; Mohd Radzi, Nor Haizan; Ngadiman, Mohd Salihin

    2013-04-01

    Quadratic Assignment Problems (QAP) is classified as the NP hard problem. It has been used to model a lot of problem in several areas such as operational research, combinatorial data analysis and also parallel and distributed computing, optimization problem such as graph portioning and Travel Salesman Problem (TSP). In the literature, researcher use exact algorithm, heuristics algorithm and metaheuristic approaches to solve QAP problem. QAP is largely applied in facility layout problem (FLP). In this paper we used QAP to model university facility layout problem. There are 8 facilities that need to be assigned to 8 locations. Hence we have modeled a QAP problem with n ≤ 10 and developed an Ant Colony Optimization (ACO) algorithm to solve the university facility layout problem. The objective is to assign n facilities to n locations such that the minimum product of flows and distances is obtained. Flow is the movement from one to another facility, whereas distance is the distance between one locations of a facility to other facilities locations. The objective of the QAP is to obtain minimum total walking (flow) of lecturers from one destination to another (distance).

  5. Diamond MOSFET: An innovative layout to improve performance of ICs

    Science.gov (United States)

    Gimenez, Salvador Pinillos

    2010-12-01

    A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the "corner effect concept" to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies.

  6. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This paper proposes a novel Direct Bonded Copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect......, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate on the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical...

  7. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This letter proposes a novel direct bonded copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect......, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical...

  8. Analytical Tools for Functional Assessment of Architectural Layouts

    Science.gov (United States)

    Bąkowski, Jarosław

    2017-10-01

    Functional layout of the building, understood as a layout or set of the facility rooms (or groups of rooms) with a system of internal communication, creates an environment and a place of mutual relations between the occupants of the object. Achieving optimal (from the occupants’ point of view) spatial arrangement is possible through activities that often go beyond the stage of architectural design. Adopted in the architectural design, most often during trial and error process or on the basis of previous experience (evidence-based design), functional layout is subject to continuous evaluation and dynamic changing since the beginning of its use. Such verification of the occupancy phase allows to plan future, possible transformations, as well as to develop model solutions for use in other settings. In broader terms, the research hypothesis is to examine whether and how the collected datasets concerning the facility and its utilization can be used to develop methods for assessing functional layout of buildings. In other words, if it is possible to develop an objective method of assessing functional layouts basing on a set of buildings’ parameters: technical, technological and functional ones and whether the method allows developing a set of tools enhancing the design methodology of complex functional objects. By linking the design with the construction phase it is possible to build parametric models of functional layouts, especially in the context of sustainable design or lean design in every aspect: ecological (by reducing the property’s impact on environment), economic (by optimizing its cost) and social (through the implementation of high-performance work environment). Parameterization of size and functional connections of the facility become part of the analyses, as well as the element of model solutions. The “lean” approach means the process of analysis of the existing scheme and consequently – finding weak points as well as means for eliminating these

  9. Marketing automation

    National Research Council Canada - National Science Library

    Raluca Dania Todor

    2016-01-01

      The automation of the marketing process seems to be nowadays, the only solution to face the major changes brought by the fast evolution of technology and the continuous increase in supply and demand...

  10. Research of Digital Interface Layout Design based on Eye-tracking

    Directory of Open Access Journals (Sweden)

    Shao Jiang

    2015-01-01

    Full Text Available The aim of this paper is to improve the low service efficiency and unsmooth human-computer interaction caused by currently irrational layouts of digital interfaces for complex systems. Also, three common layout structures for digital interfaces are to be presented and five layout types appropriate for multilevel digital interfaces are to be summarized. Based on the eye tracking technology, an assessment was conducted in advantages and disadvantages of different layout types through subjects’ search efficiency. Based on data and results, this study constructed a matching model which is appropriate for multilevel digital interface layout and verified the fact that the task element is a significant and important aspect of layout design. A scientific experimental model of research on digital interfaces for complex systems is provided. Both data and conclusions of the eye movement experiment provide a reference for layout designs of interfaces for complex systems with different task characteristics.

  11. The design, simulation, and fabrication of a BiCMOS VLSI digitally programmable GIC filter

    OpenAIRE

    Milne, Paul R.

    2001-01-01

    This thesis used a previously-designed programmable GIC filter as a basis in which to incorporate a BiCMOS operational amplifier. An NPN bipolar transistor layout was designed and incorporated into an opamp layout, which was a modified version of a CMOS-only design. The BiCMOS opamp was simulated using Silvaco SmartSpice and showed considerable improvement over its CMOS equivalent. Additional improvements were made to the GIC filter to include a passgate with reduced resistance, and a correct...

  12. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  13. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  14. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  15. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  16. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  17. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  18. Application and Integration of Quantum-Effect Devices for Cellular VLSI

    Science.gov (United States)

    Levy, Harold Joseph

    1995-01-01

    Cellular VLSI is that subclass of electronic systems for which small perturbations in a repeated cell design can dramatically influence the cost and performance of the entire system. This thesis presents examples of how the room-temperature quantum effects of tunneling and resonance may be used to condense the functionality of many conventional VLSI devices into a smaller and more efficient subunit, thus yielding tremendous benefits for the system as a whole. In particular, two and three-terminal applications of a complimentary pair of quantum-effect devices, the resonant-tunneling diode and the tunneling-switch diode, are presented. The first example is an image-segmentation network for machine vision, implemented by using resonant-tunneling diodes in one and two-dimensional networks to extract boundaries between regions of constant spatial texture. In this case a single quantum-effect device may replace up to thirty -three CMOS transistors per pixel. The second example is an artificial neural-network processor based on multistate resistors for synaptic conductances. These programmable resistors were produced by combining a vertically -integrated stack of resonant-tunneling diodes with a resistive load and a single MOSFET driven in its ohmic region. This macrostructure has the potential to provide synaptic changes on the picosecond time scale at length scales well below one micron. The third example is a current-mode transistorless memory array based on a two-dimensional network of cells containing only a single tunneling-switch diode and a resistive load. The resulting system has the potential for reaching more than an order-of-magnitude more cell density than state-of-the-art DRAM arrays, while operating at state -of-the-art SRAM speeds and reasonable power consumption.

  19. Detecting Family Resemblance: Automated Genre Classification

    Directory of Open Access Journals (Sweden)

    Yunhyong Kim

    2007-03-01

    Full Text Available This paper presents results in automated genre classification of digital documents in PDF format. It describes genre classification as an important ingredient in contextualising scientific data and in retrieving targetted material for improving research. The current paper compares the role of visual layout, stylistic features, and language model features in clustering documents and presents results in retrieving five selected genres (Scientific Article, Thesis, Periodicals, Business Report, and Form from a pool of materials populated with documents of the nineteen most popular genres found in our experimental data set.

  20. [Land layout for lake tourism based on ecological restraint].

    Science.gov (United States)

    Wang, Jian-Ying; Li, Jiang-Feng; Zou, Li-Lin; Liu, Shi-Bin

    2012-10-01

    To avoid the decrease and deterioration of lake wetlands and the other ecological issues such as lake water pollution that were caused by the unreasonable exploration of lake tourism, a land layout for the tourism development of Liangzi Lake with the priority of ecological security pattern was proposed, based on the minimal cumulative resistance model and by using GIS technology. The study area was divided into four ecological function zones, i. e., core protection zone, ecological buffer zone, ecotone zone, and human activity zone. The core protection zone was the landscape region of ecological source. In the protection zone, new tourism land was forbidden to be increased, and some of the existing fundamental tourism facilities should be removed while some of them should be upgraded. The ecological buffer zone was the landscape region with resistance value ranged from 0 to 4562. In the buffer zone, expansion of tourism land should be forbidden, the existing tourism land should be downsized, and human activities should be isolated from ecological source by converting the human environment to the natural environment as far as possible. The ecotone zone was the landscape region with resistance value ranged from 4562 to 30797. In this zone, the existing tourism land was distributed in patches, tourism land could be expanded properly, and the lake forestry ecological tourism should be developed widely. The human activity zone was the landscape region with resistance value ranged from 30797 to 97334, which would be the key area for the land layout of lake tourism. It was suggested that the land layout for tourism with the priority of landscape ecological security pattern would be the best choice for the lake sustainable development.

  1. Strategies in preflight for an optimal Yurchenko layout vault.

    Science.gov (United States)

    Koh, Michael; Jennings, Les

    2007-01-01

    An optimal Yurchenko layout vault of an elite female gymnast was identified by Koh et al. [2003. A predicted optimal performance of the Yurchenko layout vault in women's artistic gymnastics. Journal of Applied Biomechanics 19, 187-204] to require a combination of an increased body angle at horse contact and increased angular momentum for postflight than was recorded experimentally. However, the individual effect of each of these variables to producing the optimal vault is not known. The purpose of the study was to determine an appropriate strategy to teaching the optimal Yurchenko layout vault. Separate optimisations were carried out to investigate how each of these variables would change in order to produce the optimal vault identified by Koh et al. (2003). A combined optimal parameter selection and optimal control approach was used. The results suggest that when the body angle of attack at horse impact was kept low, pre-flight angular momentum had to be increased, with further gains during horse impact, to produce an optimal vault. This strategy of increasing solely the level of angular momentum needed for optimum postflight may not be attainable realistically. On the other hand, employing a larger body angle of attack required an increase in angular momentum during impact but which was attainable. Both optimisations show that increasing the vertical CM horse takeoff velocity is essential for postflight height and distance. The strategy to enhance performance should thus focus on maintaining an appropriate CM pre-flight velocity, a high level of angular momentum during pre-flight and to contact the horse with a large body angle of attack.

  2. Effects of Optimizing the Scan-Path on Scanning Keyboards with QWERTY-Layout for English Text.

    Science.gov (United States)

    Sandnes, Frode Eika; Medola, Fausto Orsi

    2017-01-01

    Scanning keyboards can be essential tools for individuals with reduced motor function. However, most research addresses layout optimization. Learning new layouts is time-consuming. This study explores the familiar QWERTY layout with alternative scanning paths intended for English text. The results show that carefully designed scan-paths can help QWERTY nearly match optimized layouts in performance.

  3. Layout for Assessing Dynamic Posture: Development, Validation, and Reproducibility.

    Science.gov (United States)

    Noll, Matias; Candotti, Cláudia Tarragô; da Rosa, Bruna Nichele; Sedrez, Juliana Adami; Vieira, Adriane; Loss, Jefferson Fagundes

    2016-01-01

    To determine the psychometric properties of the layout for assessing dynamic posture (LADy). The study was divided into 2 phases: (1) development of the instrument and (2) determination of validity and reproducibility. The LADy was designed to evaluate the position adopted in 9 dynamic postures. The results confirmed the validity and reproducibility of the instrument. From a total of 51 criteria assessing 9 postures, 1 was rejected. The reproducibility for each of the criteria was classified as moderate to excellent. The LADy constitutes a valid and reproducible instrument for the evaluation of dynamic postures in children 11 to 17 years old. It is low cost and applicable in the school environment.

  4. Influence of offshore wind farms layout on electrical resonances

    DEFF Research Database (Denmark)

    Holdyk, Andrzej; Holbøll, Joachim; Koldby, Erik

    2014-01-01

    , harmonics and interaction between components and the power system and especially on the interaction and resonance between the transformer,-cables and the circuit breaker. These phenomena are also important in offshore wind farms, where the specific and often complex structure of the collection grid can......, winding resistances and winding capacitances. Considering the frequency range of the present investigations, up to about 1 MHz, a lumped representation of the transformer characteristics was deemed sufficient. Breakers and capacitors are modelled as ideal components. The chosen wind farm layout includes...

  5. A new dynamical layout algorithm for complex biochemical reaction networks.

    Science.gov (United States)

    Wegner, Katja; Kummer, Ursula

    2005-08-26

    To study complex biochemical reaction networks in living cells researchers more and more rely on databases and computational methods. In order to facilitate computational approaches, visualisation techniques are highly important. Biochemical reaction networks, e.g. metabolic pathways are often depicted as graphs and these graphs should be drawn dynamically to provide flexibility in the context of different data. Conventional layout algorithms are not sufficient for every kind of pathway in biochemical research. This is mainly due to certain conventions to which biochemists/biologists are used to and which are not in accordance to conventional layout algorithms. A number of approaches has been developed to improve this situation. Some of these are used in the context of biochemical databases and make more or less use of the information in these databases to aid the layout process. However, visualisation becomes also more and more important in modelling and simulation tools which mostly do not offer additional connections to databases. Therefore, layout algorithms used in these tools have to work independently of any databases. In addition, all of the existing algorithms face some limitations with respect to the number of edge crossings when it comes to larger biochemical systems due to the interconnectivity of these. Last but not least, in some cases, biochemical conventions are not met properly. Out of these reasons we have developed a new algorithm which tackles these problems by reducing the number of edge crossings in complex systems, taking further biological conventions into account to identify and visualise cycles. Furthermore the algorithm is independent from database information in order to be easily adopted in any application. It can also be tested as part of the SimWiz package (free to download for academic users at 1). The new algorithm reduces the complexity of pathways, as well as edge crossings and edge length in the resulting graphical representation

  6. High-Quality Ultra-Compact Grid Layout of Grouped Networks.

    Science.gov (United States)

    Yoghourdjian, Vahan; Dwyer, Tim; Gange, Graeme; Kieffer, Steve; Klein, Karsten; Marriott, Kim

    2016-01-01

    Prior research into network layout has focused on fast heuristic techniques for layout of large networks, or complex multi-stage pipelines for higher quality layout of small graphs. Improvements to these pipeline techniques, especially for orthogonal-style layout, are difficult and practical results have been slight in recent years. Yet, as discussed in this paper, there remain significant issues in the quality of the layouts produced by these techniques, even for quite small networks. This is especially true when layout with additional grouping constraints is required. The first contribution of this paper is to investigate an ultra-compact, grid-like network layout aesthetic that is motivated by the grid arrangements that are used almost universally by designers in typographical layout. Since the time when these heuristic and pipeline-based graph-layout methods were conceived, generic technologies (MIP, CP and SAT) for solving combinatorial and mixed-integer optimization problems have improved massively. The second contribution of this paper is to reassess whether these techniques can be used for high-quality layout of small graphs. While they are fast enough for graphs of up to 50 nodes we found these methods do not scale up. Our third contribution is a large-neighborhood search meta-heuristic approach that is scalable to larger networks.

  7. VLSI Research

    Science.gov (United States)

    1983-10-31

    Caesar and Mextra and other old programs, as well as several previously-unreleased pro- grams, such as Lyra. Crystal. Peg, and Tpack . The 1983...release was sent to eight beta test sites in January, and began general distribution on April 1. EL1. Tpack : A System for Combining Graphics and Procedures

  8. VLSI Research

    Science.gov (United States)

    1984-04-01

    23,1984 / CONTINENTAL BALLROOMS 6-9 / 9:00 A.M. *T-ś! J SESSION XII: MICROPROCESSORS ANO MICROCONTROLLERS THAM 12.1: A 32b NMOS Microprocessor...roisideration, AlC is insensitive to the interface-wrapt..2 charge. The difference between AVr and Al£, therefore, will be the con- tribution from the...reduction of AVr . Since the degree of impact ionization increases with the substrate bias, the end result is the observed decrease in AVj- with

  9. Analog integrated circuit design automation placement, routing and parasitic extraction techniques

    CERN Document Server

    Martins, Ricardo; Horta, Nuno

    2017-01-01

    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures...

  10. The importance of layout and configuration data for flexibility during commissionning and operation of the LHC machine protection systems

    CERN Document Server

    Mariethoz, Julien; Le Roux, Pascal; Bernard, Frederic; Harrison, Robert; Zerlauth, Markus

    2006-01-01

    Due to the large stored energies in both magnets and particle beams, the Large Hadron Collider (LHC) requires a large inventory of machine protection systems, as e.g. powering interlock systems, based on a series of distributed industrial controllers for the protection of the more than 10'000 normal and superconducting magnets. Such systems are required to be at the same time fast, reliable and secure but also flexible and configurable to allow for automated commissioning, remote monitoring and optimization during later operation. Based on the generic hardware architecture of the LHC machine protection systems presented at EPAC 2002 [2] and ICALEPS 2003, the use of configuration data for protection systems in view of the required reliability and safety is discussed. To achieve the very high level of reliability, it is required to use a coherent description of the layout of the accelerator components and of the associated machine protection architecture and their logical interconnections. Mechanisms to guarant...

  11. Automated Wormscan

    Science.gov (United States)

    Puckering, Timothy; Thompson, Jake; Sathyamurthy, Sushruth; Sukumar, Sinduja; Shapira, Tirosh; Ebert, Paul

    2017-01-01

    There has been a recent surge of interest in computer-aided rapid data acquisition to increase the potential throughput and reduce the labour costs of large scale Caenorhabditis elegans studies. We present Automated WormScan, a low-cost, high-throughput automated system using commercial photo scanners, which is extremely easy to implement and use, capable of scoring tens of thousands of organisms per hour with minimal operator input, and is scalable. The method does not rely on software training for image recognition, but uses the generation of difference images from sequential scans to identify moving objects. This approach results in robust identification of worms with little computational demand. We demonstrate the utility of the system by conducting toxicity, growth and fecundity assays, which demonstrate the consistency of our automated system, the quality of the data relative to manual scoring methods and congruity with previously published results. PMID:28413617

  12. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

    Science.gov (United States)

    Xu, Peng; Pan, Zhongliang

    2017-09-01

    With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system. Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

  13. The Layout of Power and Space in Jingdezhen Imperial Factory

    Directory of Open Access Journals (Sweden)

    Zhan Jia

    2014-12-01

    Full Text Available This paper, by referring to the archaeological reports and local gazetteers and comparing images of porcelain wares, makes a comprehensive and in-depth analysis of the layout of power and space in Jingdezhen Imperial Factory according to its geography, geomancy, security management, space regulation, architectural features, production characteristics and production layout. It contends that the Imperial Factory which integrates porcelain making factory with local government is the embodiment of absolute monarchy in ceramic culture. The factory is located on Zhushan mountain, the center of Jingdezhen’s industry, business and transportation. Being at the center, it gives off an air of prestige and majesty, overlooking dominantly the surrounding private kilns. It has also turned the political system into power operation, setting up not only workshops but also administrative offices. By taking advantage of the best resources, it has produced porcelain for imperial family and court. Its specialized production has solved the contradiction between complicated technology and numerous procedures of production. The shape, color and pattern of the porcelain wares are strictly stipulated and the best of the best wares are demanded. Hence the porcelain production is featured with longest firing, largest scale, superb craftsmanship, and best kinds of wares. All of these reveal the process and rule power and space are intersected and different cultures overlapped.

  14. Page layout analysis and classification for complex scanned documents

    Science.gov (United States)

    Erkilinc, M. Sezer; Jaber, Mustafa; Saber, Eli; Bauer, Peter; Depalov, Dejan

    2011-09-01

    A framework for region/zone classification in color and gray-scale scanned documents is proposed in this paper. The algorithm includes modules for extracting text, photo, and strong edge/line regions. Firstly, a text detection module which is based on wavelet analysis and Run Length Encoding (RLE) technique is employed. Local and global energy maps in high frequency bands of the wavelet domain are generated and used as initial text maps. Further analysis using RLE yields a final text map. The second module is developed to detect image/photo and pictorial regions in the input document. A block-based classifier using basis vector projections is employed to identify photo candidate regions. Then, a final photo map is obtained by applying probabilistic model based on Markov random field (MRF) based maximum a posteriori (MAP) optimization with iterated conditional mode (ICM). The final module detects lines and strong edges using Hough transform and edge-linkages analysis, respectively. The text, photo, and strong edge/line maps are combined to generate a page layout classification of the scanned target document. Experimental results and objective evaluation show that the proposed technique has a very effective performance on variety of simple and complex scanned document types obtained from MediaTeam Oulu document database. The proposed page layout classifier can be used in systems for efficient document storage, content based document retrieval, optical character recognition, mobile phone imagery, and augmented reality.

  15. Neonatal Intensive Care Unit Layout and Nurses' Work.

    Science.gov (United States)

    Doede, Megan; Trinkoff, Alison M; Gurses, Ayse P

    2017-01-01

    Neonatal intensive care units (NICUs) remain one of the few areas in hospitals that still use an open bay (OPBY) design for patient stays greater than 24 hr, housing multiple infants, staff, and families in one large room. This creates high noise levels, contributes to the spread of infection, and affords families little privacy. These problems have given rise to the single-family room NICU. This represents a significant change in the care environment for nurses. This literature review answers the question: When compared to OPBY layout, how does a single family room layout impact neonatal nurses' work? Thirteen studies published between 2006 and 2015 were located. Many studies reported both positive and negative effects on nurses' work and were therefore sorted by their cited advantages and disadvantages. Advantages included improved quality of the physical environment; improved quality of patient care; improved parent interaction; and improvements in nurse job satisfaction, stress, and burnout. Disadvantages included decreased interaction among the NICU patient care team, increased nurse workload, decreased visibility on the unit, and difficult interactions with family. This review suggests that single-family room NICUs introduce a complex situation in which trade-offs occur for nurses, most prominently the trade-off between visibility and privacy. Additionally, the literature is clear on what elements of nurses' work are impacted, but how the built environment influences these elements, and how these elements interact during nurses' work, is not as well understood. The current level of research and directions for future research are also discussed.

  16. LAYOUT AND SIZING OF ESF ALCOVES AND REFUGE CHAMBERS

    Energy Technology Data Exchange (ETDEWEB)

    John Beesley and Romeo S. Jurani

    1995-08-25

    The purpose of this analysis is to establish size requirements and approximate locations of Exploratory Studies Facility (ESF) test and operations alcoves, including refuge chambers during construction of the Topopah Spring (TS) loop. Preliminary conceptual layouts for non-deferred test alcoves will be developed to examine construction feasibility based on current test plans and available equipment. The final location and configuration layout for alcoves will be developed when in-situ rock conditions can be visually determined. This will be after the TBM has excavated beyond the alcove location and the rock has been exposed. The analysis will examine the need for construction of walkways and electrical alcoves in the ramps and main drift. Niches that may be required to accommodate conveyor booster drives and alignments are not included in this analysis. The analysis will develop design criteria for refuge chambers to meet MSHA requirements and will examine the strategic location of refuge chambers based on their potential use in various ESF fire scenarios. This document supersedes DI:BABE00000-01717-0200-00003 Rev 01, ''TS North Ramp Alcove and Stubout Location Analysis'' in its entirety (Reference 5-6).

  17. Layout of a cross-shaped inner tracker

    CERN Document Server

    Steinkamp, O

    2001-01-01

    The LHCb Technical Proposal described a tracking system in which the Inner Tracker covered a rectangular surface of 60\\,cm$\\times$40\\,cm around the beampipe. In the meantime, simulation studies have shown that the borderline between Inner and Outer Trackers has to be shifted further away from the beampipe in order to obtain acceptably low occupancies in the innermost regions of the Outer Tracker. In an effort to keep the surface covered by the relatively expensive Inner Tracker technology as small as possible, a new layout of the tracking stations has been proposed, in which the Inner Tracker covers a cross-shaped area around the beampipe. The layout described in LHCb note 2000-107, in which each Inner Tracker station consisted of two "L"-shaped detector boxes, would not be well suited to cover such a cross-shaped area. A more elegant solution is proposed here, in which each Inner Tracker station consists of four rectangular detector boxes, one above, one below and one on each side of the beampipe.

  18. An Optimization Method for the Remanufacturing Dynamic Facility Layout Problem with Uncertainties

    Directory of Open Access Journals (Sweden)

    Lingling Li

    2015-01-01

    Full Text Available Remanufacturing is a practice of growing importance due to increasing environmental awareness and regulations. Facility layout design, as the cornerstone of effective facility planning, is concerned about resource localization for a well-coordinated workflow that leads to lower material handling costs and reduced lead times. However, due to stochastic returns of used products/components and their uncontrollable quality conditions, the remanufacturing process exhibits a high level of uncertainty challenging the facility layout design for remanufacturing. This paper undertakes this problem and presents an optimization method for remanufacturing dynamic facility layout with variable process capacities, unequal processing cells, and intercell material handling. A dynamic multirow layout model is presented for layout optimization and a modified simulated annealing heuristic is proposed toward the determination of optimal layout schemes. The approach is demonstrated through a machine tool remanufacturing system.

  19. Aircraft Cockpit Ergonomic Layout Evaluation Based on Uncertain Linguistic Multiattribute Decision Making

    Directory of Open Access Journals (Sweden)

    Junxuan Chen

    2014-03-01

    Full Text Available In the view of the current cockpit information interaction, facilities and other characteristics are increasingly multifarious; the early layout evaluation methods based on single or partial components, often cause comprehensive evaluation unilateral, leading to the problems of long development period and low efficiency. Considering the fuzziness of ergonomic evaluation and diversity of evaluation information attributes, we refine and build an evaluation system based on the characteristics of the current cockpit man-machine layout and introduce the different types of uncertain linguistic multiple attribute combination decision making (DTULDM method in the cockpit layout evaluation process. Meanwhile, we also establish an aircraft cockpit ergonomic layout evaluation model. Finally, an experiment about cockpit layout evaluation is given, and the result demonstrates that the proposed method about cockpit ergonomic layout evaluation is feasible and effective.

  20. Coplanar Electrode Layout Optimized for Increased Sensitivity for Electrical Impedance Spectroscopy

    OpenAIRE

    Casper Hyttel Clausen; Gustav Erik Skands; Christian Vinther Bertelsen; Winnie Edith Svendsen

    2014-01-01

    This work describes an improvement in the layout of coplanar electrodes for electrical impedance spectroscopy. We have developed, fabricated, and tested an improved electrode layout, which improves the sensitivity of an impedance flow cytometry chip. The improved chip was experimentally tested and compared to a chip with a conventional electrode layout. The improved chip was able to discriminate 0.5 mu m beads from 1 mu m as opposed to the conventional chip. Furthermore, finite element modeli...

  1. Library Automation.

    Science.gov (United States)

    Husby, Ole

    1990-01-01

    The challenges and potential benefits of automating university libraries are reviewed, with special attention given to cooperative systems. Aspects discussed include database size, the role of the university computer center, storage modes, multi-institutional systems, resource sharing, cooperative system management, networking, and intelligent…

  2. Evolutionary approach for spatial architecture layout design enhanced by an agent-based topology finding system

    Directory of Open Access Journals (Sweden)

    Zifeng Guo

    2017-03-01

    Full Text Available This paper presents a method for the automatic generation of a spatial architectural layout from a user-specified architectural program. The proposed approach binds a multi-agent topology finding system and an evolutionary optimization process. The former generates topology satisfied layouts for further optimization, while the latter focuses on refining the layouts to achieve predefined architectural criteria. The topology finding process narrows the search space and increases the performance in subsequent optimization. Results imply that the spatial layout modeling and the multi-floor topology are handled.

  3. Integration of value stream map and strategic layout planning into DMAIC approach to improve carpeting process

    National Research Council Canada - National Science Library

    Ayman Nagi; Safwan Altarazi

    2017-01-01

    .... Utilized tools included: Pareto analysis, control charts, Ishikawa chart, 5-whys, failure mode and effect analysis, process capability ratio, value stream mapping, and strategic layout planning. Findings...

  4. Impact of data layouts on the efficiency of GPU-accelerated IDW interpolation.

    Science.gov (United States)

    Mei, Gang; Tian, Hong

    2016-01-01

    This paper focuses on evaluating the impact of different data layouts on the computational efficiency of GPU-accelerated Inverse Distance Weighting (IDW) interpolation algorithm. First we redesign and improve our previous GPU implementation that was performed by exploiting the feature of CUDA dynamic parallelism (CDP). Then we implement three versions of GPU implementations, i.e., the naive version, the tiled version, and the improved CDP version, based upon five data layouts, including the Structure of Arrays (SoA), the Array of Structures (AoS), the Array of aligned Structures (AoaS), the Structure of Arrays of aligned Structures (SoAoS), and the Hybrid layout. We also carry out several groups of experimental tests to evaluate the impact. Experimental results show that: the layouts AoS and AoaS achieve better performance than the layout SoA for both the naive version and tiled version, while the layout SoA is the best choice for the improved CDP version. We also observe that: for the two combined data layouts (the SoAoS and the Hybrid), there are no notable performance gains when compared to other three basic layouts. We recommend that: in practical applications, the layout AoaS is the best choice since the tiled version is the fastest one among three versions. The source code of all implementations are publicly available.

  5. A fast and efficient method for device level layout analysis

    Science.gov (United States)

    Dong, YaoQi; Zou, Elaine; Pang, Jenny; Huang, Lucas; Yang, Legender; Zhang, Chunlei; Du, Chunshan; Hu, Xinyi; Wan, Qijian

    2017-03-01

    There is an increasing demand for device level layout analysis, especially as technology advances. The analysis is to study standard cells by extracting and classifying critical dimension parameters. There are couples of parameters to extract, like channel width, length, gate to active distance, and active to adjacent active distance, etc. for 14nm technology, there are some other parameters that are cared about. On the one hand, these parameters are very important for studying standard cell structures and spice model development with the goal of improving standard cell manufacturing yield and optimizing circuit performance; on the other hand, a full chip device statistics analysis can provide useful information to diagnose the yield issue. Device analysis is essential for standard cell customization and enhancements and manufacturability failure diagnosis. Traditional parasitic parameters extraction tool like Calibre xRC is powerful but it is not sufficient for this device level layout analysis application as engineers would like to review, classify and filter out the data more easily. This paper presents a fast and efficient method based on Calibre equation-based DRC (eqDRC). Equation-based DRC extends the traditional DRC technology to provide a flexible programmable modeling engine which allows the end user to define grouped multi-dimensional feature measurements using flexible mathematical expressions. This paper demonstrates how such an engine and its programming language can be used to implement critical device parameter extraction. The device parameters are extracted and stored in a DFM database which can be processed by Calibre YieldServer. YieldServer is data processing software that lets engineers query, manipulate, modify, and create data in a DFM database. These parameters, known as properties in eqDRC language, can be annotated back to the layout for easily review. Calibre DesignRev can create a HTML formatted report of the results displayed in Calibre

  6. Methodology for bus layout for topological quantum error correcting codes

    Energy Technology Data Exchange (ETDEWEB)

    Wosnitzka, Martin; Pedrocchi, Fabio L.; DiVincenzo, David P. [RWTH Aachen University, JARA Institute for Quantum Information, Aachen (Germany)

    2016-12-15

    Most quantum computing architectures can be realized as two-dimensional lattices of qubits that interact with each other. We take transmon qubits and transmission line resonators as promising candidates for qubits and couplers; we use them as basic building elements of a quantum code. We then propose a simple framework to determine the optimal experimental layout to realize quantum codes. We show that this engineering optimization problem can be reduced to the solution of standard binary linear programs. While solving such programs is a NP-hard problem, we propose a way to find scalable optimal architectures that require solving the linear program for a restricted number of qubits and couplers. We apply our methods to two celebrated quantum codes, namely the surface code and the Fibonacci code. (orig.)

  7. Overview of the Westinghouse Small Modular Reactor building layout

    Energy Technology Data Exchange (ETDEWEB)

    Cronje, J. M. [Westinghouse Electric Company LLC, Centurion (South Africa); Van Wyk, J. J.; Memmott, M. J. [Westinghouse Electric Company LLC, Cranberry Township, PA (United States)

    2012-07-01

    The Westinghouse Small Modular Reactor (SMR) is an 800 MWt (>225 MWe) integral pressurized water reactor (iPWR), in which all of the components typically associated with the nuclear steam supply system (NSSS) of a nuclear power plant are incorporated within a single reactor pressure vessel. This paper is the third in a series of four papers, which describe the design and functionality of the Westinghouse SMR. It focuses in particular upon the plant building layout and modular design of the Westinghouse SMR. In the development of small modular reactors, the building layout is an area where the safety of the plant can be improved by applying new design approaches. This paper will present an overview of the Westinghouse SMR building layout and indicate how the design features improve the safety and robustness of the plant. The Westinghouse SMR is designed with no shared systems between individual reactor units. The main buildings inside the security fence are the nuclear island, the rad-waste building, the annex building, and the turbine building. All safety related equipment is located in the nuclear island, which is a seismic class 1 building. To further enhance the safety and robustness of the design, the reactor, containment, and most of the safety related equipment are located below grade on the nuclear island. This reduces the possibility of severe damage from external threats or natural disasters. Two safety related ultimate heat sink (UHS) water tanks that are used for decay heat removal are located above grade, but are redundant and physically separated as far as possible for improved safety. The reactor and containment vessel are located below grade in the center of the nuclear island. The rad-waste and other radioactive systems are located on the bottom floors to limit the radiation exposure to personnel. The Westinghouse SMR safety trains are completely separated into four unconnected quadrants of the building, with access between quadrants only allowed

  8. Optimization of Wind Farm Layout in Complex Terrain

    DEFF Research Database (Denmark)

    Xu, Chang; Yang, Jianchuan; Li, Chenqi

    2013-01-01

    Microscopic site selection for wind farms in complex terrain is a technological difficulty in the development of onshore wind farms. This paper presented a method for optimizing wind farm layout in complex terrain. This method employed Lissaman and Jensen wake models, took wind velocity....... To calculate the output of each section, we used the wind speed distribution and its probability density as well as the wake loss between wind turbines for every section. The objective function is maximization of the whole wind farm's power output and the free variables are the wind turbines' coordinates which...... distribution law and wake loss between different turbines into consideration and calculated the sheltering area effect of wake loss from upstream wind turbines on downstream wind turbines. Wind direction was divided into sixteen sections, and the wind speed was processed by the Weibull distribution...

  9. Hydrodynamic Modelling and Layout Optimisation of Wave Energy Converter Arrays

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé

    2017-01-01

    This PhD thesis explores mathematical models for recreation of small-amplitude ocean waves and their interaction with assemblies of oscillating wave energy converters. Underpinned by the simulation capabilities associated with these models, algorithms seeking optimal arrangements between devices...... in various positions and orientations are finally investigated. This thesis intends in this way to offer a practical approach to the analysis of wave energy converters when they operate together as an array and the optimal design of array layouts. The topics covered by the text include propagation of waves...... around solid bodies, generation of waves by oscillating bodies, wave transformation due to slowly-varying water depth conditions, basic principles of wave power extraction by oscillating bodies, and optimal formation of arrays of wave energy converters....

  10. The information system for LHC parameters and layouts

    CERN Document Server

    Wildner, E; Mottier, M; Pettersson, Thomas Sven; Risselada, Thys

    1998-01-01

    The construction of the Large Hadron Collider, LHC, at CERN implies both the handling of a huge amount of information and the control of the coherence of this information. The LHC machine parameters have to be maintained coherent as the design evolves from the conceptual stage to the actual, installed, machine and have to be made available to all concerned. Design data is provided in many different formats from the machine builders, drawings, technical documents, meeting notes, lattice simulation input files, etc. The World Wide Web is being used to make the information accessible both at CERN and at the external collaborating laboratories. In this paper we describe the implementation of an Oracle database as the central common repository for machine parameters and of information for the automatic generation of CAD layout drawings and WWW pages. This system is integrated in a larger context, the EDMS system for the LHC project, which encompasses both the accelerator and the experiments.

  11. Analyzing the layout of China's strategic petroleum reserve base

    Science.gov (United States)

    Lan, Huiqing; Zhang, Zhijie

    2017-08-01

    With the development of China's economy, its dependence on foreign oil increases every year. Therefore, oil reserves play a vital role in ensuring China's energy security. The selection of a base site for the construction of strategic oil reserves is a priority. This study analyzes the status quo as well as future development trends for oil processing conditions, pipeline transportation conditions, consumption and production in the base radiation area, crude oil loading and unloading capacity of the port, reserve modes, and other factors. Preliminary planning of the spatial layout of the petroleum strategic reserve base is also detailed in this study. Strategic oil reserve bases can be positioned at the Pearl River Delta, the crude oil pipelines of Central and Southwest China and the large refineries and locations near the crude oil port terminals. Meanwhile, ground and underground reserve modes should be combined.

  12. The CERN-SPL Chopper Concept and Final Layout

    CERN Document Server

    Caspers, Friedhelm; Genest, J; Haase, M; Paoluzzi, M; Teixeira, A

    2004-01-01

    The fast chopper for the CERN SPL (Superconducting Proton Linac) consists of a double meander structure with β = v/c of 8 % printed on an alumina substrate for the deflecting plates. Each chopper unit is 50 cm long and housed in a quadrupole magnet surrounding the vacuum chamber. The deflecting plates are operated simultaneously in a dual mode, namely traveling wave mode for frequencies above about 10 MHz and as quasi electrostatic deflectors below. The deflecting structures are water-cooled to handle heating from beam losses as well as from the deflecting signal. A detailed mechanical layout is presented including the tri-axial feeding and termination technique as well as a discussion of the drive amplifier.

  13. A New Data Layout For Set Intersection on GPUs

    DEFF Research Database (Denmark)

    Amossen, Rasmus Resen; Pagh, Rasmus

    2011-01-01

    Set intersection is the core in a variety of problems, e.g. frequent itemset mining and sparse boolean matrix multiplication. It is well-known that large speed gains can, for some computational problems, be obtained by using a graphics processing unit (GPU) as a massively parallel computing device....... However, GPUs require highly regular control flow and memory access patterns, and for this reason previous GPU methods for intersecting sets have used a simple bitmap representation. This representation requires excessive space on sparse data sets. In this paper we present a novel data layout, BATMAP....... The main finding is that our method is able to achieve speedups over both Apriori and FP-growth when the number of distinct items is large, and the density of the problem instance is above 1%. Previous implementations of frequent itemset mining on GPU have not been able to show speedups over the best...

  14. An efficient grid layout algorithm for biological networks utilizing various biological attributes

    Directory of Open Access Journals (Sweden)

    Kato Mitsuru

    2007-03-01

    Full Text Available Abstract Background Clearly visualized biopathways provide a great help in understanding biological systems. However, manual drawing of large-scale biopathways is time consuming. We proposed a grid layout algorithm that can handle gene-regulatory networks and signal transduction pathways by considering edge-edge crossing, node-edge crossing, distance measure between nodes, and subcellular localization information from Gene Ontology. Consequently, the layout algorithm succeeded in drastically reducing these crossings in the apoptosis model. However, for larger-scale networks, we encountered three problems: (i the initial layout is often very far from any local optimum because nodes are initially placed at random, (ii from a biological viewpoint, human layouts still exceed automatic layouts in understanding because except subcellular localization, it does not fully utilize biological information of pathways, and (iii it employs a local search strategy in which the neighborhood is obtained by moving one node at each step, and automatic layouts suggest that simultaneous movements of multiple nodes are necessary for better layouts, while such extension may face worsening the time complexity. Results We propose a new grid layout algorithm. To address problem (i, we devised a new force-directed algorithm whose output is suitable as the initial layout. For (ii, we considered that an appropriate alignment of nodes having the same biological attribute is one of the most important factors of the comprehension, and we defined a new score function that gives an advantage to such configurations. For solving problem (iii, we developed a search strategy that considers swapping nodes as well as moving a node, while keeping the order of the time complexity. Though a naïve implementation increases by one order, the time complexity, we solved this difficulty by devising a method that caches differences between scores of a layout and its possible updates

  15. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  16. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  17. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  18. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  19. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  20. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  1. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  2. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  3. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  4. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  5. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  6. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces. Copyright © 2014 Elsevier B.V. All rights reserved.

  7. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  8. Designing with Space Syntax : A configurative approach to architectural layout, proposing a computational methodology

    NARCIS (Netherlands)

    Nourian, P.; Rezvani, S.; Sariyildiz, I.S.

    2013-01-01

    This paper introduces a design methodology and a toolkit developed as a parametric CAD program for configurative design of architectural plan layouts. Using this toolkit, designers can start plan layout process with sketching the way functional spaces need to connect to each other. A tool draws an

  9. 29 CFR 1926.752 - Site layout, site-specific erection plan and construction sequence.

    Science.gov (United States)

    2010-07-01

    ... 29 Labor 8 2010-07-01 2010-07-01 false Site layout, site-specific erection plan and construction sequence. 1926.752 Section 1926.752 Labor Regulations Relating to Labor (Continued) OCCUPATIONAL SAFETY AND... Steel Erection § 1926.752 Site layout, site-specific erection plan and construction sequence. (a...

  10. The changing pages of comics : Page layouts across eight decades of American superhero comics

    NARCIS (Netherlands)

    Pederson, Kaitlin; Cohn, Neil

    2016-01-01

    Page layouts are one of the most overt features of comics’ structure. We hypothesized that American superhero comics have changed in their page layout over eight decades, and investigated this using a corpus analysis of 40 comics from 1940 through 2014. On the whole, we found that comics pages

  11. Coplanar Electrode Layout Optimized for Increased Sensitivity for Electrical Impedance Spectroscopy

    DEFF Research Database (Denmark)

    Clausen, Casper Hyttel; Skands, Gustav Erik; Bertelsen, Christian Vinther

    2015-01-01

    This work describes an improvement in the layout of coplanar electrodes for electrical impedance spectroscopy. We have developed, fabricated, and tested an improved electrode layout, which improves the sensitivity of an impedance flow cytometry chip. The improved chip was experimentally tested...

  12. Optimization lighting layout based on gene density improved genetic algorithm for indoor visible light communications

    Science.gov (United States)

    Liu, Huanlin; Wang, Xin; Chen, Yong; Kong, Deqian; Xia, Peijie

    2017-05-01

    For indoor visible light communication system, the layout of LED lamps affects the uniformity of the received power on communication plane. In order to find an optimized lighting layout that meets both the lighting needs and communication needs, a gene density genetic algorithm (GDGA) is proposed. In GDGA, a gene indicates a pair of abscissa and ordinate of a LED, and an individual represents a LED layout in the room. The segmented crossover operation and gene mutation strategy based on gene density are put forward to make the received power on communication plane more uniform and increase the population's diversity. A weighted differences function between individuals is designed as the fitness function of GDGA for reserving the population having the useful LED layout genetic information and ensuring the global convergence of GDGA. Comparing square layout and circular layout, with the optimized layout achieved by the GDGA, the power uniformity increases by 83.3%, 83.1% and 55.4%, respectively. Furthermore, the convergence of GDGA is verified compared with evolutionary algorithm (EA). Experimental results show that GDGA can quickly find an approximation of optimal layout.

  13. Layout Geometry in the Selection of Intrinsic Frames of Reference from Multiple Viewpoints

    Science.gov (United States)

    Mou, Weimin; Zhao, Mintao; McNamara, Timothy P.

    2007-01-01

    Four experiments investigated the roles of layout geometry in the selection of intrinsic frames of reference in spatial memory. Participants learned the locations of objects in a room from 2 or 3 viewing perspectives. One view corresponded to the axis of bilateral symmetry of the layout, and the other view(s) was (were) nonorthogonal to the axis…

  14. 49 CFR 238.447 - Train operator's controls and power car cab layout.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Train operator's controls and power car cab layout. 238.447 Section 238.447 Transportation Other Regulations Relating to Transportation (Continued... layout. (a) Train operator controls in the power car cab shall be arranged so as to minimize the chance...

  15. Sensitivity Analysis of WEC Array Layout Parameters Effect on the Power Performance

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé; Ferri, Francesco; Kofoed, Jens Peter

    2015-01-01

    This study assesses the effect that the array layout choice has on the power performance. To this end, a sensitivity analysis is carried out with six array layout parameters, as the simulation inputs, the array power performance (q-factor), as the simulation output, and a simulation model specially...

  16. Extracting 3D layout from a single image using global image structures.

    Science.gov (United States)

    Lou, Zhongyu; Gevers, Theo; Hu, Ninghang

    2015-10-01

    Extracting the pixel-level 3D layout from a single image is important for different applications, such as object localization, image, and video categorization. Traditionally, the 3D layout is derived by solving a pixel-level classification problem. However, the image-level 3D structure can be very beneficial for extracting pixel-level 3D layout since it implies the way how pixels in the image are organized. In this paper, we propose an approach that first predicts the global image structure, and then we use the global structure for fine-grained pixel-level 3D layout extraction. In particular, image features are extracted based on multiple layout templates. We then learn a discriminative model for classifying the global layout at the image-level. Using latent variables, we implicitly model the sublevel semantics of the image, which enrich the expressiveness of our model. After the image-level structure is obtained, it is used as the prior knowledge to infer pixel-wise 3D layout. Experiments show that the results of our model outperform the state-of-the-art methods by 11.7% for 3D structure classification. Moreover, we show that employing the 3D structure prior information yields accurate 3D scene layout segmentation.

  17. An integrated approach for the cell formation and layout design in cellular manufacturing systems

    NARCIS (Netherlands)

    Javadi, Babak; Jolai, Fariborz; Slomp, Jannes; Rabbani, Masoud; Tavakkoli-Moghaddam, Reza

    2013-01-01

    In this paper, a comprehensive model is presented for cell formation and layout design in cellular manufacturing systems (CMS). The proposed model incorporates an extensive coverage of important operational features and especially layout design aspects to determine optimal cell configuration and

  18. 33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

    Science.gov (United States)

    2010-07-01

    ... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Layout and spacing of marine transfer area for LHG. 127.1105 Section 127.1105 Navigation and Navigable Waters COAST GUARD, DEPARTMENT OF... Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

  19. 33 CFR 127.105 - Layout and spacing of marine transfer area for LNG.

    Science.gov (United States)

    2010-07-01

    ... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Layout and spacing of marine transfer area for LNG. 127.105 Section 127.105 Navigation and Navigable Waters COAST GUARD, DEPARTMENT OF... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Natural Gas § 127.105 Layout and...

  20. Thermal Performance for Wet Cooling Tower with Different Layout Patterns of Fillings under Typical Crosswind Conditions

    Directory of Open Access Journals (Sweden)

    Ming Gao

    2017-01-01

    Full Text Available A thermal-state model experimental study was performed in lab to investigate the thermal performance of a wet cooling tower with different kinds of filling layout patterns under windless and 0.4 m/s crosswind conditions. In this paper, the contrast analysis was focused on comparing a uniform layout pattern and one kind of optimal non-uniform layout pattern when the environmental crosswind speed is 0 m/s and 0.4 m/s. The experimental results proved that under windless conditions, the heat transfer coefficient and total heat rejection of circulating water for the optimal non-uniform layout pattern can enhance by approximately 40% and 28%, respectively, compared with the uniform layout pattern. It was also discovered that the optimal non-uniform pattern can dramatically relieve the influence of crosswind on the thermal performance of the tower when the crosswind speed is equal to 0.4 m/s. For the uniform layout pattern, the heat transfer coefficient under 0.4 m/s crosswind conditions decreased by 9.5% compared with the windless conditions, while that value lowered only by 2.0% for the optimal non-uniform layout pattern. It has been demonstrated that the optimal non-uniform layout pattern has the better thermal performance under 0.4 m/s crosswind condition.

  1. Yearbook and Magazine Layout, English, Journalism. Language Arts: 5113.200.

    Science.gov (United States)

    Adams, Marlene E.

    Developed as a quinmester unit for the high school on yearbook and magazine layout, this guide provides the teacher with suggested teaching strategies for a study of the theory and practice of page layout, photo cropping and editing, use of color and special effects, copy fitting and headline writing and fitting, and principles of typography.…

  2. Intelligent Help in the LOCATE Workspace Layout Tool

    Science.gov (United States)

    1999-06-01

    LOCATE’s basic design and analysis features; • commercialising the application; • expanding the groundwork for tracking actions and goals at the interface...Muraida, D.J. (Eds.) (1993). Automating instructional design: Concepts and issues. Englewood Cliffs, N.J.: Educational Technology Publications

  3. Young children reorient by computing layout geometry, not by matching images of the environment.

    Science.gov (United States)

    Lee, Sang Ah; Spelke, Elizabeth S

    2011-02-01

    Disoriented animals from ants to humans reorient in accord with the shape of the surrounding surface layout: a behavioral pattern long taken as evidence for sensitivity to layout geometry. Recent computational models suggest, however, that the reorientation process may not depend on geometrical analyses but instead on the matching of brightness contours in 2D images of the environment. Here we test this suggestion by investigating young children's reorientation in enclosed environments. Children reoriented by extremely subtle geometric properties of the 3D layout: bumps and ridges that protruded only slightly off the floor, producing edges with low contrast. Moreover, children failed to reorient by prominent brightness contours in continuous layouts with no distinctive 3D structure. The findings provide evidence that geometric layout representations support children's reorientation.

  4. Using the clustered circular layout as an informative method for visualizing protein-protein interaction networks.

    Science.gov (United States)

    Fung, David C Y; Wilkins, Marc R; Hart, David; Hong, Seok-Hee

    2010-07-01

    The force-directed layout is commonly used in computer-generated visualizations of protein-protein interaction networks. While it is good for providing a visual outline of the protein complexes and their interactions, it has two limitations when used as a visual analysis method. The first is poor reproducibility. Repeated running of the algorithm does not necessarily generate the same layout, therefore, demanding cognitive readaptation on the investigator's part. The second limitation is that it does not explicitly display complementary biological information, e.g. Gene Ontology, other than the protein names or gene symbols. Here, we present an alternative layout called the clustered circular layout. Using the human DNA replication protein-protein interaction network as a case study, we compared the two network layouts for their merits and limitations in supporting visual analysis.

  5. A New Layout for English Letters on the Keyboard Using Evolutionary Strategy

    Directory of Open Access Journals (Sweden)

    Ali Asghar Poorhajikazam

    2015-10-01

    Full Text Available Since the keyboard is the primary device of entering text into a computer, a keyboard with letters on the proper layout of high performance is essential. Obtaining a suitable arrangements for the letters on the keyboard is an optimization problem which different methods have been proposed to solve it and its answer is the most appropriate permutation for letters on the keyboard which is 26 letters for English keyboard. In this paper, a new English keyboard layout has been proposed using evolutionary strategy which aims to increase typing speed and rectify some problems of current layout. To this end, a fitness function is used which includes parameters such as keys distance, fingers switch, frequency of use of both hands and etc. Different experiments have been conducted to evaluate the proposed approach and the results indicate that the obtained layout acts better than the current and other proposed layouts in the literature.

  6. Layout Optimization of Sensor-based Reconstruction of Explosion Overpressure Field Based on the Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    Miaomiao Bai

    2014-11-01

    Full Text Available In underwater blasting experiment, the layout of the sensor has always been highly concerned. From the perspective of reconstruction with explosion overpressure field, the paper presents four indicators, which can obtain the optimal sensor layout scheme and guide sensor layout in practical experiment, combining with the genetic algorithm with global search. Then, a multi-scale model in every subregion of underwater blasting field was established to be used simulation experiments. By Matlab, the variation of these four indicators with different sensor layout, and reconstruction accuracy are analyzed and discussed. Finally, a conclusion has been raised through the analysis and comparison of simulation results, that the program can get a better sensor layout. It requires fewer number of sensors to be able to get good results with high accuracy. In the actual test explosions, we can refer to this scheme laid sensors.

  7. Apron layout design and flight-to-gate assignment at Lanseria International airport

    Directory of Open Access Journals (Sweden)

    Leonard, T.

    2013-05-01

    Full Text Available Air traffic is continuously increasing and more efficient air transport systems are required to handle the air travel demand. The study investigates the expansion of Lanseria International Airport in Gauteng, South Africa. Expansion of Lanseria requires a study of the airport apron layout to ensure efficient passenger-aircraft flow as well as the efficient flow of aircraft to and from the airport. The candidate layout designs are based on the layout concept of the Hartsfield-Jackson Atlanta International Airport in Atlanta, USA. In the study, different airport apron layouts were compared, including the existing layout of Atlanta Airport, via a simulation model of each. Designs based mainly on passenger transfer distance between the terminal building and aircraft were evaluated. The cross-entropy method was used to develop a generic flight-to-gate assignment program that minimises passenger transfer distances.

  8. Coal mining with Triple-section extraction process in stagger arrangement roadway layout method

    Science.gov (United States)

    Cui, Zimo; Liu, Baozhu; Zhao, Jingli; Chanda, Emmanuel

    2017-03-01

    This paper introduces the Triple-section extraction process in the three-dimensional roadway layout of stagger arrangement method for longwall top-coal caving mining. This 3-D roadway layout of stagger arrangement method without coal pillars, which arranged the air intake roadway and air return roadway in different horizons, realizing the design theory transformation of roadway layout from 2D system to 3D system. And the paper makes systematic analysis to the geological, technical and economic factors, applies this new mining roadway layout technology for raising coal recovery ratio and solving the problems about full-seam mining in thick coal seam synthetically according to theoretical study and mining practice. Furthermore, the paper presents a physical simulation about inner staggered roadway layout of this particular longwall top-coal caving method.

  9. Automated Generation of Finite-Element Meshes for Aircraft Conceptual Design

    Science.gov (United States)

    Li, Wu; Robinson, Jay

    2016-01-01

    This paper presents a novel approach for automated generation of fully connected finite-element meshes for all internal structural components and skins of a given wing-body geometry model, controlled by a few conceptual-level structural layout parameters. Internal structural components include spars, ribs, frames, and bulkheads. Structural layout parameters include spar/rib locations in wing chordwise/spanwise direction and frame/bulkhead locations in longitudinal direction. A simple shell thickness optimization problem with two load conditions is used to verify versatility and robustness of the automated meshing process. The automation process is implemented in ModelCenter starting from an OpenVSP geometry and ending with a NASTRAN 200 solution. One subsonic configuration and one supersonic configuration are used for numerical verification. Two different structural layouts are constructed for each configuration and five finite-element meshes of different sizes are generated for each layout. The paper includes various comparisons of solutions of 20 thickness optimization problems, as well as discussions on how the optimal solutions are affected by the stress constraint bound and the initial guess of design variables.

  10. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  11. Young children's knowledge about the spatial layout of writing.

    Science.gov (United States)

    Treiman, Rebecca; Mulqueeny, Kevin; Kessler, Brett

    2015-07-01

    Children who are knowledgeable about the basic properties of writing when formal literacy instruction begins are better prepared to benefit from that instruction than children who know less about this topic. In the present study, we examined U.S. preschoolers' knowledge about one aspect of writing: its spatial arrangement. Our participants, who had a mean age of 4 years, 2 months and who could not read any words in a list of simple words, were significantly above the level of chance at determining that horizontally arranged strings of letters are more like the writing in books than are letters with vertical, diagonal, or scattered arrangements. Contrary to the theory that children learn about the characteristics of writing that hold true in all writing systems before they learn about the characteristics that are specific to their own writing system, young children did not show a priority for vertical arrangements. The results are more consistent with the hypothesis that preschoolers apply their statistical learning skills to the spatial layout of writing.

  12. Environmental layout complexity affects neural activity during navigation in humans.

    Science.gov (United States)

    Slone, Edward; Burles, Ford; Iaria, Giuseppe

    2016-05-01

    Navigating large-scale surroundings is a fundamental ability. In humans, it is commonly assumed that navigational performance is affected by individual differences, such as age, sex, and cognitive strategies adopted for orientation. We recently showed that the layout of the environment itself also influences how well people are able to find their way within it, yet it remains unclear whether differences in environmental complexity are associated with changes in brain activity during navigation. We used functional magnetic resonance imaging to investigate how the brain responds to a change in environmental complexity by asking participants to perform a navigation task in two large-scale virtual environments that differed solely in interconnection density, a measure of complexity defined as the average number of directional choices at decision points. The results showed that navigation in the simpler, less interconnected environment was faster and more accurate relative to the complex environment, and such performance was associated with increased activity in a number of brain areas (i.e. precuneus, retrosplenial cortex, and hippocampus) known to be involved in mental imagery, navigation, and memory. These findings provide novel evidence that environmental complexity not only affects navigational behaviour, but also modulates activity in brain regions that are important for successful orientation and navigation. © 2016 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

  13. LADS: Optimizing Data Transfers using Layout-Aware Data Scheduling

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Youngjae [ORNL; Atchley, Scott [ORNL; Vallee, Geoffroy R [ORNL; Shipman, Galen M [ORNL

    2015-01-01

    While future terabit networks hold the promise of signifi- cantly improving big-data motion among geographically distributed data centers, significant challenges must be overcome even on today s 100 gigabit networks to real- ize end-to-end performance. Multiple bottlenecks exist along the end-to-end path from source to sink. Data stor- age infrastructure at both the source and sink and its in- terplay with the wide-area network are increasingly the bottleneck to achieving high performance. In this paper, we identify the issues that lead to congestion on the path of an end-to-end data transfer in the terabit network en- vironment, and we present a new bulk data movement framework called LADS for terabit networks. LADS ex- ploits the underlying storage layout at each endpoint to maximize throughput without negatively impacting the performance of shared storage resources for other users. LADS also uses the Common Communication Interface (CCI) in lieu of the sockets interface to use zero-copy, OS-bypass hardware when available. It can further im- prove data transfer performance under congestion on the end systems using buffering at the source using flash storage. With our evaluations, we show that LADS can avoid congested storage elements within the shared stor- age resource, improving I/O bandwidth, and data transfer rates across the high speed networks.

  14. Sandia Agile MEMS Prototyping, Layout Tools, Education and Services Program

    Energy Technology Data Exchange (ETDEWEB)

    Schriner, H.; Davies, B.; Sniegowski, J.; Rodgers, M.S.; Allen, J.; Shepard, C.

    1998-05-01

    Research and development in the design and manufacture of Microelectromechanical Systems (MEMS) is growing at an enormous rate. Advances in MEMS design tools and fabrication processes at Sandia National Laboratories` Microelectronics Development Laboratory (MDL) have broadened the scope of MEMS applications that can be designed and manufactured for both military and commercial use. As improvements in micromachining fabrication technologies continue to be made, MEMS designs can become more complex, thus opening the door to an even broader set of MEMS applications. In an effort to further research and development in MEMS design, fabrication, and application, Sandia National Laboratories has launched the Sandia Agile MEMS Prototyping, Layout Tools, Education and Services Program or SAMPLES program. The SAMPLES program offers potential partners interested in MEMS the opportunity to prototype an idea and produce hardware that can be used to sell a concept. The SAMPLES program provides education and training on Sandia`s design tools, analysis tools and fabrication process. New designers can participate in the SAMPLES program and design MEMS devices using Sandia`s design and analysis tools. As part of the SAMPLES program, participants` designs are fabricated using Sandia`s 4 level polycrystalline silicon surface micromachine technology fabrication process known as SUMMiT (Sandia Ultra-planar, Multi-level MEMS Technology). Furthermore, SAMPLES participants can also opt to obtain state of the art, post-fabrication services provided at Sandia such as release, packaging, reliability characterization, and failure analysis. This paper discusses the components of the SAMPLES program.

  15. LAYOUT AND DESIGN OF ELECTROMOBILE CHARGING STATIONS AS URBAN ELEMENTS

    Directory of Open Access Journals (Sweden)

    Tomáš Chovan

    2015-12-01

    Full Text Available The contribution is dedicated to the processing of the problems of the insufficient charging for the electric vehicles within the concrete urbanistic centre. It brings a different perspective on the mobility, which is shown in the form of electric energy as the alternative for the needs of urbanization of the cities. It analyses electromobility, new technologies in the field of electric vehicles and the charging stations as the elements of the urbanism. In terms of the solution, the contribution is focused on the Košice city and the location of the public charging stations. Košice do not have sufficient amount of the public charging stations and until the 2014 there was only one public charging station. The contribution is focused on the designing of the parking places with the charging station placed on the appropriate parking places. The resulting design is created in the CAD system, it brings the view of the layout of the charging station at the shopping centre in the open space and in the parking house.

  16. Graph-based layout analysis for PDF documents

    Science.gov (United States)

    Xu, Canhui; Tang, Zhi; Tao, Xin; Li, Yun; Shi, Cao

    2013-03-01

    To increase the flexibility and enrich the reading experience of e-book on small portable screens, a graph based method is proposed to perform layout analysis on Portable Document Format (PDF) documents. Digital born document has its inherent advantages like representing texts and fractional images in explicit form, which can be straightforwardly exploited. To integrate traditional image-based document analysis and the inherent meta-data provided by PDF parser, the page primitives including text, image and path elements are processed to produce text and non text layer for respective analysis. Graph-based method is developed in superpixel representation level, and page text elements corresponding to vertices are used to construct an undirected graph. Euclidean distance between adjacent vertices is applied in a top-down manner to cut the graph tree formed by Kruskal's algorithm. And edge orientation is then used in a bottom-up manner to extract text lines from each sub tree. On the other hand, non-textual objects are segmented by connected component analysis. For each segmented text and non-text composite, a 13-dimensional feature vector is extracted for labelling purpose. The experimental results on selected pages from PDF books are presented.

  17. Application of approximate pattern matching in two dimensional spaces to grid layout for biochemical network maps.

    Science.gov (United States)

    Inoue, Kentaro; Shimozono, Shinichi; Yoshida, Hideaki; Kurata, Hiroyuki

    2012-01-01

    For visualizing large-scale biochemical network maps, it is important to calculate the coordinates of molecular nodes quickly and to enhance the understanding or traceability of them. The grid layout is effective in drawing compact, orderly, balanced network maps with node label spaces, but existing grid layout algorithms often require a high computational cost because they have to consider complicated positional constraints through the entire optimization process. We propose a hybrid grid layout algorithm that consists of a non-grid, fast layout (preprocessor) algorithm and an approximate pattern matching algorithm that distributes the resultant preprocessed nodes on square grid points. To demonstrate the feasibility of the hybrid layout algorithm, it is characterized in terms of the calculation time, numbers of edge-edge and node-edge crossings, relative edge lengths, and F-measures. The proposed algorithm achieves outstanding performances compared with other existing grid layouts. Use of an approximate pattern matching algorithm quickly redistributes the laid-out nodes by fast, non-grid algorithms on the square grid points, while preserving the topological relationships among the nodes. The proposed algorithm is a novel use of the pattern matching, thereby providing a breakthrough for grid layout. This application program can be freely downloaded from http://www.cadlive.jp/hybridlayout/hybridlayout.html.

  18. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  19. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  20. Automated Budget System -

    Data.gov (United States)

    Department of Transportation — The Automated Budget System (ABS) automates management and planning of the Mike Monroney Aeronautical Center (MMAC) budget by providing enhanced capability to plan,...

  1. A segmentation algorithm based on image projection for complex text layout

    Science.gov (United States)

    Zhu, Wangsheng; Chen, Qin; Wei, Chuanyi; Li, Ziyang

    2017-10-01

    Segmentation algorithm is an important part of layout analysis, considering the efficiency advantage of the top-down approach and the particularity of the object, a breakdown of projection layout segmentation algorithm. Firstly, the algorithm will algorithm first partitions the text image, and divided into several columns, then for each column scanning projection, the text image is divided into several sub regions through multiple projection. The experimental results show that, this method inherits the projection itself and rapid calculation speed, but also can avoid the effect of arc image information page segmentation, and also can accurate segmentation of the text image layout is complex.

  2. A case study of printing industry plant layout for effective production

    Science.gov (United States)

    Viswajit, T.; Teja, T. Ravi; Deepthi, Y. P.

    2017-07-01

    This paper presents the overall picture of the processes happening in printing industry. This research is aimed to improve the plant layout of existing plant. The travel time was reduced by relocating machinery. Relocation is based on systematic layout planning (SLP). The complete process of raw material entering the industry to dispatching of finished product is shown in 3-D Flow diagram. The process happening in each floor explained in detail using Flow Process chart. Travel time is reduced by 25% after modifying existing plant layout.

  3. Automation 2017

    CERN Document Server

    Zieliński, Cezary; Kaliczyńska, Małgorzata

    2017-01-01

    This book consists of papers presented at Automation 2017, an international conference held in Warsaw from March 15 to 17, 2017. It discusses research findings associated with the concepts behind INDUSTRY 4.0, with a focus on offering a better understanding of and promoting participation in the Fourth Industrial Revolution. Each chapter presents a detailed analysis of a specific technical problem, in most cases followed by a numerical analysis, simulation and description of the results of implementing the solution in a real-world context. The theoretical results, practical solutions and guidelines presented are valuable for both researchers working in the area of engineering sciences and practitioners looking for solutions to industrial problems. .

  4. Marketing automation

    Directory of Open Access Journals (Sweden)

    TODOR Raluca Dania

    2017-01-01

    Full Text Available The automation of the marketing process seems to be nowadays, the only solution to face the major changes brought by the fast evolution of technology and the continuous increase in supply and demand. In order to achieve the desired marketing results, businessis have to employ digital marketing and communication services. These services are efficient and measurable thanks to the marketing technology used to track, score and implement each campaign. Due to the technical progress, the marketing fragmentation, demand for customized products and services on one side and the need to achieve constructive dialogue with the customers, immediate and flexible response and the necessity to measure the investments and the results on the other side, the classical marketing approached had changed continue to improve substantially.

  5. Analog very large-scale integrated (VLSI) implementation of a model of amplitude-modulation sensitivity in the auditory brainstem.

    Science.gov (United States)

    van Schaik, A; Meddis, R

    1999-02-01

    An analog very large-scale integrated (VLSI) implementation of a model of signal processing in the auditory brainstem is presented and evaluated. The implementation is based on a model of amplitude-modulation sensitivity in the central nucleus of the inferior colliculus (CNIC) previously described by Hewitt and Meddis [J. Acoust. Soc. Am. 95, 2145-2159 (1994)]. A single chip is used to implement the three processing stages of the model; the inner-hair cell (IHC), cochlear nucleus sustained-chopper, and CNIC coincidence-detection stages. The chip incorporates two new circuits: an IHC circuit and a neuron circuit. The input to the chip is taken from a "silicon cochlea" consisting of a cascade of filters that simulate basilar membrane mechanical frequency selectivity. The chip which contains 142 neurons was evaluated using amplitude-modulated pure tones. Individual cells in the CNIC stage demonstrate bandpass rate-modulation responses using these stimuli. The frequency of modulation is represented spatially in an array of these cells as the location of the cell generating the highest rate of action potentials. The chip processes acoustic signals in real time and demonstrates the feasibility of using analog VLSI to build and test auditory models that use large numbers of component neurons.

  6. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  7. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  8. Layout design process in conventional Brazilian supermarkets Proceso de formulación de layouts en supermercados convencionales en Brasil Processo de formulação de layouts em supermercados convencionais no Brasil

    Directory of Open Access Journals (Sweden)

    Ana Maria Machado Toaldo

    2010-12-01

    Full Text Available The importance of the layout is well known in the performance of supermarket companies. However since there are very few studies on the subject, this research sought to understand the layout design process in conventionally sized supermarkets in the South of Brazil. For this reason an exploratory study was carried out. The choice of this methodology was due to scarceness of accumulated and systematized knowledge. Data were collected by in-depth interviews with a layout supervisor and a store manager in three supermarket chains in the South of Brazil. Results confirm that layout has considerable influence on company performance. A variety of strategies is used by the companies in layouts to make the customer remain in the store longer, make his stay more enjoyable and consequently encourage spending thus bringing about greater profitability. Finally, a theoretical structure of design layout was proposed. The intention of this study is not to be definitive, but to shed light on the subject, which while important, has never been emphasized in marketing studies.Es evidente la importancia del layout en el desempeño de las empresas supermercadistas. Sin embargo, faltan estudios sobre el tema. Pensando en esa laguna, esta investigación tuvo el objetivo principal de entender como es el proceso de formulación de layouts en supermercados de porte convencional en el Sur brasileño. Para eso, se realizó un estudio exploratorio. La decisión de escoger esa metodología fue en consecuencia de la escasez de conocimiento acumulado y sistematizado. Los datos fueron obtenidos por medio de entrevistas en profundidad realizadas con dos informantes en tres redes supermercadistas del sur de Brasil: un supervisor de layout y un gerente de tienda. Los resultados muestran que el layout tiene mucha influencia en el desempeño de la empresa. Por su intermedio, utilizándose una serie de estrategias, las empresas buscan los siguientes objetivos: hacer con que el

  9. Navigating comics: an empirical and theoretical approach to strategies of reading comic page layouts.

    Science.gov (United States)

    Cohn, Neil

    2013-01-01

    Like the sequence of words in written language, comic book page layouts direct images into a deliberate reading sequence. Conventional wisdom would expect that comic panels follow the order of text: left-to-right and down - a "Z-path" - though several layouts can violate this order, such as Gestalt groupings of panels that deny a Z-path of reading. To examine how layouts pressure readers to choose pathways deviating from the Z-path, we presented participants with comic pages empty of content, and asked them to number the panels in the order they would read them. Participants frequently used strategies departing from both the traditional Z-path and Gestalt groupings. These preferences reveal a system of constraints that organizes panels into hierarchic constituents, guiding readers through comic page layouts.

  10. Integration of value stream map and strategic layout planning into DMAIC approach to improve carpeting process

    National Research Council Canada - National Science Library

    Ayman Nagi; Safwan Altarazi

    2017-01-01

    Purpose: This paper presents an implementation of the Six Sigma DMAIC approach implementing lean tools and facilities layout techniques to reduce the occurrence of different types of nonconformities in the carpeting process...

  11. Coplanar Electrode Layout Optimized for Increased Sensitivity for Electrical Impedance Spectroscopy

    Directory of Open Access Journals (Sweden)

    Casper Hyttel Clausen

    2014-12-01

    Full Text Available This work describes an improvement in the layout of coplanar electrodes for electrical impedance spectroscopy. We have developed, fabricated, and tested an improved electrode layout, which improves the sensitivity of an impedance flow cytometry chip. The improved chip was experimentally tested and compared to a chip with a conventional electrode layout. The improved chip was able to discriminate 0.5 μm beads from 1 μm as opposed to the conventional chip. Furthermore, finite element modeling was used to simulate the improvements in electrical field density and uniformity between the electrodes of the new electrode layout. Good agreement was observed between the model and the obtained experimental results.

  12. Navigating comics: an empirical and theoretical approach to strategies of reading comic page layouts

    Directory of Open Access Journals (Sweden)

    Neil eCohn

    2013-04-01

    Full Text Available Like the sequence of words in written language, comic book page layouts direct images into a deliberate reading sequence. Conventional wisdom would expect that comic panels follow the order of text: left-to-right and down—a Z-path—though several layouts can violate this order, such as Gestalt groupings of panels that deny a Z-path of reading. To examine how layouts pressure readers to choose pathways deviating from the Z-path, we presented participants with comic pages empty of content, and asked them to number the panels in the order they would read them. Participants frequently used strategies departing from both the traditional Z-path and Gestalt groupings. These preferences reveal a system of constraints that organizes panels into hierarchic constituents, guiding readers through comic page layouts.

  13. Navigating Comics: An Empirical and Theoretical Approach to Strategies of Reading Comic Page Layouts

    Science.gov (United States)

    Cohn, Neil

    2013-01-01

    Like the sequence of words in written language, comic book page layouts direct images into a deliberate reading sequence. Conventional wisdom would expect that comic panels follow the order of text: left-to-right and down – a “Z-path” – though several layouts can violate this order, such as Gestalt groupings of panels that deny a Z-path of reading. To examine how layouts pressure readers to choose pathways deviating from the Z-path, we presented participants with comic pages empty of content, and asked them to number the panels in the order they would read them. Participants frequently used strategies departing from both the traditional Z-path and Gestalt groupings. These preferences reveal a system of constraints that organizes panels into hierarchic constituents, guiding readers through comic page layouts. PMID:23616776

  14. Solving the wind farm layout optimization problem using random search algorithm

    DEFF Research Database (Denmark)

    Feng, Ju; Shen, Wen Zhong

    2015-01-01

    Wind farm (WF) layout optimization is to find the optimal positions of wind turbines (WTs) inside a WF, so as to maximize and/or minimize a single objective or multiple objectives, while satisfying certain constraints. In this work, a random search (RS) algorithm based on continuous formulation...... by expert guesses or other optimization methods, and as an optimization tool to find the optimal layout of WF with a certain number of WTs. A new strategy to evaluate layouts is also used, which can largely save the computation cost. This method is first applied to a widely studied ideal test problem....... In this application, it is also found that in order to get consistent and reliable optimization results, up to 360 or more sectors for wind direction have to be used. Finally, considering the inevitable inter-annual variations in the wind conditions, the robustness of the optimized layouts against wind condition...

  15. Wind farm layout optimization in complex terrain: A preliminary study on a Gaussian hill

    DEFF Research Database (Denmark)

    Feng, Ju; Shen, Wen Zhong

    2014-01-01

    One of the crucial problems for wind farm (WF) development is wind farm layout optimization. It seeks to find the optimal positions of wind turbines (WTs) inside a WF, so as to maximize and/or minimize a single objective or multiple objectives, while satisfying certain constraints. Although...... this problem for WFs in flat terrain or offshore has been investigated in many studies, it is still a challenging problem for WFs in complex terrain. In this preliminary study, the wind flow conditions of complex terrain without WTs are first obtained from computational fluid dynamics (CFD) simulation...... adaptive mechanisms and applied to solve the layout optimization problem of a WF on a Gaussian shape hill. The layout of the WF with a certain number of WTs is optimized to maximize the total power output, which obtained steady improvements over expert guess layouts....

  16. Change of the layout of an office of a metallurgical company: simple projects, big solutions.

    Science.gov (United States)

    Duarte, Luiz Carlos da Silva; Eckhardt, Moacir; da Motta, Giordano Paulo

    2012-01-01

    The posture, a good organization and the proper layout of the environment and workplaces have a positive influence on the income of an employee. To develop the work it is used a methodology that addressed the study phases of the theory involving the subject, description of the current situation, preparation of conceptions, choice of design, implementation and reporting of results. Through the project of "Change of the layout of an office of a metallurgical company" there was an intervention in these reported aspects providing improvements in the office, regarding ergonomic, layout, workplace and lighting issues, bringing welfare to the official, with the intent to improve its performance within the company and facilitating its actions, as the company's customer service. The results provided improvements in layout, in the workplace and especially in comfort for the human resources that perform their activities.

  17. Layout Optimization of Structures with Finite-size Features using Multiresolution Analysis

    DEFF Research Database (Denmark)

    Chellappa, S.; Diaz, A. R.; Bendsøe, Martin P.

    2004-01-01

    A scheme for layout optimization in structures with multiple finite-sized heterogeneities is presented. Multiresolution analysis is used to compute reduced operators (stiffness matrices) representing the elastic behavior of material distributions with heterogeneities of sizes that are comparable...

  18. A spatial multi-objective optimization model for sustainable urban wastewater system layout planning.

    Science.gov (United States)

    Dong, X; Zeng, S; Chen, J

    2012-01-01

    Design of a sustainable city has changed the traditional centralized urban wastewater system towards a decentralized or clustering one. Note that there is considerable spatial variability of the factors that affect urban drainage performance including urban catchment characteristics. The potential options are numerous for planning the layout of an urban wastewater system, which are associated with different costs and local environmental impacts. There is thus a need to develop an approach to find the optimal spatial layout for collecting, treating, reusing and discharging the municipal wastewater of a city. In this study, a spatial multi-objective optimization model, called Urban wastewateR system Layout model (URL), was developed. It is solved by a genetic algorithm embedding Monte Carlo sampling and a series of graph algorithms. This model was illustrated by a case study in a newly developing urban area in Beijing, China. Five optimized system layouts were recommended to the local municipality for further detailed design.

  19. Validation of the Data Consolidation in Layout Database for the LHC Tunnel Cryogenics Controls Upgrade

    CERN Document Server

    Tovar-Gonzalez, A; Blanco, E; Fortescue-Beck, E; Fluder, C; Inglese, V; Pezzetti, M; Gomes, P; Wolak, T; Dudek, M; Frassinelli, F; Drozd, A; Zapolski, M

    2014-01-01

    The control system of the Large Hadron Collider cryogenics manages over 34’000 instrumentation and actuator channels. The complete information on their characteristics and parameters can be extracted from a set of views on the Layout database, to generate the specifications of the control system; from these, the code to populate PLCs (Programmable Logic Controller) and SCADA (Supervisory Control & Data Acquisition) is automatically produced, within the UNICOS framework (Unified Industrial Control System). The Layout database is, since 2003, progressively integrating and centralizing information on the whole CERN Accelerator complex. It models topographical organization (layouts) as functional positions and relationships. After three years of machine operation, many parameters have been manually adjusted in SCADA and PLCs; they now differ from their original values in the Layout database. Furthermore, to accommodate the upgrade of the UNICOS Continuous Process Control package to version 6, some data stru...

  20. A hierarchical layout design method based on rubber band potentialenergy descending

    Directory of Open Access Journals (Sweden)

    Ou Cheng Yi

    2016-01-01

    Full Text Available Strip packing problems is one important sub-problem of the Cutting stock problems. Its application domains include sheet metal, ship making, wood, furniture, garment, shoes and glass. In this paper, a hierarchical layout design method based on rubber band potential-energy descending was proposed. The basic concept of the rubber band enclosing model was described in detail. We divided the layout process into three different stages: initial layout stage, rubber band enclosing stage and local adjustment stage. In different stages, the most efficient strategies were employed for further improving the layout solution. Computational results show that the proposed method performed better than the GLSHA algorithm for three out of nine instances in utilization.

  1. BioLayout(Java): versatile network visualisation of structural and functional relationships.

    Science.gov (United States)

    Goldovsky, Leon; Cases, Ildefonso; Enright, Anton J; Ouzounis, Christos A

    2005-01-01

    Visualisation of biological networks is becoming a common task for the analysis of high-throughput data. These networks correspond to a wide variety of biological relationships, such as sequence similarity, metabolic pathways, gene regulatory cascades and protein interactions. We present a general approach for the representation and analysis of networks of variable type, size and complexity. The application is based on the original BioLayout program (C-language implementation of the Fruchterman-Rheingold layout algorithm), entirely re-written in Java to guarantee portability across platforms. BioLayout(Java) provides broader functionality, various analysis techniques, extensions for better visualisation and a new user interface. Examples of analysis of biological networks using BioLayout(Java) are presented.

  2. Two-Finger Keyboard Layout Problem: An Application On Turkish Language

    OpenAIRE

    Agpak, Kursad; Karateke, Huseyin; Mete, Suleyman

    2016-01-01

    Smart phone and tablet usage has sharply increased for the last decade. While entering test on these devices, virtual keyboards are generally used instead of conventional hardware keyboards. In this study, a new problem which is two-finger keyboard layout problem and solution approach is presented for increasing user test entrance performance, especially on virtual keyboards. Defined two-finger keyboard layout problem is modeled as Quadratic Assignment Problem. Because of combinatorial struct...

  3. Site Layout of the proposed new Hadrons' Injector Chain at CERN

    CERN Document Server

    Baldy, J L; Evans, L; Garoby, R; Gerigk, F; Lindroos, M; López-Hernandez, L A; Maury, S; Poehler, M; Silari, M; Vretenar, M

    2008-01-01

    The replacement of almost all the LHC injector complex on the Meyrin-site of CERN (Linac2, PSB and PS) is planned within the next 10 years. The layout foreseen for the new accelerators is described in this paper, together with its compatibility with the existing experimental physics facilities. These machines can, after upgrade, supply with high beam power future physics facilities for radioactive ions and/or neutrinos. Their possible layout is also sketched in this document.

  4. Improvement of productivity in low volume production industry layout by using witness simulation software

    Science.gov (United States)

    Jaffrey, V.; Mohamed, N. M. Z. N.; Rose, A. N. M.

    2017-10-01

    In almost all manufacturing industry, increased productivity and better efficiency of the production line are the most important goals. Most factories especially small scale factory has less awareness of manufacturing system optimization and lack of knowledge about it and uses the traditional way of management. Problems that are commonly identified in the factory are a high idle time of labour and also small production. This study is done in a Small and Medium Enterprises (SME) low volume production company. Data collection and problems affecting productivity and efficiency are identified. In this study, Witness simulation software is being used to simulate the layout and the output is focusing on the improvement of layout in terms of productivity and efficiency. In this study, the layout is rearranged by reducing the travel time from a workstation to another workstation. Then, the improved layout is modelled and the machine and labour statistic of both, original and improved layout is taken. Productivity and efficiency are calculated for both layout and then being compared.

  5. Systematic Layout Planning of a Radiology Reporting Area to Optimize Radiologists' Performance.

    Science.gov (United States)

    Benitez, Guilherme Brittes; Fogliatto, Flavio Sanson; Cardoso, Ricardo Bertoglio; Torres, Felipe Soares; Faccin, Carlo Sasso; Dora, José Miguel

    2017-11-28

    Optimizing radiologists' performance is a major priority for managers of health services/systems, since the radiologists' reporting activity imposes a severe constraint on radiology productivity. Despite that, methods to optimize radiologists' reporting workplace layout are scarce in the literature. This study was performed in the Radiology Division (RD) of an 850-bed University-based general hospital. The analysis of the reporting workplace layout was carried out using the systematic layout planning (SLP) method, in association with cluster analysis as a complementary tool in early stages of SLP. Radiologists, architects, and hospital managers were the stakeholders consulted for the completion of different stages of the layout planning process. A step-by-step description of the proposed methodology to plan an RD reporting layout is presented. Clusters of radiologists were defined using types of exams reported and their frequency of occurrence as clustering variables. Sectors with high degree of interaction were placed in proximity in the new RD layout, with separation of noisy and quiet areas. Four reporting cells were positioned in the quiet area, grouping radiologists by subspecialty, as follows: cluster 1-abdomen; cluster 2-musculoskeletal; cluster 3-neurological, vascular and head & neck; cluster 4-thoracic and cardiac. The creation of reporting cells has the potential to limit unplanned interruptions and enhance the exchange of knowledge and information within cells, joining radiologists with the same expertise. That should lead to improvements in productivity, allowing managers to more easily monitor radiologists' performance.

  6. a Preliminary Work on Layout Slam for Reconstruction of Indoor Corridor Environments

    Science.gov (United States)

    Baligh Jahromi, A.; Sohn, G.; Shahbazi, M.; Kang, J.

    2017-09-01

    We propose a real time indoor corridor layout estimation method based on visual Simultaneous Localization and Mapping (SLAM). The proposed method adopts the Manhattan World Assumption at indoor spaces and uses the detected single image straight line segments and their corresponding orthogonal vanishing points to improve the feature matching scheme in the adopted visual SLAM system. Using the proposed real time indoor corridor layout estimation method, the system is able to build an online sparse map of structural corner point features. The challenges presented by abrupt camera rotation in the 3D space are successfully handled through matching vanishing directions of consecutive video frames on the Gaussian sphere. Using the single image based indoor layout features for initializing the system, permitted the proposed method to perform real time layout estimation and camera localization in indoor corridor areas. For layout structural corner points matching, we adopted features which are invariant under scale, translation, and rotation. We proposed a new feature matching cost function which considers both local and global context information. The cost function consists of a unary term, which measures pixel to pixel orientation differences of the matched corners, and a binary term, which measures the amount of angle differences between directly connected layout corner features. We have performed the experiments on real scenes at York University campus buildings and the available RAWSEEDS dataset. The incoming results depict that the proposed method robustly performs along with producing very limited position and orientation errors.

  7. Exploring the Effects of Pitch Layout on Learning a New Musical Instrument

    Directory of Open Access Journals (Sweden)

    Jennifer MacRitchie

    2017-11-01

    Full Text Available Although isomorphic pitch layouts are proposed to afford various advantages for musicians playing new musical instruments, this paper details the first substantive set of empirical tests on how two fundamental aspects of isomorphic pitch layouts affect motor learning: shear, which makes the pitch axis vertical, and the adjacency (or nonadjacency of pitches a major second apart. After receiving audio-visual training tasks for a scale and arpeggios, performance accuracies of 24 experienced musicians were assessed in immediate retention tasks (same as the training tasks, but without the audio-visual guidance and in a transfer task (performance of a previously untrained nursery rhyme. Each participant performed the same tasks with three different pitch layouts and, in total, four different layouts were tested. Results show that, so long as the performance ceiling has not already been reached (due to ease of the task or repeated practice, adjacency strongly improves performance accuracy in the training and retention tasks. They also show that shearing the layout, to make the pitch axis vertical, worsens performance accuracy for the training tasks but, crucially, it strongly improves performance accuracy in the transfer task when the participant needs to perform a new, but related, task. These results can inform the design of pitch layouts in new musical instruments.

  8. Using RGB-D sensors and evolutionary algorithms for the optimization of workstation layouts.

    Science.gov (United States)

    Diego-Mas, Jose Antonio; Poveda-Bautista, Rocio; Garzon-Leal, Diana

    2017-11-01

    RGB-D sensors can collect postural data in an automatized way. However, the application of these devices in real work environments requires overcoming problems such as lack of accuracy or body parts' occlusion. This work presents the use of RGB-D sensors and genetic algorithms for the optimization of workstation layouts. RGB-D sensors are used to capture workers' movements when they reach objects on workbenches. Collected data are then used to optimize workstation layout by means of genetic algorithms considering multiple ergonomic criteria. Results show that typical drawbacks of using RGB-D sensors for body tracking are not a problem for this application, and that the combination with intelligent algorithms can automatize the layout design process. The procedure described can be used to automatically suggest new layouts when workers or processes of production change, to adapt layouts to specific workers based on their ways to do the tasks, or to obtain layouts simultaneously optimized for several production processes. Copyright © 2017 Elsevier Ltd. All rights reserved.

  9. LIDAR TS for ITER core plasma. Part I: layout & hardware

    Science.gov (United States)

    Salzmann, H.; Gowers, C.; Nielsen, P.

    2017-12-01

    The original time-of-flight design of the Thomson scattering diagnostic for the ITER core plasma has been shown up by ITER. This decision was justified by insufficiencies of some of the components. In this paper we show that with available, present day technology a LIDAR TS system is feasible which meets all the ITER specifications. As opposed to the conventional TS system the LIDAR TS also measures the high field side of the plasma. The optical layout of the front end has been changed only little in comparison with the latest one considered by ITER. The main change is that it offers an optical collection without any vignetting over the low field side. The throughput of the system is defined only by the size and the angle of acceptance of the detectors. This, in combination with the fact that the LIDAR system uses only one set of spectral channels for the whole line of sight, means that no absolute calibration using Raman or Rayleigh scattering from a non-hydrogen isotope gas fill of the vessel is needed. Alignment of the system is easy since the collection optics view the footprint of the laser on the inner wall. In the described design we use, simultaneously, two different wavelength pulses from a Nd:YAG laser system. Its fundamental wavelength ensures measurements of 2 keV up to more than 40 keV, whereas the injection of the second harmonic enables measurements of low temperatures. As it is the purpose of this paper to show the technological feasibility of the LIDAR system, the hardware is considered in Part I of the paper. In Part II we demonstrate by numerical simulations that the accuracy of the measurements as required by ITER is maintained throughout the given plasma parameter range. The effect of enhanced background radiation in the wavelength range 400 nm–500 nm is considered. In Part III the recovery of calibration in case of changing spectral transmission of the front end is treated. We also investigate how to improve the spatial resolution at the

  10. Automation of soft-gluon resummation in Sherpa

    Energy Technology Data Exchange (ETDEWEB)

    Ferrarese, Piero; Schumann, Steffen [II. Physikalisches Institut, Georg-August-Universitaet Goettingen (Germany)

    2016-07-01

    We present a fully automated NLL resummation of soft-gluons in global event-shape distributions at hadron colliders, for generic QCD processes. In general, for non-additive variables, the single logarithmic piece of the resummed distribution involves integrals that are not analytically solvable. We present a new algorithm to evaluate such integral, based on Monte Carlo methods. For this purpose we employ the parton-shower formalism, as implemented in the SHERPA event generator, to efficiently generate points in the multiple emission phase space. We discuss the general layout of our approach and present exemplary results.

  11. Real-time feedback for improving compliance to hand sanitization among healthcare workers in an open layout ICU using radiofrequency identification.

    Science.gov (United States)

    Radhakrishna, Kedar; Waghmare, Abijeet; Ekstrand, Maria; Raj, Tony; Selvam, Sumithra; Sreerama, Sai Madhukar; Sampath, Sriram

    2015-06-01

    The aim of this study is to increase hand sanitizer usage among healthcare workers by developing and implementing a low-cost intervention using RFID and wireless mesh networks to provide real-time alarms for increasing hand hygiene compliance during opportune moments in an open layout Intensive Care Unit (ICU). A wireless, RFID based system was developed and implemented in the ICU. The ICU beds were divded into an intervention arm (n = 10) and a control arm (n = 14). Passive RFID tags were issued to the doctors, nurses and support staff of the ICU. Long range RFID readers were positioned strategically. Sensors were placed beneath the hand sanitizers to record sanitizer usage. The system would alert the HCWs by flashing a light if an opportune moment for hand sanitization was detected. A significant increase in hand sanitizer use was noted in the intervention arm. Usage was highest during the early part of the workday and decreased as the day progressed. Hand wash events per person hour was highest among the ancilliary staff followed by the doctors and nurses. Real-time feedback has potential to increase hand hygiene compliance among HCWs. The system demonstrates the possibility of automating compliance monitoring in an ICU with an open layout.

  12. New shipyard layout design for the preliminary phase & case study for the green field project

    Directory of Open Access Journals (Sweden)

    Young Joo Song

    2013-03-01

    Full Text Available For several decades, Asian nations such as Korea, Japan and China have been leading the shipbuilding industry since the decline in Europe and America. However, several developing countries such as India, Brazil, etc. are going to make an entrance into the shipbuilding industry. These developing countries are finding technical partners or information providers because they are in situation of little experiences and technologies. Now, the shipbuilding engineering companies of shipbuilding advanced countries are getting a chance of engineering business against those developing countries. The starting point of this business model is green field project for the construction of new shipyard. This business model is started with a design of the shipyard layout. For the conducting of the shipyard layout design, four kinds of engineering parts are required. Those are civil engineering, building engineering, utility engineering and production layout engineering. Among these parts, production layout engineering is most important because its result is the foundation of the other engineering parts and it determines the shipyard capacity during the shipyard operation lifecycle. Previous researches about the shipyard layout design are out of the range from the business requirements because most research cases are in the tower of ivory, which means that there are little consideration of real ship and shipbuilding operation. In this paper, a shipyard layout design for preliminary phase is conducted for the target of newly planned shipyard at Venezuela of South America with an integrated method that is capable of dealing with actual master data from the shipyard. The layout design method of this paper is differentiated from the previous researches in that the actual product data from the target ship and the actual shipbuilding operation data are used for the required area estimation.

  13. Built environmental factors and adults' travel behaviors: Role of street layout and local destinations.

    Science.gov (United States)

    Koohsari, Mohammad Javad; Owen, Neville; Cole, Rachel; Mavoa, Suzanne; Oka, Koichiro; Hanibuchi, Tomoya; Sugiyama, Takemi

    2017-03-01

    Street layout is consistently associated with adults' travel behaviors, however factors influencing this association are unclear. We examined associations of street layout with travel behaviors: walking for transport (WT) and car use; and, the extent to which these relationships may be accounted for by availability of local destinations. A 24-h travel diary was completed in 2009 by 16,345 adult participants of the South-East Queensland Household Travel Survey, Australia. Three travel-behavior outcomes were derived: any home-based WT; over 30min of home-based WT; and, over 60min of car use. For street layout, a space syntax measure of street integration was calculated for each Statistical Area 1 (SA1, the smallest geographic unit in Australia). An objective measure of availability of destinations - Walk Score - was also derived for each SA1. Logistic regression examined associations of street layout with travel behaviors. Mediation analyses examined to what extent availability of destinations explained the associations. Street integration was significantly associated with travel behaviors. Each one-decile increment in street integration was associated with an 18% (95%CI: 1.15, 1.21) higher odds of any home-based WT; a 10% (95%CI: 1.06, 1.15) higher odds of over 30min of home-based WT; and a 5% (95%CI: 0.94, 0.96) lower odds of using a car over 60min. Local destinations partially mediated the effects of street layout on travel behaviors. Well-connected street layout contributes to active travel partially through availability of more local destinations. Urban design strategies need to address street layout and destinations to promote active travel among residents. Copyright © 2016 Elsevier Inc. All rights reserved.

  14. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  15. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  16. Manufacturing and automation

    Directory of Open Access Journals (Sweden)

    Ernesto Córdoba Nieto

    2006-09-01

    Full Text Available The article presents concepts and definitions from different sources concerning automation. The work approaches automation by virtue of the author’s experience in manufacturing production; why and how automation prolects are embarked upon is considered. Technological reflection regarding the progressive advances or stages of automation in the production area is stressed. Coriat and Freyssenet’s thoughts about and approaches to the problem of automation and its current state are taken and examined, especially that referring to the problem’s relationship with reconciling the level of automation with the flexibility and productivity demanded by competitive, worldwide manufacturing.

  17. Simulation based performance analysis of an end-of-Aisle automated storage and retrieval system

    OpenAIRE

    Bahrami, Behnam; Aghezzaf, El-Houssaine; Limère, Veronique

    2014-01-01

    This paper presents and discusses simulation of an End-of-Aisle automated storage and retrieval system, using FLEXSIM 6. The objective of the simulation model is to analyze and compare results of different control policies and physical designs. The performance measures considered for the evaluation of each control policy and layout combination are the total travel time of the crane and the number of storage and retrieval operations performed. The experiments set up and the corresponding resul...

  18. Emulated Muscle Spindle and Spiking Afferents Validates VLSI Neuromorphic Hardware as a Testbed for Sensorimotor Function and Disease

    Directory of Open Access Journals (Sweden)

    Chuanxin M. Niu

    2014-12-01

    Full Text Available The lack of multi-scale empirical measurements (e.g. recording simultaneously from neurons, muscles, whole body, etc. complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI technology to provide considerable scalability and high-speed, as much as 365x faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006 and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Matthews, 1964; 1972; Crowe and Matthews, 1964b. Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365x real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  19. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  20. Layout de teclado para uma prancha de comunicação alternativa e ampliada Keyboard layout for an augmentative and alternative communication board

    Directory of Open Access Journals (Sweden)

    Luciane Aparecida Liegel

    2008-12-01

    Full Text Available O objetivo deste artigo é descrever e discutir a proposta de um novo layout de teclado projetado especialmente para uma prancha de comunicação alternativa com acionamento mecânico e remoto, para ser utilizado por portadores de paralisia cerebral com capacidade cognitiva preservada. Para compor o layout do teclado de comunicação alternativa, realizou-se uma pesquisa envolvendo disposição e conteúdo das teclas. Participaram do estudo onze voluntárias, sendo: cinco professoras de educação especial, quatro pedagogas especializadas em educação especial e duas fonoaudiólogas. O layout é composto por 95 teclas dispostas em grupos de teclas: alfabéticas, de letras acentuadas, numéricas, de funções e de comunicação alternativa e ampliada. As teclas de comunicação alternativa, contêm ícones associados à palavras ou frases, além de teclas acentuadas. Os ícones contemplados fazem parte de uma linguagem visual brasileira de comunicação, em desenvolvimento. Para auxiliar na localização, tanto o tamanho de teclas e caracteres quanto as cores de fundo das teclas diferenciadas foram utilizadas. As teclas com letras acentuadas e as teclas de comunicação alternativa visam facilitar e acelerar a digitação das mensagens, reduzindo assim o tempo de digitação e conseqüentemente, a ocorrência de fadiga muscular.The aim of this article is to describe and discuss a novel layout proposal for keyboard especially designed for a communication board using mechanical and remote activation to be used by people with cerebral paralysis who present sufficient cognitive skills. In order to design the layout of the augmentative and alternative communication keyboard, a research study involving position and content of the keys was undertaken. Eleven volunteers participated in the study, and they were: five special education teachers, four pedagogues specialized in special education and two speech and language therapists. The layout is made up

  1. Efficient Digital Signage-Based Online Store Layout: An Experimental Study

    Directory of Open Access Journals (Sweden)

    Muhammad Fazal Ijaz

    2016-05-01

    Full Text Available In today’s era of information technology, human computer interaction and interface design are critical factors for a successful retail business. In a virtual world, the purpose of store layout is to create an environment that fascinates customers, entices them to spend more time in the store and encourages them to purchase from the store. The accomplishment of a successful retail business relies on a quick response and the adoption of new technologies that simplify the customer’s shopping experience. Virtual stores play a vital role in enhancing the success of a retail business. Nowadays, digital signage is widely used to publicize different store contents. The aim of this paper is to select a distinct layout that can be used in digital signage. To enhance Customer Relationship Management (CRM, digital signage can be installed in various contexts, such as metro stations, shopping centers, airplane terminals, and so on. The proposed system scans the Quick Response (QR code of a product, and the product then arrives at the user end. The tree, pipeline and guiding pathway layouts are employed in the context of digital signage. A questionnaire is used to determine customers’ opinions on the most efficient layout. The statistical results show that layout significantly affects customer’s behavior. Moreover, human computer interaction can help understand more about the customer’s interaction with digital signage.

  2. The Systems Biology Markup Language (SBML) Level 3 Package: Layout, Version 1 Core.

    Science.gov (United States)

    Gauges, Ralph; Rost, Ursula; Sahle, Sven; Wengler, Katja; Bergmann, Frank Thomas

    2015-09-04

    Many software tools provide facilities for depicting reaction network diagrams in a visual form. Two aspects of such a visual diagram can be distinguished: the layout (i.e.: the positioning and connections) of the elements in the diagram, and the graphical form of the elements (for example, the glyphs used for symbols, the properties of the lines connecting them, and so on). For software tools that also read and write models in SBML (Systems Biology Markup Language) format, a common need is to store the network diagram together with the SBML representation of the model. This in turn raises the question of how to encode the layout and the rendering of these diagrams. The SBML Level 3 Version 1 Core specification does not provide a mechanism for explicitly encoding diagrams, but it does provide a mechanism for SBML packages to extend the Core specification and add additional syntactical constructs. The Layout package for SBML Level 3 adds the necessary features to SBML so that diagram layouts can be encoded in SBML files, and a companion package called SBML Rendering specifies how the graphical rendering of elements can be encoded. The SBML Layout package is based on the principle that reaction network diagrams should be described as representations of entities such as species and reactions (with direct links to the underlying SBML elements), and not as arbitrary drawings or graphs; for this reason, existing languages for the description of vector drawings (such as SVG) or general graphs (such as GraphML) cannot be used.

  3. Conversion of KEGG metabolic pathways to SBGN maps including automatic layout.

    Science.gov (United States)

    Czauderna, Tobias; Wybrow, Michael; Marriott, Kim; Schreiber, Falk

    2013-08-16

    Biologists make frequent use of databases containing large and complex biological networks. One popular database is the Kyoto Encyclopedia of Genes and Genomes (KEGG) which uses its own graphical representation and manual layout for pathways. While some general drawing conventions exist for biological networks, arbitrary graphical representations are very common. Recently, a new standard has been established for displaying biological processes, the Systems Biology Graphical Notation (SBGN), which aims to unify the look of such maps. Ideally, online repositories such as KEGG would automatically provide networks in a variety of notations including SBGN. Unfortunately, this is non-trivial, since converting between notations may add, remove or otherwise alter map elements so that the existing layout cannot be simply reused. Here we describe a methodology for automatic translation of KEGG metabolic pathways into the SBGN format. We infer important properties of the KEGG layout and treat these as layout constraints that are maintained during the conversion to SBGN maps. This allows for the drawing and layout conventions of SBGN to be followed while creating maps that are still recognizably the original KEGG pathways. This article details the steps in this process and provides examples of the final result.

  4. Impact of Furniture Layout on Indoor Daylighting Performance in Existing Residential Buildings in Malaysia

    Directory of Open Access Journals (Sweden)

    Seyed Mohammad Mousavi

    2018-06-01

    Full Text Available Currently, home-based computing workspaces have developed substantially all over the world, especially in Malaysia. This growing trend attracts computer workers to run a business from their residential units. Hence, visual comfort needs to be considered in addition to thermal comfort for home workers in their residential working rooms. While such rooms are always occupied with furniture, the layout of the furniture may influence the indoor daylighting distribution. Several various furniture layouts can be arranged in a residential working room. However, to have better generalisation, this study focused on the impacts of mostly-used-furniture-layouts (MUFLs on indoor daylighting performance in residential working rooms. The field measurement was conducted in a typically furnished room under a tropical sky to validate the results of the simulation software under different sky conditions. Then, daylight ratio (DR, as a quantitative daylighting variable, and the illuminance uniformity ratio (IUR, CIE glare index (CGI, and Guth visual comfort probability (GVCP, as qualitative daylighting variables, were analysed through simulation experiments. In conclusion, by changing the furniture layout, daylight uniformity recorded the highest fluctuations in the case room among all variables. While various furniture layouts, in a residential working room in the tropics, may even slightly reduce the extreme indoor daylight quantity, they can worsen the indoor daylight quality compared to an unfurnished space. The paper shows that furniture as an interior design parameter cannot help to improve tropical daylighting performance in a building.

  5. Optimasi Site Layout pada Proyek Pembangunan Apartemen Pavilion Permata Tower 2

    Directory of Open Access Journals (Sweden)

    Dhanang Bagus Setyobudi

    2017-03-01

    Full Text Available Dalam pelaksanaan pekerjaan proyek konstruksi terdapat fasilitas-fasilitas yang mendukung seperti gudang, direksi kit, barak kerja dan lain sebagainya yang terdapat pada area proyek. Tata letak fasilitas-fasilitas, luas lahan dan perencanaan mobilisasi gerak terdapat pada site layout. Namun, penataan site layout umumnya masih kurang mendapatkan perhatian atau tidak direncanakan secara optimal. Oleh karena itu perlu dilakukan perhitungan site layout secara terperinci untuk mendapatkan hasil yang optimal Proyek yang akan digunakan dalam penelitian ini adalah proyek pembangunan Apartemen Pavilion Permata Tower 2 Surabaya. Dalam penelitian ini akan dioptimasi berdasarkan hubungan jarak antara fasilitas bergerak dan fasilitas tetap berdasarkan jarak perjalanan pekerja dan jarak tempuh tower crane yang mempertimbangkan segi Traveling Distance Pekerja, Traveling Distance Tower Crane dan Safety Index . Keputusan dilakukan dengan mengguanakan analisa pengambil keputusan Analytical Hierarchy Process (AHP. Dari hasil penelitian didapatkan nilai hasil perangkingan site layout sebagai berikut eksisting sebesar 0,348, alternatif 1 sebesar 0,317 dan alternatif 2 sebesar 0,35. Dari hasil analisa tersebut dipilih nilai yang terkecil. Jadi site layout yang digunakan ialah alternatif 1 yaitu yang terbentuk berdasarkan jarak fasilitas tetap dengan fasilitas bergerak.

  6. Multiobjective Optimization for Fixture Locating Layout of Sheet Metal Part Using SVR and NSGA-II

    Directory of Open Access Journals (Sweden)

    Yuan Yang

    2017-01-01

    Full Text Available Fixture plays a significant role in determining the sheet metal part (SMP spatial position and restraining its excessive deformation in many manufacturing operations. However, it is still a difficult task to design and optimize SMP fixture locating layout at present because there exist multiple conflicting objectives and excessive computational cost of finite element analysis (FEA during the optimization process. To this end, a new multiobjective optimization method for SMP fixture locating layout is proposed in this paper based on the support vector regression (SVR surrogate model and the elitist nondominated sorting genetic algorithm (NSGA-II. By using ABAQUS™ Python script interface, a parametric FEA model is established. And the fixture locating layout is treated as design variables, while the overall deformation and maximum deformation of SMP under external forces are as the multiple objective functions. First, a limited number of training and testing samples are generated by combining Latin hypercube design (LHD with FEA. Second, two SVR prediction models corresponding to the multiple objectives are established by learning from the limited training samples and are integrated as the multiobjective optimization surrogate model. Third, NSGA-II is applied to determine the Pareto optimal solutions of SMP fixture locating layout. Finally, a multiobjective optimization for fixture locating layout of an aircraft fuselage skin case is conducted to illustrate and verify the proposed method.

  7. RELOCATION OF HOME APPLIANCES FACTORY BY USING SYSTEMATICAL LAYOUT PLANNING (SLP COMBINED WITH FLOW ANALYSIS AND ASSEMBLY PROCESS DESIGN

    Directory of Open Access Journals (Sweden)

    Yosef Adji Baskoro

    2011-12-01

    Full Text Available Every manufacturing company must have experiencing building a layout. Fred.E Meyers has stated that only death and taxes are certain, there exist a third certainty-a plant layout will change, thus many methods to generate layout are established and each has its own purposes and benefits. This research focused on the design of manufacturing facilities supported by in-depth analysis of Assembly process design with a high stresses on the Systematical Layout Planning ( SLP and Flow Analysis method to facilitate an outcome of layout accordingly to the system needs. This is a real case study conducts with an objective of generating a recommendation layout for Home Appliances Company specifically for television plant.

  8. RELOCATION OF HOME APPLIANCES FACTORY BY USING SYSTEMATICAL LAYOUT PLANNING (SLP COMBINED WITH FLOW ANALYSIS AND ASSEMBLY PROCESS DESIGN

    Directory of Open Access Journals (Sweden)

    Yosef Adji Baskoro

    2011-12-01

    Full Text Available Every manufacturing company must have experiencing building a layout. Fred.E Meyers has stated that only death and taxes are certain, there exist a third certainty-a plant layout will change, thus many methods to generate layout are established and each has its own purposes and benefits. This research focused on the design of manufacturing facilities supported by in-depth analysis of Assembly process design with a high stresses on the Systematical Layout Planning ( SLP and Flow Analysis method to facilitate an outcome of layout accordingly to the system needs. This is a real case study conducts with an objective of generating a recommendation layout for Home Appliances Company specifically for television plant

  9. Configuration Management Automation (CMA) -

    Data.gov (United States)

    Department of Transportation — Configuration Management Automation (CMA) will provide an automated, integrated enterprise solution to support CM of FAA NAS and Non-NAS assets and investments. CMA...

  10. Autonomy and Automation

    Science.gov (United States)

    Shively, Jay

    2017-01-01

    A significant level of debate and confusion has surrounded the meaning of the terms autonomy and automation. Automation is a multi-dimensional concept, and we propose that Remotely Piloted Aircraft Systems (RPAS) automation should be described with reference to the specific system and task that has been automated, the context in which the automation functions, and other relevant dimensions. In this paper, we present definitions of automation, pilot in the loop, pilot on the loop and pilot out of the loop. We further propose that in future, the International Civil Aviation Organization (ICAO) RPAS Panel avoids the use of the terms autonomy and autonomous when referring to automated systems on board RPA. Work Group 7 proposes to develop, in consultation with other workgroups, a taxonomy of Levels of Automation for RPAS.

  11. Cadence® High-Speed PCB Layout Flow Workshop

    CERN Document Server

    2003-01-01

    Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for high-speed board designs at CERN. The implementation of this methodology, build around the new Constraint Manager program, is essential when you have to develop a board having a lot of high-speed design rules such as terminated lines, large bus structures, maximum length, timing, crosstalk etc.. that could not be under control by traditional method. On more conventional designs, formal aspect of the methodology could avoid misunderstanding between hardware and ALLEGRO layout designers, minimizing prototype iteration, development time and price. The capability to keep trace of the original digital designer intents in schematic or board layout, loading formal constraints in EDMS, could also be considered for LHC electro...

  12. Efficiency Optimization by Considering the High Voltage Flyback Transformer Parasitics using an Automatic Winding Layout Technique

    DEFF Research Database (Denmark)

    Thummala, Prasanth; Schneider, Henrik; Zhang, Zhe

    2015-01-01

    .The energy efficiency is optimized using a proposed new automatic winding layout (AWL) technique and a comprehensive loss model.The AWL technique generates a large number of transformer winding layouts.The transformer parasitics such as dc resistance, leakage inductance and self-capacitance are calculated...... for each winding layout.An optimization technique is formulated to minimize the sum of energy losses during charge and discharge operations.The efficiency and energy loss distribution results from the optimization routine provide a deep insight into the high voltage transformer designand its impact...... on the total converter efficiency.The proposed efficiency optimization approach is experimentally verified on a25 W (average charging power) with100 W (peakpower) flyback dc-dc prototype....

  13. Considering induction factor using BEM method in wind farm layout optimization

    DEFF Research Database (Denmark)

    Ghadirian, Amin; Dehghan, M.; Torabi, F.

    2014-01-01

    For wind farm layout optimization process, a simple linear model has been mostly used for considering the wake effect of a wind turbine on its downstream turbines. In this model, the wind velocity in the wake behind a turbine is obtained as a function of turbine induction factor which was conside......For wind farm layout optimization process, a simple linear model has been mostly used for considering the wake effect of a wind turbine on its downstream turbines. In this model, the wind velocity in the wake behind a turbine is obtained as a function of turbine induction factor which...... and consequently influences the farm layout in optimization process. (C) 2014 Elsevier Ltd. All rights reserved....

  14. Model-based strategy for cell culture seed train layout verified at lab scale.

    Science.gov (United States)

    Kern, Simon; Platas-Barradas, Oscar; Pörtner, Ralf; Frahm, Björn

    2016-08-01

    Cell culture seed trains-the generation of a sufficient viable cell number for the inoculation of the production scale bioreactor, starting from incubator scale-are time- and cost-intensive. Accordingly, a seed train offers potential for optimization regarding its layout and the corresponding proceedings. A tool has been developed to determine the optimal points in time for cell passaging from one scale into the next and it has been applied to two different cell lines at lab scale, AGE1.HN AAT and CHO-K1. For evaluation, experimental seed train realization has been evaluated in comparison to its layout. In case of the AGE1.HN AAT cell line, the results have also been compared to the formerly manually designed seed train. The tool provides the same seed train layout based on the data of only two batches.

  15. A spectral algorithm for fast de novo layout of uncorrected long nanopore reads.

    Science.gov (United States)

    Recanati, Antoine; Brüls, Thomas; d'Aspremont, Alexandre

    2017-10-15

    New long read sequencers promise to transform sequencing and genome assembly by producing reads tens of kilobases long. However, their high error rate significantly complicates assembly and requires expensive correction steps to layout the reads using standard assembly engines. We present an original and efficient spectral algorithm to layout the uncorrected nanopore reads, and its seamless integration into a straightforward overlap/layout/consensus (OLC) assembly scheme. The method is shown to assemble Oxford Nanopore reads from several bacterial genomes into good quality (∼99% identity to the reference) genome-sized contigs, while yielding more fragmented assemblies from the eukaryotic microbe Sacharomyces cerevisiae. https://github.com/antrec/spectrassembler. antoine.recanati@inria.fr. Supplementary data are available at Bioinformatics online.

  16. Effects of scene content and layout on the perceived light direction in 3D spaces.

    Science.gov (United States)

    Xia, Ling; Pont, Sylvia C; Heynderickx, Ingrid

    2016-08-01

    The lighting and furnishing of an interior space (i.e., the reflectance of its materials, the geometries of the furnishings, and their arrangement) determine the appearance of this space. Conversely, human observers infer lighting properties from the space's appearance. We conducted two psychophysical experiments to investigate how the perception of the light direction is influenced by a scene's objects and their layout using real scenes. In the first experiment, we confirmed that the shape of the objects in the scene and the scene layout influence the perceived light direction. In the second experiment, we systematically investigated how specific shape properties influenced the estimation of the light direction. The results showed that increasing the number of visible faces of an object, ultimately using globally spherical shapes in the scene, supported the veridicality of the estimated light direction. Furthermore, symmetric arrangements in the scene improved the estimation of the tilt direction. Thus, human perception of light should integrally consider materials, scene content, and layout.

  17. Low Carbon Design Research on the Space Layout Types of Office Buildings

    Science.gov (United States)

    Xia, Bing

    2018-01-01

    It is beneficial to find out the relationship of the spatial layout and low-carbon design in order to reduce buildings’ carbon emissions in the conceptual design phase. This paper analyzes and compares shape coefficient values, annual energy consumption and lighting performance of office buildings of different space layout types in Shanghai. Based on morphological characteristics of different types, the study also analyzes and presents low-carbon design strategies for each single type. This study assumes that architects should conduct passive and active design according to the specific building space layout, so that to make best use of the advantages and bypassing the disadvantages, in order to maximally reduce buildings’ carbon emissions.

  18. Otimização de layouts industriais com base em busca tabu

    Directory of Open Access Journals (Sweden)

    Martins Valdair Candido

    2003-01-01

    Full Text Available Este artigo aborda uma solução computacional para o problema de layout industrial considerando hard-constraints não tratadas em trabalhos anteriores. O problema é solucionado em duas etapas. Na primeira, uma solução inicial baseada em heurística construtiva é gerada e na segunda, por intermédio da aplicação da meta-heurística busca tabu, a solução inicial é melhorada. Como contribuição, apresenta-se a ferramenta computacional denominada Ambiente Visual para Otimização de Layout Industrial (AVOLI, a fim de gerar layouts viáveis e eficientes capazes de tratar problemas de grande porte sujeitos a um conjunto de restrições realistas.

  19. Hyperspecificity in visual implicit learning: learning of spatial layout is contingent on item identity.

    Science.gov (United States)

    Jiang, Yuhong; Song, Joo-Hyun

    2005-12-01

    Humans conduct visual search faster when the same display is presented for a 2nd time, showing implicit learning of repeated displays. This study examines whether learning of a spatial layout transfers to other layouts that are occupied by items of new shapes or colors. The authors show that spatial context learning is sometimes contingent on item identity. For example, when the training session included some trials with black items and other trials with white items, learning of the spatial layout became specific to the trained color--no transfer was seen when items were in a new color during testing. However, when the training session included only trials in black (or white), learning transferred to displays with a new color. Similar results held when items changed shapes after training. The authors conclude that implicit visual learning is sensitive to trial context and that spatial context learning can be identity contingent. (c) 2005 APA, all rights reserved.

  20. Investigating Effects of Screen Layout Elements on Interface and Screen Design Aesthetics

    Directory of Open Access Journals (Sweden)

    Ahamed Altaboli

    2011-01-01

    Full Text Available A recent study suggested the use of the screen layout elements of balance, unity, and sequence as a part of a computational model of interface aesthetics. It is argued that these three elements are the most contributed terms in the model. In the current study, a controlled experiment was designed and conducted to systematically investigate effects of these three elements (balance, unity, and sequence on the perceived interface aesthetics. Results showed that the three elements have significant effects on the perceived interface aesthetics. Significant interactions were also found among the three elements. A regression model relating the perceived visual aesthetics to the three elements was constructed. When validating the model using standard questionnaire scores of real web pages, high correlations were found between the values computed by the model and scores of questionnaire items related to visual layout of the web pages, indicating that layout-based measures are good at assessing the classical dimension of website aesthetics.

  1. Workflow automation architecture standard

    Energy Technology Data Exchange (ETDEWEB)

    Moshofsky, R.P.; Rohen, W.T. [Boeing Computer Services Co., Richland, WA (United States)

    1994-11-14

    This document presents an architectural standard for application of workflow automation technology. The standard includes a functional architecture, process for developing an automated workflow system for a work group, functional and collateral specifications for workflow automation, and results of a proof of concept prototype.

  2. Why should we pay more for layout designers?

    Science.gov (United States)

    Khan, Samee U.

    2003-12-01

    In this paper, we discuss the Passive Optical Network (PON) deployment on an arbitrary grid with guarenteed p-1 equipment failure. We show that this problem in general is NP-hard. We propose an algorithm, which guarantees a solution of 4-approximation to the optimal deployment, and further argue that this is the best lower bound achievable in our case.A basic architecture of PON is shown in figure 1.The main component of PON is an optical splitter device. Depending on which direction the light is travelling, it splits the incoming light and distributes it to multiple fibers towards Optical Network Termination (ONT), or combines it into one towards Optical Line Terminal (OLT). The PON technology uses a double-star architecture. The first star topology centers at the OLT, and the second at the optical splitter. PROBLEM DESCRIPTION: We can formulate the problem of optimal p-1 fault-tolerent PON Network Layout (PNL)as a graph theoretical problem. Consider a graph G(V,E), such that V represent the physical locations of the subscriber's, CO, and another location acquired by the CO to expand its network, and E represent the communication lines between two Vi's. If there is no direct communication line c(i,j) between Vi and Vj, we consider the shortest path between them measured in terms of simple distance or cost constraints. Without the loss of generality we assume that c(i,j)=c(j,i). For simplicity we do not further sub-divide V into the obvious categories that represent the locations of OLT, ONT, CO, optical splitters and the subscribers. We can now formulate the PNL problem as follows: "Given an undirected graph G, find the locations of ONTs and splitters such that the cost of the equipment is minimized and for QoS the maximum distance from an ONT to the pth splitter and from a splitter to the pth OLT is minimized". We assume that the OLT is residing inside the CO. The problem definition does not consider the optimization of ONT to the customer premises. This is due

  3. “The Naming of Cats”: Automated Genre Classification

    Directory of Open Access Journals (Sweden)

    Yunhyong Kim

    2007-07-01

    Full Text Available This paper builds on the work presented at the ECDL 2006 in automated genre classification as a step toward automating metadata extraction from digital documents for ingest into digital repositories such as those run by archives, libraries and eprint services (Kim & Ross, 2006b. We have previously proposed dividing features of a document into five types (features for visual layout, language model features, stylometric features, features for semantic structure, and contextual features as an object linked to previously classified objects and other external sources and have examined visual and language model features. The current paper compares results from testing classifiers based on image and stylometric features in a binary classification to show that certain genres have strong image features which enable effective separation of documents belonging to the genre from a large pool of other documents.

  4. LAYOUT CELULAR: PROPOSTA E IMPLANTAÇÃO EM EMPRESA START-UP DE TECNOLOGIA

    Directory of Open Access Journals (Sweden)

    Lucas Almeida Dos Santos

    2016-12-01

    Full Text Available A escolha correta de um layout proporciona à organização se adaptar para melhor utilizar seus recursos em busca da melhoria contínua. A presente pesquisa, apresenta a elaboração e implantação de um layout celular tendo por base o uso das ferramentas de processos, Fluxograma, 5W2H e Diagrama de causa e efeito, no apoio da tomada de decisão do melhor layout a ser implantado.  Diante do exposto, o escopo da pesquisa objetiva apresentar a implantação do layout celular em uma empresa start-up de tecnologia, bem como os resultados obtidos mediante a proposta apresentada. Como metodologia de pesquisa, definiu-se o presente estudo como um estudo de caso, onde foi possível realizar a análise da estrutura física que corresponde a 60 m² de área de produção, para implementar o layout celular. Como principal resultado obtido destaca-se o sucesso da implantação, onde, o mesmo atendeu todas as necessidades de fabricação do produto na organização pesquisada. Concomitantemente a evolução do layout, foram definidos quatro postos de trabalho, onde se tem a entrada de MP (matéria-prima em A e a saída do produto acabado em D, conforme exposto nos resultados.

  5. Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

    OpenAIRE

    Aguirre Echanove, Miguel Ángel; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo

    1995-01-01

    Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando...

  6. ALTERAÇÃO DE UM LAYOUT FUNCIONAL PARA LAYOUT CELULAR MOTIVADO PELOS FUNDAMENTOS DA MANUFATURA ENXUTA: ESTUDO DE CASO EM UMA INDÚSTRIA DE TRANSFORMADORES

    Directory of Open Access Journals (Sweden)

    Felipe Crisóstomo Gadelha

    2015-12-01

    Full Text Available O presente trabalho apresenta o estudo de uma alteração de layout, de funcional para celular, motivado pelos fundamentos da manufatura enxuta. Tendo como objetivo verificar os benefícios de se utilizar a manufatura celular com fluxo enxuto (contínuo, apresenta como metodologia um estudo de caso, pós-fato, em uma indústria de transformadores, onde a mudança foi realizada. Para fundamentar o estudo, apresenta revisão dos temas: Sistema de Manufatura Enxuta e layout industrial, para, em seguida, trazer os dados apresentados por esta indústria, ainda em um arranjo físico funcional, antes da alteração, e, em seguida, nas células de manufatura com um fluxo enxuto, após a alteração, e realizar uma comparação entre ambos. Os resultados obtidos desta comparação apresentam ganhos como aumento de produção, em 20%, e produtividade, em 56%, redução de lead time, em 67%, mão de obra direta, em 30%, tempo de processamento, em 20%, e área fabril, em 24%, dentre outros, evidenciando os benefícios que a utilização de um layout celular e Manufatura Enxuta proporcionam.

  7. TO THE SYNTHESIS OF A LAYOUT OF MACHINE TOOL FOR BATCH PROCESSING

    Directory of Open Access Journals (Sweden)

    B. M. Rozin

    2014-01-01

    Full Text Available The problems of choosing the optimal standard size of the basic units and assembly components of machine tools for batch processing of parts are considered. The algorithms for solving some of these problems by optimizing of mutual disposition of unit elements are proposed. The algorithm for constructing 3D-models of machine tool layout elements in the graphics system T-Flex is pro-posed. The structure and method for implementation of the software for construction and estimation of the machine tool layouts for batch processing are given.

  8. Layout and EB data reduction: comparison of OASIS based approach with format-specific reversible compressions

    Science.gov (United States)

    Pai, Ravi; Pereira, Mark; Manu, C. S.; Parchuri, Anil; Baruah, Barsha

    2007-05-01

    With rapid increase in the number of geometries in a chip and aggressive RET carried out on layout data, it has become very much imperative to address the issue of layout and EB data explosion during IC design. Currently, the most widely used GDSII format for layout data as well as the widely used data formats for EB data, are incapable of handling the huge amount of data prevalent in the UDSM regime. The new non-proprietary standardized formats of OASIS for layout data and OASIS.VSB for EB data are the way the industry is likely to go in the near future to address the issue of data explosion. But, the process of adoption of these new formats is too slow as it takes a long time for new design flows to mature. The speed of adoption is especially slow in the post-layout domain as it is very close to manufacturing and the cost of error is too high. However, the issue of layout and EB data explosion is real and immediate and hence, it should be addressed in short term without waiting for the long term solution to arrive. This paper discusses about an alternative approach of employing format-specific lossless reversible layout and EB data compression schemes to compress the layout and EB data. The performance and the advantage of this approach are compared with the currently prevalent approach of using OASIS primarily and solely for on-disk file size reduction. It is argued that the reversible compression techniques could be a better approach for on-disk data file size reduction as they would not only reduce the file sizes but could also almost seamlessly get integrated into the current tool flow without necessitating major changes in the tool flow. The possibility of using OASIS itself as a format for lossless reversible compression of GDSII and MEBES data is also discussed. It is also argued that for successful adoption of OASIS formats by the industry mere on-disk file size reduction may not be sufficient. Higher value additions such as reduction in in-core database

  9. Note: Optimization of magnifying a polarization angle with Littrow layout blazed gratings.

    Science.gov (United States)

    Sasao, H; Arakawa, H; Imazawa, R; Kawano, Y; Itami, K; Kubo, H

    2017-03-01

    Magnification of a polarization angle with Littrow layout gratings has been developed. High magnification with a factor of 7.7 using two gratings in Littrow layout was experimentally proved. The magnification range was investigated by calculation at a wavelength of 10.6 μm. The method can be applied for a high magnification factor >30. Larger groove numbers and smaller blaze angles are suitable for the large magnification. Statistical fluctuation of the diffracted polarization angle is compared with that of the incident polarization angle.

  10. Layout of NALM fiber laser with adjustable peak power of generated pulses.

    Science.gov (United States)

    Smirnov, Sergey; Kobtsev, Sergey; Ivanenko, Alexey; Kokhanovskiy, Alexey; Kemmer, Anna; Gervaziev, Mikhail

    2017-05-01

    The Letter proposes a new layout of a passively mode-locked fiber laser based on a nonlinear amplifying loop mirror (NALM) with two stretches of active fiber and two independently controlled pump modules. In contrast with conventional NALM configurations using a single piece of active fiber that yields virtually constant peak power, the proposed novel laser features larger than a factor of 2 adjustment range of peak power of generated pulses. The proposed layout also provides independent adjustment of duration and peak power of generated pulses as well as power-independent control of generated pulse spectral width impossible in NALM lasers with a single piece of active fiber.

  11. The Characteristics Of Malay House Spatial Layout Of Pekanbaru In Accordance With Islamic Values

    Science.gov (United States)

    Samra, Boby

    2017-12-01

    House is not only is a place to get rest and do activities bu also treated as a pride for the Malay community. The values contained in the spatial layout of the house have specific meaning to the owners. This makes the Malay house becomes the symbol of pride to uphold the “tuah” and dignity of the owner. This research is conducted using qualitative approach through management and data management available through several methods such as observation, interview, documentation and group discussion. This is expected to provide understanding of the perception of Islam dealing with the characteristics of the spatial layout of the Malay house of Pekanbaru.

  12. tkLayout: a design tool for innovative silicon tracking detectors

    Science.gov (United States)

    Bianchi, G.

    2014-03-01

    A new CMS tracker is scheduled to become operational for the LHC Phase 2 upgrade in the early 2020's. tkLayout is a software package developed to create 3d models for the design of the CMS tracker and to evaluate its fundamental performance figures. The new tracker will have to cope with much higher luminosity conditions, resulting in increased track density, harsher radiation exposure and, especially, much higher data acquisition bandwidth, such that equipping the tracker with triggering capabilities is envisaged. The design of an innovative detector involves deciding on an architecture offering the best trade-off among many figures of merit, such as tracking resolution, power dissipation, bandwidth, cost and so on. Quantitatively evaluating these figures of merit as early as possible in the design phase is of capital importance and it is best done with the aid of software models. tkLayout is a flexible modeling tool: new performance estimates and support for different detector geometries can be quickly added, thanks to its modular structure. Besides, the software executes very quickly (about two minutes), so that many possible architectural variations can be rapidly modeled and compared, to help in the choice of a viable detector layout and then to optimize it. A tracker geometry is generated from simple configuration files, defining the module types, layout and materials. Support structures are automatically added and services routed to provide a realistic tracker description. The tracker geometries thus generated can be exported to the standard CMS simulation framework (CMSSW) for full Monte Carlo studies. tkLayout has proven essential in giving guidance to CMS in studying different detector layouts and exploring the feasibility of innovative solutions for tracking detectors, in terms of design, performance and projected costs. This tool has been one of the keys to making important design decisions for over five years now and has also enabled project engineers

  13. Automation in Clinical Microbiology

    Science.gov (United States)

    Ledeboer, Nathan A.

    2013-01-01

    Historically, the trend toward automation in clinical pathology laboratories has largely bypassed the clinical microbiology laboratory. In this article, we review the historical impediments to automation in the microbiology laboratory and offer insight into the reasons why we believe that we are on the cusp of a dramatic change that will sweep a wave of automation into clinical microbiology laboratories. We review the currently available specimen-processing instruments as well as the total laboratory automation solutions. Lastly, we outline the types of studies that will need to be performed to fully assess the benefits of automation in microbiology laboratories. PMID:23515547

  14. Architectural and landscape layout principles of river valley areas in the Ukrainian Carpathians

    OpenAIRE

    Lukomska, Iryna

    2013-01-01

    The research is focused on the challenging problem of correlation between the architecture and landscape in the river valleys located in the Ukrainian Carpathians. The article defines and proves five essential principles of architectural and landscape layout of these territories, based on the results of author’s research and modern scientific developments.

  15. Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

    DEFF Research Database (Denmark)

    Müller, Christoph; Kasapaki, Evangelia; Sørensen, Rasmus Bo

    2014-01-01

    is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented...

  16. Aspects of Wind Power Plant Collector Network Layout and Control Architecture

    DEFF Research Database (Denmark)

    Altin, Müfit; Teodorescu, Remus; Bak-Jensen, Birgitte

    2010-01-01

    . Therefore, connection topology and control concepts of large WPPs should be carefully investigated to improve the overall performance of both the WPP and the power systems. This paper aims to present a general overview of the design considerations for the electrical layout of WPPs and the WPP control...

  17. Design layout for gas monitoring system II (GMS-2) computer system

    Energy Technology Data Exchange (ETDEWEB)

    Vo, V.; Philipp, B.L.; Manke, M.P.

    1995-08-02

    This document provides a general overview of the computer systems software that perform the data acquisition and control for the 241-SY-101 Gas Monitoring System II (GMS-2). It outlines the system layout, and contains descriptions of components and the functions they perform. The GMS-2 system was designed and implemented by Los Alamos National Laboratory and supplied to Westinghouse Hanford Company

  18. Optimization for Solving Workcell Layouts using Gaussian Penalties for Escaping Local Minima

    DEFF Research Database (Denmark)

    Iversen, Thomas Fridolin; Ellekilde, Lars-Peter

    2017-01-01

    The main contribution of this paper is a method for optimizing the layout of workcells taking into consideration both the reachability of the robot as well as the expected cycle time. To analyse the reachability for systems using sensors to pose estimate objects, the method uses a combination of ...

  19. Process Mining-Based Method of Designing and Optimizing the Layouts of Emergency Departments in Hospitals.

    Science.gov (United States)

    Rismanchian, Farhood; Lee, Young Hoon

    2017-07-01

    This article proposes an approach to help designers analyze complex care processes and identify the optimal layout of an emergency department (ED) considering several objectives simultaneously. These objectives include minimizing the distances traveled by patients, maximizing design preferences, and minimizing the relocation costs. Rising demand for healthcare services leads to increasing demand for new hospital buildings as well as renovating existing ones. Operations management techniques have been successfully applied in both manufacturing and service industries to design more efficient layouts. However, high complexity of healthcare processes makes it challenging to apply these techniques in healthcare environments. Process mining techniques were applied to address the problem of complexity and to enhance healthcare process analysis. Process-related information, such as information about the clinical pathways, was extracted from the information system of an ED. A goal programming approach was then employed to find a single layout that would simultaneously satisfy several objectives. The layout identified using the proposed method improved the distances traveled by noncritical and critical patients by 42.2% and 47.6%, respectively, and minimized the relocation costs. This study has shown that an efficient placement of the clinical units yields remarkable improvements in the distances traveled by patients.

  20. Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

    NARCIS (Netherlands)

    Krabbenborg, B.H.; Krabbenborg, B.H.; Bosma, A.; de Graaff, H.C.; de Graaff, H.C.; Mouthaan, A.J.

    1996-01-01

    In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit

  1. Wind farm layout optimization in complex terrain: A preliminary study on a Gaussian hill

    Science.gov (United States)

    Feng, J.; Shen, W. Z.

    2014-06-01

    One of the crucial problems for wind farm (WF) development is wind farm layout optimization. It seeks to find the optimal positions of wind turbines (WTs) inside a WF, so as to maximize and/or minimize a single objective or multiple objectives, while satisfying certain constraints. Although this problem for WFs in flat terrain or offshore has been investigated in many studies, it is still a challenging problem for WFs in complex terrain. In this preliminary study, the wind flow conditions of complex terrain without WTs are first obtained from computational fluid dynamics (CFD) simulation, then an adapted Jensen wake model is developed by considering the terrain features and taking the inflow conditions as input. Using this combined method, the wake effects of WF in complex terrain are properly modelled. Besides, a random search (RS) algorithm proposed in previous study is improved by adding some adaptive mechanisms and applied to solve the layout optimization problem of a WF on a Gaussian shape hill. The layout of the WF with a certain number of WTs is optimized to maximize the total power output, which obtained steady improvements over expert guess layouts.

  2. Accelerator-based conversion (ABC) of weapons plutonium: Plant layout study and related design issues

    Energy Technology Data Exchange (ETDEWEB)

    Cowell, B.S.; Fontana, M.H. [Oak Ridge National Lab., TN (United States); Krakowski, R.A.; Beard, C.A.; Buksa, J.J.; Davidson, J.W.; Sailor, W.C.; Williamson, M.A. [Los Alamos National Lab., NM (United States)

    1995-04-01

    In preparation for and in support of a detailed R and D Plan for the Accelerator-Based Conversion (ABC) of weapons plutonium, an ABC Plant Layout Study was conducted at the level of a pre-conceptual engineering design. The plant layout is based on an adaptation of the Molten-Salt Breeder Reactor (MSBR) detailed conceptual design that was completed in the early 1070s. Although the ABC Plant Layout Study included the Accelerator Equipment as an essential element, the engineering assessment focused primarily on the Target; Primary System (blanket and all systems containing plutonium-bearing fuel salt); the Heat-Removal System (secondary-coolant-salt and supercritical-steam systems); Chemical Processing; Operation and Maintenance; Containment and Safety; and Instrumentation and Control systems. Although constrained primarily to a reflection of an accelerator-driven (subcritical) variant of MSBR system, unique features and added flexibilities of the ABC suggest improved or alternative approaches to each of the above-listed subsystems; these, along with the key technical issues in need of resolution through a detailed R&D plan for ABC are described on the bases of the ``strawman`` or ``point-of-departure`` plant layout that resulted from this study.

  3. Development and layout of a protocol for the field performance of concrete deck and crack sealers.

    Science.gov (United States)

    2009-09-01

    The main objective of this project was to develop and layout a protocol for the long-term monitoring and assessment of the performance of concrete deck and crack sealants in the field. To accomplish this goal, a total of six bridge decks were chosen ...

  4. Performance of Ductless Personalized Ventilation in Conjunction with Displacement Ventilation: Impact of Workstations Layout and Partitions

    DEFF Research Database (Denmark)

    Halvonova, Barbara; Melikov, Arsen Krikor

    2010-01-01

    cleaner for some of the layouts studied. The use of DPV in conjunction with DV substantially decreased the temperature of the inhaled air and increased the body cooling in comparison with use of DV alone, i.e., DPV also had potential for improving occupants' perceived air quality and thermal comfort....

  5. BFL: a node and edge betweenness based fast layout algorithm for large scale networks

    Science.gov (United States)

    Hashimoto, Tatsunori B; Nagasaki, Masao; Kojima, Kaname; Miyano, Satoru

    2009-01-01

    Background Network visualization would serve as a useful first step for analysis. However, current graph layout algorithms for biological pathways are insensitive to biologically important information, e.g. subcellular localization, biological node and graph attributes, or/and not available for large scale networks, e.g. more than 10000 elements. Results To overcome these problems, we propose the use of a biologically important graph metric, betweenness, a measure of network flow. This metric is highly correlated with many biological phenomena such as lethality and clusters. We devise a new fast parallel algorithm calculating betweenness to minimize the preprocessing cost. Using this metric, we also invent a node and edge betweenness based fast layout algorithm (BFL). BFL places the high-betweenness nodes to optimal positions and allows the low-betweenness nodes to reach suboptimal positions. Furthermore, BFL reduces the runtime by combining a sequential insertion algorim with betweenness. For a graph with n nodes, this approach reduces the expected runtime of the algorithm to O(n2) when considering edge crossings, and to O(n log n) when considering only density and edge lengths. Conclusion Our BFL algorithm is compared against fast graph layout algorithms and approaches requiring intensive optimizations. For gene networks, we show that our algorithm is faster than all layout algorithms tested while providing readability on par with intensive optimization algorithms. We achieve a 1.4 second runtime for a graph with 4000 nodes and 12000 edges on a standard desktop computer. PMID:19146673

  6. LimitS - A system for limit state analysis and optimal material layout

    DEFF Research Database (Denmark)

    Damkilde, Lars; Krenk, Steen

    1997-01-01

    distribution or an optimal material layout is determined. Through linearization of the yield criteria the optimization problem is stated as a linear programming problem. Within the formulation of the discretized model the optimal lower-bound solution is shown to be an upper-bound solution, and thereby both...

  7. Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

    Science.gov (United States)

    Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

    2017-05-01

    This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

  8. Efficacy of paediatric anaesthetic trolleys: A call for a basic standard and layout.

    Science.gov (United States)

    Griffiths, Sian E; Boleat, Elizabeth; Goodwin, Alison; Sheikh, Asme; Goonasekera, Chulananda

    2015-01-01

    Providing safe anaesthesia to children especially in emergency situations goes hand in hand with instant availability of appropriately sized equipment and monitoring. This is best achieved using a designated paediatric anaesthetic trolley containing essential equipment. Guidance for the contents of such trolleys is neither explicit nor standard. We used a survey and a qualitative enquiry to develop a checklist suitable for standardisation of contents and layout of paediatric anaesthetic trolleys. We conducted an observational study of our current practice and paediatric anaesthetic trolleys in a tertiary care hospital. We also performed a qualitative enquiry from experienced paediatric anaesthetists and operating department practitioners.We developed an empirical checklist to ensure the minimum 'essential' equipment is available on these trolleys and implemented a standard layout to facilitate its use. We identified 11 areas in our hospital where anaesthesia is provided to children, each with a designated paediatric anaesthetic trolley. There were considerable deficiencies of items in all areas with no standard pattern or layout. Different types of trolleys contributed to the confusion. In addition, overstocking of inappropriate items hindered its efficient use. Standardising the contents and layout of the paediatric anaesthetic trolley is an essential pre-requisite for safer paediatric anaesthetic practice.

  9. Robust Layout Synthesis of a MEM Crab-Leg Resonator Using a Constrained Genetic Algorithm

    DEFF Research Database (Denmark)

    Fan, Zhun; Achiche, Sofiane

    2007-01-01

    The research work carried out in this paper introduces a robust design method for layout synthesis of MEM resonator subject to inherent geometric uncertainties such as the fabrication error on the sidewall of the structure. The robust design problem is formulated as a multi-objective constrained...

  10. Wind farm power production in the changing wind: Robustness quantification and layout optimization

    DEFF Research Database (Denmark)

    Feng, Ju; Shen, Wen Zhong

    2017-01-01

    condition variations. Based on these metrics, wind farm layout optimization is performed to maximize the robustness of a real offshore wind farm in Denmark. The results demonstrate that the robustness metrics are more flexible and complete than the conventional metrics for characterizing wind farm power...

  11. Layout design-based research on optimization and assessment method for shipbuilding workshop

    Science.gov (United States)

    Liu, Yang; Meng, Mei; Liu, Shuang

    2013-06-01

    The research study proposes to examine a three-dimensional visualization program, emphasizing on improving genetic algorithms through the optimization of a layout design-based standard and discrete shipbuilding workshop. By utilizing a steel processing workshop as an example, the principle of minimum logistic costs will be implemented to obtain an ideological equipment layout, and a mathematical model. The objectiveness is to minimize the total necessary distance traveled between machines. An improved control operator is implemented to improve the iterative efficiency of the genetic algorithm, and yield relevant parameters. The Computer Aided Tri-Dimensional Interface Application (CATIA) software is applied to establish the manufacturing resource base and parametric model of the steel processing workshop. Based on the results of optimized planar logistics, a visual parametric model of the steel processing workshop is constructed, and qualitative and quantitative adjustments then are applied to the model. The method for evaluating the results of the layout is subsequently established through the utilization of AHP. In order to provide a mode of reference to the optimization and layout of the digitalized production workshop, the optimized discrete production workshop will possess a certain level of practical significance.

  12. 77 FR 55896 - Notice of Release Effecting Federal Grant Assurance Obligations Due to Airport Layout Plan...

    Science.gov (United States)

    2012-09-11

    ... Administration (FAA) proposes to rule and invites public comment on the application for an Airport Layout Plan... following is a brief overview of the request: The County of Sacramento requested a modification to the... property were three parcels that did not serve an airport purpose. The three parcels are a wildlife...

  13. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...

  14. On the Impact of Diagram Layout: How Are Models Actually Read?

    DEFF Research Database (Denmark)

    Störrle, Harald; Baltsen, Nick; Christoffersen, Henrik

    2014-01-01

    This poster presents the latest results from a very large eye tracking study (n=29) that explores how modelers read UML diagrams. We find that various factors like layout quality, modeler experience, and diagram type lead to significant differences in diagram reading strategies. We derive element...

  15. Alternative Layouts for the Carbon Capture with the Chilled Ammonia Process

    DEFF Research Database (Denmark)

    Valenti, Gianluca; Bonalumi, Davide; Fosbøl, Philip Loldrup

    2013-01-01

    Many alternatives are being investigated for the carbon capture, but none appears to have been proved as the choice for full-scale applications. This work considers the Chilled Ammonia Process for coal-fired Ultra Super Critical power plants. Three layouts are simulated with Aspen Plus...

  16. Effect of Changes in Layout Shape on Unit Construction Cost of ...

    African Journals Online (AJOL)

    cost and overall project cost are affected by variation in plan shape narrowness and complexity (irregularity). These results will assist construction professionals, especially the cost consultants, in making more objective design decisions and in giving cost advice related to plan layout for the benefits of their clients. Samaru ...

  17. Scopes describe frames : A uniform model for memory layout in dynamic semantics

    NARCIS (Netherlands)

    Poulsen, C.B.; Neron, P.J.M.; Tolmach, Andrew; Visser, Eelco; Krishnamurthi, Shriram; Lerner, Benjamin S.

    2016-01-01

    Semantic specifications do not make a systematic connection between the names and scopes in the static structure of a program and memory layout, and access during its execution. In this paper we introduce a systematic approach to the alignment of names in static semantics and memory in dynamic

  18. On the Impact of Layout Quality to Understanding UML Diagrams: Diagram Type and Expertise

    DEFF Research Database (Denmark)

    Störrle, Harald

    2012-01-01

    . In the current paper, we expand on our earlier experiments by varying both diagram types and populations studied. We find no difference in the beneficial evidence of good layout wrt. diagram types. We also find support for the hypothesis that experts benefit less than novices. While still lacking independent...

  19. Design of a modular product architecture and a cellular manufacturing layout : A concurrent engineering approach

    NARCIS (Netherlands)

    Slomp, J; McGinnis, LF; Ahmad, MM; Sullivan, WG

    1996-01-01

    This paper formalizes the problem of a concurrent design of a modular product architecture and a cellular manufacturing layout and presents a way to deal with this design problem. First, the different types of a modular product architecture are explained as well as important implications of

  20. Interaction Between Shelf Layout and Marketing Effectiveness and Its Impact on Optimizing Shelf Arrangements

    NARCIS (Netherlands)

    van Nierop, Erjen; Fok, Dennis; Franses, Philip Hans

    2008-01-01

    In this paper, we propose and operationalize a new method for optimizing shelf arrangements. We show that there are important dependencies between the layout of the shelf and stock-keeping unit (SKU) sales and marketing effectiveness. The importance of these dependencies is further shown by the

  1. Visualization of the Evolution of Layout Metrics for Business Process Models

    DEFF Research Database (Denmark)

    Haisjackl, Cornelia; Burattin, Andrea; Soffer, Pnina

    2017-01-01

    Considerable progress regarding impact factors of process model understandability has been achieved. For example, it has been shown that layout features of process models have an effect on model understandability. Even so, it appears that our knowledge about the modeler’s behavior regarding the l...

  2. Mathematical models for the definition of cell manufacturing layout. Literature review

    Directory of Open Access Journals (Sweden)

    Gustavo Andrés Romero Duque

    2015-11-01

    Full Text Available This review article discusses the approach to the layout problem of cell manufacturing (LCM in a descriptive form; considering at first the problem and its variations, then the elements of the mathematical models, subsequently presenting solution methods used; and finally some future perspectives about this topic are considered.

  3. Effects of a Green Space Layout on the Outdoor Thermal Environment at the Neighborhood Level

    Directory of Open Access Journals (Sweden)

    Chi-Ming Lai

    2012-09-01

    Full Text Available This study attempted to address the existing urban design needs and computer-aided thermal engineering and explore the optimal green space layout to obtain an acceptable thermal environment at the neighborhood scale through a series of building energy and computational fluid dynamics (CFD simulations. The building-energy analysis software eQUEST and weather database TMY2 were adopted to analyze the electric energy consumed by air conditioners and the analysis results were incorporated to derive the heat dissipated from air conditioners. Then, the PHOENICS CFD software was used to analyze how the green space layout influences outdoor thermal environment based on the heat dissipated from air conditioners and the solar heat reemitted from the built surfaces. The results show that a green space located in the center of this investigated area and at the far side of the downstream of a summer monsoon is the recommended layout. The layouts, with green space in the center, can decrease the highest temperature by 0.36 °C.

  4. Determination of planning capacity and layout criteria of outdoor recreation projects

    NARCIS (Netherlands)

    Lier, van H.N.

    1973-01-01


    When meeting the increasing demand for outdoor recreation projects, problems arise concerning location, planning capacity and layout. A system has been developed to solve the two last mentioned problems. Special attention is paid to inland beaches in the Netherlands. To apply the system two

  5. Design of Web Questionnaires : The Effect of Layout in Rating Scales

    NARCIS (Netherlands)

    Toepoel, V.; Das, J.W.M.; van Soest, A.H.O.

    2006-01-01

    This article shows that respondents gain meaning from visual cues in a web survey as well as from verbal cues (words).We manipulated the layout of a five point rating scale using verbal, graphical, numerical, and symbolic language. This paper extends the existing literature in four directions: (1)

  6. Layout Design of Human-Machine Interaction Interface of Cabin Based on Cognitive Ergonomics and GA-ACA.

    Science.gov (United States)

    Deng, Li; Wang, Guohua; Yu, Suihuai

    2016-01-01

    In order to consider the psychological cognitive characteristics affecting operating comfort and realize the automatic layout design, cognitive ergonomics and GA-ACA (genetic algorithm and ant colony algorithm) were introduced into the layout design of human-machine interaction interface. First, from the perspective of cognitive psychology, according to the information processing process, the cognitive model of human-machine interaction interface was established. Then, the human cognitive characteristics were analyzed, and the layout principles of human-machine interaction interface were summarized as the constraints in layout design. Again, the expression form of fitness function, pheromone, and heuristic information for the layout optimization of cabin was studied. The layout design model of human-machine interaction interface was established based on GA-ACA. At last, a layout design system was developed based on this model. For validation, the human-machine interaction interface layout design of drilling rig control room was taken as an example, and the optimization result showed the feasibility and effectiveness of the proposed method.

  7. Automated DNA Sequencing System

    Energy Technology Data Exchange (ETDEWEB)

    Armstrong, G.A.; Ekkebus, C.P.; Hauser, L.J.; Kress, R.L.; Mural, R.J.

    1999-04-25

    Oak Ridge National Laboratory (ORNL) is developing a core DNA sequencing facility to support biological research endeavors at ORNL and to conduct basic sequencing automation research. This facility is novel because its development is based on existing standard biology laboratory equipment; thus, the development process is of interest to the many small laboratories trying to use automation to control costs and increase throughput. Before automation, biology Laboratory personnel purified DNA, completed cycle sequencing, and prepared 96-well sample plates with commercially available hardware designed specifically for each step in the process. Following purification and thermal cycling, an automated sequencing machine was used for the sequencing. A technician handled all movement of the 96-well sample plates between machines. To automate the process, ORNL is adding a CRS Robotics A- 465 arm, ABI 377 sequencing machine, automated centrifuge, automated refrigerator, and possibly an automated SpeedVac. The entire system will be integrated with one central controller that will direct each machine and the robot. The goal of this system is to completely automate the sequencing procedure from bacterial cell samples through ready-to-be-sequenced DNA and ultimately to completed sequence. The system will be flexible and will accommodate different chemistries than existing automated sequencing lines. The system will be expanded in the future to include colony picking and/or actual sequencing. This discrete event, DNA sequencing system will demonstrate that smaller sequencing labs can achieve cost-effective the laboratory grow.

  8. Large-scale analytical Fourier transform of photomask layouts using graphics processing units

    Science.gov (United States)

    Sakamoto, Julia A.

    2015-10-01

    Compensation of lens-heating effects during the exposure scan in an optical lithographic system requires knowledge of the heating profile in the pupil of the projection lens. A necessary component in the accurate estimation of this profile is the total integrated distribution of light, relying on the squared modulus of the Fourier transform (FT) of the photomask layout for individual process layers. Requiring a layout representation in pixelated image format, the most common approach is to compute the FT numerically via the fast Fourier transform (FFT). However, the file size for a standard 26- mm×33-mm mask with 5-nm pixels is an overwhelming 137 TB in single precision; the data importing process alone, prior to FFT computation, can render this method highly impractical. A more feasible solution is to handle layout data in a highly compact format with vertex locations of mask features (polygons), which correspond to elements in an integrated circuit, as well as pattern symmetries and repetitions (e.g., GDSII format). Provided the polygons can decompose into shapes for which analytical FT expressions are possible, the analytical approach dramatically reduces computation time and alleviates the burden of importing extensive mask data. Algorithms have been developed for importing and interpreting hierarchical layout data and computing the analytical FT on a graphics processing unit (GPU) for rapid parallel processing, not assuming incoherent imaging. Testing was performed on the active layer of a 392- μm×297-μm virtual chip test structure with 43 substructures distributed over six hierarchical levels. The factor of improvement in the analytical versus numerical approach for importing layout data, performing CPU-GPU memory transfers, and executing the FT on a single NVIDIA Tesla K20X GPU was 1.6×104, 4.9×103, and 3.8×103, respectively. Various ideas for algorithm enhancements will be discussed.

  9. Numerical simulation for estimating of sediment transport due layouts of port

    Science.gov (United States)

    Nengsih, Sri Hartuti; Fachrurrazi, Syamsidik, Kato, Shigeru

    2017-10-01

    The need for a new and improved fisheries port has significantly increased in the Bireuen District of Aceh, particularly in Peudada due to several factors presented in this paper. During this time the fishing port used by the communities located in the river channel makes it difficult for the fishermen to get into the port area due to the shallowness of the mouth of the estuary. Port master plan study is required to examine several possible locations for the proposed port. In planning the hydro-oceanographic aspects of the port is an essential requirement to determine the layout of a port. Several factors that need to be reviewed relating to the layout of the ports include sedimentation, waves, and currents. These factors affect the movement of the ship, tranquility waves in the port basin, and for the maintenance dredging of the harbor due to sedimentation. This study is aimed at estimating the best layout of the port basin between two scenarios due to the sedimentation process, waves propagation, and currents. The software used in this study is Delft3D developed by Deltares. The program can simulate waves, currents and sediment transport in coastal areas by using schematized grids. The simulation was performed under two scenarios port layout using three dominant wind direction influencing wave generation, i.e., Northwest, North, and Northeast. All two scenarios modeled by changing the direction of opening the mouth of the harbor. After one year, both scenarios simulation has created a new bathymetry map to select the best port layout based on smallest sedimentation volume.

  10. Performance criteria of the layout of the filling area of a petrol station

    Directory of Open Access Journals (Sweden)

    Maslennikov Valeriy Aleksandrovich

    2015-12-01

    Full Text Available The increasing traffic on the roads requires relevant technological planning, construction, reconstruction and re-equipment of the expanding network of filling stations. The basis for developing of these guidelines lies in the evolution of urban planning concepts and methods to determine the effective parameters of gas stations. This article describes various layout solutions of the fueling area of a station taking into account the main technical characteristics and regulatory requirements for the design, construction and operation of the station. Typical projects of one power station may be of various sizes, taking away residential areas under the land station changes depending on the layout and features host of technological equipment. Excessive area occupied by the service area leads to additional costs for construction, taxes, etc. For an overall evaluation of the effectiveness of the station operation, the paper proposed an integrated criterion of efficiency of layout solutions, considering both technical and economic indicators of the object functioning. In order to justify the effective layout fueling positions at the station the authors used a comparative analysis of the fueling areas and gas throughput for different number of zones and the method of placing fuel dispensers. According to the results of calculations the linear relationship was obtained between the number of columns and the size of the filling area of the station. As a critical metric in evaluating the effectiveness of various variants of layout solutions of a petrol station an assessment of its bandwidth we made. According to the results of calculations a single-row method of speaker placement on the station is more efficient than double-row or three-row ones.

  11. A multilevel layout algorithm for visualizing physical and genetic interaction networks, with emphasis on their modular organization.

    Science.gov (United States)

    Tuikkala, Johannes; Vähämaa, Heidi; Salmela, Pekka; Nevalainen, Olli S; Aittokallio, Tero

    2012-03-26

    Graph drawing is an integral part of many systems biology studies, enabling visual exploration and mining of large-scale biological networks. While a number of layout algorithms are available in popular network analysis platforms, such as Cytoscape, it remains poorly understood how well their solutions reflect the underlying biological processes that give rise to the network connectivity structure. Moreover, visualizations obtained using conventional layout algorithms, such as those based on the force-directed drawing approach, may become uninformative when applied to larger networks with dense or clustered connectivity structure. We implemented a modified layout plug-in, named Multilevel Layout, which applies the conventional layout algorithms within a multilevel optimization framework to better capture the hierarchical modularity of many biological networks. Using a wide variety of real life biological networks, we carried out a systematic evaluation of the method in comparison with other layout algorithms in Cytoscape. The multilevel approach provided both biologically relevant and visually pleasant layout solutions in most network types, hence complementing the layout options available in Cytoscape. In particular, it could improve drawing of large-scale networks of yeast genetic interactions and human physical interactions. In more general terms, the biological evaluation framework developed here enables one to assess the layout solutions from any existing or future graph drawing algorithm as well as to optimize their performance for a given network type or structure. By making use of the multilevel modular organization when visualizing biological networks, together with the biological evaluation of the layout solutions, one can generate convenient visualizations for many network biology applications.

  12. Automated stopcock actuator

    OpenAIRE

    Vandehey, N. T.; O\\'Neil, J. P.

    2015-01-01

    Introduction We have developed a low-cost stopcock valve actuator for radiochemistry automation built using a stepper motor and an Arduino, an open-source single-board microcontroller. The con-troller hardware can be programmed to run by serial communication or via two 5–24 V digital lines for simple integration into any automation control system. This valve actuator allows for automated use of a single, disposable stopcock, providing a number of advantages over stopcock manifold systems ...

  13. Laboratory Automation and Middleware.

    Science.gov (United States)

    Riben, Michael

    2015-06-01

    The practice of surgical pathology is under constant pressure to deliver the highest quality of service, reduce errors, increase throughput, and decrease turnaround time while at the same time dealing with an aging workforce, increasing financial constraints, and economic uncertainty. Although not able to implement total laboratory automation, great progress continues to be made in workstation automation in all areas of the pathology laboratory. This report highlights the benefits and challenges of pathology automation, reviews middleware and its use to facilitate automation, and reviews the progress so far in the anatomic pathology laboratory. Copyright © 2015 Elsevier Inc. All rights reserved.

  14. Complacency and Automation Bias in the Use of Imperfect Automation.

    Science.gov (United States)

    Wickens, Christopher D; Clegg, Benjamin A; Vieane, Alex Z; Sebok, Angelia L

    2015-08-01

    We examine the effects of two different kinds of decision-aiding automation errors on human-automation interaction (HAI), occurring at the first failure following repeated exposure to correctly functioning automation. The two errors are incorrect advice, triggering the automation bias, and missing advice, reflecting complacency. Contrasts between analogous automation errors in alerting systems, rather than decision aiding, have revealed that alerting false alarms are more problematic to HAI than alerting misses are. Prior research in decision aiding, although contrasting the two aiding errors (incorrect vs. missing), has confounded error expectancy. Participants performed an environmental process control simulation with and without decision aiding. For those with the aid, automation dependence was created through several trials of perfect aiding performance, and an unexpected automation error was then imposed in which automation was either gone (one group) or wrong (a second group). A control group received no automation support. The correct aid supported faster and more accurate diagnosis and lower workload. The aid failure degraded all three variables, but "automation wrong" had a much greater effect on accuracy, reflecting the automation bias, than did "automation gone," reflecting the impact of complacency. Some complacency was manifested for automation gone, by a longer latency and more modest reduction in accuracy. Automation wrong, creating the automation bias, appears to be a more problematic form of automation error than automation gone, reflecting complacency. Decision-aiding automation should indicate its lower degree of confidence in uncertain environments to avoid the automation bias. © 2015, Human Factors and Ergonomics Society.

  15. Optimization of signal-to-noise ratio for wireless light-emitting diode communication in modern lighting layouts

    Science.gov (United States)

    Azizan, Luqman A.; Ab-Rahman, Mohammad S.; Hassan, Mazen R.; Bakar, A. Ashrif A.; Nordin, Rosdiadee

    2014-04-01

    White light-emitting diodes (LEDs) are predicted to be widely used in domestic applications in the future, because they are becoming widespread in commercial lighting applications. The ability of LEDs to be modulated at high speeds offers the possibility of using them as sources for communication instead of illumination. The growing interest in using these devices for both illumination and communication requires attention to combine this technology with modern lighting layouts. A dual-function system is applied to three models of modern lighting layouts: the hybrid corner lighting layout (HCLL), the hybrid wall lighting layout (HWLL), and the hybrid edge lighting layout (HELL). Based on the analysis, the relationship between the space adversity and the signal-to-noise ratio (SNR) performance is demonstrated for each model. The key factor that affects the SNR performance of visible light communication is the reliance on the design parameter that is related to the number and position of LED lights. The model of HWLL is chosen as the best layout, since 61% of the office area is considered as an excellent communication area and the difference between the area classification, Δp, is 22%. Thus, this system is applicable to modern lighting layouts.

  16. Application of a concept development process to evaluate process layout designs using value stream mapping and simulation

    Directory of Open Access Journals (Sweden)

    Ki-Young Jeong

    2011-07-01

    Full Text Available Purpose: We propose and demonstrate a concept development process (CDP as a framework to solve a value stream mapping (VSM related process layout design optimization problem.Design/methodology/approach: A case study approach was used to demonstrate the effectiveness of CDP framework in a portable fire extinguisher manufacturing company. To facilitate the CDP application, we proposed the system coupling level index (SCLI and simulation to evaluate the process layout design concepts.Findings: As part of the CDP framework application, three process layout design concepts - current layout (CL, express lane layout (ELL and independent zone layout (IZL - were generated. Then, the SCLI excluded CL and simulation selected IZL as the best concept. The simulation was also applied to optimize the performance of IZL in terms of the number of pallets. Based on this case study, we concluded that CDP framework worked well.Research limitations/implications: The process layout design optimization issue has not been well addressed in the VSM literature. We believe that this paper initiated the relevant discussion by showing the feasibility of CDP as a framework in this issue.Practical implications: The CDP and SCLI are very practice-oriented approaches in the sense that they do not require any complex analytical knowledge.Originality/value: We discussed a not well-addressed issue with a systematic framework. In addition, the SCLI presented was also unique.

  17. Safety assessment in plant layout design using indexing approach: implementing inherent safety perspective. Part 1 - guideword applicability and method description.

    Science.gov (United States)

    Tugnoli, Alessandro; Khan, Faisal; Amyotte, Paul; Cozzani, Valerio

    2008-12-15

    Layout planning plays a key role in the inherent safety performance of process plants since this design feature controls the possibility of accidental chain-events and the magnitude of possible consequences. A lack of suitable methods to promote the effective implementation of inherent safety in layout design calls for the development of new techniques and methods. In the present paper, a safety assessment approach suitable for layout design in the critical early phase is proposed. The concept of inherent safety is implemented within this safety assessment; the approach is based on an integrated assessment of inherent safety guideword applicability within the constraints typically present in layout design. Application of these guidewords is evaluated along with unit hazards and control devices to quantitatively map the safety performance of different layout options. Moreover, the economic aspects related to safety and inherent safety are evaluated by the method. Specific sub-indices are developed within the integrated safety assessment system to analyze and quantify the hazard related to domino effects. The proposed approach is quick in application, auditable and shares a common framework applicable in other phases of the design lifecycle (e.g. process design). The present work is divided in two parts: Part 1 (current paper) presents the application of inherent safety guidelines in layout design and the index method for safety assessment; Part 2 (accompanying paper) describes the domino hazard sub-index and demonstrates the proposed approach with a case study, thus evidencing the introduction of inherent safety features in layout design.

  18. The Effect of Design Modifications to the Typographical Layout of the New York State Elementary Science Learning Standards on User Preference and Process Time

    Science.gov (United States)

    Arnold, Jeffery E.

    2010-01-01

    The purpose of this study was to determine the effect of four different design layouts of the New York State elementary science learning standards on user processing time and preference. Three newly developed layouts contained the same information as the standards core curriculum. In this study, the layout of the core guide is referred to as Book.…

  19. Automation in Warehouse Development

    NARCIS (Netherlands)

    Hamberg, R.; Verriet, J.

    2012-01-01

    The warehouses of the future will come in a variety of forms, but with a few common ingredients. Firstly, human operational handling of items in warehouses is increasingly being replaced by automated item handling. Extended warehouse automation counteracts the scarcity of human operators and

  20. Library Automation in Pakistan.

    Science.gov (United States)

    Haider, Syed Jalaluddin

    1998-01-01

    Examines the state of library automation in Pakistan. Discusses early developments; financial support by the Netherlands Library Development Project (Pakistan); lack of automated systems in college/university and public libraries; usage by specialist libraries; efforts by private-sector libraries and the National Library in Pakistan; commonly used…