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Sample records for vlsi layout automation

  1. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  2. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  3. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  4. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  5. Automated Layout Generation of Analogue and Mixed-Signal ASIC's

    DEFF Research Database (Denmark)

    Bloch, Rene

    search for better solutions can be guided into new and more prosperous areas of the search space. This feature also provides the designer with the ability to easily try out several implementation options, thus exploring the solution space, which are especially important in the early stages of the design...... is generated using a full-custom layout style and is based on a library of CMOS process independent device generators. The placement for the analogue circuit is derived using the interactive floorplan optimization algorithm described above. This ensures that a high degree of user control is implemented...

  6. An algorithm for automated layout of process description maps drawn in SBGN.

    Science.gov (United States)

    Genc, Begum; Dogrusoz, Ugur

    2016-01-01

    Evolving technology has increased the focus on genomics. The combination of today's advanced techniques with decades of molecular biology research has yielded huge amounts of pathway data. A standard, named the Systems Biology Graphical Notation (SBGN), was recently introduced to allow scientists to represent biological pathways in an unambiguous, easy-to-understand and efficient manner. Although there are a number of automated layout algorithms for various types of biological networks, currently none specialize on process description (PD) maps as defined by SBGN. We propose a new automated layout algorithm for PD maps drawn in SBGN. Our algorithm is based on a force-directed automated layout algorithm called Compound Spring Embedder (CoSE). On top of the existing force scheme, additional heuristics employing new types of forces and movement rules are defined to address SBGN-specific rules. Our algorithm is the only automatic layout algorithm that properly addresses all SBGN rules for drawing PD maps, including placement of substrates and products of process nodes on opposite sides, compact tiling of members of molecular complexes and extensively making use of nested structures (compound nodes) to properly draw cellular locations and molecular complex structures. As demonstrated experimentally, the algorithm results in significant improvements over use of a generic layout algorithm such as CoSE in addressing SBGN rules on top of commonly accepted graph drawing criteria. An implementation of our algorithm in Java is available within ChiLay library (https://github.com/iVis-at-Bilkent/chilay). ugur@cs.bilkent.edu.tr or dogrusoz@cbio.mskcc.org Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press.

  7. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  8. Layout Construction

    DEFF Research Database (Denmark)

    Frandsen, Gudmund Skovbjerg; Palsberg, Jens; Schmidt, Erik Meineche

    We design a system for generating newspaper layout proposals. The input to the system consists of editorial information (text, pictures, etc) and style information (non-editorial information that specifies the aesthetic appearance of a layout). We consider the automation of layout construction...... to pose two main problems. One problem consists in optimizing the layout with respect to the constraints and preferences specified in the style information. Another problem consists in finding a representation of the style information that both supports its use in the combinatorial optimization...

  9. A Tool for the Automated Design and Evaluation of Habitat Interior Layouts

    Science.gov (United States)

    Simon, Matthew A.; Wilhite, Alan W.

    2013-01-01

    The objective of space habitat design is to minimize mass and system size while providing adequate space for all necessary equipment and a functional layout that supports crew health and productivity. Unfortunately, development and evaluation of interior layouts is often ignored during conceptual design because of the subjectivity and long times required using current evaluation methods (e.g., human-in-the-loop mockup tests and in-depth CAD evaluations). Early, more objective assessment could prevent expensive design changes that may increase vehicle mass and compromise functionality. This paper describes a new interior design evaluation method to enable early, structured consideration of habitat interior layouts. This interior layout evaluation method features a comprehensive list of quantifiable habitat layout evaluation criteria, automatic methods to measure these criteria from a geometry model, and application of systems engineering tools and numerical methods to construct a multi-objective value function measuring the overall habitat layout performance. In addition to a detailed description of this method, a C++/OpenGL software tool which has been developed to implement this method is also discussed. This tool leverages geometry modeling coupled with collision detection techniques to identify favorable layouts subject to multiple constraints and objectives (e.g., minimize mass, maximize contiguous habitable volume, maximize task performance, and minimize crew safety risks). Finally, a few habitat layout evaluation examples are described to demonstrate the effectiveness of this method and tool to influence habitat design.

  10. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  11. Optimal Stack Layout in a Sea Container Terminal with Automated Lifting Vehicles

    OpenAIRE

    Roy, D.; Gupta, A.; Parhi, S.; de Koster, M.B.M.

    2014-01-01

    textabstractContainer terminal performance is largely determined by its design decisions, which include the number and type of quay cranes (QCs), stack cranes (SCs), transport vehicles, vehicle travel path, and stack layout. The terminal design process is complex because it is affected by factors such as topological constraints, stochastic interactions among the quayside, vehicle transport and stackside operations. Further, the orientation of the stack layout (parallel or perpendicular to the...

  12. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  13. Optimal Stack Layout in a Sea Container Terminal with Automated Lifting Vehicles

    NARCIS (Netherlands)

    D. Roy (Debjit); A. Gupta (Akash); S. Parhi (Sampanna); M.B.M. de Koster (René)

    2014-01-01

    textabstractContainer terminal performance is largely determined by its design decisions, which include the number and type of quay cranes (QCs), stack cranes (SCs), transport vehicles, vehicle travel path, and stack layout. The terminal design process is complex because it is affected by factors

  14. Area-Efficient Graph Layouts (for VLSI).

    Science.gov (United States)

    1980-08-13

    thle short side, then no rectangle is ew r generated x’.ho se aspect r~itho i s \\orse di ai aJ. ’I lie d i % ide-I mid -cimq tier clInt ruolIn in... Sutherland and Donald Oestrcichcr, "flow big should a printed circuit board be?," ILEEE, Transactions on Computers, Vol. C-22, May 1973, pp. 537-542. 22

  15. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  16. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  17. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  18. Applying machine learning to pattern analysis for automated in-design layout optimization

    Science.gov (United States)

    Cain, Jason P.; Fakhry, Moutaz; Pathak, Piyush; Sweis, Jason; Gennari, Frank; Lai, Ya-Chieh

    2018-04-01

    Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk are then mapped to functionally equivalent patterns with lower risk. The higher risk patterns are then replaced in the design with their lower risk equivalents. The pattern selection and replacement is fully automated and suitable for use for full-chip designs. Results from 14nm product designs show that the approach can identify and replace risk patterns with quantifiable positive impact on the risk score distribution after replacement.

  19. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  20. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  1. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  2. Parallel VLSI Architecture

    Science.gov (United States)

    Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

    1985-01-01

    Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

  3. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  4. DPL/Daedalus design environment (for VLSI)

    Energy Technology Data Exchange (ETDEWEB)

    Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

    1981-01-01

    The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

  5. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  6. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  7. Course Layout

    OpenAIRE

    2005-01-01

    present roll Presentation roll Interactive Media Element This is an interactive diagram of a MATLAB course layout covering 16 topics in 4 different main areas: Basics of MATLAB, Numerical Methods in MATLAB, Symbolic Manipulations in MATLAB, Mathematical Modeling in MATLAB and Simulink AE2440 Introduction to Digital Computation

  8. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  9. Synthesis algorithm of VLSI multipliers for ASIC

    Science.gov (United States)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  10. Nano lasers in photonic VLSI

    NARCIS (Netherlands)

    Hill, M.T.; Oei, Y.S.; Smit, M.K.

    2007-01-01

    We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

  11. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  12. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  13. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  14. Facade Layout Symmetrization

    KAUST Repository

    Jiang, Haiyong

    2016-04-11

    We present an automatic algorithm for symmetrizing facade layouts. Our method symmetrizes a given facade layout while minimally modifying the original layout. Based on the principles of symmetry in urban design, we formulate the problem of facade layout symmetrization as an optimization problem. Our system further enhances the regularity of the final layout by redistributing and aligning boxes in the layout. We demonstrate that the proposed solution can generate symmetric facade layouts efficiently. © 2015 IEEE.

  15. Symmetrization of Facade Layouts

    KAUST Repository

    Jiang, Haiyong; Yan, Dong-Ming; Dong, Weiming; Wu, Fuzhang; Nan, Liangliang; Zhang, Xiaopeng

    2016-01-01

    We present an automatic approach for symmetrizing urban facade layouts. Our method can generate a symmetric layout through minimally modifying the original input layout. Based on the principles of symmetry in urban design, we formulate facade layout symmetrization as an optimization problem. Our method further enhances the regularity of the final layout by redistributing and aligning elements in the layout. We demonstrate that the proposed solution can effectively generate symmetric facade layouts.

  16. Facade Layout Symmetrization

    KAUST Repository

    Jiang, Haiyong; Dong, Weiming; Yan, Dongming; Zhang, Xiaopeng

    2016-01-01

    We present an automatic algorithm for symmetrizing facade layouts. Our method symmetrizes a given facade layout while minimally modifying the original layout. Based on the principles of symmetry in urban design, we formulate the problem of facade layout symmetrization as an optimization problem. Our system further enhances the regularity of the final layout by redistributing and aligning boxes in the layout. We demonstrate that the proposed solution can generate symmetric facade layouts efficiently. © 2015 IEEE.

  17. Symmetrization of Facade Layouts

    KAUST Repository

    Jiang, Haiyong

    2016-02-26

    We present an automatic approach for symmetrizing urban facade layouts. Our method can generate a symmetric layout through minimally modifying the original input layout. Based on the principles of symmetry in urban design, we formulate facade layout symmetrization as an optimization problem. Our method further enhances the regularity of the final layout by redistributing and aligning elements in the layout. We demonstrate that the proposed solution can effectively generate symmetric facade layouts.

  18. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  19. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  20. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  1. Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

    Science.gov (United States)

    Makhijani, Vinod B.; Przekwas, Andrzej J.

    2002-10-01

    This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

  2. Underground Layout Configuration

    International Nuclear Information System (INIS)

    A. Linden

    2003-01-01

    The purpose of this analysis was to develop an underground layout to support the license application (LA) design effort. In addition, the analysis will be used as the technical basis for the underground layout general arrangement drawings

  3. VLSI structures for track finding

    International Nuclear Information System (INIS)

    Dell'Orso, M.

    1989-01-01

    We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

  4. The test of VLSI circuits

    Science.gov (United States)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  5. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  6. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  7. Reconfigurable layout problem

    NARCIS (Netherlands)

    Meng, G.; Heragu, S.S.; Heragu, S.S.; Zijm, Willem H.M.

    2004-01-01

    This paper addresses the reconfigurable layout problem, which differs from traditional, robust and dynamic layout problems mainly in two aspects: first, it assumes that production data are available only for the current and upcoming production period. Second, it considers queuing performance

  8. Analysis on flexible manufacturing system layout using arena simulation software

    Science.gov (United States)

    Fadzly, M. K.; Saad, Mohd Sazli; Shayfull, Z.

    2017-09-01

    Flexible manufacturing system (FMS) was defined as highly automated group technology machine cell, consisting of a group of processing stations interconnected by an automated material handling and storage system, and controlled by an integrated computer system. FMS can produce parts or products are in the mid-volume, mid-variety production range. The layout system in FMS is an important criterion to design the FMS system to produce a part or product. This facility layout of an FMS involves the positioning of cells within given boundaries, so as to minimize the total projected travel time between cells. Defining the layout includes specifying the spatial coordinates of each cell, its orientation in either a horizontal or vertical position, and the location of its load or unloads point. There are many types of FMS layout such as In-line, loop ladder and robot centered cell layout. The research is concentrating on the design and optimization FMS layout. The final conclusion can be summarized that the objective to design and optimisation of FMS layout for this study is successful because the FMS In-line layout is the best layout based on effective time and cost using ARENA simulation software.

  9. Fast-prototyping of VLSI

    International Nuclear Information System (INIS)

    Saucier, G.; Read, E.

    1987-01-01

    Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

  10. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  11. Lithography requirements in complex VLSI device fabrication

    International Nuclear Information System (INIS)

    Wilson, A.D.

    1985-01-01

    Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

  12. A Knowledge Based Approach to VLSI CAD

    Science.gov (United States)

    1983-09-01

    Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

  13. Electro-optic techniques for VLSI interconnect

    Science.gov (United States)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  14. Site Recommendation Subsurface Layout

    International Nuclear Information System (INIS)

    C.L. Linden

    2000-01-01

    The purpose of this analysis is to develop a Subsurface Facility layout that is capable of accommodating the statutory capacity of 70,000 metric tons of uranium (MTU), as well as an option to expand the inventory capacity, if authorized, to 97,000 MTU. The layout configuration also requires a degree of flexibility to accommodate potential changes in site conditions or program requirements. The objective of this analysis is to provide a conceptual design of the Subsurface Facility sufficient to support the development of the Subsurface Facility System Description Document (CRWMS M andO 2000e) and the ''Emplacement Drift System Description Document'' (CRWMS M andO 2000i). As well, this analysis provides input to the Site Recommendation Consideration Report. The scope of this analysis includes: (1) Evaluation of the existing facilities and their integration into the Subsurface Facility design. (2) Identification and incorporation of factors influencing Subsurface Facility design, such as geological constraints, thermal loading, constructibility, subsurface ventilation, drainage control, radiological considerations, and the Test and Evaluation Facilities. (3) Development of a layout showing an available area in the primary area sufficient to support both the waste inventories and individual layouts showing the emplacement area required for 70,000 MTU and, if authorized, 97,000 MTU

  15. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  16. Parallel computation of nondeterministic algorithms in VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Hortensius, P D

    1987-01-01

    This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

  17. Heavy ion tests on programmable VLSI

    International Nuclear Information System (INIS)

    Provost-Grellier, A.

    1989-11-01

    The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

  18. Applications of VLSI circuits to medical imaging

    International Nuclear Information System (INIS)

    O'Donnell, M.

    1988-01-01

    In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

  19. Electrostatic Levitator Layout

    Science.gov (United States)

    1998-01-01

    Electrostatic Levitator (ESL) general layout with captions. The ESL uses static electricity to suspend an object (about 2-3 mm in diameter) inside a vacuum chamber while a laser heats the sample until it melts. This lets scientists record a wide range of physical properties without the sample contacting the container or any instruments, conditions that would alter the readings. The Electrostatic Levitator is one of several tools used in NASA's microgravity materials science program.

  20. Layout of LHCb

    CERN Multimedia

    CERN AC

    1998-01-01

    This diagram shows the layout for the LHCb detector, which will be part of the LHC project at CERN. The main purpose of this detector is to look for rare decays of a heavy quark known as 'bottom', a version of the down quark that is found in protons and neutrons. In particular, decays by a process known as 'CP violation' will be studied to investigate Nature's preference for matter over antimatter.

  1. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  2. Structure completion for facade layouts

    KAUST Repository

    Fan, Lubin

    2014-11-18

    (Figure Presented) We present a method to complete missing structures in facade layouts. Starting from an abstraction of the partially observed layout as a set of shapes, we can propose one or multiple possible completed layouts. Structure completion with large missing parts is an ill-posed problem. Therefore, we combine two sources of information to derive our solution: the observed shapes and a database of complete layouts. The problem is also very difficult, because shape positions and attributes have to be estimated jointly. Our proposed solution is to break the problem into two components: a statistical model to evaluate layouts and a planning algorithm to generate candidate layouts. This ensures that the completed result is consistent with the observation and the layouts in the database.

  3. An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

    Science.gov (United States)

    Corliss, Walter F., II

    1989-03-01

    The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

  4. Supporting the design of office layout meeting ergonomics requirements.

    Science.gov (United States)

    Margaritis, Spyros; Marmaras, Nicolas

    2007-11-01

    This paper proposes a method and an information technology tool aiming to support the ergonomics layout design of individual workstations in a given space (building). The proposed method shares common ideas with previous generic methods for office layout. However, it goes a step forward and focuses on the cognitive tasks which have to be carried out by the designer or the design team trying to alleviate them. This is achieved in two ways: (i) by decomposing the layout design problem to six main stages, during which only a limited number of variables and requirements are considered and (ii) by converting the ergonomics requirements to functional design guidelines. The information technology tool (ErgoOffice 0.1) automates certain phases of the layout design process, and supports the design team either by its editing and graphical facilities or by providing adequate memory support.

  5. Auditory Spatial Layout

    Science.gov (United States)

    Wightman, Frederic L.; Jenison, Rick

    1995-01-01

    All auditory sensory information is packaged in a pair of acoustical pressure waveforms, one at each ear. While there is obvious structure in these waveforms, that structure (temporal and spectral patterns) bears no simple relationship to the structure of the environmental objects that produced them. The properties of auditory objects and their layout in space must be derived completely from higher level processing of the peripheral input. This chapter begins with a discussion of the peculiarities of acoustical stimuli and how they are received by the human auditory system. A distinction is made between the ambient sound field and the effective stimulus to differentiate the perceptual distinctions among various simple classes of sound sources (ambient field) from the known perceptual consequences of the linear transformations of the sound wave from source to receiver (effective stimulus). Next, the definition of an auditory object is dealt with, specifically the question of how the various components of a sound stream become segregated into distinct auditory objects. The remainder of the chapter focuses on issues related to the spatial layout of auditory objects, both stationary and moving.

  6. Layout and composition for animation

    CERN Document Server

    Ghertner, Ed

    2012-01-01

    This essential, hands-on guide is filled with examples of what a composition should look like and example of poorly designed layouts. Spot potential problems before they cost time and money, and adapt creative solutions for your own projects with this invaluable resource for beginner and intermediate artists.  With Beauty and the Beast examples and Simpson character layouts, readers will learn how to develop character layout and background layout as well as strengthen composition  styles with a creative toolset of trick shot examples and inspirational case studies. A companion website will

  7. Optimization of a furniture factory layout

    Directory of Open Access Journals (Sweden)

    Tadej Kanduč

    2015-03-01

    Full Text Available This paper deals with the problem of optimizing a factory floor layout in a Slovenian furniture factory. First, the current state of the manufacturing system is analyzed by constructing a discrete event simulation (DES model that reflects the manufacturing processes. The company produces over 10,000 different products, and their manufacturing processes include approximately 30,000 subprocesses. Therefore, manually constructing a model to include every subprocess is not feasible. To overcome this problem, a method for automated model construction was developed to construct a DES model based on a selection of manufacturing orders and relevant subprocesses. The obtained simulation model provided insight into the manufacturing processes and enable easy modification of model parameters for optimizing the manufacturing processes. Finally, the optimization problem was solved: the total distance the products had to traverse between machines was minimized by devising an optimal machine layout. With the introduction of certain simplifications, the problem was best described as a quadratic assignment problem. A novel heuristic method based on force-directed graph drawing algorithms was developed. Optimizing the floor layout resulted in a significant reduction of total travel distance for the products.

  8. Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2017-06-01

    Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

  9. The EPR layout design

    International Nuclear Information System (INIS)

    Mast, U.; Le Carrer, P.Y.

    2001-01-01

    General: The European Pressurised Water Reactor (EPR) is a French - German development for the next generation of Pressurised Water Reactor. The new reactor design is based on the experiences of operation and design of nuclear power plants in both countries. The EPR fulfils enhanced safety standards, higher availability and a longer service life. Utilities aspects: For the Utilities one important requirement is the reduction of personnel exposure during maintenance and in-service inspection. The other significant requirement is of economic nature. The main points influencing costs, which have also impact on the layout, are: outage times, accessibility of the reactor building and the available maintenance and set down areas. The Utilities have also required to load the spent fuel assemblies into the shipping cask from the bottom of the fuel pool, because of the exclusion of the drop of the cask and in order to avoid contamination at the outer cask shell. Layout and safety aspects: All safety relevant Nuclear Island (NI) buildings are designed against design earthquake as well as explosion pressure wave. The protection against Airplane Crash (APC) is realised by civil and layout dispositions. The Reactor Building, the Safeguard Buildings division 2 and 3 and the Fuel Building are protected by concrete structures. The other safety relevant nuclear buildings are protected by geographical separation. Important safety requirements are the further reduction of the probability of severe accidents and the mitigation of such an accident on the plant area. For that, a spreading area for molten corium, a channel from the reactor pit to the spreading area and the In Containment Refuelling Water Storage Tank (IRWST) for flooding and initial cooling of the corium, were implemented in the design of the Reactor Building. Layout results: The following buildings are arranged on a common raft to protect them against design earthquake: Reactor Building (RB), Safeguard Buildings (SAB

  10. Underground layout tradeoff study

    International Nuclear Information System (INIS)

    1988-01-01

    This report presents the results of a technical and economic comparative study of four alternative underground layouts for a nuclear waste geologic repository in salt. The four alternatives considered in this study are (1) separate areas for spent fuel (SF) and commercial high-level waste (CHLW); (2) panel alternation, in which SF and CHLW are emplaced in adjacent panels of rooms; (3) room alternation, in which SF and CHLW are emplaced in adjacent rooms within each panel; and (4) intimate mixture, in which SF and CHLW are emplaced in random order within each storage room. The study concludes that (1) cost is not an important factor; (2) the separate-areas and intimate-mixture alternatives appear, technically, to be more desirable than the other alternatives; and (3) the selection between the separate-areas and intimate mixture alternatives depends upon future resolution of site-specific and reprocessing questions. 5 refs., 6 figs., 12 tabs

  11. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  12. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  13. Wavelength-encoded OCDMA system using opto-VLSI processors

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  14. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  15. Computing layouts with deformable templates

    KAUST Repository

    Peng, Chi-Han

    2014-07-22

    In this paper, we tackle the problem of tiling a domain with a set of deformable templates. A valid solution to this problem completely covers the domain with templates such that the templates do not overlap. We generalize existing specialized solutions and formulate a general layout problem by modeling important constraints and admissible template deformations. Our main idea is to break the layout algorithm into two steps: a discrete step to lay out the approximate template positions and a continuous step to refine the template shapes. Our approach is suitable for a large class of applications, including floorplans, urban layouts, and arts and design. Copyright © ACM.

  16. Computing layouts with deformable templates

    KAUST Repository

    Peng, Chi-Han; Yang, Yongliang; Wonka, Peter

    2014-01-01

    In this paper, we tackle the problem of tiling a domain with a set of deformable templates. A valid solution to this problem completely covers the domain with templates such that the templates do not overlap. We generalize existing specialized solutions and formulate a general layout problem by modeling important constraints and admissible template deformations. Our main idea is to break the layout algorithm into two steps: a discrete step to lay out the approximate template positions and a continuous step to refine the template shapes. Our approach is suitable for a large class of applications, including floorplans, urban layouts, and arts and design. Copyright © ACM.

  17. Practical Aspects of CMOS Layout

    DEFF Research Database (Denmark)

    Stassen, Flemming

    1996-01-01

    The topics covered in these notes are the practical aspects and limitations of layout, when random process variations result in electrical parameters, which are not constant but rather statistically distributed.The focus is on design methods for reducing or eliminating the effects. The notes cover...... three aspects:1) to introduce layout structures robust to process variations2) to present simplistic models for analog building blocks with the aim of analysing consequences of parameter variations3) to present the basic noise considerations which guide the layout of supply structures etc....

  18. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  19. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  20. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  1. VLSI Design of Trusted Virtual Sensors.

    Science.gov (United States)

    Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

    2018-01-25

    This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

  2. Structure completion for facade layouts

    KAUST Repository

    Fan, Lubin; Musialski, Przemyslaw; Liu, Ligang; Wonka, Peter

    2014-01-01

    completion with large missing parts is an ill-posed problem. Therefore, we combine two sources of information to derive our solution: the observed shapes and a database of complete layouts. The problem is also very difficult, because shape positions

  3. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    National Research Council Canada - National Science Library

    Horiuchi, Timothy K; Krishnaprasad, P. S

    2007-01-01

    .... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

  4. Preliminary Design Through Graphs: A Tool for Automatic Layout Distribution

    Directory of Open Access Journals (Sweden)

    Carlo Biagini

    2015-02-01

    Full Text Available Diagrams are essential in the preliminary stages of design for understanding distributive aspects and assisting the decision-making process. By drawing a schematic graph, designers can visualize in a synthetic way the relationships between many aspects: functions and spaces, distribution of layouts, space adjacency, influence of traffic flows within a facility layout, and so on. This process can be automated through the use of modern Information and Communication Technologies tools (ICT that allow the designers to manage a large quantity of information. The work that we will present is part of an on-going research project into how modern parametric software influences decision-making on the basis of automatic and optimized layout distribution. The method involves two phases: the first aims to define the ontological relation between spaces, with particular reference to a specific building typology (rules of aggregation of spaces; the second entails the implementation of these rules through the use of specialist software. The generation of ontological relations begins with the collection of data from historical manuals and analyses of case studies. These analyses aim to generate a “relationship matrix” based on preferences of space adjacency. The phase of implementing the previously defined rules is based on the use of Grasshopper to analyse and visualize different layout configurations. The layout is generated by simulating a process involving the collision of spheres, which represents specific functions of the design program. The spheres are attracted or rejected as a function of the relationships matrix, as defined above. The layout thus obtained will remain in a sort of abstract state independent of information about the exterior form, but will still provide a useful tool for the decision-making process. In addition, preliminary results gathered through the analysis of case studies will be presented. These results provide a good variety

  5. Accelerating ROP detector layout optimization

    International Nuclear Information System (INIS)

    Kastanya, D.; Fodor, B.

    2012-01-01

    The ADORE (Alternating Detector layout Optimization for REgional overpower protection system) algorithm for performing the optimization of regional overpower protection (ROP) system for CANDU® reactors have been recently developed. The simulated annealing (SA) stochastic optimization technique is utilized to come up with a quasi optimized detector layout for the ROP systems. Within each simulated annealing history, the objective function is calculated as a function of the trip set point (TSP) corresponding to the detector layout for that particular history. The evaluation of the TSP is done probabilistically using the ROVER-F code. Since during each optimization execution thousands of candidate detector layouts are evaluated, the overall optimization process is time consuming. Since for each ROVER-F evaluation the number of fuelling ripples controls the execution time, reducing the number of fuelling ripples used during the calculation of TSP will reduce the overall optimization execution time. This approach has been investigated and the results are presented in this paper. The challenge is to construct a set of representative fuelling ripples which will significantly speedup the optimization process while guaranteeing that the resulting detector layout has similar quality to the ones produced when the complete set of fuelling ripples is employed. Results presented in this paper indicate that a speedup of up to around 40 times is attainable when this approach is utilized. (author)

  6. Global floor planning approach for VLSI design

    International Nuclear Information System (INIS)

    LaPotin, D.P.

    1986-01-01

    Within a hierarchical design environment, initial decisions regarding the partitioning and choice of module attributes greatly impact the quality of the resulting IC in terms of area and electrical performance. This dissertation presents a global floor-planning approach which allows designers to quickly explore layout issues during the initial stages of the IC design process. In contrast to previous efforts, which address the floor-planning problem from a strict module placement point of view, this approach considers floor-planning from an area planning point of view. The approach is based upon a combined min-cut and slicing paradigm, which ensures routability. To provide flexibility, modules may be specified as having a number of possible dimensions and orientations, and I/O pads as well as layout constraints are considered. A slicing-tree representation is employed, upon which a sequence of traversal operations are applied in order to obtain an area efficient layout. An in-place partitioning technique, which provides an improvement over previous min-cut and slicing-based efforts, is discussed. Global routing and module I/O pin assignment are provided for floor-plan evaluation purposes. A computer program, called Mason, has been developed which efficiently implements the approach and provides an interactive environment for designers to perform floor-planning. Performance of this program is illustrated via several industrial examples

  7. An electron undulating ring for VLSI lithography

    International Nuclear Information System (INIS)

    Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

    1985-01-01

    The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

  8. Convolving optically addressed VLSI liquid crystal SLM

    Science.gov (United States)

    Jared, David A.; Stirk, Charles W.

    1994-03-01

    We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

  9. Multi-valued LSI/VLSI logic design

    Science.gov (United States)

    Santrakul, K.

    A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

  10. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  11. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  12. Design automation, languages, and simulations

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume covers a broad range of topics relevant to design automation, languages, and simulations. These include a collaborative framework that coordinates distributed design activities through the Internet, an overview of the Verilog hardware description language and its use in a design environment, hardware/software co-design, syst

  13. Cache-Oblivious Mesh Layouts

    International Nuclear Information System (INIS)

    Yoon, S; Lindstrom, P; Pascucci, V; Manocha, D

    2005-01-01

    We present a novel method for computing cache-oblivious layouts of large meshes that improve the performance of interactive visualization and geometric processing algorithms. Given that the mesh is accessed in a reasonably coherent manner, we assume no particular data access patterns or cache parameters of the memory hierarchy involved in the computation. Furthermore, our formulation extends directly to computing layouts of multi-resolution and bounding volume hierarchies of large meshes. We develop a simple and practical cache-oblivious metric for estimating cache misses. Computing a coherent mesh layout is reduced to a combinatorial optimization problem. We designed and implemented an out-of-core multilevel minimization algorithm and tested its performance on unstructured meshes composed of tens to hundreds of millions of triangles. Our layouts can significantly reduce the number of cache misses. We have observed 2-20 times speedups in view-dependent rendering, collision detection, and isocontour extraction without any modification of the algorithms or runtime applications

  14. Simulated annealing and circuit layout

    NARCIS (Netherlands)

    Aarts, E.H.L.; Laarhoven, van P.J.M.

    1991-01-01

    We discuss the problem of approximately sotvlng circuit layout problems by simulated annealing. For this we first summarize the theoretical concepts of the simulated annealing algorithm using Ihe theory of homogeneous and inhomogeneous Markov chains. Next we briefly review general aspects of the

  15. Small Business Location and Layout.

    Science.gov (United States)

    Small Business Administration, Washington, DC.

    As an approach to teaching small-business location and layout, this publication contains material for teaching one session of a basic course. The sections of the publication are as follows: (1) The Lesson Plan--an outline of the material covered, which may be used as a teaching guide, presented in two columns: an outline of the presentation, and a…

  16. High performance VLSI telemetry data systems

    Science.gov (United States)

    Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

    1990-01-01

    NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

  17. Generating and exploring good building layouts

    KAUST Repository

    Bao, Fan; Yan, Dongming; Mitra, Niloy J.; Wonka, Peter

    2013-01-01

    Good building layouts are required to conform to regulatory guidelines, while meeting certain quality measures. While different methods can sample the space of such good layouts, there exists little support for a user to understand

  18. Patch layout generation by detecting feature networks

    KAUST Repository

    Cao, Yuanhao; Yan, Dongming; Wonka, Peter

    2015-01-01

    The patch layout of 3D surfaces reveals the high-level geometric and topological structures. In this paper, we study the patch layout computation by detecting and enclosing feature loops on surfaces. We present a hybrid framework which combines

  19. HOLA: Human-like Orthogonal Network Layout.

    Science.gov (United States)

    Kieffer, Steve; Dwyer, Tim; Marriott, Kim; Wybrow, Michael

    2016-01-01

    Over the last 50 years a wide variety of automatic network layout algorithms have been developed. Some are fast heuristic techniques suitable for networks with hundreds of thousands of nodes while others are multi-stage frameworks for higher-quality layout of smaller networks. However, despite decades of research currently no algorithm produces layout of comparable quality to that of a human. We give a new "human-centred" methodology for automatic network layout algorithm design that is intended to overcome this deficiency. User studies are first used to identify the aesthetic criteria algorithms should encode, then an algorithm is developed that is informed by these criteria and finally, a follow-up study evaluates the algorithm output. We have used this new methodology to develop an automatic orthogonal network layout method, HOLA, that achieves measurably better (by user study) layout than the best available orthogonal layout algorithm and which produces layouts of comparable quality to those produced by hand.

  20. COMPUTER AIDED SELECTION OF PLANT LAYOUT

    African Journals Online (AJOL)

    Special focus is directed at improving the preparation of the input data to enhance computer assistance to plant layout. ... INTRODUCTION. Plant layout problems have ... 1960's with the development by industrial engineers and operational ...

  1. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  2. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  3. Numerical analysis of electromigration in thin film VLSI interconnections

    NARCIS (Netherlands)

    Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

    1995-01-01

    Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

  4. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  5. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  6. Computational Design of Urban Layouts

    KAUST Repository

    Wonka, Peter

    2015-10-07

    A fundamental challenge in computational design is to compute layouts by arranging a set of shapes. In this talk I will present recent urban modeling projects with applications in computer graphics, urban planning, and architecture. The talk will look at different scales of urban modeling (streets, floorplans, parcels). A common challenge in all these modeling problems are functional and aesthetic constraints that should be respected. The talk also highlights interesting links to geometry processing problems, such as field design and quad meshing.

  7. Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

    Science.gov (United States)

    2010-10-01

    spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

  8. ITER fuel cycle systems layout

    International Nuclear Information System (INIS)

    Kveton, O.K.

    1990-10-01

    The ITER fuel cycle building (FCB) will contain the following systems: fuel purification - permeator based; fuel purification - molecular sieves; impurity treatment; waste water storage and treatment; isotope separation; waste water tritium extraction; tritium extraction from solid breeder; tritium extraction from test modules; tritium storage, shipping and receiving; tritium laboratory; atmosphere detritiation systems; fuel cycle control centre; tritiated equipment maintenance space; control maintenance space; health physics laboratory; access, access control and facilities. The layout of the FCB and the requirements for these systems are described. (10 figs.)

  9. Emerging Applications for High K Materials in VLSI Technology

    Science.gov (United States)

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  10. Emerging Applications for High K Materials in VLSI Technology

    Directory of Open Access Journals (Sweden)

    Robert D. Clark

    2014-04-01

    Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

  11. A VLSI image processor via pseudo-mersenne transforms

    International Nuclear Information System (INIS)

    Sei, W.J.; Jagadeesh, J.M.

    1986-01-01

    The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

  12. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  13. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  14. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  15. The AMchip: A VLSI associative memory for track finding

    International Nuclear Information System (INIS)

    Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

    1992-01-01

    An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

  16. Drift chamber tracking with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

  17. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

  18. Generating and exploring good building layouts

    KAUST Repository

    Bao, Fan

    2013-07-16

    Good building layouts are required to conform to regulatory guidelines, while meeting certain quality measures. While different methods can sample the space of such good layouts, there exists little support for a user to understand and systematically explore the samples. Starting from a discrete set of good layouts, we analytically characterize the local shape space of good layouts around each initial layout, compactly encode these spaces, and link them to support transitions across the different local spaces. We represent such transitions in the form of a portal graph. The user can then use the portal graph, along with the family of local shape spaces, to globally and locally explore the space of good building layouts. We use our framework on a variety of different test scenarios to showcase an intuitive design, navigation, and exploration interface. Copyright © ACM. Copyright © ACM 2013.

  19. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  20. Interactive Graph Layout of a Million Nodes

    OpenAIRE

    Peng Mi; Maoyuan Sun; Moeti Masiane; Yong Cao; Chris North

    2016-01-01

    Sensemaking of large graphs, specifically those with millions of nodes, is a crucial task in many fields. Automatic graph layout algorithms, augmented with real-time human-in-the-loop interaction, can potentially support sensemaking of large graphs. However, designing interactive algorithms to achieve this is challenging. In this paper, we tackle the scalability problem of interactive layout of large graphs, and contribute a new GPU-based force-directed layout algorithm that exploits graph to...

  1. Patch layout generation by detecting feature networks

    KAUST Repository

    Cao, Yuanhao

    2015-02-01

    The patch layout of 3D surfaces reveals the high-level geometric and topological structures. In this paper, we study the patch layout computation by detecting and enclosing feature loops on surfaces. We present a hybrid framework which combines several key ingredients, including feature detection, feature filtering, feature curve extension, patch subdivision and boundary smoothing. Our framework is able to compute patch layouts through concave features as previous approaches, but also able to generate nice layouts through smoothing regions. We demonstrate the effectiveness of our framework by comparing with the state-of-the-art methods.

  2. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  3. The UA9 experimental layout

    CERN Document Server

    Scandale, W.; Assmann, R.; Bracco, C.; Cerutti, F.; Christiansen, J.; Gilardoni, S.; Laface, E.; Losito, R.; Masi, A.; Metral, E.; Mirarchi, D.; Montesano, S.; Previtali, V.; Redaelli, S.; Valentino, G.; Schoofs, P.; Smirnov, G.; Tlustos, L.; Bagli, E.; Baricordi, S.; Dalpiaz, P.; Guidi, V.; Mazzolari, A.; Vincenzi, D.; Dabagov, S.; Murtas, F.; Carnera, A.; Della Mea, G.; De Salvador, D.; Lombardi, A.; Lytovchenko, O.; Tonezzer, M.; Cavoto, G.; Ludovici, L.; Santacesaria, R.; Valente, P.; Galluccio, F.; Afonin, A.G.; Bulgakov, M.K.; Chesnokov, Yu.A.; Maisheev, V.A.; Yazynin, I.A.; Kovalenko, A.D.; Taratin, A.M.; Gavrikov, Yu.A.; Ivanov, Yu.M.; Lapina, L.P.; Skorobogatov, V.V.; Ferguson, W.; Fulcher, J.; Hall, G.; Pesaresi, M.; Raymond, M.; Rose, A.; Ryan, M.; Zorba, O.; Robert-Demolaize, G.; Markiewicz, T.; Oriunno, M.; Wienands, U.

    2011-01-01

    The UA9 experimental equipment was installed in the CERN-SPS in March '09 with the aim of investigating crystal assisted collimation in coasting mode. Its basic layout comprises silicon bent crystals acting as primary collimators mounted inside two vacuum vessels. A movable 60 cm long block of tungsten located downstream at about 90 degrees phase advance intercepts the deflected beam. Scintillators, Gas Electron Multiplier chambers and other beam loss monitors measure nuclear loss rates induced by the interaction of the beam halo in the crystal. Roman pots are installed in the path of the deflected particles and are equipped with a Medipix detector to reconstruct the transverse distribution of the impinging beam. Finally UA9 takes advantage of an LHC-collimator prototype installed close to the Roman pot to help in setting the beam conditions and to analyze the efficiency to deflect the beam. This paper describes in details the hardware installed to study the crystal collimation during 2010.

  4. Economics of wind farm layout

    Energy Technology Data Exchange (ETDEWEB)

    Germain, A.C. [Wind Energy Resource Specialist, Oakland, CA (United States); Bain, D.A. [Oregon Office of Energy, Portland, OR (United States)

    1997-12-31

    The life cycle cost of energy (COE) is the primary determinant of the economic viability of a wind energy generation facility. The cost of wind turbines and associated hardware is counterbalanced by the energy which can be generated. This paper focuses on the turbine layout design process, considering the cost and energy capture implications of potential spacing options from the viewpoint of a practicing project designer. It is argued that lateral spacings in the range of 1.5 to 5 diameters are all potentially optimal, but only when matched to wind resource characteristics and machine design limits. The effect of wakes on energy capture is quantified while the effect on turbine life and maintenance cost is discussed qualitatively. Careful optimization can lower COE and project designers are encouraged to integrate the concepts in project designs.

  5. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  6. Control room lay-out

    International Nuclear Information System (INIS)

    Toma, Violeta

    2004-01-01

    TRIUMF (Tri-University Meson Facility) is Canada's national laboratory for particle and nuclear physics. There are 6 accelerators and 3 Control Rooms at TRIUMF. The main control room serves the big cyclotron, the 500 MeV, and the adjacent experiment. The 42 MeV and two 32 MeV ones are production dedicated. These cyclotrons belong to a private company but are operated by TRIUMF staff from ATG (Applied Technology Group) Control Room. The last is ISAC (Isotope Acceleration and Separation) Control Room, from which the LINAC is controlled. Research areas cover theoretical (2 subjects), pure (5 subjects) and applied (8 subjects) physics. In the early '70s, as the 500 MeV was being completed, the first Control Room was built in the main accelerator building. The recent topics covered by this paper are proton and pion therapy, what are the operator's duties?, the CP42, TR30 and TR13 cyclotron control rooms, the ISAC control systems including control room modification. Due to the nature of an operator's job, the Control Room layout is pretty important. This is true for any work environment, but when working shifts it becomes essential. Lots of time and effort, not to mention money, were spent to figure out the optimum configuration. It seems to me that the key factor in the control room layout is versatility, and this is because it has to keep happy a group of people with different inclinations, which have a tendency to become quite moody after the second night shift. No matter what, there will still be unhappy people, but we are trying our best. (Y. Tanaka)

  7. Vegetation response to wagon wheel camp layouts.

    African Journals Online (AJOL)

    Wagon wheel camp layouts have been favoured, in some quarters, for rotational grazing due to the economy and convenience of having the camps radially arranged around central facilities. A possible disadvantage of such layouts is the tendency for over-grazing near the hub and under-grazing at the extremities.

  8. Staking Terraces Online: A Terrace Layout Program

    Science.gov (United States)

    Terrace construction in Missouri exceeded 3 million feet at a cost of over $8 million in 2008. Up to 50 % of the total construction and design time is spent on the terrace layout itself. A web-based computer program, MOTERR, has been developed to design terrace layouts. The program utilizes digital ...

  9. Interactive Graph Layout of a Million Nodes

    Directory of Open Access Journals (Sweden)

    Peng Mi

    2016-12-01

    Full Text Available Sensemaking of large graphs, specifically those with millions of nodes, is a crucial task in many fields. Automatic graph layout algorithms, augmented with real-time human-in-the-loop interaction, can potentially support sensemaking of large graphs. However, designing interactive algorithms to achieve this is challenging. In this paper, we tackle the scalability problem of interactive layout of large graphs, and contribute a new GPU-based force-directed layout algorithm that exploits graph topology. This algorithm can interactively layout graphs with millions of nodes, and support real-time interaction to explore alternative graph layouts. Users can directly manipulate the layout of vertices in a force-directed fashion. The complexity of traditional repulsive force computation is reduced by approximating calculations based on the hierarchical structure of multi-level clustered graphs. We evaluate the algorithm performance, and demonstrate human-in-the-loop layout in two sensemaking case studies. Moreover, we summarize lessons learned for designing interactive large graph layout algorithms on the GPU.

  10. Operator Station Design System - A computer aided design approach to work station layout

    Science.gov (United States)

    Lewis, J. L.

    1979-01-01

    The Operator Station Design System is resident in NASA's Johnson Space Center Spacecraft Design Division Performance Laboratory. It includes stand-alone minicomputer hardware and Panel Layout Automated Interactive Design and Crew Station Assessment of Reach software. The data base consists of the Shuttle Transportation System Orbiter Crew Compartment (in part), the Orbiter payload bay and remote manipulator (in part), and various anthropometric populations. The system is utilized to provide panel layouts, assess reach and vision, determine interference and fit problems early in the design phase, study design applications as a function of anthropometric and mission requirements, and to accomplish conceptual design to support advanced study efforts.

  11. Luminaire layout: Design and implementation

    Science.gov (United States)

    Both, A. J.

    1994-01-01

    The information contained in this report was presented during the discussion regarding guidelines for PAR uniformity in greenhouses. The data shows a lighting uniformity analysis in a research greenhouse for rose production at the Cornell University campus. The luminaire layout was designed using the computer program Lumen-Micro. After implementation of the design, accurate measurements were taken in the greenhouse and the uniformity analysis for both the design and implementation were compared. A study of several supplemental lighting installations resulted in the following recommendations: include only the actual growing area in the lighting uniformity analysis; for growing areas up to 20 square meters, take four measurements per square meter; for growing areas above 20 square meters, take one measurement per square meter; use one of the uniformity criteria and frequency graphs to compare lighting uniformity amongst designs; and design for uniformity criterion of a least 0.75 and the fraction within +/- 15% of the average PAR value should be close to one.

  12. Point DCT VLSI Architecture for Emerging HEVC Standard

    OpenAIRE

    Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

    2012-01-01

    This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

  13. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  14. Power efficient and high performance VLSI architecture for AES algorithm

    Directory of Open Access Journals (Sweden)

    K. Kalaiselvi

    2015-09-01

    Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

  15. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  16. Automatic Generation of User Interface Layouts for Alternative Screen Orientations

    OpenAIRE

    Zeidler , Clemens; Weber , Gerald; Stuerzlinger , Wolfgang; Lutteroth , Christof

    2017-01-01

    Part 1: Adaptive Design and Mobile Applications; International audience; Creating multiple layout alternatives for graphical user interfaces to accommodate different screen orientations for mobile devices is labor intensive. Here, we investigate how such layout alternatives can be generated automatically from an initial layout. Providing good layout alternatives can inspire developers in their design work and support them to create adaptive layouts. We performed an analysis of layout alternat...

  17. Layout Optimisation of Wave Energy Converter Arrays

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé; Nava, Vincenzo; Topper, Mathew B. R.

    2017-01-01

    This paper proposes an optimisation strategy for the layout design of wave energy converter (WEC) arrays. Optimal layouts are sought so as to maximise the absorbed power given a minimum q-factor, the minimum distance between WECs, and an area of deployment. To guarantee an efficient optimisation......, a four-parameter layout description is proposed. Three different optimisation algorithms are further compared in terms of performance and computational cost. These are the covariance matrix adaptation evolution strategy (CMA), a genetic algorithm (GA) and the glowworm swarm optimisation (GSO) algorithm...

  18. Space station automation study: Automation requriements derived from space manufacturing concepts,volume 2

    Science.gov (United States)

    1984-01-01

    Automation reuirements were developed for two manufacturing concepts: (1) Gallium Arsenide Electroepitaxial Crystal Production and Wafer Manufacturing Facility, and (2) Gallium Arsenide VLSI Microelectronics Chip Processing Facility. A functional overview of the ultimate design concept incoporating the two manufacturing facilities on the space station are provided. The concepts were selected to facilitate an in-depth analysis of manufacturing automation requirements in the form of process mechanization, teleoperation and robotics, sensors, and artificial intelligence. While the cost-effectiveness of these facilities was not analyzed, both appear entirely feasible for the year 2000 timeframe.

  19. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  20. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  1. VLSI architecture and design for the Fermat Number Transform implementation

    Energy Technology Data Exchange (ETDEWEB)

    Pajayakrit, A.

    1987-01-01

    A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

  2. Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

    Science.gov (United States)

    Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

    2017-12-01

    Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

  3. Development of Radhard VLSI electronics for SSC calorimeters

    International Nuclear Information System (INIS)

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

  4. Design of two easily-testable VLSI array multipliers

    Energy Technology Data Exchange (ETDEWEB)

    Ferguson, J.; Shen, J.P.

    1983-01-01

    Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

  5. Layout optimization using the homogenization method

    Science.gov (United States)

    Suzuki, Katsuyuki; Kikuchi, Noboru

    1993-01-01

    A generalized layout problem involving sizing, shape, and topology optimization is solved by using the homogenization method for three-dimensional linearly elastic shell structures in order to seek a possibility of establishment of an integrated design system of automotive car bodies, as an extension of the previous work by Bendsoe and Kikuchi. A formulation of a three-dimensional homogenized shell, a solution algorithm, and several examples of computing the optimum layout are presented in this first part of the two articles.

  6. Tinjauan Anatomi Layout Halaman Republika Epaper

    Directory of Open Access Journals (Sweden)

    Suprayitno Suprayitno

    2012-10-01

    Full Text Available Communities are increasingly familiar with Internet technology became one of the reasons for the rapid growth of digital newspaper in Indonesia. The ability of the media presents news in brief, fast, accessible and inexpensive form the basis of high growth of consumer interest in digital newspaper / electronic. Technological developments, triggering changes to the newspaper that had shaped the physical print later developed in digital form. In principle, newspaper print and digital newspapers contain messages or the same news, namely providing information to readers about the actual and weighted, as well as other light information that is entertainment. Review the anatomy of the digital newspaper layout is a study to trace and explore what and how the anatomy of a newspaper page layout, at least to provide information and understanding of the anatomy of the layouts in outline. Process layout in the digital version is no different from print media, which distinguishes its output only. In the process to any design layout of a medium, a designer is still expected to possess and master the basic principles such as layout hierarchy, emphasis, balance, and unity. 

  7. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  8. Computer aided selection of plant layout | Kitaw | Zede Journal

    African Journals Online (AJOL)

    This paper deals with the fundamental concepts of plant layout, in which the need for plant layout, the systematic and logical approaches to the problems, layout solutions and the objectives of plant layout are discussed. Further the approaches and the scoring techniques of the two available computer rout ines are ...

  9. 48 CFR 52.236-17 - Layout of Work.

    Science.gov (United States)

    2010-10-01

    ... 48 Federal Acquisition Regulations System 2 2010-10-01 2010-10-01 false Layout of Work. 52.236-17... Layout of Work. As prescribed in 36.517, insert the following clause in solicitations and contracts when... need for accurate work layout and for siting verification during work performance: Layout of Work (APR...

  10. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    Science.gov (United States)

    2007-03-31

    IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

  11. VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

    Science.gov (United States)

    Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

    1984-01-01

    Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

  12. VLSI and system architecture-the new development of system 5G

    Energy Technology Data Exchange (ETDEWEB)

    Sakamura, K.; Sekino, A.; Kodaka, T.; Uehara, T.; Aiso, H.

    1982-01-01

    A research and development proposal is presented for VLSI CAD systems and for a hardware environment called system 5G on which the VLSI CAD systems run. The proposed CAD systems use a hierarchically organized design language to enable design of anything from basic architectures of VLSI to VLSI mask patterns in a uniform manner. The cad systems will eventually become intelligent cad systems that acquire design knowledge and perform automatic design of VLSI chips when the characteristic requirements of VLSI chip is given. System 5G will consist of superinference machines and the 5G communication network. The superinference machine will be built based on a functionally distributed architecture connecting inferommunication network. The superinference machine will be built based on a functionally distributed architecture connecting inference machines and relational data base machines via a high-speed local network. The transfer rate of the local network will be 100 mbps at the first stage of the project and will be improved to 1 gbps. Remote access to the superinference machine will be possible through the 5G communication network. Access to system 5G will use the 5G network architecture protocol. The users will access the system 5G using standardized 5G personal computers. 5G personal logic programming stations, very high intelligent terminals providing an instruction set that supports predicate logic and input/output facilities for audio and graphical information.

  13. Development of pipe layout system

    International Nuclear Information System (INIS)

    Ota, Yoshimi; Yamamoto, Shigeru; Tokumasu, Shinji; Yamaguchi, Yukio; Besho, Hiromi; Sakano, Tatuo.

    1986-01-01

    In the plant design carried out so far, the process up to final drawings has been the repetition of the correction of drawings. This is because the space as the object of design is finite, and it is difficult to lay many pipes efficiently. Especially in nuclear power plants, the quantity of materials required for ensuring the safety and quality control is enormous, and only the skilled engineers having rich experience have become unable to deal with it. The model engineering using plastic models has been adopted, but still there are problems. In order to solve this problem, the development of the system for unitarily managing the various design information of plants with a computer, checking up various design with this information, automatically outputting design drawings and management data, and heightening the quality of design, synchronizing the progress, increasing the speed and saving the labor of design was carried out. This system is versatile and can be used for all plants. The emphasis in the development was placed on compact data structure, rapid picture processing and easy operation. The present status of design and the automation, the basic design of the system, the function of the system, the internal expression of models, the method of picture processing, and the results of application are reported. (Kako, I.)

  14. Evaluating Direct Manipulation Operations for Constraint-Based Layout

    OpenAIRE

    Zeidler , Clemens; Lutteroth , Christof; Stuerzlinger , Wolfgang; Weber , Gerald

    2013-01-01

    Part 11: Interface Layout and Data Entry; International audience; Layout managers are used to control the placement of widgets in graphical user interfaces (GUIs). Constraint-based layout managers are more powerful than other ones. However, they are also more complex and their layouts are prone to problems that usually require direct editing of constraints. Today, designers commonly use GUI builders to specify GUIs. The complexities of traditional approaches to constraint-based layouts pose c...

  15. An optimization tool for satellite equipment layout

    Science.gov (United States)

    Qin, Zheng; Liang, Yan-gang; Zhou, Jian-ping

    2018-01-01

    Selection of the satellite equipment layout with performance constraints is a complex task which can be viewed as a constrained multi-objective optimization and a multiple criteria decision making problem. The layout design of a satellite cabin involves the process of locating the required equipment in a limited space, thereby satisfying various behavioral constraints of the interior and exterior environments. The layout optimization of satellite cabin in this paper includes the C.G. offset, the moments of inertia and the space debris impact risk of the system, of which the impact risk index is developed to quantify the risk to a satellite cabin of coming into contact with space debris. In this paper an optimization tool for the integration of CAD software as well as the optimization algorithms is presented, which is developed to automatically find solutions for a three-dimensional layout of equipment in satellite. The effectiveness of the tool is also demonstrated by applying to the layout optimization of a satellite platform.

  16. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  17. Point DCT VLSI Architecture for Emerging HEVC Standard

    Directory of Open Access Journals (Sweden)

    Ashfaq Ahmed

    2012-01-01

    Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

  18. PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    T. Tharaneeswaran

    2012-06-01

    Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

  19. VLSI-based video event triggering for image data compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-02-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  20. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  1. Layout Optimisation of Wave Energy Converter Arrays

    Directory of Open Access Journals (Sweden)

    Pau Mercadé Ruiz

    2017-08-01

    Full Text Available This paper proposes an optimisation strategy for the layout design of wave energy converter (WEC arrays. Optimal layouts are sought so as to maximise the absorbed power given a minimum q-factor, the minimum distance between WECs, and an area of deployment. To guarantee an efficient optimisation, a four-parameter layout description is proposed. Three different optimisation algorithms are further compared in terms of performance and computational cost. These are the covariance matrix adaptation evolution strategy (CMA, a genetic algorithm (GA and the glowworm swarm optimisation (GSO algorithm. The results show slightly higher performances for the latter two algorithms; however, the first turns out to be significantly less computationally demanding.

  2. Discrete optimization in architecture architectural & urban layout

    CERN Document Server

    Zawidzki, Machi

    2016-01-01

    This book presents three projects that demonstrate the fundamental problems of architectural design and urban composition – the layout design, evaluation and optimization. Part I describes the functional layout design of a residential building, and an evaluation of the quality of a town square (plaza). The algorithm for the functional layout design is based on backtracking using a constraint satisfaction approach combined with coarse grid discretization. The algorithm for the town square evaluation is based on geometrical properties derived directly from its plan. Part II introduces a crowd-simulation application for the analysis of escape routes on floor plans, and optimization of a floor plan for smooth crowd flow. The algorithms presented employ agent-based modeling and cellular automata.

  3. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  4. FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2016-03-01

    Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

  5. Experimental verification of layout physical verification of silicon photonics

    Science.gov (United States)

    El Shamy, Raghi S.; Swillam, Mohamed A.

    2018-02-01

    Silicon photonics have been approved as one of the best platforms for dense integration of photonic integrated circuits (PICs) due to the high refractive index contrast among its materials. Silicon on insulator (SOI) is a widespread photonics technology, which support a variety of devices for lots of applications. As the photonics market is growing, the number of components in the PICs increases which increase the need for an automated physical verification (PV) process. This PV process will assure reliable fabrication of the PICs as it will check both the manufacturability and the reliability of the circuit. However, PV process is challenging in the case of PICs as it requires running an exhaustive electromagnetic (EM) simulations. Our group have recently proposed an empirical closed form models for the directional coupler and the waveguide bends based on the SOI technology. The models have shown a very good agreement with both finite element method (FEM) and finite difference time domain (FDTD) solvers. These models save the huge time of the 3D EM simulations and can be easily included in any electronic design automation (EDA) flow as the equations parameters can be easily extracted from the layout. In this paper we present experimental verification for our previously proposed models. SOI directional couplers with different dimensions have been fabricated using electron beam lithography and measured. The results from the measurements of the fabricate devices have been compared to the derived models and show a very good agreement. Also the matching can reach 100% by calibrating certain parameter in the model.

  6. Final Report: ATLAS Phase-2 Tracker Upgrade Layout Task Force

    CERN Document Server

    Clark, A; The ATLAS collaboration; Hessey, N; Mättig, P; Styles, N; Wells, P; Burdin, S; Cornelissen, T; Todorov, T; Vankov, P; Watson, I; Wenig, S

    2012-01-01

    he mandate of the Upgrade Layout Task Force was to develop a benchmark layout proposal for the ATLAS Phase-2 Upgrade Letter of Intent (LOI), due in late 2012. The work described in this note has evolved from simulation and design studies made using an earlier "UTOPIA" upgrade tracker layout, and experience gained from the current ATLAS Inner Detector during the first years of data taking. The layout described in this document, called the LoI-layout, will be used as a benchmark layout for the LoI and will be used for simulation and engineering studies described in the LoI.

  7. Intersection layout, traffic volumes and accidents.

    NARCIS (Netherlands)

    Poppe, F.

    1988-01-01

    This paper reports on the accident research carried out as a part of a large project started in 1983. For this accident research an inventory was made of a large number of intersections.Recorded were layout features, accident data and estimates of traffic volumes. Attention will be given to the

  8. Concept Layout Model of Transportation Terminals

    Directory of Open Access Journals (Sweden)

    Li-ya Yao

    2012-01-01

    Full Text Available Transportation terminal is the key node in transport systems. Efficient terminals can improve operation of passenger transportation networks, adjust the layout of public transportation networks, provide a passenger guidance system, and regulate the development of commercial forms, as well as optimize the assembly and distribution of modern logistic modes, among others. This study aims to clarify the relationship between the function and the structure of transportation terminals and establish the function layout design. The mapping mechanism of demand, function, and structure was analyzed, and a quantitative relationship between function and structure was obtained from a design perspective. Passenger demand and terminal structure were decomposed into several demand units and structural elements following the principle of reverse engineering. The relationship maps between these two kinds of elements were then analyzed. Function-oriented concept layout model of transportation terminals was established using the previous method. Thus, a technique in planning and design of transportation structures was proposed. Meaningful results were obtained from the optimization of transportation terminal facilities, which guide the design of the functional layout of transportation terminals and improve the development of urban passenger transportation systems.

  9. Terrace Layout Using a Computer Assisted System

    Science.gov (United States)

    Development of a web-based terrace design tool based on the MOTERR program is presented, along with representative layouts for conventional and parallel terrace systems. Using digital elevation maps and geographic information systems (GIS), this tool utilizes personal computers to rapidly construct ...

  10. Customisation of Indico pages - Layout and Menus

    CERN Multimedia

    CERN. Geneva; Ferreira, Pedro

    2017-01-01

    In this tutorial you are going to learn how to customize the layout of your Indico pages (for example you can change the color of the background images or change the logo) and the menus on your Indico pages  (for example you can add or hide certain blocks, or change their name and order).  

  11. You Be the Judge: Newspaper Advertising Layout.

    Science.gov (United States)

    Koeninger, Jimmy G.

    The learning package is designed to provide the marketing educator with a culminating activity for an instructional unit focusing on advertising layout principles and procedures. It is to be used in conjunction with 35mm slides of newspaper advertisements, which the student views and rates in comparison with the ratings of a panel of experts. A…

  12. Hardware and layout aspects affecting maintainability

    International Nuclear Information System (INIS)

    Jayaraman, V.N.; Surendar, Ch.

    1977-01-01

    It has been found from maintenance experience at the Rajasthan Atomic Power Station that proper hardware and instrumentation layout can reduce maintenance and down-time on the related equipment. The problems faced in this connection and how they were solved is narrated. (M.G.B.)

  13. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  14. Beam Dynamics and Layout arXiv

    CERN Document Server

    Lombardi, Alessandra

    In this paper, we give some guidelines for the design of linear accelerators, with special emphasis on their use in a hadron therapy facility. We concentrate on two accelerator layouts, based on linacs. The conventional one based on a linac injecting into a synchrotron and a all-linac solution based on high gradient high frequency RF cavities.

  15. Automatic Constraint Detection for 2D Layout Regularization.

    Science.gov (United States)

    Jiang, Haiyong; Nan, Liangliang; Yan, Dong-Ming; Dong, Weiming; Zhang, Xiaopeng; Wonka, Peter

    2016-08-01

    In this paper, we address the problem of constraint detection for layout regularization. The layout we consider is a set of two-dimensional elements where each element is represented by its bounding box. Layout regularization is important in digitizing plans or images, such as floor plans and facade images, and in the improvement of user-created contents, such as architectural drawings and slide layouts. To regularize a layout, we aim to improve the input by detecting and subsequently enforcing alignment, size, and distance constraints between layout elements. Similar to previous work, we formulate layout regularization as a quadratic programming problem. In addition, we propose a novel optimization algorithm that automatically detects constraints. We evaluate the proposed framework using a variety of input layouts from different applications. Our results demonstrate that our method has superior performance to the state of the art.

  16. Automatic Constraint Detection for 2D Layout Regularization

    KAUST Repository

    Jiang, Haiyong

    2015-09-18

    In this paper, we address the problem of constraint detection for layout regularization. As layout we consider a set of two-dimensional elements where each element is represented by its bounding box. Layout regularization is important for digitizing plans or images, such as floor plans and facade images, and for the improvement of user created contents, such as architectural drawings and slide layouts. To regularize a layout, we aim to improve the input by detecting and subsequently enforcing alignment, size, and distance constraints between layout elements. Similar to previous work, we formulate the layout regularization as a quadratic programming problem. In addition, we propose a novel optimization algorithm to automatically detect constraints. In our results, we evaluate the proposed framework on a variety of input layouts from different applications, which demonstrates our method has superior performance to the state of the art.

  17. Automatic Constraint Detection for 2D Layout Regularization

    KAUST Repository

    Jiang, Haiyong; Nan, Liangliang; Yan, Dongming; Dong, Weiming; Zhang, Xiaopeng; Wonka, Peter

    2015-01-01

    plans or images, such as floor plans and facade images, and for the improvement of user created contents, such as architectural drawings and slide layouts. To regularize a layout, we aim to improve the input by detecting and subsequently enforcing

  18. A Multi-Objective Optimization Framework for Offshore Wind Farm Layouts and Electric Infrastructures

    Directory of Open Access Journals (Sweden)

    Silvio Rodrigues

    2016-03-01

    Full Text Available Current offshore wind farms (OWFs design processes are based on a sequential approach which does not guarantee system optimality because it oversimplifies the problem by discarding important interdependencies between design aspects. This article presents a framework to integrate, automate and optimize the design of OWF layouts and the respective electrical infrastructures. The proposed framework optimizes simultaneously different goals (e.g., annual energy delivered and investment cost which leads to efficient trade-offs during the design phase, e.g., reduction of wake losses vs collection system length. Furthermore, the proposed framework is independent of economic assumptions, meaning that no a priori values such as the interest rate or energy price, are needed. The proposed framework was applied to the Dutch Borssele areas I and II. A wide range of OWF layouts were obtained through the optimization framework. OWFs with similar energy production and investment cost as layouts designed with standard sequential strategies were obtained through the framework, meaning that the proposed framework has the capability to create different OWF layouts that would have been missed by the designers. In conclusion, the proposed multi-objective optimization framework represents a mind shift in design tools for OWFs which allows cost savings in the design and operation phases.

  19. A High Performance VLSI Computer Architecture For Computer Graphics

    Science.gov (United States)

    Chin, Chi-Yuan; Lin, Wen-Tai

    1988-10-01

    A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

  20. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  1. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  2. CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

    International Nuclear Information System (INIS)

    Seidl, Albert; Klose, Helmut; Svoboda, Mildos

    2004-01-01

    1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

  3. 48 CFR 36.517 - Layout of work.

    Science.gov (United States)

    2010-10-01

    ... 48 Federal Acquisition Regulations System 1 2010-10-01 2010-10-01 false Layout of work. 36.517... CONTRACTING CONSTRUCTION AND ARCHITECT-ENGINEER CONTRACTS Contract Clauses 36.517 Layout of work. The contracting officer shall insert the clause at 52.236-17, Layout of Work, in solicitations and contracts when...

  4. A second generation 50 Mbps VLSI level zero processing system prototype

    Science.gov (United States)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  5. Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2004-09-01

    Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

  6. Pure JavaScript Storyline Layout Algorithm

    Energy Technology Data Exchange (ETDEWEB)

    2017-10-02

    This is a JavaScript library for a storyline layout algorithm. Storylines are adept at communicating complex change by encoding time on the x-axis and using the proximity of lines in the y direction to represent interaction between entities. The library in this disclosure takes as input a list of objects containing an id, time, and state. The output is a data structure that can be used to conveniently render a storyline visualization. Most importantly, the library computes the y-coordinate of the entities over time that decreases layout artifacts including crossings, wiggles, and whitespace. This is accomplished through multi-objective, multi-stage optimization problem, where the output of one stage produces input and constraints for the next stage.

  7. Concept Layout Model of Transportation Terminals

    OpenAIRE

    Yao, Li-ya; Sun, Li-shan; Wang, Wu-hong; Xiong, Hui

    2012-01-01

    Transportation terminal is the key node in transport systems. Efficient terminals can improve operation of passenger transportation networks, adjust the layout of public transportation networks, provide a passenger guidance system, and regulate the development of commercial forms, as well as optimize the assembly and distribution of modern logistic modes, among others. This study aims to clarify the relationship between the function and the structure of transportation terminals and establish ...

  8. CLASSIFICATION OF THE MGR SITE LAYOUT SYSTEM

    International Nuclear Information System (INIS)

    S.E. Salzman

    1999-01-01

    The purpose of this analysis is to document the Quality Assurance (QA) classification of the Monitored Geologic Repository (MGR) site layout system structures, systems and components (SSCs) performed by the MGR Safety Assurance Department. This analysis also provides the basis for revision of YMP/90-55Q, Q-List (YMP 1998). The Q-List identifies those MGR SSCs subject to the requirements of DOE/RW-0333P, ''Quality Assurance Requirements and Description'' (QARD) (DOE 1998)

  9. Inverse procedural modeling of facade layouts

    KAUST Repository

    Wu, Feng; Yan, Dongming; Dong, Weiming; Zhang, Xiaopeng; Wonka, Peter

    2014-01-01

    In this paper, we address the following research problem: How can we generate a meaningful split grammar that explains a given facade layout? To evaluate if a grammar is meaningful, we propose a cost function based on the description length and minimize this cost using an approximate dynamic programming framework. Our evaluation indicates that our framework extracts meaningful split grammars that are competitive with those of expert users, while some users and all competing automatic solutions are less successful. Copyright © ACM.

  10. Familiarisation: Restructuring Layouts with Visual Learning Models

    OpenAIRE

    Todi, Kashyap; Jokinen, Jussi; Luyten, Kris; Oulasvirta, Antti

    2018-01-01

    In domains where users are exposed to large variations in visuo-spatial features among designs, they often spend excess time searching for common elements (features) in familiar locations. This paper contributes computational approaches to restructuring layouts such that features on a new, unvisited interface can be found quicker. We explore four concepts of familiarisation, inspired by the human visual system (HVS), to automatically generate a familiar design for each user. Given a histor...

  11. Ergonomic Application on the Work Station Layout

    International Nuclear Information System (INIS)

    Suharyo Widagdo; Darlis

    2003-01-01

    Work station layout in the ideal way has been made. The dimension of the work station is 9.4 m x 7.1 m. The workers to be stationed should feel comfort. This can be done by honoring the dimensions and the sum of the tools that should be stationed and also the free space that should be mention between the tools as state in EPRI, NP-2411. (author)

  12. Inverse procedural modeling of facade layouts

    KAUST Repository

    Wu, Feng

    2014-07-22

    In this paper, we address the following research problem: How can we generate a meaningful split grammar that explains a given facade layout? To evaluate if a grammar is meaningful, we propose a cost function based on the description length and minimize this cost using an approximate dynamic programming framework. Our evaluation indicates that our framework extracts meaningful split grammars that are competitive with those of expert users, while some users and all competing automatic solutions are less successful. Copyright © ACM.

  13. Improved Layout of Inverter for EMC Analysis

    OpenAIRE

    Yade , Ousseynou; Martin , Christian; Vollaire , Christian; Bréard , Arnaud; Ali , Marwan; Meuret , Régis; Hervé , Morel

    2017-01-01

    International audience; This paper details EMC (electromagnetic compatibility) analysis on an inverter application. The work deals with the whole power chain (±270Vdc input voltage to 3-phase 115 Vac output voltage). This inverter is composed by modular parts (power module and EMC filters) that supply motors in more electrical aircraft. Through our analysis an approach is defined to design a detailed lumped circuit model of the power module layout by using Q3D extractor and SABER software. Fr...

  14. Space station automation study: Automation requirements derived from space manufacturing concepts. Volume 1: Executive summary

    Science.gov (United States)

    1984-01-01

    The electroepitaxial process and the Very Large Scale Integration (VLSI) circuits (chips) facilities were chosen because each requires a very high degree of automation, and therefore involved extensive use of teleoperators, robotics, process mechanization, and artificial intelligence. Both cover a raw materials process and a sophisticated multi-step process and are therfore highly representative of the kinds of difficult operation, maintenance, and repair challenges which can be expected for any type of space manufacturing facility. Generic areas were identified which will require significant further study. The initial design will be based on terrestrial state-of-the-art hard automation. One hundred candidate missions were evaluated on the basis of automation portential and availability of meaning ful knowldege. The design requirements and unconstrained design concepts developed for the two missions are presented.

  15. Probabilistic Graph Layout for Uncertain Network Visualization.

    Science.gov (United States)

    Schulz, Christoph; Nocaj, Arlind; Goertler, Jochen; Deussen, Oliver; Brandes, Ulrik; Weiskopf, Daniel

    2017-01-01

    We present a novel uncertain network visualization technique based on node-link diagrams. Nodes expand spatially in our probabilistic graph layout, depending on the underlying probability distributions of edges. The visualization is created by computing a two-dimensional graph embedding that combines samples from the probabilistic graph. A Monte Carlo process is used to decompose a probabilistic graph into its possible instances and to continue with our graph layout technique. Splatting and edge bundling are used to visualize point clouds and network topology. The results provide insights into probability distributions for the entire network-not only for individual nodes and edges. We validate our approach using three data sets that represent a wide range of network types: synthetic data, protein-protein interactions from the STRING database, and travel times extracted from Google Maps. Our approach reveals general limitations of the force-directed layout and allows the user to recognize that some nodes of the graph are at a specific position just by chance.

  16. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    International Nuclear Information System (INIS)

    Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

    1993-01-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

  17. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  18. Production layout improvement by using line balancing and Systematic Layout Planning (SLP) at PT. XYZ

    Science.gov (United States)

    Buchari; Tarigan, U.; Ambarita, M. B.

    2018-02-01

    PT. XYZ is a wood processing company which produce semi-finished wood with production system is make to order. In the production process, it can be seen that the production line is not balanced. The imbalance of the production line is caused by the difference in cycle time between work stations. In addition, there are other issues, namely the existence of material flow pattern is irregular so it resulted in the backtracking and displacement distance away. This study aimed to obtain the allocation of work elements to specific work stations and propose an improvement of the production layout based on the result of improvements in the line balancing. The method used in the balancing is Ranked Positional Weight (RPW) or also known as Helgeson Birnie method. While the methods used in the improvement of the layout is the method of Systematic Layout Planning (SLP). By using Ranked Positional Weight (RPW) obtained increase in line efficiency becomes 84,86% and decreased balance delay becomes 15,14%. Repairing the layout using the method of Systematic Layout Planning (SLP) also give good results with a reduction in path length becomes 133,82 meters from 213,09 meters previously or a decrease of 37.2%.

  19. A REDESIGN LAYOUT TO INCREASE PRODUCTIVITY OF A COMPANY

    Directory of Open Access Journals (Sweden)

    Vincentia Kitriastika

    2013-06-01

    Full Text Available This project is conducted in Company X, a passenger cars wheel producing company located in Sunter, North Jakarta. With a view of increasing the productivity of the company, the focus of this project will be redesigned the layout of the factory. The main problem encountered is that the goods are not produced in single location, causing a considerable hindrance in terms of time and distance, and hence efficiency. The redesigning layout process will use SLP method and flow analysis while supported by analysis of assembly line balancing to optimize the layout. Regarding the evaluation process, ARENA software will be used to simulate and identify the bottleneck in the production process, and comparing the layout alternatives to decide the best layout. The best chosen layout according to the simulation and SLP method that supported with flow analysis and assembly line balancing will be used as the master draft layout that will be proposed to Company X.

  20. VLSI for High-Speed Digital Signal Processing

    Science.gov (United States)

    1994-09-30

    particular, the design, layout and fab - rication of integrated circuits. The primary project for this grant has been the design and implementation of a...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

  1. General layout of a 1300 MW PWR buildings: standard lay-out and influence factors

    International Nuclear Information System (INIS)

    Silva Messias, M. da

    1986-01-01

    The Standardization concept of a 1300 MW Nuclear Power Plant equipped with pressurized-water reactors (PWR) will be considered with regard to the factors which have various degrees of influence on the Layout of the Site. Standardization with regard to the Layout of nuclear power plant, stands, however also for a fixed arrangement of the components in the main buildings and a fixed arrangement of the buildings in the site plan. Standardization may result in simplified and shorter licensing procedures and mean less planning effort. Concentration of systems, optimization of the electro-mechanical design, clear separation of the controlled area, need for shielding, maintenance and safety aspects are some of number of factors which have various degress of influence on the layout of the buildings. (Author) [pt

  2. Repository surface design site layout analysis

    International Nuclear Information System (INIS)

    Montalvo, H.R.

    1998-01-01

    The purpose of this analysis is to establish the arrangement of the Yucca Mountain Repository surface facilities and features near the North Portal. The analysis updates and expands the North Portal area site layout concept presented in the ACD, including changes to reflect the resizing of the Waste Handling Building (WHB), Waste Treatment Building (WTB), Carrier Preparation Building (CPB), and site parking areas; the addition of the Carrier Washdown Buildings (CWBs); the elimination of the Cask Maintenance Facility (CMF); and the development of a concept for site grading and flood control. The analysis also establishes the layout of the surface features (e.g., roads and utilities) that connect all the repository surface areas (North Portal Operations Area, South Portal Development Operations Area, Emplacement Shaft Surface Operations Area, and Development Shaft Surface Operations Area) and locates an area for a potential lag storage facility. Details of South Portal and shaft layouts will be covered in separate design analyses. The objective of this analysis is to provide a suitable level of design for the Viability Assessment (VA). The analysis was revised to incorporate additional material developed since the issuance of Revision 01. This material includes safeguards and security input, utility system input (size and location of fire water tanks and pump houses, potable water and sanitary sewage rates, size of wastewater evaporation pond, size and location of the utility building, size of the bulk fuel storage tank, and size and location of other exterior process equipment), main electrical substation information, redundancy of water supply and storage for the fire support system, and additional information on the storm water retention pond

  3. Mechanical structures with enhanced layout characteristics

    Directory of Open Access Journals (Sweden)

    Yefimenko A. A.

    2016-10-01

    Full Text Available The authors propose solutions for constructing mechanical structures for electronic equipment in terms of plug-in units and subracks, allowing to increase the layout characteristics of electronic modules, sections and desktop devices and increase their functional capacity without changing the architecture of standard mechanical structures. The paper shows effectiveness of the developed solutions. There is a problem of restraining of mass redundancy of mechanical structures for electronic equipment in relation to the weight of the electronic components. On the other hand, the weight is an indicator of structural strength, providing of which is not less important problem. These problems can be solved in different ways, the main of which are the following: a development of new mechanical structures for electronic equipment taking into account the development of the electronic components; b improving layout characteristics of mechanical structures for electronic equipment without significant changes in their architecture. The aim of the study was to research mechanical structures of the first level (plug-in units and modules of the second level of subracks to improve layout characteristics, and to develop methods for the use of connections for surface mounting and for the use of printed circuit boards of smaller dimensions without changing the architecture of the mechanical structures in order to improve layout characteristics. The research allowed the authors to develop the following solutions: 1. The design of plug-in units in which instead of one printed circuit board (PCB may be two, three or more PCBs of smaller dimensions to compensate a decrease in PCB fill factor in time and to increase the functional capacity of electronic modules. 2. Construction of block designs with a bilateral arrangement of plug-in units and the organization of the electrical connections by way of backplanes with electrical connectors for surface mounting, which allows

  4. Methodology of shell structure reinforcement layout optimization

    Science.gov (United States)

    Szafrański, Tomasz; Małachowski, Jerzy; Damaziak, Krzysztof

    2018-01-01

    This paper presents an optimization process of a reinforced shell diffuser intended for a small wind turbine (rated power of 3 kW). The diffuser structure consists of multiple reinforcement and metal skin. This kind of structure is suitable for optimization in terms of selection of reinforcement density, stringers cross sections, sheet thickness, etc. The optimisation approach assumes the reduction of the amount of work to be done between the optimization process and the final product design. The proposed optimization methodology is based on application of a genetic algorithm to generate the optimal reinforcement layout. The obtained results are the basis for modifying the existing Small Wind Turbine (SWT) design.

  5. High-energy heavy ion testing of VLSI devices for single event ...

    Indian Academy of Sciences (India)

    Unknown

    per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

  6. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

    2011-01-01

    -designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

  7. Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

    Science.gov (United States)

    Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

    1991-01-01

    A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

  8. An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

    DEFF Research Database (Denmark)

    Paaske, Erik; Pedersen, Steen; Sparsø, Jens

    1991-01-01

    Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

  9. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  10. Hierarchically organized layout for visualization of biochemical pathways.

    Science.gov (United States)

    Tsay, Jyh-Jong; Wu, Bo-Liang; Jeng, Yu-Sen

    2010-01-01

    Many complex pathways are described as hierarchical structures in which a pathway is recursively partitioned into several sub-pathways, and organized hierarchically as a tree. The hierarchical structure provides a natural way to visualize the global structure of a complex pathway. However, none of the previous research on pathway visualization explores the hierarchical structures provided by many complex pathways. In this paper, we aim to develop algorithms that can take advantages of hierarchical structures, and give layouts that explore the global structures as well as local structures of pathways. We present a new hierarchically organized layout algorithm to produce layouts for hierarchically organized pathways. Our algorithm first decomposes a complex pathway into sub-pathway groups along the hierarchical organization, and then partition each sub-pathway group into basic components. It then applies conventional layout algorithms, such as hierarchical layout and force-directed layout, to compute the layout of each basic component. Finally, component layouts are joined to form a final layout of the pathway. Our main contribution is the development of algorithms for decomposing pathways and joining layouts. Experiment shows that our algorithm is able to give comprehensible visualization for pathways with hierarchies, cycles as well as complex structures. It clearly renders the global component structures as well as the local structure in each component. In addition, it runs very fast, and gives better visualization for many examples from previous related research. 2009 Elsevier B.V. All rights reserved.

  11. Josephson shift register design and layout

    International Nuclear Information System (INIS)

    Przybysz, J.X.; Buttyan, J.; Blaugher, R.D.

    1989-01-01

    Integrated circuit chips were designed and fabricated, based on Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25 mm square chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO/sub x//Nb Josephson junctions with a design value of 2000 A/cm/sup 2/ critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. Gate bias resistors were treated as resistive transmission lines. A layout geometry for the superconductive transmission lines and thin film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2 degrees of 10 Ghz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers

  12. Evolutionary optimization technique for site layout planning

    KAUST Repository

    El Ansary, Ayman M.

    2014-02-01

    Solving the site layout planning problem is a challenging task. It requires an iterative approach to satisfy design requirements (e.g. energy efficiency, skyview, daylight, roads network, visual privacy, and clear access to favorite views). These design requirements vary from one project to another based on location and client preferences. In the Gulf region, the most important socio-cultural factor is the visual privacy in indoor space. Hence, most of the residential houses in this region are surrounded by high fences to provide privacy, which has a direct impact on other requirements (e.g. daylight and direction to a favorite view). This paper introduces a novel technique to optimally locate and orient residential buildings to satisfy a set of design requirements. The developed technique is based on genetic algorithm which explores the search space for possible solutions. This study considers two dimensional site planning problems. However, it can be extended to solve three dimensional cases. A case study is presented to demonstrate the efficiency of this technique in solving the site layout planning of simple residential dwellings. © 2013 Elsevier B.V. All rights reserved.

  13. Document reconstruction by layout analysis of snippets

    Science.gov (United States)

    Kleber, Florian; Diem, Markus; Sablatnig, Robert

    2010-02-01

    Document analysis is done to analyze entire forms (e.g. intelligent form analysis, table detection) or to describe the layout/structure of a document. Also skew detection of scanned documents is performed to support OCR algorithms that are sensitive to skew. In this paper document analysis is applied to snippets of torn documents to calculate features for the reconstruction. Documents can either be destroyed by the intention to make the printed content unavailable (e.g. tax fraud investigation, business crime) or due to time induced degeneration of ancient documents (e.g. bad storage conditions). Current reconstruction methods for manually torn documents deal with the shape, inpainting and texture synthesis techniques. In this paper the possibility of document analysis techniques of snippets to support the matching algorithm by considering additional features are shown. This implies a rotational analysis, a color analysis and a line detection. As a future work it is planned to extend the feature set with the paper type (blank, checked, lined), the type of the writing (handwritten vs. machine printed) and the text layout of a snippet (text size, line spacing). Preliminary results show that these pre-processing steps can be performed reliably on a real dataset consisting of 690 snippets.

  14. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  15. Getting it across : layout issues for kiosk systems

    OpenAIRE

    Borchers, Jan; Deussen, Oliver; Knörzer, Clemens

    1995-01-01

    A clear and appealing screen layout is crucial to the success of on-line kiosk systems, public terminals that are connected to a network. This paper addresses the problem of developing such a layout, and provides several guidelines, drawn from traditional typography and Gestalt psychology as well as from hypertext authoring, and human-computer interaction. To identify how a kiosk system s primary task influences optimal layout, kiosk systems are classified into four basic types. The usability...

  16. Creation of Warehouse Models for Different Layout Designs

    OpenAIRE

    Köhler, Mirko; Lukić, Ivica; Nenadić, Krešimir

    2014-01-01

    Warehouse is one of the most important components in logistics of the supply chain network. Efficiency of warehouse operations is influenced by many different factors. One of the key factors is the racks layout configuration. A warehouse with good racks layout may significantly reduce the cost of warehouse servicing. The objective of this paper is to give a scheme for building warehouses models with one-block and two-block layout for future research in warehouse optimization. An algorithm ...

  17. A New Layout Method for Graphical User Interfaces

    OpenAIRE

    Scoditti , Adriano; Stuerzlinger , Wolfgang

    2010-01-01

    International audience; The layout mechanisms for many GUI toolkits are hard to understand, the associated tools and API's often difficult to use. This work investigates new, easy-to-understand layout mechanisms and evaluates its implementation. We will analyze the requirements for the definition of layouts of a graphical user interface. Part of the issue is that several aspects need to be considered simultaneously while laying-out a component: the alignment with other components as well as i...

  18. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    National Research Council Canada - National Science Library

    Altmeyer, Ronald

    2002-01-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

  19. Three-dimensional computer aided design system for plant layout

    International Nuclear Information System (INIS)

    Yoshinaga, Toshiaki; Kiguchi, Takashi; Tokumasu, Shinji; Kumamoto, Kenjiro.

    1986-01-01

    The CAD system for three-dimensional plant layout planning, with which the layout of pipings, cable trays, air conditioning ducts and so on in nuclear power plants can be planned and designed effectively in a short period is reported. This system comprises the automatic routing system by storing the rich experience and know-how of designers in a computer as the knowledge, and deciding the layout automatically following the predetermined sequence by using these, the interactive layout system for reviewing the routing results from higher level and modifying to the optimum layout, the layout evaluation system for synthetically evaluating the layout from the viewpoint of the operability such as checkup and maintenance, and the data base system which enables these effective planning and design. In this report, the total constitution of this system and the technical features and effects of the individual subsystems are outlined. In this CAD system for three-dimensional plant layout planning, knowledge engineering, CAD/CAM, computer graphics and other latest technology were introduced, accordingly by applying this system to plant design, the design can be performed quickly, various case studies can be carried out at planning stage, and systematic and optimum layout planning becomes possible. (Kako, I.)

  20. Layout compliance for triple patterning lithography: an iterative approach

    Science.gov (United States)

    Yu, Bei; Garreton, Gilda; Pan, David Z.

    2014-10-01

    As the semiconductor process further scales down, the industry encounters many lithography-related issues. In the 14nm logic node and beyond, triple patterning lithography (TPL) is one of the most promising techniques for Metal1 layer and possibly Via0 layer. As one of the most challenging problems in TPL, recently layout decomposition efforts have received more attention from both industry and academia. Ideally the decomposer should point out locations in the layout that are not triple patterning decomposable and therefore manual intervention by designers is required. A traditional decomposition flow would be an iterative process, where each iteration consists of an automatic layout decomposition step and manual layout modification task. However, due to the NP-hardness of triple patterning layout decomposition, automatic full chip level layout decomposition requires long computational time and therefore design closure issues continue to linger around in the traditional flow. Challenged by this issue, we present a novel incremental layout decomposition framework to facilitate accelerated iterative decomposition. In the first iteration, our decomposer not only points out all conflicts, but also provides the suggestions to fix them. After the layout modification, instead of solving the full chip problem from scratch, our decomposer can provide a quick solution for a selected portion of layout. We believe this framework is efficient, in terms of performance and designer friendly.

  1. The Offshore Wind Farm Array Cable Layout Problem

    DEFF Research Database (Denmark)

    Bauer, Joanna; Lysgaard, Jens

    2014-01-01

    In an offshore wind farm (OWF), the turbines are connected to a transformer by cable routes that cannot cross each other. Finding the minimum cost array cable layout thus amounts to a vehicle routing problem with the additional constraints that the routes must be embedded in the plane. For this p......In an offshore wind farm (OWF), the turbines are connected to a transformer by cable routes that cannot cross each other. Finding the minimum cost array cable layout thus amounts to a vehicle routing problem with the additional constraints that the routes must be embedded in the plane....... For this problem, both exact and heuristic methods are of interest. We optimize cable layouts for real-world OWFs by a hop-indexed integer programming formulation, and develop a heuristic for computing layouts based on the Clarke and Wright savings heuristic for vehicle routing. Our heuristic computes layouts...... on average only 2% more expensive than the optimal layout. Finally, we present two problem extensions arising from real-world OWF cable layouts, and adapt the integer programming formulation to one of them. The thus obtained optimal layouts are up to 13% cheaper than the actually installed layouts....

  2. Ergonomics influence on control room layout

    International Nuclear Information System (INIS)

    Hartfiel, H.D.

    1984-01-01

    Nowadays, human factors has become an important aspect of the design of work places. Since the control room in a nuclear power plant is a work place, too, its layout is also influenced by ergonomics. With the KWU control room concept for the 1300 MW PWR as an example, we show how assured and applicable ergonomic findings enter into the control room design. On the basis of general design principles for work places, specific methods for control room planning have been developed. By working with these methods a concept that makes it possible to build a man-machine interface able to fulfill the process control tasks with all their underlying conditions has been derived. (author)

  3. Procedural facade variations from a single layout

    KAUST Repository

    Bao, Fan

    2013-02-19

    We introduce a framework to generate many variations of a facade design that look similar to a given facade layout. Starting from an input image, the facade is hierarchically segmented and labeled with a collection of manual and automatic tools. The user can then model constraints that should be maintained in any variation of the input facade design. Subsequently, facade variations are generated for different facade sizes, where multiple variations can be produced for a certain size. Computing such new facade variations has many unique challenges, and we propose a new algorithm based on interleaving heuristic search and quadratic programming. In contrast to most previous work, we focus on the generation of new design variations and not on the automatic analysis of the input\\'s structure. Adding a modeling step with the user in the loop ensures that our results routinely are of high quality. © 2013 ACM.

  4. Procedural facade variations from a single layout

    KAUST Repository

    Bao, Fan; Schwarz, Michael; Wonka, Peter

    2013-01-01

    We introduce a framework to generate many variations of a facade design that look similar to a given facade layout. Starting from an input image, the facade is hierarchically segmented and labeled with a collection of manual and automatic tools. The user can then model constraints that should be maintained in any variation of the input facade design. Subsequently, facade variations are generated for different facade sizes, where multiple variations can be produced for a certain size. Computing such new facade variations has many unique challenges, and we propose a new algorithm based on interleaving heuristic search and quadratic programming. In contrast to most previous work, we focus on the generation of new design variations and not on the automatic analysis of the input's structure. Adding a modeling step with the user in the loop ensures that our results routinely are of high quality. © 2013 ACM.

  5. Underground design Laxemar, Layout D2

    Energy Technology Data Exchange (ETDEWEB)

    2009-11-15

    Laxemar candidate area is located in the province of Smaaland, some 320 km south of Stockholm. The area is located close to the shoreline of the Baltic Sea and is within the municipality of Oskarshamn, and immediately west of the Oskarshamn nuclear power plant and the Central interim storage facility for spent fuel (Clab). The easternmost part (Simpevarp subarea) includes the Simpevarp peninsula, which hosts the power plants and the Clab facility. The island of Aespoe, containing the Aespoe Hard Rock Laboratory is located some three kilometres northeast of the central parts of Laxemar. The Laxemar subarea covers some 12.5 km2, compared with the Simepvarp subarea, which is approximately 6.6 km2. The Laxemar candidate area has been investigated in stages, referred to as the initial site investigations (ISI) and the complete site investigations (CSI). These investigations commenced in 2002 and were completed in 2008. During the site investigations, several studies and design steps (D0, D1 and D2) were carried out to ensure that sufficient space was available for the 6,000-canister layout within the target volume at a depth of approximately 500 m. The findings from design Step D2 for the underground facilities including the access ramp, shafts, rock caverns in a Central Area, transport tunnels, and deposition tunnels and deposition holes are contained in this report. The layout for these underground excavations at the deposition horizon requires an area of 5.7 km2, and the total rock volume to be excavated is 3,008 x 103 m3 using a total tunnel length of approximately 115 km. The behaviour of the underground openings associated with this layout is expected to be similar to the behaviour of other underground openings in the Scandinavian shield at similar depths. The dominant mode of instability is expected to be structurally controlled wedge failure. Stability of the openings will be achieved with traditional underground rock support and by orienting the openings

  6. Automation in control laboratory and related information management system

    International Nuclear Information System (INIS)

    Gopalan, B.; Syamsundar, S.

    1997-01-01

    In the field of technology, the word automation is often employed to indicate many types of mechanized operations, though in the strict sense it means those operations which involve application of an element of knowledge or decision making without the intervention of human mind. In laboratory practice for example, the use of multi-sample array turret and millivolt recorder connected to a spectrophotometer represents a situation of mechanized operation as these gadgets help eliminating human muscle power. If a micro processor or a computer is connected to the above equipment for interpreting the measured parameters and establishing calibration graphs or display concentration results, then a real automated situation results where the application of human mind is eliminated. The state of the art of modern laboratory analysis abounds in the employment of automatic analytical equipment thanks to the development in the field of VLSI, computer, software etc. and this has given rise to the concept of laboratory automation

  7. Optimal layout of radiological environment monitoring based on TOPSIS method

    International Nuclear Information System (INIS)

    Li Sufen; Zhou Chunlin

    2006-01-01

    TOPSIS is a method for multi-objective-decision-making, which can be applied to comprehensive assessment of environmental quality. This paper adopts it to get the optimal layout of radiological environment monitoring, it is proved that this method is a correct, simple and convenient, practical one, and beneficial to supervision departments to scientifically and reasonably layout Radiological Environment monitoring sites. (authors)

  8. Layout and cabling considerations for a large communications antenna array

    Science.gov (United States)

    Logan, R. T., Jr.

    1993-01-01

    Layout considerations for a large deep space communications antenna array are discussed. A fractal geometry for the antenna layout is described that provides optimal packing of antenna elements, efficient cable routing, and logical division of the array into identical sub-arrays.

  9. Mental Layout Extrapolations Prime Spatial Processing of Scenes

    Science.gov (United States)

    Gottesman, Carmela V.

    2011-01-01

    Four experiments examined whether scene processing is facilitated by layout representation, including layout that was not perceived but could be predicted based on a previous partial view (boundary extension). In a priming paradigm (after Sanocki, 2003), participants judged objects' distances in photographs. In Experiment 1, full scenes (target),…

  10. Selecting a pharmacy layout design using a weighted scoring system.

    Science.gov (United States)

    McDowell, Alissa L; Huang, Yu-Li

    2012-05-01

    A weighted scoring system was used to select a pharmacy layout redesign. Facilities layout design techniques were applied at a local hospital pharmacy using a step-by-step design process. The process involved observing and analyzing the current situation, observing the current available space, completing activity flow charts of the pharmacy processes, completing communication and material relationship charts to detail which areas in the pharmacy were related to one another and how they were related, researching applications in other pharmacies or in scholarly works that could be beneficial, numerically defining space requirements for areas within the pharmacy, measuring the available space within the pharmacy, developing a set of preliminary designs, and modifying preliminary designs so they were all acceptable to the pharmacy staff. To select a final layout that could be implemented in the pharmacy, those layouts were compared via a weighted scoring system. The weighted aspect further allowed additional emphasis on categories based on their effect on pharmacy performance. The results produced a beneficial layout design as determined through simulated models of the pharmacy operation that more effectively allocated and strategically located space to improve transportation distances and materials handling, employee utilization, and ergonomics. Facilities layout designs for a hospital pharmacy were evaluated using a weighted scoring system to identify a design that was superior to both the current layout and alternative layouts in terms of feasibility, cost, patient safety, employee safety, flexibility, robustness, transportation distance, employee utilization, objective adherence, maintainability, usability, and environmental impact.

  11. Optimization of machining fixture layout for tolerance requirements ...

    African Journals Online (AJOL)

    Dimensional accuracy of workpart under machining is strongly influenced by the layout of the fixturing elements like locators and clamps. Setup or geometrical errors in locators result in overall machining error of the feature under consideration. Therefore it is necessary to ensure that the layout is optimized for the desired ...

  12. Student Perceptions of Textbook Layout and Learnability in Private Schools

    Science.gov (United States)

    Hoshangabadwala, Alefiyah

    2015-01-01

    This research is an exploratory study that investigates students' perceptions pertinent to textbook layout and organization and their evaluation of the textbook ease of learning. The objective is to find out whether the layout dynamics of school textbooks make any difference in students' interest in studying or subject understanding. 73 students…

  13. Layout Geometry in Encoding and Retrieval of Spatial Memory

    Science.gov (United States)

    Mou, Weimin; Liu, Xianyun; McNamara, Timothy P.

    2009-01-01

    Two experiments investigated whether the spatial reference directions that are used to specify objects' locations in memory can be solely determined by layout geometry. Participants studied a layout of objects from a single viewpoint while their eye movements were recorded. Subsequently, participants used memory to make judgments of relative…

  14. Layout Of Antennas And Cables In A Large Array

    Science.gov (United States)

    Logan, Ronald T., Jr.

    1995-01-01

    Layout devised to minimize total land area occupied by large phased array of antennas and to minimize total length of cables in array. In original intended application, array expanded version of array of paraboloidal-dish microwave communication antennas of Deep Space Network. Layout also advantageous for other phased arrays of antennas and antenna elements, including notably printed-circuit microwave antenna arrays.

  15. DSS 13 phase 2 pedestal room microwave layout

    Science.gov (United States)

    Cwik, T.; Chen, J. C.

    1991-01-01

    The design and predicted performance is described of the microwave layout for three band operation of the beam waveguide antenna Deep Space Station 13. Three pedestal room microwave candidate layout designs were produced for simultaneous X/S and X/Ka band operation. One of the three designs was chosen based on given constraints, and for this design the microwave performance was estimated.

  16. Layout and flow of dermatology clinics: principles from operations management.

    Science.gov (United States)

    Wang, Jordan V

    2018-04-15

    Dermatology is a medical specialty that experiences high patient demand and long patient wait times. Dermatology clinics should look for ways to improve efficiency through the incorporation of principles from operations management. Addressing the layout and flow of a clinic can lead to operational efficiency. An ideal layout may lead to increased patient volume, satisfaction, and retention.

  17. Scalable force directed graph layout algorithms using fast multipole methods

    KAUST Repository

    Yunis, Enas Abdulrahman; Yokota, Rio; Ahmadia, Aron

    2012-01-01

    We present an extension to ExaFMM, a Fast Multipole Method library, as a generalized approach for fast and scalable execution of the Force-Directed Graph Layout algorithm. The Force-Directed Graph Layout algorithm is a physics-based approach

  18. A linear time layout algorithm for business process models

    NARCIS (Netherlands)

    Gschwind, T.; Pinggera, J.; Zugal, S.; Reijers, H.A.; Weber, B.

    2014-01-01

    The layout of a business process model influences how easily it can beunderstood. Existing layout features in process modeling tools often rely on graph representations, but do not take the specific properties of business process models into account. In this paper, we propose an algorithm that is

  19. Simulation Modeling of a Facility Layout in Operations Management Classes

    Science.gov (United States)

    Yazici, Hulya Julie

    2006-01-01

    Teaching quantitative courses can be challenging. Similarly, layout modeling and lean production concepts can be difficult to grasp in an introductory OM (operations management) class. This article describes a simulation model developed in PROMODEL to facilitate the learning of layout modeling and lean manufacturing. Simulation allows for the…

  20. Agriculture Education. Elements of Farm and Building Layout.

    Science.gov (United States)

    Stuttgart Public Schools, AR.

    This curriculum guide is designed for group instruction of secondary agricultural education students enrolled in one or two semester-long courses in elements of farm and building layout. The guide presents units of study in the following areas: (1) sketching and drawing equipment, (2) gothic lettering, (3) layout of a standard sheet, (4) job…

  1. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  2. On the impact of layout quality to understanding UML diagrams

    DEFF Research Database (Denmark)

    Störrle, Harald

    2011-01-01

    previous research considered them in isolation only. In this paper, we report the results of a series of controlled experiments using compound layouts on requirements analysis models. With very high significance, we find a notable impact of the layout quality measured by different aspects of cognitive load....

  3. FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

    Directory of Open Access Journals (Sweden)

    A. A. Doudkin

    2015-01-01

    Full Text Available Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

  4. Issues in Text Design and Layout for Computer Based Communications.

    Science.gov (United States)

    Andresen, Lee W.

    1991-01-01

    Discussion of computer-based communications (CBC) focuses on issues involved with screen design and layout for electronic text, based on experiences with electronic messaging, conferencing, and publishing within the Australian Open Learning Information Network (AOLIN). Recommendations for research on design and layout for printed text are also…

  5. Target aligned heliostat field layout for non-flat terrrain

    CSIR Research Space (South Africa)

    Buck, R

    2012-05-01

    Full Text Available The layout for a solar tower test facility for CSIR, Pretoria, is described. The solar tower system is designed for 400kWth receiver outlet power. The heliostat field layout takes into account both the real (non-flat) topography of the terrain...

  6. Layout of the LER [Low Energy Ring] Arc

    International Nuclear Information System (INIS)

    Hutton, A.

    1990-01-01

    We have recently been trying to accumulate all of the information necessary to decide on the layout of the regular curved arcs of the Low Energy Ring (LER) and there have been several ABC Notes published on different aspects of the problem. This note will describe the layout that has been derived from these considerations

  7. Planning, layout and infrastructure of modern coal mines

    Energy Technology Data Exchange (ETDEWEB)

    Haarmann, K R

    1978-02-01

    When designing layout and infrastructure of new coal mines, the principles of planning play a decisive role. Apart from exploration, ventilation, transport, dirt haulage and product haulage, material transport is very important. Illustrated by three examples, modern layout and infrastructure design is presented.

  8. Multipurpose layout drawing of metalware of bridge crane load trolley

    Directory of Open Access Journals (Sweden)

    Goncharov K.A.

    2017-03-01

    Full Text Available Multipurpose layout drawing of metalware of bridge crane load trolley is proposed. The numerical analysis of proposed layout drawing is conducted using the example of bridge crane load trolley with capacity of 20 t. This analysis is carried out using the finite element method.

  9. Optimal Control Surface Layout for an Aeroservoelastic Wingbox

    Science.gov (United States)

    Stanford, Bret K.

    2017-01-01

    This paper demonstrates a technique for locating the optimal control surface layout of an aeroservoelastic Common Research Model wingbox, in the context of maneuver load alleviation and active utter suppression. The combinatorial actuator layout design is solved using ideas borrowed from topology optimization, where the effectiveness of a given control surface is tied to a layout design variable, which varies from zero (the actuator is removed) to one (the actuator is retained). These layout design variables are optimized concurrently with a large number of structural wingbox sizing variables and control surface actuation variables, in order to minimize the sum of structural weight and actuator weight. Results are presented that demonstrate interdependencies between structural sizing patterns and optimal control surface layouts, for both static and dynamic aeroelastic physics.

  10. Topology-optimized metasurfaces: impact of initial geometric layout.

    Science.gov (United States)

    Yang, Jianji; Fan, Jonathan A

    2017-08-15

    Topology optimization is a powerful iterative inverse design technique in metasurface engineering and can transform an initial layout into a high-performance device. With this method, devices are optimized within a local design phase space, making the identification of suitable initial geometries essential. In this Letter, we examine the impact of initial geometric layout on the performance of large-angle (75 deg) topology-optimized metagrating deflectors. We find that when conventional metasurface designs based on dielectric nanoposts are used as initial layouts for topology optimization, the final devices have efficiencies around 65%. In contrast, when random initial layouts are used, the final devices have ultra-high efficiencies that can reach 94%. Our numerical experiments suggest that device topologies based on conventional metasurface designs may not be suitable to produce ultra-high-efficiency, large-angle metasurfaces. Rather, initial geometric layouts with non-trivial topologies and shapes are required.

  11. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  12. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Science.gov (United States)

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  13. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  14. Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

    Science.gov (United States)

    Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

    2011-09-01

    Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

  15. An analog VLSI real time optical character recognition system based on a neural architecture

    International Nuclear Information System (INIS)

    Bo, G.; Caviglia, D.; Valle, M.

    1999-01-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

  16. An analog VLSI real time optical character recognition system based on a neural architecture

    Energy Technology Data Exchange (ETDEWEB)

    Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

    1999-03-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

  17. First results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

    1986-01-01

    A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

  18. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  19. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  20. ITER plant layout and site services

    International Nuclear Information System (INIS)

    Chuyanov, V.A.

    2000-01-01

    The ITER site has not yet been determined. Nevertheless, to develop a construction plan and a cost estimate, it is necessary to have a detailed layout of the buildings, structures and outdoor equipment integrated with the balance of plant service systems prototypical of large fusion power plants. These services include electrical power for magnet feeds and plasma heating systems, cryogenic and conventional cooling systems, compressed air, gas supplies, demineralized water, steam and drainage. Nuclear grade facilities are provided to handle tritium fuel and activated waste, as well as to prevent radiation exposure of workers and the public. To prevent interference between services of different types and for efficient arrangement of buildings, structures and equipment within the site area, a plan was developed which segregated different classes of services to four quadrants surrounding the tokamak building, placed at the approximate geographical centre of the site. The locations of the buildings on the generic site were selected to meet all design requirements at minimum total project cost. A similar approach was used to determine the locations of services above, at and below grade. The generic site plan can be adapted to the site selected for ITER without significant changes to the buildings or equipment. Some rearrangements may be required by site topography, resulting primarily in changes to the length of services that link the buildings and equipment. (author)

  1. A generic algorithm for layout of biological networks.

    Science.gov (United States)

    Schreiber, Falk; Dwyer, Tim; Marriott, Kim; Wybrow, Michael

    2009-11-12

    Biological networks are widely used to represent processes in biological systems and to capture interactions and dependencies between biological entities. Their size and complexity is steadily increasing due to the ongoing growth of knowledge in the life sciences. To aid understanding of biological networks several algorithms for laying out and graphically representing networks and network analysis results have been developed. However, current algorithms are specialized to particular layout styles and therefore different algorithms are required for each kind of network and/or style of layout. This increases implementation effort and means that new algorithms must be developed for new layout styles. Furthermore, additional effort is necessary to compose different layout conventions in the same diagram. Also the user cannot usually customize the placement of nodes to tailor the layout to their particular need or task and there is little support for interactive network exploration. We present a novel algorithm to visualize different biological networks and network analysis results in meaningful ways depending on network types and analysis outcome. Our method is based on constrained graph layout and we demonstrate how it can handle the drawing conventions used in biological networks. The presented algorithm offers the ability to produce many of the fundamental popular drawing styles while allowing the exibility of constraints to further tailor these layouts.

  2. Fast grid layout algorithm for biological networks with sweep calculation.

    Science.gov (United States)

    Kojima, Kaname; Nagasaki, Masao; Miyano, Satoru

    2008-06-15

    Properly drawn biological networks are of great help in the comprehension of their characteristics. The quality of the layouts for retrieved biological networks is critical for pathway databases. However, since it is unrealistic to manually draw biological networks for every retrieval, automatic drawing algorithms are essential. Grid layout algorithms handle various biological properties such as aligning vertices having the same attributes and complicated positional constraints according to their subcellular localizations; thus, they succeed in providing biologically comprehensible layouts. However, existing grid layout algorithms are not suitable for real-time drawing, which is one of requisites for applications to pathway databases, due to their high-computational cost. In addition, they do not consider edge directions and their resulting layouts lack traceability for biochemical reactions and gene regulations, which are the most important features in biological networks. We devise a new calculation method termed sweep calculation and reduce the time complexity of the current grid layout algorithms through its encoding and decoding processes. We conduct practical experiments by using 95 pathway models of various sizes from TRANSPATH and show that our new grid layout algorithm is much faster than existing grid layout algorithms. For the cost function, we introduce a new component that penalizes undesirable edge directions to avoid the lack of traceability in pathways due to the differences in direction between in-edges and out-edges of each vertex. Java implementations of our layout algorithms are available in Cell Illustrator. masao@ims.u-tokyo.ac.jp Supplementary data are available at Bioinformatics online.

  3. Neighboring Structure Visualization on a Grid-based Layout.

    Science.gov (United States)

    Marcou, G; Horvath, D; Varnek, A

    2017-10-01

    Here, we describe an algorithm to visualize chemical structures on a grid-based layout in such a way that similar structures are neighboring. It is based on structure reordering with the help of the Hilbert Schmidt Independence Criterion, representing an empirical estimate of the Hilbert-Schmidt norm of the cross-covariance operator. The method can be applied to any layout of bi- or three-dimensional shape. The approach is demonstrated on a set of dopamine D5 ligands visualized on squared, disk and spherical layouts. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Optimization of offshore wind farm layout in restricted zones

    DEFF Research Database (Denmark)

    Hou, Peng; Hu, Weihao; Chen, Cong

    2016-01-01

    In this research, an optimization method for offshore wind farm layout design is proposed. With the purpose of maximizing the energy production of the wind farm, the wind turbine (WT) positions are optimized. Due to the limitations of seabed conditions, marine traffic limitations or shipwrecks, etc...... with multiple adaptive methods (PSO-MAM) is adopted. The simulation results indicate that the proposed method can find a layout which outperforms a baseline layout of a reference wind farm (RWF) by increasing the energy yield by 3.84%....

  5. Large-scale double-patterning compliant layouts for DP engine and design rule development

    Science.gov (United States)

    Cork, Christopher; Lucas, Kevin; Hapli, John; Raffard, Herve; Barnes, Levi

    2009-03-01

    Double Patterning is seen as the prime technology to keep Moore's law on path while EUV technology is still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask technology[1], layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a production worthy double patterning engine with highly non-compliant layouts would put unrealistic expectations on that engine and provide metrics with poor applicability for eventual large designs. The true production use-case would be for designs that have at least some significant double patterning compliance already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and complexities were created that were double patterning compliant. To achieve this, a set of standard cells were generated, which individually and in isolation were double patterning compliant, for multiple layers simultaneously. This was done using the automated Standard Cell creation tool CadabraTM [4]. To create a full ASIC, however, additional constraints were added to make sure compliance would not be broken across the boundaries between standard cells when placed next to each other [5]. These standard cells were then used to create a variety of double patterning compliant ASICs using iCCompilerTM to place the cells correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such large datasets. A production worthy double patterning engine is ideally distributable over multiple processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results can be understood

  6. Quantitative comparison between two geometrical layouts for diffraction enhanced imaging

    International Nuclear Information System (INIS)

    Huang Wanxia; Yuan Qingxi; Zhu Peiping; Wang Junyue; Shu Hang; Chen Bo; Hu Tiandou; Wu Ziyu

    2007-01-01

    Diffraction enhanced imaging (DEI) with two crystals has been performed at the 4W1A beamline at Beijing Synchrotron Radiation Facility (BSRF). Two different crystal geometrical layouts were used to collect images, in the first layout the rotation axis of the crystal has been set perpendicular to the orbital plane while in the second the axis is parallel to the orbital plane. Performance comparison between the two layouts is discussed in terms of thermal expansion of the crystal induced by the heat load, imaging homogeneity, spatial resolution and angular resolution. From both experimental and theoretical data we show that the best images may be obtained with the optical layout in which the rotation axis of the crystals is perpendicular to the orbital plane

  7. Quantitative comparison between two geometrical layouts for diffraction enhanced imaging

    Energy Technology Data Exchange (ETDEWEB)

    Huang Wanxia; Yuan Qingxi [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China); Zhu Peiping [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China)], E-mail: zhupp@ihep.ac.cn; Wang Junyue; Shu Hang [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China); Chen Bo [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China); Department of Physics, University of Science and Technology of China, Hefei (China); Hu Tiandou [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China); Wu Ziyu [Beijing Synchrotron Radiation Facility, Institute of High Energy Physics, CAS, Beijing (China)], E-mail: wuzy@ihep.ac.cn

    2007-07-15

    Diffraction enhanced imaging (DEI) with two crystals has been performed at the 4W1A beamline at Beijing Synchrotron Radiation Facility (BSRF). Two different crystal geometrical layouts were used to collect images, in the first layout the rotation axis of the crystal has been set perpendicular to the orbital plane while in the second the axis is parallel to the orbital plane. Performance comparison between the two layouts is discussed in terms of thermal expansion of the crystal induced by the heat load, imaging homogeneity, spatial resolution and angular resolution. From both experimental and theoretical data we show that the best images may be obtained with the optical layout in which the rotation axis of the crystals is perpendicular to the orbital plane.

  8. Learning Layouts for Single-Page Graphic Designs.

    Science.gov (United States)

    O'Donovan, Peter; Agarwala, Aseem; Hertzmann, Aaron

    2014-08-01

    This paper presents an approach for automatically creating graphic design layouts using a new energy-based model derived from design principles. The model includes several new algorithms for analyzing graphic designs, including the prediction of perceived importance, alignment detection, and hierarchical segmentation. Given the model, we use optimization to synthesize new layouts for a variety of single-page graphic designs. Model parameters are learned with Nonlinear Inverse Optimization (NIO) from a small number of example layouts. To demonstrate our approach, we show results for applications including generating design layouts in various styles, retargeting designs to new sizes, and improving existing designs. We also compare our automatic results with designs created using crowdsourcing and show that our approach performs slightly better than novice designers.

  9. Optimal Material Layout - Applied on Reinforced Concrete Slabs

    DEFF Research Database (Denmark)

    Dollerup, Niels; Jepsen, Michael S.; Damkilde, Lars

    2015-01-01

    This paper introduces a general, finite-element-based optimisation tool for improving the material layout of concrete structures. The application presented is general and exemplified by material optimisation of reinforced concrete slabs. By utilising the optimisation tool, it is possible to deter......This paper introduces a general, finite-element-based optimisation tool for improving the material layout of concrete structures. The application presented is general and exemplified by material optimisation of reinforced concrete slabs. By utilising the optimisation tool, it is possible...... to determine the optimal material layout of a slab in the ultimate load state, based on simple inputs such as outer geometry, boundary conditions, multiple load cases and design domains. The material layout of the optimal design can either be fully orthotropic or isotropic, or a combination with a predefined...

  10. Factors driving the spatial layout of distribution channels

    NARCIS (Netherlands)

    Onstein, A.T.C.; Ektesaby, M.; Rezaei, J.; Tavasszy, L.A.; van Damme, D.A.

    2017-01-01

    Research statement Our study analyses the factors that drive decision-making on distribution structures, including the layout of distribution channels and the locations of distribution centres. Distribution is a primary firm activity, which strongly influences logistics costs and logistics

  11. KBS-3H layout adaptation 2007 for the Olkiluoto site

    International Nuclear Information System (INIS)

    Johansson, Erik; Hagros, Annika; Autio, Jorma; Kirkkomaeki, Timo

    2008-05-01

    As part of the KBS-3H design an Olkiluoto-specific layout of a KBS-3H repository has been produced based on the latest Olkiluoto data and the bedrock model. One of the main goals of this work was to support the evaluation of the feasibility of the one layer KBS-3H concept and to compare the layouts based on the KBS-3H and KBS-3V disposal concepts. The layout presented in this work can be considered only preliminary and involves a number of uncertainties. The percentage of unusable host rock was assumed to be 25% in this work but can change due to the further design of the different components of the KBS-3H disposal system and further development of the host rock criteria. The layout is also significantly affected by the layout-determining fracture zones. In this work 11 major (highly transmissive) fracture zones interpreted to intersect the -420 m level were considered deterministically. The KBS-3H layout requires a larger area than the KBS-3V repository and takes up most of the available area between the major fracture zones HZ20 and HZ21. This is mainly due to the long drift sections occupied by the compartment plugs (30 m) and the bentonite blocks in the blank zones (10 m), which reduces the usability of the host rock and results in larger canister spacings than in the KBS-3V concept, where the positioning of the deposition holes is very flexible and narrow zones with a moderate transmissivity usually have only a minor effect on the locations of the canisters. According to the results, there is enough bedrock in the current investigation area at central Olkiluoto for KBS-3H layout in one layer. However the layout takes up nearly all of the potential bedrock resource and therefore the result is quite sensitive to possible changes in the design bases

  12. Site selection and general layout of heap leaching uranium mill

    International Nuclear Information System (INIS)

    Zhang Chunmao; Rongfeng

    2011-01-01

    The site selection and general layout of uranium mill is an important work in the design and consultation stage of uranium mining and metallurgy's engineering construction. Based on the design practices, the principles and methods for the site selection and general layout of heap leaching uranium mill are analyzed and studied. Some problems which should be paid much attention to in the design are discussed in hopes of providing a useful reference for the design and consultation of similar projects. (authors)

  13. Influence of offshore wind farms layout on electrical resonances

    DEFF Research Database (Denmark)

    Holdyk, Andrzej; Holbøll, Joachim; Koldby, Erik

    2014-01-01

    , winding resistances and winding capacitances. Considering the frequency range of the present investigations, up to about 1 MHz, a lumped representation of the transformer characteristics was deemed sufficient. Breakers and capacitors are modelled as ideal components. The chosen wind farm layout includes...... ranges. The results show the influence of specific parameters being varied depending on the farm layout. In particular, cable lengths and transformer broad band characteristics turned out to have significant impact on the results....

  14. Student Perceptions of Textbook Layout and Learnability in Private Schools

    OpenAIRE

    Alefiyah Hoshangabadwala

    2015-01-01

    This research is an exploratory study that investigates students’ perceptions pertinent to textbook layout and organization and their evaluation of the textbook ease of learning. The objective is to find out whether the layout dynamics of school textbooks make any difference in students’ interest in studying or subject understanding. 73 students from various private schools of Pakistan’s cosmopolitan city Karachi responded to a quantitative survey that gauged their percep...

  15. Design and control of automated guided vehicle systems: A case study

    NARCIS (Netherlands)

    Li, Q.; Adriaansen, A.C.; Udding, J.T.; Pogromski, A.Y.

    2011-01-01

    In this paper, we study the design and control of automated guided vehicle (AGV) systems, with the focus on the quayside container transport in an automated container terminal. We first set up an event-driven model for an AGV system in the zone control framework. Then a number of layouts of the road

  16. Global scene layout modulates contextual learning in change detection.

    Science.gov (United States)

    Conci, Markus; Müller, Hermann J

    2014-01-01

    Change in the visual scene often goes unnoticed - a phenomenon referred to as "change blindness." This study examined whether the hierarchical structure, i.e., the global-local layout of a scene can influence performance in a one-shot change detection paradigm. To this end, natural scenes of a laid breakfast table were presented, and observers were asked to locate the onset of a new local object. Importantly, the global structure of the scene was manipulated by varying the relations among objects in the scene layouts. The very same items were either presented as global-congruent (typical) layouts or as global-incongruent (random) arrangements. Change blindness was less severe for congruent than for incongruent displays, and this congruency benefit increased with the duration of the experiment. These findings show that global layouts are learned, supporting detection of local changes with enhanced efficiency. However, performance was not affected by scene congruency in a subsequent control experiment that required observers to localize a static discontinuity (i.e., an object that was missing from the repeated layouts). Our results thus show that learning of the global layout is particularly linked to the local objects. Taken together, our results reveal an effect of "global precedence" in natural scenes. We suggest that relational properties within the hierarchy of a natural scene are governed, in particular, by global image analysis, reducing change blindness for local objects through scene learning.

  17. Estimating perception of scene layout properties from global image features.

    Science.gov (United States)

    Ross, Michael G; Oliva, Aude

    2010-01-08

    The relationship between image features and scene structure is central to the study of human visual perception and computer vision, but many of the specifics of real-world layout perception remain unknown. We do not know which image features are relevant to perceiving layout properties, or whether those features provide the same information for every type of image. Furthermore, we do not know the spatial resolutions required for perceiving different properties. This paper describes an experiment and a computational model that provides new insights on these issues. Humans perceive the global spatial layout properties such as dominant depth, openness, and perspective, from a single image. This work describes an algorithm that reliably predicts human layout judgments. This model's predictions are general, not specific to the observers it trained on. Analysis reveals that the optimal spatial resolutions for determining layout vary with the content of the space and the property being estimated. Openness is best estimated at high resolution, depth is best estimated at medium resolution, and perspective is best estimated at low resolution. Given the reliability and simplicity of estimating the global layout of real-world environments, this model could help resolve perceptual ambiguities encountered by more detailed scene reconstruction schemas.

  18. Layout design of user interface components with multiple objectives

    Directory of Open Access Journals (Sweden)

    Peer S.K.

    2004-01-01

    Full Text Available A multi-goal layout problem may be formulated as a Quadratic Assignment model, considering multiple goals (or factors, both qualitative and quantitative in the objective function. The facilities layout problem, in general, varies from the location and layout of facilities in manufacturing plant to the location and layout of textual and graphical user interface components in the human–computer interface. In this paper, we propose two alternate mathematical approaches to the single-objective layout model. The first one presents a multi-goal user interface component layout problem, considering the distance-weighted sum of congruent objectives of closeness relationships and the interactions. The second one considers the distance-weighted sum of congruent objectives of normalized weighted closeness relationships and normalized weighted interactions. The results of first approach are compared with that of an existing single objective model for example task under consideration. Then, the results of first approach and second approach of the proposed model are compared for the example task under consideration.

  19. Global scene layout modulates contextual learning in change detection

    Directory of Open Access Journals (Sweden)

    Markus eConci

    2014-02-01

    Full Text Available Change in the visual scene often goes unnoticed – a phenomenon referred to as ‘change blindness’. This study examined whether the hierarchical structure, i.e., the global-local layout of a scene can influence performance in a one-shot change detection paradigm. To this end, natural scenes of a laid breakfast table were presented, and observers were asked to locate the onset of a new local object. Importantly, the global structure of the scene was manipulated by varying the relations among objects in the scene layouts. The very same items were either presented as global-congruent (typical layouts or as global-incongruent (random arrangements. Change blindness was less severe for congruent than for incongruent displays, and this congruency benefit increased with the duration of the experiment. These findings show that global layouts are learned, supporting detection of local changes with enhanced efficiency. However, performance was not affected by scene congruency in a subsequent control experiment that required observers to localize a static discontinuity (i.e., an object that was missing from the repeated layouts. Our results thus show that learning of the global layout is particularly linked to the local objects. Taken together, our results reveal an effect of global precedence in natural scenes. We suggest that relational properties within the hierarchy of a natural scene are governed, in particular, by global image analysis, reducing change blindness for local objects through scene learning.

  20. Scalable force directed graph layout algorithms using fast multipole methods

    KAUST Repository

    Yunis, Enas Abdulrahman

    2012-06-01

    We present an extension to ExaFMM, a Fast Multipole Method library, as a generalized approach for fast and scalable execution of the Force-Directed Graph Layout algorithm. The Force-Directed Graph Layout algorithm is a physics-based approach to graph layout that treats the vertices V as repelling charged particles with the edges E connecting them acting as springs. Traditionally, the amount of work required in applying the Force-Directed Graph Layout algorithm is O(|V|2 + |E|) using direct calculations and O(|V| log |V| + |E|) using truncation, filtering, and/or multi-level techniques. Correct application of the Fast Multipole Method allows us to maintain a lower complexity of O(|V| + |E|) while regaining most of the precision lost in other techniques. Solving layout problems for truly large graphs with millions of vertices still requires a scalable algorithm and implementation. We have been able to leverage the scalability and architectural adaptability of the ExaFMM library to create a Force-Directed Graph Layout implementation that runs efficiently on distributed multicore and multi-GPU architectures. © 2012 IEEE.

  1. Design of underground layout and their maintenance

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Bok Youn; Kang, Chang Hee; Jo, Young Do; Lim, Sang Taek [Korea Institute of Geology Mining and Materials, Taejon (Korea, Republic of)

    1997-12-01

    Layout of underground structure has to be designed based on rock mechanical analysis and the concept of active support has to be adopted considering the large openings are requested to accommodate heavy duty diesel equipment in underground. Rock bolt and shotcrete will be the most applicable method to support such a large dimensional tunnels. 1) Direction: The main haulage way of the mines where diesel equipment are operating is ramp way system. For optimizing safety measures, and minimizing maintenance cost of the tunnels, it is strongly recommended that all the tunnels including ramp way, rooms and sublevels should be designed in parallel to the direction of principal stress and perpendicular to the direction of major discontinuity. 2) Inclination: Basically, the inclination of the ramp way depends on the specification of the equipment, but 10-15% is usual. The steep inclination needs less initial investment but there will be an adverse effects such as higher operating and maintenance costs. 3) Profile (Cross section): The maximum dimension of the equipment operating in local mines appeared 12.8m long, 3.705m wide and 3.68m high. Considering the dimension, the requested profile simply can be calculated to 4m x 4m, but it should be decided according to the regulated minimum clearances from the walls and roof. The minimum inner curvature radius of the tunnels should be more than 5.2m, and in this case, the tunnel width of the curved zone should be more than 5.5m. 4) Sight distance and braking distance: For the safe operation of the equipment, the sight distance must be longer than braking distance, so that the driver can hold up the equipment safely after finding the obstacles in front of him. The maximum braking distance without heating of brake shoe is 60m. 5) Support and maintenance: Due to the large dimensional tunnels where diesel equipment are operating, the conventional supporting system is not applicable. Therefore, the active support concept should be

  2. Using discrete event simulation to change from a functional layout to a cellular layout in an auto parts industry

    Directory of Open Access Journals (Sweden)

    Thiago Buselato Maurício

    2015-07-01

    Full Text Available This paper presents a discrete event simulation employed in a Brazilian automotive company. There was a huge waste caused by one family scrap. It was believed one reason was the company functional layout. In this case, changing from current to cellular layout, employee synergy and knowledge about this family would increase. Due to the complexity for dimensioning a new cellular layout, mainly because of batch size and client’s demand variation. In this case, discrete event simulation was used, which made possible to introduce those effects improving accuracy in final results. This accuracy will be shown by comparing results obtained with simulation and without it (as company used to do. To conclude, cellular layout was responsible for increasing 15% of productivity, reducing lead-time in 7 days and scrap in 15% for this family.

  3. Home Automation

    OpenAIRE

    Ahmed, Zeeshan

    2010-01-01

    In this paper I briefly discuss the importance of home automation system. Going in to the details I briefly present a real time designed and implemented software and hardware oriented house automation research project, capable of automating house's electricity and providing a security system to detect the presence of unexpected behavior.

  4. Automatic yield-line analysis of slabs using discontinuity layout optimization.

    Science.gov (United States)

    Gilbert, Matthew; He, Linwei; Smith, Colin C; Le, Canh V

    2014-08-08

    The yield-line method of analysis is a long established and extremely effective means of estimating the maximum load sustainable by a slab or plate. However, although numerous attempts to automate the process of directly identifying the critical pattern of yield-lines have been made over the past few decades, to date none has proved capable of reliably analysing slabs of arbitrary geometry. Here, it is demonstrated that the discontinuity layout optimization (DLO) procedure can successfully be applied to such problems. The procedure involves discretization of the problem using nodes inter-connected by potential yield-line discontinuities, with the critical layout of these then identified using linear programming. The procedure is applied to various benchmark problems, demonstrating that highly accurate solutions can be obtained, and showing that DLO provides a truly systematic means of directly and reliably automatically identifying yield-line patterns. Finally, since the critical yield-line patterns for many problems are found to be quite complex in form, a means of automatically simplifying these is presented.

  5. 32 CFR 553.7 - Design and layout of Army national cemeteries.

    Science.gov (United States)

    2010-07-01

    ... 32 National Defense 3 2010-07-01 2010-07-01 true Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

  6. SIMPLIFIED MATHEMATICAL MODEL OF SMALL SIZED UNMANNED AIRCRAFT VEHICLE LAYOUT

    Directory of Open Access Journals (Sweden)

    2016-01-01

    Full Text Available Strong reduction of new aircraft design period using new technology based on artificial intelligence is the key problem mentioned in forecasts of leading aerospace industry research centers. This article covers the approach to devel- opment of quick aerodynamic design methods based on artificial intelligence neural system. The problem is being solved for the classical scheme of small sized unmanned aircraft vehicle (UAV. The principal parts of the method are the mathe- matical model of layout, layout generator of this type of aircraft is built on aircraft neural networks, automatic selection module for cleaning variety of layouts generated in automatic mode, robust direct computational fluid dynamics method, aerodynamic characteristics approximators on artificial neural networks.Methods based on artificial neural networks have intermediate position between computational fluid dynamics methods or experiments and simplified engineering approaches. The use of ANN for estimating aerodynamic characteris-tics put limitations on input data. For this task the layout must be presented as a vector with dimension not exceeding sev-eral hundred. Vector components must include all main parameters conventionally used for layouts description and com- pletely replicate the most important aerodynamics and structural properties.The first stage of the work is presented in the paper. Simplified mathematical model of small sized UAV was developed. To estimate the range of geometrical parameters of layouts the review of existing vehicle was done. The result of the work is the algorithm and computer software for generating the layouts based on ANN technolo-gy. 10000 samples were generated and the dataset containig geometrical and aerodynamic characteristics of layoutwas created.

  7. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  8. Initial beam test results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Adolphsen, C.; Litke, A.; Schwarz, A.

    1986-01-01

    Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

  9. New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

    Energy Technology Data Exchange (ETDEWEB)

    Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

    1983-07-01

    This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

  10. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  11. Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

    International Nuclear Information System (INIS)

    Jones, W.F.; Byars, L.G.; Casey, M.E.

    1988-01-01

    A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

  12. FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

    International Nuclear Information System (INIS)

    Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

    1998-01-01

    We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

  13. Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

    1985-01-01

    The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  14. An efficient biological pathway layout algorithm combining grid-layout and spring embedder for complicated cellular location information.

    Science.gov (United States)

    Kojima, Kaname; Nagasaki, Masao; Miyano, Satoru

    2010-06-18

    Graph drawing is one of the important techniques for understanding biological regulations in a cell or among cells at the pathway level. Among many available layout algorithms, the spring embedder algorithm is widely used not only for pathway drawing but also for circuit placement and www visualization and so on because of the harmonized appearance of its results. For pathway drawing, location information is essential for its comprehension. However, complex shapes need to be taken into account when torus-shaped location information such as nuclear inner membrane, nuclear outer membrane, and plasma membrane is considered. Unfortunately, the spring embedder algorithm cannot easily handle such information. In addition, crossings between edges and nodes are usually not considered explicitly. We proposed a new grid-layout algorithm based on the spring embedder algorithm that can handle location information and provide layouts with harmonized appearance. In grid-layout algorithms, the mapping of nodes to grid points that minimizes a cost function is searched. By imposing positional constraints on grid points, location information including complex shapes can be easily considered. Our layout algorithm includes the spring embedder cost as a component of the cost function. We further extend the layout algorithm to enable dynamic update of the positions and sizes of compartments at each step. The new spring embedder-based grid-layout algorithm and a spring embedder algorithm are applied to three biological pathways; endothelial cell model, Fas-induced apoptosis model, and C. elegans cell fate simulation model. From the positional constraints, all the results of our algorithm satisfy location information, and hence, more comprehensible layouts are obtained as compared to the spring embedder algorithm. From the comparison of the number of crossings, the results of the grid-layout-based algorithm tend to contain more crossings than those of the spring embedder algorithm due to

  15. Plant Layout Analysis by Computer Simulation for Electronic Manufacturing Service Plant

    OpenAIRE

    Visuwan D.; Phruksaphanrat B

    2014-01-01

    In this research, computer simulation is used for Electronic Manufacturing Service (EMS) plant layout analysis. The current layout of this manufacturing plant is a process layout, which is not suitable due to the nature of an EMS that has high-volume and high-variety environment. Moreover, quick response and high flexibility are also needed. Then, cellular manufacturing layout design was determined for the selected group of products. Systematic layout planning (SLP) was used to analyze and de...

  16. A flexible layout design method for passive micromixers.

    Science.gov (United States)

    Deng, Yongbo; Liu, Zhenyu; Zhang, Ping; Liu, Yongshun; Gao, Qingyong; Wu, Yihui

    2012-10-01

    This paper discusses a flexible layout design method of passive micromixers based on the topology optimization of fluidic flows. Being different from the trial and error method, this method obtains the detailed layout of a passive micromixer according to the desired mixing performance by solving a topology optimization problem. Therefore, the dependence on the experience of the designer is weaken, when this method is used to design a passive micromixer with acceptable mixing performance. Several design disciplines for the passive micromixers are considered to demonstrate the flexibility of the layout design method for passive micromixers. These design disciplines include the approximation of the real 3D micromixer, the manufacturing feasibility, the spacial periodic design, and effects of the Péclet number and Reynolds number on the designs obtained by this layout design method. The capability of this design method is validated by several comparisons performed between the obtained layouts and the optimized designs in the recently published literatures, where the values of the mixing measurement is improved up to 40.4% for one cycle of the micromixer.

  17. The Influence of Environmental Spatial Layout on Perceived Lightness

    Science.gov (United States)

    Kanari, Kei; Inagami, Makoto; Kaneko, Hirohiko

    2011-01-01

    It is obvious that perceived lightness of a surface depends on the surrounding luminance distribution in 2D and 3D. These effects are usually explained by the mechanisms at relatively low level of visual system. However, there seems to be a relation between the illuminance and spatial layout of the scene regardless of the surrounding luminance distribution. If this is valid, perceived lightness of a surface in the scene could be influenced by the spatial layout in the scene. In this research, we investigated the relation between the perceived lightness of surface and the spatial layout of the scene. The subject matched the lightness of test patch presented on a natural picture with various spatial layout to that of comparison stimulus presented on a uniform gray background. The mean luminance of the surround stimuli were the same and the local contrast between the text patch and the surround was kept constant. Results showed that the perceived lightness of a stimulus depended on the spatial structure presented in the background. This result indicates that the spatial layout of the scene is related to the illuminance of that and influenced on perceived lightness.

  18. Genetic Algorithm (GA)-Based Inclinometer Layout Optimization.

    Science.gov (United States)

    Liang, Weijie; Zhang, Ping; Chen, Xianping; Cai, Miao; Yang, Daoguo

    2015-04-17

    This paper presents numerical simulation results of an airflow inclinometer with sensitivity studies and thermal optimization of the printed circuit board (PCB) layout for an airflow inclinometer based on a genetic algorithm (GA). Due to the working principle of the gas sensor, the changes of the ambient temperature may cause dramatic voltage drifts of sensors. Therefore, eliminating the influence of the external environment for the airflow is essential for the performance and reliability of an airflow inclinometer. In this paper, the mechanism of an airflow inclinometer and the influence of different ambient temperatures on the sensitivity of the inclinometer will be examined by the ANSYS-FLOTRAN CFD program. The results show that with changes of the ambient temperature on the sensing element, the sensitivity of the airflow inclinometer is inversely proportional to the ambient temperature and decreases when the ambient temperature increases. GA is used to optimize the PCB thermal layout of the inclinometer. The finite-element simulation method (ANSYS) is introduced to simulate and verify the results of our optimal thermal layout, and the results indicate that the optimal PCB layout greatly improves (by more than 50%) the sensitivity of the inclinometer. The study may be useful in the design of PCB layouts that are related to sensitivity improvement of gas sensors.

  19. Vertical Object Layout and Compression for Fixed Heaps

    Science.gov (United States)

    Titzer, Ben L.; Palsberg, Jens

    Research into embedded sensor networks has placed increased focus on the problem of developing reliable and flexible software for microcontroller-class devices. Languages such as nesC [10] and Virgil [20] have brought higher-level programming idioms to this lowest layer of software, thereby adding expressiveness. Both languages are marked by the absence of dynamic memory allocation, which removes the need for a runtime system to manage memory. While nesC offers code modules with statically allocated fields, arrays and structs, Virgil allows the application to allocate and initialize arbitrary objects during compilation, producing a fixed object heap for runtime. This paper explores techniques for compressing fixed object heaps with the goal of reducing the RAM footprint of a program. We explore table-based compression and introduce a novel form of object layout called vertical object layout. We provide experimental results that measure the impact on RAM size, code size, and execution time for a set of Virgil programs. Our results show that compressed vertical layout has better execution time and code size than table-based compression while achieving more than 20% heap reduction on 6 of 12 benchmark programs and 2-17% heap reduction on the remaining 6. We also present a formalization of vertical object layout and prove tight relationships between three styles of object layout.

  20. Layout design in order to improve efficiency in manufacturing

    Science.gov (United States)

    Siregar, I.; Tarigan, U.; Nasution, T. H.

    2018-02-01

    This research was conducted at the company that produces bobbins and ream type cigarette paper. Problems that found on the production process is the back and forth (back tracking) movement. Back and forth (back tracking) movement extending the total distance moved by the material and increase the total moment of transfer materials thus reducing the efficiency of the transfer of materials in the production process. The purpose of this study is to give design for the layout of production facilities in the company, so that the expected production produced by the company can reach the targets set by the management company. The method used in this research is the Graph-Based Construction and Travel Chart Method. The results of the analysis of the proposed layout with Graph-Based Construction was selected with a total value that is equal to the moment of transfer of 780 758 m / year. This result is better than the actual layout in the amount of 1,021,038.12 meters / year and the results of the method Travel Alternative Chart I of 826.236,60 meters/year, Alternative II of 1.004.433,56 meters / year, and Alternative III for 828,467.12 meters/year. The design layout of Graph-Based Construction material increases the transfer efficiency for 23.53%. With this layout proposal, expected production capacity will be increased along with the shortening of the distance of the displacement that must be passed by the material to be processed.

  1. Optimization of offshore wind farm layout in restricted zones

    International Nuclear Information System (INIS)

    Hou, Peng; Hu, Weihao; Chen, Cong; Soltani, Mohsen; Chen, Zhe

    2016-01-01

    In this research, an optimization method for offshore wind farm layout design is proposed. With the purpose of maximizing the energy production of the wind farm, the wind turbine (WT) positions are optimized. Due to the limitations of seabed conditions, marine traffic limitations or shipwrecks, etc., the WTs are expected to be placed outside specific areas. Based on this fact, a restriction zone concept is proposed in this paper and implemented with the penalty function method. In order to find a feasible solution, a recent proposed stochastic algorithm, particle swarm optimization algorithm with multiple adaptive methods (PSO-MAM) is adopted. The simulation results indicate that the proposed method can find a layout which outperforms a baseline layout of a reference wind farm (RWF) by increasing the energy yield by 3.84%. - Highlights: • The offshore restricted area concept is proposed. • The recent developed PSO-MAM algorithm is arranged to optimize the layout. • The penalty function method is adopted to help find the feasible solution. • The optimized layout increases energy yields 3.84% than reference wind farm.

  2. Conceptual layout design of CFETR Hot Cell Facility

    Energy Technology Data Exchange (ETDEWEB)

    Gong, Zheng, E-mail: gongz@mail.ustc.edu.cn [University of Science and Technology of China, Hefei 230026 (China); Institute of Plasma Physics, Chinese Academy of Sciences, Hefei (China); Qi, Minzhong, E-mail: qiminzhong@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei (China); Cheng, Yong, E-mail: chengyong@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei (China); Song, Yuntao, E-mail: songyt@ipp.ac.cn [University of Science and Technology of China, Hefei 230026 (China); Institute of Plasma Physics, Chinese Academy of Sciences, Hefei (China)

    2015-11-15

    Highlights: • This article proposed a conceptual layout design for CFETR. • The design principles are to support efficient maintenance to ensure the realization of high duty time. • The preliminary maintenance process and logistics are described in detail. • Life cycle management, maneuverability, risk and safety are in the consideration of design. - Abstract: CFETR (China Fusion Engineering Test Reactor) is new generation of Tokomak device beyond EAST in China. An overview of hot cell layout design for CFETR has been proposed by ASIPP&USTC. Hot Cell, as major auxiliary facility, not only plays a pivotal role in supporting maintenance to meet the requirements of high duty time 0.3–0.5 but also supports installation and decommissioning. Almost all of the Tokomak devices are lateral handling internal components like ITER and JET, but CFETR maintain the blanket module from 4 vertical ports, which is quite a big challenge for the hot cell layout design. The activated in-vessel components and several diagnosis instruments will be repaired and refurbished in the Hot Cell Facility, so the appropriate layout is very important to the Hot Cell Facility to ensure the high duty time, it is divided into different parts equipped with a variety of RH equipment and diagnosis devices based on the functional requirements. The layout of the Hot Cell Facility should make maintenance process more efficient and reliable, and easy to service and rescue when a sudden events taking place, that is the capital importance issue considered in design.

  3. Joint Graph Layouts for Visualizing Collections of Segmented Meshes

    KAUST Repository

    Ren, Jing; Schneider, Jens; Ovsjanikov, Maks; Wonka, Peter

    2017-01-01

    We present a novel and efficient approach for computing joint graph layouts and then use it to visualize collections of segmented meshes. Our joint graph layout algorithm takes as input the adjacency matrices for a set of graphs along with partial, possibly soft, correspondences between nodes of different graphs. We then use a two stage procedure, where in the first step, we extend spectral graph drawing to include a consistency term so that a collection of graphs can be handled jointly. Our second step extends metric multi-dimensional scaling with stress majorization to the joint layout setting, while using the output of the spectral approach as initialization. Further, we discuss a user interface for exploring a collection of graphs. Finally, we show multiple example visualizations of graphs stemming from collections of segmented meshes and we present qualitative and quantitative comparisons with previous work.

  4. Effect of layout on surge line thermal stratification

    International Nuclear Information System (INIS)

    Lai Jianyong; Huang Wei

    2011-01-01

    In order to analyze and evaluate the effect of layout on the thermal stratification for PWR Pressurizer surge line, numerical simulation by Computational Fluid Dynamics (CFD) method is taken on 6 kinds of layout improvement with 2 improvement schemes, i.e., increasing the obliquity of quasi horizontal section and adding a vertical pipe between the quasi horizontal section and next elbow, and the maximum temperature differences of quasi horizontal section of surge line of various layouts under different flowrate are obtained. The comparison shows that, the increasing of the obliquity of quasi horizontal section can mitigate the thermal stratification phenomena but can not eliminate this phenomena, while the adding of a vertical pipe between the quasi horizontal section and next elbow can effectively mitigate and eliminate the thermal stratification phenomena. (authors)

  5. How the global layout of the mask influences masking strength.

    Science.gov (United States)

    Ghose, Tandra; Hermens, Frouke; Herzog, Michael H

    2012-12-10

    In visual backward masking, the perception of a target is influenced by a trailing mask. Masking is usually explained by local interactions between the target and the mask representations. However, recently it has been shown that the global spatial layout of the mask rather than its local structure determines masking strength (Hermens & Herzog, 2007). Here, we varied the mask layout by spatial, luminance, and temporal cues. We presented a vernier target followed by a mask with 25 elements. Performance deteriorated when the length of the two mask elements neighboring the target vernier was doubled. However, when the length of every second mask element was doubled, performance improved. When the luminance of the neighboring elements was doubled, performance also deteriorated but no improvement in performance was observed when every second element had a double luminance. For temporal manipulations, a complex nonmonotonic masking function was observed. Hence, changes in the mask layout by spatial, luminance, and temporal cues lead to highly different results.

  6. Production layout improvement in emergency services: a participatory approach.

    Science.gov (United States)

    Zanatta, Mateus; Amaral, Fernando Gonçalves

    2012-01-01

    Volunteer fire department is a service that responds emergency situations in places where there are no military emergency services. These services need to respond quickly, because time is often responsible for the operation success besides work environment and setup time interfere with the prompt response to these calls and care efficiency. The layout design is one factor that interferes with the quick setup. In this case, the spaces arrangement can result in excessive or unnecessary movements; also the equipment provision may hinder the selection and collection of these or even create movement barriers for the workers. This work created a new layout for the emergency assistance service, considering the human factors related to work through the task analysis and workers participation on the alternatives of improvement. The results showed an alternate layout with corridors and minimization of unusable sites, allowing greater flexibility and new possibilities of requirements.

  7. Analysis of Sequence Diagram Layout in Advanced UML Modelling Tools

    Directory of Open Access Journals (Sweden)

    Ņikiforova Oksana

    2016-05-01

    Full Text Available System modelling using Unified Modelling Language (UML is the task that should be solved for software development. The more complex software becomes the higher requirements are stated to demonstrate the system to be developed, especially in its dynamic aspect, which in UML is offered by a sequence diagram. To solve this task, the main attention is devoted to the graphical presentation of the system, where diagram layout plays the central role in information perception. The UML sequence diagram due to its specific structure is selected for a deeper analysis on the elements’ layout. The authors research represents the abilities of modern UML modelling tools to offer automatic layout of the UML sequence diagram and analyse them according to criteria required for the diagram perception.

  8. Optimization of Orchestral Layouts Based on Instrument Directivity Patterns

    Science.gov (United States)

    Stroud, Nathan Paul

    The experience of hearing an exceptional symphony orchestra perform in an excel- lent concert hall can be profound and moving, causing a level of excitement not often reached for listeners. Romantic period style orchestral music, recognized for validating the use of intense emotion for aesthetic pleasure, was the last significant development in the history of the orchestra. In an age where orchestral popularity is waning, the possibil- ity of evolving the orchestral sound in our modern era exists through the combination of our current understanding of instrument directivity patterns and their interaction with architectural acoustics. With the aid of wave field synthesis (WFS), newly proposed variations on orchestral layouts are tested virtually using a 64-channel WFS array. Each layout is objectively and subjectively compared for determination of which layout could optimize the sound of the orchestra and revitalize the excitement of the performance.

  9. Joint Graph Layouts for Visualizing Collections of Segmented Meshes

    KAUST Repository

    Ren, Jing

    2017-09-12

    We present a novel and efficient approach for computing joint graph layouts and then use it to visualize collections of segmented meshes. Our joint graph layout algorithm takes as input the adjacency matrices for a set of graphs along with partial, possibly soft, correspondences between nodes of different graphs. We then use a two stage procedure, where in the first step, we extend spectral graph drawing to include a consistency term so that a collection of graphs can be handled jointly. Our second step extends metric multi-dimensional scaling with stress majorization to the joint layout setting, while using the output of the spectral approach as initialization. Further, we discuss a user interface for exploring a collection of graphs. Finally, we show multiple example visualizations of graphs stemming from collections of segmented meshes and we present qualitative and quantitative comparisons with previous work.

  10. Ergonomics and simulation-based approach in improving facility layout

    Science.gov (United States)

    Abad, Jocelyn D.

    2018-02-01

    The use of the simulation-based technique in facility layout has been a choice in the industry due to its convenience and efficient generation of results. Nevertheless, the solutions generated are not capable of addressing delays due to worker's health and safety which significantly impact overall operational efficiency. It is, therefore, critical to incorporate ergonomics in facility design. In this study, workstation analysis was incorporated into Promodel simulation to improve the facility layout of a garment manufacturing. To test the effectiveness of the method, existing and improved facility designs were measured using comprehensive risk level, efficiency, and productivity. Results indicated that the improved facility layout generated a decrease in comprehensive risk level and rapid upper limb assessment score; an increase of 78% in efficiency and 194% increase in productivity compared to existing design and thus proved that the approach is effective in attaining overall facility design improvement.

  11. Optimization of Wind Farm Layout in Complex Terrain

    DEFF Research Database (Denmark)

    Xu, Chang; Yang, Jianchuan; Li, Chenqi

    2013-01-01

    Microscopic site selection for wind farms in complex terrain is a technological difficulty in the development of onshore wind farms. This paper presented a method for optimizing wind farm layout in complex terrain. This method employed Lissaman and Jensen wake models, took wind velocity distribut......Microscopic site selection for wind farms in complex terrain is a technological difficulty in the development of onshore wind farms. This paper presented a method for optimizing wind farm layout in complex terrain. This method employed Lissaman and Jensen wake models, took wind velocity...... are subject to boundary conditions and minimum distance conditions. The improved genetic algorithm (GA) for real number coding was used to search the optimal result. Then the optimized result was compared to the result from the experienced layout method. Results show the advantages of the present method...

  12. Student Perceptions of Textbook Layout and Learnability in Private Schools

    Directory of Open Access Journals (Sweden)

    Alefiyah Hoshangabadwala

    2015-06-01

    Full Text Available This research is an exploratory study that investigates students’ perceptions pertinent to textbook layout and organization and their evaluation of the textbook ease of learning. The objective is to find out whether the layout dynamics of school textbooks make any difference in students’ interest in studying or subject understanding. 73 students from various private schools of Pakistan’s cosmopolitan city Karachi responded to a quantitative survey that gauged their perceptions regarding textbook components such as paper, print, color, and textbook pedagogical features. Findings indicate that students rank print and color above paper quality, and that there is no particular relationship between a book layout and the actual use of textbooks.

  13. A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2005-07-01

    In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

  14. A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

    Science.gov (United States)

    Shi, Cong; Luo, Gang

    2018-04-01

    This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

  15. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    International Nuclear Information System (INIS)

    Jian Haifang; Shi Yin

    2009-01-01

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  16. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  17. A multi coding technique to reduce transition activity in VLSI circuits

    International Nuclear Information System (INIS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-01-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

  18. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  19. Built-in self-repair of VLSI memories employing neural nets

    Science.gov (United States)

    Mazumder, Pinaki

    1998-10-01

    The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

  20. Urban pattern: Layout design by hierarchical domain splitting

    KAUST Repository

    Yang, Yongliang; Wang, Jun; Vouga, Etienne; Wonka, Peter

    2013-01-01

    We present a framework for generating street networks and parcel layouts. Our goal is the generation of high-quality layouts that can be used for urban planning and virtual environments. We propose a solution based on hierarchical domain splitting using two splitting types: streamline-based splitting, which splits a region along one or multiple streamlines of a cross field, and template-based splitting, which warps pre-designed templates to a region and uses the interior geometry of the template as the splitting lines. We combine these two splitting approaches into a hierarchical framework, providing automatic and interactive tools to explore the design space.

  1. Urban pattern: Layout design by hierarchical domain splitting

    KAUST Repository

    Yang, Yongliang

    2013-11-06

    We present a framework for generating street networks and parcel layouts. Our goal is the generation of high-quality layouts that can be used for urban planning and virtual environments. We propose a solution based on hierarchical domain splitting using two splitting types: streamline-based splitting, which splits a region along one or multiple streamlines of a cross field, and template-based splitting, which warps pre-designed templates to a region and uses the interior geometry of the template as the splitting lines. We combine these two splitting approaches into a hierarchical framework, providing automatic and interactive tools to explore the design space.

  2. Collimator Layouts for HL-LHC in the Experimental Insertions

    CERN Document Server

    Bruce, R; Esposito, Luigi Salvatore; Jowett, John; Lechner, Anton; Quaranta, Elena; Redaelli, Stefano; Schaumann, Michaela; Skordis, Eleftherios; Eleanor Steele, G; Garcia Morales, H; Kwee-Hinzmann, Regina

    2015-01-01

    This paper presents the layout of collimators for HL-LHC in the experimental insertions. On the incoming beam, we propose to install additional tertiary collimators to protect potential new aperture bottlenecks in cells 4 and 5, which in addition reduce the experimental background. For the outgoing beam, the layout of the present LHC with three physics debris absorbers gives sufficient protection for highluminosity proton operation. However, collisional processes for heavy ions cause localized beam losses with the potential to quench magnets. To alleviate these losses, an installation of dispersion suppressor collimators is proposed.

  3. An Evolutionary Approach for Robust Layout Synthesis of MEMS

    DEFF Research Database (Denmark)

    Fan, Zhun; Wang, Jiachuan; Goodman, Erik

    2005-01-01

    The paper introduces a robust design method for layout synthesis of MEM resonators subject to inherent geometric uncertainties such as the fabrication error on the sidewall of the structure. The robust design problem is formulated as a multi-objective constrained optimisation problem after certain...... assumptions and treated with multiobjective genetic algorithm (MOGA), a special type of evolutionary computing approaches. Case study based on layout synthesis of a comb-driven MEM resonator shows that the approach proposed in this paper can lead to design results that meet the target performance and are less...

  4. Testing of polarimeter UVP layout on telescope AZT-2

    Science.gov (United States)

    Nevodovskyi, P. V.; Vidmachenko, A. P.; Morozhenko, O. V.

    2018-05-01

    Layout of on-board small-sized ultraviolet polarimeter was created. On its basis a ground version of the layout was prepared. It was installed on the AZT-2 telescope for carrying out special tests. With this device we investigated the possibility of determining the degree of polarization of the twilight glow of the Earth's atmosphere, and also worked out the observation methodology required for such work, and the basic principles of the implementation of this method. For this purpose, a special complex of auxiliary equipment was developed.

  5. Complete PCB design using OrCAD capture and layout

    CERN Document Server

    Mitzner, Kraig

    2011-01-01

    This book provides instruction on how to use the OrCAD design suite to design and manufacture printed circuit boards. The book is written for both students and practicing engineers who need a quick tutorial on how to use the software and who need in-depth knowledge of the capabilities and limitations of the software package. There are two goals the book aims to reach:The primary goal is to show the reader how to design a PCB using OrCAD Capture and OrCAD Layout. Capture is used to build the schematic diagram of the circuit, and Layout is used to design the circuit board so that

  6. Lithography-based automation in the design of program defect masks

    Science.gov (United States)

    Vakanas, George P.; Munir, Saghir; Tejnil, Edita; Bald, Daniel J.; Nagpal, Rajesh

    2004-05-01

    In this work, we are reporting on a lithography-based methodology and automation in the design of Program Defect masks (PDM"s). Leading edge technology masks have ever-shrinking primary features and more pronounced model-based secondary features such as optical proximity corrections (OPC), sub-resolution assist features (SRAF"s) and phase-shifted mask (PSM) structures. In order to define defect disposition specifications for critical layers of a technology node, experience alone in deciding worst-case scenarios for the placement of program defects is necessary but may not be sufficient. MEEF calculations initiated from layout pattern data and their integration in a PDM layout flow provide a natural approach for improvements, relevance and accuracy in the placement of programmed defects. This methodology provides closed-loop feedback between layout and hard defect disposition specifications, thereby minimizing engineering test restarts, improving quality and reducing cost of high-end masks. Apart from SEMI and industry standards, best-known methods (BKM"s) in integrated lithographically-based layout methodologies and automation specific to PDM"s are scarce. The contribution of this paper lies in the implementation of Design-For-Test (DFT) principles to a synergistic interaction of CAD Layout and Aerial Image Simulator to drive layout improvements, highlight layout-to-fracture interactions and output accurate program defect placement coordinates to be used by tools in the mask shop.

  7. Evidence-based ergonomics. A comparison of Japanese and American office layouts.

    Science.gov (United States)

    Noro, Kageyu; Fujimaki, Goroh; Kishi, Shinsuke

    2003-01-01

    There is a variety of alternatives in office layouts. Yet the theoretical basis and criteria for predicting how well these layouts accommodate employees are poorly understood. The objective of this study was to evaluate criteria for selecting office layouts. Intensive computer workers worked in simulated office layouts in a controlled experimental laboratory. Eye movement measures indicate that knowledge work requires both concentration and interaction. Findings pointed to one layout as providing optimum balance between these 2 requirements. Recommendations for establishing a theoretical basis and design criteria for selecting office layouts based on work style are suggested.

  8. CONTROLLABILITY OF TRADITIONAL NEIGHBORHOOD AND ITS SIMPLIFIED LAYOUT

    Directory of Open Access Journals (Sweden)

    M. Salim Ferwati

    2010-03-01

    Full Text Available Street hierarchy, as a way of presenting intended information, conforms to social rules that underlay architectural and urban designs to create public, semi-public, and semi-private. These social rules have the responsibility to convey necessary information about place to outsiders as well as to insiders. This research looks at urban spaces as physical structures that represent foci of attention of users and that are collectively a part of the social pattern framework. The argument of this study is that connectivity and forms of streets house certain social rules that intended to serve users, so that any changes in the street layout lead to changes in its social rules. As a case study, the complexity of a walled Arab neighborhood was examined through Sur Lawatyia, located in Muscat Governorate, Oman. By replacing the curvilinear and broken streets of this neighborhood with straight ones; a simplified street layout was derived. Then, a comparison of both street layouts was carried out through mapping, tabulation, charts, correlation test, and with reliance on the method of measurement of street control values introduced by Hillier and Hanson in 1984. The result was that the simple form is far short to be the representation of the space syntax of the traditional street layout.

  9. Seismic analysis of a reactor building with eccentric layout

    International Nuclear Information System (INIS)

    Itoh, T.; Deng, D.Z.F.; Lui, K.

    1987-01-01

    Conventional design for a reactor building in a high seismic area has adopted an essentially concentric layout in response to fear of excessive torsional effect due to horizontal seismic load on an eccentric plant. This concentric layout requirement generally results in an inflexible arrangement of the plant facilities and thus increases the plant volume. This study is performed to investigate the effect of eccentricity on the overall seismic structural response and to provide technical information in this regard to substantiate the volume reduction of the overall power plant. The plant layout is evolved from the Bechtel standard plan of a PWR plant by integrating the reactor building and the auxiliary building into a combined building supported on a common basemat. This plant layout is optimized for volume utilization and to reduce the length of piping systems. The mass centers at various elevations of the combined building do not coincide with the rigidity center (RC) of the respective floor and the geometric center of the basemat, thus creating an eccentric response of the building in a seismic environment. Therefore, the torsional effects of the structure have to be taken into account in the seismic analysis

  10. An online planning tool for designing terrace layouts

    Science.gov (United States)

    A web-based conservation planning tool, WebTERLOC (web-based Terrace Location Program), was developed to provide multiple terrace layout options using digital elevation model (DEM) and geographic information systems (GIS). Development of a terrace system is complicated by the time-intensive manual ...

  11. Why multicamp layouts? | BR | African Journal of Range and Forage ...

    African Journals Online (AJOL)

    Although it has become standard practice in Southern Africa to recommend grazing systems based on a maximum of five camps, there are indications that the use of multicamp layouts, employing a greater number of camps per herd, may increase the efficiency of animal production from natural veld. The basic advantage of ...

  12. Representing Spatial Layout According to Intrinsic Frames of Reference.

    Science.gov (United States)

    Xie, Chaoxiang; Li, Shiyi; Tao, Weidong; Wei, Yiping; Sun, Hong-Jin

    2017-01-01

    Mou and McNamara have suggested that object locations are represented according to intrinsic reference frames. In three experiments, we investigated the limitations of intrinsic reference frames as a mean to represent object locations in spatial memory. Participants learned the locations of seven or eight common objects in a rectangular room and then made judgments of relative direction based on their memory of the layout. The results of all experiments showed that when all objects were positioned regularly, judgments of relative direction were faster or more accurate for novel headings that were aligned with the primary intrinsic structure than for other novel headings; however, when one irregularly positioned object was added to the layout, this advantage was eliminated. The experiments further indicated that with a single view at study, participants could represent the layout from either an egocentric orientation or a different orientation, according to experimental instructions. Together, these results suggest that environmental reference frames and intrinsic axes can influence performance for novel headings, but their role in spatial memory depends on egocentric experience, layout regularity, and instructions.

  13. Modeling human-machine interactions for operations room layouts

    Science.gov (United States)

    Hendy, Keith C.; Edwards, Jack L.; Beevis, David

    2000-11-01

    The LOCATE layout analysis tool was used to analyze three preliminary configurations for the Integrated Command Environment (ICE) of a future USN platform. LOCATE develops a cost function reflecting the quality of all human-human and human-machine communications within a workspace. This proof- of-concept study showed little difference between the efficacy of the preliminary designs selected for comparison. This was thought to be due to the limitations of the study, which included the assumption of similar size for each layout and a lack of accurate measurement data for various objects in the designs, due largely to their notional nature. Based on these results, the USN offered an opportunity to conduct a LOCATE analysis using more appropriate assumptions. A standard crew was assumed, and subject matter experts agreed on the communications patterns for the analysis. Eight layouts were evaluated with the concepts of coordination and command factored into the analysis. Clear differences between the layouts emerged. The most promising design was refined further by the USN, and a working mock-up built for human-in-the-loop evaluation. LOCATE was applied to this configuration for comparison with the earlier analyses.

  14. Proximity search heuristics for wind farm optimal layout

    DEFF Research Database (Denmark)

    Fischetti, Martina; Monaci, Michele

    2016-01-01

    A heuristic framework for turbine layout optimization in a wind farm is proposed that combines ad-hoc heuristics and mixed-integer linear programming. In our framework, large-scale mixed-integer programming models are used to iteratively refine the current best solution according to the recently...

  15. FOOD safety and hygiene - Systematic layout planning of food processes

    NARCIS (Netherlands)

    Van Donk, DP; Gaalman, G

    2004-01-01

    Hygiene and food safety have been dealt with from different fields of science such as biology and health, and from different angles such as HACCP and GMP. Little systematically ordered knowledge is available for the analysis of a layout, taking hygienic factors into account. HACCP and GMP are

  16. Hydrodynamic Modelling and Layout Optimisation of Wave Energy Converter Arrays

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé

    2017-01-01

    in various positions and orientations are finally investigated. This thesis intends in this way to offer a practical approach to the analysis of wave energy converters when they operate together as an array and the optimal design of array layouts. The topics covered by the text include propagation of waves...

  17. A New Data Layout For Set Intersection on GPUs

    DEFF Research Database (Denmark)

    Amossen, Rasmus Resen; Pagh, Rasmus

    2011-01-01

    . However, GPUs require highly regular control flow and memory access patterns, and for this reason previous GPU methods for intersecting sets have used a simple bitmap representation. This representation requires excessive space on sparse data sets. In this paper we present a novel data layout, BATMAP...

  18. Preconceptual ABC design definition and system configuration layout: Appendix A

    International Nuclear Information System (INIS)

    1995-03-01

    The mission of the ABC system is to destroy as effectively as possible the fissile material inserted into the core without producing any new fissile material. The contents of this report are as follows: operating conditions for the steam-cycle ABC system; flow rates and component dimensions; drawings of the ABC layout; and impact of core design parameters on containment size

  19. Layout considerations for the PSB H- injection system

    CERN Document Server

    Aiba, M; Carli, C; Chanel, M; Fowler, A; Goddard, B; Weterings, W

    2009-01-01

    The layout of the PSB H- injection system is described, including the arguments for the geometry and the required equipment performance parameters. The longitudinal positions of the main elements are specified, together with the injected and circulating beam axes. The assumptions used in determining the geometry are listed.

  20. Product Category Layout and Organization: Retail Placement of Food Products

    NARCIS (Netherlands)

    Herpen, van E.

    2016-01-01

    This article discusses the placement of food products in retail stores, in particular how the placement of food products can influence how consumers perceive the store in general and these products in particular. It reviews the overall layout of the store, assortment organization, and shelf

  1. Preconceptual ABC design definition and system configuration layout

    International Nuclear Information System (INIS)

    Barthold, W.

    1995-03-01

    This document is the conceptual design document for the follow-on to the Molten Salt Breeder Reactor, known as the ABC type reactor. It addresses blanket design options, containment options, off-gas systems, drainage systems, and components/layouts of the primary, secondary, and tertiary systems, and it contains a number of diagrams for the configuration of the major systems

  2. Performance evaluation of cellular layouts : extension to DRC system contexts

    NARCIS (Netherlands)

    Suresh, NC; Gaalman, GJC

    This study involves a comparison of the performance of functional layouts (FL) and cellular manufacturing (CM) systems in a dual-resource-constrained( DRC) system context. Past studies of FL and CM have been based mostly on single-resource-constrained( SRC) systems. Recent studies have included

  3. Process automation

    International Nuclear Information System (INIS)

    Moser, D.R.

    1986-01-01

    Process automation technology has been pursued in the chemical processing industries and to a very limited extent in nuclear fuel reprocessing. Its effective use has been restricted in the past by the lack of diverse and reliable process instrumentation and the unavailability of sophisticated software designed for process control. The Integrated Equipment Test (IET) facility was developed by the Consolidated Fuel Reprocessing Program (CFRP) in part to demonstrate new concepts for control of advanced nuclear fuel reprocessing plants. A demonstration of fuel reprocessing equipment automation using advanced instrumentation and a modern, microprocessor-based control system is nearing completion in the facility. This facility provides for the synergistic testing of all chemical process features of a prototypical fuel reprocessing plant that can be attained with unirradiated uranium-bearing feed materials. The unique equipment and mission of the IET facility make it an ideal test bed for automation studies. This effort will provide for the demonstration of the plant automation concept and for the development of techniques for similar applications in a full-scale plant. A set of preliminary recommendations for implementing process automation has been compiled. Some of these concepts are not generally recognized or accepted. The automation work now under way in the IET facility should be useful to others in helping avoid costly mistakes because of the underutilization or misapplication of process automation. 6 figs

  4. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-01-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  5. Operation of a Fast-RICH Prototype with VLSI readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

    1994-04-01

    We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

  6. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  7. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  8. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  9. Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

    International Nuclear Information System (INIS)

    Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

    1992-01-01

    Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

  10. Real time track finding in a drift chamber with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-01-01

    In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

  11. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  12. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  13. A novel configurable VLSI architecture design of window-based image processing method

    Science.gov (United States)

    Zhao, Hui; Sang, Hongshi; Shen, Xubang

    2018-03-01

    Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

  14. Research of Digital Interface Layout Design based on Eye-tracking

    OpenAIRE

    Shao Jiang; Xue Chengqi; Wang Fang; Wang Haiyan; Tang Wencheng; Chen Mo; Kang Mingwu

    2015-01-01

    The aim of this paper is to improve the low service efficiency and unsmooth human-computer interaction caused by currently irrational layouts of digital interfaces for complex systems. Also, three common layout structures for digital interfaces are to be presented and five layout types appropriate for multilevel digital interfaces are to be summarized. Based on the eye tracking technology, an assessment was conducted in advantages and disadvantages of different layout types through subjects’ ...

  15. A combined approach of simulation and analytic hierarchy process in assessing production facility layouts

    Science.gov (United States)

    Ramli, Razamin; Cheng, Kok-Min

    2014-07-01

    One of the important areas of concern in order to obtain a competitive level of productivity in a manufacturing system is the layout design and material transportation system (conveyor system). However, changes in customers' requirements have triggered the need to design other alternatives of the manufacturing layout for existing production floor. Hence, this paper discusses effective alternatives of the process layout specifically, the conveyor system layout. Subsequently, two alternative designs for the conveyor system were proposed with the aims to increase the production output and minimize space allocation. The first proposed layout design includes the installation of conveyor oven in the particular manufacturing room based on priority, and the second one is the one without the conveyor oven in the layout. Simulation technique was employed to design the new facility layout. Eventually, simulation experiments were conducted to understand the performance of each conveyor layout design based on operational characteristics, which include predicting the output of layouts. Utilizing the Analytic Hierarchy Process (AHP), the newly and improved layout designs were assessed before the final selection was done. As a comparison, the existing conveyor system layout was included in the assessment process. Relevant criteria involved in this layout design problem were identified as (i) usage of space of each design, (ii) operator's utilization rates, (iii) return of investment (ROI) of the layout, and (iv) output of the layout. In the final stage of AHP analysis, the overall priority of each alternative layout was obtained and thus, a selection for final use by the management was made based on the highest priority value. This efficient planning and designing of facility layout in a particular manufacturing setting is able to minimize material handling cost, minimize overall production time, minimize investment in equipment, and optimize utilization of space.

  16. Distribution automation

    International Nuclear Information System (INIS)

    Gruenemeyer, D.

    1991-01-01

    This paper reports on a Distribution Automation (DA) System enhances the efficiency and productivity of a utility. It also provides intangible benefits such as improved public image and market advantages. A utility should evaluate the benefits and costs of such a system before committing funds. The expenditure for distribution automation is economical when justified by the deferral of a capacity increase, a decrease in peak power demand, or a reduction in O and M requirements

  17. Rearrangement of the layout of the welding equipment of a company in the metal mechanical sector using the Systematic Layout Planning method (SLP

    Directory of Open Access Journals (Sweden)

    Silvio Alexsandro Turati

    2016-06-01

    Full Text Available The correct physical layout is relevant to the operational efficiency of the company. This study proposes rearranging the layout of the welding equipment of a company in the metal mechanical sector, which is located in Araras/SP, aiming to improve the production workflow. The Systematic Layout Planning method (SLP was used, with the field research divided into steps: obtaining detailed information about the process and the product; meetings with stakeholders; determining inter-related activities; analyzing space requirements; developing a new layout. The new layout has space allocated for the purchasing of new machinery, the existing machinery has been redistributed by specialty, and the unloading of raw materials has been transferred to the shed, maximizing the use of overhead cranes and keeping the stock close to the warehouse. In addition, forklift traffic flow has decreased; new movement corridors were demarcated; and painting areas were isolated. In conclusion, the SLP method proved efficient in creating a layout.

  18. 29 CFR 1926.752 - Site layout, site-specific erection plan and construction sequence.

    Science.gov (United States)

    2010-07-01

    ... 29 Labor 8 2010-07-01 2010-07-01 false Site layout, site-specific erection plan and construction... Steel Erection § 1926.752 Site layout, site-specific erection plan and construction sequence. (a... strength or sufficient strength to support the loads imposed during steel erection. (c) Site layout. The...

  19. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This letter proposes a novel direct bonded copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect...

  20. Typography and layout of technical reports - Survey of current practices

    Science.gov (United States)

    Pinelli, T. E.; Cordle, V. M.; Mccullough, R.

    1985-01-01

    As part of a review of the NASA Langley Research Center scientific and technical information program, 50 technical reports from industry, research institutions, and government agencies were systematically examined and analyzed to determine current usage and practice in regard to (1) typography, including composition method, type style, type size, and margin treatment; (2) graphic design, including layout and imposition of material on the page; and (3) physical media, including paper, ink, and binding methods. The results indicate that approximately 50 percent of the reports were typeset, 70 percent used Roman (serif) type, 80 percent used 10- or 11-point type for text, 60 percent used a ragged right-hand margin, slightly more than half used paragraph indentation, 75 percent used a single-column layout, 65 percent had one or more figures or tables placed perpendicular to (not aligned with) the text, and perfect binding was the most frequently used binding method.

  1. An UI Layout Files Analyzer for Test Data Generation

    Directory of Open Access Journals (Sweden)

    Paul POCATILU

    2014-01-01

    Full Text Available Prevention actions (trainings, audits and inspections (tests, validations, code reviews are the crucial factors in achieving a high quality level for any software application simply because low investments in this area are leading to significant expenses in terms of corrective actions needed for defect fixing. Mobile applications testing involves the use of various tools and scenarios. An important process is represented by test data generation. This paper proposes a test data generator (TDG system for mobile applications using several sources for test data and it focuses on the UI layout files analyzer module. The proposed architecture aims to reduce time-to-market for mobile applications. The focus is on test data generators based on the source code, user interface layout files (using markup languages like XML or XAML and application specifications. In order to assure a common interface for test data generators, an XML or JSON-based language called Data Specification Language (DSL is proposed.

  2. VLSI Research

    Science.gov (United States)

    1984-04-01

    Interpretation of IMMEDIATE fields of instructions (except ldhi ): W (c) (d) (e) sssssssssssss s imml9 sssssssssssssssssss...s imml3 Destination REGISTER of a LDHI instruction: imml9 0000000000000 Data in REGISTERS when operated upon: 32-bit quantity...Oll x l OOOO OOOl calli sll OOlO getpsw sra xxzOOll getlpc srl OlOO putpsw ldhi OlOl and zzzOllO or ldxw stxw Olll xor

  3. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  4. Analysis tools for the interplay between genome layout and regulation.

    Science.gov (United States)

    Bouyioukos, Costas; Elati, Mohamed; Képès, François

    2016-06-06

    Genome layout and gene regulation appear to be interdependent. Understanding this interdependence is key to exploring the dynamic nature of chromosome conformation and to engineering functional genomes. Evidence for non-random genome layout, defined as the relative positioning of either co-functional or co-regulated genes, stems from two main approaches. Firstly, the analysis of contiguous genome segments across species, has highlighted the conservation of gene arrangement (synteny) along chromosomal regions. Secondly, the study of long-range interactions along a chromosome has emphasised regularities in the positioning of microbial genes that are co-regulated, co-expressed or evolutionarily correlated. While one-dimensional pattern analysis is a mature field, it is often powerless on biological datasets which tend to be incomplete, and partly incorrect. Moreover, there is a lack of comprehensive, user-friendly tools to systematically analyse, visualise, integrate and exploit regularities along genomes. Here we present the Genome REgulatory and Architecture Tools SCAN (GREAT:SCAN) software for the systematic study of the interplay between genome layout and gene expression regulation. SCAN is a collection of related and interconnected applications currently able to perform systematic analyses of genome regularities as well as to improve transcription factor binding sites (TFBS) and gene regulatory network predictions based on gene positional information. We demonstrate the capabilities of these tools by studying on one hand the regular patterns of genome layout in the major regulons of the bacterium Escherichia coli. On the other hand, we demonstrate the capabilities to improve TFBS prediction in microbes. Finally, we highlight, by visualisation of multivariate techniques, the interplay between position and sequence information for effective transcription regulation.

  5. Impact of risk analysis on ITER nuclear buildings layout

    International Nuclear Information System (INIS)

    Sabathe, Laurent; Lignini, Franck; Rodriguez-Rodrigo, Lina; Uzan-Elbez, Joelle; Girard, Jean-Philippe

    2007-01-01

    The internal layout of ITER nuclear buildings (Tokamak, Tritium, Hot cell and Radwaste buildings) is the result of an iterative process. Notwithstanding civil engineering requirements, technical and functional requirements for the processes housed in the buildings, the internal layout must also take into account safety requirements and workers protection requirements in normal, incidental and accidental conditions. Potential hazards and constraints result in the definition of various zonings. Each room is classified depending on the level of the risks induced by normal and incidental or accidental conditions: - radiological exposure to tritium, and activated products → radiological zoning; - exposure to beryllium (vacuum vessel blankets) → beryllium zoning; - exposure to electromagnetic fields during plasma shots → electromagnetic zoning; - fire hazard: fire compartmentalization; ·explosion hazard: anti-blast zoning; - waste treatment → waste zoning. Prevention of common mode failure due to internal hazards (fire, flooding, load drop...) for redundant safety important components is also taken into account by geographical separation or by installation of protections between components (either in the same room or preferably when possible by segregation in different rooms). The designer has also taken into account access requirements to equipments and circulation rules for personal, material and substances in ITER nuclear buildings. Risk analyses are performed in the Preliminary Safety Report in order to demonstrate that the layout of ITER nuclear buildings allows meeting the safety objectives and takes into account the requirements associated with the zonings classifications and complies with the regulation. When necessary, modifications are implemented in the design. For example, recent layout modifications are been studied in the tritium building: utility rooms (electrical supply) were transferred outside the radiological hazard zones. A direct access from

  6. Impact of risk analysis on ITER nuclear buildings internal layout

    International Nuclear Information System (INIS)

    Lignini, F.; Sabathe, L.; Rodriguez-Rodrigo, L.; Uzan-Elbez, J.; Girard, J.-P.

    2006-01-01

    The internal layout of ITER nuclear buildings (Tokamak, Tritium, Hot cell and Radwaste buildings) is the result of an iterative process. Notwithstanding civil engineering requirements, technical and functional requirements for the processes housed in the buildings, the internal layout must also take into account safety requirements and workers protection requirements in normal, incidental and accidental conditions. Potential hazards and constraints result in the definition of various zonings. Each room is classified depending on the level of risk induced by normal and incidental or accidental conditions : - radiological exposure to tritium, and activated products → radiological zoning - exposure to beryllium (vacuum vessel blankets) → beryllium zoning - exposure to electromagnetic fields during plasma shots → electromagnetic zoning - fire hazard : fire compartmentalisation - explosion hazard → anti-blast zoning - waste treatment → waste zoning Prevention of common mode failure due to internal hazards (fire, flooding, load drop ...) for redundant safety important components is also taken into account by geographical separation or by installation of protections between components (either in the same room or preferably when possible by segregation in different rooms). The designer also has to take into account access requirements to equipment and circulation rules for personal, material and substances in ITER nuclear buildings. Risk analyses are performed in the Preliminary Safety Report in order to demonstrate that the layout of ITER nuclear buildings allows to meet the safety objectives and takes into account the requirements associated with the zonings classifications and complies with the regulation. When necessary, modifications are implemented in the design. For example, recent layout modifications were included in the tritium building : utility rooms (electrical supply) were transferred outside the radiological hazard zones. A direct access from the

  7. Nuclear island buildings layout collaborative design platform development and application

    International Nuclear Information System (INIS)

    Chen Li; Huang Wenqiang

    2014-01-01

    Based on characteristics of nuclear island layout design, the large number files and complicated interface, for realizing collaborative design and fine management goal, Establish collaborative design platform, which includes the design task module, 3D design module, project management module. These three modules can package design input files, realize synchronous design and real-time track design drawings state, timely feedback between design, procurement, construction site. There is no design task delay due to tracking and has realized fine management of design. (authors)

  8. Doublet vs. FODO structure: beam dynamics and layout

    CERN Document Server

    Eshraqi, M; CERN. Geneva. BE Department

    2010-01-01

    A FoDo (singlet) structure is designed for the CERN Superconducting Proton LINAC. This architecture is compared to the baseline (doublet) architecture of SPL on the basis of its beam dynamics performance and the required investment. The sensitivity of both layouts to quadrupole gradient errors and misalignment is checked and a correction scheme for beam steering is proposed. Finally a single quad beam dilution scheme is studied and designed for the pilot beam dump.

  9. Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics.

    Science.gov (United States)

    1987-09-01

    level descrip- tion without human intervention. Although design rules and the layout function may not be checked, performance verification is still a...digital syvstems.- Proc. I1E1., vol. 69. no. 10. pp. 1200-1211. October 198 1. [2] A. Gupta, AT A circuit extractor." Proc. 20th Design Automiation

  10. Study of site layout in the Rokkasho site

    International Nuclear Information System (INIS)

    Sato, Kazuyoshi; Tamura, Kousaku; Yagenji, Akira; Sekiya, Shigeki; Takahashi, Hideo; Neyatani, Yuzuru; Uehara, Masaharu; Motohashi, Keiichi; Hashimoto, Masayoshi; Ogino, Shunji; Nagamatsu, Nobuhide

    2006-03-01

    The Final Design Report (FDR) of the International Thermonuclear Experimental Reactor (ITER) was published on July 2001 as a summary of the Engineering Design Activity (EDA). After the EDA, site dependent design has been investigated for the invitation of ITER toward Rokkasho Site (Iyasakadai area) in Aomori prefecture. This report describes the results of site layout of major buildings and structures of ITER in the Rokkasho-Site. The data of the ground near the site and the results of site dependent design in Japan were applied to this study. Through this study, the most appropriate site layout has been constructed with satisfaction of following conditions. (1) Bedrock level at the tokamak complex building is relatively high and it can be reduced the cost of excavation and foundation work. (2) Total amount of excavation soil for site preparation is minimized and the flexibility of the layout is ensured with flat ground level. (3) Accessibility of human and equipments, reduction of noise and vibration to the environment can be obtained. Total length of ducts and piping between buildings in site is minimized. (author)

  11. Camera Layout Design for the Upper Stage Thrust Cone

    Science.gov (United States)

    Wooten, Tevin; Fowler, Bart

    2010-01-01

    Engineers in the Integrated Design and Analysis Division (EV30) use a variety of different tools to aid in the design and analysis of the Ares I vehicle. One primary tool in use is Pro-Engineer. Pro-Engineer is a computer-aided design (CAD) software that allows designers to create computer generated structural models of vehicle structures. For the Upper State thrust cone, Pro-Engineer was used to assist in the design of a layout for two camera housings. These cameras observe the separation between the first and second stage of the Ares I vehicle. For the Ares I-X, one standard speed camera was used. The Ares I design calls for two separate housings, three cameras, and a lighting system. With previous design concepts and verification strategies in mind, a new layout for the two camera design concept was developed with members of the EV32 team. With the new design, Pro-Engineer was used to draw the layout to observe how the two camera housings fit with the thrust cone assembly. Future analysis of the camera housing design will verify the stability and clearance of the camera with other hardware present on the thrust cone.

  12. CiSE: a circular spring embedder layout algorithm.

    Science.gov (United States)

    Dogrusoz, Ugur; Belviranli, Mehmet E; Dilek, Alptug

    2013-06-01

    We present a new algorithm for automatic layout of clustered graphs using a circular style. The algorithm tries to determine optimal location and orientation of individual clusters intrinsically within a modified spring embedder. Heuristics such as reversal of the order of nodes in a cluster and swap of neighboring node pairs in the same cluster are employed intermittently to further relax the spring embedder system, resulting in reduced inter-cluster edge crossings. Unlike other algorithms generating circular drawings, our algorithm does not require the quotient graph to be acyclic, nor does it sacrifice the edge crossing number of individual clusters to improve respective positioning of the clusters. Moreover, it reduces the total area required by a cluster by using the space inside the associated circle. Experimental results show that the execution time and quality of the produced drawings with respect to commonly accepted layout criteria are quite satisfactory, surpassing previous algorithms. The algorithm has also been successfully implemented and made publicly available as part of a compound and clustered graph editing and layout tool named CHISIO.

  13. Coherent image layout using an adaptive visual vocabulary

    Science.gov (United States)

    Dillard, Scott E.; Henry, Michael J.; Bohn, Shawn; Gosink, Luke J.

    2013-03-01

    When querying a huge image database containing millions of images, the result of the query may still contain many thousands of images that need to be presented to the user. We consider the problem of arranging such a large set of images into a visually coherent layout, one that places similar images next to each other. Image similarity is determined using a bag-of-features model, and the layout is constructed from a hierarchical clustering of the image set by mapping an in-order traversal of the hierarchy tree into a space-filling curve. This layout method provides strong locality guarantees so we are able to quantitatively evaluate performance using standard image retrieval benchmarks. Performance of the bag-of-features method is best when the vocabulary is learned on the image set being clustered. Because learning a large, discriminative vocabulary is a computationally demanding task, we present a novel method for efficiently adapting a generic visual vocabulary to a particular dataset. We evaluate our clustering and vocabulary adaptation methods on a variety of image datasets and show that adapting a generic vocabulary to a particular set of images improves performance on both hierarchical clustering and image retrieval tasks.

  14. Lower-Temperature Subsurface Layout and Ventilation Concepts

    International Nuclear Information System (INIS)

    Christine L. Linden; Edward G. Thomas

    2001-01-01

    This analysis combines work scope identified as subsurface facility (SSF) low temperature (LT) Facilities System and SSF LT Ventilation System in the Technical Work Plan for Subsurface Design Section FY 01 Work Activities (CRWMS M and O 2001b, pp. 6 and 7, and pp. 13 and 14). In accordance with this technical work plan (TWP), this analysis is performed using AP-3.10Q, Analyses and Models. It also incorporates the procedure AP-SI.1Q, Software Management. The purpose of this analysis is to develop an overall subsurface layout system and the overall ventilation system concepts that address a lower-temperature operating mode for the Monitored Geologic Repository (MGR). The objective of this analysis is to provide a technical design product that supports the lower-temperature operating mode concept for the revision of the system description documents and to provide a basis for the system description document design descriptions. The overall subsurface layout analysis develops and describes the overall subsurface layout, including performance confirmation facilities (also referred to as Test and Evaluation Facilities) for the Site Recommendation design. This analysis also incorporates current program directives for thermal management

  15. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  16. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This paper proposes a novel Direct Bonded Copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect......, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate on the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical...

  17. Virtual automation.

    Science.gov (United States)

    Casis, E; Garrido, A; Uranga, B; Vives, A; Zufiaurre, C

    2001-01-01

    Total laboratory automation (TLA) can be substituted in mid-size laboratories by a computer sample workflow control (virtual automation). Such a solution has been implemented in our laboratory using PSM, software developed in cooperation with Roche Diagnostics (Barcelona, Spain), to this purpose. This software is connected to the online analyzers and to the laboratory information system and is able to control and direct the samples working as an intermediate station. The only difference with TLA is the replacement of transport belts by personnel of the laboratory. The implementation of this virtual automation system has allowed us the achievement of the main advantages of TLA: workload increase (64%) with reduction in the cost per test (43%), significant reduction in the number of biochemistry primary tubes (from 8 to 2), less aliquoting (from 600 to 100 samples/day), automation of functional testing, drastic reduction of preanalytical errors (from 11.7 to 0.4% of the tubes) and better total response time for both inpatients (from up to 48 hours to up to 4 hours) and outpatients (from up to 10 days to up to 48 hours). As an additional advantage, virtual automation could be implemented without hardware investment and significant headcount reduction (15% in our lab).

  18. Analytical Tools for Functional Assessment of Architectural Layouts

    Science.gov (United States)

    Bąkowski, Jarosław

    2017-10-01

    Functional layout of the building, understood as a layout or set of the facility rooms (or groups of rooms) with a system of internal communication, creates an environment and a place of mutual relations between the occupants of the object. Achieving optimal (from the occupants’ point of view) spatial arrangement is possible through activities that often go beyond the stage of architectural design. Adopted in the architectural design, most often during trial and error process or on the basis of previous experience (evidence-based design), functional layout is subject to continuous evaluation and dynamic changing since the beginning of its use. Such verification of the occupancy phase allows to plan future, possible transformations, as well as to develop model solutions for use in other settings. In broader terms, the research hypothesis is to examine whether and how the collected datasets concerning the facility and its utilization can be used to develop methods for assessing functional layout of buildings. In other words, if it is possible to develop an objective method of assessing functional layouts basing on a set of buildings’ parameters: technical, technological and functional ones and whether the method allows developing a set of tools enhancing the design methodology of complex functional objects. By linking the design with the construction phase it is possible to build parametric models of functional layouts, especially in the context of sustainable design or lean design in every aspect: ecological (by reducing the property’s impact on environment), economic (by optimizing its cost) and social (through the implementation of high-performance work environment). Parameterization of size and functional connections of the facility become part of the analyses, as well as the element of model solutions. The “lean” approach means the process of analysis of the existing scheme and consequently - finding weak points as well as means for eliminating these

  19. Research of Digital Interface Layout Design based on Eye-tracking

    Directory of Open Access Journals (Sweden)

    Shao Jiang

    2015-01-01

    Full Text Available The aim of this paper is to improve the low service efficiency and unsmooth human-computer interaction caused by currently irrational layouts of digital interfaces for complex systems. Also, three common layout structures for digital interfaces are to be presented and five layout types appropriate for multilevel digital interfaces are to be summarized. Based on the eye tracking technology, an assessment was conducted in advantages and disadvantages of different layout types through subjects’ search efficiency. Based on data and results, this study constructed a matching model which is appropriate for multilevel digital interface layout and verified the fact that the task element is a significant and important aspect of layout design. A scientific experimental model of research on digital interfaces for complex systems is provided. Both data and conclusions of the eye movement experiment provide a reference for layout designs of interfaces for complex systems with different task characteristics.

  20. Automated fuel fabrication- a vision comes true

    International Nuclear Information System (INIS)

    Hemantha Rao, G.V.S.; Prakash, M.S.; Setty, C.R.P.; Gupta, U.C.

    1997-01-01

    When New Uranium Fuel Assembly Project at Nuclear Fuel Complex (NFC) begins production, its operator will have equipment provided with intramachine handling systems working automatically by pressing a single button. Additionally simple low cost inter machine handling systems will further help in critical areas. All these inter and intra machine handling systems will result in improved reliability, productivity and quality. The fault diagnostics, mimics and real time data acquisition systems make the plant more operator friendly. The paper deals with the experience starting from layout, selection of product carriers, different handling systems, the latest technology and the integration of which made the vision on automation in fuel fabrication come true. (author)

  1. Analog integrated circuit design automation placement, routing and parasitic extraction techniques

    CERN Document Server

    Martins, Ricardo; Horta, Nuno

    2017-01-01

    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures...

  2. Automating Finance

    Science.gov (United States)

    Moore, John

    2007-01-01

    In past years, higher education's financial management side has been riddled with manual processes and aging mainframe applications. This article discusses schools which had taken advantage of an array of technologies that automate billing, payment processing, and refund processing in the case of overpayment. The investments are well worth it:…

  3. Library Automation.

    Science.gov (United States)

    Husby, Ole

    1990-01-01

    The challenges and potential benefits of automating university libraries are reviewed, with special attention given to cooperative systems. Aspects discussed include database size, the role of the university computer center, storage modes, multi-institutional systems, resource sharing, cooperative system management, networking, and intelligent…

  4. Wendelstein 7-X Torus Hall Layout and System Integration

    International Nuclear Information System (INIS)

    Hartmann, D.; Damiani, C.; Hartfuss, H.-J.; Krampitz, R.; Neuner, U.

    2006-01-01

    Wendelstein 7-X is an experimental fusion device presently under construction in Greifswald, Germany, to study the stellarator concept at reactor relevant parameters und steady-state conditions. The heart of the machine consists of the torus that houses the superconducting coils and the plasma vacuum vessel. It is located nearly in the center of a 30 m x 30 m x 20 m hall. A large number of components need to be placed in close proximity of the torus to provide the system with the required means, e.g. cryogenic gases, cooling water, electricity, and to integrate it with the peripheral diagnostic and heating components. The arrangement of these components has to be supported by suitable structures, and has to be optimized to allow for installation, maintenance, and repair. In addition, space has to be provided for escape routes and for sufficient distance between components that could negatively influence each other's performance, etc. The layout of the components has been done over many years using 3D CAD software. It was based on simple geometric models of the components and of the additionally required space. Presently the layout design is being detailed and updated by replacing the original coarse models with more refined estimates or - in some cases - with as-built models. All interface requirements are carefully taken into account. Detailed routing was specified for the cryo and cooling water supply lines whose design and installation is outsourced. Due to the limited space available and severely restricted access during experimental campaigns, the requirement to put auxiliary components like electronic racks into the torus hall is being queried. The paper summarizes the present state of the component layout in the torus hall, and how the peripheral supply, diagnostics, and heating systems are integrated into the machine. (author)

  5. [Land layout for lake tourism based on ecological restraint].

    Science.gov (United States)

    Wang, Jian-Ying; Li, Jiang-Feng; Zou, Li-Lin; Liu, Shi-Bin

    2012-10-01

    To avoid the decrease and deterioration of lake wetlands and the other ecological issues such as lake water pollution that were caused by the unreasonable exploration of lake tourism, a land layout for the tourism development of Liangzi Lake with the priority of ecological security pattern was proposed, based on the minimal cumulative resistance model and by using GIS technology. The study area was divided into four ecological function zones, i. e., core protection zone, ecological buffer zone, ecotone zone, and human activity zone. The core protection zone was the landscape region of ecological source. In the protection zone, new tourism land was forbidden to be increased, and some of the existing fundamental tourism facilities should be removed while some of them should be upgraded. The ecological buffer zone was the landscape region with resistance value ranged from 0 to 4562. In the buffer zone, expansion of tourism land should be forbidden, the existing tourism land should be downsized, and human activities should be isolated from ecological source by converting the human environment to the natural environment as far as possible. The ecotone zone was the landscape region with resistance value ranged from 4562 to 30797. In this zone, the existing tourism land was distributed in patches, tourism land could be expanded properly, and the lake forestry ecological tourism should be developed widely. The human activity zone was the landscape region with resistance value ranged from 30797 to 97334, which would be the key area for the land layout of lake tourism. It was suggested that the land layout for tourism with the priority of landscape ecological security pattern would be the best choice for the lake sustainable development.

  6. Design Methodology of Process Layout considering Various Equipment Types for Large scale Pyro processing Facility

    International Nuclear Information System (INIS)

    Yu, Seung Nam; Lee, Jong Kwang; Lee, Hyo Jik

    2016-01-01

    At present, each item of process equipment required for integrated processing is being examined, based on experience acquired during the Pyropocess Integrated Inactive Demonstration Facility (PRIDE) project, and considering the requirements and desired performance enhancement of KAPF as a new facility beyond PRIDE. Essentially, KAPF will be required to handle hazardous materials such as spent nuclear fuel, which must be processed in an isolated and shielded area separate from the operator location. Moreover, an inert-gas atmosphere must be maintained, because of the radiation and deliquescence of the materials. KAPF must also achieve the goal of significantly increased yearly production beyond that of the previous facility; therefore, several parts of the production line must be automated. This article presents the method considered for the conceptual design of both the production line and the overall layout of the KAPF process equipment. This study has proposed a design methodology that can be utilized as a preliminary step for the design of a hot-cell-type, large-scale facility, in which the various types of processing equipment operated by the remote handling system are integrated. The proposed methodology applies to part of the overall design procedure and contains various weaknesses. However, if the designer is required to maximize the efficiency of the installed material-handling system while considering operation restrictions and maintenance conditions, this kind of design process can accommodate the essential components that must be employed simultaneously in a general hot-cell system

  7. Demonstration of automated robotic workcell for hazardous waste characterization

    International Nuclear Information System (INIS)

    Holliday, M.; Dougan, A.; Gavel, D.; Gustaveson, D.; Johnson, R.; Kettering, B.; Wilhelmsen, K.

    1993-02-01

    An automated robotic workcell to classify hazardous waste stream items with previously unknown characteristics has been designed, tested and demonstrated The object attributes being quantified are radiation signature, metal content, and object orientation and volume. The multi sensor information is used to make segregation decisions plus do automatic grasping of objects. The work-cell control program uses an off-line programming system by Cimetrix Inc. as a server to do both simulation control as well as actual hardware control of the workcell. This paper will discuss the overall workcell layout, sensor specifications, workcell supervisory control, 2D vision based automated grasp planning and object classification algorithms

  8. Wind conditions in urban layout - Numerical and experimental research

    Science.gov (United States)

    Poćwierz, Marta; Zielonko-Jung, Katarzyna

    2018-01-01

    This paper presents research which compares the numerical and the experimental results for different cases of airflow around a few urban layouts. The study is concerned mostly with the analysis of parameters, such as pressure and velocity fields, which are essential in the building industry. Numerical simulations have been performed by the commercial software Fluent, with the use of a few different turbulence models, including popular k-ɛ, k-ɛ realizable or k-ω. A particular attention has been paid to accurate description of the conditions on the inlet and the selection of suitable computing grid. The pressure measurement near buildings and oil visualization were undertaken and described accordingly.

  9. The Influence of Classroom Layout on Children's English Learning Development

    Institute of Scientific and Technical Information of China (English)

    林琬媚

    2016-01-01

    Nowadays, more and more Children English Training organization developed, all the parents and teachers also want to improve the children's English. So the parents will find the organization where the teachers are better in teaching. They will motive a lot of imagine and acquire many information which you can not know. If we can care more about this point from the children, may be it also can help children to learn English well. This essay aims at how does classroom Layout influence the children to learn English well and let the children love this environment.

  10. DESIGNING OF TOWN SKYLINE ON THE STAGE OF GENERAL LAYOUT

    Directory of Open Access Journals (Sweden)

    Yu. N. Kishik

    2007-01-01

    Full Text Available It is proposed to consider an aggregation of such active elements of town structure as multistoreyed dominants to be used as a basis for designing skyline of a large town on the stage of its general layout. Some interrelated principles, namely: spatial integration, subordination, nature consistence, succession are formulated for improvement of their spatial organization. Every principle takes down any general property of the network of vertical accents which is formed as a system. The obtained principles of the system organization of the multistoreyed dominants are checked while designing Grodno skyline. 

  11. Energy efficient LED layout optimization for near-uniform illumination

    Science.gov (United States)

    Ali, Ramy E.; Elgala, Hany

    2016-09-01

    In this paper, we consider the problem of designing energy efficient light emitting diodes (LEDs) layout while satisfying the illumination constraints. Towards this objective, we present a simple approach to the illumination design problem based on the concept of the virtual LED. We formulate a constrained optimization problem for minimizing the power consumption while maintaining a near-uniform illumination throughout the room. By solving the resulting constrained linear program, we obtain the number of required LEDs and the optimal output luminous intensities that achieve the desired illumination constraints.

  12. Effects of Optimizing the Scan-Path on Scanning Keyboards with QWERTY-Layout for English Text.

    Science.gov (United States)

    Sandnes, Frode Eika; Medola, Fausto Orsi

    2017-01-01

    Scanning keyboards can be essential tools for individuals with reduced motor function. However, most research addresses layout optimization. Learning new layouts is time-consuming. This study explores the familiar QWERTY layout with alternative scanning paths intended for English text. The results show that carefully designed scan-paths can help QWERTY nearly match optimized layouts in performance.

  13. High-Quality Ultra-Compact Grid Layout of Grouped Networks.

    Science.gov (United States)

    Yoghourdjian, Vahan; Dwyer, Tim; Gange, Graeme; Kieffer, Steve; Klein, Karsten; Marriott, Kim

    2016-01-01

    Prior research into network layout has focused on fast heuristic techniques for layout of large networks, or complex multi-stage pipelines for higher quality layout of small graphs. Improvements to these pipeline techniques, especially for orthogonal-style layout, are difficult and practical results have been slight in recent years. Yet, as discussed in this paper, there remain significant issues in the quality of the layouts produced by these techniques, even for quite small networks. This is especially true when layout with additional grouping constraints is required. The first contribution of this paper is to investigate an ultra-compact, grid-like network layout aesthetic that is motivated by the grid arrangements that are used almost universally by designers in typographical layout. Since the time when these heuristic and pipeline-based graph-layout methods were conceived, generic technologies (MIP, CP and SAT) for solving combinatorial and mixed-integer optimization problems have improved massively. The second contribution of this paper is to reassess whether these techniques can be used for high-quality layout of small graphs. While they are fast enough for graphs of up to 50 nodes we found these methods do not scale up. Our third contribution is a large-neighborhood search meta-heuristic approach that is scalable to larger networks.

  14. Comparative study T-type and I-type layout of PWR nuclear power plants

    International Nuclear Information System (INIS)

    Eko Rudi Iswanto and Siti Alimah

    2010-01-01

    Determining plant layout is one of the five major stages during the life time of a nuclear power plant. Some important factors that affect in the selecting of plant layout are availability of infrastructure, economic aspects, social aspects, public and environment safety, and also easy to do. Another factor to be considered is requirements as seismic design, which refers to the principles of good security workers, communities and the environment of radiological risks. There are many layout types of nuclear power plant, two of them are T-type layout and I-type layout. Each type of the plant layout has advantage and disadvantage, therefore this study is to understand them. Good layout is able to provide a high level of security against earthquakes. In term of earthquake design, I-type layout has a higher security level than T-type layout. Therefore, I-type layout can be a good choice for PWR nuclear power plants 1000 MWe that will be built in Indonesia. (author)

  15. The importance of layout and configuration data for flexibility during commissionning and operation of the LHC machine protection systems

    CERN Document Server

    Mariethoz, Julien; Le Roux, Pascal; Bernard, Frederic; Harrison, Robert; Zerlauth, Markus

    2006-01-01

    Due to the large stored energies in both magnets and particle beams, the Large Hadron Collider (LHC) requires a large inventory of machine protection systems, as e.g. powering interlock systems, based on a series of distributed industrial controllers for the protection of the more than 10'000 normal and superconducting magnets. Such systems are required to be at the same time fast, reliable and secure but also flexible and configurable to allow for automated commissioning, remote monitoring and optimization during later operation. Based on the generic hardware architecture of the LHC machine protection systems presented at EPAC 2002 [2] and ICALEPS 2003, the use of configuration data for protection systems in view of the required reliability and safety is discussed. To achieve the very high level of reliability, it is required to use a coherent description of the layout of the accelerator components and of the associated machine protection architecture and their logical interconnections. Mechanisms to guarant...

  16. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  17. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  18. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  19. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  20. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  1. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  2. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  3. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Science.gov (United States)

    McEwan, Alistair; van Schaik, André

    2003-12-01

    The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  4. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  5. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Science.gov (United States)

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  6. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  7. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Directory of Open Access Journals (Sweden)

    Alistair McEwan

    2003-06-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  8. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  9. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  10. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  11. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  12. CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

    International Nuclear Information System (INIS)

    Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

    1996-01-01

    In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

  13. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  14. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  15. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  16. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  17. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  18. Neonatal Intensive Care Unit Layout and Nurses' Work.

    Science.gov (United States)

    Doede, Megan; Trinkoff, Alison M; Gurses, Ayse P

    2018-01-01

    Neonatal intensive care units (NICUs) remain one of the few areas in hospitals that still use an open bay (OPBY) design for patient stays greater than 24 hr, housing multiple infants, staff, and families in one large room. This creates high noise levels, contributes to the spread of infection, and affords families little privacy. These problems have given rise to the single-family room NICU. This represents a significant change in the care environment for nurses. This literature review answers the question: When compared to OPBY layout, how does a single family room layout impact neonatal nurses' work? Thirteen studies published between 2006 and 2015 were located. Many studies reported both positive and negative effects on nurses' work and were therefore sorted by their cited advantages and disadvantages. Advantages included improved quality of the physical environment; improved quality of patient care; improved parent interaction; and improvements in nurse job satisfaction, stress, and burnout. Disadvantages included decreased interaction among the NICU patient care team, increased nurse workload, decreased visibility on the unit, and difficult interactions with family. This review suggests that single-family room NICUs introduce a complex situation in which trade-offs occur for nurses, most prominently the trade-off between visibility and privacy. Additionally, the literature is clear on what elements of nurses' work are impacted, but how the built environment influences these elements, and how these elements interact during nurses' work, is not as well understood. The current level of research and directions for future research are also discussed.

  19. Methodologies for optimizing ROP detector layout for CANDU (registered) reactors

    Energy Technology Data Exchange (ETDEWEB)

    Kastanya, Doddy, E-mail: kastanyd@aecl.c [Reactor Core Physics Branch, Atomic Energy of Canada Limited, 2251 Speakman Drive, Mississauga, ON, L5K 1B2 (Canada); Caxaj, Victor [Reactor Core Physics Branch, Atomic Energy of Canada Limited, 2251 Speakman Drive, Mississauga, ON, L5K 1B2 (Canada)

    2011-01-15

    The regional overpower protection (ROP) systems protect CANDU (registered) reactors against overpower in the fuel that would reduce the safety margin-to-dryout. Both a localized power peaking within the core (for example, as a result of certain reactivity device configuration) or a general increase in the core power level during a slow-loss-of-regulation (SLOR) event could cause overpower in the fuel. This overpower could lead to fuel sheath dryout. In the CANDU (registered) 600 MW (CANDU 6) design, there are two ROP systems in the core, one for each fast-acting shutdown systems. Each ROP system includes a number of fast-responding, self-powered flux detectors suitably distributed throughout the core within vertical and horizontal assemblies. Traditionally, the placement of these detectors was done using a method called the detector layout optimization (DLO). A new methodology for designing the detector layout for the ROP system has been developed recently. The new method, called the DETPLASA algorithm, utilizes the simulated annealing (SA) technique to optimize the placement of the detectors in the core. Both methodologies will be discussed in detail in this paper. Numerical examples are employed to better illustrate how each method works. Results from some sensitivity studies on three SA parameters are also presented.

  20. The Layout of Power and Space in Jingdezhen Imperial Factory

    Directory of Open Access Journals (Sweden)

    Zhan Jia

    2014-12-01

    Full Text Available This paper, by referring to the archaeological reports and local gazetteers and comparing images of porcelain wares, makes a comprehensive and in-depth analysis of the layout of power and space in Jingdezhen Imperial Factory according to its geography, geomancy, security management, space regulation, architectural features, production characteristics and production layout. It contends that the Imperial Factory which integrates porcelain making factory with local government is the embodiment of absolute monarchy in ceramic culture. The factory is located on Zhushan mountain, the center of Jingdezhen’s industry, business and transportation. Being at the center, it gives off an air of prestige and majesty, overlooking dominantly the surrounding private kilns. It has also turned the political system into power operation, setting up not only workshops but also administrative offices. By taking advantage of the best resources, it has produced porcelain for imperial family and court. Its specialized production has solved the contradiction between complicated technology and numerous procedures of production. The shape, color and pattern of the porcelain wares are strictly stipulated and the best of the best wares are demanded. Hence the porcelain production is featured with longest firing, largest scale, superb craftsmanship, and best kinds of wares. All of these reveal the process and rule power and space are intersected and different cultures overlapped.

  1. Aircraft Cockpit Ergonomic Layout Evaluation Based on Uncertain Linguistic Multiattribute Decision Making

    Directory of Open Access Journals (Sweden)

    Junxuan Chen

    2014-03-01

    Full Text Available In the view of the current cockpit information interaction, facilities and other characteristics are increasingly multifarious; the early layout evaluation methods based on single or partial components, often cause comprehensive evaluation unilateral, leading to the problems of long development period and low efficiency. Considering the fuzziness of ergonomic evaluation and diversity of evaluation information attributes, we refine and build an evaluation system based on the characteristics of the current cockpit man-machine layout and introduce the different types of uncertain linguistic multiple attribute combination decision making (DTULDM method in the cockpit layout evaluation process. Meanwhile, we also establish an aircraft cockpit ergonomic layout evaluation model. Finally, an experiment about cockpit layout evaluation is given, and the result demonstrates that the proposed method about cockpit ergonomic layout evaluation is feasible and effective.

  2. Incorporating Workflow Interference in Facility Layout Design: The Quartic Assignment Problem

    OpenAIRE

    Wen-Chyuan Chiang; Panagiotis Kouvelis; Timothy L. Urban

    2002-01-01

    Although many authors have noted the importance of minimizing workflow interference in facility layout design, traditional layout research tends to focus on minimizing the distance-based transportation cost. This paper formalizes the concept of workflow interference from a facility layout perspective. A model, formulated as a quartic assignment problem, is developed that explicitly considers the interference of workflow. Optimal and heuristic solution methodologies are developed and evaluated.

  3. Research on Layout Optimization of Urban Circle Solid Waste Transfer and Disposal Stations

    OpenAIRE

    Xuhui Li; Gangyan Li; Guowen Sun; Huiping Shi; Bao’an Yang

    2013-01-01

    Based on the Systematic Layout Planning theory and the analysis of transfer stations’ technological processes, a layout optimization model for solid waste transfer and disposal stations was made. The operating units’ layout of the solid waste transfer and disposal stations was simulated and optimized using the genetic algorithm, which could achieve reasonable technological processes, the smallest floor space and the lowest construction cost. The simulation result can also direct t...

  4. Study on comprehensive evaluation model for nuclear power plant control room layout

    International Nuclear Information System (INIS)

    Zhu Yiming; Liu Yuan; Fan Huixian

    2010-01-01

    A comprehensive evaluation model for layout of the main control room of nuclear power plants was proposed. Firstly the design scope and principle for the layout of the main control room were defined based on the standards, and then the index system for the comprehensive evaluation was established. Finally, comprehensive evaluation was carried out for the layout design by applying the fuzzy comprehensive evaluation method in the index system. (authors)

  5. Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

    Energy Technology Data Exchange (ETDEWEB)

    Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

    1992-01-01

    The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

  6. Calculation of calibration factors and layout criteria for gamma scanning of waste drums from nuclear plants

    International Nuclear Information System (INIS)

    Inder Schmitten, W.; Sohnius, B.; Wehner, E.

    1990-01-01

    This paper present a procedure to calculate calibration factors for converting the measured gamma rate of waste drums into activity content and a layout and free release measurement criterion for waste drums. A computer program is developed that simulates drum scanning technique, which calculates calibration factors and eliminates laborious experimental measurements. The calculated calibration factors exhibit good agreement with experimentally determined values. By checking the calculated calibration factors for trial equipment layouts (including the waste drum and the scanning facility) using the layout and free release measurement criterion, a layout can be achieved that clearly determines whether there can be free release of a waste drum

  7. The performance of the ATLAS initial detector layout for B-physics channels

    International Nuclear Information System (INIS)

    Epp, B.; Ghete, V.M.; Kuhn, D.; Zhang, Y.J.

    2004-01-01

    At the start-up of LHC one expects parts of the ATLAS detector to be missing. This layout is called initial layout, whereas the fully staged detector is called complete layout. B-physics channels were simulated, reconstructed and analyzed using the software tools of ATLAS data challenge-1 (DC1). The performance of the detector with respect to quantities relevant to the analysis of the B s → D s π channel and the validation of the full chain generation-simulation-reconstruction-analysis were evaluated for the initial and complete layout. (author)

  8. Coplanar Electrode Layout Optimized for Increased Sensitivity for Electrical Impedance Spectroscopy

    DEFF Research Database (Denmark)

    Clausen, Casper Hyttel; Skands, Gustav Erik; Bertelsen, Christian Vinther

    2015-01-01

    This work describes an improvement in the layout of coplanar electrodes for electrical impedance spectroscopy. We have developed, fabricated, and tested an improved electrode layout, which improves the sensitivity of an impedance flow cytometry chip. The improved chip was experimentally tested...... and compared to a chip with a conventional electrode layout. The improved chip was able to discriminate 0.5 mu m beads from 1 mu m as opposed to the conventional chip. Furthermore, finite element modeling was used to simulate the improvements in electrical field density and uniformity between the electrodes...... of the new electrode layout. Good agreement was observed between the model and the obtained experimental results....

  9. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  10. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

    Science.gov (United States)

    Breuer, M. A.; Carlan, A. J.

    1982-10-01

    Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

  11. Methodology for bus layout for topological quantum error correcting codes

    Energy Technology Data Exchange (ETDEWEB)

    Wosnitzka, Martin; Pedrocchi, Fabio L.; DiVincenzo, David P. [RWTH Aachen University, JARA Institute for Quantum Information, Aachen (Germany)

    2016-12-15

    Most quantum computing architectures can be realized as two-dimensional lattices of qubits that interact with each other. We take transmon qubits and transmission line resonators as promising candidates for qubits and couplers; we use them as basic building elements of a quantum code. We then propose a simple framework to determine the optimal experimental layout to realize quantum codes. We show that this engineering optimization problem can be reduced to the solution of standard binary linear programs. While solving such programs is a NP-hard problem, we propose a way to find scalable optimal architectures that require solving the linear program for a restricted number of qubits and couplers. We apply our methods to two celebrated quantum codes, namely the surface code and the Fibonacci code. (orig.)

  12. Mechanic- and hydraulic shock-absorbers - layout, construction, operation experience

    International Nuclear Information System (INIS)

    Kluge, M.

    1981-01-01

    The problem lies in the protection of the flexible supported power plant components against undesired sudden movements. Various shock absorbing systems are at disposal in this case: Mechanical and hydraulic shock absorbers, whose functioning systems are shown in figures. The operation experience showed a series of deficiencies, as demonstrated on various figures. In order to avoid them, some important recommendations are given. Requirements and layout are demonstrated according to todays' state-of-the-art. The admissible stresses, resulting from the summary of various specifications for the analytical evidence will be described. Development and construction will be explained in detail by means of pictures with cross sections of original shock absorbers. Todays' construction characteristics will be summarized. The final remark includes a request for generally valid guidelines. (orig.) [de

  13. Offshore Wind Farm Layout Design Considering Optimized Power Dispatch Strategy

    DEFF Research Database (Denmark)

    Hou, Peng; Hu, Weihao; N. Soltani, Mohsen

    2017-01-01

    Offshore wind farm has drawn more and more attention recently due to its higher energy capacity and more freedom to occupy area. However, the investment is higher. In order to make a cost-effective wind farm, the wind farm layout should be optimized. The wake effect is one of the dominant factors...... leading to energy losses. It is expected that the optimized placement of wind turbines (WT) over a large sea area can lead to the best tradeoff between energy yields and capital investment. This paper proposes a novel way to position offshore WTs for a regular shaped wind farm. In addition to optimizing...... the direction of wind farm placement and the spacing between WTs, the control strategy’s impact on energy yields is also discussed. Since the problem is non-convex and lots of optimization variables are involved, an evolutionary algorithm, the particle swarm optimization algorithm (PSO), is adopted to find...

  14. Forget about switching keyboard layouts with the "Compose Key"

    CERN Multimedia

    CERN. Geneva

    2018-01-01

    Growing up with a Spanish keyboard was not an easy childhood (using Shift+7 (/) to search in vim, or having to type AltGr+[ to actually have an opening bracket), so at some point in my life I switched to an American keyboard. At the beginning I was happy switching layouts to either do some coding or talk to my mum (I am not a fan of the classical excuse "sorry for my typos, I don't have the 'ñ' in my keyboard"). Things got much worse when I started to need French characters (ç, è) to interact with some services at CERN, or some Slovak letters (č, đ) to talk to Robert, my Slovak colleague . Then I discovered the Compose Key and my life has been different ever since.

  15. Overview of the Westinghouse Small Modular Reactor building layout

    Energy Technology Data Exchange (ETDEWEB)

    Cronje, J. M. [Westinghouse Electric Company LLC, Centurion (South Africa); Van Wyk, J. J.; Memmott, M. J. [Westinghouse Electric Company LLC, Cranberry Township, PA (United States)

    2012-07-01

    The Westinghouse Small Modular Reactor (SMR) is an 800 MWt (>225 MWe) integral pressurized water reactor (iPWR), in which all of the components typically associated with the nuclear steam supply system (NSSS) of a nuclear power plant are incorporated within a single reactor pressure vessel. This paper is the third in a series of four papers, which describe the design and functionality of the Westinghouse SMR. It focuses in particular upon the plant building layout and modular design of the Westinghouse SMR. In the development of small modular reactors, the building layout is an area where the safety of the plant can be improved by applying new design approaches. This paper will present an overview of the Westinghouse SMR building layout and indicate how the design features improve the safety and robustness of the plant. The Westinghouse SMR is designed with no shared systems between individual reactor units. The main buildings inside the security fence are the nuclear island, the rad-waste building, the annex building, and the turbine building. All safety related equipment is located in the nuclear island, which is a seismic class 1 building. To further enhance the safety and robustness of the design, the reactor, containment, and most of the safety related equipment are located below grade on the nuclear island. This reduces the possibility of severe damage from external threats or natural disasters. Two safety related ultimate heat sink (UHS) water tanks that are used for decay heat removal are located above grade, but are redundant and physically separated as far as possible for improved safety. The reactor and containment vessel are located below grade in the center of the nuclear island. The rad-waste and other radioactive systems are located on the bottom floors to limit the radiation exposure to personnel. The Westinghouse SMR safety trains are completely separated into four unconnected quadrants of the building, with access between quadrants only allowed

  16. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  17. The perception of spatial layout in real and virtual worlds.

    Science.gov (United States)

    Arthur, E J; Hancock, P A; Chrysler, S T

    1997-01-01

    As human-machine interfaces grow more immersive and graphically-oriented, virtual environment systems become more prominent as the medium for human-machine communication. Often, virtual environments (VE) are built to provide exact metrical representations of existing or proposed physical spaces. However, it is not known how individuals develop representational models of these spaces in which they are immersed and how those models may be distorted with respect to both the virtual and real-world equivalents. To evaluate the process of model development, the present experiment examined participant's ability to reproduce a complex spatial layout of objects having experienced them previously under different viewing conditions. The layout consisted of nine common objects arranged on a flat plane. These objects could be viewed in a free binocular virtual condition, a free binocular real-world condition, and in a static monocular view of the real world. The first two allowed active exploration of the environment while the latter condition allowed the participant only a passive opportunity to observe from a single viewpoint. Viewing conditions were a between-subject variable with 10 participants randomly assigned to each condition. Performance was assessed using mapping accuracy and triadic comparisons of relative inter-object distances. Mapping results showed a significant effect of viewing condition where, interestingly, the static monocular condition was superior to both the active virtual and real binocular conditions. Results for the triadic comparisons showed a significant interaction for gender by viewing condition in which males were more accurate than females. These results suggest that the situation model resulting from interaction with a virtual environment was indistinguishable from interaction with real objects at least within the constraints of the present procedure.

  18. An efficient grid layout algorithm for biological networks utilizing various biological attributes

    Directory of Open Access Journals (Sweden)

    Kato Mitsuru

    2007-03-01

    Full Text Available Abstract Background Clearly visualized biopathways provide a great help in understanding biological systems. However, manual drawing of large-scale biopathways is time consuming. We proposed a grid layout algorithm that can handle gene-regulatory networks and signal transduction pathways by considering edge-edge crossing, node-edge crossing, distance measure between nodes, and subcellular localization information from Gene Ontology. Consequently, the layout algorithm succeeded in drastically reducing these crossings in the apoptosis model. However, for larger-scale networks, we encountered three problems: (i the initial layout is often very far from any local optimum because nodes are initially placed at random, (ii from a biological viewpoint, human layouts still exceed automatic layouts in understanding because except subcellular localization, it does not fully utilize biological information of pathways, and (iii it employs a local search strategy in which the neighborhood is obtained by moving one node at each step, and automatic layouts suggest that simultaneous movements of multiple nodes are necessary for better layouts, while such extension may face worsening the time complexity. Results We propose a new grid layout algorithm. To address problem (i, we devised a new force-directed algorithm whose output is suitable as the initial layout. For (ii, we considered that an appropriate alignment of nodes having the same biological attribute is one of the most important factors of the comprehension, and we defined a new score function that gives an advantage to such configurations. For solving problem (iii, we developed a search strategy that considers swapping nodes as well as moving a node, while keeping the order of the time complexity. Though a naïve implementation increases by one order, the time complexity, we solved this difficulty by devising a method that caches differences between scores of a layout and its possible updates

  19. Plant automation

    International Nuclear Information System (INIS)

    Christensen, L.J.; Sackett, J.I.; Dayal, Y.; Wagner, W.K.

    1989-01-01

    This paper describes work at EBR-II in the development and demonstration of new control equipment and methods and associated schemes for plant prognosis, diagnosis, and automation. The development work has attracted the interest of other national laboratories, universities, and commercial companies. New initiatives include use of new control strategies, expert systems, advanced diagnostics, and operator displays. The unique opportunity offered by EBR-II is as a test bed where a total integrated approach to automatic reactor control can be directly tested under real power plant conditions

  20. Intelligent Help in the LOCATE Workspace Layout Tool

    Science.gov (United States)

    1999-06-01

    LOCATE’s basic design and analysis features; • commercialising the application; • expanding the groundwork for tracking actions and goals at the interface...Muraida, D.J. (Eds.) (1993). Automating instructional design: Concepts and issues. Englewood Cliffs, N.J.: Educational Technology Publications

  1. Automated logic conversion method for plant controller systems

    International Nuclear Information System (INIS)

    Wada, Yutaka; Kobayashi, Yasuhiro; Miyo, Tsunemasa; Okano, Masato.

    1990-01-01

    An automated method is proposed for logic conversion from functional description diagrams to detailed logic schematics by incorporating expertise knowledge in plant controller systems design. The method uses connection data of function elements in the functional description diagram as input, and synthesizes a detailed logic structure by adding elements to the given connection data incrementally, and to generate detailed logic schematics. In logic synthesis, for building up complex synthesis procedures by combining generally-described knowledge, knowledge is applied by groups. The search order of the groups is given by upper-level knowledge. Furthermore, the knowledge is expressed in terms of two classes of rules; one for generating a hypothesis of individual synthesis operations and the other for considering several hypotheses to determine the connection ordering of elements to be added. In the generation of detailed logic schematics, knowledge is used as rules for deriving various kinds of layout conditions on schematics, and rules for generating two-dimensional coordinates of layout objects. Rules in the latter class use layout conditions to predict intersections among layout objects without their coordinates being fixed. The effectiveness of the method with 150 rules was verified by its experimental application to some logic conversions in a real power plant design. Evaluation of the results showed them to be equivalent to those obtained by well qualified designers. (author)

  2. WIDAFELS flexible automation systems

    International Nuclear Information System (INIS)

    Shende, P.S.; Chander, K.P.; Ramadas, P.

    1990-01-01

    After discussing the various aspects of automation, some typical examples of various levels of automation are given. One of the examples is of automated production line for ceramic fuel pellets. (M.G.B.)

  3. An Automation Planning Primer.

    Science.gov (United States)

    Paynter, Marion

    1988-01-01

    This brief planning guide for library automation incorporates needs assessment and evaluation of options to meet those needs. A bibliography of materials on automation planning and software reviews, library software directories, and library automation journals is included. (CLB)

  4. 33 CFR 127.105 - Layout and spacing of marine transfer area for LNG.

    Science.gov (United States)

    2010-07-01

    ... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Layout and spacing of marine transfer area for LNG. 127.105 Section 127.105 Navigation and Navigable Waters COAST GUARD, DEPARTMENT OF... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Natural Gas § 127.105 Layout and...

  5. Extracting 3D layout from a single image using global image structures.

    Science.gov (United States)

    Lou, Zhongyu; Gevers, Theo; Hu, Ninghang

    2015-10-01

    Extracting the pixel-level 3D layout from a single image is important for different applications, such as object localization, image, and video categorization. Traditionally, the 3D layout is derived by solving a pixel-level classification problem. However, the image-level 3D structure can be very beneficial for extracting pixel-level 3D layout since it implies the way how pixels in the image are organized. In this paper, we propose an approach that first predicts the global image structure, and then we use the global structure for fine-grained pixel-level 3D layout extraction. In particular, image features are extracted based on multiple layout templates. We then learn a discriminative model for classifying the global layout at the image-level. Using latent variables, we implicitly model the sublevel semantics of the image, which enrich the expressiveness of our model. After the image-level structure is obtained, it is used as the prior knowledge to infer pixel-wise 3D layout. Experiments show that the results of our model outperform the state-of-the-art methods by 11.7% for 3D structure classification. Moreover, we show that employing the 3D structure prior information yields accurate 3D scene layout segmentation.

  6. 49 CFR 238.447 - Train operator's controls and power car cab layout.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Train operator's controls and power car cab layout. 238.447 Section 238.447 Transportation Other Regulations Relating to Transportation (Continued... layout. (a) Train operator controls in the power car cab shall be arranged so as to minimize the chance...

  7. 33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

    Science.gov (United States)

    2010-07-01

    ... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Layout and spacing of marine transfer area for LHG. 127.1105 Section 127.1105 Navigation and Navigable Waters COAST GUARD, DEPARTMENT OF... Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

  8. Design aspects of the alpha repository. II. Conceptual layouts of underground storage facilities

    International Nuclear Information System (INIS)

    Grams, W.H.

    1975-01-01

    Five conceptual repository layouts are presented: linear repository, 1 panel; bow tie repository, 2 panels; maltese cross repository, 4 panels; snowflake repository; 5 panels, and sash window repository, 8 panels. The layouts are compared with respect to excavation requirements, haulage distances, ventilation flow path designs, and safety features

  9. Yearbook and Magazine Layout, English, Journalism. Language Arts: 5113.200.

    Science.gov (United States)

    Adams, Marlene E.

    Developed as a quinmester unit for the high school on yearbook and magazine layout, this guide provides the teacher with suggested teaching strategies for a study of the theory and practice of page layout, photo cropping and editing, use of color and special effects, copy fitting and headline writing and fitting, and principles of typography.…

  10. Sensitivity Analysis of WEC Array Layout Parameters Effect on the Power Performance

    DEFF Research Database (Denmark)

    Ruiz, Pau Mercadé; Ferri, Francesco; Kofoed, Jens Peter

    2015-01-01

    This study assesses the effect that the array layout choice has on the power performance. To this end, a sensitivity analysis is carried out with six array layout parameters, as the simulation inputs, the array power performance (q-factor), as the simulation output, and a simulation model special...

  11. Layout level design for testability strategy applied to a CMOS cell library

    NARCIS (Netherlands)

    Blom, F.C.; Oliver, J.; Rullan, M.; Ferrer, C.

    1993-01-01

    The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce

  12. Thermal Performance for Wet Cooling Tower with Different Layout Patterns of Fillings under Typical Crosswind Conditions

    Directory of Open Access Journals (Sweden)

    Ming Gao

    2017-01-01

    Full Text Available A thermal-state model experimental study was performed in lab to investigate the thermal performance of a wet cooling tower with different kinds of filling layout patterns under windless and 0.4 m/s crosswind conditions. In this paper, the contrast analysis was focused on comparing a uniform layout pattern and one kind of optimal non-uniform layout pattern when the environmental crosswind speed is 0 m/s and 0.4 m/s. The experimental results proved that under windless conditions, the heat transfer coefficient and total heat rejection of circulating water for the optimal non-uniform layout pattern can enhance by approximately 40% and 28%, respectively, compared with the uniform layout pattern. It was also discovered that the optimal non-uniform pattern can dramatically relieve the influence of crosswind on the thermal performance of the tower when the crosswind speed is equal to 0.4 m/s. For the uniform layout pattern, the heat transfer coefficient under 0.4 m/s crosswind conditions decreased by 9.5% compared with the windless conditions, while that value lowered only by 2.0% for the optimal non-uniform layout pattern. It has been demonstrated that the optimal non-uniform layout pattern has the better thermal performance under 0.4 m/s crosswind condition.

  13. Studies of Inner Detector Layouts with 5 Pixel layers for the Phase-II Upgrade

    CERN Document Server

    Ludwig, A; The ATLAS collaboration; Garcia-Sciveres, M

    2013-01-01

    This note describes a study of Inner Detector layouts for the phase-II upgrade. Starting from the LOI layout the impact of adding a 5th pixel layer, and shortening the pixel and/or SCT barrel layers is studied.

  14. An interactive system for the automatic layout of printed circuit boards (ARAIGNEE)

    International Nuclear Information System (INIS)

    Combet, M.; Eder, J.; Pagny, C.

    1974-12-01

    A software package for the automatic layout of printed circuit boards is presented. The program permits an interaction of the user during the layout process. The automatic searching of paths can be interrupted at any step and convenient corrections can be inserted. This procedure improves strongly the performance of the program as far as the number of unresolved connections is concerned

  15. Electrical Parasitics and Thermal Modeling for Optimized Layout Design of High Power SiC Modules

    DEFF Research Database (Denmark)

    Bahman, Amir Sajjad; Blaabjerg, Frede; Dutta, Atanu

    2016-01-01

    , the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by FEM simulations and also experiment....

  16. A Novel Energy Yields Calculation Method for Irregular Wind Farm Layout

    DEFF Research Database (Denmark)

    Hou, Peng; Hu, Weihao; Soltani, Mohsen

    2015-01-01

    Due to the increasing size of offshore wind farm, the impact of the wake effect on energy yields become more and more evident. The Seafloor topography would limit the layout of the wind farm so that irregular layout is usually adopted inlarge scale offshore wind farm. However, the calculation...

  17. The changing pages of comics : Page layouts across eight decades of American superhero comics

    NARCIS (Netherlands)

    Pederson, Kaitlin; Cohn, Neil

    2016-01-01

    Page layouts are one of the most overt features of comics’ structure. We hypothesized that American superhero comics have changed in their page layout over eight decades, and investigated this using a corpus analysis of 40 comics from 1940 through 2014. On the whole, we found that comics pages

  18. A novel approach of ensuring layout regularity correct by construction in advanced technologies

    Science.gov (United States)

    Ahmed, Shafquat Jahan; Vaderiya, Yagnesh; Gupta, Radhika; Parthasarathy, Chittoor; Marin, Jean-Claude; Robert, Frederic

    2017-03-01

    In advanced technology nodes, layout regularity has become a mandatory prerequisite to create robust designs less sensitive to variations in manufacturing process in order to improve yield and minimizing electrical variability. In this paper we describe a method for designing regular full custom layouts based on design and process co-optimization. The method includes various design rule checks that can be used on-the-fly during leaf-cell layout development. We extract a Layout Regularity Index (LRI) from the layouts based on the jogs, alignments and pitches used in the design for any given metal layer. Regularity Index of a layout is the direct indicator of manufacturing yield and is used to compare the relative health of different layout blocks in terms of process friendliness. The method has been deployed for 28nm and 40nm technology nodes for Memory IP and is being extended to other IPs (IO, standard-cell). We have quantified the gain of layout regularity with the deployed method on printability and electrical characteristics by process-variation (PV) band simulation analysis and have achieved up-to 5nm reduction in PV band.

  19. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  20. Low cost automation

    International Nuclear Information System (INIS)

    1987-03-01

    This book indicates method of building of automation plan, design of automation facilities, automation and CHIP process like basics of cutting, NC processing machine and CHIP handling, automation unit, such as drilling unit, tapping unit, boring unit, milling unit and slide unit, application of oil pressure on characteristics and basic oil pressure circuit, application of pneumatic, automation kinds and application of process, assembly, transportation, automatic machine and factory automation.

  1. Young children reorient by computing layout geometry, not by matching images of the environment.

    Science.gov (United States)

    Lee, Sang Ah; Spelke, Elizabeth S

    2011-02-01

    Disoriented animals from ants to humans reorient in accord with the shape of the surrounding surface layout: a behavioral pattern long taken as evidence for sensitivity to layout geometry. Recent computational models suggest, however, that the reorientation process may not depend on geometrical analyses but instead on the matching of brightness contours in 2D images of the environment. Here we test this suggestion by investigating young children's reorientation in enclosed environments. Children reoriented by extremely subtle geometric properties of the 3D layout: bumps and ridges that protruded only slightly off the floor, producing edges with low contrast. Moreover, children failed to reorient by prominent brightness contours in continuous layouts with no distinctive 3D structure. The findings provide evidence that geometric layout representations support children's reorientation.

  2. Economy analysis on vertical layout of conventional island of nuclear power plant

    International Nuclear Information System (INIS)

    Wang Xuefeng; Liu Xiaoyun; Liu Jinwei

    2011-01-01

    This paper briefly introduces the aboveground layout scheme and integral sinking layout scheme of conventional island of nuclear power plants. Technological-economic analysis formula are given, as a result, main factors influencing scheme selection is obtained. Determination of the layout scheme selection and optimization direction through the curve between the accumulative NPV and related factors is brought forward. The paper carries out the technological-economic comparison to the two schemes referred to a 1000 MW level nuclear power project as the example, getting the curve between the accumulative NPV and the plant ground elevation, and offering the method of selecting the vertical layout scheme of conventional island and vertical layout optimization direction. (authors)

  3. Using the clustered circular layout as an informative method for visualizing protein-protein interaction networks.

    Science.gov (United States)

    Fung, David C Y; Wilkins, Marc R; Hart, David; Hong, Seok-Hee

    2010-07-01

    The force-directed layout is commonly used in computer-generated visualizations of protein-protein interaction networks. While it is good for providing a visual outline of the protein complexes and their interactions, it has two limitations when used as a visual analysis method. The first is poor reproducibility. Repeated running of the algorithm does not necessarily generate the same layout, therefore, demanding cognitive readaptation on the investigator's part. The second limitation is that it does not explicitly display complementary biological information, e.g. Gene Ontology, other than the protein names or gene symbols. Here, we present an alternative layout called the clustered circular layout. Using the human DNA replication protein-protein interaction network as a case study, we compared the two network layouts for their merits and limitations in supporting visual analysis.

  4. Apron layout design and flight-to-gate assignment at Lanseria International airport

    Directory of Open Access Journals (Sweden)

    Leonard, T.

    2013-05-01

    Full Text Available Air traffic is continuously increasing and more efficient air transport systems are required to handle the air travel demand. The study investigates the expansion of Lanseria International Airport in Gauteng, South Africa. Expansion of Lanseria requires a study of the airport apron layout to ensure efficient passenger-aircraft flow as well as the efficient flow of aircraft to and from the airport. The candidate layout designs are based on the layout concept of the Hartsfield-Jackson Atlanta International Airport in Atlanta, USA. In the study, different airport apron layouts were compared, including the existing layout of Atlanta Airport, via a simulation model of each. Designs based mainly on passenger transfer distance between the terminal building and aircraft were evaluated. The cross-entropy method was used to develop a generic flight-to-gate assignment program that minimises passenger transfer distances.

  5. A descriptive analysis of quantitative indices for multi-objective block layout

    Directory of Open Access Journals (Sweden)

    Amalia Medina Palomera

    2013-01-01

    Full Text Available Layout generation methods provide alternative solutions whose feasibility and quality must be evaluated. Indices must be used to distinguish the feasible solutions (involving different criteria obtained for block layout to identify s solution’s suitability, according to set objectives. This paper provides an accurate and descriptive analysis of the geometric indices used in designing facility layout (during block layout phase. The indices studied here have advantages and disadvantages which should be considered by an analyst before attempting to resolve the facility layout problem. New equations are proposed for measuring geometric indices. The analysis revealed redundant indices and that a minimum number of indices covering overall quality criteria may be used when selecting alternative solutions.

  6. Constructing an optimal facility layout to maximize adjacency as a function of common boundary length

    Science.gov (United States)

    Ghassemi Tari, Farhad; Neghabi, Hossein

    2018-03-01

    An effective facility layout implies that departments with high flow are laid adjacent. However, in the case of a very narrow boundary length between the neighbouring departments, the adjacency would actually be useless. In traditional layout design methods, a score is generally assigned independent of the department's boundary length. This may result in a layout design with a restricted material flow. This article proposes a new concept of adjacency in which the department pairs are laid adjacent with a wider path. To apply this concept, a shop with unequal rectangular departments is contemplated and a mathematical programming model with the objective of maximizing the sum of the adjacency degrees is proposed. A computational experiment is conducted to demonstrate the efficiency of the layout design. It is demonstrated that the new concept provides a more efficient and a more realistic layout design.

  7. Automated Budget System -

    Data.gov (United States)

    Department of Transportation — The Automated Budget System (ABS) automates management and planning of the Mike Monroney Aeronautical Center (MMAC) budget by providing enhanced capability to plan,...

  8. Automation 2017

    CERN Document Server

    Zieliński, Cezary; Kaliczyńska, Małgorzata

    2017-01-01

    This book consists of papers presented at Automation 2017, an international conference held in Warsaw from March 15 to 17, 2017. It discusses research findings associated with the concepts behind INDUSTRY 4.0, with a focus on offering a better understanding of and promoting participation in the Fourth Industrial Revolution. Each chapter presents a detailed analysis of a specific technical problem, in most cases followed by a numerical analysis, simulation and description of the results of implementing the solution in a real-world context. The theoretical results, practical solutions and guidelines presented are valuable for both researchers working in the area of engineering sciences and practitioners looking for solutions to industrial problems. .

  9. Marketing automation

    Directory of Open Access Journals (Sweden)

    TODOR Raluca Dania

    2017-01-01

    Full Text Available The automation of the marketing process seems to be nowadays, the only solution to face the major changes brought by the fast evolution of technology and the continuous increase in supply and demand. In order to achieve the desired marketing results, businessis have to employ digital marketing and communication services. These services are efficient and measurable thanks to the marketing technology used to track, score and implement each campaign. Due to the technical progress, the marketing fragmentation, demand for customized products and services on one side and the need to achieve constructive dialogue with the customers, immediate and flexible response and the necessity to measure the investments and the results on the other side, the classical marketing approached had changed continue to improve substantially.

  10. Creating a Single South African Keyboard Layout to Promote Language

    Directory of Open Access Journals (Sweden)

    Dwayne Bailey

    2011-10-01

    Full Text Available

    Abstract: In this case study, a description is given of a keyboard layout designed to address the input needs of South African languages, specifically Venda, a language which would otherwise be impossible to type on a computer. In creating this keyboard, the designer, Translate.org.za, uses a practical intervention that transforms technology from a means harming a language into one ensuring the creation and preservation of good language resources for minority languages. The study first looks at the implications and consequences of this missing keyboard, and then follows the process from conception, strategy, research and design to the final user response. Not only are problems such as researching the orthographies, key placement and keyboard input options examined, but strategic objectives such as ensuring its wide adoption and creating a multilingual keyboard for all South African languages are also discussed. The result is a keyboard that furthers multilingualism and ensures the capturing of good data for future research. Finally it is a tool helping to boost and bolster the vitality of a language.

    Keywords: KEYBOARD, MULTILINGUALISM, VENDA, AFRIKAANS, TSWANA, NORTH-ERN SOTHO, ZULU, SOURCE, FREE SOFTWARE, LAYOUT

    Opsomming: Die skep van 'n enkelvoudige Suid-Afrikaanse toetsborduit-leg om taal te bevorder. In hierdie gevallestudie word 'n beskrywing gegee van die ontwerp van 'n sleutelborduitleg vir die hantering van die insetbehoeftes van Suid-Afrikaanse tale, veral Venda, 'n taal wat andersins onmoontlik op 'n rekenaar getik sou kon word. Deur die skep van hierdie sleutelbord gebruik die ontwerper, Translate.org.za, 'n praktiese ingryp wat tegnologie verander van 'n middel wat 'n taal benadeel tot een wat die skep en bewaring van nuttige taal-hulpbronne vir minderheidstale verseker. Die studie kyk eers na die implikasies en gevolge van hierdie ontbrekende sleutelbord, en volg dan die proses van konsepsie, strategie, navorsing en

  11. Progress report on research project [Plan for www interface layout

    International Nuclear Information System (INIS)

    Fukahori, T.

    2006-01-01

    Full text: Presentations and status reports. T. Fukahori reported the plan for www interface layout as a status report. Discussed were which functions were needed for new RIPL-3 web pages. The results are summarized in next section. Layout of the interfaces and retrieval tools and web. The RIPL-3 home page will include a summary description and link to the HANDBOOK: a) The web page for 'mass' segment contains same contents as RIPL-2 except to remove the information about ground state deformation. The abundance data will be replaced by those according to the new BNL wallet card (2005 version). The Q-value calculation tool will be also improved. The 'Nuclear Matter Density' will be renamed as 'Nucleon Density Distribution'. b) Those of 'levels' segment will be same as before, and the deformation parameters for excited levels will be moved from 'optical' segment with the name of 'deformation'. c) Those of 'resonances' segment will be same as before. It will be considered to replace RIPL-2 database with the new Mughabghab tables. d) Those of 'optical' segment will be same as before, and the deformation parameters for excited levels will be moved to 'optical' segment with the name of 'deformation'. The optical model calculation with ECIS and OPTMAN will be considered and double-folding calculation tool will be possibly provided. e) Those of 'densities' segment will be same as before, and the programs used to plot will be checked. The 3-7 sets of combination of GC, BSFG, GSFM with/without enhancement factors will be given. f) Those of 'gamma' segment will be same as before with adding MLO and theoretical GDR calculation. g) Those of 'fission' segment will be same as before, and 'Exp.' will be renamed. New barrier evaluations will be added. Some additional information could be included, for example, fission transition states. The fission spectrum calculation tool (codes and inputs) will be considered to be added. The fundamental format will be kept as before. For new

  12. Relation between front suspension layout and handling performance. Analysis depending on the Taguchi method and ADAMS; Front suspension layout to soda tokusei no kankei ni tsuite. Kiko kaiseki gengo wo mochiita hinshitsu kogaku ni yoru kaiseki

    Energy Technology Data Exchange (ETDEWEB)

    Okada, K [Daihatsu Motor Co. Ltd., Osaka (Japan)

    1997-10-01

    A variation of suspension layout gives an influence to the vehicle dynamics. Examined the suspension layout variation to make the handling performance change small. Analyzed the effect of suspension layout variation about steering response delay and gain besides the tire wear effect and movable load. 3 refs., 12 figs., 4 tabs.

  13. Environmental layout complexity affects neural activity during navigation in humans.

    Science.gov (United States)

    Slone, Edward; Burles, Ford; Iaria, Giuseppe

    2016-05-01

    Navigating large-scale surroundings is a fundamental ability. In humans, it is commonly assumed that navigational performance is affected by individual differences, such as age, sex, and cognitive strategies adopted for orientation. We recently showed that the layout of the environment itself also influences how well people are able to find their way within it, yet it remains unclear whether differences in environmental complexity are associated with changes in brain activity during navigation. We used functional magnetic resonance imaging to investigate how the brain responds to a change in environmental complexity by asking participants to perform a navigation task in two large-scale virtual environments that differed solely in interconnection density, a measure of complexity defined as the average number of directional choices at decision points. The results showed that navigation in the simpler, less interconnected environment was faster and more accurate relative to the complex environment, and such performance was associated with increased activity in a number of brain areas (i.e. precuneus, retrosplenial cortex, and hippocampus) known to be involved in mental imagery, navigation, and memory. These findings provide novel evidence that environmental complexity not only affects navigational behaviour, but also modulates activity in brain regions that are important for successful orientation and navigation. © 2016 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

  14. International Thermonuclear Experimental Reactor (ITER) plant layout and site services

    International Nuclear Information System (INIS)

    Chuyanov, V.

    2001-01-01

    The ITER site has not been determined at this time. Nevertheless, to develop a construction plan and a cost estimate, it is necessary to have a detailed layout of the buildings, structures, and outdoor equipment integrated with the balance of plant service systems prototypical of large fusion power plants. These services include electric power for magnet feeds and plasma heating systems, cryogenic and conventional cooling systems, compressed air, gas supplies, de-mineralized water, steam, and drainage. Nuclear grade facilities are provided to handle tritium fuel and activated waste, as well as to prevent radioactive exposure of either the workers or the public. To avoid interference between services of different types and for efficient arrangement of buildings, structures, and equipment within the site area, a plan was developed which segregated different classes of services to four quadrants surrounding the tokamak building, placed at the approximate geographic center of the site. Location of the twenty-seven buildings on the generic site was selected to meet all design requirements at minimum total project cost. A similar approach has been used to determine the location of services above, at, and below grade. The generic site plan can be adapted to the site selected for ITER without significant changes to the buildings or equipment. Some rearrangements may be required by site topography resulting primarily in changes to the length of services that link the buildings and equipment. (author)

  15. LAYOUT AND DESIGN OF ELECTROMOBILE CHARGING STATIONS AS URBAN ELEMENTS

    Directory of Open Access Journals (Sweden)

    Tomáš Chovan

    2015-12-01

    Full Text Available The contribution is dedicated to the processing of the problems of the insufficient charging for the electric vehicles within the concrete urbanistic centre. It brings a different perspective on the mobility, which is shown in the form of electric energy as the alternative for the needs of urbanization of the cities. It analyses electromobility, new technologies in the field of electric vehicles and the charging stations as the elements of the urbanism. In terms of the solution, the contribution is focused on the Košice city and the location of the public charging stations. Košice do not have sufficient amount of the public charging stations and until the 2014 there was only one public charging station. The contribution is focused on the designing of the parking places with the charging station placed on the appropriate parking places. The resulting design is created in the CAD system, it brings the view of the layout of the charging station at the shopping centre in the open space and in the parking house.

  16. Inherent safety features in balance-of-plant layout

    International Nuclear Information System (INIS)

    Wattelet, P.L.; Green, K.J.

    1992-01-01

    Future nuclear units must be more economical to construct and operate, and, at the same time, clearly incorporate advances in safety over the current generation of light water reactors. To achieve these goals, the root causes of safety issues must be addressed. In this way, global, cost-effective solutions can be implemented. With simple, direct design approaches, the licensing risk is minimized and configuration control is enhanced. With proper planning in the early stages of plant design, postulated accidents and events can often be mitigated by passive features inherent in the basic structure and layout, eliminating expensive added protective structures and components often found in current designs. Korea Electric Power Corporation's Yonggwang (YGN) Units 3 and 4, shown in an artist's rendering in Figure 1, are now under construction in Korea. Engineering is more than 85% complete, and Unit 3 construction is more than 50% complete. Significant steps toward design simplification and safety enhancement have been made by addressing safety concerns very early in the design effort. The tools used to achieve this were improved symmetry and separation, isolation of potential hazards, and an improved design process

  17. Optimization of wind farm turbines layout using an evolutive algorithm

    International Nuclear Information System (INIS)

    Gonzalez, Javier Serrano; Santos, Jesus Riquelme; Payan, Manuel Burgos; Gonzalez Rodriguez, Angel G.; Mora, Jose Castro

    2010-01-01

    The optimum wind farm configuration problem is discussed in this paper and an evolutive algorithm to optimize the wind farm layout is proposed. The algorithm's optimization process is based on a global wind farm cost model using the initial investment and the present value of the yearly net cash flow during the entire wind-farm life span. The proposed algorithm calculates the yearly income due to the sale of the net generated energy taking into account the individual wind turbine loss of production due to wake decay effects and it can deal with areas or terrains with non-uniform load-bearing capacity soil and different roughness length for every wind direction or restrictions such as forbidden areas or limitations in the number of wind turbines or the investment. The results are first favorably compared with those previously published and a second collection of test cases is used to proof the performance and suitability of the proposed evolutive algorithm to find the optimum wind farm configuration. (author)

  18. LADS: Optimizing Data Transfers using Layout-Aware Data Scheduling

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Youngjae [ORNL; Atchley, Scott [ORNL; Vallee, Geoffroy R [ORNL; Shipman, Galen M [ORNL

    2015-01-01

    While future terabit networks hold the promise of signifi- cantly improving big-data motion among geographically distributed data centers, significant challenges must be overcome even on today s 100 gigabit networks to real- ize end-to-end performance. Multiple bottlenecks exist along the end-to-end path from source to sink. Data stor- age infrastructure at both the source and sink and its in- terplay with the wide-area network are increasingly the bottleneck to achieving high performance. In this paper, we identify the issues that lead to congestion on the path of an end-to-end data transfer in the terabit network en- vironment, and we present a new bulk data movement framework called LADS for terabit networks. LADS ex- ploits the underlying storage layout at each endpoint to maximize throughput without negatively impacting the performance of shared storage resources for other users. LADS also uses the Common Communication Interface (CCI) in lieu of the sockets interface to use zero-copy, OS-bypass hardware when available. It can further im- prove data transfer performance under congestion on the end systems using buffering at the source using flash storage. With our evaluations, we show that LADS can avoid congested storage elements within the shared stor- age resource, improving I/O bandwidth, and data transfer rates across the high speed networks.

  19. Automatic pattern localization across layout database and photolithography mask

    Science.gov (United States)

    Morey, Philippe; Brault, Frederic; Beisser, Eric; Ache, Oliver; Röth, Klaus-Dieter

    2016-03-01

    Advanced process photolithography masks require more and more controls for registration versus design and critical dimension uniformity (CDU). The distribution of the measurement points should be distributed all over the whole mask and may be denser in areas critical to wafer overlay requirements. This means that some, if not many, of theses controls should be made inside the customer die and may use non-dedicated patterns. It is then mandatory to access the original layout database to select patterns for the metrology process. Finding hundreds of relevant patterns in a database containing billions of polygons may be possible, but in addition, it is mandatory to create the complete metrology job fast and reliable. Combining, on one hand, a software expertise in mask databases processing and, on the other hand, advanced skills in control and registration equipment, we have developed a Mask Dataprep Station able to select an appropriate number of measurement targets and their positions in a huge database and automatically create measurement jobs on the corresponding area on the mask for the registration metrology system. In addition, the required design clips are generated from the database in order to perform the rendering procedure on the metrology system. This new methodology has been validated on real production line for the most advanced process. This paper presents the main challenges that we have faced, as well as some results on the global performances.

  20. Sandia Agile MEMS Prototyping, Layout Tools, Education and Services Program

    Energy Technology Data Exchange (ETDEWEB)

    Schriner, H.; Davies, B.; Sniegowski, J.; Rodgers, M.S.; Allen, J.; Shepard, C.

    1998-05-01

    Research and development in the design and manufacture of Microelectromechanical Systems (MEMS) is growing at an enormous rate. Advances in MEMS design tools and fabrication processes at Sandia National Laboratories` Microelectronics Development Laboratory (MDL) have broadened the scope of MEMS applications that can be designed and manufactured for both military and commercial use. As improvements in micromachining fabrication technologies continue to be made, MEMS designs can become more complex, thus opening the door to an even broader set of MEMS applications. In an effort to further research and development in MEMS design, fabrication, and application, Sandia National Laboratories has launched the Sandia Agile MEMS Prototyping, Layout Tools, Education and Services Program or SAMPLES program. The SAMPLES program offers potential partners interested in MEMS the opportunity to prototype an idea and produce hardware that can be used to sell a concept. The SAMPLES program provides education and training on Sandia`s design tools, analysis tools and fabrication process. New designers can participate in the SAMPLES program and design MEMS devices using Sandia`s design and analysis tools. As part of the SAMPLES program, participants` designs are fabricated using Sandia`s 4 level polycrystalline silicon surface micromachine technology fabrication process known as SUMMiT (Sandia Ultra-planar, Multi-level MEMS Technology). Furthermore, SAMPLES participants can also opt to obtain state of the art, post-fabrication services provided at Sandia such as release, packaging, reliability characterization, and failure analysis. This paper discusses the components of the SAMPLES program.

  1. International Thermonuclear Experimental Reactor (ITER) plant layout and site services

    International Nuclear Information System (INIS)

    Chuyanov, V.

    1999-01-01

    The ITER site has not been determined at this time. Nevertheless, to develop a construction plan and a cost estimate, it is necessary to have a detailed layout of the buildings, structures, and outdoor equipment integrated with the balance of plant service systems prototypical of large fusion power plants. These services include electric power for magnet feeds and plasma heating systems, cryogenic and conventional cooling systems, compressed air, gas supplies, de-mineralized water, steam, and drainage. Nuclear grade facilities are provided to handle tritium fuel and activated waste, as well as to prevent radioactive exposure of either the workers or the public. To avoid interference between services of different types and for efficient arrangement of buildings, structures, and equipment within the site area, a plan was developed which segregated different classes of services to four quadrants surrounding the tokamak building, placed at the approximate geographic center of the site. Location of the twenty-seven buildings on the generic site was selected to meet all design requirements at minimum total project cost. A similar approach has been used to determine the location of services above, at, and below grade. The generic site plan can be adapted to the site selected for ITER without significant changes to the buildings or equipment. Some rearrangements may be required by site topography resulting primarily in changes to the length of services that link the buildings and equipment. (author)

  2. A silicon pixel detector with routing for external VLSI read-out

    International Nuclear Information System (INIS)

    Thomas, S.L.; Seller, P.

    1988-07-01

    A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)

  3. Safety assessment in plant layout design using indexing approach: Implementing inherent safety perspective

    International Nuclear Information System (INIS)

    Tugnoli, Alessandro; Khan, Faisal; Amyotte, Paul; Cozzani, Valerio

    2008-01-01

    Layout planning plays a key role in the inherent safety performance of process plants since this design feature controls the possibility of accidental chain-events and the magnitude of possible consequences. A lack of suitable methods to promote the effective implementation of inherent safety in layout design calls for the development of new techniques and methods. In the present paper, a safety assessment approach suitable for layout design in the critical early phase is proposed. The concept of inherent safety is implemented within this safety assessment; the approach is based on an integrated assessment of inherent safety guideword applicability within the constraints typically present in layout design. Application of these guidewords is evaluated along with unit hazards and control devices to quantitatively map the safety performance of different layout options. Moreover, the economic aspects related to safety and inherent safety are evaluated by the method. Specific sub-indices are developed within the integrated safety assessment system to analyze and quantify the hazard related to domino effects. The proposed approach is quick in application, auditable and shares a common framework applicable in other phases of the design lifecycle (e.g. process design). The present work is divided in two parts: Part 1 (current paper) presents the application of inherent safety guidelines in layout design and the index method for safety assessment; Part 2 (accompanying paper) describes the domino hazard sub-index and demonstrates the proposed approach with a case study, thus evidencing the introduction of inherent safety features in layout design

  4. Application of approximate pattern matching in two dimensional spaces to grid layout for biochemical network maps.

    Science.gov (United States)

    Inoue, Kentaro; Shimozono, Shinichi; Yoshida, Hideaki; Kurata, Hiroyuki

    2012-01-01

    For visualizing large-scale biochemical network maps, it is important to calculate the coordinates of molecular nodes quickly and to enhance the understanding or traceability of them. The grid layout is effective in drawing compact, orderly, balanced network maps with node label spaces, but existing grid layout algorithms often require a high computational cost because they have to consider complicated positional constraints through the entire optimization process. We propose a hybrid grid layout algorithm that consists of a non-grid, fast layout (preprocessor) algorithm and an approximate pattern matching algorithm that distributes the resultant preprocessed nodes on square grid points. To demonstrate the feasibility of the hybrid layout algorithm, it is characterized in terms of the calculation time, numbers of edge-edge and node-edge crossings, relative edge lengths, and F-measures. The proposed algorithm achieves outstanding performances compared with other existing grid layouts. Use of an approximate pattern matching algorithm quickly redistributes the laid-out nodes by fast, non-grid algorithms on the square grid points, while preserving the topological relationships among the nodes. The proposed algorithm is a novel use of the pattern matching, thereby providing a breakthrough for grid layout. This application program can be freely downloaded from http://www.cadlive.jp/hybridlayout/hybridlayout.html.

  5. Application of approximate pattern matching in two dimensional spaces to grid layout for biochemical network maps.

    Directory of Open Access Journals (Sweden)

    Kentaro Inoue

    Full Text Available BACKGROUND: For visualizing large-scale biochemical network maps, it is important to calculate the coordinates of molecular nodes quickly and to enhance the understanding or traceability of them. The grid layout is effective in drawing compact, orderly, balanced network maps with node label spaces, but existing grid layout algorithms often require a high computational cost because they have to consider complicated positional constraints through the entire optimization process. RESULTS: We propose a hybrid grid layout algorithm that consists of a non-grid, fast layout (preprocessor algorithm and an approximate pattern matching algorithm that distributes the resultant preprocessed nodes on square grid points. To demonstrate the feasibility of the hybrid layout algorithm, it is characterized in terms of the calculation time, numbers of edge-edge and node-edge crossings, relative edge lengths, and F-measures. The proposed algorithm achieves outstanding performances compared with other existing grid layouts. CONCLUSIONS: Use of an approximate pattern matching algorithm quickly redistributes the laid-out nodes by fast, non-grid algorithms on the square grid points, while preserving the topological relationships among the nodes. The proposed algorithm is a novel use of the pattern matching, thereby providing a breakthrough for grid layout. This application program can be freely downloaded from http://www.cadlive.jp/hybridlayout/hybridlayout.html.

  6. Safety assessment in plant layout design using indexing approach: Implementing inherent safety perspective

    International Nuclear Information System (INIS)

    Tugnoli, Alessandro; Khan, Faisal; Amyotte, Paul; Cozzani, Valerio

    2008-01-01

    The design of layout plans requires adequate assessment tools for the quantification of safety performance. The general focus of the present work is to introduce an inherent safety perspective at different points of the layout design process. In particular, index approaches for safety assessment and decision-making in the early stages of layout design are developed and discussed in this two-part contribution. Part 1 (accompanying paper) of the current work presents an integrated index approach for safety assessment of early plant layout. In the present paper (Part 2), an index for evaluation of the hazard related to the potential of domino effects is developed. The index considers the actual consequences of possible escalation scenarios and scores or ranks the subsequent accident propagation potential. The effects of inherent and passive protection measures are also assessed. The result is a rapid quantification of domino hazard potential that can provide substantial support for choices in the early stages of layout design. Additionally, a case study concerning selection among various layout options is presented and analyzed. The case study demonstrates the use and applicability of the indices developed in both parts of the current work and highlights the value of introducing inherent safety features early in layout design

  7. Both Automation and Paper.

    Science.gov (United States)

    Purcell, Royal

    1988-01-01

    Discusses the concept of a paperless society and the current situation in library automation. Various applications of automation and telecommunications are addressed, and future library automation is considered. Automation at the Monroe County Public Library in Bloomington, Indiana, is described as an example. (MES)

  8. The stress analysis evaluation and pipe support layout for pressurizer discharge system

    International Nuclear Information System (INIS)

    Mao Qing; Wang Wei; Zhang Yixiong

    2000-01-01

    The author presents the stress analysis and evaluation of pipe layout and support adjustment process for Qinshan phase II pressurizer discharge system. Using PDL-SYSPIPE INTERFACE software, the characteristic parameters of the system are gained from 3-D CAD engineering design software PDL and outputted as the input date file format of special pipe stress analysis program SYSPIPE. Based on that, SYSPIPE program fast stress analysis function is applied in adjusting pipe layout , support layout and support types. According to RCC-M standard, the pipe stress analysis and evaluation under deadweight, internal pressure, thermal expansion, seismic, pipe rupture and discharge loads are fulfilled

  9. Mathematical programming models for solving in equal-sized facilities layout problems. A genetic search method

    International Nuclear Information System (INIS)

    Tavakkoli-Moghaddam, R.

    1999-01-01

    This paper present unequal-sized facilities layout solutions generated by a genetic search program. named Layout Design using a Genetic Algorithm) 9. The generalized quadratic assignment problem requiring pre-determined distance and material flow matrices as the input data and the continuous plane model employing a dynamic distance measure and a material flow matrix are discussed. Computational results on test problems are reported as compared with layout solutions generated by the branch - and bound algorithm a hybrid method merging simulated annealing and local search techniques, and an optimization process of an enveloped block

  10. B-physics performance with Initial and Complete Inner detector layouts in Data Challenge-1

    CERN Document Server

    Benekos, N C; Bouhova-Thacker, E; Epp, B; Ghete, V M; Jones, R; Kartvelishvili, V G; Lagouri, T; Laporte, J F; Nairz, A; Nikitine, N; Reznicek, P; Sivoklokov, S Yu; Smizanska, M; Testa, M; Toms, K

    2004-01-01

    The B-physics performance for the Initial and the Complete Inner Detector layouts is presented. Selected types of B-physics events were simulated, reconstructed and analyzed using the software tools of ATLAS Data Challenge-1 (DC1). The results were compared to those obtained with an older ATLAS detector design the so-called TDR layout. Within the limitations of the DC1 software tools an attempt was made to evaluate the performance loss due to missing detector parts in the Initial layout in comparison with the Complete detector.

  11. dRail: a novel physical layout methodology for power gated circuits

    OpenAIRE

    Mistry, Jatin N.; Biggs, John; Myers, James; Al-Hashimi, Bashir M.; Flynn, David

    2012-01-01

    In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 proces...

  12. A Layout for the Carbon Capture with Aqueous Ammonia without Salt Precipitation

    DEFF Research Database (Denmark)

    Bonalumi, Davide; Valenti, Gianluca; Lillia, Stefano

    2016-01-01

    Post-combustion carbon capture technologies seem to be necessary to realize the CO2 mitigation policies internationally shared for the next future, despite none of them appears to be ready for full-scale applications. This work considers the aqueous ammonia based process for a coal-fired Ultra....... The second layout operates at cooled conditions, which does not yield any salt precipitation. The Chilled layout reveals low specific heat duty and SPECCA equal to 2.2 and 2.86 MJ/kgco2, respectively. In contrast, the Cooled layout presents a higher specific heat duty of almost 3 MJ/kgco2 but, importantly...

  13. Efficiency Optimization by Considering the High Voltage Flyback Transformer Parasitics using an Automatic Winding Layout Technique

    DEFF Research Database (Denmark)

    Thummala, Prasanth; Schneider, Henrik; Zhang, Zhe

    2015-01-01

    .The energy efficiency is optimized using a proposed new automatic winding layout (AWL) technique and a comprehensive loss model.The AWL technique generates a large number of transformer winding layouts.The transformer parasitics such as dc resistance, leakage inductance and self-capacitance are calculated...... for each winding layout.An optimization technique is formulated to minimize the sum of energy losses during charge and discharge operations.The efficiency and energy loss distribution results from the optimization routine provide a deep insight into the high voltage transformer designand its impact...

  14. Piping data retrieval system (PDRS): An integrated package to aid piping layout

    International Nuclear Information System (INIS)

    Vyas, K.N.; Sharma, A.; Susandhi, R.; Basu, S.

    1986-01-01

    An integrated package to aid piping layout has been developed and implemented on PDP-11/34 system at Hall 7. The package allows various equipments to be modelled, consisting of primitive equipment components. The equipment layout for the plant can then be reproduced in the form of drawings such as plan, elevation, isometric or perspective. The package has the built in function to perform hidden line removal among equipments. Once the equipment layout is finalised, the package aids in superimposing the piping as per the specified pipe routine. The report discusses the general capabilities and the major input requirements for the package. (author)

  15. A segmentation algorithm based on image projection for complex text layout

    Science.gov (United States)

    Zhu, Wangsheng; Chen, Qin; Wei, Chuanyi; Li, Ziyang

    2017-10-01

    Segmentation algorithm is an important part of layout analysis, considering the efficiency advantage of the top-down approach and the particularity of the object, a breakdown of projection layout segmentation algorithm. Firstly, the algorithm will algorithm first partitions the text image, and divided into several columns, then for each column scanning projection, the text image is divided into several sub regions through multiple projection. The experimental results show that, this method inherits the projection itself and rapid calculation speed, but also can avoid the effect of arc image information page segmentation, and also can accurate segmentation of the text image layout is complex.

  16. A case study of printing industry plant layout for effective production

    Science.gov (United States)

    Viswajit, T.; Teja, T. Ravi; Deepthi, Y. P.

    2017-07-01

    This paper presents the overall picture of the processes happening in printing industry. This research is aimed to improve the plant layout of existing plant. The travel time was reduced by relocating machinery. Relocation is based on systematic layout planning (SLP). The complete process of raw material entering the industry to dispatching of finished product is shown in 3-D Flow diagram. The process happening in each floor explained in detail using Flow Process chart. Travel time is reduced by 25% after modifying existing plant layout.

  17. Layout design process in conventional Brazilian supermarkets Proceso de formulación de layouts en supermercados convencionales en Brasil Processo de formulação de layouts em supermercados convencionais no Brasil

    Directory of Open Access Journals (Sweden)

    Ana Maria Machado Toaldo

    2010-12-01

    Full Text Available The importance of the layout is well known in the performance of supermarket companies. However since there are very few studies on the subject, this research sought to understand the layout design process in conventionally sized supermarkets in the South of Brazil. For this reason an exploratory study was carried out. The choice of this methodology was due to scarceness of accumulated and systematized knowledge. Data were collected by in-depth interviews with a layout supervisor and a store manager in three supermarket chains in the South of Brazil. Results confirm that layout has considerable influence on company performance. A variety of strategies is used by the companies in layouts to make the customer remain in the store longer, make his stay more enjoyable and consequently encourage spending thus bringing about greater profitability. Finally, a theoretical structure of design layout was proposed. The intention of this study is not to be definitive, but to shed light on the subject, which while important, has never been emphasized in marketing studies.Es evidente la importancia del layout en el desempeño de las empresas supermercadistas. Sin embargo, faltan estudios sobre el tema. Pensando en esa laguna, esta investigación tuvo el objetivo principal de entender como es el proceso de formulación de layouts en supermercados de porte convencional en el Sur brasileño. Para eso, se realizó un estudio exploratorio. La decisión de escoger esa metodología fue en consecuencia de la escasez de conocimiento acumulado y sistematizado. Los datos fueron obtenidos por medio de entrevistas en profundidad realizadas con dos informantes en tres redes supermercadistas del sur de Brasil: un supervisor de layout y un gerente de tienda. Los resultados muestran que el layout tiene mucha influencia en el desempeño de la empresa. Por su intermedio, utilizándose una serie de estrategias, las empresas buscan los siguientes objetivos: hacer con que el

  18. Genetic algorithm optimization for dynamic construction site layout planning

    Directory of Open Access Journals (Sweden)

    Farmakis Panagiotis M.

    2018-02-01

    Full Text Available The dynamic construction site layout planning (DCSLP problem refers to the efficient placement and relocation of temporary construction facilities within a dynamically changing construction site environment considering the characteristics of facilities and work interrelationships, the shape and topography of the construction site, and the time-varying project needs. A multi-objective dynamic optimization model is developed for this problem that considers construction and relocation costs of facilities, transportation costs of resources moving from one facility to another or to workplaces, as well as safety and environmental considerations resulting from facilities’ operations and interconnections. The latter considerations are taken into account in the form of preferences or constraints regarding the proximity or remoteness of particular facilities to other facilities or work areas. The analysis of multiple project phases and the dynamic facility relocation from phase to phase highly increases the problem size, which, even in its static form, falls within the NP (for Nondeterministic Polynomial time- hard class of combinatorial optimization problems. For this reason, a genetic algorithm has been implemented for the solution due to its capability to robustly search within a large solution space. Several case studies and operational scenarios have been implemented through the Palisade’s Evolver software for model testing and evaluation. The results indi­cate satisfactory model response to time-varying input data in terms of solution quality and computation time. The model can provide decision support to site managers, allowing them to examine alternative scenarios and fine-tune optimal solutions according to their experience by introducing desirable preferences or constraints in the decision process.

  19. An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1991-01-01

    A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

  20. 10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

    Science.gov (United States)

    Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

    1985-02-01

    An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.