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Sample records for vlsi design environment

  1. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  2. A Coherent VLSI Design Environment

    Science.gov (United States)

    1987-03-31

    In the figure, AminH and Ama.H represent the smallest and largest eigenvalues I of YH and AminAH and AmaAH represent the smallest and largest...Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International Conference on Computer-Aided

  3. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  4. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  5. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  6. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  7. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  8. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  9. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  10. A Coherent VLSI Environment

    Science.gov (United States)

    1987-03-31

    smallest and largest eigenvalues of YH and AminAH and Am,..AH represent the smallest and largest eigenvalues of YAH, respectively. Fig. 3b illustrates a...101, Princeton U. Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International

  11. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  12. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  13. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  14. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  15. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  16. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  17. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  18. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  19. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  20. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  1. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  2. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  3. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  4. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  5. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  6. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  7. A Coherent VLSI Design Environment

    Science.gov (United States)

    1987-12-31

    April 1, L0 A Mastiplexd Switched-Capacitor Filter Bank, Patrick Bosshart, MIT April 8, IM Analog Circuits in DOS PSI, Yannis Tsividis , Columbia...A.I. (Analog Intelligence), Yanni Tsividis , Columbia University, New York, NY December 2,1986 The Semiconductor Industry (Losing Sight of Your Added...Dept. of Elec. Eng. & Comp. Sci. 3:50 Yannis Tsividis and Dimitri A. Antoniadis, "A Mulitproject Chip i Approach to the Teaching of Analog MOS LSI and

  8. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-09-30

    85-257, September, 1985. e b . . B% V" 4 pathway in bipolar logic. ii) finding a rational and easily automated method for modeling the driving-point...where the resistors are fixed, there is no internodal coupling capacitance, the pullup and pulldown networks have no internal capacitance, and the

  9. A Coherent VLSI Design Environment.

    Science.gov (United States)

    2014-09-26

    physical devices from which physical circuits are fabricated. By analogy with context-free languages , a class of circuits is generated by a phrase-structure... language called CLU [131. It consists of SPICE interface, minimization, and matrix manipulation program modules. These modules contain 3200, 1800, and...greatly simplify the optimization problem. They reformulated the original problem, a minimization subject to nonlinear constraints, as an

  10. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  11. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  12. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  13. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  14. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  15. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  16. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  17. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  18. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  19. Dual Butterfly Match Filter VLSI Design

    Institute of Scientific and Technical Information of China (English)

    LIU Zhenyu; HAN Yueqiu

    2001-01-01

    Match filter is widely used in realtime signal processing, especially in Radar Signal Processing. This paper provides a novel ASIC design,which not only saves resource, but also improves thethroughput of the system. This ASIC is specially designed for Radar Pulse Compression. Certainly it canalso be used in other circumstances, such as FIR filter.

  20. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  1. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  2. Simplified microprocessor design for VLSI control applications

    Science.gov (United States)

    Cameron, K.

    1991-01-01

    A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

  3. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  4. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  5. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  6. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  7. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  8. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  9. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  10. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  11. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  12. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  13. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  14. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  15. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  16. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  17. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  18. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  19. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  20. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  1. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  2. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  3. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  4. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  5. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  6. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  7. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  8. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  9. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  10. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  11. Research News: Are VLSI Microcircuits Too Hard to Design?

    Science.gov (United States)

    Robinson, Arthur L.

    1980-01-01

    This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

  12. Principles of VLSI RTL design a practical guide

    CERN Document Server

    Churiwala, Sanjay; Gianfagna, Mike

    2011-01-01

    This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

  13. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  14. Design and implementation of multipattern generators in analog VLSI.

    Science.gov (United States)

    Kier, Ryan J; Ames, Jeffrey C; Beer, Randall D; Harrison, Reid R

    2006-07-01

    In recent years, computational biologists have shown through simulation that small neural networks with fixed connectivity are capable of producing multiple output rhythms in response to transient inputs. It is believed that such networks may play a key role in certain biological behaviors such as dynamic gait control. In this paper, we present a novel method for designing continuous-time recurrent neural networks (CTRNNs) that contain multiple embedded limit cycles, and we show that it is possible to switch the networks between these embedded limit cycles with simple transient inputs. We also describe the design and testing of a fully integrated four-neuron CTRNN chip that is used to implement the neural network pattern generators. We provide two example multipattern generators and show that the measured waveforms from the chip agree well with numerical simulations.

  15. A digital neuron-type processor and its VLSI design

    Science.gov (United States)

    Akel, H.; Habib, Mahmoud K.

    1989-05-01

    A set of neuron-type circuits elements based on logic gate circuits with multiinput multifan output capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base, and the axon circuit. These three elements are cascaded to form a neuron-type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VSLI techniques.

  16. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  17. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  18. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  19. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  20. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  1. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    Science.gov (United States)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  2. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  3. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  4. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  5. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  6. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  7. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  8. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  9. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  10. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  11. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  12. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  13. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  14. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  15. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  16. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  17. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  18. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  19. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  20. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  1. Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology

    Directory of Open Access Journals (Sweden)

    Joyashree Bag

    2012-12-01

    Full Text Available RFID is a low power wireless emerging technology which has given rise to highly promising applications in real life. It can be employed for robot navigation. In multi-robot environment, when many robots are moving in the same work space, there is a possibility of their physical collision with themselves as well as with physical objects. In the present work, we have proposed and developed a processor incorporating smart algorithm for avoiding such collisions with the help of RFID technology and implemented it by using VHDL. The design procedure and the simulated results are very useful in designing and implementing a practical RFID system. The RTL schematic view of the processor is achieved by successfully synthesizing the proposed design.KEYWORDS

  2. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  3. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  4. Visualization Design Environment

    Energy Technology Data Exchange (ETDEWEB)

    Pomplun, A.R.; Templet, G.J.; Jortner, J.N.; Friesen, J.A.; Schwegel, J.; Hughes, K.R.

    1999-02-01

    Improvements in the performance and capabilities of computer software and hardware system, combined with advances in Internet technologies, have spurred innovative developments in the area of modeling, simulation and visualization. These developments combine to make it possible to create an environment where engineers can design, prototype, analyze, and visualize components in virtual space, saving the time and expenses incurred during numerous design and prototyping iterations. The Visualization Design Centers located at Sandia National Laboratories are facilities built specifically to promote the ''design by team'' concept. This report focuses on designing, developing and deploying this environment by detailing the design of the facility, software infrastructure and hardware systems that comprise this new visualization design environment and describes case studies that document successful application of this environment.

  5. Designing Creative Learning Environments

    Directory of Open Access Journals (Sweden)

    Thomas Cochrane

    2015-05-01

    Full Text Available Designing creative learning environments involves not only facilitating student creativity, but also modeling creative pedagogical practice. In this paper we explore the implementation of a framework for designing creative learning environments using mobile social media as a catalyst for redefining both lecturer pedagogical practice, as well as redesigning the curriculum around student generated m-portfolios.

  6. Designing Creative Learning Environments

    OpenAIRE

    Thomas Cochrane; Laurent Antonczak

    2015-01-01

    Designing creative learning environments involves not only facilitating student creativity, but also modeling creative pedagogical practice. In this paper we explore the implementation of a framework for designing creative learning environments using mobile social media as a catalyst for redefining both lecturer pedagogical practice, as well as redesigning the curriculum around student generated m-portfolios.

  7. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  8. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  9. Rotorcraft Conceptual Design Environment

    Science.gov (United States)

    Johnson, Wayne; Sinsay, Jeffrey D.

    2010-01-01

    Requirements for a rotorcraft conceptual design environment are discussed, from the perspective of a government laboratory. Rotorcraft design work in a government laboratory must support research, by producing technology impact assessments and defining the context for research and development; and must support the acquisition process, including capability assessments and quantitative evaluation of designs, concepts, and alternatives. An information manager that will enable increased fidelity of analysis early in the design effort is described. This manager will be a framework to organize information that describes the aircraft, and enable movement of that information to and from analyses. Finally, a recently developed rotorcraft system analysis tool is described.

  10. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  11. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  12. A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.

    Science.gov (United States)

    Tseng, Yu-Cheng; Hsu, Po-Hsiung; Chang, Tian-Sheuan

    2011-11-01

    This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.

  13. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    OpenAIRE

    Rita M. Shende; Pritesh R. Gumble

    2012-01-01

    Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the prod...

  14. Designing Virtual Learning Environments

    DEFF Research Database (Denmark)

    Veirum, Niels Einar

    2003-01-01

    The main objective of this working paper is to present a conceptual model for media integrated communication in virtual learning environments. The model for media integrated communication is very simple and identifies the necessary building blocks for virtual place making in a synthesis of methods...... from Cultural Media Science, Architecture and Digital Design...

  15. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  16. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  17. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    Directory of Open Access Journals (Sweden)

    Rita M. Shende

    2012-01-01

    Full Text Available Analog-to-digital converters (ADCs are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since theADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially powerconsumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

  18. Future integrated design environments

    DEFF Research Database (Denmark)

    Christiansson, Per; Svidt, Kjeld; Sørensen, Kristian Birch

    2009-01-01

    and modeling of explicit and implicit end-user needs and requirements on both the building to be designed and the supporting design tools. The paper provides grounds to higher success rate in capture of explicit and implicit end user needs and requirements on functional performance in use and re......We are facing a probable great change in the way we carry through design in future ICT supported environments. The main driving forces are the digitalization of information handling leading to a paramount paradigm shift when information storage and access media are separated, building process...... and product systems are formalized in digital models, user environments are provided with rich adaptable multimedia access to virtual models, virtual collaboration rooms established, and new efficient and effective ICT tools defined and implemented. There are though some barriers putting strains...

  19. Future integrated design environments

    DEFF Research Database (Denmark)

    Christiansson, Per; Svidt, Kjeld; Sørensen, Kristian Birch

    2009-01-01

    We are facing a probable great change in the way we carry through design in future ICT supported environments. The main driving forces are the digitalization of information handling leading to a paramount paradigm shift when information storage and access media are separated, building process...... on the development. Among the most important are missing ontologies both on business and Web/Internet service levels as well as their interrelations, poor user involvement in needs and requirements formulations on new ICT tools as well as in continuous user involvement in design and evaluation of new user...... environments, lack of interoperability within building process/product models, and the effects of local community behavior on global scale. The general competence level and preparedness for organizational and work change due to globalization and development of new common grounds for building design needs...

  20. Design of a VLSI charge-coupled device analog delay line

    Science.gov (United States)

    Gedra, David R.

    1995-03-01

    Charge coupled devices (CCD's) are semiconductor devices which can transfer information, represented by a quantity of electrical charge, from one physical location of the semiconductor substrate to another in a controlled manner with the use of properly sequenced clock pulses. These devices can be applied to imaging, signal processing, logic, and digital storage applications. In this thesis, the design of an electrically stimulated CCD analog delay line, using the design tools currently available at the Naval Postgraduate School, is reported on. The major issues addressed are the electrode gate structure and composition, charge confinement techniques, and clocking schemes. Additionally, techniques for inpuning and detecting charge packets from the CCD register are examined. The Metal Oxide Semiconductor Integration Service (MOSIS) design rules only permit Bulk Channel Charge Couple Devices (BCCD's) to be lald out, and not Surface Channel Charge Coupled Devices (SCCD's). Restricted to a die size of 2.24 mm length, the electrode gates were chosen to be polysilicon polysilicon 8 micron length with 2 micron overlap and 20 micron width, giving the BCCD 64 stages. An on chip four phase clocking circuit with output drivers on each phase provides the control voltage for the gate electrodes. The small width of the BCCD delay line utilizes only a small portion of the available 2.22 mm die width. Therefore, four different BCCD's were designed in the layout. Two of the BCCD's have a p-diffusion stop to contain the charge laterally as it propagates along the channel while two BCCD's do not. Additionally, two of the BCCD's utilize the charge partition input technique with three control gates and two BCCD's use the dynamic current injection with one control gate.

  1. VLSI design of lossless frame recompression using multi-orientation prediction

    Science.gov (United States)

    Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

    2016-01-01

    Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

  2. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  3. GLobal Integrated Design Environment

    Science.gov (United States)

    Kunkel, Matthew; McGuire, Melissa; Smith, David A.; Gefert, Leon P.

    2011-01-01

    The GLobal Integrated Design Environment (GLIDE) is a collaborative engineering application built to resolve the design session issues of real-time passing of data between multiple discipline experts in a collaborative environment. Utilizing Web protocols and multiple programming languages, GLIDE allows engineers to use the applications to which they are accustomed in this case, Excel to send and receive datasets via the Internet to a database-driven Web server. Traditionally, a collaborative design session consists of one or more engineers representing each discipline meeting together in a single location. The discipline leads exchange parameters and iterate through their respective processes to converge on an acceptable dataset. In cases in which the engineers are unable to meet, their parameters are passed via e-mail, telephone, facsimile, or even postal mail. The result of this slow process of data exchange would elongate a design session to weeks or even months. While the iterative process remains in place, software can now exchange parameters securely and efficiently, while at the same time allowing for much more information about a design session to be made available. GLIDE is written in a compilation of several programming languages, including REALbasic, PHP, and Microsoft Visual Basic. GLIDE client installers are available to download for both Microsoft Windows and Macintosh systems. The GLIDE client software is compatible with Microsoft Excel 2000 or later on Windows systems, and with Microsoft Excel X or later on Macintosh systems. GLIDE follows the Client-Server paradigm, transferring encrypted and compressed data via standard Web protocols. Currently, the engineers use Excel as a front end to the GLIDE Client, as many of their custom tools run in Excel.

  4. Statistics on VLSI Designs.

    Science.gov (United States)

    1980-04-17

    been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE

  5. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  6. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  7. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  8. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  9. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  10. Space Radiation Environment Prediction for VLSI microelectronics devices onboard a LEO Satellite using OMERE-Trad Software

    Science.gov (United States)

    Sajid, Muhammad

    This tutorial/survey paper presents the assessment/determination of level of hazard/threat to emerging microelectronics devices in Low Earth Orbit (LEO) space radiation environment with perigee at 300 Km, apogee at 600Km altitude having different orbital inclinations to predict the reliability of onboard Bulk Built-In Current Sensor (BBICS) fabricated in 350nm technology node at OptMA Lab. UFMG Brazil. In this context, the various parameters for space radiation environment have been analyzed to characterize the ionizing radiation environment effects on proposed BBICS. The Space radiation environment has been modeled in the form of particles trapped in Van-Allen radiation belts(RBs), Energetic Solar Particles Events (ESPE) and Galactic Cosmic Rays (GCR) where as its potential effects on Device- Under-Test (DUT) has been predicted in terms of Total Ionizing Dose (TID), Single-Event Effects (SEE) and Displacement Damage Dose (DDD). Finally, the required mitigation techniques including necessary shielding requirements to avoid undesirable effects of radiation environment at device level has been estimated /determined with assumed standard thickness of Aluminum shielding. In order to evaluate space radiation environment and analyze energetic particles effects on BBICS, OMERE toolkit developed by TRAD was utilized.

  11. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  12. Space radiation environment prediction for VLSI microelectronics devices onboard a LEO satellite using OMERE-TRAD software

    Science.gov (United States)

    Sajid, Muhammad; Chechenin, N. G.; Torres, Frank Sill; Khan, E. U.; Agha, Shahrukh

    2015-07-01

    Space radiation environment at Low Earth Orbits (LEO) with perigee at 300 km, apogee at 600 km altitude having different orbital inclinations was modeled in the form of electrons and protons trapped in Van Allen Earth Radiation Belts (ERBs), heavy ions and protons in Galactic Cosmic Rays (GCRs), and Energetic Solar Particles (ESP) Events during solar maximum period. The co-relation between various shielding thicknesses and particles transport flux was analyzed for this specific orbit. We observed that there is an optimum shield thickness above which the attenuation of the transmitted flux of incident particles is negligible. To estimate the orbit average differential and integral fluxes to be encountered by onboard devices an appropriate radiation environment models were chosen in OMERE-TRAD toolkit and the impact of various shielding thickness for different orbital inclinations on integral Linear-Energy-Transfer (LET) spectra were determined.

  13. Designing Virtual Learning Environments

    DEFF Research Database (Denmark)

    Veirum, Niels Einar

    2003-01-01

    The main objective of this working paper is to present a conceptual model for media integrated communication in virtual learning environments. The model for media integrated communication is very simple and identifies the necessary building blocks for virtual place making in a synthesis of methods...

  14. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  15. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  16. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  17. 超大规模集成电路可调试性设计综述%Survey of Design-for-Debug of VLSI

    Institute of Scientific and Technical Information of China (English)

    钱诚; 沈海华; 陈天石; 陈云霁

    2012-01-01

    随着硬件复杂度的不断提高和并行软件调试的需求不断增长,可调试性设计已经成为集成电路设计中的重要内容.一方面,仅靠传统的硅前验证已经无法保证现代超大规模复杂集成电路设计验证的质量,因此作为硅后验证重要支撑技术的可调试性设计日渐成为大规模集成电路设计领域的研究热点.另一方面,并行程序的调试非常困难,很多细微的bug无法直接用传统的单步、断点等方法进行调试,如果没有专门的硬件支持,需要耗费极大的人力和物力.全面分析了现有的可调试性设计,在此基础上归纳总结了可调试性设计技术的主要研究方向并介绍了各个方向的研究进展,深入探讨了可调试性结构设计研究中的热点问题及其产生根源,给出了可调试性结构设计领域的发展趋势.%Design-for-debug (DFD) has become an important feature of modern VLSI. On the one hand, traditional pre-silicon verification methods are not sufficient to enssure the quality of modern complex VLSI designs, thus employing DFD to facilitate post-silicon verification has attracted wide interests from both academia and industry; on the other hand, debugging parallel program is a worldwide difficult problem, which cries out for DFD hardware supports. In this paper, we analyze the existing structures of DFD comprehensively and introduce different fields of DFD for debugging hardware and software. These fields contain various kinds of DFD infrastructures, such as the DFD infrastructure for the pipe line of processor, the system-on-chips (SOC) and the networks on multi-cores processor. We also introduce the recent researches on how to design the DFD infrastructures with certain processor architecture and how to use the DFD infrastructures to solve the debug problems in these different fields. The topologic of the whole infrastructure, the hardware design of components, the methods of analyzing signals, the

  18. Designing the Knowledge Integration Environment.

    Science.gov (United States)

    Linn, Marcia C.

    2000-01-01

    Explains Knowledge Integration Environment (KIE) activities which are designed to promote lifelong science learning. Describes the partnership process that guided the design as well as the Scaffolded Knowledge Integration (SKI) framework that gave the partnership a head start on creating effective materials. (Contains 52 references.) (Author/YDS)

  19. RNEDE: Resilient Network Design Environment

    Energy Technology Data Exchange (ETDEWEB)

    Venkat Venkatasubramanian, Tanu Malik, Arun Giridh; Craig Rieger; Keith Daum; Miles McQueen

    2010-08-01

    Modern living is more and more dependent on the intricate web of critical infrastructure systems. The failure or damage of such systems can cause huge disruptions. Traditional design of this web of critical infrastructure systems was based on the principles of functionality and reliability. However, it is increasingly being realized that such design objectives are not sufficient. Threats, disruptions and faults often compromise the network, taking away the benefits of an efficient and reliable design. Thus, traditional network design parameters must be combined with self-healing mechanisms to obtain a resilient design of the network. In this paper, we present RNEDEa resilient network design environment that that not only optimizes the network for performance but tolerates fluctuations in its structure that result from external threats and disruptions. The environment evaluates a set of remedial actions to bring a compromised network to an optimal level of functionality. The environment includes a visualizer that enables the network administrator to be aware of the current state of the network and the suggested remedial actions at all times.

  20. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  1. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  2. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments practical design aspects

    CERN Document Server

    Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    1999-01-01

    We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).

  3. Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Adhiyaman P1 ,

    2014-03-01

    Full Text Available In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF and a novel embedded logic module (DDFF-ELM based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.

  4. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  5. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  6. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  7. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  8. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  9. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  10. Collaborative design in virtual environments

    CERN Document Server

    Wang, Xiangyu

    2011-01-01

    Collaborative virtual environments (CVEs) are multi-user virtual realities which actively support communication and co-operation. This book offers a comprehensive reference volume to the state-of-the-art in the area of design studies in CVEs. It is an excellent mix of contributions from over 25 leading researcher/experts in multiple disciplines from academia and industry, providing up-to-date insight into the current research topics in this field as well as the latest technological advancements and the best working examples. Many of these results and ideas are also applicable to other areas su

  11. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  12. A Method of Neural Network Controller Implementation in VLSI Design%将神经网络控制器用于VLSI设计的方法研究

    Institute of Scientific and Technical Information of China (English)

    詹璨铭

    2015-01-01

    This article presents an approach to neural network implementation in VLSI ,which is called as neural network controller based on Petri net .The structure of the neurons in the network is uniform ;it is triggered by external events ,and output place and transition signals of petri net .Two types of neurons are introduced ,one is standing for serial process ,and the other is used in synchronization of processes .The dual types of neurons are chained together by stimulate inputs ,and compose the fabric .The controller is designed to conquer the side effects of state machine ,and improves the performance and reliability .Typically ,the controller is a precise description of the circuits .It is optimized to timing closure against constraints much easier than state machine .Reduplication of each node in neural network decrease single event upset (SEU) .Finally ,the controller is easy to rebuild .The new design flow has applied in practice ,and proved effectively .%探索在超大规模集成电路中应用神经网络控制器的方法.根据Petri网理论,将库所与变迁组合成神经节点,节点通过输入触发信号链接组成复杂控制网络.定义两种类型神经节点,一种是节点组成串行分枝,另外一种用于同步并发分枝.通过两种节点组合,形成三种基本网络结构,三种结构再次组合又可形成任意复杂控制器结构.根据控制器分枝内串行、分枝间并行的特点,设计编译软件,输入更抽象的分枝描述代码,自动生成对应神经网络控制器逻辑电路描述代码.VLSI设计中使用神经网络控制器,能够更接近了寄存器传输级电路,以及更精确地描述电路,还能提高设计性能与可靠性.复制神经节点减小单节点负载,可优化电路时序;复制节点还可构成冗余缓解空间单粒子翻转.神经网络控制器可以处理各种异常情况,提高功能容错性和可维护性.这种方法已经用

  13. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  14. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  15. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  16. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  17. Interactive Environment Design in Smart City

    Science.gov (United States)

    Deng, DeXiang; Chen, LanSha; Zhou, Xi

    2017-08-01

    The interactive environment design of smart city is not just an interactive progress or interactive mode design, rather than generate an environment such as the “organic” life entity as human beings through interactive design, forming a smart environment with perception, memory, thinking, and reaction.

  18. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  19. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  20. 用于混合信号VLSI的可扩展JTAG控制器IP核设计%Design of Extendable JTAG Controller IP Core for Mixed-signal VLSI

    Institute of Scientific and Technical Information of China (English)

    段延亮; 魏廷存; 高武; 许望洋

    2012-01-01

    The front-end read-out circuit for Positron Emission Tomography(PET) imaging system is a kind of digital-analog mixed-signal VLSI.Based on the features of multi-channel and high performances of these kinds of chip,the JTAG controller is adopted to realize the initial control and auxiliary test of the chip.An extendable JTAG controller IP core is designed using TSMC 0.18 μm CMOS process,which supports 14 groups of extendable control signal and also supports the reading and writing operations of 16 multi-bits registers scan chains,and joins with the customized substrate driving software.The designed JTAG controller IP core can be also used for the controlling and testing of other mixed-signal VLSI,and has good universality and engineering usage.%正电子发射断层成像系统(PET)前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值.

  1. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  2. 2-D DCT Algorithm and Its Reduced VLSI Design%二维DCT算法及其精简的VLSI设计

    Institute of Scientific and Technical Information of China (English)

    陈伟; 卢贵主; 郑灵翔

    2008-01-01

    采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.

  3. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  4. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  5. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  6. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  7. Design and management of sustainable built environments

    CERN Document Server

    2013-01-01

    Climate change is believed to be a great challenge to built environment professionals in design and management. An integrated approach in delivering a sustainable built environment is desired by the built environment professional institutions. The aim of this book is to provide an advanced understanding of the key subjects required for the design and management of modern built environments to meet carbon emission reduction targets. In Design and Management of Sustainable Built Environments, an international group of experts provide comprehensive and the most up-to-date knowledge, covering sustainable urban and building design, management and assessment. The best practice case studies of the implementation of sustainable technology and management from the BRE Innovation Park are included. Design and Management of Sustainable Built Environments will be of interest to urban and building designers, environmental engineers, and building performance assessors.  It will be particularly useful as a reference book ...

  8. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  9. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  10. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  11. A Design Framework for Personal Learning Environments

    NARCIS (Netherlands)

    Rahimi, E.

    2015-01-01

    The purpose of our research was to develop a PLE (personal learning environment) design framework for workplace settings. By doing such, the research has answered this research question, how should a technology-based personal learning environment be designed, aiming at supporting learners to gain

  12. A Design Framework for Personal Learning Environments

    NARCIS (Netherlands)

    Rahimi, E.

    2015-01-01

    The purpose of our research was to develop a PLE (personal learning environment) design framework for workplace settings. By doing such, the research has answered this research question, how should a technology-based personal learning environment be designed, aiming at supporting learners to gain co

  13. A Design Framework for Personal Learning Environments

    NARCIS (Netherlands)

    Rahimi, E.

    2015-01-01

    The purpose of our research was to develop a PLE (personal learning environment) design framework for workplace settings. By doing such, the research has answered this research question, how should a technology-based personal learning environment be designed, aiming at supporting learners to gain co

  14. Design Environments for Material Performance

    DEFF Research Database (Denmark)

    Tamke, Martin; Burry, Mark; Ayres, Phil

    2011-01-01

    The research project that induced the Dermoid installation investigates the making of digital tools by which architects and engineers can work intelligently with material performance. Working with wood as a material, we were especially interested in how the bend and flex of wood can become...... an active parameter in the digital design process....

  15. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  16. Stigmergy in the design of social environments

    Science.gov (United States)

    Borghini, S. G.

    2017-01-01

    The paper argues that physical environments are relevant and at time critical elements of the cognitive activities of individual agents and communities, and this should become an important consideration in designing such environments. To this end, the concept of stigmergy can be instrumental to the evaluation and design of environments that facilitate cognitive and information processing activities of human individuals and communities. Stigmergy is here introduced both as an explanatory principle and as the operative mechanism by which structured environments can operate as mediums of shared knowledge and mediators of self-organizing processes of coordination among loosely coupled individuals. The arguments are supported by three case studies.

  17. Stigmergy in the design of social environments

    Science.gov (United States)

    Borghini, S. G.

    2017-01-01

    The paper argues that physical environments are relevant and at time critical elements of the cognitive activities of individual agents and communities, and this should become an important consideration in designing such environments. To this end, the concept of stigmergy can be instrumental to the evaluation and design of environments that facilitate cognitive and information processing activities of human individuals and communities. Stigmergy is here introduced both as an explanatory principle and as the operative mechanism by which structured environments can operate as mediums of shared knowledge and mediators of self-organizing processes of coordination among loosely coupled individuals. The arguments are supported by three case studies.

  18. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  19. Design for the Environment Products (Raw Data)

    Data.gov (United States)

    U.S. Environmental Protection Agency — This dataset contains a list of products that carry the Design for the Environment (DfE) label. This mark enables consumers to quickly identify and choose products...

  20. Design for the Environment Products (Online Search)

    Data.gov (United States)

    U.S. Environmental Protection Agency — This dataset contains a list of products that carry the Design for the Environment (DfE) label. This mark enables consumers to quickly identify and choose products...

  1. Designing open learning environments for professional development

    NARCIS (Netherlands)

    Sloep, Peter

    2011-01-01

    Sloep, P. B. (2011). Designing open learning environments for professional development. Presentation at the FP7 Handover Project Meeting. April, 9, 2011, Amsterdam, The Netherlands: Open University in the Netherlands.

  2. Designing open learning environments for professional development

    NARCIS (Netherlands)

    Sloep, Peter

    2011-01-01

    Sloep, P. B. (2011). Designing open learning environments for professional development. Presentation at the FP7 Handover Project Meeting. April, 9, 2011, Amsterdam, The Netherlands: Open University in the Netherlands.

  3. User Interactive Guided Search Design Environment Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Phoenix Integration's vision is to create an intuitive human-in-the-loop engineering design environment called Guided Search that leverages recent advances in...

  4. Designing Learning Resources in Synchronous Learning Environments

    DEFF Research Database (Denmark)

    Christiansen, Rene B

    2015-01-01

    Computer-mediated Communication (CMC) and synchronous learning environments offer new solutions for teachers and students that transcend the singular one-way transmission of content knowledge from teacher to student. CMC makes it possible not only to teach computer mediated but also to design...... and create new learning resources targeted to a specific group of learners. This paper addresses the possibilities of designing learning resources within synchronous learning environments. The empirical basis is a cross-country study involving students and teachers in primary schools in three Nordic...... Countries (Denmark, Sweden and Norway). On the basis of these empirical studies a set of design examples is drawn with the purpose of showing how the design fulfills the dual purpose of functioning as a remote, synchronous learning environment and - using the learning materials used and recordings...

  5. Virtual environments for nuclear power plant design

    Energy Technology Data Exchange (ETDEWEB)

    Brown-VanHoozer, S.A.; Singleterry, R.C. Jr.; King, R.W. [and others

    1996-03-01

    In the design and operation of nuclear power plants, the visualization process inherent in virtual environments (VE) allows for abstract design concepts to be made concrete and simulated without using a physical mock-up. This helps reduce the time and effort required to design and understand the system, thus providing the design team with a less complicated arrangement. Also, the outcome of human interactions with the components and system can be minimized through various testing of scenarios in real-time without the threat of injury to the user or damage to the equipment. If implemented, this will lead to a minimal total design and construction effort for nuclear power plants (NPP).

  6. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  7. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  8. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  9. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  10. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  11. Psychosocially supportive design in the indoor environment

    OpenAIRE

    Fischl, Geza

    2006-01-01

    A built environment is psychosocially supportive, when its quality can strengthen or sustain the ability of an individual to perform his/her role, conduct him-/herself in society, and communicate or interact with others in accordance to his/her values, interest, and self-concept. The aim of this thesis was to investigate potential methods in design and re-design for identification, visualization, and evaluation of such environmental qualities. The thesis is divided into two main theoretical a...

  12. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  13. An Experiential Exercise in Service Environment Design

    Science.gov (United States)

    Fowler, Kendra; Bridges, Eileen

    2012-01-01

    A new experiential exercise affords marketing students the opportunity to learn to design service environments. The exercise is appropriate for a variety of marketing courses and is especially beneficial in teaching services marketing because the proposed activity complements two other exercises widely used in this course. Service journal and…

  14. An Experiential Exercise in Service Environment Design

    Science.gov (United States)

    Fowler, Kendra; Bridges, Eileen

    2012-01-01

    A new experiential exercise affords marketing students the opportunity to learn to design service environments. The exercise is appropriate for a variety of marketing courses and is especially beneficial in teaching services marketing because the proposed activity complements two other exercises widely used in this course. Service journal and…

  15. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  16. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  17. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  18. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  19. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  20. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  1. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  2. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  3. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 2: Hardware design verification

    Science.gov (United States)

    Carlan, A. J.; Breuer, M. A.

    1982-10-01

    The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

  4. Designing Assessments and Assessing Designs in Virtual Educational Environments

    Science.gov (United States)

    Hickey, Daniel T.; Ingram-Goble, Adam A.; Jameson, Ellen M.

    2009-01-01

    This study used innovative assessment practices to obtain and document broad learning outcomes for a 15-hour game-based curriculum in Quest Atlantis, a multi-user virtual environment that supports school-based participation in socio scientific inquiry in ecological sciences. Design-based methods were used to refine and align the enactment of…

  5. Multiple metaphor environments: designing for diversity.

    Science.gov (United States)

    Akoumianakis, D; Stephanidis, C

    2003-01-15

    This paper advances a proposition for the engineering of interactive computer-based environments capable of exhibiting alternative interactive embodiments to cope with diversity in users, interaction platforms and usage contexts. Such systems are referred to as Multiple Metaphor Environments (MME). The theoretical underpinnings of an MME rely on a conception of HCI design as mapping functions in a machine-oriented language (target domain) to symbols in a user-oriented language (source domain), and vice versa. Such a conception, which is rooted in developments in communication theory and the philosophy of language, constitutes the baseline for formulating a proposal for the design of MME. The proposal comprises a set of engineering principles, process-oriented guidelines and design techniques intended to facilitate a detailed account of how interactive systems could be designed to cope with diversity. To aid the articulation of the various properties of MME, we refer to concrete case studies that provide exemplars of novel insights and promising design practices towards the specification of MME.

  6. Design of supply chain in fuzzy environment

    Science.gov (United States)

    Rao, Kandukuri Narayana; Subbaiah, Kambagowni Venkata; Singh, Ganja Veera Pratap

    2013-05-01

    Nowadays, customer expectations are increasing and organizations are prone to operate in an uncertain environment. Under this uncertain environment, the ultimate success of the firm depends on its ability to integrate business processes among supply chain partners. Supply chain management emphasizes cross-functional links to improve the competitive strategy of organizations. Now, companies are moving from decoupled decision processes towards more integrated design and control of their components to achieve the strategic fit. In this paper, a new approach is developed to design a multi-echelon, multi-facility, and multi-product supply chain in fuzzy environment. In fuzzy environment, mixed integer programming problem is formulated through fuzzy goal programming in strategic level with supply chain cost and volume flexibility as fuzzy goals. These fuzzy goals are aggregated using minimum operator. In tactical level, continuous review policy for controlling raw material inventories in supplier echelon and controlling finished product inventories in plant as well as distribution center echelon is considered as fuzzy goals. A non-linear programming model is formulated through fuzzy goal programming using minimum operator in the tactical level. The proposed approach is illustrated with a numerical example.

  7. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Sudarshan Tiwari

    2012-05-01

    Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.

  8. Designing (for) experiences in photorealistic VR environments

    Science.gov (United States)

    Carroll, Fiona

    2010-04-01

    This paper investigates the role of aesthetics in the design of "intended" experiences in photorealistic virtual reality (VR) environments. It is motivated by the very notion that the aesthetic potential of photorealistic VR content is, and continues to be, underestimated whilst the emphasis on the development of newer and more efficient visualisation technologies to create new and exciting VR experiences increases. Challenging this, the paper looks beyond the technological (and the more traditional human computer interaction approaches that have primarily focused on the performance and efficiency issues of the technology) in order to explore more human values and the experiential side of VR. It focuses on the design of an "engaged interaction" and in doing so, implements a comparative study to explore how the strategic patterning of the aesthetic elements (particularly colour) within a photorealistic VR environment can allow for the design of a certain experience. In conclusion, the paper demonstrates that aesthetics and the "engaged interaction" can play an important role in getting to the heart of the photorealistic VR "user" experience. It highlights how we might design for (i.e. suggest, coax and guide) an "intended" VR experience.

  9. Collaborative software design in an SOA environment

    Institute of Scientific and Technical Information of China (English)

    W.T. TSAI; Bingnan XIAO; Qian HUANG; Yinong CHEN

    2006-01-01

    Based on the current Service-Oriented Architecture (SOA), this paper proposes a new collaborative software design methodology in an SOA Environment: the Global Software Enterprise (GSE). The current SOA is producer-centric, in which the service providers publish services that they produce and let the consumers to search available services to compose their applications. GSE is build on top of Consumer-Centric SOA (CCSOA), in which the application builders publish their application requirements for the service providers to follow when producing or customizing services to support the application. This new methodology reduces the workload and improves the application description capability of the service consumers. It also extends the capacity of design and code sharing, and thus further improves the software productivity. This paper presents the concepts, architecture, enabling techniques, and illustrative examples of collaborative software design in GSE.

  10. International space station microgravity environment design & verification

    Science.gov (United States)

    Del Basso, Steve

    1999-01-01

    A broad class of scientific experiments has evolved which utilize extreme low acceleration environments. The International Space Station will provide such a ``microgravity'' environment, in conjunction with an unparalleled combination of quiescent period duration, payload volume and power, and manned or telescience interaction. The International Space Station is the world's first manned space vehicle with microgravity requirements. These place limits on the acceleration levels within the pressurized laboratories and affect everything from flight altitude and attitude to the mechanical and acoustic energies emitted by an air circulation fan. To achieve such performance within the program's resource constraints, a microgravity control approach has been adopted which balances both source and receiver disturbance mitigation. The Active Rack Isolation System (ARIS) provides acceleration attenuation at the payload rack level, and dominant sources have been reduced either by isolation or design modifications. Analytical assessments indicate that the vehicle is capable of meeting the challenging microgravity requirements, although some current marginal non-compliances do exist. Assessment refinements will continue through the verification phase with greater reliance on test and on-orbit measured data as part of a long term effort to clearly define and understand the constitution of the acceleration environment. This process will assure that the design and operation of the International Space Station will support significant microgravity science research.

  11. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  12. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  13. Designing better healthcare environments: interprofessional competencies in healthcare design.

    Science.gov (United States)

    Lamb, Gerri; Zimring, Craig; Chuzi, Joshua; Dutcher, Diane

    2010-07-01

    There has been considerable interest in bridging educational programs in the United States across healthcare, architecture, industrial design, and human computing disciplines to design more effective and safer healthcare environments. New combinations of professionals including those outside the traditional healthcare disciplines are coming together to solve quality and safety problems and to re-envision the physical and social design of healthcare organizations. Little is known about the knowledge and skills essential to integrate these diverse perspectives and pose innovative solutions. A set of seven interprofessional competencies were identified through review of the literature, interviews of faculty and leaders in the field, and experience of the authors teaching interprofessional courses in healthcare design. The relevance and feasibility of these competencies were assessed through expert review by faculty and consultants and implementation in multiple courses.

  14. Telemedicine Workplace Environments: Designing for Success

    Directory of Open Access Journals (Sweden)

    Elizabeth A. Krupinski

    2014-02-01

    Full Text Available When designing a facility for telemedicine, there are several things to consider from a human factors point of view, as well as from a practicality point of view. Although the future practice of telemedicine is likely to be more of a mobile-based practice and centered more in the home than it is now, it is still very important to consider ways to optimize the design of clinic-based telemedicine facilities. This is true on both ends of a consultation—where the patient is and where the consultant is. On the patient side, the first thing to realize is that most telemedicine clinics are not going to be newly designed and built. In all likelihood they will be existing rooms converted to telemedicine clinic rooms. Quite often the former room will not even have been used for clinical purposes, but may have simply been a storage area cleared out for telemedicine use. Therefore, design is often a challenge but there are a few basic principles that can be followed to create a workable clinical space. This paper will review some of the basic human factors principles to take into account when designing a working telemedicine environment.

  15. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  16. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  17. Approaches to Integrated Building Design Environments

    DEFF Research Database (Denmark)

    Bagger-Petersen, Susanne C; Andersen, Tom

    1996-01-01

    This report discusses functional requirements and specification which needs to be defined and fulfilled to initiate development of an integrated building design environment. The purpose is to outline specifications for further discussion and development. The report documents the first phase...... in an ongoing project at the Technical University of Denmark. The overall project objective is to provide a theoretically well-founded prototype of an integrated IT-system which can serve as a device of feedback from practice and as a test-bed for the developed concept and architecture....

  18. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  19. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  20. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  1. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  2. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  3. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  4. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  5. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  6. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  7. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  8. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  9. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  10. Autonomous Mission Design in Extreme Orbit Environments

    Science.gov (United States)

    Surovik, David Allen

    An algorithm for autonomous online mission design at asteroids, comets, and small moons is developed to meet the novel challenges of their complex non-Keplerian orbit environments, which render traditional methods inapplicable. The core concept of abstract reachability analysis, in which a set of impulsive maneuvering options is mapped onto a space of high-level mission outcomes, is applied to enable goal-oriented decision-making with robustness to uncertainty. These nuanced analyses are efficiently computed by utilizing a heuristic-based adaptive sampling scheme that either maximizes an objective function for autonomous planning or resolves details of interest for preliminary analysis and general study. Illustrative examples reveal the chaotic nature of small body systems through the structure of various families of reachable orbits, such as those that facilitate close-range observation of targeted surface locations or achieve soft impact upon them. In order to fulfill extensive sets of observation tasks, the single-maneuver design method is implemented in a receding-horizon framework such that a complete mission is constructed on-the-fly one piece at a time. Long-term performance and convergence are assured by augmenting the objective function with a prospect heuristic, which approximates the likelihood that a reachable end-state will benefit the subsequent planning horizon. When state and model uncertainty produce larger trajectory deviations than were anticipated, the next control horizon is advanced to allow for corrective action -- a low-frequency form of feedback control. Through Monte Carlo analysis, the planning algorithm is ultimately demonstrated to produce mission profiles that vary drastically in their physical paths but nonetheless consistently complete all goals, suggesting a high degree of flexibility. It is further shown that the objective function can be tuned to preferentially minimize fuel cost or mission duration, as well as to optimize

  11. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  12. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  13. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  14. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  15. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  16. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  17. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  18. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  19. Designing Environment for Teaching Internet of Things

    Science.gov (United States)

    Simic, Konstantin; Vujin, Vladimir; Labus, Aleksandra; Stepanic, Ðorde; Stevanovic, Mladen

    2014-01-01

    One of the new topics taught at technical universities is Internet of Things. In this paper, a workshop for organizing a lab in academic environment for the subject Internet of Things is described. The architecture of the platform, scenario and a description of components used for creating the environment for learning Internet of things are also…

  20. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  1. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  2. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  3. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  4. A Knowledge-based and Extensible Aircraft Conceptual Design Environment

    Institute of Scientific and Technical Information of China (English)

    FENG Haocheng; LUO Mingqiang; LIU Hu; WU Zhe

    2011-01-01

    Design knowledge and experience are the bases to carry out aircraft conceptual design tasks due to the high complexity and integration of the tasks during this phase.When carrying out the same task,different designers may need individual strategies to fulfill their own demands.A knowledge-based and extensible method in building aircraft conceptual design systems is studied considering the above requirements.Based on the theory,a knowledge-based aircraft conceptual design environment,called knowledge-based and extensible aircraft conceptual design environment (KEACDE) with open architecture,is built as to enable designers to wrap add-on extensions and make their own aircraft conceptual design systems.The architecture,characteristics and other design and development aspects of KEACDE are discussed.A civil airplane conceptual design system (CACDS) is achieved using KEACDE.Finally,a civil airplane design case is presented to demonstrate the usability and effectiveness of this environment.

  5. Multi-Disciplinary Multi-Fidelity Design Environment Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Phoenix Integration will develop a collaborative simulation and design environment that will seamlessly integrate the people, data, and tools required for analyzing...

  6. Design automation, languages, and simulations

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume covers a broad range of topics relevant to design automation, languages, and simulations. These include a collaborative framework that coordinates distributed design activities through the Internet, an overview of the Verilog hardware description language and its use in a design environment, hardware/software co-design, syst

  7. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  8. Reconfiguring Course Design in Virtual Learning Environments

    DEFF Research Database (Denmark)

    Mullins, Michael; Zupancic, Tadeja

    2007-01-01

    Although many administrators and educators are familiar with e-learning programs, learning management systems and portals, fewer may have experience with virtual distributed learning environments and their academic relevance. The blended learning experience of the VIPA e-learning project for arch......Although many administrators and educators are familiar with e-learning programs, learning management systems and portals, fewer may have experience with virtual distributed learning environments and their academic relevance. The blended learning experience of the VIPA e-learning project...

  9. Investigating design issues in household environments

    DEFF Research Database (Denmark)

    Baillie, Lynne; Benyon, David; Macauley, Catriona

    2003-01-01

    This paper argues that the current involvement of end users in the design of technological artefacts is too superficial. It is common to involve people in requirements generation, but rarely in product inception or design. A study is reported involving five households in central Scotland, who were...... each visited on three occasions, using a new investigative framework. Illustrative examples are provided of the strengths and weaknesses of the methods used. Despite the latter, it is demonstrated that the general public can both generate and critique design ideas and that valuable contributions...... to understanding people's relationships with technologies can be expected both from children and from the elderly....

  10. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  11. Adding Intelligence to a Learning Environment: Learner-Centred Design?

    Science.gov (United States)

    Brna, Paul; Cox, R.

    1998-01-01

    Discussion of learner-centered design focuses on the development of switchEr, a specific learning environment changed to an intelligent learning environment by switching from one external representation (ER) to another. Topics include user-centered design; the role of artificial intelligence; and the development of effective educational computing…

  12. Design of New Food Technology: Social Shaping of Working Environment

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design process is seen as a network building activity and as a social shaping process of the artefact. A working environment log...

  13. Design Milieux for Learning Environments in African Contexts

    Science.gov (United States)

    Duveskog, Marcus; Sutinen, Erkki; Cronje, Johannes

    2014-01-01

    During the years 2002 to 2009, five African settings were used as foundation for designing different learning environments. While the content and target group for each learning environment varied, all of their design settings, or milieux, shared one implicit expectation: the milieu should facilitate the production of a change-making learning…

  14. Design of New Food Technology: Social Shaping of Working Environment

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design process is seen as a network building activity and as a social shaping process of the artefact. A working environment log is s...

  15. Architectural design and the collaborative research environment.

    Science.gov (United States)

    Goldstein, Roger N

    2006-10-20

    Given that science is a collaborative endeavor, architects are striving to design new research buildings that not only provide a more pleasant work space but also facilitate interactions among researchers.

  16. Designing areas and elements in traffic environment for disabled people

    OpenAIRE

    Markovič, Anja

    2011-01-01

    Traffic environment is one of the most dangerous areas in human's everyday because of interweaving between pedestrian's paths and traffic. Disabled people are even more undangered in this kind of areas. Graduation thesis describes elements and measures for designing traffic environment according to different types of human disability and their requirements with intention to build transitional and safe environment for everyone. It describes tehnical elements of designing areas and different ki...

  17. Knowledge management in the engineering design environment

    Science.gov (United States)

    Briggs, Hugh C.

    2006-01-01

    The Aerospace and Defense industry is experiencing an increasing loss of knowledge through workforce reductions associated with business consolidation and retirement of senior personnel. Significant effort is being placed on process definition as part of ISO certification and, more recently, CMMI certification. The process knowledge in these efforts represents the simplest of engineering knowledge and many organizations are trying to get senior engineers to write more significant guidelines, best practices and design manuals. A new generation of design software, known as Product Lifecycle Management systems, has many mechanisms for capturing and deploying a wider variety of engineering knowledge than simple process definitions. These hold the promise of significant improvements through reuse of prior designs, codification of practices in workflows, and placement of detailed how-tos at the point of application.

  18. A Distributed Feature-based Environment for Collaborative Design

    Directory of Open Access Journals (Sweden)

    Wei-Dong Li

    2003-02-01

    Full Text Available This paper presents a client/server design environment based on 3D feature-based modelling and Java technologies to enable design information to be shared efficiently among members within a design team. In this environment, design tasks and clients are organised through working sessions generated and maintained by a collaborative server. The information from an individual design client during a design process is updated and broadcast to other clients in the same session through an event-driven and call-back mechanism. The downstream manufacturing analysis modules can be wrapped as agents and plugged into the open environment to support the design activities. At the server side, a feature-feature relationship is established and maintained to filter the varied information of a working part, so as to facilitate efficient information update during the design process.

  19. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  20. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  1. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  2. 低成本可调FFT处理器的超大规模集成电路设计%Low Cost VLSI Design of a Flexible FFT Processor

    Institute of Scientific and Technical Information of China (English)

    戴亦奇

    2011-01-01

    In this paper, a radix-22/23 based pipeline structure is presented, in order to implement a low-cost VLSI fast Fourier transform (FFT) processor. As well as reducing the steps of normal complex multiplications, it minimizes the memory words to get the FFT results with the single-path delay feedback (SDF) memory access method. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements.%文章提出了一种以基-22/23为基础的流水线结构,用以实现低成本、超大规模集成电路(VLSI)的快速傅里叶变换(FFT)处理器设计。该处理器在减少普通复数乘法器级数的同时,通过单路延时反馈(SDF)存取方式,以最少的存储字来获得FFT结果。对于数据通路,我们采用了混合浮点的数据缩放方式,在保证信噪比的同时,降低了数据长度和RAM容量的需求。

  3. Reconfiguring Course Design in Virtual Learning Environments

    DEFF Research Database (Denmark)

    Mullins, Michael; Zupancic, Tadeja

    2007-01-01

    Although many administrators and educators are familiar with e-learning programs, learning management systems and portals, fewer may have experience with virtual distributed learning environments and their academic relevance. The blended learning experience of the VIPA e-learning project...... for architectural students offers some innovative insights into experientially oriented educational interfaces. A comparative analysis of VIPA courses and project results are presented in the paper. Special attention in the discussion is devoted to the improvements of e-learning solutions in architecture....... The criterion of the relation between the actual applicability of selected e-learning solutions and elements of collaborative educational interfaces with VR are taken into account. A system of e-learning applicability levels in program and course development and implementation of architectural tectonics...

  4. Collaborative Design in PDM/3D CAD Integrated Environment

    Institute of Scientific and Technical Information of China (English)

    CHEN Zhuoning; ZHANG Fen; YAN Xiaoguang; BIN Hongzan

    2006-01-01

    Some key issues in supporting collaborative design in product data management (PDM) system and 3D computer aided design(CAD) system integrated environment are analyzed. The general architecture of the integrated environment is divided into five tiers and employs the transparently integrated mode, with the mode, function calling and information exchanging among independent PDM and CAD processes are carried out via message translation /parse approach.Product layout feature(PLF ) model definition is presented,PLF model is used to represent design intention at the preliminary design phase. The collaborative design methodology employing the PLF model in PDM/3D CAD integrated environment is analyzed. The design methodology can speed up the design process, reduce the investment and improve the product quality.

  5. Designing safer living environments support for local government

    CSIR Research Space (South Africa)

    Landman, K

    1999-06-01

    Full Text Available This paper addresses the built environment, the opportunities it presents for crime and the role city planners and urban designers have to play in the design of safer cities and towns. City planners and urban designers can play a role...

  6. Design of a Networked Learning Master Environment for Professionals

    DEFF Research Database (Denmark)

    2010-01-01

    The paper is presenting the overall learning design of MIL (Master in ICT and Learning). The learning design is integrating a number of principles: 1. Principles of problem and project based learning 2. Networked learning / learning in communities of practice. The paper will discuss how...... these principles interact productively in the design of a networked learning environment for professionals....

  7. The Curriculum Design and Development in MOOCs Environment

    Science.gov (United States)

    Li, Fei; Du, Jing; Li, Bin

    2014-01-01

    The paper selects over 20 online courses and analyses the subjects, organization, the way to show the content of the courses, the use of media, and design of the teaching in the case study of Chinese popular MOOC platform. On this basis, the paper summarizes the principles of curriculum design and design models in MOOC environment, such as…

  8. Design Rework Prediction in Concurrent Design Environment: Current Trends and Future Research Directions

    OpenAIRE

    Arundachawat, Panumas; Roy, Rajkumar; Al-Ashaab, Ahmed; Shehab, Essam

    2009-01-01

    This paper aims to present state-of-the-art and formulate future research areas on design rework in concurrent design environment. Related literatures are analysed to extract the key factors which impact design rework. Design rework occurs due to changes from upstream design activities and/or by feedbacks from downstream design activities. Design rework is considered as negative iteration; therefore, value in design activities will be increased if design rework is reduced. Set-bas...

  9. Encoder designed to work in harsh environments

    Energy Technology Data Exchange (ETDEWEB)

    Toop, L.

    2007-05-15

    Dynapar has developed the Acuro AX71 absolute encoder for use on offshore or land-based oil rig operations. It provides feedback on the operation of automated systems such as draw works, racking systems, rotary tables and top drives. By ensuring that automated systems function properly, this encoder responds to a need by the oil and gas industry to keep workers safe and improve efficiency, particularly for operations in rugged situations. The encoder provides feedback from motor systems to controllers, giving information about position and speed of downhole drill bits. This newly developed encoder is better than commonly used incremental encoders which are not precise in strong electrical noise environments. Rather, the absolute encoder uses a different method of reporting to the controller. A digital signal is transmitted constantly as the device operates. It is less susceptible to noise issues. It is highly accurate, tolerant of noise and is not affected by power outages. However, the absolute encoder is generally more delicate in drilling applications with high ambient temperatures and shock levels. Dynapar addressed this issue by developing compact stainless steel housing that is useful for corrosion resistance in marine applications. The AX71 absolute encoder can withstand up to 100 G of mechanical shock and ambient temperatures of up to 60 degrees C. The encoder is ATEX certified without barriers, and offers the high resolution feedback of 4,000 counts of multiturn rotation and 16,000 counts of position. 1 fig.

  10. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  11. Learning Design Implementation in SCORM E-Learning Environment

    NARCIS (Netherlands)

    Shoikova, Elena; Ivanova, Malinka

    2006-01-01

    Please, cite this publication as: Shoikova, L., & Ivanova, E. (2006). Learning Design Implementation in SCORM E-Learning Environment. Proceedings of International Workshop in Learning Networks for Lifelong Competence Development, TENCompetence Conference. March 30th-31st, Sofia, Bulgaria: TENCompete

  12. Designing user models in a virtual cave environment

    Energy Technology Data Exchange (ETDEWEB)

    Brown-VanHoozer, S. [Argonne National Lab., Idaho Falls, ID (United States); Hudson, R. [Argonne National Lab., IL (United States); Gokhale, N. [Madge Networks, San Jose, CA (United States)

    1995-12-31

    In this paper, the results of a first study into the use of virtual reality for human factor studies and design of simple and complex models of control systems, components, and processes are described. The objective was to design a model in a virtual environment that would reflect more characteristics of the user`s mental model of a system and fewer of the designer`s. The technology of a CAVE{trademark} virtual environment and the methodology of Neuro Linguistic Programming were employed in this study.

  13. Internet-centric collaborative design in a distributed environment

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Hyun; Kim, Hyoung Sun; Do, Nam Chul; Lee, Jae Yeol; Lee, Joo Haeng [Electronics and telecommunications Research Institute, Taejon (Korea, Republic of); Myong, Jae Hyong [nXEN, Taejon (Korea, Republic of)

    2001-07-01

    Recently, advanced information technologies including internet-related technology and distributed object technology have opened new possibilities for collaborative designs. In this paper, we discuss computer supports for collaborative design in a distributed environment. The proposed system is the internet-centric system composed of an engineering framework, collaborative virtual workspace and engineering service. It allows the distributed designers to more efficiently and collaboratively work their engineering tasks throughout the design process.

  14. Gene–Environment Interaction: Definitions and Study Designs

    OpenAIRE

    Ottman, Ruth

    1996-01-01

    Study of gene–environment interaction is important for improving accuracy and precision in the assessment of both genetic and environmental influences. This overview presents a simple definition of gene–environment interaction and suggests study designs for detecting it. Gene–environment interaction is defined as “a different effect of an environmental exposure on disease risk in persons with different genotypes,” or, alternatively, “a different effect of a genotype on disease risk in persons...

  15. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  16. CASTE Revisited: Principles of Course Design in a Hypertext Environment.

    Science.gov (United States)

    Scott, Bernard

    2000-01-01

    Describes CASTE (Course Assembly System and Tutorial Environment) that was developed to help students choose appropriate learning strategies in a hypertext environment. Highlights include the need for principles of course design; resource-based learning and computer-aided learning; conversation theory; and a comparison to other approaches.…

  17. Standardization of green building technologies for environment design

    Directory of Open Access Journals (Sweden)

    Benuzh Andrey

    2016-01-01

    Full Text Available The article describes the structure and field of standardization ISO / TC 205 “Building environment design”, provides examples of green building technologies. The main purpose of the article is to show the interaction between international ISO / TC 205 “Building environment design” and created in Russia in 2016 the Technical Committee of Standardization № 366 “Green technology of the build environment and green innovative products”. Both of these technical committees promote green building technologies for environment design, thereby deal with the negative impact on the environment and the reasons of global warming. Instead of buildings that attempt to suppress and overcome nature, why not design buildings that integrate with the environment, on every possible level? The international standardization work which ISO/TC 205 “Building environment design” performs seeks, in addition to lowering trade barriers for engineering design, to promote and facilitate the design of high performance buildings: higher performing as economic assets for their owners, higher performing as buildings that provide amenable indoor environment for their occupants, and higher performing with respect to resource utilization and environmental impact.

  18. Temporal Issues in the Design of Virtual Learning Environments.

    Science.gov (United States)

    Bergeron, Bryan; Obeid, Jihad

    1995-01-01

    Describes design methods used to influence user perception of time in virtual learning environments. Examines the use of temporal cues in medical education and clinical competence testing. Finds that user perceptions of time affects user acceptance, ease of use, and the level of realism of a virtual learning environment. Contains 51 references.…

  19. A Web Based Collaborative Design Environment for Spacecraft

    Science.gov (United States)

    Dunphy, Julia

    1998-01-01

    In this era of shrinking federal budgets in the USA we need to dramatically improve our efficiency in the spacecraft engineering design process. We have come up with a method which captures much of the experts' expertise in a dataflow design graph: Seamlessly connectable set of local and remote design tools; Seamlessly connectable web based design tools; and Web browser interface to the developing spacecraft design. We have recently completed our first web browser interface and demonstrated its utility in the design of an aeroshell using design tools located at web sites at three NASA facilities. Multiple design engineers and managers are now able to interrogate the design engine simultaneously and find out what the design looks like at any point in the design cycle, what its parameters are, and how it reacts to adverse space environments.

  20. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  1. Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac%面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现

    Institute of Scientific and Technical Information of China (English)

    潘志鹏; 吴斌; 尉志伟; 叶甜春

    2015-01-01

    针对IEEE 802.11i协议中多种安全协议实现进行研究,结合以IEEE 802.11ac协议为代表的下一代无线局域网( WLAN)系统对高吞吐率的需求,提出了一种支持WEP/TKIP/CCMP协议的多模、高速安全加速引擎的大规模集成电路( VLSI)架构. 提出了基于哈希算法的密钥信息查找算法,缩小了查找时钟延迟. 基于复合域的运算方式实现高级加密标准( AES)算法,提出双AES运算核的并行架构实现计数器与密码分组链接( CCM)模式,提升运算吞吐率的同时也降低了引擎的响应延迟. 经过FPGA实现和ASIC流片验证表明,该安全加速引擎具备可重构性,处理延迟仅为33个时钟周期,在322 MHz工作频率下运算吞吐率可达3.747 Gbit/s.%In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration ( VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP proto-cols was presented taking into account the demand for high throughput of the next generation wireless local area net-work ( WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryp-tion standard ( AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code ( CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz.

  2. The integrated and evidence-based design of healthcare environments.

    NARCIS (Netherlands)

    van Hoof, J.; Rutten, P.G.S.; Struck, C.; Huisman, E.R.C.M.; Kort, H.S.M.

    2014-01-01

    van Hoof, J., Rutten, P.G.S., Struck, C., Huisman, E.R.C.M., Kort, H.S.M. (2014) The integrated and evidence-based design of healthcare environments. Architectural Engineering and Design Management doi:10.1080/17452007.2014.892471

  3. Designing Prediction Tasks in a Mathematics Software Environment

    Science.gov (United States)

    Brunström, Mats; Fahlgren, Maria

    2015-01-01

    There is a recognised need in mathematics teaching for new kinds of tasks which exploit the affordances provided by new technology. This paper focuses on the design of prediction tasks to foster student reasoning about exponential functions in a mathematics software environment. It draws on the first iteration of a design based research study…

  4. Synthetic Environments as visualization method for product design

    NARCIS (Netherlands)

    Meijer, Frank; Broek, van den Egon L.; Schouten, Theo E.; Damgrave, Roy G.J.; Ridder, de Huib; Rogowitz, Bernice E.; Pappas, Thrasyvoulos N.

    2010-01-01

    In this paper, we explored the use of low fidelity Synthetic Environments (SE; i.e., a combination of simulation techniques) for product design. We explored the usefulness of low fidelity SE to make design problems explicit. In particular, we were interested in the influence of interactivity on user

  5. Synthetic environments as visualization method for product design

    NARCIS (Netherlands)

    Meijer, F.; Van den Broek, E.L.; Schouten, T.E.; Damgrave, R.G.J.; De Ridder, H.

    2010-01-01

    In this paper, we explored the use of low fidelity Synthetic Environments (SE; i.e., a combination of simulation techniques) for product design. We explored the usefulness of low fidelity SE to make design problems explicit. In particular, we were interested in the influence of interactivity on user

  6. Designing Learning Environments to Teach Interactive Quantum Physics

    Science.gov (United States)

    Puente, Sonia M. Gomez; Swagten, Henk J. M.

    2012-01-01

    This study aims at describing and analysing systematically an interactive learning environment designed to teach Quantum Physics, a second-year physics course. The instructional design of Quantum Physics is a combination of interactive lectures (using audience response systems), tutorials and self-study in unit blocks, carried out with small…

  7. Designing Learning Environments to Teach Interactive Quantum Physics

    Science.gov (United States)

    Puente, Sonia M. Gomez; Swagten, Henk J. M.

    2012-01-01

    This study aims at describing and analysing systematically an interactive learning environment designed to teach Quantum Physics, a second-year physics course. The instructional design of Quantum Physics is a combination of interactive lectures (using audience response systems), tutorials and self-study in unit blocks, carried out with small…

  8. Ethics of Living Technology: Design Principles for Proactive Home Environments

    Directory of Open Access Journals (Sweden)

    Frans Mäyrä

    2004-07-01

    Full Text Available The entry of proactive technology into highly sensitive environments, such as the home, produces specific design challenges that are inextricably linked to ethical issues. Two design goals are presented and analysed: proactive solutions have to be both personalized and consistent. These requirements are partially contradictory, and need to be understood in the context of the socio-cognitive setting of the home. The embedding of proactive technology into a home environment has to provide the user with an awareness of the possibilities of control and play. These design goals are further developed with regard to different user cultures: here we concentrate on early adopters and elderly people.

  9. Fictional space in participatory design of engaging interactive environments

    DEFF Research Database (Denmark)

    Dindler, Christian

    2010-01-01

    This dissertation addresses the topic of designing engaging interactive environments and is positioned in the intersection between participatory design, design theory, and interaction design. This topic has been addressed through a research program on designing engaging interactive exhibition...... perspective on how people as resourceful individuals and groups invest their time, skill, and knowledge in interactive environments. Within this overarching perspective, the notion of means of engagement is presented denoting the intentional constructs that mediate engagement. The notion stretches beyond...... individual technologies and interfaces to encompass the multitude of interconnected aspects that are arranged through design and that, in concert, mediate engagement. Through a discussion of the issue of motivation it is argued that museums might spur visitors engagement by mediating between the everyday...

  10. Computer-aided design development transition for IPAD environment

    Science.gov (United States)

    Owens, H. G.; Mock, W. D.; Mitchell, J. C.

    1980-01-01

    The relationship of federally sponsored computer-aided design/computer-aided manufacturing (CAD/CAM) programs to the aircraft life cycle design process, an overview of NAAD'S CAD development program, an evaluation of the CAD design process, a discussion of the current computing environment within which NAAD is developing its CAD system, some of the advantages/disadvantages of the NAAD-IPAD approach, and CAD developments during transition into the IPAD system are discussed.

  11. Research and Application of Integration Design Environment Faced to CSCD

    Institute of Scientific and Technical Information of China (English)

    ZHAO Han; LI Yanfeng; DONG Yude

    2006-01-01

    Computer supported collaborative design(CSCD) technology has been applied extensively with intensive market competition. The key technologies and problems of CSCD are analyzed and a CSCD design frame faced to product design is established. Then a CSCD system faced to radar key components is founded with Pro/INTRALINK software and re-exploiting technology. Some key processes are also designed, such as database management, workflow programming, information communication, file release, conflict identification and safety management. These will provide a reference for constructing a cooperative design environment.

  12. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  13. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  14. Design research and the globalization of healthcare environments.

    Science.gov (United States)

    Shepley, Mardelle McCuskey; Song, Yilin

    2014-01-01

    Global healthcare practice has expanded in the past 20 years. At the same time the incorporation of research into the design process has gained prominence as a best practice among architects. The authors of this study investigated the status of design research in a variety of international settings. We intended to answer the question, "how pervasive is healthcare design research outside of the United States?" The authors reviewed the international literature on the design of healthcare facilities. More than 500 international studies and conference proceedings were incorporated in this literature review. A team of five research assistants searched multiple databases comparing approximately 16 keywords to geographic location. Some of those keywords included: evidence-based design, salutogenic design, design research, and healthcare environment. Additional articles were gathered by contacting prominent researchers and asking for their personal assessment of local health design research studies. While there are design researchers in most parts of the world, the majority of studies focus on the needs of populations in developed countries and generate guidelines that have significant cost and cultural implications that prohibit their implementation in developing countries. Additionally, the body of literature discussing the role of culture in healthcare environments is extremely limited. Design researchers must address the cultural implications of their studies. Additionally, we need to expand our research objectives to address healthcare design in countries that have not been previous considered. © 2014 Vendome Group, LLC.

  15. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  16. DTDWS-DESIGN OF TESTBED FOR DISTRIBUTED WEB SERVICE ENVIRONMENT

    Directory of Open Access Journals (Sweden)

    D.CHANDRAMOHAN,

    2011-03-01

    Full Text Available Designing and developing a testbed to evaluate the features of web service properties and their service interfaces in a distributed web service environment. This testbed interface helps the clients and their tools to build automatically with the corresponding web services and to identify its related issues in which it can communicate and cooperate among services in a distributed environment. By establishing set of policy and preferences for relevant supporting tools to evaluate the semantic technology of service and enhancing the tuning features by avoiding interoperability among web services. A light weighted application having unique and specific structure for designing testbed for istributed web service environment (DTDWS with a build in concepts encoded with XML (Extensible Mark-up Language. This proposal breed a trustful zone in a distributed environment by an automated simulation,composition and testing techniques are put into service. Many service conflicts are resolved in a timely and consistent approach all the way through our proposed testbed .

  17. Paradigms for the design of multimedia learning environments in engineering

    OpenAIRE

    Smith, Chrisopher Robert

    1996-01-01

    The starting point for this research was the belief that interactive multimedia learning environments represent a significant evolution in computer based learning and therefore their design requires a re-examination of the underlying principles of learning and knowledge representation. Current multimedia learning environments (MLEs) can be seen as descendants of the earlier technologies of computer-aided learning (CAL), intelligent tutoring systems (ITS) and videodisc-based ...

  18. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  19. Design of Feedback in Interactive Multimedia Language Learning Environments

    Directory of Open Access Journals (Sweden)

    Vehbi Türel

    2012-01-01

    Full Text Available In interactive multimedia environments, different digital elements (i. e. video, audio, visuals, text, animations, graphics and glossary can be combined and delivered on the same digital computer screen (TDM 1997: 151, CCED 1987, Brett 1998: 81, Stenton 1998: 11, Mangiafico 1996: 46. This also enables effectively provision and presentation of feedback in pedagogically more efficient ways, which meets not only the requirement of different teaching and learning theories, but also the needs of language learners who vary in their learning-style preferences (Robinson 1991: 156, Peter 1994: 157f.. This study aims to bring out the pedagogical and design principles that might help us to more effectively design and customise feedback in interactive multimedia language learning environments. While so doing, some examples of thought out and customized computerised feedback from an interactive multimedia language learning environment, which were designed and created by the author of this study and were also used for language learning purposes, will be shown.

  20. Formation of Training Environment by Means of Didactic Design

    Directory of Open Access Journals (Sweden)

    Elena Vaktina

    2013-01-01

    Full Text Available Recent studies have argued the necessity of revealing pedagogical conditions in the university educational process for formation of the future engineers’ readiness to productive and innovative activity. Training environment creates the system of pedagogical conditions and effects on the development of student qualities. We offers the didactic design as a technology for formation and development process management for future engineers by creation of training environment of the given quality. This technology has the spiral phase organization: modeling, designing, constructing and operation. The application of the didactic design on the example of the educational resource for programming microcontroller is considered. The submitted technology develops modern engineering educational practice in the field of creation of the developing training environment.

  1. Seal designing of theodolite used in seaside environment

    Science.gov (United States)

    Jin, Humin; Yan, Xiaoxu; Hao, Wei; Zhou, Sizhong

    2014-08-01

    Based on the environment requirements in seaside there exists static and dynamic seal designing for the photoelectric Theodolite. Static seal designing emphatically includes the designing of o-ring size and mechanical property analysis of o-ring seal, which is difficult to adopt conventional dynamic seal to meet the requirements. According to practical application, the combination of the radial labyrinth seal and high quality felt seal are designed. The combination seal which better solves the seal problem of narrow radial size is a good way of dynamic seal. At the same time, there is engineering practice needing to proof the radial labyrinth seal.

  2. Influence of Natural Environments in Spacecraft Design, Development, and Operation

    Science.gov (United States)

    Edwards, Dave

    2013-01-01

    Spacecraft are growing in complexity and sensitivity to environmental effects. The spacecraft engineer must understand and take these effects into account in building reliable, survivable, and affordable spacecraft. Too much protections, however, means unnecessary expense while too little will potentially lead to early mission loss. The ability to balance cost and risk necessitates an understanding of how the environment impacts the spacecraft and is a critical factor in its design. This presentation is intended to address both the space environment and its effects with the intent of introducing the influence of the environment on spacecraft performance.

  3. Trajectory Design for the Phobos and Deimos & Mars Environment Spacecraft

    Science.gov (United States)

    Genova, Anthony L.; Korsmeyer, David J.; Loucks, Michel E.; Yang, Fan Yang; Lee, Pascal

    2016-01-01

    The presented trajectory design and analysis was performed for the Phobos and Deimos & Mars Environment (PADME) mission concept as part of a NASA proposal submission managed by NASA Ames Research Center in the 2014-2015 timeframe. The PADME spacecraft would be a derivative of the successfully flown Lunar Atmosphere & Dust Environment Explorer (LADEE) spacecraft. While LADEE was designed to enter low-lunar orbit, the PADME spacecraft would instead enter an elliptical Mars orbit of 2-week period. This Mars orbit would pass by Phobos near periapsis on successive orbits and then raise periapsis to yield close approaches of Deimos every orbit thereafter.

  4. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  5. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  6. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  7. Living closer to the environment: Housing design concept

    Directory of Open Access Journals (Sweden)

    Kosorić Vesna

    2011-01-01

    Full Text Available The main idea of this design concept is to strengthen the relationship and understanding between a man - resident and his environment. Residents are separated from the outdoor environment by glazing, which enables constant observation of environment from nearly all points of indoor space, encouraging positive feelings towards external world and understanding of the fragility of biosphere. Care for the environment should become a part of a man's nature and way of living, and it is the people who are expected to become the driving force of positive global changes towards sustainable development. The semisphere-like single family house of 14m in diameter has a multifunctional, multi-layer 'active' facade envelope. The envelope ensures constant visual contact of residents with the whole surroundings, while still providing comfort. The living space of the house reflects natural shapes which are organic rather than rectangular. Such indoor space becomes a part of the environment, rather than being protected, distanced and isolated from it. The house is designed to use solar energy 'passively' by absorption through insulated glazed envelope and 'actively' by outer skin layer on the first floor, made of stripes of flat semi-transparent polycrystalline photovoltaic (PV panels. In addition to its constructive role, the concrete core of the house acts as thermal mass and enables absorption and accumulation of thermal energy. The developed housing concept is applicable in different urban-design units and sets.

  8. Design and analysis issues in gene and environment studies

    Directory of Open Access Journals (Sweden)

    Liu Chen-yu

    2012-12-01

    Full Text Available Abstract Both nurture (environmental and nature (genetic factors play an important role in human disease etiology. Traditionally, these effects have been thought of as independent. This perspective is ill informed for non-mendelian complex disorders which result as an interaction between genetics and environment. To understand health and disease we must study how nature and nurture interact. Recent advances in human genomics and high-throughput biotechnology make it possible to study large numbers of genetic markers and gene products simultaneously to explore their interactions with environment. The purpose of this review is to discuss design and analytic issues for gene-environment interaction studies in the “-omics” era, with a focus on environmental and genetic epidemiological studies. We present an expanded environmental genomic disease paradigm. We discuss several study design issues for gene-environmental interaction studies, including confounding and selection bias, measurement of exposures and genotypes. We discuss statistical issues in studying gene-environment interactions in different study designs, such as choices of statistical models, assumptions regarding biological factors, and power and sample size considerations, especially in genome-wide gene-environment studies. Future research directions are also discussed.

  9. Mental and behavioral health environments: critical considerations for facility design.

    Science.gov (United States)

    Shepley, Mardelle McCuskey; Watson, Angela; Pitts, Francis; Garrity, Anne; Spelman, Elizabeth; Kelkar, Janhawi; Fronsman, Andrea

    2016-01-01

    The purpose of the study was to identify features in the physical environment that are believed to positively impact staff and patients in psychiatric environments and use these features as the foundation for future research regarding the design of mental and behavioral health facilities. Pursuant to a broad literature review that produced an interview script, researchers conducted 19 interviews of psychiatric staff, facility administrators and architects. Interview data were analyzed using the highly structured qualitative data analysis process authored by Lincoln and Guba (1985). Seventeen topics were addressed ranging from the importance of a deinstitutionalized environment to social interaction and autonomy. The interviewees reinforced the controversy that exists around the implications of a deinstitutionalized environment, when the resulting setting diminishes patient and staff safety. Respondents tended to support open nurse stations vs. enclosed stations. Support for access to nature and the provision of an aesthetic environment was strong. Most interviewees asserted that private rooms were highly desirable because lower room density reduces the institutional character of a unit. However, a few interviewees adamantly opposed private rooms because they considered the increased supervision of one patient by another to be a deterrent to self-harm. The need to address smoking rooms in future research received the least support of all topics. Responses of interviews illustrate current opinion regarding best practice in the design of psychiatric facilities. The findings emphasize the need for more substantive research on appropriate physical environments in mental and behavioral health settings. Copyright © 2016 Elsevier Inc. All rights reserved.

  10. Liner Shipping Hub Network Design in a Competitive Environment

    DEFF Research Database (Denmark)

    Gelareh, Shahin; Nickel, Stefan; Pisinger, David

    A new mixed integer programming formulation is proposed for hub-and-spoke network design in a competitive environment. It addresses competition between a newcomer liner service provider and an alliance, both operating on hub-and-spoke networks. The newcomer company maximizes its market share...

  11. Liner shipping hub network design in a competitive environment

    DEFF Research Database (Denmark)

    Gelareh, Shahin; Nickel, Stefan; Pisinger, David

    2010-01-01

    A mixed integer programming formulation is proposed for hub-and-spoke network design in a competitive environment. It addresses the competition between a newcomer liner service provider and an existing dominating operator, both operating on hub-and-spoke networks. The newcomer company maximizes its...

  12. Knowledge management in an integrated design and engineering environment

    NARCIS (Netherlands)

    Reefman, R.J.B.; Van Nederveen, G.A.

    2012-01-01

    Organisations and / or disciplines in Building and Construction projects are usually working in their own design and engineering environments and using their own Building Information Models (BIM). The discipline models are merged into a project BIM which is mainly used to check for interferences or

  13. Ethics, Design and Planning of the Built Environment

    NARCIS (Netherlands)

    Basta, C.; Moroni, S.

    2013-01-01

    The book proposes a set of original contributions in research areas shared by planning theory, architectural research, design and ethical inquiry. The contributors gathered in 2010 at the Ethics of the Built Environment seminar organized by the editors at Delft University of Technology. Both promine

  14. Designing for Real-World Scientific Inquiry in Virtual Environments

    Science.gov (United States)

    Ketelhut, Diane Jass; Nelson, Brian C.

    2010-01-01

    Background: Most policy doctrines promote the use of scientific inquiry in the K-12 classroom, but good inquiry is hard to implement, particularly for schools with fiscal and safety constraints and for teachers struggling with understanding how to do so. Purpose: In this paper, we present the design of a multi-user virtual environment (MUVE)…

  15. Designing a Virtual-Reality-Based, Gamelike Math Learning Environment

    Science.gov (United States)

    Xu, Xinhao; Ke, Fengfeng

    2016-01-01

    This exploratory study examined the design issues related to a virtual-reality-based, gamelike learning environment (VRGLE) developed via OpenSimulator, an open-source virtual reality server. The researchers collected qualitative data to examine the VRGLE's usability, playability, and content integration for math learning. They found it important…

  16. Liner shipping hub network design in a competitive environment

    DEFF Research Database (Denmark)

    Gelareh, Shahin; Nickel, Stefan; Pisinger, David

    2010-01-01

    A mixed integer programming formulation is proposed for hub-and-spoke network design in a competitive environment. It addresses the competition between a newcomer liner service provider and an existing dominating operator, both operating on hub-and-spoke networks. The newcomer company maximizes i...

  17. Designing for Learning: Online Social Networks as a Classroom Environment

    Science.gov (United States)

    Casey, Gail; Evans, Terry

    2011-01-01

    This paper deploys notions of emergence, connections, and designs for learning to conceptualize high school students' interactions when using online social media as a learning environment. It makes links to chaos and complexity theories and to fractal patterns as it reports on a part of the first author's action research study, conducted while she…

  18. Virtual Worlds; Real Learning: Design Principles for Engaging Immersive Environments

    Science.gov (United States)

    Wu (u. Sjarpm)

    2012-01-01

    The EMDT master's program at Full Sail University embarked on a small project to use a virtual environment to teach graduate students. The property used for this project has evolved our several iterations and has yielded some basic design principles and pedagogy for virtual spaces. As a result, students are emerging from the program with a better grasp of future possibilities.

  19. Making microbiology of the built environment relevant to design.

    Science.gov (United States)

    Brown, G Z; Kline, Jeff; Mhuireach, Gwynne; Northcutt, Dale; Stenson, Jason

    2016-02-16

    Architects are enthusiastic about "bioinformed design" as occupant well-being is a primary measure of architectural success. However, architects are also under mounting pressure to create more sustainable buildings. Scientists have a critical opportunity to make the emerging field of microbiology of the built environment more relevant and applicable to real-world design problems by addressing health and sustainability in tandem. Practice-based research, which complements evidence-based design, represents a promising approach to advancing knowledge of the indoor microbiome and translating it to architectural practice.

  20. ELISA, a demonstrator environment for information systems architecture design

    Science.gov (United States)

    Panem, Chantal

    1994-01-01

    This paper describes an approach of reusability of software engineering technology in the area of ground space system design. System engineers have lots of needs similar to software developers: sharing of a common data base, capitalization of knowledge, definition of a common design process, communication between different technical domains. Moreover system designers need to simulate dynamically their system as early as possible. Software development environments, methods and tools now become operational and widely used. Their architecture is based on a unique object base, a set of common management services and they host a family of tools for each life cycle activity. In late '92, CNES decided to develop a demonstrative software environment supporting some system activities. The design of ground space data processing systems was chosen as the application domain. ELISA (Integrated Software Environment for Architectures Specification) was specified as a 'demonstrator', i.e. a sufficient basis for demonstrations, evaluation and future operational enhancements. A process with three phases was implemented: system requirements definition, design of system architectures models, and selection of physical architectures. Each phase is composed of several activities that can be performed in parallel, with the provision of Commercial Off the Shelves Tools. ELISA has been delivered to CNES in January 94, currently used for demonstrations and evaluations on real projects (e.g. SPOT4 Satellite Control Center). It is on the way of new evolutions.

  1. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  2. DESIGN COORDINATION IN DISTRIBUTED ENVIRONMENTS USING VIRTUAL REALITY SYSTEMS

    Directory of Open Access Journals (Sweden)

    Rusdi HA

    2003-01-01

    Full Text Available This paper presents a research project, which investigates the use of virtual reality and computer communication technology to facilitate building design coordination in distributed environments. The emphasis of the system, called VR-based DEsign COordination (VRDECO is providing a communication tool that can be used by remote designers for settling ideas before they fully engage in concurrent engineering environments. VRDECO provides the necessary design tools, library of building elements and communication procedures, for designers from remote places to perform and coordinate their initial tasks. It has been implemented using available commercial software packages, and is used in designing a simple house. VRDECO facilitates the creation a preliminary design and simple communication with the client. There are, however, some difficulties in the development of the full version of VRDECO, i.e.: creating an adequate number of building elements, building specification database with a sufficient number of choices, and establishing a systematic rule to determine the parts of a building that are updateable.

  3. Designing Equipment for Use in Gamma Radiation Environments

    Energy Technology Data Exchange (ETDEWEB)

    Vandergriff, K.U.

    1990-01-01

    High levels of gamma radiation are known to cause degradation in a variety of materials and components. When designing systems to operate in a high radiation environment, special precautions and procedures should be followed. This report (1) outlines steps that should be followed in designing equipment and (2) explains the general effects of radiation on various engineering materials and components. Much information exists in the literature on radiation effects upon materials. However, very little information is available to give the designer a step-by-step process for designing systems that will be subject to high levels of gamma radiation, such as those found in a nuclear fuel reprocessing facility. In this report, many radiation effect references are relied upon to aid in the design of components and systems.

  4. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  5. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  6. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  7. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  8. The role of environment design in an educational Multi-User Virtual Environment

    DEFF Research Database (Denmark)

    Papachristos, Nikiforos; Vrellis, Ioannis; Natsis, Antonios

    2014-01-01

    This paper presents empirical results from an exploratory study conducted in an authentic educational situation with preservice education students enrolled in an undergraduate course, which was partially taught in Second Life. The study investigated the effect of environment design on presence, l...... necessary for all students to become familiar with the virtual environment and possible time losses due to technical issues. This study could act as support to construct and test hypotheses regarding the role of educational setting design in teaching and learning in MUVEs......., learning outcomes and the overall experience of the students. Two different educational virtual environments (a traditional university auditorium and an open-air setting) were designed and presented to different groups of students (n = 51). Results indicate that students' experience from the educational...... activities, their attitudes toward the environment and the induced sense of presence are not affected by the design of the educational setting. Learning outcomes seem to be slightly better in virtual educational settings that replicate traditional educational settings. Experience shows that undergraduate...

  9. Intelligent Agents for Design and Synthesis Environments: My Summary

    Science.gov (United States)

    Norvig, Peter

    1999-01-01

    This presentation gives a summary of intelligent agents for design synthesis environments. We'll start with the conclusions, and work backwards to justify them. First, an important assumption is that agents (whatever they are) are good for software engineering. This is especially true for software that operates in an uncertain, changing environment. The "real world" of physical artifacts is like that: uncertain in what we can measure, changing in that things are always breaking down, and we must interact with non-software entities. The second point is that software engineering techniques can contribute to good design. There may have been a time when we wanted to build simple artifacts containing little or no software. But modern aircraft and spacecraft are complex, and rely on a great deal of software. So better software engineering leads to better designed artifacts, especially when we are designing a series of related artifacts and can amortize the costs of software development. The third point is that agents are especially useful for design tasks, above and beyond their general usefulness for software engineering, and the usefulness of software engineering to design.

  10. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  11. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  12. The Virtual Environment for Reactor Applications (VERA). Design and architecture☆

    Science.gov (United States)

    Turner, John A.; Clarno, Kevin; Sieger, Matt; Bartlett, Roscoe; Collins, Benjamin; Pawlowski, Roger; Schmidt, Rodney; Summers, Randall

    2016-12-01

    VERA, the Virtual Environment for Reactor Applications, is the system of physics capabilities being developed and deployed by the Consortium for Advanced Simulation of Light Water Reactors (CASL). CASL was established for the modeling and simulation of commercial nuclear reactors. VERA consists of integrating and interfacing software together with a suite of physics components adapted and/or refactored to simulate relevant physical phenomena in a coupled manner. VERA also includes the software development environment and computational infrastructure needed for these components to be effectively used. We describe the architecture of VERA from both software and numerical perspectives, along with the goals and constraints that drove major design decisions, and their implications. We explain why VERA is an environment rather than a framework or toolkit, why these distinctions are relevant (particularly for coupled physics applications), and provide an overview of results that demonstrate the use of VERA tools for a variety of challenging applications within the nuclear industry.

  13. The Virtual Environment for Reactor Applications (VERA): Design and architecture

    Energy Technology Data Exchange (ETDEWEB)

    Turner, John A., E-mail: turnerja@ornl.gov [Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Clarno, Kevin; Sieger, Matt; Bartlett, Roscoe; Collins, Benjamin [Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Pawlowski, Roger; Schmidt, Rodney; Summers, Randall [Sandia National Laboratories, Albuquerque, NM 87185 (United States)

    2016-12-01

    VERA, the Virtual Environment for Reactor Applications, is the system of physics capabilities being developed and deployed by the Consortium for Advanced Simulation of Light Water Reactors (CASL). CASL was established for the modeling and simulation of commercial nuclear reactors. VERA consists of integrating and interfacing software together with a suite of physics components adapted and/or refactored to simulate relevant physical phenomena in a coupled manner. VERA also includes the software development environment and computational infrastructure needed for these components to be effectively used. We describe the architecture of VERA from both software and numerical perspectives, along with the goals and constraints that drove major design decisions, and their implications. We explain why VERA is an environment rather than a framework or toolkit, why these distinctions are relevant (particularly for coupled physics applications), and provide an overview of results that demonstrate the use of VERA tools for a variety of challenging applications within the nuclear industry.

  14. Agent-Based Design for E-learning Environment

    Directory of Open Access Journals (Sweden)

    Khadidja Harbouche

    2007-01-01

    Full Text Available We presented an agent-based e-learning environment. Our aim was to allow many users to interact collectively and intelligently with the environment. In this cooperation model, human users and artificial agents carry out tasks in the learners’ service. We define the internal structure of our kernel supposed to work within Internet/Intranet settings. Design was structured in three parts: individual learning space, collaborative space, and cooperative space. We advocate the employment of an agent-based approach, a suitable for two main reasons: agents were a natural metaphor of human acts, and the learning systems are generally complex. Prometheus methodology used for the design and emphasis placed on the agent-based features.

  15. Usability Issues of an Augmented Virtuality Environment for Design

    Science.gov (United States)

    Wang, Xiangyu; Chen, Irene Rui

    This paper presents a usability evaluation of an Augmented Virtuality (AV)-based system dedicated for design. The philosophy behind the concept of the system is discussed based on the dimensions of transportation and artificiality in shared-space technologies. This system is introduced as a method that allows users to experience the real remote environment without the need of physically visiting the actual place. Such experience is realized by using AV technology to enrich the virtual counterparts of the place with captured real images from the real environment. The combination of the physicality reality and virtual reality provides key landmarks or features of the to-be-visited place, live video streams of the remote participants, and 3D virtual design geometry. The focus of this paper describes the implementation and a usability evaluation of the system in its current state and also discusses the limitations, issues and challenges of this AV system.

  16. Healing gardens: design processes and realizations of beneficial environments

    Directory of Open Access Journals (Sweden)

    Clare Cooper Marcus

    2015-04-01

    Full Text Available Having defined the topic and its related management effects in the healthcare environment, this paper reports considerations of specific design processes, including evidence-based design, Integrated Healthcare Strategies, participatory practices and post occupancy evaluation. Landscape of Italian examples follows before a case study of three Californian healing gardens dedicated to cancer patients, linked to a survey of this category of users’ needs in such spaces. Conclusions report the reflection of practical implications deriving from studying North American examples, underlining the opportunity for audit and certification of therapeutic gardens, as well as the chance to export them outside health infrastructures for social needs.

  17. Ergonomics, gerontechnology, and design for the home-environment.

    Science.gov (United States)

    Pinto, M R; De Medici, S; Van Sant, C; Bianchi, A; Zlotnicki, A; Napoli, C

    2000-06-01

    An ergonomic approach could improve the quality of life and activities in daily living. Gerontechnology reduces the effects of age-related impairments with technological devices and particular design for the home-environment. Physiological decline with increasing age renders the daily activities at home more difficult. This paper highlights some "common sense" and specific design suggestions in the entrance and kitchen, aimed to increase the self-sufficiency of elderly people. We suggest that gerontechnology may have a particular role in the improvement of comfort and safety for aged people.

  18. Requirements of Integrated Design Teams While Evaluating Advanced Energy Retrofit Design Options in Immersive Virtual Environments

    Directory of Open Access Journals (Sweden)

    Xue Yang

    2015-12-01

    Full Text Available One of the significant ways to save energy use in buildings is to implement advanced energy retrofits in existing buildings. Improving energy performance of buildings through advanced energy retrofitting requires a clear understanding of the cost and energy implications of design alternatives from various engineering disciplines when different retrofit options are considered. The communication of retrofit design alternatives and their energy implications is essential in the decision-making process, as it affects the final retrofit selections and hence the energy efficiency of the retrofitted buildings. The objective of the research presented here was to identify a generic list of information requirements that are needed to be shared and collectively analyzed by integrated design teams during advanced energy retrofit design review meetings held in immersive settings. While identifying such requirements, the authors used an immersive environment based iterative requirements elicitation approach. The technology was used as a means to better identify the information requirements of integrated design teams to be analyzed as a group. This paper provides findings on information requirements of integrated design teams when evaluating retrofit options in immersive virtual environments. The information requirements were identified through interactions with sixteen experts in design and energy modeling domain, and validated with another group of participants consisting of six design experts who were experienced in integrated design processes. Industry practitioners can use the findings in deciding on what information to share with integrated design team members during design review meetings that utilize immersive virtual environments.

  19. GLobal Integrated Design Environment (GLIDE): A Concurrent Engineering Application

    Science.gov (United States)

    McGuire, Melissa L.; Kunkel, Matthew R.; Smith, David A.

    2010-01-01

    The GLobal Integrated Design Environment (GLIDE) is a client-server software application purpose-built to mitigate issues associated with real time data sharing in concurrent engineering environments and to facilitate discipline-to-discipline interaction between multiple engineers and researchers. GLIDE is implemented in multiple programming languages utilizing standardized web protocols to enable secure parameter data sharing between engineers and researchers across the Internet in closed and/or widely distributed working environments. A well defined, HyperText Transfer Protocol (HTTP) based Application Programming Interface (API) to the GLIDE client/server environment enables users to interact with GLIDE, and each other, within common and familiar tools. One such common tool, Microsoft Excel (Microsoft Corporation), paired with its add-in API for GLIDE, is discussed in this paper. The top-level examples given demonstrate how this interface improves the efficiency of the design process of a concurrent engineering study while reducing potential errors associated with manually sharing information between study participants.

  20. Blended Learning Environments and Suggesstions for Blended Learning Design

    Directory of Open Access Journals (Sweden)

    Funda DAĞ

    2011-06-01

    Full Text Available The number of studies in blended learning field, which has gained importance by being reinterpreted with the effect of the developments in information and communication technologies, has been increasing recently. There have been many diverse approaches in these studies on the point of defining blended learning and on the point of which components of blended learning environments need blending and how they are blended. The aim of this study is to examine national and international studies in blended learning in higher education and to make suggestions about necessary components for designing an effective blended learning environment. Within this framework the studies on blended learning, which were accessible online, were examined from the perspectives of research methods that were used, preferred e-learning environments and/or e-learning methods, preferred face to face learning/teaching strategies and the methods used in the evaluation of blended learning. In the light of the findings it is seen that blended learning should be regarded as a teaching design approach in order to create effectively blended learning environments and it is hoped that the suggestions made will be lodestar in forming blended learning models for diverse learning fields.

  1. Semantic Middleware for Designing Collaborative Applications in Mobile Environment

    OpenAIRE

    Benmouffok, Lamia; Busca, Jean-Michel; Shapiro, Marc

    2007-01-01

    International audience; The Telex middleware facilitates the design of collaborative applications in a mobile environment. It provides optimistic replication, tentative execution and disconnected work. It solves conflicts based on semantic information provided by applications. We study in particular a Shared Calendar (SC) application, whereby mobile users can create and manage meetings in a collection of shared calendars. The application provides Telex with objects representing (1) meeting cr...

  2. Collaborative virtual reality environments for computational science and design.

    Energy Technology Data Exchange (ETDEWEB)

    Papka, M. E.

    1998-02-17

    The authors are developing a networked, multi-user, virtual-reality-based collaborative environment coupled to one or more petaFLOPs computers, enabling the interactive simulation of 10{sup 9} atom systems. The purpose of this work is to explore the requirements for this coupling. Through the design, development, and testing of such systems, they hope to gain knowledge that allows computational scientists to discover and analyze their results more quickly and in a more intuitive manner.

  3. Design of a Smart Unmanned Ground Vehicle for Hazardous Environments

    CERN Document Server

    Chakraborty, Saurav

    2010-01-01

    A smart Unmanned Ground Vehicle (UGV) is designed and developed for some application specific missions to operate predominantly in hazardous environments. In our work, we have developed a small and lightweight vehicle to operate in general cross-country terrains in or without daylight. The UGV can send visual feedbacks to the operator at a remote location. Onboard infrared sensors can detect the obstacles around the UGV and sends signals to the operator.

  4. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  5. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  6. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  7. Designing Collaborative Learning Environments Using Educational Scenarios Based on SR

    Directory of Open Access Journals (Sweden)

    Fotini Paraskeva

    2009-01-01

    Full Text Available As more and more studies acknowledge that students are basic contributors to the learning process, factors such as self concept, (computer self-efficacy and self-regulation are important in enhancing human performance. Nevertheless, these learner characteristics have received little attention in the e-learning environment. This paper presents the results of a study indicating significant positive relationships between learner characteristics, such as self-concept (academic achievement and job achievement, Computer Self Efficacy (CSE and Self-Regulation (SR constructs. Acknowledging the requirement for a strong shift of students towards developing self-regulated scenarios and strategies, we suggest that collaborative e-learning environments should be designed according to the self-regulated theory and self-beliefs. As a result, in this study we present a model examining how we can design educational scenarios based on self-regulation theory in a collaborative e-learning environment. This model is a tool for conducting experiments in e-learning university courses, studying the design, development and evaluation of the collaborative learning process.

  8. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  9. Healthy Toronto by Design: Promoting a healthier built environment.

    Science.gov (United States)

    Macfarlane, Ronald G; Wood, Linda P; Campbell, Monica E

    2014-07-08

    Chronic diseases, obesity and sedentary lifestyles are some of the health challenges facing Canada today. There is increasing recognition and evidence that the way our cities are planned, designed and built can contribute to these problems. Many of the policy levers to address the built environment exist outside the health sector and at the municipal level in areas such as urban planning, transportation, parks and recreation, and housing. The challenge for the public health sector is to build and sustain partnerships and collaboration across various sectors to ensure that health is considered in built environment policies. As the public health unit for the city of Toronto and part of the municipal government, Toronto Public Health is in a unique position to provide leadership, advocacy and support for healthy municipal public policies related to the built environment. This article provides some examples of CLASP (Coalitions Linking Action and Science for Prevention) initiatives undertaken to help create support for healthy public policies in the built environment and suggests that the "Healthy Cities" approach is a useful framework to promote policy change in the built environment at the municipal level.

  10. Designing discovery learning environments: process analysis and implications for designing an information system

    NARCIS (Netherlands)

    Pieters, Julius Marie; Limbach, R.; de Jong, Anthonius J.M.

    2004-01-01

    A systematic analysis of the design process of authors of (simulation based) discovery learning environments was carried out. The analysis aimed at identifying the design activities of authors and categorising knowledge gaps that they experience. First, five existing studies were systematically

  11. COVE: a visual environment for ocean observatory design

    Science.gov (United States)

    Grochow, K.; Stoermer, M.; Kelley, D.; Delaney, J.; Lazowska, E.

    2008-07-01

    Physical, chemical, and biological ocean processes play a crucial role in determining Earth's environment. Unfortunately, our knowledge of these processes is limited because oceanography is carried out today largely the way it was a century ago: as expeditionary science, going to sea in ships and measuring a relatively small number of parameters (e.g., temperature, salinity, and pressure) as time and budget allow. The NSF Ocean Observatories Initiative is a US330 million project that will help transform oceanography from a data-poor to a data-rich science. A cornerstone of this project is the deep water Regional Scale Nodes (RSN) that will be installed off the coasts of Washington and Oregon. The RSN will include 1500 km of fiber optic cable providing power and bandwidth to the seafloor and throughout the water column. Thousands of sensors will be deployed to stream data and imagery to shore, where they will be available in real time for ocean scientists and the public at large. The design of the RSN is a complex undertaking, requiring a combination of many different interactive tools and areas of visualization: geographic visualization to see the available seafloor bathymetry, scientific visualization to examine existing geospatially located datasets, layout tools to place the sensors, and collaborative tools to communicate across the team during the design. COVE, the Common Observatory Visualization Environment, is a visualization environment designed to meet all these needs. COVE has been built by computer scientists working closely with the engineering and scientific teams who will build and use the RSN. This paper discusses the data and activities of cabled observatory design, the design of COVE, and results from its use across the team.

  12. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  13. Thermal insulating concrete wall panel design for sustainable built environment.

    Science.gov (United States)

    Zhou, Ao; Wong, Kwun-Wah; Lau, Denvid

    2014-01-01

    Air-conditioning system plays a significant role in providing users a thermally comfortable indoor environment, which is a necessity in modern buildings. In order to save the vast energy consumed by air-conditioning system, the building envelopes in envelope-load dominated buildings should be well designed such that the unwanted heat gain and loss with environment can be minimized. In this paper, a new design of concrete wall panel that enhances thermal insulation of buildings by adding a gypsum layer inside concrete is presented. Experiments have been conducted for monitoring the temperature variation in both proposed sandwich wall panel and conventional concrete wall panel under a heat radiation source. For further understanding the thermal effect of such sandwich wall panel design from building scale, two three-story building models adopting different wall panel designs are constructed for evaluating the temperature distribution of entire buildings using finite element method. Both the experimental and simulation results have shown that the gypsum layer improves the thermal insulation performance by retarding the heat transfer across the building envelopes.

  14. Thermal Insulating Concrete Wall Panel Design for Sustainable Built Environment

    Directory of Open Access Journals (Sweden)

    Ao Zhou

    2014-01-01

    Full Text Available Air-conditioning system plays a significant role in providing users a thermally comfortable indoor environment, which is a necessity in modern buildings. In order to save the vast energy consumed by air-conditioning system, the building envelopes in envelope-load dominated buildings should be well designed such that the unwanted heat gain and loss with environment can be minimized. In this paper, a new design of concrete wall panel that enhances thermal insulation of buildings by adding a gypsum layer inside concrete is presented. Experiments have been conducted for monitoring the temperature variation in both proposed sandwich wall panel and conventional concrete wall panel under a heat radiation source. For further understanding the thermal effect of such sandwich wall panel design from building scale, two three-story building models adopting different wall panel designs are constructed for evaluating the temperature distribution of entire buildings using finite element method. Both the experimental and simulation results have shown that the gypsum layer improves the thermal insulation performance by retarding the heat transfer across the building envelopes.

  15. User-centered virtual environment design for virtual rehabilitation

    Directory of Open Access Journals (Sweden)

    Rizzo Albert A

    2010-02-01

    Full Text Available Abstract Background As physical and cognitive rehabilitation protocols utilizing virtual environments transition from single applications to comprehensive rehabilitation programs there is a need for a new design cycle methodology. Current human-computer interaction designs focus on usability without benchmarking technology within a user-in-the-loop design cycle. The field of virtual rehabilitation is unique in that determining the efficacy of this genre of computer-aided therapies requires prior knowledge of technology issues that may confound patient outcome measures. Benchmarking the technology (e.g., displays or data gloves using healthy controls may provide a means of characterizing the "normal" performance range of the virtual rehabilitation system. This standard not only allows therapists to select appropriate technology for use with their patient populations, it also allows them to account for technology limitations when assessing treatment efficacy. Methods An overview of the proposed user-centered design cycle is given. Comparisons of two optical see-through head-worn displays provide an example of benchmarking techniques. Benchmarks were obtained using a novel vision test capable of measuring a user's stereoacuity while wearing different types of head-worn displays. Results from healthy participants who performed both virtual and real-world versions of the stereoacuity test are discussed with respect to virtual rehabilitation design. Results The user-centered design cycle argues for benchmarking to precede virtual environment construction, especially for therapeutic applications. Results from real-world testing illustrate the general limitations in stereoacuity attained when viewing content using a head-worn display. Further, the stereoacuity vision benchmark test highlights differences in user performance when utilizing a similar style of head-worn display. These results support the need for including benchmarks as a means of better

  16. The Design Space of Multi-Language Development Environments

    DEFF Research Database (Denmark)

    Pfeiffer, Rolf-Helge; Wasowski, Andrzej

    2014-01-01

    languages. By means of a literature survey, tool prototyping and experiments we study the design space of multi-language development environments (MLDEs)—tools that consider the cross-language relations as first artifacts. We ask: what is the state of the art in the MLDE space? What are the design choices...... and challenges faced by tool builders? To what extent MLDEs are desired by users, and for what support features? Our main conclusions are that (a) cross-language re- lations are ubiquitous and troublesome in multi-language systems, (b) users highly appreciated cross-language sup- port mechanisms of MLDEs and (c......, that implement two radically different choices in the design space....

  17. Interaction Design in the Built Environment: Designing for the 'Universal User'.

    Science.gov (United States)

    Dalton, Cathy

    2016-01-01

    Concepts of responsive architecture have to date largely involved response to environmental context, in order to mediate ambient environmental factors and modify internal conditions for the comfort of users, with energy efficiency and sustainability as the main impetus. 'Smart' buildings often address little other than technically functional issues, with any ideas of 'design' as a unifying factor being disregarded. At the same time, music and performance art have been in the vanguard of creating digital interaction that intimately involves the user in aesthetic outcomes, in the creation of what Umberto Eco describes as an 'Open Work'. Environments made responsive through embedment of computational technologies can similarly extend usability and user-centred design towards universality, through careful consideration of the relationship between person, context and activity, and of the continuous and ultimately transactional nature of human occupation of built environment. Truly 'smart' environments will learn from and through usage, and can be conceived and designed so as to maximise environmental 'fit' for a wider variety of users, including people described as being 'neurodiverse'. Where user response becomes a significant component in managing a smart environment, the transactional relationship between user and environment is made explicit, and can ultimately be used to drive interaction that favours ease-of-use and personalisation. Inclusion of affective computing in human interaction with built environment offers significant potential for extending the boundaries of Universal Design to include people with autism, people with intellectual disability, and users with acquired cognitive impairment, including that arising from dementia. The same users frequently have issues with sensory-perceptual sensitivity and processing. The resulting mismatch between their individual needs and abilities, and the environments they typically occupy, can give rise to states of

  18. Cold & Black Environment Design in Large Space Simulator

    Science.gov (United States)

    Min, Liu; Botao, Liu; Zijuan, Wang; Weiwei, Shan; Wenjing, Ding

    A space simulator provides a spacecraft with a specified environment during a thermal test of which a cold & black background is one of the important technical specifications. A shroud and nitrogen system used to simulate a cold & black environment with the effective space of 8500 mm × 9000 mm are studied in this article. In terms of the design of the shroud of the large space simulator, we should not only consider heat exchange and temperature uniformity, but also the feasibility of manufacture, transportation and installation. The cooling system adopts single-phase closed loop cycle. Based on the result of the test, it can be concluded that test data accord with the computational simulation result. The average temperature is 90 K and the temperature uniformity of the shroud meets the technical requirement.

  19. Cognitive theories and the design of e-learning environments.

    Science.gov (United States)

    Gillani, Bijan; O'Guinn, Christina

    2004-01-01

    Cognitive development refers to a mental process by which knowledge is acquired, stored, and retrieved to solve problems. Therefore, cognitive developmental theories attempt to explain cognitive activities that contribute to students' intellectual development and their capacity to learn and solve problems. Cognitive developmental research has had a great impact on the constructivism movement in education and educational technology. In order to appreciate how cognitive developmental theories have contributed to the design, process and development of constructive e-learning environments, we shall first present Piaget's cognitive theory and derive an inquiry training model from it that will support a constructivism approach to teaching and learning. Second, we will discuss an example developed by NASA that used the Web as an appropriate instructional delivery medium to apply Piaget's cognitive theory to create e-learning environments.

  20. Islam and the healthcare environment: designing patient rooms.

    Science.gov (United States)

    Kopec, D A K; Han, Li

    2008-01-01

    Islam and the Muslim population are often the source of much misunderstanding and media-influenced misconceptions. Muslim patients who enter the healthcare environment are often weak and likely to experience feelings of vulnerability. Because of the complex and interwoven nature of culture and religion in a person's identity, it is important to consider patient belief systems and values when designing a patient's immediate environment. Through an exploration of literature related to culture and diversity and the beliefs and value system of the Muslim population, the authors were able to identify flexible design initiatives that could accommodate an array of cultural and spiritual practices. Islam and the Muslim population were chosen as the points of reference for this study because of the strong influence of the religion on the culture, and because of the many nuances that differ from the dominant culture within the United States. From these points of reference, a hypothetical design was developed for a patient room that considers differing notions of privacy, alternatives for cultural and religious practices, and ways to include symbolic meaning derived from attributes such as color.

  1. Design for the environment - do we get the focus right?

    DEFF Research Database (Denmark)

    Hauschild, Michael Zwicky; Jeswiet, Jack; Alting, Leo

    2004-01-01

    is the function provided and what is the optimal way of providing it while making a business out of it? Which product should the company then produce? 2. Where are the “environmental hot spots” in the life cycle of this product? 3. Which DFE tool supports optimisation of the product by reducing these hot spots?......Sometimes, products resulting from design for environment (DFE) endeavours are sub-optimisations from an environmental perspective, because the tool determines the process and not vice versa. For a more systematic way of getting the focus right, a hierarchy of focusing is introduced: 1. What...

  2. Strategic implementation of design for environment at Embraer

    DEFF Research Database (Denmark)

    Pigosso, Daniela Cristina Antelmi; Grandi, Carlos M.; Rozenfeld, Henrique

    2013-01-01

    Design for Environment (or ecodesign) has become increasingly important in the aircraft industry. Embraer, one of the world’s leading aircraft manufacturers, is committed to improve the environmental performance of the developed aircrafts. The roadmap for the strategic implementation of Df......E at Embraer, developed based on the application of the Ecodesign Maturity Model (EcoM2), is presented and further discussed in this paper. The paper describes the main projects and activities carried out at the company so to develop robust processes for the development of products with a better environmental...

  3. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  4. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  5. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  6. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  7. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  8. Fluorine local environment: from screening to drug design.

    Science.gov (United States)

    Vulpetti, Anna; Dalvit, Claudio

    2012-08-01

    Fluorine is widely used in the lead optimization phase of drug discovery projects. More recently, fluorine NMR-based spectroscopy has emerged as a versatile, reliable and efficient tool for performing binding and biochemical assays. Different libraries of fluorinated compounds, designed by maximizing the chemical space around the fluorine atom, are screened for identifying binding fragments and for detecting putative fluorophilic hot spots on the desired macromolecular target. A statistical analysis of the fluorine NMR chemical shift, which is a marker of the fluorine local environment, and of the X-ray structures of fluorinated molecules has resulted in the development of the 'rule of shielding'. This method could become a useful tool for lead optimization and for designing novel chemical scaffolds that recognize distinct protein structural motifs. Copyright © 2012 Elsevier Ltd. All rights reserved.

  9. Design and Implementation of an Extensible Learner-Adaptive Environment

    Directory of Open Access Journals (Sweden)

    Kiyoshi Nakabayashi

    2010-09-01

    Full Text Available This paper describes the design and implementation of a flexible architecture that is capable of extending the functions of a learner-adaptive self-learning environment. A “courseware object”, which is a program module that is used to implement various educational functionalities, has been newly introduced to ensure both function extensibility as well as content reusability. A prototype system was designed and implemented to investigate the feasibility of the proposed architecture and to identify the core behavior and interaction schema of courseware objects. The results from this trial indicated that several learner-adaptive functionalities including the SCORM 2004 standard specifications will be able to be successfully implemented into the proposed architecture.

  10. Designing Run-Time Environments to Have Predefined Global Dynamics

    Directory of Open Access Journals (Sweden)

    Massimo Monti

    2013-06-01

    Full Text Available The stability and the predictability of a computer network algorithm's performance are as important as themain functional purpose of networking software. However, asserting or deriving such properties from thefinite state machine implementations of protocols is hard and, except for singular cases like TCP, is notdone today. In this paper, we propose to design and study run-time environments for networking protocolswhich inherently enforce desirable, predictable global dynamics. To this end we merge two complementarydesign approaches: (i A design-time and bottom up approach that enables us to engineer algorithms basedon an analyzable (reaction flow model. (ii A run-time and top-down approach based on an autonomousstack composition framework, which switches among implementation alternatives to find optimal operationconfigurations. We demonstrate the feasibility of our self-optimizing system in both simulations and real-world Internet setups.

  11. Design and Verification Guidelines for Vibroacoustic and Transient Environments

    Science.gov (United States)

    1986-01-01

    Design and verification guidelines for vibroacoustic and transient environments contain many basic methods that are common throughout the aerospace industry. However, there are some significant differences in methodology between NASA/MSFC and others - both government agencies and contractors. The purpose of this document is to provide the general guidelines used by the Component Analysis Branch, ED23, at MSFC, for the application of the vibroacoustic and transient technology to all launch vehicle and payload components and payload components and experiments managed by NASA/MSFC. This document is intended as a tool to be utilized by the MSFC program management and their contractors as a guide for the design and verification of flight hardware.

  12. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  13. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  14. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  15. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  16. Works on color design installed in an urban environment

    Science.gov (United States)

    Rizzo, Silvia

    2002-06-01

    This project is about color-design paintings with evident chromatic contents to be located in several parts of the city. This project aims to make a two-dimension work alive in the three-dimension urban environment thus provoking a global vision of color and at the same time establishing a relation between both dimensions of the surrounding environment. Each work, which consists of a big colorful canvas, invites people to accept color as an active and aesthetic element to be experimented also in those areas that are normally without color. The project of color has been created and diversified considering the differences among various parts of the city. It is a confluence- comparison relationship between color and architecture. This project is part of a wide-research on 're-education to color,' helping people to enjoy the positive vital message of color. Re-appropriation of color is therefore an element of cultural evolution for a more harmonious and sensitive relationship with the environment. Hence, it is the responsibility of scientists and aesthetic operators to investigate and communicate new suggestions in the exciting field of color. Aesthetic operators along with scientists may contribute to a richer exploration in the use of color under innovative circumstances, in order to stimulate sensitivity to colors.

  17. LISP as an Environment for Software Design: Powerful and Perspicuous

    Science.gov (United States)

    Blum, Robert L.; Walker, Michael G.

    1986-01-01

    The LISP language provides a useful set of features for prototyping knowledge-intensive, clinical applications software that is not found In most other programing environments. Medical computer programs that need large medical knowledge bases, such as programs for diagnosis, therapeutic consultation, education, simulation, and peer review, are hard to design, evolve continually, and often require major revisions. They necessitate an efficient and flexible program development environment. The LISP language and programming environments bullt around it are well suited for program prototyping. The lingua franca of artifical intelligence researchers, LISP facllitates bullding complex systems because it is simple yet powerful. Because of its simplicity, LISP programs can read, execute, modify and even compose other LISP programs at run time. Hence, it has been easy for system developers to create programming tools that greatly speed the program development process, and that may be easily extended by users. This has resulted in the creation of many useful graphical interfaces, editors, and debuggers, which facllitate the development of knowledge-intensive medical applications.

  18. Architectural Design and the Learning Environment: A Framework for School Design Research

    Science.gov (United States)

    Gislason, Neil

    2010-01-01

    This article develops a theoretical framework for studying how instructional space, teaching and learning are related in practice. It is argued that a school's physical design can contribute to the quality of the learning environment, but several non-architectural factors also determine how well a given facility serves as a setting for teaching…

  19. Designing and Improving a Blended Synchronous Learning Environment: An Educational Design Research

    Science.gov (United States)

    Wang, Qiyun; Lang Quek, Choon; Hu, Xiaoyong

    2017-01-01

    In this study, a blended synchronous learning environment (BSLE) was created to support a group of graduate students when they were taking a course. Instruction was delivered to both face-to-face (F2F) and online students simultaneously. The purpose of this paper is to present how this BSLE was gradually designed, implemented, and improved by…

  20. Architectural Design and the Learning Environment: A Framework for School Design Research

    Science.gov (United States)

    Gislason, Neil

    2010-01-01

    This article develops a theoretical framework for studying how instructional space, teaching and learning are related in practice. It is argued that a school's physical design can contribute to the quality of the learning environment, but several non-architectural factors also determine how well a given facility serves as a setting for teaching…

  1. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  2. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  3. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  4. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  5. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  6. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  7. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  8. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  9. Real-time motion detection using an analog VLSI zero-crossing chip

    Science.gov (United States)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  10. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  11. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  12. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  13. Virtual Environment Design for Low/Zero Visibility Tower Tools

    Science.gov (United States)

    Reisman, Ron; Farouk, Ahmed; Edwards, Thomas A. (Technical Monitor)

    1998-01-01

    This paper describes prototype software for three-dimensional display of aircraft movement based on realtime radar and other Air Traffic Control (ATC) information. This prototype can be used to develop operational tools for controllers in ATC Towers who cannot view aircraft in low or zero visibility (LZV) weather conditions. The controller could also use the software to arbitrarily reposition his virtual eyepoint to overcome physical obstructions or increase situation awareness. The LZV Tower tool prototype consists of server and client components. The server interfaces to operational ATC radar and communications systems, sending processed data to a client process written in java. This client process runs under Netscape Communicator to provide an interactive perspective display of aircraft in the airport environment. Prototype VRML airport models were derived from 3-D databases used in FAA-certified high fidelity flight-simulators. The web-based design offers potential efficiency increases and decreased costs in the development and deployment of operational LZV Tower tools.

  14. Ethics, design and planning of the built environment

    CERN Document Server

    Moroni, Stefano

    2013-01-01

    The book proposes a set of original contributions in research areas shared by planning theory, architectural research, design and ethical inquiry. The contributors gathered in 2010 at the Ethics of the Built Environment seminar organized by the editors at Delft University of Technology. Both prominent and emerging scholars presented their researches in the areas of aesthetics, technological risks, planning theory and architecture. The scope of the seminar was highlighting shared lines of ethical inquiry among the themes discussed, in order to identify perspectives of innovative interdisciplinary research. After the seminar all seminar participants have elaborated their proposed contributions. Some of the most prominent international authors in the field were subsequently invited to join in with this inquiry. Claudia Basta teaches "Network Infrastructures and Mobility" at Wageningen University. Between 2009 and 2011 she worked as Coordinator of the 3TU Centre of Excellence for Ethics and Technology of Delft Un...

  15. Design and Testing of Electronic Devices for Harsh Environments

    CERN Document Server

    Nico, Costantino

    This thesis reports an overview and the main results of the research activity carried out within the PhD programme in Information Engineering of the University of Pisa (2010-2012). The research activity has been focused on different fields, including Automotive and High Energy Physics experiments, according to a common denominator: the development of electroni c devices and systems operating in harsh environments. There are many applications that forc e the adoption of design methodologies and strategies focused on this type of envir onments: military, biom edical, automotive, industrial and space. The development of solutions fulfilling specific operational requirements, therefore represents an interesting field of research. The first research activity has been framed within the ATHENIS project, funded by the CORDIS Commission of the European Community, and aiming at the development of a System-on-Chip, a r egulator for alternators employed on vehicles, presenting both configurability an d t...

  16. The design of a study environment for acquiring academic and professional competence

    NARCIS (Netherlands)

    Kirschner, P.A.; Vilsteren, P. van

    1997-01-01

    Proposes a framework for the design of a learning environment which encourages the acquisition of academic and professional competence. Definition of knowledge, cognitive skill and competence; Acquisition of competence; Designing an environment for competence acquisition; Implementation of study env

  17. Designing for Learning: Online Social Networks as a Classroom Environment

    Directory of Open Access Journals (Sweden)

    Gail Casey

    2011-11-01

    Full Text Available This paper deploys notions of emergence, connections, and designs for learning to conceptualize high school students’ interactions when using online social media as a learning environment. It makes links to chaos and complexity theories and to fractal patterns as it reports on a part of the first author’s action research study, conducted while she was a teacher working in an Australian public high school and completing her PhD. The study investigates the use of a Ning online social network as a learning environment shared by seven classes, and it examines students’ reactions and online activity while using a range of social media and Web 2.0 tools.The authors use Graham Nuthall’s (2007 “lens on learning” to explore the social processes and culture of this shared online classroom. The paper uses his extensive body of research and analyses of classroom learning processes to conceptualize and analyze data throughout the action research cycle. It discusses the pedagogical implications that arise from the use of social media and, in so doing, challenges traditional models of teaching and learning.

  18. Exascale Co-design for Modeling Materials in Extreme Environments

    Energy Technology Data Exchange (ETDEWEB)

    Germann, Timothy C. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

    2014-07-08

    Computational materials science has provided great insight into the response of materials under extreme conditions that are difficult to probe experimentally. For example, shock-induced plasticity and phase transformation processes in single-crystal and nanocrystalline metals have been widely studied via large-scale molecular dynamics simulations, and many of these predictions are beginning to be tested at advanced 4th generation light sources such as the Advanced Photon Source (APS) and Linac Coherent Light Source (LCLS). I will describe our simulation predictions and their recent verification at LCLS, outstanding challenges in modeling the response of materials to extreme mechanical and radiation environments, and our efforts to tackle these as part of the multi-institutional, multi-disciplinary Exascale Co-design Center for Materials in Extreme Environments (ExMatEx). ExMatEx has initiated an early and deep collaboration between domain (computational materials) scientists, applied mathematicians, computer scientists, and hardware architects, in order to establish the relationships between algorithms, software stacks, and architectures needed to enable exascale-ready materials science application codes within the next decade. We anticipate that we will be able to exploit hierarchical, heterogeneous architectures to achieve more realistic large-scale simulations with adaptive physics refinement, and are using tractable application scale-bridging proxy application testbeds to assess new approaches and requirements. Such current scale-bridging strategies accumulate (or recompute) a distributed response database from fine-scale calculations, in a top-down rather than bottom-up multiscale approach.

  19. Designing for Change: Interoperability in a scaling and adapting environment

    Science.gov (United States)

    Yarmey, L.

    2015-12-01

    The Earth Science cyberinfrastructure landscape is constantly changing. Technologies advance and technical implementations are refined or replaced. Data types, volumes, packaging, and use cases evolve. Scientific requirements emerge and mature. Standards shift while systems scale and adapt. In this complex and dynamic environment, interoperability remains a critical component of successful cyberinfrastructure. Through the resource- and priority-driven iterations on systems, interfaces, and content, questions fundamental to stable and useful Earth Science cyberinfrastructure arise. For instance, how are sociotechnical changes planned, tracked, and communicated? How should operational stability balance against 'new and shiny'? How can ongoing maintenance and mitigation of technical debt be managed in an often short-term resource environment? The Arctic Data Explorer is a metadata brokering application developed to enable discovery of international, interdisciplinary Arctic data across distributed repositories. Completely dependent on interoperable third party systems, the Arctic Data Explorer publicly launched in 2013 with an original 3000+ data records from four Arctic repositories. Since then the search has scaled to 25,000+ data records from thirteen repositories at the time of writing. In the final months of original project funding, priorities shift to lean operations with a strategic eye on the future. Here we present lessons learned from four years of Arctic Data Explorer design, development, communication, and maintenance work along with remaining questions and potential directions.

  20. Ftklipse - Design and Implementation of an Extendable Computer Forensics Environment: Specification Design Document

    CERN Document Server

    Laverdière, Marc-André; Tsapa, Suhasini; Benredjem, Djamel

    2009-01-01

    The purpose of this work is to design and implement a plugin-based environment that allows to integrate forensic tools working together to support programming tasks and addition of new tools. Integration is done through GUI components. The end-system environment must have user friendly GUI, configuration capabilities, plug-in capabilities to insert/inject new tools, case management, and chain of custody capabilities, along with evidence gathering capabilities, evidence preservation capabilities, and, finally report generation capabilities. A subset of these requirements has been implemented in Ftklipse, an open-source project, which is detailed throughout the rest of this document.

  1. Automated design synthesis of robotic/human workcells for improved manufacturing system design in hazardous environments

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Joshua M. [Los Alamos National Laboratory

    2012-06-12

    Manufacturing tasks that are deemed too hazardous for workers require the use of automation, robotics, and/or other remote handling tools. The associated hazards may be radiological or nonradiological, and based on the characteristics of the environment and processing, a design may necessitate robotic labor, human labor, or both. There are also other factors such as cost, ergonomics, maintenance, and efficiency that also effect task allocation and other design choices. Handling the tradeoffs of these factors can be complex, and lack of experience can be an issue when trying to determine if and what feasible automation/robotics options exist. To address this problem, we utilize common engineering design approaches adapted more for manufacturing system design in hazardous environments. We limit our scope to the conceptual and embodiment design stages, specifically a computational algorithm for concept generation and early design evaluation. In regard to concept generation, we first develop the functional model or function structure for the process, using the common 'verb-noun' format for describing function. A common language or functional basis for manufacturing was developed and utilized to formalize function descriptions and guide rules for function decomposition. Potential components for embodiment are also grouped in terms of this functional language and are stored in a database. The properties of each component are given as quantitative and qualitative criteria. Operators are also rated for task-relevant criteria which are used to address task compatibility. Through the gathering of process requirements/constraints, construction of the component database, and development of the manufacturing basis and rule set, design knowledge is stored and available for computer use. Thus, once the higher level process functions are defined, the computer can automate the synthesis of new design concepts through alternating steps of embodiment and function structure

  2. Review of Opinions of Math Teachers Concerning the Learning Environment That They Design

    Science.gov (United States)

    Aydin, Bünyamin; Yavuz, Ayse

    2016-01-01

    Design of appropriate learning environment has a significant importance in creation of aims of the math teaching. In the design of learning environments, teachers play a significant role. The aim of this study is determination of opinions of the math teachers concerning the learning environment that they design. In accordance with this aim, an…

  3. Designing for Learning: Multiplayer Digital Game Learning Environments

    Science.gov (United States)

    Kim, Chung On

    2010-01-01

    Many people in general think that digital game environment has potential as a learning environment. However, empirical research in digital game environment and education is a still relative young field, so to create a digital learning environment where students are actively engaged in the learning process is a great challenge. In part, it has been…

  4. Game Design Narrative for Learning: Appropriating Adventure Game Design Narrative Devices and Techniques for the Design of Interactive Learning Environments

    Science.gov (United States)

    Dickey, Michele D.

    2006-01-01

    The purpose of this conceptual analysis is to investigate how contemporary video and computer games might inform instructional design by looking at how narrative devices and techniques support problem solving within complex, multimodal environments. Specifically, this analysis presents a brief overview of game genres and the role of narrative in…

  5. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  6. Incorporating Kansei Engineering in instructional design: Designing virtual reality based learning environments from a novel perspective

    Directory of Open Access Journals (Sweden)

    Kee Man Chuah

    2008-01-01

    Full Text Available In recent years, the application of virtual reality (VR technology in education is rapidly gaining momentum. The educational benefits offered by such technology have prompted many educators as well as instructional designers to investigate ways to create effective and engaging VR learning. Instructional designers have examined widely the capability of VR in influencing the cognitive capacity as well as motivational processes of learners. Nonetheless, one often-neglected aspect is its ability to stimulate emotions, which in turn can affect learning. With the current intense interest in designing emotionally sound instructional applications, this paper proposes a new outlook by incorporating Kansei Engineering methodology in the instructional design process. Specifically, as part of an on-going project, it describes how Kansei Engineering method can be incorporated in the design of VR based learning environments based on the model suggested by Chen, Toh and Wan (2004. The proposed method is not only able to facilitate the instructional designers in identifying desired design elements but also to refine the methods prescribed in an instructional model.

  7. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  8. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  9. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  10. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  11. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  12. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  13. Methodology for Determining the Acceptability of Given Designs in Uncertain Environments

    NARCIS (Netherlands)

    Kleijnen, J.P.C.; Pierreval, H.; Zhang, J.

    2009-01-01

    Managers wish to verify that a particular engineering design meets their require- ments. This design's future environment will differ from the environment assumed during the design. Therefore it is crucial to determine which variations in the envi- ronment may make this design unacceptable. The prop

  14. Ground Bounce Noise Reduction in Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Vipin Kumar Sharma

    2015-12-01

    Full Text Available : Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.

  15. Design for environment for the National Ignition Facility

    Energy Technology Data Exchange (ETDEWEB)

    Cantwell, E.; Gobor, K.; Celeste, J.; Cerruti, S.

    1998-05-01

    The National Ignition Facility (NIF) will be a U.S. Department of Energy (DOE) national center for inertial confinement fusion (ICF) and other research into the physics of high temperatures and high densities, and a vital element of the DOE`s nuclear weapons Stockpile Stewardship and Management Program. It will be used by scientists from a numerous different institutions and disciplines to support research advancements in national security, energy, basic science, and economic development. Multiple powerful laser beams will `ignite` small fusion targets, helping liberate more energy than is required to initiate the fusion reactions. This paper discusses the Design for Environment process for NIF, some of the subsequent activities resulting from the initial study, and a few of the lessons learned from this process. Subsequent activities include the development of a Pollution Prevention and Waste Minimization Plan (P2/WMin) for the facility, which includes Pollution Prevention Opportunity Assessments (PPOAS) on predicted waste streams from NIF, development of construction phase recycling plans, analysis of some of the specialized materials of construction to minimize future demolition and decommissioning (D&D) costs and development of cost assessments for more benign cleaning procedures that meet the stringent cleaning specifications for this facility.

  16. DESIGN OF ROBOTIC COLONIZER CONTROL SYSTEM FOR AQUEOUS ENVIRONMENT

    Directory of Open Access Journals (Sweden)

    C.VENKATESH

    2013-05-01

    Full Text Available Now a days there is a huge interest on underwater communication systems for various applications in order to explore aqueous environments. Intelligent robots and cooperative multi- agent robotic systems can be very efficient tools to speed up search and research operations in remote areas. Robots are also useful to do jobs inareas and in situations that are hazardous for human, they can go anywhere that is not reachable my humans and can go into gaps and move trough small holes that are impossible for humans and even trained dogs. in this paper, a wireless underwater mobile robot system is designed in order to study the behavior of artemia group. anew idea has been presented for underwater mobile robot system which is consists of two parts, first is the underwater mechanical robot and the second is ZigBee wireless based mobile robot which controls and moves the first part. by this system different patterns motion control (linear, circular, zigzag, etc. has been performed and proved the ability to control group of robot by controlling the group of artemia and monitoring the underwater mobile robot control with the help of water proof RF wireless camera and also explore the details present around the mobile robot

  17. A VLSI design for a trace-back Viterbi decoder

    Science.gov (United States)

    Truong, T. K.; Shih, Ming-Tang; Reed, Irving S.; Satorius, E. H.

    1992-01-01

    A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

  18. Design and Implementation of VLSI Prime Factor Algorithm Processor.

    Science.gov (United States)

    1987-12-01

    for A, 1i ’ 1 1 Fh Ai ,,r equjAtIInI. art, ( , 4 10 4,t’ 4 ( - /’ cr tht, (-arr% sur ma% akL, be represented as Figure 36 Carry Select Adder Blocking... Select Adder Blocking .......................................................... 81 Figure 37: ALU Adder Cell...ALU Logic Implementation............................................................ 81 viii J,.. in List of Figures (continued) Figure 36: Carry

  19. VLSI Design Tools, Reference Manual, Release 2.0.

    Science.gov (United States)

    1984-08-01

    xz) -.. ISOCMOS Macros md(x,y); ba(x ,y); Sop(x,y); bm(xy); 8.10. CMOSFW Macrof rgb (z,yl; rb(z,Y); 9. ISOCMOS Example The following is a sample file of...ABC B Y Eqalvalesit: Nodes A I BIC I YI I I I I IInpu Load I I I I I I I I I I mock Diev d 1/0 PWm CAI misb 32 X ~ AC Cherdortas V0 - $ input Imidm...A 1B C YI Input Load III Mek Dlr= o !/O pbS Call Wdtl 5 AC EhmdWdIes VD, - SV bpt 1tmidm TN - Sm .1. Fm Ot FIND One r. mes, Led -I Led -1l

  20. Human-centered environment design in intensive care unit

    NARCIS (Netherlands)

    Li, Y.; Albayrak, A.; Goossens, R.H.M.; Xiao, D.; Jakimowicz, J.J.

    2013-01-01

    Because of high risk and instability of the patients in Intensive care unit(ICU), the design of ICU is very difficult. ICU design, auxiliary building design, lighting design, noise control and other aspects can also enhance its management. In this paper, we compare ICU design in China and Holland ba

  1. Transition of a Three-Dimensional Unsteady Viscous Flow Analysis from a Research Environment to the Design Environment

    Science.gov (United States)

    Dorney, Suzanne; Dorney, Daniel J.; Huber, Frank; Sheffler, David A.; Turner, James E. (Technical Monitor)

    2001-01-01

    The advent of advanced computer architectures and parallel computing have led to a revolutionary change in the design process for turbomachinery components. Two- and three-dimensional steady-state computational flow procedures are now routinely used in the early stages of design. Unsteady flow analyses, however, are just beginning to be incorporated into design systems. This paper outlines the transition of a three-dimensional unsteady viscous flow analysis from the research environment into the design environment. The test case used to demonstrate the analysis is the full turbine system (high-pressure turbine, inter-turbine duct and low-pressure turbine) from an advanced turboprop engine.

  2. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  3. A social sustainability approach to birth environment design

    DEFF Research Database (Denmark)

    Jangaard, Karin; Folmer, Mette Blicher

    2016-01-01

    RESEARCH PROCESS Measuring on welness, lifequality and experience of user involvement in all processes. DESIGN PROCESS Research and design thinking USERINVOLVEMENT Ownership of design solutions CARE MODEL / ORGANISATION Humanity, vison for care and tre......RESEARCH PROCESS Measuring on welness, lifequality and experience of user involvement in all processes. DESIGN PROCESS Research and design thinking USERINVOLVEMENT Ownership of design solutions CARE MODEL / ORGANISATION Humanity, vison for care and tre...

  4. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  5. Low-power VLSI circuits and systems

    CERN Document Server

    Pal, Ajit

    2015-01-01

    The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.

  6. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  7. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  8. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  9. Signal processing in high data rate environments. Design tradeoffs in the exploitation of parallel architectures and fast system clock rates. An overview

    Science.gov (United States)

    Gilbert, B. K.; Kinter, T. M.; Schwab, D. J.; Naused, B. A.; Krueger, L. M.; Rice, K. M.; Lee, F. S.

    1983-11-01

    This conference is exploring the methods by which the emerging very large scale integration (VLSI) technology, i.e., the ability to place more than 10,000 logic gates on a single integrated circuit, can be exploited for the solution of difficult signal processing problems. The following discussion will concentrate on a highly specialized subset of the total signal processing environment, i.e., that small minority of such problems in which a single unprocessed data stream appears at the input of a digital processor in real time and at very high data bandwidths. These high volume data streams must be processed by the front end of the signal processor at clock rates equal to or greater than the rates at which they are delivered; in later stages of processing, it may be possible to partition the single high-speed data stream into a series of lower speed substreams and to institute parallel processing on the substreams. We have been compelled to consider potential solutions to these high data rate problems, and to compare these problems with the capabilities of silicon VLSI, as well as other technologies, with which they may be addressed.

  10. Method for integrated design of low energy buildings with high quality indoor environment

    DEFF Research Database (Denmark)

    Petersen, Steffen

    2008-01-01

    Energy performance and indoor environment have due to new increased regulatory demands become decisive design parameters in the building design process. In order to comply with the increased regulatory demands, we present an integrated design method which argues that the design of buildings must ...... to become the preferred method for integrated design of low energy buildings with high quality indoor environment.......Energy performance and indoor environment have due to new increased regulatory demands become decisive design parameters in the building design process. In order to comply with the increased regulatory demands, we present an integrated design method which argues that the design of buildings must...... start on room level rather than total building level. The proposed method starts with the establishment of design goals, including goals regarding energy performance and indoor environment, followed by a building physical analysis of performance-decisive parameters. This analysis is used to establish...

  11. Design of Mobile Enhanced Learning Environment on English Language Learning

    Institute of Scientific and Technical Information of China (English)

    陈文辉

    2014-01-01

    Information and Communication Technology (ICT)has brought about a totally new way of learning,that is mobile -enhanced learning environments (MELE),and it might even take the place of the traditional class teaching.The study’s objective is to measure the impact of mobile -enhanced learning environment (MELE)on English language writing.

  12. Using scenarios to design complex technology-enhanced learning environments

    NARCIS (Netherlands)

    de Jong, Anthonius J.M.; Weinberger, A.; Girault, I.; Kluge, A.W.; Lazonder, Adrianus W.; Pedaste, M.; Ludvigsen, S.; Ney, M.; Wasson, B.; Wichmann, A.; Geraedts, C.; Giemza, A.; Hovardas, T.; Julien, R.; van Joolingen, Wouter; Lejeune, A.M.; Manoli, C.; Matteman, Y.; Sarapuu, T.; Verkade, A.; Vold, V.; Zacharia, Z.

    2012-01-01

    Science Created by You (SCY) learning environments are computer-based environments in which students learn about science topics in the context of addressing a socio-scientific problem. Along their way to a solution for this problem students produce many types of intermediate products or learning obj

  13. Design Characteristics of Virtual Learning Environments: State of Research

    Science.gov (United States)

    Mueller, Daniel; Strohmeier, Stefan

    2011-01-01

    Virtual learning environments constitute current information systems' category for electronically supported training and development in (higher) education(al) and vocational training settings. Frequently expected advantages of using virtual learning environments refer, for instance, to the efficiency, individuality, ubiquity, timeliness and…

  14. A Low power and area efficient CLA adder design using Full swing GDI technique

    OpenAIRE

    Matcha Hemanth Kumar; Prof. Dr.S.M.VALI

    2015-01-01

    The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gat...

  15. The application of mechatronic design approach in a reconfigurable manufacturing environment

    CSIR Research Space (South Africa)

    Xing, B

    2010-12-01

    Full Text Available . J. Intelligent Systems Technologies and Applications, Vol. 8, Nos. 1-4, 2010 The application of mechatronic design approach in a reconfigurable manufacturing environment Bo Xing* Faculty of Engineering and the Built Environment, University...

  16. Borderless learning experiences : the development of design guidelines for collaborative distance learning environments

    NARCIS (Netherlands)

    Verdonschot, Suzanne; Kwakman, Kitty

    2004-01-01

    This study aims at the development of design guidelines that aid the educational designer in creating learning environments for collaborative learning at distance. Using a multiple case study design in which learners' experiences with distance learning environments are gathered, a theoretical model

  17. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  18. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  19. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  20. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  1. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  2. VLSI digital PSK demodulator for space communication

    Science.gov (United States)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  3. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  4. Multi-Disciplinary Multi-Fidelity Design Environment Project

    Data.gov (United States)

    National Aeronautics and Space Administration — To meet the design challenges of tomorrow, NASA and industry require advancements in the state-of-the-art for physics-based design and analysis frameworks. In...

  5. Sociotechnical design processes and working environment: The case of a continuous process wok

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design process is seen as a network building activity and as a social shaping process of the artefact. A working environment log...... is suggested as a tool designers can use to integrate considerations of future operators' working environment....

  6. Neuromorphic VLSI realization of the hippocampal formation.

    Science.gov (United States)

    Aggarwal, Anu

    2016-05-01

    The medial entorhinal cortex grid cells, aided by the subicular head direction cells, are thought to provide a matrix which is utilized by the hippocampal place cells for calculation of position of an animal during spatial navigation. The place cells are thought to function as an internal GPS for the brain and provide a spatiotemporal stamp on episodic memories. Several computational neuroscience models have been proposed to explain the place specific firing patterns of the cells of the hippocampal formation - including the GRIDSmap model for grid cells and Bayesian integration for place cells. In this work, we present design and measurement results from a first ever system of silicon circuits which successfully realize the function of the hippocampal formation of brain based on these models.

  7. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  8. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  9. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  10. Generation of graphic language-oriented design environments

    OpenAIRE

    1989-01-01

    We review some results in the area of using meta techniques to generate language-oriented programming environments. We focus on environments for languages having a two-dimensional syntax based on attribute grammars and constraints. We introduce edit-semantic attributes, a new classof attributes which control the user interaction and graphic presentation. We present LOGGIE, a prototype tool implementing some of the meta techniques discussed. The tool generates interactive language-oriented gra...

  11. INTELLIGENT MECHANISM TO SUPPORT DFX-ABILITIESIN AUTOMATED DESIGNER'S ENVIRONMENT

    Institute of Scientific and Technical Information of China (English)

    2000-01-01

    From the information integration point of view, design activities are the processes of the information handling. Mechanism module in DesignerSpace, like an operator, operates on the information (which can be thought as the input or output) being processed during certain design activity, as shown in Fig.3. Therefore, Mechanism is a comprehensive framework which intends to integrate more computational technologies along the whole product design process.  Because of different engineering application domains involved in solving a design problem, Mechanism offers generaloperator and specialoperator. The former is proposed for general mechanical product design, such as DFX; and the latter has definite application scope and needs special design technologies, for example, blankdisc design in aircraft. Any mechanism operator is giving the constraints on design, but CAD system is needed to help construct PDMD under the constraints. Generaloperator or specialoperator is made up of three basic components: knowledgebase, algorithmbase and monitoring/debugging. The components of DFX mechanism with Process module and Resource module in DesignerSpace are described in EXPRESS-G in Fig.4.2.1 Product models and operated product model data  The DFX intelligent mechanism operates on the product model data for obtaining the optimized product model data which are of DFX abilities. The product models used in DesignerSpace are structured into two levels: geometricmodel and featuremodel[11].

  12. Designing robots for industrial environments. [economic factors and vulnerability

    Science.gov (United States)

    1975-01-01

    Environmental hazards to industrial robots are summarized. The inherent reliability of the design of the Unimate robot is assessed and the data used in a management system to bring the reliability performance up to a level nearing what is theoretically available. The design is shown to be capable of a mean time between failure of 400 hours and an average up time of 98%. Specific design decisions made in view of application requirements are explored.

  13. Advances in VLSI testing at MultiGb per second rates

    Directory of Open Access Journals (Sweden)

    Topisirović Dragan

    2005-01-01

    Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

  14. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  15. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  16. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  17. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  18. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  19. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  20. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  1. Using virtual worlds as collaborative environments for innovation and design

    DEFF Research Database (Denmark)

    Ehsani, Ehsan; Chase, Scott Curland

    2009-01-01

    In this paper we discuss observations and lessons learned in conducting architectural design projects in virtual worlds. By integrating a community of users in virtual worlds into a collaborative architectural design process, organisations can tap the community's creativity and intelligence throu...

  2. Teacher-Led Design of an Adaptive Learning Environment

    Science.gov (United States)

    Mavroudi, Anna; Hadzilacos, Thanasis; Kalles, Dimitris; Gregoriades, Andreas

    2016-01-01

    This paper discusses a requirements engineering process that exemplifies teacher-led design in the case of an envisioned system for adaptive learning. Such a design poses various challenges and still remains an open research issue in the field of adaptive learning. Starting from a scenario-based elicitation method, the whole process was highly…

  3. Application of mechatronic design approach in a reconfigurable manufacturing environment

    CSIR Research Space (South Africa)

    Xing, B

    2008-12-01

    Full Text Available of reconfigurable manufacturing tools (RMTs) for RMS. But according to the literature, there is no suitable methods available yet can be applied directly to RMT design. So in this paper, the authors came up with a novel machine design approach termed mechatronics...

  4. Early user involvement in designing intelligent products and environments

    NARCIS (Netherlands)

    Kuijt-Evers, L.; Steen, M.

    2008-01-01

    A literature review was conducted on user involvement in design. The focus of the review was on how researchers and designers attempt to cooperate with end-users, with the goal of making a better match with end-users’ needs and preferences. The main goal of the research was to get insight in which m

  5. Understanding the Academic Environments: From Field Study to Design

    NARCIS (Netherlands)

    Vyas, Dhaval; de Groot, Spencer; van der Veer, Gerrit C.; Rizzo, Antonio; Grote, Gudela; Wong, William

    2006-01-01

    Ethnographic methods have been widely used for requirements elicitation purposes in systems design, especially when the focus is on understanding users’ social, cultural and political contexts. Designing an on-line search engine for peer-reviewed papers could be a challenge considering the diversity

  6. Advantageous application of Synthetic Environments in product design

    NARCIS (Netherlands)

    Miedema, J.; van der Voort, Mascha C.; van Houten, Frederikus J.A.M.

    2009-01-01

    Despite the abundance of supporting tools and methods engineers have at their disposal nowadays, the early stages of design processes are still not extensively supported. Strikingly, the whole of design aids is characterized by mono-disciplinarity, scattered availability and the fact that the majori

  7. Advantageous application of Synthetic Environments in product design

    NARCIS (Netherlands)

    Miedema, J.; van der Voort, Mascha C.; van Houten, Frederikus J.A.M.

    2009-01-01

    Despite the abundance of supporting tools and methods engineers have at their disposal nowadays, the early stages of design processes are still not extensively supported. Strikingly, the whole of design aids is characterized by mono-disciplinarity, scattered availability and the fact that the

  8. Personal Learning Environments: Challenging the dominant design of educational systems

    NARCIS (Netherlands)

    Wilson, Scott; Liber, Oleg; Beauvoir, Phil; MIlligan, Colin; Johnson, Mark; Sharples, Paul

    2006-01-01

    Current systems used in education follow a consistent design pattern, not supportive of lifelong learning or personalization, is asymmetric in terms of user capability, and which is disconnected from the global ecology of Internet services. In this paper we propose an alternative design pattern for

  9. A Virtual Environment for Resilient Infrastructure Modeling and Design

    Science.gov (United States)

    2015-09-01

    geospatially and functionally realistic structure. He uses this tool to evaluate the resilience of this fictional system. This thesis follows the basic steps...network but is illustrative of the ultimate goal to connect models of interdependent CI systems in a geographically realistic environment...each other. Therefore, optimizing usage and structure of one system realistically means optimizing the dependent systems appropriately in context

  10. Restorative Virtual Environment Design for Augmenting Nursing Home Rehabilitation

    DEFF Research Database (Denmark)

    Bruun-Pedersen, Jon Ram; Serafin, Stefania; Kofoed, Lise

    2017-01-01

    to experience natural surroundings. Augmenting a conventional biking exercise with a recreational virtual environment (RVE) has shown to serve as an intrinsic motivation contributor to exercise for nursing home residents. RVEs might be able to provide some of the health benefits that regular nature experiences...

  11. Designing a Social Environment for Human-Robot Cooperation.

    Science.gov (United States)

    Amram, Fred M.

    Noting that work is partly a social activity, and that workers' psychological and emotional needs influence their productivity, this paper explores avenues for improving human-robot cooperation and for enhancing worker satisfaction in the environment of flexible automation. The first section of the paper offers a brief overview of the…

  12. Visual Environment for Designing Interactive Learning Scenarios with Augmented Reality

    Science.gov (United States)

    Mota, José Miguel; Ruiz-Rube, Iván; Dodero, Juan Manuel; Figueiredo, Mauro

    2016-01-01

    Augmented Reality (AR) technology allows the inclusion of virtual elements on a vision of actual physical environment for the creation of a mixed reality in real time. This kind of technology can be used in educational settings. However, the current AR authoring tools present several drawbacks, such as, the lack of a mechanism for tracking the…

  13. Designing Learning Environments To Promote Conceptual Change in Science.

    Science.gov (United States)

    Vosniadou, Stella; Ioannides, Christos; Dimitrakopoulou, Aggeliki; Papademetriou, Efi

    2001-01-01

    Studied the use of research-based principles to create a learning environment for teaching mechanics to one class of Greek fifth and sixth graders. Students were encouraged to take active control of their learning, make predictions, and test their own hypotheses. Results show significant differences between experimental and control groups,…

  14. The Design of Immersive English Learning Environment Using Augmented Reality

    Science.gov (United States)

    Li, Kuo-Chen; Chen, Cheng-Ting; Cheng, Shein-Yung; Tsai, Chung-Wei

    2016-01-01

    The study uses augmented reality (AR) technology to integrate virtual objects into the real learning environment for language learning. The English AR classroom is constructed using the system prototyping method and evaluated by semi-structured in-depth interviews. According to the flow theory by Csikszenmihalyi in 1975 along with the immersive…

  15. Designing Learning Environments for Cultural Inclusivity: A Case Study of Indigenous Online Learning at Tertiary Level.

    Science.gov (United States)

    McLoughlin, Catherine; Oliver, Ron

    2000-01-01

    Considers cultural diversity in Web design and traces the design processes involved in the development of an online learning environment for indigenous Australian learners entering university. Highlights include culture, constructivist learning and situated cognition; cultural pluralism in instructional design; and ten design principles for…

  16. The influence of Chinese Classical Garden Aesthetics on the design of outdoor environment in residential area

    Institute of Scientific and Technical Information of China (English)

    石运红

    2016-01-01

    The outdoor environment of residential area is closely related to the life of the residents. This paper analyzes the aesthetic ideas of Chinese classical gardens, and seeks the way of the outdoor environment design of residential areas with perfect function, reasonable layout and beautiful environment.

  17. Design methods for fault-tolerant finite state machines

    Science.gov (United States)

    Niranjan, Shailesh; Frenzel, James F.

    1993-01-01

    VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

  18. Adding a Design Perspective to Study Learning Environments in Higher Professional Education

    Science.gov (United States)

    Zitter, Ilya; De Bruijn, Elly; Simons, P. Robert Jan; Cate, Th. J. Ten

    2011-01-01

    How to design learning environments leading to learning-, thinking, collaboration- and regulation skills which can be applied to transferable, knowledge oriented learning outcomes is still controversial. We studied the designs of learning environments in innovative higher professional education more closely. To characterize learning environments…

  19. Medium-Based Design: Extending a Medium to Create an Exploratory Learning Environment

    Science.gov (United States)

    Rick, Jochen; Lamberty, K. K.

    2005-01-01

    This article introduces "medium-based" design -- an approach to creating "exploratory learning environments" using the method of "extending a medium". First, the characteristics of exploratory learning environments and medium-based design are described and grounded in related work. Particular attention is given to "extending a medium" --…

  20. Sociotechnical design processes and working environment: The case of a continuous process wok

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design proc-ess is seen as a network building activity and as a social shaping process of the artefact. A working environment log...

  1. Sociotechnical design processes and working environment: The case of a continuous process wok

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design process is seen as a network building activity and as a social shaping process of the artefact. A working environment log...

  2. Sociotechnical design processes and working environment: The case of a continuous process wok

    DEFF Research Database (Denmark)

    Broberg, Ole

    2000-01-01

    A five-year design process of a continuous process wok has been studied with the aim of elucidating the conditions for integrating working environment aspects. The design process is seen as a network building activity and as a social shaping process of the artefact. A working environment log...

  3. Learning Environments Designed According to Learning Styles and Its Effects on Mathematics Achievement

    Science.gov (United States)

    Özerem, Aysen; Akkoyunlu, Buket

    2015-01-01

    Problem Statement: While designing a learning environment it is vital to think about learner characteristics (learning styles, approaches, motivation, interests… etc.) in order to promote effective learning. The learning environment and learning process should be designed not to enable students to learn in the same manner and at the same level,…

  4. Design of Quadcopter Robot as a Disaster Environment Remote Monitor

    National Research Council Canada - National Science Library

    Made Sudarma; I B Alit Swamardika; Adinata Mas Pratama

    2016-01-01

    .... Quadcopter was designed by using KK Board V 2.0 Flight Controller which is a series of motor rotation controller and all at once has Accelerometer censor as acceleration censor and Gyroscop censor as a balance or stability censor...

  5. Computer Aided Design Tools for Extreme Environment Electronics Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This project aims to provide Computer Aided Design (CAD) tools for radiation-tolerant, wide-temperature-range digital, analog, mixed-signal, and radio-frequency...

  6. Modelling the cybersecurity environment using morphological ontology design engineering

    CSIR Research Space (South Africa)

    Jansen van Vuuren, JC

    2015-03-01

    Full Text Available ). This methodology is based on the combination of three different research methods, i.e. design science, general morphological analysis, and ontology based representation. General morphological analysis offers a solution for extracting meaningful information from...

  7. Homeland Security Organizations: Design Contingencies in Complex Environments

    Science.gov (United States)

    2011-09-01

    in Charge Cell OMT Organization and Management Theory OPERATIONS Section Los Angeles County Operational Area Unified Command- Operations Section...and management theory” ( OMT ). The OMT literature suggests that no single organizational design is optimal in all situations, nor do all designs...referred to as Organization and Management Theory ( OMT )—have been extensively examined in the literature, using at various times and by different

  8. Integrated design optimization research and development in an industrial environment

    Science.gov (United States)

    Kumar, V.; German, Marjorie D.; Lee, S.-J.

    1989-01-01

    An overview is given of a design optimization project that is in progress at the GE Research and Development Center for the past few years. The objective of this project is to develop a methodology and a software system for design automation and optimization of structural/mechanical components and systems. The effort focuses on research and development issues and also on optimization applications that can be related to real-life industrial design problems. The overall technical approach is based on integration of numerical optimization techniques, finite element methods, CAE and software engineering, and artificial intelligence/expert systems (AI/ES) concepts. The role of each of these engineering technologies in the development of a unified design methodology is illustrated. A software system DESIGN-OPT has been developed for both size and shape optimization of structural components subjected to static as well as dynamic loadings. By integrating this software with an automatic mesh generator, a geometric modeler and an attribute specification computer code, a software module SHAPE-OPT has been developed for shape optimization. Details of these software packages together with their applications to some 2- and 3-dimensional design problems are described.

  9. Measuring Radionuclides in the environment: radiological quantities and sampling designs

    Energy Technology Data Exchange (ETDEWEB)

    Voigt, G. [ed.] [GSF - Forschungszentrum fuer Umwelt und Gesundheit Neuherberg GmbH, Oberschleissheim (Germany). Inst. fuer Strahlenschutz

    1998-10-01

    One aim of the workshop was to support and provide an ICRU report committee (International Union of Radiation Units) with actual information on techniques, data and knowledge of modern radioecology when radionuclides are to be measured in the environment. It has been increasingly recognised that some studies in radioecology, especially those involving both field sampling and laboratory measurements, have not paid adequate attention to the problem of obtaining representative, unbiased samples. This can greatly affect the quality of scientific interpretation, and the ability to manage the environment. Further, as the discipline of radioecology has developed, it has seen a growth in the numbers of quantities and units used, some of which are ill-defined and which are non-standardised. (orig.)

  10. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  11. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  12. Internal Charging Design Environments for the Earths Radiation Belts

    Science.gov (United States)

    Minow, Joseph I.; Edwards, David L.

    2009-01-01

    Relativistic electrons in the Earth's radiation belts are a widely recognized threat to spacecraft because they penetrate lightly shielded vehicle hulls and deep into insulating materials where they accumulate to sufficient levels to produce electrostatic discharges. Strategies for evaluating the magnitude of the relativistic electron flux environment and its potential for producing ESD events are varied. Simple "rule of thumb" estimates such as the widely used 10(exp 10) e-/sq cm fluence within 10 hour threshold for the onset of pulsing in dielectric materials provide a quick estimate of when to expect charging issues. More sophisticated strategies based on models of the trapped electron flux within the Earth s magnetic field provide time dependent estimates of electron flux along spacecraft orbits and orbit integrate electron flux. Finally, measurements of electron flux can be used to demonstrate mean and extreme relativistic electron environments. This presentation will evaluate strategies used to specify energetic electron flux and fluence environments along spacecraft trajectories in the Earth s radiation belts.

  13. A Design-Based Research Investigation of a Web-Based Learning Environment Designed to Support the Reading Process

    Science.gov (United States)

    Kidwai, Khusro

    2009-01-01

    This research study had two purposes, (a) to design and develop a Web-based learning environment that supports the use of a set of reading strategies, and (b) to investigate the impact of this Web-based learning environment on readers' "memory" and "understanding" of an instructional unit on the human heart (Dwyer &…

  14. Design Quality in the Context of Healthcare Environments: A Scoping Review.

    Science.gov (United States)

    Anåker, Anna; Heylighen, Ann; Nordin, Susanna; Elf, Marie

    2017-07-01

    We explored the concept of design quality in relation to healthcare environments. In addition, we present a taxonomy that illustrates the wide range of terms used in connection with design quality in healthcare. High-quality physical environments can promote health and well-being. Developments in healthcare technology and methodology put high demands on the design quality of care environments, coupled with increasing expectations and demands from patients and staff that care environments be person centered, welcoming, and accessible while also supporting privacy and security. In addition, there are demands that decisions about the design of healthcare architecture be based on the best available information from credible research and the evaluation of existing building projects. The basic principles of Arksey and O'Malley's model of scoping review design were used. Data were derived from literature searches in scientific databases. A total of 18 articles and books were found that referred to design quality in a healthcare context. Design quality of physical healthcare environments involves three different themes: (i) environmental sustainability and ecological values, (ii) social and cultural interactions and values, and (iii) resilience of the engineering and building construction. Design quality was clarified herein with a definition. Awareness of what is considered design quality in relation to healthcare architecture could help to design healthcare environments based on evidence. To operationalize the concept, its definition must be clear and explicit and able to meet the complex needs of the stakeholders in a healthcare context, including patients, staff, and significant others.

  15. Multimodality and Design of Interactive Virtual Environments for Creative Collaboration

    DEFF Research Database (Denmark)

    Gürsimsek, Remzi Ates

    . The three-dimensional representation of space and the resources for non-verbal communication enable the users to interact with the digital content in more complex yet engaging ways. However, understanding the communicative resources in virtual spaces with the theoretical tools that are conventionally used......-user interaction, customization and interdisciplinary collaboration. These spaces accommodate new forms of spatial and social practices, provide multimodal communication resources in physical and virtual environments, and allow individuals (or groups) to actively engage with collaborative creative experiences...

  16. Adaptive Collaboration Support Systems: Designing Collaboration Support for Dynamic Environments

    NARCIS (Netherlands)

    Janeiro, J.; Knoll, S.W.; Lukosch, S.G.; Kolfschoten, G.L.

    2012-01-01

    Today, engineering systems offer a variety of local and webbased applications to support collaboration by assisting groups in structuring activities, generating and sharing data, and improving group communication. To ensure the quality of collaboration, engineering system design needs to analyze and

  17. Design Environment for Novel Vertical Lift Vehicles: DELIVER

    Science.gov (United States)

    Theodore, Colin

    2016-01-01

    This is a 20 minute presentation discussing the DELIVER vision. DELIVER is part of the ARMD Transformative Aeronautics Concepts Program, particularly the Convergent Aeronautics Solutions Project. The presentation covers the DELIVER vision, transforming markets, conceptual design process, challenges addressed, technical content, and FY2016 key activities.

  18. Designing presence for real locomotion in immersive virtual environments

    DEFF Research Database (Denmark)

    Turchet, Luca

    2015-01-01

    that allows VE designers to evaluate the maturity of their systems and to pinpoint directions for future developments. A survey analysis was performed using the proposed framework, which involved three case studies to determine how many features of the proposed framework were present and their status...

  19. Fictional space in participatory design of engaging interactive environments

    DEFF Research Database (Denmark)

    Dindler, Christian

    2010-01-01

    . This provides the basis for more nuanced insights as to how participants envision that their practices might change and which particular aspects hold most potential and resistance. Third, the notion provides concepts for designers to reflect on how ideas, scenarios, or mock-ups developed during particular...

  20. Designing the online oral language learning environment SpeakApps

    NARCIS (Netherlands)

    Nic Giolla Mhichíl, Mairéad; Appel, Christine; Ó Ciardubháin, Colm; Jager, Sake; Prizel-Kania, Adriana

    2015-01-01

    Purpose – The purpose of this paper is to report on SpeakApps, a major collaborative computer-assisted language learning project, developed based on an open source techno-pedagogical solution to facilitate online oral language production and interaction. Design/methodology/approach – A mixed method