Parallel optimization algorithms and their implementation in VLSI design
Lee, G.; Feeley, J. J.
1991-01-01
Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.
Basu, D K
2014-01-01
Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...
Einspruch, Norman G
1986-01-01
VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special
Chandrasetty, Vikram Arkalgud
2011-01-01
This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic
A VLSI design concept for parallel iterative algorithms
Directory of Open Access Journals (Sweden)
C. C. Sun
2009-05-01
Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.
Parallel VLSI design for the fast -D DWT core algorithm
Institute of Scientific and Technical Information of China (English)
WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong
2007-01-01
By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.
Directory of Open Access Journals (Sweden)
Rachmad Vidya Wicaksana Putra
2016-06-01
Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
DEFF Research Database (Denmark)
Rasmussen, Ole Steen
This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.
Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm
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I. Hameem Shanavas
2014-01-01
Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
Interaction of algorithm and implementation for analog VLSI stereo vision
Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.
1991-07-01
Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.
A coherent VLSI design environment
Penfield, Paul, Jr.
1988-05-01
The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.
The Fifth NASA Symposium on VLSI Design
1993-01-01
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.
Artificial immune system algorithm in VLSI circuit configuration
Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd
2017-08-01
In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.
1980-04-17
been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE
A novel 3D algorithm for VLSI floorplanning
Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira
2013-01-01
3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.
A fast neural-network algorithm for VLSI cell placement.
Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail
1998-12-01
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems
2015-01-01
This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...
A special purpose silicon compiler for designing supercomputing VLSI systems
Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.
1991-01-01
Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.
Compact MOSFET models for VLSI design
Bhattacharyya, A B
2009-01-01
Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Directory of Open Access Journals (Sweden)
Cavallaro Joseph R
2006-01-01
Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.
Harnessing VLSI System Design with EDA Tools
Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj
2012-01-01
This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...
Design and Verification of High-Speed VLSI Physical Design
Institute of Scientific and Technical Information of China (English)
Dian Zhou; Rui-Ming Li
2005-01-01
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.
High performance genetic algorithm for VLSI circuit partitioning
Dinu, Simona
2016-12-01
Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.
AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT
Directory of Open Access Journals (Sweden)
Y. Y. Lankevich
2015-01-01
Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.
Communication Protocols Augmentation in VLSI Design Applications
Directory of Open Access Journals (Sweden)
Kanhu Charan Padhy
2015-05-01
Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.
1992-01-01
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.
VLSI design techniques for floating-point computation
Energy Technology Data Exchange (ETDEWEB)
Bose, B. K.
1988-01-01
The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors
Directory of Open Access Journals (Sweden)
S. K. Nandy
1994-01-01
Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.
An adaptive, lossless data compression algorithm and VLSI implementations
Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu
1993-01-01
This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.
A Coherent VLSI Design Environment
1987-03-31
In the figure, AminH and Ama.H represent the smallest and largest eigenvalues I of YH and AminAH and AmaAH represent the smallest and largest...Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International Conference on Computer-Aided
Digital VLSI algorithms and architectures for support vector machines.
Anguita, D; Boni, A; Ridella, S
2000-06-01
In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.
VLSI Design of a Turbo Decoder
Fang, Wai-Chi
2007-01-01
A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.
A Design Methodology for Optoelectronic VLSI
2007-01-01
it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a
Technology computer aided design simulation for VLSI MOSFET
Sarkar, Chandan Kumar
2013-01-01
Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and
The VLSI-PLM Board: Design, Construction, and Testing
1989-03-01
Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The
A VLSI Algorithm for Calculating the Treee to Tree Distance
Institute of Scientific and Technical Information of China (English)
徐美瑞; 刘小林
1993-01-01
Given two ordered,labeled trees βand α，to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.
NASA Space Engineering Research Center for VLSI System Design
1993-01-01
This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.
The 1992 4th NASA SERC Symposium on VLSI Design
Whitaker, Sterling R.
1992-01-01
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.
A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar
Fang, W.
1994-01-01
For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.
Efficient FM Algorithm for VLSI Circuit Partitioning
Directory of Open Access Journals (Sweden)
M.RAJESH
2013-04-01
Full Text Available In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if theinitial partitioning matrix is close to the final partitioning then the computation time (iteration required is small . Here we have proposed novel approach to arrive at initial partitioning by using spectralfactorization method the results was verified using several circuits.
NASA Space Engineering Research Center for VLSI systems design
1991-01-01
This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.
Handbook of VLSI chip design and expert systems
Schwarz, A F
1993-01-01
Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.
A bioinspired collision detection algorithm for VLSI implementation
Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.
2005-06-01
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.
VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement
Directory of Open Access Journals (Sweden)
Jigar Shah
2012-07-01
Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.
Design of Analog VLSI Architecture for DCT
2012-01-01
When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...
VLSI physical design analyzer: A profiling and data mining tool
Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi
2015-03-01
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
VLSI Universal Noiseless Coder
Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi
1989-01-01
Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard
Institute of Scientific and Technical Information of China (English)
Li Zhang; Don Xie; Di Wu
2006-01-01
The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.
Design of Analog VLSI Architecture for DCT
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M.Thiruveni
2012-08-01
Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel
2015-01-01
This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...
Replacing design rules in the VLSI design cycle
Hurley, Paul; Kryszczuk, Krzysztof
2012-03-01
We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Directory of Open Access Journals (Sweden)
Chávez-Bracamontes Ramón
2015-07-01
Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding
Design of a VLSI Decoder for Partially Structured LDPC Codes
Directory of Open Access Journals (Sweden)
Fabrizio Vacca
2008-01-01
of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.
2-D DCT Algorithm and Its Reduced VLSI Design%二维DCT算法及其精简的VLSI设计
Institute of Scientific and Technical Information of China (English)
陈伟; 卢贵主; 郑灵翔
2008-01-01
采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.
VLSI design for fault-dictionary based testability
Miller, Charles D.
The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.
Formal verification an essential toolkit for modern VLSI design
Seligman, Erik; Kumar, M V Achutha Kiran
2015-01-01
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific
Directory of Open Access Journals (Sweden)
B. SENTHILKUMAR
2015-05-01
Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.
VLSI chip-set for data compression using the Rice algorithm
Venbrux, J.; Liu, N.
1990-01-01
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
Dual Butterfly Match Filter VLSI Design
Institute of Scientific and Technical Information of China (English)
LIU Zhenyu; HAN Yueqiu
2001-01-01
Match filter is widely used in realtime signal processing, especially in Radar Signal Processing. This paper provides a novel ASIC design,which not only saves resource, but also improves thethroughput of the system. This ASIC is specially designed for Radar Pulse Compression. Certainly it canalso be used in other circumstances, such as FIR filter.
Kleinberg, Jon
2006-01-01
Algorithm Design introduces algorithms by looking at the real-world problems that motivate them. The book teaches students a range of design and analysis techniques for problems that arise in computing applications. The text encourages an understanding of the algorithm design process and an appreciation of the role of algorithms in the broader field of computer science.
Simplified microprocessor design for VLSI control applications
Cameron, K.
1991-01-01
A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
Knowledge-based synthesis of custom VLSI physical design tools: First steps
Setliff, Dorothy E.; Rutenbar, Rob A.
A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.
A DRAM compiler algorithm for high performance VLSI embedded memories
Eldin, A. G.
1992-01-01
In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris
2011-01-01
This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.
VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm
Directory of Open Access Journals (Sweden)
Fazal Noorbasha
2014-04-01
Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.
On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
Lin, Meng-Chun; Dung, Lan-Rong
2008-02-01
This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.
Beyond-Binary Arithmetic: Algorithms and VLSI Implementations
Aoki, Takafumi; Higuchi, Tatsuo
2000-01-01
Beyond-binary arithmetic algorithms are defined as a new class of computer arithmetic algorithms which employ non-binary data representations to achieve higher performances beyond those of conventional binary algorithms. This paper presents prominent examples of beyond-binary arithmetic algorithms: examples include (i) a high-radix redundant division algorithm without using lookup tables, (ii) a high-radix redundant CORDIC algorithm for fast vector rotation, and (iii) redundant complex arithm...
Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips
Institute of Scientific and Technical Information of China (English)
WANGJun
2004-01-01
Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.
VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.
Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram
2010-01-01
In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
Directory of Open Access Journals (Sweden)
D.Yammenavar
2011-08-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.
Design and Analog VLSI Implementation of Artificial Neural Network
Directory of Open Access Journals (Sweden)
Prof. Bapuray.D.Yammenavar
2011-07-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.
A VLSI optimal constructive algorithm for classification problems
Energy Technology Data Exchange (ETDEWEB)
Beiu, V. [Los Alamos National Lab., NM (United States); Draghici, S.; Sethi, I.K. [Wayne State Univ., Detroit, MI (United States)
1997-10-01
If neural networks are to be used on a large scale, they have to be implemented in hardware. However, the cost of the hardware implementation is critically sensitive to factors like the precision used for the weights, the total number of bits of information and the maximum fan-in used in the network. This paper presents a version of the Constraint Based Decomposition training algorithm which is able to produce networks using limited precision integer weights and units with limited fan-in. The algorithm is tested on the 2-spiral problem and the results are compared with other existing algorithms.
New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Directory of Open Access Journals (Sweden)
M. V. Atre
1995-07-01
Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.
Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.
1984-10-01
analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI
VLSI electronics microstructure science
1981-01-01
VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi
A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute
Williams, John
2008-01-01
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the
Kemeny, Sabrina E.
1994-01-01
Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional
VLSI design of an RSA encryption/decryption chip using systolic array based architecture
Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi
2016-09-01
This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
2011-01-01
Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...
Directory of Open Access Journals (Sweden)
Sidorenko V. P.
2012-08-01
Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.
VLSI implementations for image communications
Pirsch, P
1993-01-01
The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits
Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En
2015-08-13
A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris; Verbauwhede, Ingrid
2007-01-01
Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...
Carbon nanotube based VLSI interconnects analysis and design
Kaushik, Brajesh Kumar
2015-01-01
The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit
2016-09-01
The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
A cost-effective methodology for the design of massively-parallel VLSI functional units
Venkateswaran, N.; Sriram, G.; Desouza, J.
1993-01-01
In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm
Directory of Open Access Journals (Sweden)
Ying-Lun Chen
2015-08-01
Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2010-06-01
Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design
Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
Directory of Open Access Journals (Sweden)
Ankush S. Patharkar
2014-07-01
Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S.
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.
A VLSI design for a trace-back Viterbi decoder
Truong, T. K.; Shih, Ming-Tang; Reed, Irving S.; Satorius, E. H.
1992-01-01
A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.
Research News: Are VLSI Microcircuits Too Hard to Design?
Robinson, Arthur L.
1980-01-01
This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)
Principles of VLSI RTL design a practical guide
Churiwala, Sanjay; Gianfagna, Mike
2011-01-01
This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.
Design and implementation of multipattern generators in analog VLSI.
Kier, Ryan J; Ames, Jeffrey C; Beer, Randall D; Harrison, Reid R
2006-07-01
In recent years, computational biologists have shown through simulation that small neural networks with fixed connectivity are capable of producing multiple output rhythms in response to transient inputs. It is believed that such networks may play a key role in certain biological behaviors such as dynamic gait control. In this paper, we present a novel method for designing continuous-time recurrent neural networks (CTRNNs) that contain multiple embedded limit cycles, and we show that it is possible to switch the networks between these embedded limit cycles with simple transient inputs. We also describe the design and testing of a fully integrated four-neuron CTRNN chip that is used to implement the neural network pattern generators. We provide two example multipattern generators and show that the measured waveforms from the chip agree well with numerical simulations.
Skiena, Steven S
2008-01-01
Explaining designing algorithms, and analyzing their efficacy and efficiency, this book covers combinatorial algorithms technology, stressing design over analysis. It presents instruction on methods for designing and analyzing computer algorithms. It contains the catalog of algorithmic resources, implementations and a bibliography
A digital neuron-type processor and its VLSI design
Akel, H.; Habib, Mahmoud K.
1989-05-01
A set of neuron-type circuits elements based on logic gate circuits with multiinput multifan output capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base, and the axon circuit. These three elements are cascaded to form a neuron-type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VSLI techniques.
An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips
Deutsch, L. J.
1985-01-01
A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.
Ramachandran, S
2007-01-01
Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs
Energy Technology Data Exchange (ETDEWEB)
Hojat, S.
1986-01-01
The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.
Einspruch, Norman G; Gildenblat, Gennady Sh
1987-01-01
VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec
A unified approach to VLSI layout automation and algorithm mapping on processor arrays
Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.
1993-01-01
Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.
VLSI design of 3D display processing chip for binocular stereo displays
Institute of Scientific and Technical Information of China (English)
Ge Chenyang; Zheng Nanning
2010-01-01
In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.
Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.
A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.
Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo
2013-09-01
Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.
VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.
1983-10-01
34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being
Design of a reliable and self-testing VLSI datapath using residue coding techniques
Sayers, I. L.; Kinniment, D. J.; Chester, E. G.
1986-05-01
The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.
Design and Implementation of VLSI Prime Factor Algorithm Processor.
1987-12-01
for A, 1i ’ 1 1 Fh Ai ,,r equjAtIInI. art, ( , 4 10 4,t’ 4 ( - /’ cr tht, (-arr% sur ma% akL, be represented as Figure 36 Carry Select Adder Blocking... Select Adder Blocking .......................................................... 81 Figure 37: ALU Adder Cell...ALU Logic Implementation............................................................ 81 viii J,.. in List of Figures (continued) Figure 36: Carry
Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute
Williams, John Michael
2014-01-01
This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics inclu...
Sharma, Hrishikesh
2011-01-01
Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...
An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans
2015-04-01
This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems
Directory of Open Access Journals (Sweden)
Jen-Chih Kuo
2003-12-01
Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35Ã¢Â€Â‰ÃŽÂ¼m 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80Ã¢Â€Â‰MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256Ã¢ÂˆÂ¼2K, DAB, and 2K-mode DVB.
Analysis and compensation of the effects of analog VLSI arithmetic on the LMS algorithm.
Carvajal, Gonzalo; Figueroa, Miguel; Sbarbaro, Daniel; Valenzuela, Waldo
2011-07-01
Analog very large scale integration implementations of neural networks can compute using a fraction of the size and power required by their digital counterparts. However, intrinsic limitations of analog hardware, such as device mismatch, charge leakage, and noise, reduce the accuracy of analog arithmetic circuits, degrading the performance of large-scale adaptive systems. In this paper, we present a detailed mathematical analysis that relates different parameters of the hardware limitations to specific effects on the convergence properties of linear perceptrons trained with the least-mean-square (LMS) algorithm. Using this analysis, we derive design guidelines and introduce simple on-chip calibration techniques to improve the accuracy of analog neural networks with a small cost in die area and power dissipation. We validate our analysis by evaluating the performance of a mixed-signal complementary metal-oxide-semiconductor implementation of a 32-input perceptron trained with LMS.
Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts
Scheibler, Robin; Chebira, Amina
2011-01-01
We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.
Fully-depleted silicon-on-sapphire and its application to advanced VLSI design
Offord, Bruce W.
1992-01-01
In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.
Driving a car with custom-designed fuzzy inferencing VLSI chips and boards
Pin, Francois G.; Watanabe, Yutaka
1993-01-01
Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human
VLSI Architectures for Computing DFT's
Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.
1986-01-01
Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.
Self arbitrated VLSI asynchronous sequential circuits
Whitaker, S.; Maki, G.
1990-01-01
A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.
The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter
2001-09-01
December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60
A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation
Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans
2017-04-01
A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.
Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture
Directory of Open Access Journals (Sweden)
Farouk Smith
2015-07-01
Full Text Available This paper propose a Virtual-Field Programmable Gate Array (V-FPGA architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA; and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm; applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.
An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm
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Tze-Yun Sung
2010-01-01
Full Text Available Discrete Cosine transform (DCT and inverse DCT (IDCT have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array and SoC (system on chip. The linear-array DCT/IDCT processor with the computation complexity O(5N/8 and hardware complexity O(5N/8 is fully pipelined and scalable for variable-length DCT/IDCT computations.
VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal
Satheeskumaran, S.; Sabrigiriraj, M.
2016-06-01
Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.
VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.
1985-08-01
purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be
Hu, Kai; Ho, Tsung-Yi
2017-01-01
This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...
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Urard Pascal
2006-01-01
Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.
VLSI electronics microstructure science
1982-01-01
VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t
McKenzie, Neil
1989-12-01
We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.
Chen, Wai-Kai
2007-01-01
Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe
Algorithms in combinatorial design theory
Colbourn, CJ
1985-01-01
The scope of the volume includes all algorithmic and computational aspects of research on combinatorial designs. Algorithmic aspects include generation, isomorphism and analysis techniques - both heuristic methods used in practice, and the computational complexity of these operations. The scope within design theory includes all aspects of block designs, Latin squares and their variants, pairwise balanced designs and projective planes and related geometries.
Design and VLSI Implementation of Anticollision Enabled Robot Processor Using RFID Technology
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Joyashree Bag
2012-12-01
Full Text Available RFID is a low power wireless emerging technology which has given rise to highly promising applications in real life. It can be employed for robot navigation. In multi-robot environment, when many robots are moving in the same work space, there is a possibility of their physical collision with themselves as well as with physical objects. In the present work, we have proposed and developed a processor incorporating smart algorithm for avoiding such collisions with the help of RFID technology and implemented it by using VHDL. The design procedure and the simulated results are very useful in designing and implementing a practical RFID system. The RTL schematic view of the processor is achieved by successfully synthesizing the proposed design.KEYWORDS
Advanced symbolic analysis for VLSI systems methods and applications
Shi, Guoyong; Tlelo Cuautle, Esteban
2014-01-01
This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...
PLA realizations for VLSI state machines
Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.
1990-01-01
A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.
Implementing neural architectures using analog VLSI circuits
Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.
1989-05-01
Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.
Einspruch, Norman G
1989-01-01
VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The
Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices
Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun
2014-05-01
With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.
AN EXPANSIVE AND COMPARABLE STUDY OF EFFECTUAL ALGORITHMS FOR PLACEMENT IN PHYSICAL DESIGN
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PRAGYA SHARMA
2014-11-01
Full Text Available This review paper consists of comprehensive study of VLSI algorithms for placement in physical design. The work has been classified under different perspectives like performance,area,wirelength,cost and power and the algorithms address the coverage and optimization of these factors. Placement is a major step for VLSI physical design as it involves placing the blocks on the chip with minimum possible area consumption however the initial placement is done by constructive placement algorithms such as constructive and iterative placement. Under the survey work which is done, the knowledge of placement algorithms with their merits and limitations has been provided so that according to the requirement one can choose the best algorithm. The survey involves simulation of different algorithms implemented in C and C++ programming languages. Tools from the EDA vendors have been provided for the simulation work so as to achieve the results and to have best possible outcomes. We survey the history of placement research, the progress achieved up to now, and outstanding challenges. Some future work has also been mentioned in which the research work can be carried upon.
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Miss. Rachana R. Patil
2015-01-01
Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology
VLSI signal processing technology
Swartzlander, Earl
1994-01-01
This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in...
Analogue VLSI for probabilistic networks and spike-time computation.
Murray, A
2001-02-01
The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.
Bilinear Interpolation Image Scaling Processor for VLSI
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Ms. Pawar Ashwini Dilip
2014-05-01
Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process
VLSI Watermark Implementations and Applications
Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly
2008-01-01
This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...
Design and Realization of Array Signal Processor VLSI Architecture for Phased Array System
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D. Govind Rao
2016-08-01
Full Text Available A method for implementing an array signal processor for phased array radars. The array signal processor can receive planar array antenna inputs and can process it. It is based on the application of Adaptive Digital beam formers using FPGAs. Adaptive filter algorithm used here is Inverse Q-R Decomposition based Recursive Least Squares (IQRD-RLS [1] algorithm. Array signal processor based on FPGAs is suitable in the areas of Phased Array Radar receiver, where speed, accuracy and numerical stability are of utmost important. Using IQRD-RLS algorithm, optimal weights are calculated in much less time compared to conventional QRD-RLS algorithm. A customized multiple FPGA board comprising three Kintex-7 FPGAs is employed to implement array signal processor. The proposed architecture can form multiple beams from planar array antenna elements
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Xie Xiang
2007-01-01
Full Text Available In order to decrease the communication bandwidth and save the transmitting power in the wireless endoscopy capsule, this paper presents a new near-lossless image compression algorithm based on the Bayer format image suitable for hardware design. This algorithm can provide low average compression rate ( bits/pixel with high image quality (larger than dB for endoscopic images. Especially, it has low complexity hardware overhead (only two line buffers and supports real-time compressing. In addition, the algorithm can provide lossless compression for the region of interest (ROI and high-quality compression for other regions. The ROI can be selected arbitrarily by varying ROI parameters. In addition, the VLSI architecture of this compression algorithm is also given out. Its hardware design has been implemented in m CMOS process.
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ZhiHua Wang
2007-01-01
Full Text Available In order to decrease the communication bandwidth and save the transmitting power in the wireless endoscopy capsule, this paper presents a new near-lossless image compression algorithm based on the Bayer format image suitable for hardware design. This algorithm can provide low average compression rate (2.12 bits/pixel with high image quality (larger than 53.11 dB for endoscopic images. Especially, it has low complexity hardware overhead (only two line buffers and supports real-time compressing. In addition, the algorithm can provide lossless compression for the region of interest (ROI and high-quality compression for other regions. The ROI can be selected arbitrarily by varying ROI parameters. In addition, the VLSI architecture of this compression algorithm is also given out. Its hardware design has been implemented in 0.18μm CMOS process.
Institute of Scientific and Technical Information of China (English)
陈雄峰; 吴景岚; 朱文兴
2014-01-01
A hybrid genetic simulated annealing algorithm is presented for solving the problem of VLSI standard cell placement with up to millions of cells. Firstly, to make genetic algorithm be capable of handling very large scale of standard cell placement, the strategies of small size population, dynamic updating population, and crossover localization are adopted, and the global search and local search of genetic algorithm are coordinated. Then, by introducing hill climbing ( HC) and simulated annealing ( SA) into the framework of genetic algorithm and the internal procedure of its operators, an effective crossover operator named Net Cycle Crossover and local search algorithms for the placement problem are designed to further improve the evolutionary efficiency of the algorithm and the quality of its placement results. In the algorithm procedure, HC method and SA method focus on array placement and non-array placement respectively. The experimental results on Peko suite3, Peko suite4 and ISPD04 benchmark circuits show that the proposed algorithm can handle array and non-array placements with 10,000 ~1,600,000 cells and 10,000~210,000 cells respectively, and can effectively improve the quality of placement results in a reasonable running time.%提出有效处理百万个VLSI标准单元布局问题的混合遗传模拟退火算法。首先采用小规模种群、动态更新种群和交叉局部化策略，并协调全局与局部搜索，使遗传算法可处理超大规模标准单元布局问题。然后为进一步提高算法进化效率和布局结果质量，将爬山和模拟退火方法引入遗传算法框架及其算子内部流程，设计高效的线网-循环交叉算子和局部搜索算法。标准单元阵列布局侧重使用爬山法，非阵列布局侧重使用模拟退火方法。 Peko suite3、Peko suite4和ISPD04标准测试电路的实验结果表明，该算法可在合理运行时间内有效提高布局结果质量。
VLSI architectures for computing multiplications and inverses in GF(2-m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.
1983-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
VLSI architectures for computing multiplications and inverses in GF(2m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.
1985-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
1984-04-01
massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly
Implementation of Plasmonics in VLSI
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Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Implementation of Plasmonics in VLSI
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Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design
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Sumit Vaidya
2010-07-01
Full Text Available A typical processor central processing unit devotes a considerable amount of processing time inperforming arithmetic operations, particularly multiplication operations. Multiplication is one of thebasic arithmetic operations and it requires substantially more hardware resources and processing timethan addition and subtraction. In fact, 8.72% of all the instruction in typical processing units ismultiplication. In this paper, comparative study of different multipliers is done for low power requirementand high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient IndianVedic Mathematics which is utilized for multiplication to improve the speed, area parameters ofmultipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e.“Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.
A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.
Tseng, Yu-Cheng; Hsu, Po-Hsiung; Chang, Tian-Sheuan
2011-11-01
This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology
Rita M. Shende; Pritesh R. Gumble
2012-01-01
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the prod...
Einspruch, Norman G
1984-01-01
VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section
Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi
2013-01-01
This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology
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Rita M. Shende
2012-01-01
Full Text Available Analog-to-digital converters (ADCs are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since theADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially powerconsumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.
Design of a VLSI charge-coupled device analog delay line
Gedra, David R.
1995-03-01
Charge coupled devices (CCD's) are semiconductor devices which can transfer information, represented by a quantity of electrical charge, from one physical location of the semiconductor substrate to another in a controlled manner with the use of properly sequenced clock pulses. These devices can be applied to imaging, signal processing, logic, and digital storage applications. In this thesis, the design of an electrically stimulated CCD analog delay line, using the design tools currently available at the Naval Postgraduate School, is reported on. The major issues addressed are the electrode gate structure and composition, charge confinement techniques, and clocking schemes. Additionally, techniques for inpuning and detecting charge packets from the CCD register are examined. The Metal Oxide Semiconductor Integration Service (MOSIS) design rules only permit Bulk Channel Charge Couple Devices (BCCD's) to be lald out, and not Surface Channel Charge Coupled Devices (SCCD's). Restricted to a die size of 2.24 mm length, the electrode gates were chosen to be polysilicon polysilicon 8 micron length with 2 micron overlap and 20 micron width, giving the BCCD 64 stages. An on chip four phase clocking circuit with output drivers on each phase provides the control voltage for the gate electrodes. The small width of the BCCD delay line utilizes only a small portion of the available 2.22 mm die width. Therefore, four different BCCD's were designed in the layout. Two of the BCCD's have a p-diffusion stop to contain the charge laterally as it propagates along the channel while two BCCD's do not. Additionally, two of the BCCD's utilize the charge partition input technique with three control gates and two BCCD's use the dynamic current injection with one control gate.
VLSI design of lossless frame recompression using multi-orientation prediction
Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo
2016-01-01
Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.
Molecular beacon sequence design algorithm.
Monroe, W Todd; Haselton, Frederick R
2003-01-01
A method based on Web-based tools is presented to design optimally functioning molecular beacons. Molecular beacons, fluorogenic hybridization probes, are a powerful tool for the rapid and specific detection of a particular nucleic acid sequence. However, their synthesis costs can be considerable. Since molecular beacon performance is based on its sequence, it is imperative to rationally design an optimal sequence before synthesis. The algorithm presented here uses simple Microsoft Excel formulas and macros to rank candidate sequences. This analysis is carried out using mfold structural predictions along with other free Web-based tools. For smaller laboratories where molecular beacons are not the focus of research, the public domain algorithm described here may be usefully employed to aid in molecular beacon design.
Verweij, Jan F.
1993-01-01
Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was
Automatic design of decision-tree algorithms with evolutionary algorithms.
Barros, Rodrigo C; Basgalupp, Márcio P; de Carvalho, André C P L F; Freitas, Alex A
2013-01-01
This study reports the empirical analysis of a hyper-heuristic evolutionary algorithm that is capable of automatically designing top-down decision-tree induction algorithms. Top-down decision-tree algorithms are of great importance, considering their ability to provide an intuitive and accurate knowledge representation for classification problems. The automatic design of these algorithms seems timely, given the large literature accumulated over more than 40 years of research in the manual design of decision-tree induction algorithms. The proposed hyper-heuristic evolutionary algorithm, HEAD-DT, is extensively tested using 20 public UCI datasets and 10 microarray gene expression datasets. The algorithms automatically designed by HEAD-DT are compared with traditional decision-tree induction algorithms, such as C4.5 and CART. Experimental results show that HEAD-DT is capable of generating algorithms which are significantly more accurate than C4.5 and CART.
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms
Directory of Open Access Journals (Sweden)
I. Hameem Shanavas
2011-01-01
Full Text Available Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.
Bisection technique for designing synchronous parallel algorithms
Institute of Scientific and Technical Information of China (English)
王能超
1995-01-01
A basic technique for designing synchronous parallel algorithms, the so-called bisection technique, is proposed. The basic pattern of designing parallel algorithms is described. The relationship between the designing idea and I Ching (principles of change) is discussed.
MICROSTRIP COUPLER DESIGN USING BAT ALGORITHM
Directory of Open Access Journals (Sweden)
EzgiDeniz Ulker
2014-01-01
Full Text Available Evolutionary and swarm algorithms have found many applications in design problems since todays computing power enables these algorithms to find solutions to complicated design problems very fast. Newly proposed hybridalgorithm, bat algorithm, has been applied for the design of microwave microstrip couplers for the first time. Simulation results indicate that the bat algorithm is a very fast algorithm and it produces very reliable results.
VLSI Processor For Vector Quantization
Tawel, Raoul
1995-01-01
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
1992-01-01
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
Einspruch, Norman G
1987-01-01
VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.
VLSI implementation of neural networks.
Wilamowski, B M; Binfet, J; Kaynak, M O
2000-06-01
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.
Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.
Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David
2005-11-01
A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.
Chen, Wai-Kai
2009-01-01
Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.
VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network
Directory of Open Access Journals (Sweden)
Mohd Asyraf Mansor
2016-09-01
Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.
VLSI 'smart' I/O module development
Kirk, Dan
The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj
1993-01-01
Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.
Designing algorithms using CAD technologies
Directory of Open Access Journals (Sweden)
Alin IORDACHE
2008-01-01
Full Text Available A representative example of eLearning-platform modular application, Ã¢Â€Â˜Logical diagramsÃ¢Â€Â™, is intended to be a useful learning and testing tool for the beginner programmer, but also for the more experienced one. The problem this application is trying to solve concerns young programmers who forget about the fundamentals of this domain, algorithmic. Logical diagrams are a graphic representation of an algorithm, which uses different geometrical figures (parallelograms, rectangles, rhombuses, circles with particular meaning that are called blocks and connected between them to reveal the flow of the algorithm. The role of this application is to help the user build the diagram for the algorithm and then automatically generate the C code and test it.
an algorithm for an algorithm for the design the design the design of ...
African Journals Online (AJOL)
eobe
1, 2, 3DEPARTMENT OF MECHANICAL ENGINEERING, UNIVERSITY OF BENIN, BENIN CITY. ... focuses on the development of an algorithm for designing an axial flow compressor for ...... Optimization of Axial Flow Compressor Blades with.
Very Large Scale Integration (VLSI).
Yeaman, Andrew R. J.
Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…
Toward human-centered algorithm design
Directory of Open Access Journals (Sweden)
Eric PS Baumer
2017-07-01
Full Text Available As algorithms pervade numerous facets of daily life, they are incorporated into systems for increasingly diverse purposes. These systems’ results are often interpreted differently by the designers who created them than by the lay persons who interact with them. This paper offers a proposal for human-centered algorithm design, which incorporates human and social interpretations into the design process for algorithmically based systems. It articulates three specific strategies for doing so: theoretical, participatory, and speculative. Drawing on the author’s work designing and deploying multiple related systems, the paper provides a detailed example of using a theoretical approach. It also discusses findings pertinent to participatory and speculative design approaches. The paper addresses both strengths and challenges for each strategy in helping to center the process of designing algorithmically based systems around humans.
Aljada, Muhsen; Hwang, Seow; Alameh, Kamal
2008-01-21
In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.
Fashion sketch design by interactive genetic algorithms
Mok, P. Y.; Wang, X. X.; Xu, J.; Kwok, Y. L.
2012-11-01
Computer aided design is vitally important for the modern industry, particularly for the creative industry. Fashion industry faced intensive challenges to shorten the product development process. In this paper, a methodology is proposed for sketch design based on interactive genetic algorithms. The sketch design system consists of a sketch design model, a database and a multi-stage sketch design engine. First, a sketch design model is developed based on the knowledge of fashion design to describe fashion product characteristics by using parameters. Second, a database is built based on the proposed sketch design model to define general style elements. Third, a multi-stage sketch design engine is used to construct the design. Moreover, an interactive genetic algorithm (IGA) is used to accelerate the sketch design process. The experimental results have demonstrated that the proposed method is effective in helping laypersons achieve satisfied fashion design sketches.
An Incremental Approach to Automatic Algorithm Design
Institute of Scientific and Technical Information of China (English)
LUAN Shangmin; LI Wei
1999-01-01
This paper presents an incrementalapproach to automatic algorithm design, which can be described byalgebraic specifications precisely and conveniently. The definitions ofselection operator and extension operator which can be defined bystrategy relations and transformations are given in order to model theprocess of finding the solution of a problem. Also discussed is itsobject-oriented implementation. The functional specification and thedesign specification for an algorithm are given in one framework so thatthe correctness of the algorithm can be easily proved.
超大规模集成电路可调试性设计综述%Survey of Design-for-Debug of VLSI
Institute of Scientific and Technical Information of China (English)
钱诚; 沈海华; 陈天石; 陈云霁
2012-01-01
随着硬件复杂度的不断提高和并行软件调试的需求不断增长,可调试性设计已经成为集成电路设计中的重要内容.一方面,仅靠传统的硅前验证已经无法保证现代超大规模复杂集成电路设计验证的质量,因此作为硅后验证重要支撑技术的可调试性设计日渐成为大规模集成电路设计领域的研究热点.另一方面,并行程序的调试非常困难,很多细微的bug无法直接用传统的单步、断点等方法进行调试,如果没有专门的硬件支持,需要耗费极大的人力和物力.全面分析了现有的可调试性设计,在此基础上归纳总结了可调试性设计技术的主要研究方向并介绍了各个方向的研究进展,深入探讨了可调试性结构设计研究中的热点问题及其产生根源,给出了可调试性结构设计领域的发展趋势.%Design-for-debug (DFD) has become an important feature of modern VLSI. On the one hand, traditional pre-silicon verification methods are not sufficient to enssure the quality of modern complex VLSI designs, thus employing DFD to facilitate post-silicon verification has attracted wide interests from both academia and industry; on the other hand, debugging parallel program is a worldwide difficult problem, which cries out for DFD hardware supports. In this paper, we analyze the existing structures of DFD comprehensively and introduce different fields of DFD for debugging hardware and software. These fields contain various kinds of DFD infrastructures, such as the DFD infrastructure for the pipe line of processor, the system-on-chips (SOC) and the networks on multi-cores processor. We also introduce the recent researches on how to design the DFD infrastructures with certain processor architecture and how to use the DFD infrastructures to solve the debug problems in these different fields. The topologic of the whole infrastructure, the hardware design of components, the methods of analyzing signals, the
Design tool for wind turbine control algorithms
Energy Technology Data Exchange (ETDEWEB)
Van der Hooft, E.L.; Van Engelen, T.G.; Schaak, P.; Wiggelinkhuizen, E.J. [ECN Wind Energy, Petten (Netherlands)
2004-11-01
Advanced wind turbine control algorithms have become more important over the last years in order to deal with high requirements on reliability, cost of energy and extreme operating (offshore) conditions. An open source modular 'Design tool for wind turbine control algorithms' within the Matlab environment enables possibilities for wind turbine designers to develop industrial control algorithms and to utilize the benefits of more advanced control solutions. The design tool offers a proven design procedure, which takes the different design stages of a wind turbine into account. It supports initial design and evaluation of control algorithms, linking to aero-elastic codes and implementation in the turbine controller. In addition, the tool assists the designer to operate the design procedure, to avoid design failures and ordering of all the design data, models and versions. Currently, the incorporated design and evaluation models are focussed on design of classic 'rotor speed feedback control' for a variable speed and active pitch turbine and have been verified in practice. More advanced control design modules are within reach as a result of current developments on frequency domain analysis and synthesis of (linearised) turbine models.
Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney
2006-01-01
We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.
VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Li, Kang; Yu, Juebang; Li, Jian
In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
A Topological Model for Parallel Algorithm Design
1991-09-01
New York, 1989. 108. J. Dugundji . Topology . Allen and Bacon, Rockleigh, NJ, 1966. 109. R. Duncan. A Survey of Parallel Computer Architectures. IEEE...Approved for public release; distribition unlimited 4N1f-e AFIT/DS/ENG/91-02 A TOPOLOGICAL MODEL FOR PARALLEL ALGORITHM DESIGN DISSERTATION Presented to...DC 20503. 4. TITLE AND SUBTITLE 5. FUNDING NUMBERS A Topological Model For Parallel Algorithm Design 6. AUTHOR(S) Jeffrey A Simmers, Captain, USAF 7
Heuristic Algorithm in Optimal Discrete Structural Designs
Directory of Open Access Journals (Sweden)
Alongkorn Lamom
2008-01-01
Full Text Available This study proposes a Heuristic Algorithm for Material Size Selection (HAMSS. It is developed to handle discrete structural optimization problems. The proposed algorithm (HAMSS, Simulated Annealing Algorithm (SA and the conventional design algorithm obtained from a structural steel design software are studied with three selected examples. The HAMSS, in fact, is the adaptation from the traditional SA. Although the SA is one of the easiest optimization algorithms available, a huge number of function evaluations deter its use in structural optimizations. To obtain the optimum answers by the SA, possible answers are first generated randomly. Many of these possible answers are rejected because they do not pass the constraints. To effectively handle this problem, the behavior of optimal structural design problems is incorporated into the algorithm. The new proposed algorithm is called the HAMSS. The efficiency comparison between the SA and the HAMSS is illustrated in term of number of finite element analysis cycles. Results from the study show that HAMSS can significantly reduce the number of structural analysis cycles while the optimized efficiency is not different.
Genetic algorithms in computer aided inductor design
Jean Fivaz; Willem A. Cronjé
2004-01-01
The goal of this investigation is to determine the advantages of using genetic algorithms in computer-aided design as applied to inductors. These advantages are exploited in design problems with a number of specifications and constraints, as encountered in power electronics during practical inductor design. The design tool should be able to select components, such as cores and wires, from databases of available components, and evaluate these choices based on the components’ characteristic d...
Algebraic Algorithm Design and Local Search
1996-12-01
clearly illustrate that casting algorithm design into an algebraic framework brings a lot of theoretical and practical knowledge to bear on the problem ...makes defining a suitable crossover operator easier. In (47), however, the traveling salesman problem was solved using a genetic algorithm with a... Knapsack and other 0-1 integer programs can be approached with this neighborhood. Problems where a subset of a particular size is desired can be
An efficient interpolation filter VLSI architecture for HEVC standard
Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang
2015-12-01
The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.
VLSI binary multiplier using residue number systems
Energy Technology Data Exchange (ETDEWEB)
Barsi, F.; Di Cola, A.
1982-01-01
The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.
Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W
1999-01-01
We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).
Fast Fourier Transform algorithm design and tradeoffs
Kamin, Ray A., III; Adams, George B., III
1988-01-01
The Fast Fourier Transform (FFT) is a mainstay of certain numerical techniques for solving fluid dynamics problems. The Connection Machine CM-2 is the target for an investigation into the design of multidimensional Single Instruction Stream/Multiple Data (SIMD) parallel FFT algorithms for high performance. Critical algorithm design issues are discussed, necessary machine performance measurements are identified and made, and the performance of the developed FFT programs are measured. Fast Fourier Transform programs are compared to the currently best Cray-2 FFT program.
Genetic algorithms in computer aided inductor design
Directory of Open Access Journals (Sweden)
Jean Fivaz
2004-09-01
Full Text Available The goal of this investigation is to determine the advantages of using genetic algorithms in computer-aided design as applied to inductors. These advantages are exploited in design problems with a number of specifications and constraints, as encountered in power electronics during practical inductor design. The design tool should be able to select components, such as cores and wires, from databases of available components, and evaluate these choices based on the components’ characteristic data read from a database of manufacturers’ data-sheets. The proposed design must always be practically realizable, as close to the desired specifications as possible and within any specified constraints.
Directory of Open Access Journals (Sweden)
Adhiyaman P1 ,
2014-03-01
Full Text Available In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF and a novel embedded logic module (DDFF-ELM based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.
Algorithms, architectures and information systems security
Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya
2008-01-01
This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin
A radial basis function neurocomputer implemented with analog VLSI circuits
Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul
1992-01-01
An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.
Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)
Institute of Scientific and Technical Information of China (English)
周涛; 吴行军; 白国强; 陈弘毅
2003-01-01
Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.
Kudoh, Takao; Kameyama, Michitaka
One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.
Design of hyperbolic metamaterials by genetic algorithm
Goforth, Ian A.; Alisafaee, Hossein; Fullager, Daniel B.; Rosenbury, Chris; Fiddy, Michael A.
2014-09-01
We explain the design of one dimensional Hyperbolic Metamaterials (HMM) using a genetic algorithm (GA) and provide sample applications including the realization of negative refraction. The design method is a powerful optimization approach to find the optimal performance of such structures, which "naturally" finds HMM structures that are globally optimized for specific applications. We explain how a fitness function can be incorporated into the GA for different metamaterial properties.
VLSI Circuits for High Speed Data Conversion
1994-05-16
Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp
An Analog VLSI Saccadic Eye Movement System
1994-01-01
In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...
A multi coding technique to reduce transition activity in VLSI circuits
Vithyalakshmi, N.; Rajaram, M.
2014-02-01
Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.
Synaptic dynamics in analog VLSI.
Bartolozzi, Chiara; Indiveri, Giacomo
2007-10-01
Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.
VLSI circuits for high speed data conversion
Wooley, Bruce A.
1994-05-01
The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.
Multi-net optimization of VLSI interconnect
Moiseev, Konstantin; Wimer, Shmuel
2015-01-01
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...
Models and Algorithm for Stochastic Network Designs
Institute of Scientific and Technical Information of China (English)
Anthony Chen; Juyoung Kim; Seungjae Lee; Jaisung Choi
2009-01-01
The network design problem (NDP) is one of the most difficult and challenging problems in trans-portation. Traditional NDP models are often posed as a deterministic bilevel program assuming that all rele-vant inputs are known with certainty. This paper presents three stochastic models for designing transporta-tion networks with demand uncertainty. These three stochastic NDP models were formulated as the ex-pected value model, chance-constrained model, and dependent-chance model in a bilevel programming framework using different criteria to hedge against demand uncertainty. Solution procedures based on the traffic assignment algorithm, genetic algorithm, and Monte-Cado simulations were developed to solve these stochastic NDP models. The nonlinear and nonconvex nature of the bilevel program was handled by the genetic algorithm and traffic assignment algorithm, whereas the stochastic nature was addressed through simulations. Numerical experiments were conducted to evaluate the applicability of the stochastic NDP models and the solution procedure. Results from the three experiments show that the solution procedures are quite robust to different parameter settings.
CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation
Directory of Open Access Journals (Sweden)
Hussein CHIBLE,
2013-10-01
Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented
Designing quantum gates using the genetic algorithm
Kumar, Karthikeyan S.; Paraoanu, G. S.
2012-12-01
We demonstrate the usage of Genetic Algorithm (GA) to tailor the radio frequency pulses for producing unitary transformations in qubit systems. We find that the initial population converges to the optimal solution after 10 generations, for a one segment pulse corresponding to single qubit Hadamard gate. For a two qubit CNOT gate, we see the population convergence for a two segment pulse after 150 generations. This demonstrates that the method is suitable for designing quantum gates.
Parallel Algorithm Design on Some Distributed Systems
Institute of Scientific and Technical Information of China (English)
孙家昶; 张林波; 等
1997-01-01
Some testing results on DAWINING-1000,Paragon and workstation cluster are described in this paper.On the home-made parallel system DAWNING-1000 with 32 computational processors,the practical performance of 1.1777 Gflops and 1.58 Gflops has been measured in solving a dense linear system and doing matrix multiplication,respectively .The scalability is also investigated.The importance of designing efficient parallel algorithms for evaluating parallel systems is emphasized.
A Method of Neural Network Controller Implementation in VLSI Design%将神经网络控制器用于VLSI设计的方法研究
Institute of Scientific and Technical Information of China (English)
詹璨铭
2015-01-01
This article presents an approach to neural network implementation in VLSI ,which is called as neural network controller based on Petri net .The structure of the neurons in the network is uniform ;it is triggered by external events ,and output place and transition signals of petri net .Two types of neurons are introduced ,one is standing for serial process ,and the other is used in synchronization of processes .The dual types of neurons are chained together by stimulate inputs ,and compose the fabric .The controller is designed to conquer the side effects of state machine ,and improves the performance and reliability .Typically ,the controller is a precise description of the circuits .It is optimized to timing closure against constraints much easier than state machine .Reduplication of each node in neural network decrease single event upset (SEU) .Finally ,the controller is easy to rebuild .The new design flow has applied in practice ,and proved effectively .%探索在超大规模集成电路中应用神经网络控制器的方法．根据Petri网理论，将库所与变迁组合成神经节点，节点通过输入触发信号链接组成复杂控制网络．定义两种类型神经节点，一种是节点组成串行分枝，另外一种用于同步并发分枝．通过两种节点组合，形成三种基本网络结构，三种结构再次组合又可形成任意复杂控制器结构．根据控制器分枝内串行、分枝间并行的特点，设计编译软件，输入更抽象的分枝描述代码，自动生成对应神经网络控制器逻辑电路描述代码．VLSI设计中使用神经网络控制器，能够更接近了寄存器传输级电路，以及更精确地描述电路，还能提高设计性能与可靠性．复制神经节点减小单节点负载，可优化电路时序；复制节点还可构成冗余缓解空间单粒子翻转．神经网络控制器可以处理各种异常情况，提高功能容错性和可维护性．这种方法已经用
A Generic Design Model for Evolutionary Algorithms
Institute of Scientific and Technical Information of China (English)
He Feng; Kang Li-shan; Chen Yu-ping
2003-01-01
A generic design model for evolutionary algo rithms is proposed in this paper. The model, which was described by UML in details, focuses on the key concepts and mechanisms in evolutionary algorithms. The model not only achieves separation of concerns and encapsulation of implementations by classification and abstraction of those concepts,it also has a flexible architecture due to the application of design patterns. As a result, the model is reusable, extendible,easy to understand, easy to use, and easy to test. A large number of experiments applying the model to solve many different problems adequately illustrate the generality and effectivity of the model.
A Coherent VLSI Design Environment
1987-12-31
April 1, L0 A Mastiplexd Switched-Capacitor Filter Bank, Patrick Bosshart, MIT April 8, IM Analog Circuits in DOS PSI, Yannis Tsividis , Columbia...A.I. (Analog Intelligence), Yanni Tsividis , Columbia University, New York, NY December 2,1986 The Semiconductor Industry (Losing Sight of Your Added...Dept. of Elec. Eng. & Comp. Sci. 3:50 Yannis Tsividis and Dimitri A. Antoniadis, "A Mulitproject Chip i Approach to the Teaching of Analog MOS LSI and
A Coherent VLSI Design Environment.
1985-09-30
85-257, September, 1985. e b . . B% V" 4 pathway in bipolar logic. ii) finding a rational and easily automated method for modeling the driving-point...where the resistors are fixed, there is no internodal coupling capacitance, the pullup and pulldown networks have no internal capacitance, and the
A Coherent VLSI Design Environment.
2014-09-26
physical devices from which physical circuits are fabricated. By analogy with context-free languages , a class of circuits is generated by a phrase-structure... language called CLU [131. It consists of SPICE interface, minimization, and matrix manipulation program modules. These modules contain 3200, 1800, and...greatly simplify the optimization problem. They reformulated the original problem, a minimization subject to nonlinear constraints, as an
Hybrid VLSI/QCA Architecture for Computing FFTs
Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew
2003-01-01
A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.
Predicting Resistance Mutations Using Protein Design Algorithms
Energy Technology Data Exchange (ETDEWEB)
Frey, K.; Georgiev, I; Donald, B; Anderson, A
2010-01-01
Drug resistance resulting from mutations to the target is an unfortunate common phenomenon that limits the lifetime of many of the most successful drugs. In contrast to the investigation of mutations after clinical exposure, it would be powerful to be able to incorporate strategies early in the development process to predict and overcome the effects of possible resistance mutations. Here we present a unique prospective application of an ensemble-based protein design algorithm, K*, to predict potential resistance mutations in dihydrofolate reductase from Staphylococcus aureus using positive design to maintain catalytic function and negative design to interfere with binding of a lead inhibitor. Enzyme inhibition assays show that three of the four highly-ranked predicted mutants are active yet display lower affinity (18-, 9-, and 13-fold) for the inhibitor. A crystal structure of the top-ranked mutant enzyme validates the predicted conformations of the mutated residues and the structural basis of the loss of potency. The use of protein design algorithms to predict resistance mutations could be incorporated in a lead design strategy against any target that is susceptible to mutational resistance.
VLSI mixed signal processing system
Alvarez, A.; Premkumar, A. B.
1993-01-01
An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.
Fundamentals of Microelectronics Processing (VLSI).
Takoudis, Christos G.
1987-01-01
Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)
Fast search algorithms for computational protein design.
Traoré, Seydou; Roberts, Kyle E; Allouche, David; Donald, Bruce R; André, Isabelle; Schiex, Thomas; Barbe, Sophie
2016-05-01
One of the main challenges in computational protein design (CPD) is the huge size of the protein sequence and conformational space that has to be computationally explored. Recently, we showed that state-of-the-art combinatorial optimization technologies based on Cost Function Network (CFN) processing allow speeding up provable rigid backbone protein design methods by several orders of magnitudes. Building up on this, we improved and injected CFN technology into the well-established CPD package Osprey to allow all Osprey CPD algorithms to benefit from associated speedups. Because Osprey fundamentally relies on the ability of A* to produce conformations in increasing order of energy, we defined new A* strategies combining CFN lower bounds, with new side-chain positioning-based branching scheme. Beyond the speedups obtained in the new A*-CFN combination, this novel branching scheme enables a much faster enumeration of suboptimal sequences, far beyond what is reachable without it. Together with the immediate and important speedups provided by CFN technology, these developments directly benefit to all the algorithms that previously relied on the DEE/ A* combination inside Osprey* and make it possible to solve larger CPD problems with provable algorithms.
Automatic Circuit Design and Optimization Using Modified PSO Algorithm
Directory of Open Access Journals (Sweden)
Subhash Patel
2016-04-01
Full Text Available In this work, we have proposed modified PSO algorithm based optimizer for automatic circuit design. The performance of the modified PSO algorithm is compared with two other evolutionary algorithms namely ABC algorithm and standard PSO algorithm by designing two stage CMOS operational amplifier and bulk driven OTA in 130nm technology. The results show the robustness of the proposed algorithm. With modified PSO algorithm, the average design error for two stage op-amp is only 0.054% in contrast to 3.04% for standard PSO algorithm and 5.45% for ABC algorithm. For bulk driven OTA, average design error is 1.32% with MPSO compared to 4.70% with ABC algorithm and 5.63% with standard PSO algorithm.
EGNAS: an exhaustive DNA sequence design algorithm
Directory of Open Access Journals (Sweden)
Kick Alfred
2012-06-01
Full Text Available Abstract Background The molecular recognition based on the complementary base pairing of deoxyribonucleic acid (DNA is the fundamental principle in the fields of genetics, DNA nanotechnology and DNA computing. We present an exhaustive DNA sequence design algorithm that allows to generate sets containing a maximum number of sequences with defined properties. EGNAS (Exhaustive Generation of Nucleic Acid Sequences offers the possibility of controlling both interstrand and intrastrand properties. The guanine-cytosine content can be adjusted. Sequences can be forced to start and end with guanine or cytosine. This option reduces the risk of “fraying” of DNA strands. It is possible to limit cross hybridizations of a defined length, and to adjust the uniqueness of sequences. Self-complementarity and hairpin structures of certain length can be avoided. Sequences and subsequences can optionally be forbidden. Furthermore, sequences can be designed to have minimum interactions with predefined strands and neighboring sequences. Results The algorithm is realized in a C++ program. TAG sequences can be generated and combined with primers for single-base extension reactions, which were described for multiplexed genotyping of single nucleotide polymorphisms. Thereby, possible foldback through intrastrand interaction of TAG-primer pairs can be limited. The design of sequences for specific attachment of molecular constructs to DNA origami is presented. Conclusions We developed a new software tool called EGNAS for the design of unique nucleic acid sequences. The presented exhaustive algorithm allows to generate greater sets of sequences than with previous software and equal constraints. EGNAS is freely available for noncommercial use at http://www.chm.tu-dresden.de/pc6/EGNAS.
Institute of Scientific and Technical Information of China (English)
潘志鹏; 吴斌; 尉志伟; 叶甜春
2015-01-01
针对IEEE 802.11i协议中多种安全协议实现进行研究,结合以IEEE 802.11ac协议为代表的下一代无线局域网( WLAN)系统对高吞吐率的需求,提出了一种支持WEP/TKIP/CCMP协议的多模、高速安全加速引擎的大规模集成电路( VLSI)架构. 提出了基于哈希算法的密钥信息查找算法,缩小了查找时钟延迟. 基于复合域的运算方式实现高级加密标准( AES)算法,提出双AES运算核的并行架构实现计数器与密码分组链接( CCM)模式,提升运算吞吐率的同时也降低了引擎的响应延迟. 经过FPGA实现和ASIC流片验证表明,该安全加速引擎具备可重构性,处理延迟仅为33个时钟周期,在322 MHz工作频率下运算吞吐率可达3.747 Gbit/s.%In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration ( VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP proto-cols was presented taking into account the demand for high throughput of the next generation wireless local area net-work ( WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryp-tion standard ( AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code ( CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz.
用于混合信号VLSI的可扩展JTAG控制器IP核设计%Design of Extendable JTAG Controller IP Core for Mixed-signal VLSI
Institute of Scientific and Technical Information of China (English)
段延亮; 魏廷存; 高武; 许望洋
2012-01-01
The front-end read-out circuit for Positron Emission Tomography（PET） imaging system is a kind of digital-analog mixed-signal VLSI.Based on the features of multi-channel and high performances of these kinds of chip,the JTAG controller is adopted to realize the initial control and auxiliary test of the chip.An extendable JTAG controller IP core is designed using TSMC 0.18 μm CMOS process,which supports 14 groups of extendable control signal and also supports the reading and writing operations of 16 multi-bits registers scan chains,and joins with the customized substrate driving software.The designed JTAG controller IP core can be also used for the controlling and testing of other mixed-signal VLSI,and has good universality and engineering usage.%正电子发射断层成像系统（PET）前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值.
Algorithm design of liquid lens inspection system
Hsieh, Lu-Lin; Wang, Chun-Chieh
2008-08-01
In mobile lens domain, the glass lens is often to be applied in high-resolution requirement situation; but the glass zoom lens needs to be collocated with movable machinery and voice-coil motor, which usually arises some space limits in minimum design. In high level molding component technology development, the appearance of liquid lens has become the focus of mobile phone and digital camera companies. The liquid lens sets with solid optical lens and driving circuit has replaced the original components. As a result, the volume requirement is decreased to merely 50% of the original design. Besides, with the high focus adjusting speed, low energy requirement, high durability, and low-cost manufacturing process, the liquid lens shows advantages in the competitive market. In the past, authors only need to inspect the scrape defect made by external force for the glass lens. As to the liquid lens, authors need to inspect the state of four different structural layers due to the different design and structure. In this paper, authors apply machine vision and digital image processing technology to administer inspections in the particular layer according to the needs of users. According to our experiment results, the algorithm proposed can automatically delete non-focus background, extract the region of interest, find out and analyze the defects efficiently in the particular layer. In the future, authors will combine the algorithm of the system with automatic-focus technology to implement the inside inspection based on the product inspective demands.
1987-06-01
The chief advantage of conventional HDLs is a common language supports multi-level executable specifications familiarity and wide-spread use of...by function iucsa 1985. which is zero. The maximum clock rate of multiopadder is 34 [8- ] Frankel, P. E. aid S. W. Smoiar. "Beyond Register Tramaes
VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION
Directory of Open Access Journals (Sweden)
John Moses C
2014-05-01
Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.
UWB Tracking System Design with TDOA Algorithm
Ni, Jianjun; Arndt, Dickey; Ngo, Phong; Phan, Chau; Gross, Julia; Dusl, John; Schwing, Alan
2006-01-01
This presentation discusses an ultra-wideband (UWB) tracking system design effort using a tracking algorithm TDOA (Time Difference of Arrival). UWB technology is exploited to implement the tracking system due to its properties, such as high data rate, fine time resolution, and low power spectral density. A system design using commercially available UWB products is proposed. A two-stage weighted least square method is chosen to solve the TDOA non-linear equations. Matlab simulations in both two-dimensional space and three-dimensional space show that the tracking algorithm can achieve fine tracking resolution with low noise TDOA data. The error analysis reveals various ways to improve the tracking resolution. Lab experiments demonstrate the UWBTDOA tracking capability with fine resolution. This research effort is motivated by a prototype development project Mini-AERCam (Autonomous Extra-vehicular Robotic Camera), a free-flying video camera system under development at NASA Johnson Space Center for aid in surveillance around the International Space Station (ISS).
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
LIU; Yanpei(
2001-01-01
［1］Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.［2］Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.［3］Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.［4］Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.［5］Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.［6］Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.［7］Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.［8］Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.［9］Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.［10］Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.［11］Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.［12］Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.［13］Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.
Analog VLSI neural network integrated circuits
Kub, F. J.; Moon, K. K.; Just, E. A.
1991-01-01
Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.
Relaxation Based Electrical Simulation for VLSI Circuits
Directory of Open Access Journals (Sweden)
S. Rajkumar
2012-06-01
Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.
Trace-based post-silicon validation for VLSI circuits
Liu, Xiao
2014-01-01
This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...
A Contraction-based Ratio-cut Partitioning Algorithm
Directory of Open Access Journals (Sweden)
Youssef Saab
2002-01-01
Full Text Available Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, ratio-cut partitioning has received attention due to its tendency to partition circuits into their natural clusters. Node contraction has also been shown to enhance the performance of iterative partitioning algorithms. This paper describes a new simple ratio-cut partitioning algorithm using node contraction. This new algorithm combines iterative improvement with progressive cluster formation. Under suitably mild assumptions, the new algorithm runs in linear time. It is also shown that the new algorithm compares favorably with previous approaches.
Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
Directory of Open Access Journals (Sweden)
HOO, C.-S.
2013-02-01
Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.
A genetic algorithm for solving supply chain network design model
Firoozi, Z.; Ismail, N.; Ariafar, S. H.; Tang, S. H.; Ariffin, M. K. M. A.
2013-09-01
Network design is by nature costly and optimization models play significant role in reducing the unnecessary cost components of a distribution network. This study proposes a genetic algorithm to solve a distribution network design model. The structure of the chromosome in the proposed algorithm is defined in a novel way that in addition to producing feasible solutions, it also reduces the computational complexity of the algorithm. Computational results are presented to show the algorithm performance.
VLSI circuits for bidirectional interface to peripheral and visceral nerves.
Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V
2015-08-01
This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.
Design and Implementation of Bidirectional Dijkstra Algorithm
Institute of Scientific and Technical Information of China (English)
付梦印; 李杰; 周培德
2003-01-01
Bidirectional Dijkstra algorithm whose time complexity is (1)/(8)O(n2) is proposed. The theory foundation is that the classical Dijkstra algorithm has not any directional feature during searching the shortest path. The algorithm takes advantage of the adjacent link and the mechanism of bidirectional search, that is, the algorithm processes the positive search from start point to destination point and the negative search from destination point to start point at the same time. Finally, combining with the practical application of route-planning algorithm in embedded real-time vehicle navigation system (ERTVNS), one example of its practical applications is given, analysis in theory and the experimental results show that compared with the Dijkstra algorithm, the new algorithm can reduce time complexity, and guarantee the searching precision, it satisfies the needs of ERTVNS.
Approach of generating parallel programs from parallelized algorithm design strategies
Institute of Scientific and Technical Information of China (English)
WAN Jian-yi; LI Xiao-ying
2008-01-01
Today, parallel programming is dominated by message passing libraries, such as message passing interface (MPI). This article intends to simplify parallel programming by generating parallel programs from parallelized algorithm design strategies. It uses skeletons to abstract parallelized algorithm design strategies, as well as parallel architectures. Starting from problem specification, an abstract parallel abstract programming language+ (Apla+) program is generated from parallelized algorithm design strategies and problem-specific function definitions. By combining with parallel architectures, implicity of parallelism inside the parallelized algorithm design strategies is exploited. With implementation and transformation, C++ and parallel virtual machine (CPPVM) parallel program is finally generated. Parallelized branch and bound (B&B) algorithm design strategy and parallelized divide and conquer (D & C) algorithm design strategy are studied in this article as examples. And it also illustrates the approach with a case study.
A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.
Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang
2016-12-07
The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.
A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search
Directory of Open Access Journals (Sweden)
Yuan-Jyun Chang
2016-12-01
Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.
Analog Module Placement Design Using Genetic Algorithm
Institute of Scientific and Technical Information of China (English)
无
2003-01-01
This paper presents a novel genetic algorithm for analog module placement based on ageneralization of the two-dimensional bin packing problem. The genetic encoding and operators assure that allproblem constraints are always satisfied. Thus the potential problems of adding penalty terms to the costfunction are eliminated so that the search configuration space is drastically decreased. The dedicated costfunction is based on the special requirements of analog integrated circuits. A fractional factorial experimentwas conducted using an orthogonal array to study the algorithm parameters. A meta GA was applied todetermine the optimal parameter values. The algorithm was tested with several local benchmark circuits. Theexperimental results show that the algorithm has better performance than the simulated annealing approachwith satisfactory results comparable to manual placement. This study demonstrates the effectiveness of thegenetic algorithm in the analog module placement problem. The algorithm has been successfully used in alayout synthesis tool.
New Combustion CFD Algorithms Designed for Rapid GPU Computations Project
National Aeronautics and Space Administration — We propose development of new algorithms specifically designed to exploit the highly parallel structure of graphics processing units (GPUs) for performing the...
Analog Circuit Design Optimization Based on Evolutionary Algorithms
Directory of Open Access Journals (Sweden)
Mansour Barari
2014-01-01
Full Text Available This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs. Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.
Configurable intelligent optimization algorithm design and practice in manufacturing
Tao, Fei; Laili, Yuanjun
2014-01-01
Presenting the concept and design and implementation of configurable intelligent optimization algorithms in manufacturing systems, this book provides a new configuration method to optimize manufacturing processes. It provides a comprehensive elaboration of basic intelligent optimization algorithms, and demonstrates how their improvement, hybridization and parallelization can be applied to manufacturing. Furthermore, various applications of these intelligent optimization algorithms are exemplified in detail, chapter by chapter. The intelligent optimization algorithm is not just a single algorit
Surface and interface effects in VLSI
Einspruch, Norman G
1985-01-01
VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import
VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER
Directory of Open Access Journals (Sweden)
Joseph Gladwin Sekar
2013-01-01
Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.
Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks
Aggarwal, Supriya; Khare, Kavita
2012-11-01
This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.
1987-03-31
smallest and largest eigenvalues of YH and AminAH and Am,..AH represent the smallest and largest eigenvalues of YAH, respectively. Fig. 3b illustrates a...101, Princeton U. Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International
A New Design of Clock Synchronization Algorithm
Directory of Open Access Journals (Sweden)
Jingmeng Liu
2014-05-01
Full Text Available The introduction of Ethernet makes the distributed network system more flexible and efficient, but it also makes nodes which are far apart from each other unable to work in the same time basis due to the long distance. This is not allowed for the high performance requirements of the system synchronization, such as high-precision multiaxis machining system. This paper presents a high-precision network clock synchronization algorithm, namely, optimal PI clock servo, which imposes a PI controller in order to compensate for the clock drift of each network node. Then a simulation platform established by the toolbox TrueTime is used to verify the stability of the algorithm and compare it with the clock synchronization algorithm of EtherCAT. The results show that the new synchronization algorithm has higher synchronization precision and faster convergence rate.
Space mapping optimization algorithms for engineering design
DEFF Research Database (Denmark)
Koziel, Slawomir; Bandler, John W.; Madsen, Kaj
2006-01-01
A simple, efficient optimization algorithm based on space mapping (SM) is presented. It utilizes input SM to reduce the misalignment between the coarse and fine models of the optimized object over a region of interest, and output space mapping (OSM) to ensure matching of response and first......-order derivatives between the mapped coarse model and the fine model at the current iteration point. We also consider an enhanced version in which the input SM coefficients are frequency dependent. The performance of our new algorithms is comparable with the recently published SMIS algorithm when applied...... to a benchmark problem. In comparison with SMIS, the models presented are simple and have a small number of parameters that need to be extracted. The new algorithm is applied to the optimization of coupled-line band-pass filter....
Optimal Pid Controller Design Using Adaptive Vurpso Algorithm
Zirkohi, Majid Moradi
2015-04-01
The purpose of this paper is to improve theVelocity Update Relaxation Particle Swarm Optimization algorithm (VURPSO). The improved algorithm is called Adaptive VURPSO (AVURPSO) algorithm. Then, an optimal design of a Proportional-Integral-Derivative (PID) controller is obtained using the AVURPSO algorithm. An adaptive momentum factor is used to regulate a trade-off between the global and the local exploration abilities in the proposed algorithm. This operation helps the system to reach the optimal solution quickly and saves the computation time. Comparisons on the optimal PID controller design confirm the superiority of AVURPSO algorithm to the optimization algorithms mentioned in this paper namely the VURPSO algorithm, the Ant Colony algorithm, and the conventional approach. Comparisons on the speed of convergence confirm that the proposed algorithm has a faster convergence in a less computation time to yield a global optimum value. The proposed AVURPSO can be used in the diverse areas of optimization problems such as industrial planning, resource allocation, scheduling, decision making, pattern recognition and machine learning. The proposed AVURPSO algorithm is efficiently used to design an optimal PID controller.
FaSa: A Fast and Stable Quadratic Placement Algorithm
Institute of Scientific and Technical Information of China (English)
HOU WenTing(侯文婷); HONG XianLong(洪先龙); WU WeiMin(吴为民); CAI YiCi(蔡懿慈)
2003-01-01
Placement is a critical step in VLSI design because it dominates overall speed andquality of design flow. In this paper, a new fast and stable placement algorithm called FaSa is pro-posed. It uses quadratic programming model and Lagrange multiplier method to solve placementproblems. And an incremental LU factorization method is used to solve equations for speeding up.The experimental results show that FaSa is very stable, much faster than previous algorithms andits total wire length is comparable with other algorithms.
Advances in metaheuristic algorithms for optimal design of structures
Kaveh, A
2014-01-01
This book presents efficient metaheuristic algorithms for optimal design of structures. Many of these algorithms are developed by the author and his colleagues, consisting of Democratic Particle Swarm Optimization, Charged System Search, Magnetic Charged System Search, Field of Forces Optimization, Dolphin Echolocation Optimization, Colliding Bodies Optimization, Ray Optimization. These are presented together with algorithms which were developed by other authors and have been successfully applied to various optimization problems. These consist of Particle Swarm Optimization, Big Bang-Big Crunch Algorithm, Cuckoo Search Optimization, Imperialist Competitive Algorithm, and Chaos Embedded Metaheuristic Algorithms. Finally a multi-objective optimization method is presented to solve large-scale structural problems based on the Charged System Search algorithm. The concepts and algorithms presented in this book are not only applicable to optimization of skeletal structures and finite element models, but can equally ...
Advances in metaheuristic algorithms for optimal design of structures
Kaveh, A
2017-01-01
This book presents efficient metaheuristic algorithms for optimal design of structures. Many of these algorithms are developed by the author and his colleagues, consisting of Democratic Particle Swarm Optimization, Charged System Search, Magnetic Charged System Search, Field of Forces Optimization, Dolphin Echolocation Optimization, Colliding Bodies Optimization, Ray Optimization. These are presented together with algorithms which were developed by other authors and have been successfully applied to various optimization problems. These consist of Particle Swarm Optimization, Big Bang-Big Crunch Algorithm, Cuckoo Search Optimization, Imperialist Competitive Algorithm, and Chaos Embedded Metaheuristic Algorithms. Finally a multi-objective optimization method is presented to solve large-scale structural problems based on the Charged System Search algorithm. The concepts and algorithms presented in this book are not only applicable to optimization of skeletal structures and finite element models, but can equally ...
Towards Automatic Controller Design using Multi-Objective Evolutionary Algorithms
DEFF Research Database (Denmark)
Pedersen, Gerulf
of evolutionary computation, a choice was made to use multi-objective algorithms for the purpose of aiding in automatic controller design. More specifically, the choice was made to use the Non-dominated Sorting Genetic Algorithm II (NSGAII), which is one of the most potent algorithms currently in use......, as the foundation for achieving the desired goal. While working with the algorithm, some issues arose which limited the use of the algorithm for unknown problems. These issues included the relative scale of the used fitness functions and the distribution of solutions on the optimal Pareto front. Some work has...
Aerodynamic Optimum Design of Transonic Turbine Cascades Using Genetic Algorithms
Institute of Scientific and Technical Information of China (English)
无
1997-01-01
This paper presents an aerodynamic optimum design method for transonic turbine cascades based on the Genetic Algorithms coupled to the inviscid flow Euler Solver and the boundary-layer calculation.The Genetic Algorithms control the evolution of a population of cascades towards an optimum design.The fitness value of each string is evaluated using the flow solver.The design procedure has been developed and the behavior of the genetic algorithms has been tested.The objective functions of the design examples are the minimum mean-square deviation between the aimed pressure and computed pressure and the minimum amount of user expertise.
Chemical optimization algorithm for fuzzy controller design
Astudillo, Leslie; Castillo, Oscar
2014-01-01
In this book, a novel optimization method inspired by a paradigm from nature is introduced. The chemical reactions are used as a paradigm to propose an optimization method that simulates these natural processes. The proposed algorithm is described in detail and then a set of typical complex benchmark functions is used to evaluate the performance of the algorithm. Simulation results show that the proposed optimization algorithm can outperform other methods in a set of benchmark functions. This chemical reaction optimization paradigm is also applied to solve the tracking problem for the dynamic model of a unicycle mobile robot by integrating a kinematic and a torque controller based on fuzzy logic theory. Computer simulations are presented confirming that this optimization paradigm is able to outperform other optimization techniques applied to this particular robot application
Algorithmic test design using classical item parameters
van der Linden, Willem J.; Adema, Jos J.
1988-01-01
Two optimalization models for the construction of tests with a maximal value of coefficient alpha are given. Both models have a linear form and can be solved by using a branch-and-bound algorithm. The first model assumes an item bank calibrated under the Rasch model and can be used, for instance, wh
VLSI implementation of a fairness ATM buffer system
DEFF Research Database (Denmark)
Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard
1996-01-01
This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...
Design And Implementation Of Tiny Encryption Algorithm
Directory of Open Access Journals (Sweden)
Kiran Kumar.V.G
2015-06-01
Full Text Available Over the recent years, several smart applications like RFID‟s, sensor networks, including industrial systems, critical infrastructures, private and public spaces as well as portable and wearable applications in which highly constrained devices are interconnected, typically communicating wirelessly with one another, working in concert to accomplish some task. Advanced safety and security mechanisms can be very important in all of these areas. Light weight cryptography enables secure and efficient communication between networked smart objects. This proposed system focuses on the FPGA implementation of light weight cryptographic algorithm Tiny Encryption Algorithm TEA to adapt with many real time constraints such as memory, data loss and low cost. The proposed scheme uses Linear Feedback Shift Register to generate the random key making it more secure for sensitive information transfer in many real-time applications. In this study,operation of this cryptosystem is analyzed by implementing the cryptographic algorithm TEA with the key generation unit in FPGA Spartan 3E. We have also compared the results with the IDEA.
Robust reactor power control system design by genetic algorithm
Energy Technology Data Exchange (ETDEWEB)
Lee, Yoon Joon; Cho, Kyung Ho; Kim, Sin [Cheju National University, Cheju (Korea, Republic of)
1997-12-31
The H{sub {infinity}} robust controller for the reactor power control system is designed by use of the mixed weight sensitivity. The system is configured into the typical two-port model with which the weight functions are augmented. Since the solution depends on the weighting functions and the problem is of nonconvex, the genetic algorithm is used to determine the weighting functions. The cost function applied in the genetic algorithm permits the direct control of the power tracking performances. In addition, the actual operating constraints such as rod velocity and acceleration can be treated as design parameters. Compared with the conventional approach, the controller designed by the genetic algorithm results in the better performances with the realistic constraints. Also, it is found that the genetic algorithm could be used as an effective tool in the robust design. 4 refs., 6 figs. (Author)
A Generic Synthesis Algorithm for Well-Defined Parametric Design
Schotborgh, W.O.; Kokkeler, F.G.M.; Tragter, H.; Bomhoff, M.J.; Houten, van F.J.A.M.
2008-01-01
This paper aims to improve the way synthesis tools can be built by formalizing: 1) the design artefact, 2) related knowledge and 3) an algorithm to generate solutions. This paper focuses on well-defined parametric engineering design, ranging from machine elements to industrial products. A design art
Navigation Constellation Design Using a Multi-Objective Genetic Algorithm
2015-03-26
the mutation and crossover functions specified that certain design parameters be integer values [17]. Equation 21 represents the variables that...been used to force certain design variables to be integer values. Understanding the MATLAB code for the mutation and crossover functions is not...NAVIGATION CONSTELLATION DESIGN USING A MULTI-OBJECTIVE GENETIC ALGORITHM THESIS MARCH 2015
A Parallel Genetic Algorithm for Automated Electronic Circuit Design
Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)
2000-01-01
We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.
Designers' Cognitive Thinking Based on Evolutionary Algorithms
Zhang Shutao; Jianning Su; Chibing Hu; Peng Wang
2013-01-01
The research on cognitive thinking is important to construct the efficient intelligent design systems. But it is difficult to describe the model of cognitive thinking with reasonable mathematical theory. Based on the analysis of design strategy and innovative thinking, we investigated the design cognitive thinking model that included the external guide thinking of "width priority - depth priority" and the internal dominated thinking of "divergent thinking - convergent thinking", built a reaso...
Optimal Design of Materials for DJMP Based on Genetic Algorithm
Institute of Scientific and Technical Information of China (English)
FENG Zhong-ren; WANG Xiong-jiang
2004-01-01
The genetic algorithm was used in optimal design of deep jet method pile. The cost of deep jetmethod pile in one unit area of foundation was taken as the objective function. All the restrains were listed followingthe corresponding specification. Suggestions were proposed and the modified. The real-coded Genetic Algorithm wasgiven to deal with the problems of excessive computational cost and premature convergence. Software system of opti-mal design of deep jet method pile was developed.
Improved taboo search algorithm for designing DNA sequences
Institute of Scientific and Technical Information of China (English)
Kai Zhang; Jin Xu; Xiutang Geng; Jianhua Xiao; Linqiang Pan
2008-01-01
The design of DNA sequences is one of the most practical and important research topics in DNA computing.We adopt taboo search algorithm and improve the method for the systematic design of equal-length DNA sequences,which can satisfy certain combinatorial and thermodynamic constraints.Using taboo search algorithm,our method can avoid trapping into local optimization and can find a set of good DNA sequences satisfying required constraints.
A framework for integrated design of algorithmic architectural forms
Svoboda, Ladislav; Novák, Jan; Kurilla, Lukáš; Zeman, Jan
2012-01-01
This paper presents a methodology and software tools for parametric design of complex architectural objects, called digital or algorithmic forms. In order to provide a flexible tool, the proposed design philosophy involves two open source utilities Donkey and MIDAS written in Grasshopper algorithm editor and C++, respectively, that are to be linked with a scripting-based architectural modellers Rhinoceros, IntelliCAD and the open source Finite Element solver OOFEM. The emphasis is put on the ...
The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits
Energy Technology Data Exchange (ETDEWEB)
Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))
1993-08-01
An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.
A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level
Institute of Scientific and Technical Information of China (English)
胡谋
1992-01-01
A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.
Channel Access Algorithm Design for Automatic Identification System
Institute of Scientific and Technical Information of China (English)
Oh Sang-heon; Kim Seung-pum; Hwang Dong-hwan; Park Chan-sik; Lee Sang-jeong
2003-01-01
The Automatic Identification System (AIS) is a maritime equipment to allow an efficient exchange of the navigational data between ships and between ships and shore stations. It utilizes a channel access algorithm which can quickly resolve conflicts without any intervention from control stations. In this paper, a design of channel access algorithm for the AIS is presented. The input/output relationship of each access algorithm module is defined by drawing the state transition diagram, dataflow diagram and flowchart based on the technical standard, ITU-R M.1371. In order to verify the designed channel access algorithm, the simulator was developed using the C/C++ programming language. The results show that the proposed channel access algorithm can properly allocate transmission slots and meet the operational performance requirements specified by the technical standard.
Generative Algorithmic Techniques for Architectural Design
DEFF Research Database (Denmark)
Larsen, Niels Martin
2012-01-01
Architectural design methodology is expanded through the ability to create bespoke computational methods as integrated parts of the design process. The rapid proliferation of digital production techniques within building industry provides new means for establishing seamless flows between digital...... form-generation and the realisation process. A tendency in recent practice shows an increased focus on developing unique tectonic solutions as a crucial ingredient in the design solution. These converging trajectories form the contextual basis for this thesis. In architectural design, digital tools....... The principles are further developed to form new modes of articulation in architectural design. Certain methods are contributions, which suggest a potential for future use and development. Thus, a method is directed towards bottom-up generation of surface topology through the use of an agentbased logic. Another...
VLSI digital demodulator co-processor
Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.
A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.
A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
Richstein, James K.
1993-12-01
Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.
VLSI architectures for modern error-correcting codes
Zhang, Xinmiao
2015-01-01
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI
Low-power Analog VLSI Implementation of Wavelet Transform
Institute of Scientific and Technical Information of China (English)
ZHANG Jiang-hong
2009-01-01
For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.
Structural design optimization of vehicle components using Cuckoo Search Algorithm
Energy Technology Data Exchange (ETDEWEB)
Yildiz, Ali Riza [Bursa Technical Univ., Bursa (Turkey). Dept. of Mechanical Engineering; Durgun, Ismail
2012-07-01
In order to meet today's vehicle design requirements and to improve the cost and fuel efficiency, there is an increasing interest to design light-weight and cost-effective vehicle components. In this research, a new optimization algorithm, called the Cuckoo Search Algorithm (CS) algorithm, is introduced for solving structural design optimization problems. This research is the first application of the CS to the shape design optimization problems in the literature. The CS algorithm is applied to the structural design optimization of a vehicle component to illustrate how the present approach can be applied for solving structural design problems. Results show the ability of the CS to find better optimal structural design. [German] Um heutige Anforderungen an das Fahrzeugdesign zu beruecksichtigen und um die Kosten- und Kraftstoffeffektivitaet zu erhoehen, nimmt das Interesse am Design leichter und kosteneffektiver Fahrzeugkomponenten weiterhin zu. In der diesem Beitrag zugrunde liegenden Studie wurde ein neuer Optimierungsalgorithmus angewendet, der so genannte Cuckoo Suchalgorithmus (CS). Es handelt sich um die erste CS-Applikation fuer das Formdesign in der Literatur. Der CS-Algorithmus wird hierbei zur Strukturdesignoptimierung einer Fahrzeugkomponente angewendet, um zu zeigen, wie er bei der Loesung von Strukturdesignaufgaben angewendet werden kann. Die Ergebnisse zeigen, wie damit ein verbessertes Design erreicht werden kann.
Quantum Multiplexer Designing and Optimization applying Genetic Algorithm
Directory of Open Access Journals (Sweden)
Debarka Mukhopadhyay
2010-09-01
Full Text Available This paper shows how to design efficient quantum multiplexer circuit borrowed from classical computer design. The design will show that it is composed of some Toffole gates or C2NOT gate and some two input CNOT gates. Every C2NOT gate is synthesized and optimized by applying the genetic algorithm to get the best possible combination for the design of these gate circuits.
Neural-Network-Biased Genetic Algorithms for Materials Design: Evolutionary Algorithms That Learn.
Patra, Tarak K; Meenakshisundaram, Venkatesh; Hung, Jui-Hsiang; Simmons, David S
2017-02-13
Machine learning has the potential to dramatically accelerate high-throughput approaches to materials design, as demonstrated by successes in biomolecular design and hard materials design. However, in the search for new soft materials exhibiting properties and performance beyond those previously achieved, machine learning approaches are frequently limited by two shortcomings. First, because they are intrinsically interpolative, they are better suited to the optimization of properties within the known range of accessible behavior than to the discovery of new materials with extremal behavior. Second, they require large pre-existing data sets, which are frequently unavailable and prohibitively expensive to produce. Here we describe a new strategy, the neural-network-biased genetic algorithm (NBGA), for combining genetic algorithms, machine learning, and high-throughput computation or experiment to discover materials with extremal properties in the absence of pre-existing data. Within this strategy, predictions from a progressively constructed artificial neural network are employed to bias the evolution of a genetic algorithm, with fitness evaluations performed via direct simulation or experiment. In effect, this strategy gives the evolutionary algorithm the ability to "learn" and draw inferences from its experience to accelerate the evolutionary process. We test this algorithm against several standard optimization problems and polymer design problems and demonstrate that it matches and typically exceeds the efficiency and reproducibility of standard approaches including a direct-evaluation genetic algorithm and a neural-network-evaluated genetic algorithm. The success of this algorithm in a range of test problems indicates that the NBGA provides a robust strategy for employing informatics-accelerated high-throughput methods to accelerate materials design in the absence of pre-existing data.
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A
1999-01-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.
1999-05-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
New VLSI complexity results for threshold gate comparison
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1996-12-31
The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.
Institute of Scientific and Technical Information of China (English)
刘弘; 王文红; 等
1993-01-01
A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.
Genetic Algorithm Based Proportional Integral Controller Design for Induction Motor
Directory of Open Access Journals (Sweden)
Mohanasundaram Kuppusamy
2011-01-01
Full Text Available Problem statement: This study has expounded the application of evolutionary computation method namely Genetic Algorithm (GA for estimation of feedback controller parameters for induction motor. GA offers certain advantages such as simple computational steps, derivative free optimization, reduced number of iterations and assured near global optima. The development of the method is well documented and computed and measured results are presented. Approach: The design of PI controller parameter for three phase induction motor drives was done using Genetic Algorithm. The objective function of motor current reduction, using PI controller, at starting is formulated as an optimization problem and solved with Genetic Algorithm. Results: The results showed the selected values of PI controller parameter using genetic algorithm approach, with objective of induction motor starting current reduction. Conclusions/Recommendation: The results proved the robustness and easy implementation of genetic algorithm selection of PI parameters for induction motor starting.
Impact of hierarchical memory systems on linear algebra algorithm design
Energy Technology Data Exchange (ETDEWEB)
Gallivan, K.; Jalby, W.; Meier, U.; Sameh, A.H.
1988-01-01
Linear algebra algorithms based on the BLAS or extended BLAS do not achieve high performance on multivector processors with a hierarchical memory system because of a lack of data locality. For such machines, block linear algebra algorithms must be implemented in terms of matrix-matrix primitives (BLAS3). Designing efficient linear algebra algorithms for these architectures requires analysis of the behavior of the matrix-matrix primitives and the resulting block algorithms as a function of certain system parameters. The analysis must identify the limits of performance improvement possible via blocking and any contradictory trends that require trade-off consideration. The authors propose a methodology that facilitates such an analysis and use it to analyze the performance of the BLAS3 primitives used in block methods. A similar analysis of the block size-performance relationship is also performed at the algorithm level for block versions of the LU decomposition and the Gram-Schmidt orthogonalization procedures.
Acoustic design of rotor blades using a genetic algorithm
Wells, V. L.; Han, A. Y.; Crossley, W. A.
1995-01-01
A genetic algorithm coupled with a simplified acoustic analysis was used to generate low-noise rotor blade designs. The model includes thickness, steady loading and blade-vortex interaction noise estimates. The paper presents solutions for several variations in the fitness function, including thickness noise only, loading noise only, and combinations of the noise types. Preliminary results indicate that the analysis provides reasonable assessments of the noise produced, and that genetic algorithm successfully searches for 'good' designs. The results show that, for a given required thrust coefficient, proper blade design can noticeably reduce the noise produced at some expense to the power requirements.
Analog Group Delay Equalizers Design Based on Evolutionary Algorithm
Directory of Open Access Journals (Sweden)
M. Laipert
2006-04-01
Full Text Available This paper deals with a design method of the analog all-pass filter designated for equalization of the group delay frequency response of the analog filter. This method is based on usage of evolutionary algorithm, the Differential Evolution algorithm in particular. We are able to design such equalizers to be obtained equal-ripple group delay frequency response in the pass-band of the low-pass filter. The procedure works automatically without an input estimation. The method is presented on solving practical examples.
Foundations of digital signal processing theory, algorithms and hardware design
Gaydecki, Patrick
2005-01-01
An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.
An ellipsoid algorithm for probabilistic robust controller design
Kanev, S.K.; de Schutter, B.; Verhaegen, M.H.G.
2003-01-01
In this paper, a new iterative approach to probabilistic robust controller design is presented, which is applicable to any robust controller/filter design problem that can be represented as an LMI feasibility problem. Recently, a probabilistic Subgradient Iteration algorithm was proposed for solving
The nonstandard algorithm for constructing efficient conjoint experimental designs
Directory of Open Access Journals (Sweden)
Kuzmanović Marija
2008-01-01
Full Text Available Conjoint analysis is a research technique for measuring consumer preferences, and it is a method for simulating consumers' possible reactions to changes in current products or newly introduced products into an existing competitive market. One of the most critical steps in Conjoint analysis application is experimental designs construction. The purpose of an experimental design is to give a rough overall idea as to the shape of the experimental response surface, while only requiring a relatively small number of runs. These designs are expected to be orthogonal and balanced in an ideal case. In practice, though, it is hard to construct optimal designs and thus constructing of near optimal and efficient designs is carried out. There are several ways to quantify the relative efficiency of experimental designs. The choice of measure will determine which types of experimental designs are favored as well as the algorithms for choosing efficient designs. In this paper it is proposed the algorithm which combines one standard and one non-standard optimality criteria. The computational experiments were made, and results of comparison with algorithm implemented in commercial package SPSS confirm the efficiency of the proposed algorithm. .
Raghunathan, Shriram; Gupta, Sumeet K; Markandeya, Himanshu S; Roy, Kaushik; Irazoqui, Pedro P
2010-10-30
Implantable neural prostheses that deliver focal electrical stimulation upon demand are rapidly emerging as an alternate therapy for roughly a third of the epileptic patient population that is medically refractory. Seizure detection algorithms enable feedback mechanisms to provide focally and temporally specific intervention. Real-time feasibility and computational complexity often limit most reported detection algorithms to implementations using computers for bedside monitoring or external devices communicating with the implanted electrodes. A comparison of algorithms based on detection efficacy does not present a complete picture of the feasibility of the algorithm with limited computational power, as is the case with most battery-powered applications. We present a two-dimensional design optimization approach that takes into account both detection efficacy and hardware cost in evaluating algorithms for their feasibility in an implantable application. Detection features are first compared for their ability to detect electrographic seizures from micro-electrode data recorded from kainate-treated rats. Circuit models are then used to estimate the dynamic and leakage power consumption of the compared features. A score is assigned based on detection efficacy and the hardware cost for each of the features, then plotted on a two-dimensional design space. An optimal combination of compared features is used to construct an algorithm that provides maximal detection efficacy per unit hardware cost. The methods presented in this paper would facilitate the development of a common platform to benchmark seizure detection algorithms for comparison and feasibility analysis in the next generation of implantable neuroprosthetic devices to treat epilepsy.
Kirk, David Blair
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for
Associative Pattern Recognition In Analog VLSI Circuits
Tawel, Raoul
1995-01-01
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Carlan, A. J.; Breuer, M. A.
1982-10-01
The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.
Automatic design of decision-tree induction algorithms
Barros, Rodrigo C; Freitas, Alex A
2015-01-01
Presents a detailed study of the major design components that constitute a top-down decision-tree induction algorithm, including aspects such as split criteria, stopping criteria, pruning, and the approaches for dealing with missing values. Whereas the strategy still employed nowadays is to use a 'generic' decision-tree induction algorithm regardless of the data, the authors argue on the benefits that a bias-fitting strategy could bring to decision-tree induction, in which the ultimate goal is the automatic generation of a decision-tree induction algorithm tailored to the application domain o
Algorithmically specialized parallel computers
Snyder, Lawrence; Gannon, Dennis B
1985-01-01
Algorithmically Specialized Parallel Computers focuses on the concept and characteristics of an algorithmically specialized computer.This book discusses the algorithmically specialized computers, algorithmic specialization using VLSI, and innovative architectures. The architectures and algorithms for digital signal, speech, and image processing and specialized architectures for numerical computations are also elaborated. Other topics include the model for analyzing generalized inter-processor, pipelined architecture for search tree maintenance, and specialized computer organization for raster
Directory of Open Access Journals (Sweden)
Sudarshan Tiwari
2012-05-01
Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.
Improved Quantum-Inspired Evolutionary Algorithm for Engineering Design Optimization
Directory of Open Access Journals (Sweden)
Jinn-Tsong Tsai
2012-01-01
Full Text Available An improved quantum-inspired evolutionary algorithm is proposed for solving mixed discrete-continuous nonlinear problems in engineering design. The proposed Latin square quantum-inspired evolutionary algorithm (LSQEA combines Latin squares and quantum-inspired genetic algorithm (QGA. The novel contribution of the proposed LSQEA is the use of a QGA to explore the optimal feasible region in macrospace and the use of a systematic reasoning mechanism of the Latin square to exploit the better solution in microspace. By combining the advantages of exploration and exploitation, the LSQEA provides higher computational efficiency and robustness compared to QGA and real-coded GA when solving global numerical optimization problems with continuous variables. Additionally, the proposed LSQEA approach effectively solves mixed discrete-continuous nonlinear design optimization problems in which the design variables are integers, discrete values, and continuous values. The computational experiments show that the proposed LSQEA approach obtains better results compared to existing methods reported in the literature.
Optimal design of steel portal frames based on genetic algorithms
Institute of Scientific and Technical Information of China (English)
Yue CHEN; Kai HU
2008-01-01
As for the optimal design of steel portal frames, due to both the complexity of cross selections of beams and columns and the discreteness of design variables, it is difficult to obtain satisfactory results by traditional optimization. Based on a set of constraints of the Technical Specification for Light-weighted Steel Portal Frames of China, a genetic algorithm (GA) optimization program for portal frames, written in MATLAB code, was proposed in this paper. The graph user interface (GUI) is also developed for this optimal program, so that it can be used much more conveniently. Finally, some examples illustrate the effectiveness and efficiency of the genetic-algorithm-based optimal program.
DESIGN OF A NEW SECURITY PROTOCOL USING HYBRID CRYPTOGRAPHY ALGORITHMS
Directory of Open Access Journals (Sweden)
Dr.S.Subasree and Dr.N.K.Sakthivel
2010-02-01
Full Text Available A Computer Network is an interconnected group of autonomous computing nodes, which use a well defined, mutually agreed set of rules and conventions known as protocols, interact with one-another meaningfully and allow resource sharing preferably in a predictable and controllable manner. Communication has a major impact on today’s business. It is desired to communicate data with high security. Security Attacks compromises the security and hence various Symmetric and Asymmetric cryptographic algorithms have been proposed to achieve the security services such as Authentication, Confidentiality, Integrity, Non-Repudiation and Availability. At present, various types of cryptographic algorithms provide high security to information on controlled networks. These algorithms are required to provide data security and users authenticity. To improve the strength of these security algorithms, a new security protocol for on line transaction can be designed using combination of both symmetric and asymmetric cryptographic techniques. This protocol provides three cryptographic primitives such as integrity, confidentiality and authentication. These three primitives can be achieved with the help of Elliptic Curve Cryptography, Dual-RSA algorithm and Message Digest MD5. That is it uses Elliptic Curve Cryptography for encryption, Dual-RSA algorithm for authentication and MD-5 for integrity. This new security protocol has been designed for better security with integrity using a combination of both symmetric and asymmetric cryptographic techniques.
Alexander, George
1984-01-01
Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…
Designing Artificial Neural Networks Using Particle Swarm Optimization Algorithms.
Garro, Beatriz A; Vázquez, Roberto A
2015-01-01
Artificial Neural Network (ANN) design is a complex task because its performance depends on the architecture, the selected transfer function, and the learning algorithm used to train the set of synaptic weights. In this paper we present a methodology that automatically designs an ANN using particle swarm optimization algorithms such as Basic Particle Swarm Optimization (PSO), Second Generation of Particle Swarm Optimization (SGPSO), and a New Model of PSO called NMPSO. The aim of these algorithms is to evolve, at the same time, the three principal components of an ANN: the set of synaptic weights, the connections or architecture, and the transfer functions for each neuron. Eight different fitness functions were proposed to evaluate the fitness of each solution and find the best design. These functions are based on the mean square error (MSE) and the classification error (CER) and implement a strategy to avoid overtraining and to reduce the number of connections in the ANN. In addition, the ANN designed with the proposed methodology is compared with those designed manually using the well-known Back-Propagation and Levenberg-Marquardt Learning Algorithms. Finally, the accuracy of the method is tested with different nonlinear pattern classification problems.
Designing Artificial Neural Networks Using Particle Swarm Optimization Algorithms
Directory of Open Access Journals (Sweden)
Beatriz A. Garro
2015-01-01
Full Text Available Artificial Neural Network (ANN design is a complex task because its performance depends on the architecture, the selected transfer function, and the learning algorithm used to train the set of synaptic weights. In this paper we present a methodology that automatically designs an ANN using particle swarm optimization algorithms such as Basic Particle Swarm Optimization (PSO, Second Generation of Particle Swarm Optimization (SGPSO, and a New Model of PSO called NMPSO. The aim of these algorithms is to evolve, at the same time, the three principal components of an ANN: the set of synaptic weights, the connections or architecture, and the transfer functions for each neuron. Eight different fitness functions were proposed to evaluate the fitness of each solution and find the best design. These functions are based on the mean square error (MSE and the classification error (CER and implement a strategy to avoid overtraining and to reduce the number of connections in the ANN. In addition, the ANN designed with the proposed methodology is compared with those designed manually using the well-known Back-Propagation and Levenberg-Marquardt Learning Algorithms. Finally, the accuracy of the method is tested with different nonlinear pattern classification problems.
Motion estimation for video coding efficient algorithms and architectures
Chakrabarti, Indrajit; Chatterjee, Sumit Kumar
2015-01-01
The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones.
Backbone analysis and algorithm design for the quadratic assignment problem
Institute of Scientific and Technical Information of China (English)
JIANG He; ZHANG XianChao; CHEN GuoLiang; LI MingChu
2008-01-01
As the hot line in NP-hard problems research in recent years, backbone analysis is crucial for phase transition, hardness, and algorithm design. Whereas theoretical analysis of backbone and its applications in algorithm design are still at a begin-ning state yet, this paper took the quadratic assignment problem (QAP) as a case study and proved by theoretical analysis that it is NP-hard to find the backbone, l.e., no algorithm exists to obtain the backbone of a QAP in polynomial time. Results of this paper showed that it is reasonable to acquire approximate backbone by inter-section of local optimal solutions. Furthermore, with the method of constructing biased instances, this paper proposed a new meta-heuristic - biased instance based approximate backbone (BI-AB), whose basic idea is as follows: firstly, con-struct a new biased instance for every QAP instance (the optimal solution of the new instance is also optimal for the original one); secondly, the approximate backbone is obtained by intersection of multiple local optimal solutions computed by some existing algorithm; finally, search for the optimal solutions in the reduced space by fixing the approximate backbone. Work of the paper enhanced the re-search area of theoretical analysis of backbone. The meta-heuristic proposed in this paper provided a new way for general algorithm design of NP-hard problems as well.
Cascaded VLSI Chips Help Neural Network To Learn
Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.
1993-01-01
Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.
Power Efficient Sub-Array in Reconfigurable VLSI Meshes
Institute of Scientific and Technical Information of China (English)
Ji-Gang Wu; Thambipillai Srikanthan
2005-01-01
Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.
Design of synthetic biological logic circuits based on evolutionary algorithm.
Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei
2013-08-01
The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.
Design of Automatic Extraction Algorithm of Knowledge Points for MOOCs.
Chen, Haijian; Han, Dongmei; Dai, Yonghui; Zhao, Lina
2015-01-01
In recent years, Massive Open Online Courses (MOOCs) are very popular among college students and have a powerful impact on academic institutions. In the MOOCs environment, knowledge discovery and knowledge sharing are very important, which currently are often achieved by ontology techniques. In building ontology, automatic extraction technology is crucial. Because the general methods of text mining algorithm do not have obvious effect on online course, we designed automatic extracting course knowledge points (AECKP) algorithm for online course. It includes document classification, Chinese word segmentation, and POS tagging for each document. Vector Space Model (VSM) is used to calculate similarity and design the weight to optimize the TF-IDF algorithm output values, and the higher scores will be selected as knowledge points. Course documents of "C programming language" are selected for the experiment in this study. The results show that the proposed approach can achieve satisfactory accuracy rate and recall rate.
Design of Automatic Extraction Algorithm of Knowledge Points for MOOCs
Chen, Haijian; Han, Dongmei; Zhao, Lina
2015-01-01
In recent years, Massive Open Online Courses (MOOCs) are very popular among college students and have a powerful impact on academic institutions. In the MOOCs environment, knowledge discovery and knowledge sharing are very important, which currently are often achieved by ontology techniques. In building ontology, automatic extraction technology is crucial. Because the general methods of text mining algorithm do not have obvious effect on online course, we designed automatic extracting course knowledge points (AECKP) algorithm for online course. It includes document classification, Chinese word segmentation, and POS tagging for each document. Vector Space Model (VSM) is used to calculate similarity and design the weight to optimize the TF-IDF algorithm output values, and the higher scores will be selected as knowledge points. Course documents of “C programming language” are selected for the experiment in this study. The results show that the proposed approach can achieve satisfactory accuracy rate and recall rate. PMID:26448738
Design of Automatic Extraction Algorithm of Knowledge Points for MOOCs
Directory of Open Access Journals (Sweden)
Haijian Chen
2015-01-01
Full Text Available In recent years, Massive Open Online Courses (MOOCs are very popular among college students and have a powerful impact on academic institutions. In the MOOCs environment, knowledge discovery and knowledge sharing are very important, which currently are often achieved by ontology techniques. In building ontology, automatic extraction technology is crucial. Because the general methods of text mining algorithm do not have obvious effect on online course, we designed automatic extracting course knowledge points (AECKP algorithm for online course. It includes document classification, Chinese word segmentation, and POS tagging for each document. Vector Space Model (VSM is used to calculate similarity and design the weight to optimize the TF-IDF algorithm output values, and the higher scores will be selected as knowledge points. Course documents of “C programming language” are selected for the experiment in this study. The results show that the proposed approach can achieve satisfactory accuracy rate and recall rate.
Application of Different Algorithms to Optimal Design of Canal Sections
Directory of Open Access Journals (Sweden)
A. Kentli
2014-08-01
Full Text Available Today the increased world population and therefore the growth demand has forced the researchers to investigate better water canal networks distributing much more water while at least keeping its quality. Canal design formulas are explicitly obtained for different cross-sections considering minimum area but optimal design of canal sections considering seepage and evaporation losses are still an open area to study. In this study, two different algorithms are applied to this problem and results are compared with the one in literature. Genetic algorithm and sequential quadratic programming technique are used in optimization. Triangular, rectangular and trapezoidal cross-sections are optimized. It is seen that both algorithms are giving more accurate results than in literature.
A superlinear interior points algorithm for engineering design optimization
Herskovits, J.; Asquier, J.
1990-01-01
We present a quasi-Newton interior points algorithm for nonlinear constrained optimization. It is based on a general approach consisting of the iterative solution in the primal and dual spaces of the equalities in Karush-Kuhn-Tucker optimality conditions. This is done in such a way to have primal and dual feasibility at each iteration, which ensures satisfaction of those optimality conditions at the limit points. This approach is very strong and efficient, since at each iteration it only requires the solution of two linear systems with the same matrix, instead of quadratic programming subproblems. It is also particularly appropriate for engineering design optimization inasmuch at each iteration a feasible design is obtained. The present algorithm uses a quasi-Newton approximation of the second derivative of the Lagrangian function in order to have superlinear asymptotic convergence. We discuss theoretical aspects of the algorithm and its computer implementation.
A superlinear interior points algorithm for engineering design optimization
Herskovits, J.; Asquier, J.
1990-01-01
We present a quasi-Newton interior points algorithm for nonlinear constrained optimization. It is based on a general approach consisting of the iterative solution in the primal and dual spaces of the equalities in Karush-Kuhn-Tucker optimality conditions. This is done in such a way to have primal and dual feasibility at each iteration, which ensures satisfaction of those optimality conditions at the limit points. This approach is very strong and efficient, since at each iteration it only requires the solution of two linear systems with the same matrix, instead of quadratic programming subproblems. It is also particularly appropriate for engineering design optimization inasmuch at each iteration a feasible design is obtained. The present algorithm uses a quasi-Newton approximation of the second derivative of the Lagrangian function in order to have superlinear asymptotic convergence. We discuss theoretical aspects of the algorithm and its computer implementation.
The Conceptual Design Algorithm of Inland LNG Barges
Łozowicka, Dorota; Kaup, Magdalena
2017-03-01
The article concerns the problem of inland waterways transport of LNG. Its aim is to present the algorithm of conceptual design of inland barges for LNG transport, intended for exploitation on European waterways. The article describes the areas where LNG barges exist, depending on the allowable operating parameters on the waterways. It presents existing architectural and construction solutions of barges for inland LNG transport, as well as the necessary equipment, due to the nature of cargo. Then the article presents the procedure of the conceptual design of LNG barges, including navigation restrictions and functional and economic criteria. The conceptual design algorithm of LGN barges, presented in the article, allows to preliminary design calculations, on the basis of which, are obtained the main dimensions and parameters of unit, depending on the transport task and the class of inland waterways, on which the transport will be realized.
Genetic Algorithm Design of a 3D Printed Heat Sink
Energy Technology Data Exchange (ETDEWEB)
Wu, Tong [ORNL; Ozpineci, Burak [ORNL; Ayers, Curtis William [ORNL
2016-01-01
In this paper, a genetic algorithm- (GA-) based approach is discussed for designing heat sinks based on total heat generation and dissipation for a pre-specified size andshape. This approach combines random iteration processesand genetic algorithms with finite element analysis (FEA) to design the optimized heat sink. With an approach that prefers survival of the fittest , a more powerful heat sink can bedesigned which can cool power electronics more efficiently. Some of the resulting designs can only be 3D printed due totheir complexity. In addition to describing the methodology, this paper also includes comparisons of different cases to evaluate the performance of the newly designed heat sinkcompared to commercially available heat sinks.
USING GENETIC ALGORITHMS TO DESIGN ENVIRONMENTALLY FRIENDLY PROCESSES
Genetic algorithm calculations are applied to the design of chemical processes to achieve improvements in environmental and economic performance. By finding the set of Pareto (i.e., non-dominated) solutions one can see how different objectives, such as environmental and economic ...
Design optimization of mechanical systems using genetic algorithms
National Research Council Canada - National Science Library
UYGUR, İlyas; SARUHAN, Hamit
2003-01-01
... içinde tarama yapan ve genetik fikrine dayalı uygun araştırma teknikleridir. This paper presents an algorithm for the design of minimum weight of speed reducer, gear train, subject to a specified set of constraints...
USING GENETIC ALGORITHMS TO DESIGN ENVIRONMENTALLY FRIENDLY PROCESSES
Genetic algorithm calculations are applied to the design of chemical processes to achieve improvements in environmental and economic performance. By finding the set of Pareto (i.e., non-dominated) solutions one can see how different objectives, such as environmental and economic ...
Synthesis design of artificial magnetic metamaterials using a genetic algorithm.
Chen, P Y; Chen, C H; Wang, H; Tsai, J H; Ni, W X
2008-08-18
In this article, we present a genetic algorithm (GA) as one branch of artificial intelligence (AI) for the optimization-design of the artificial magnetic metamaterial whose structure is automatically generated by computer through the filling element methodology. A representative design example, metamaterials with permeability of negative unity, is investigated and the optimized structures found by the GA are presented. It is also demonstrated that our approach is effective for the synthesis of functional magnetic and electric metamaterials with optimal structures. This GA-based optimization-design technique shows great versatility and applicability in the design of functional metamaterials.
Interactive evolutionary algorithms and data mining for drug design
Lameijer, Eric Marcel Wubbo
2010-01-01
One of the main problems of drug design is that it is quite hard to discover compounds that have all the required properties to become a drug (efficacy against the disease, good biological availability, low toxicity). This thesis describes the use of data mining and interactive evolutionary algorithms to design novel classes of molecules. Using data mining, we split a 250,000 compound database into ring systems, substituents and linkers. We then counted the occurrence of the different fragmen...
Current-mode subthreshold MOS circuits for analog VLSI neural systems
Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.
1991-03-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Current-mode subthreshold MOS circuits for analog VLSI neural systems.
Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K
1991-01-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Biologically inspired binaural hearing aid algorithms: Design principles and effectiveness
Feng, Albert
2002-05-01
Despite rapid advances in the sophistication of hearing aid technology and microelectronics, listening in noise remains problematic for people with hearing impairment. To solve this problem two algorithms were designed for use in binaural hearing aid systems. The signal processing strategies are based on principles in auditory physiology and psychophysics: (a) the location/extraction (L/E) binaural computational scheme determines the directions of source locations and cancels noise by applying a simple subtraction method over every frequency band; and (b) the frequency-domain minimum-variance (FMV) scheme extracts a target sound from a known direction amidst multiple interfering sound sources. Both algorithms were evaluated using standard metrics such as signal-to-noise-ratio gain and articulation index. Results were compared with those from conventional adaptive beam-forming algorithms. In free-field tests with multiple interfering sound sources our algorithms performed better than conventional algorithms. Preliminary intelligibility and speech reception results in multitalker environments showed gains for every listener with normal or impaired hearing when the signals were processed in real time with the FMV binaural hearing aid algorithm. [Work supported by NIH-NIDCD Grant No. R21DC04840 and the Beckman Institute.
DESIGN AND SIMULATION OF VERTICAL HANDOVER ALGORITHM FOR VEHICULAR COMMUNICATION
Directory of Open Access Journals (Sweden)
Sourav Dhar,
2010-10-01
Full Text Available The primary objective in this work is to design and simulate a novel handover algorithm in heterogeneous radio mnetwork for intelligent transportation system (ITS. Analytic hierarchy process (AHP is used to solve decision problem in multiple constraint environment. The user preferences are taken into consideration in this algorithm. Acase study is illustrated to demonstrate the effectiveness of this model. Several network contexts like received signal strength (RSS, initial delay for connection establishment, network traffic load and bandwidth offered, service context like usage cost, user contexts like type of application and terminal context like speed of the vehicle are considered as different attributes of this algorithm. RSS is considered as the triggering factor, i.e, a network will be considered as an alternative only if its RSS is above threshold. The proposed method decides the priority of radio access network that is most suitable for user’s application at a particular vehicular speed in the constraint resource environment. Sensitivity analysis is done to justify the design of the algorithm. This algorithm is specific tovehicular communication system and hence variation in network selection with vehicle speed is presented. The results show that the presented model not only realistically optimizes the best available network on the move but also avoids unnecessary handovers. Simulation work has been carried out in the MATLAB environment.
Convolution kernel design and efficient algorithm for sampling density correction.
Johnson, Kenneth O; Pipe, James G
2009-02-01
Sampling density compensation is an important step in non-cartesian image reconstruction. One of the common techniques to determine weights that compensate for differences in sampling density involves a convolution. A new convolution kernel is designed for sampling density attempting to minimize the error in a fully reconstructed image. The resulting weights obtained using this new kernel are compared with various previous methods, showing a reduction in reconstruction error. A computationally efficient algorithm is also presented that facilitates the calculation of the convolution of finite kernels. Both the kernel and the algorithm are extended to 3D. Copyright 2009 Wiley-Liss, Inc.
An Algorithm for the Mixed Transportation Network Design Problem.
Liu, Xinyu; Chen, Qun
2016-01-01
This paper proposes an optimization algorithm, the dimension-down iterative algorithm (DDIA), for solving a mixed transportation network design problem (MNDP), which is generally expressed as a mathematical programming with equilibrium constraint (MPEC). The upper level of the MNDP aims to optimize the network performance via both the expansion of the existing links and the addition of new candidate links, whereas the lower level is a traditional Wardrop user equilibrium (UE) problem. The idea of the proposed solution algorithm (DDIA) is to reduce the dimensions of the problem. A group of variables (discrete/continuous) is fixed to optimize another group of variables (continuous/discrete) alternately; then, the problem is transformed into solving a series of CNDPs (continuous network design problems) and DNDPs (discrete network design problems) repeatedly until the problem converges to the optimal solution. The advantage of the proposed algorithm is that its solution process is very simple and easy to apply. Numerical examples show that for the MNDP without budget constraint, the optimal solution can be found within a few iterations with DDIA. For the MNDP with budget constraint, however, the result depends on the selection of initial values, which leads to different optimal solutions (i.e., different local optimal solutions). Some thoughts are given on how to derive meaningful initial values, such as by considering the budgets of new and reconstruction projects separately.
Exact and approximation algorithms for DNA tag set design.
Măndoiu, Ion I; Trincă, Dragoş
2006-04-01
In this paper, we propose new solution methods for designing tag sets for use in universal DNA arrays. First, we give integer linear programming formulations for two previous formalizations of the tag set design problem. We show that these formulations can be solved to optimality for problem instances of moderate size by using general purpose optimization packages and also give more scalable algorithms based on an approximation scheme for packing linear programs. Second, we note the benefits of periodic tags and establish an interesting connection between the tag design problem and the problem of packing the maximum number of vertex-disjoint directed cycles in a given graph. We show that combining a simple greedy cycle packing algorithm with a previously proposed alphabetic tree search strategy yields an increase of over 40% in the number of tags compared to previous methods.
Energy Technology Data Exchange (ETDEWEB)
Martinez-Canales, Monica L.; Heaphy, Robert (Sandia National Laboratories, Albuquerque, NM); Gramacy, Robert B. (University of Cambridge); Taddy, Matt (University of California, Santa Cruz, CA); Chiesa, Michael L.; Thomas, Stephen W. (Sandia National Laboratories, Albuquerque, NM); Swiler, Laura Painton (Sandia National Laboratories, Albuquerque, NM); Hough, Patricia Diane; Lee, Herbert K. H. (University of California, Santa Cruz, CA); Trucano, Timothy Guy (Sandia National Laboratories, Albuquerque, NM); Gray, Genetha Anne
2006-11-01
This project focused on research and algorithmic development in optimization under uncertainty (OUU) problems driven by earth penetrator (EP) designs. While taking into account uncertainty, we addressed three challenges in current simulation-based engineering design and analysis processes. The first challenge required leveraging small local samples, already constructed by optimization algorithms, to build effective surrogate models. We used Gaussian Process (GP) models to construct these surrogates. We developed two OUU algorithms using 'local' GPs (OUU-LGP) and one OUU algorithm using 'global' GPs (OUU-GGP) that appear competitive or better than current methods. The second challenge was to develop a methodical design process based on multi-resolution, multi-fidelity models. We developed a Multi-Fidelity Bayesian Auto-regressive process (MF-BAP). The third challenge involved the development of tools that are computational feasible and accessible. We created MATLAB{reg_sign} and initial DAKOTA implementations of our algorithms.
Genetic Algorithms for the Optimal Design of Superconducting Accelerator Magnets
Ramberger, S
1998-01-01
The paper describes the use of genetic algorithms with the concept of niching for the optimal design of superconducting magnets for the Large Hadron Collider, LHC at CERN. The method provides the designer with a number of local optima which can be further examined with respect to objectives such as ease of coil winding, sensitivity to manufacturing tolerances and local electromagnetic force distribution. A 6 block dipole coil was found to have advantages compared to the standard 5 block version which was previously designed using deterministic optimization methods. Results were proven by a short model magnet recently built and tested at CERN.
Performance of a recursive algorithm for polynomial predistorter design
Institute of Scientific and Technical Information of China (English)
XU Ling-jun; WU Xiao-guang; WANG Yong; ZHANG Ping
2008-01-01
In this article, based on least square estimation, a recursive algorithm for indirect learning structure predistorter is introduced. Simulation results show that of all polynomial predistorter nonlinear terms, higher-order (higher than 7th-order) nonlinear terms are so minor that they can be omitted in practical predistorter design. So, it is unnecessary to construct predistorter with higher-order polynomials, and the algorithm will always be stable. Further results show that even when 15th-order polynomial model is used, the algorithm is convergent after 10 iterations, and it can improve out-band spectrum of 20 MHz bandwidth signal by 64 dB, with a 1.2×1011 matrix condition number.
Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications
Directory of Open Access Journals (Sweden)
P. Mohan Krishna
2014-04-01
Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.
Deterministic Polynomial-Time Algorithms for Designing Short DNA Words
Kao, Ming-Yang; Sun, He; Zhang, Yong
2012-01-01
Designing short DNA words is a problem of constructing a set (i.e., code) of n DNA strings (i.e., words) with the minimum length such that the Hamming distance between each pair of words is at least k and the n words satisfy a set of additional constraints. This problem has applications in, e.g., DNA self-assembly and DNA arrays. Previous works include those that extended results from coding theory to obtain bounds on code and word sizes for biologically motivated constraints and those that applied heuristic local searches, genetic algorithms, and randomized algorithms. In particular, Kao, Sanghi, and Schweller (2009) developed polynomial-time randomized algorithms to construct n DNA words of length within a multiplicative constant of the smallest possible word length (e.g., 9 max{log n, k}) that satisfy various sets of constraints with high probability. In this paper, we give deterministic polynomial-time algorithms to construct DNA words based on derandomization techniques. Our algorithms can construct n DN...
Optimal Design of a Centrifugal Compressor Impeller Using Evolutionary Algorithms
Directory of Open Access Journals (Sweden)
Soo-Yong Cho
2012-01-01
Full Text Available An optimization study was conducted on a centrifugal compressor. Eight design variables were chosen from the control points for the Bezier curves which widely influenced the geometric variation; four design variables were selected to optimize the flow passage between the hub and the shroud, and other four design variables were used to improve the performance of the impeller blade. As an optimization algorithm, an artificial neural network (ANN was adopted. Initially, the design of experiments was applied to set up the initial data space of the ANN, which was improved during the optimization process using a genetic algorithm. If a result of the ANN reached a higher level, that result was re-calculated by computational fluid dynamics (CFD and was applied to develop a new ANN. The prediction difference between the ANN and CFD was consequently less than 1% after the 6th generation. Using this optimization technique, the computational time for the optimization was greatly reduced and the accuracy of the optimization algorithm was increased. The efficiency was improved by 1.4% without losing the pressure ratio, and Pareto-optimal solutions of the efficiency versus the pressure ratio were obtained through the 21st generation.
Entropy-Based Search Algorithm for Experimental Design
Malakar, N. K.; Knuth, K. H.
2011-03-01
The scientific method relies on the iterated processes of inference and inquiry. The inference phase consists of selecting the most probable models based on the available data; whereas the inquiry phase consists of using what is known about the models to select the most relevant experiment. Optimizing inquiry involves searching the parameterized space of experiments to select the experiment that promises, on average, to be maximally informative. In the case where it is important to learn about each of the model parameters, the relevance of an experiment is quantified by Shannon entropy of the distribution of experimental outcomes predicted by a probable set of models. If the set of potential experiments is described by many parameters, we must search this high-dimensional entropy space. Brute force search methods will be slow and computationally expensive. We present an entropy-based search algorithm, called nested entropy sampling, to select the most informative experiment for efficient experimental design. This algorithm is inspired by Skilling's nested sampling algorithm used in inference and borrows the concept of a rising threshold while a set of experiment samples are maintained. We demonstrate that this algorithm not only selects highly relevant experiments, but also is more efficient than brute force search. Such entropic search techniques promise to greatly benefit autonomous experimental design.
Realistic model of compact VLSI FitzHugh-Nagumo oscillators
Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel
2014-02-01
In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.
Centronit: Initial Centroid Designation Algorithm for K-Means Clustering
Directory of Open Access Journals (Sweden)
Ali Ridho Barakbah
2014-06-01
Full Text Available Clustering performance of the K-means highly depends on the correctness of initial centroids. Usually initial centroids for the K- means clustering are determined randomly so that the determined initial centers may cause to reach the nearest local minima, not the global optimum. In this paper, we propose an algorithm, called as Centronit, for designation of initial centroidoptimization of K-means clustering. The proposed algorithm is based on the calculation of the average distance of the nearest data inside region of the minimum distance. The initial centroids can be designated by the lowest average distance of each data. The minimum distance is set by calculating the average distance between the data. This method is also robust from outliers of data. The experimental results show effectiveness of the proposed method to improve the clustering results with the K-means clustering. Keywords: K-means clustering, initial centroids, Kmeansoptimization.
Optimization of transmission system design based on genetic algorithm
Directory of Open Access Journals (Sweden)
Xianbing Chen
2016-05-01
Full Text Available Transmission system is a crucial precision mechanism for twin-screw chemi-mechanical pulping equipment. The structure of the system designed by traditional method is not optimal because the structure designed by the traditional methods is easy to fall into the local optimum. To achieve the global optimum, this article applies the genetic algorithm which has grown in recent years in the field of structure optimization. The article uses the volume of transmission system as the objective function to optimize the structure designed by traditional method. Compared to the simulation results, the original structure is not optimal, and the optimized structure is tighter and more reasonable. Based on the optimized results, the transmission shafts in the transmission system are designed and checked, and the parameters of the twin screw are selected and calculated. The article provided an effective method to design the structure of transmission system.
VLSI Microsystem for Rapid Bioinformatic Pattern Recognition
Fang, Wai-Chi; Lue, Jaw-Chyng
2009-01-01
A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).
Leak detection utilizing analog binaural (VLSI) techniques
Hartley, Frank T. (Inventor)
1995-01-01
A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Generating Weighted Test Patterns for VLSI Chips
Siavoshi, Fardad
1990-01-01
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam
2011-12-01
Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.
Specific PCR product primer design using memetic algorithm.
Yang, Cheng-Hong; Cheng, Yu-Huei; Chuang, Li-Yeh; Chang, Hsueh-Wei
2009-01-01
To provide feasible primer sets for performing a polymerase chain reaction (PCR) experiment, many primer design methods have been proposed. However, the majority of these methods require a relatively long time to obtain an optimal solution since large quantities of template DNA need to be analyzed. Furthermore, the designed primer sets usually do not provide a specific PCR product size. In recent years, evolutionary computation has been applied to PCR primer design and yielded promising results. In this article, a memetic algorithm (MA) is proposed to solve primer design problems associated with providing a specific product size for PCR experiments. The MA is compared with a genetic algorithm (GA) using an accuracy formula to estimate the quality of the primer design and test the running time. Overall, 50 accession nucleotide sequences were sampled for the comparison of the accuracy of the GA and MA for primer design. Five hundred runs of the GA and MA primer design were performed with PCR product lengths of 150-300 bps and 500-800 bps, and two different methods of calculating T(m) for each accession nucleotide sequence were tested. A comparison of the accuracy results for the GA and MA primer design showed that the MA primer design yielded better results than the GA primer design. The results further indicate that the proposed method finds optimal or near-optimal primer sets and effective PCR products in a dry dock experiment. Related materials are available online at http://bio.kuas.edu.tw/ma-pd/. 2009 American Institute of Chemical Engineers
Fey, D; Kasche, B; Burkert, C; Tschäche, O
1998-01-10
A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.
Vlsi implementation of flexible architecture for decision tree classification in data mining
Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak
2017-07-01
The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.
Robust Optimization Design Algorithm for High-Frequency TWTs
Wilson, Jeffrey D.; Chevalier, Christine T.
2010-01-01
Traveling-wave tubes (TWTs), such as the Ka-band (26-GHz) model recently developed for the Lunar Reconnaissance Orbiter, are essential as communication amplifiers in spacecraft for virtually all near- and deep-space missions. This innovation is a computational design algorithm that, for the first time, optimizes the efficiency and output power of a TWT while taking into account the effects of dimensional tolerance variations. Because they are primary power consumers and power generation is very expensive in space, much effort has been exerted over the last 30 years to increase the power efficiency of TWTs. However, at frequencies higher than about 60 GHz, efficiencies of TWTs are still quite low. A major reason is that at higher frequencies, dimensional tolerance variations from conventional micromachining techniques become relatively large with respect to the circuit dimensions. When this is the case, conventional design- optimization procedures, which ignore dimensional variations, provide inaccurate designs for which the actual amplifier performance substantially under-performs that of the design. Thus, this new, robust TWT optimization design algorithm was created to take account of and ameliorate the deleterious effects of dimensional variations and to increase efficiency, power, and yield of high-frequency TWTs. This design algorithm can help extend the use of TWTs into the terahertz frequency regime of 300-3000 GHz. Currently, these frequencies are under-utilized because of the lack of efficient amplifiers, thus this regime is known as the "terahertz gap." The development of an efficient terahertz TWT amplifier could enable breakthrough applications in space science molecular spectroscopy, remote sensing, nondestructive testing, high-resolution "through-the-wall" imaging, biomedical imaging, and detection of explosives and toxic biochemical agents.
Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis
2005-06-01
In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.
Optimal brushless DC motor design using genetic algorithms
Energy Technology Data Exchange (ETDEWEB)
Rahideh, A. [Department of Engineering, Queen Mary, University of London, London E1 4NS (United Kingdom); Korakianitis, T., E-mail: korakianitis@alum.mit.ed [Department of Engineering, Queen Mary, University of London, London E1 4NS (United Kingdom); Ruiz, P. [Department of Engineering, Queen Mary, University of London, London E1 4NS (United Kingdom); Keeble, T.; Rothman, M.T. [Cardiac Research and Development, Barts and the London NHS Trust, The London Chest Hospital, London E2 9JX (United Kingdom)
2010-11-15
This paper presents a method for the optimal design of a slotless permanent magnet brushless DC (BLDC) motor with surface mounted magnets using a genetic algorithm. Characteristics of the motor are expressed as functions of motor geometries. The objective function is a combination of losses, volume and cost to be minimized simultaneously. Electrical and mechanical requirements (i.e. voltage, torque and speed) and other limitations (e.g. upper and lower limits of the motor geometries) are cast into constraints of the optimization problem. One sample case is used to illustrate the design and optimization technique.
Optimal brushless DC motor design using genetic algorithms
Rahideh, A.; Korakianitis, T.; Ruiz, P.; Keeble, T.; Rothman, M. T.
2010-11-01
This paper presents a method for the optimal design of a slotless permanent magnet brushless DC (BLDC) motor with surface mounted magnets using a genetic algorithm. Characteristics of the motor are expressed as functions of motor geometries. The objective function is a combination of losses, volume and cost to be minimized simultaneously. Electrical and mechanical requirements (i.e. voltage, torque and speed) and other limitations (e.g. upper and lower limits of the motor geometries) are cast into constraints of the optimization problem. One sample case is used to illustrate the design and optimization technique.
A Matrix-Free Algorithm for Multidisciplinary Design Optimization
Lambe, Andrew Borean
Multidisciplinary design optimization (MDO) is an approach to engineering design that exploits the coupling between components or knowledge disciplines in a complex system to improve the final product. In aircraft design, MDO methods can be used to simultaneously design the outer shape of the aircraft and the internal structure, taking into account the complex interaction between the aerodynamic forces and the structural flexibility. Efficient strategies are needed to solve such design optimization problems and guarantee convergence to an optimal design. This work begins with a comprehensive review of MDO problem formulations and solution algorithms. First, a fundamental MDO problem formulation is defined from which other formulations may be obtained through simple transformations. Using these fundamental problem formulations, decomposition methods from the literature are reviewed and classified. All MDO methods are presented in a unified mathematical notation to facilitate greater understanding. In addition, a novel set of diagrams, called extended design structure matrices, are used to simultaneously visualize both data communication and process flow between the many software components of each method. For aerostructural design optimization, modern decomposition-based MDO methods cannot efficiently handle the tight coupling between the aerodynamic and structural states. This fact motivates the exploration of methods that can reduce the computational cost. A particular structure in the direct and adjoint methods for gradient computation. motivates the idea of a matrix-free optimization method. A simple matrix-free optimizer is developed based on the augmented Lagrangian algorithm. This new matrix-free optimizer is tested on two structural optimization problems and one aerostructural optimization problem. The results indicate that the matrix-free optimizer is able to efficiently solve structural and multidisciplinary design problems with thousands of variables and
Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology
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Ms. Ujwala A. Belorkar
2011-03-01
Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.
Chiral metamaterial design using optimized pixelated inclusions with genetic algorithm
Akturk, Cemal; Karaaslan, Muharrem; Ozdemir, Ersin; Ozkaner, Vedat; Dincer, Furkan; Bakir, Mehmet; Ozer, Zafer
2015-03-01
Chiral metamaterials have been a research area for many researchers due to their polarization rotation properties on electromagnetic waves. However, most of the proposed chiral metamaterials are designed depending on experience or time-consuming inefficient simulations. A method is investigated for designing a chiral metamaterial with a strong and natural chirality admittance by optimizing a grid of metallic pixels through both sides of a dielectric sheet placed perpendicular to the incident wave by using a genetic algorithm (GA) technique based on finite element method solver. The effective medium parameters are obtained by using constitutive equations and S parameters. The proposed methodology is very efficient for designing a chiral metamaterial with the desired effective medium parameters. By using GA-based topology, it is proven that a chiral metamaterial can be designed and manufactured more easily and with a low cost.
An Ant Colony Optimization Algorithm for Microwave Corrugated Filters Design
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Ivan A. Mantilla-Gaviria
2013-01-01
Full Text Available A practical and useful application of the Ant Colony Optimization (ACO method for microwave corrugated filter design is shown. The classical, general purpose ACO method is adapted to deal with the microwave filter design problem. The design strategy used in this paper is an iterative procedure based on the use of an optimization method along with an electromagnetic simulator. The designs of high-pass and band-pass microwave rectangular waveguide filters working in the C-band and X-band, respectively, for communication applications, are shown. The average convergence performance of the ACO method is characterized by means of Monte Carlo simulations and compared with that obtained with the well-known Genetic Algorithm (GA. The overall performance, for the simulations presented herein, of the ACO is found to be better than that of the GA.
Design of dual-band reflectarray using genetic algorithm
Maruyama, Tamami
2017-07-01
This paper proposes novel design method of dual-band reflectarray using genetic algorithm (GA). Ordinary, each elements of reflectarray are designed to have desired reflection phase. However, when we adopt same polarization in dual frequencies, the element configuration designed to satisfy desired reflection phase in one frequency influences the characteristics in other frequency. Therefore, it is difficult to achieve dual-band reflectarray. To address the issues, we adopt two layer patches for element to increase flexibility of design and optimize the patches configuration using GA. As a result, we achieve novel reflectarray that reflect wave towards the direction of theta equal to 27 deg. and phi equal to 0 deg. in dual frequency simultaneously when incidence wave is coming from the direction of theta equal to 0 deg. and phi equal to 0 deg. in dual frequency.
OPTIMAL DESIGN OF SINGLE PHASE TRANSFORMER USING BACTERIAL FORAGING ALGORITHM
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S.SUBRAMANIAN,
2011-04-01
Full Text Available The aim of the transformer design is to obtain the dimensions of all the parts of the transformer based on the given specification, using available materials economically in order to achieve lower cost,reduced size and better operating performance. In this paper, the task of finding optimal design of single phase transformer has been formulated as nonlinear programming problem, so as to meet thespecification with the minimum cost and improve the efficiency. Four independent variables and two constraints are taken to meet the requirement of the design. The method utilizes Bacterial ForagingAlgorithm (BFA to provide optimum design of single phase transformer. The validity of the proposed method has been tested on a sample transformer and the simulation results obtained are compared with conventional method and Particle Swarm Optimization (PSO technique. The simulation results reveal that the proposed scheme determines the optimal variables of transformer along with the performance parameters efficiently.
Differential evolution and simulated annealing algorithms for mechanical systems design
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H. Saruhan
2014-09-01
Full Text Available In this study, nature inspired algorithms – the Differential Evolution (DE and the Simulated Annealing (SA – are utilized to seek a global optimum solution for ball bearings link system assembly weight with constraints and mixed design variables. The Genetic Algorithm (GA and the Evolution Strategy (ES will be a reference for the examination and validation of the DE and the SA. The main purpose is to minimize the weight of an assembly system composed of a shaft and two ball bearings. Ball bearings link system is used extensively in many machinery applications. Among mechanical systems, designers pay great attention to the ball bearings link system because of its significant industrial importance. The problem is complex and a time consuming process due to mixed design variables and inequality constraints imposed on the objective function. The results showed that the DE and the SA performed and obtained convergence reliability on the global optimum solution. So the contribution of the DE and the SA application to the mechanical system design can be very useful in many real-world mechanical system design problems. Beside, the comparison confirms the effectiveness and the superiority of the DE over the others algorithms – the SA, the GA, and the ES – in terms of solution quality. The ball bearings link system assembly weight of 634,099 gr was obtained using the DE while 671,616 gr, 728213.8 gr, and 729445.5 gr were obtained using the SA, the ES, and the GA respectively.
Jiang, P C; Chen, H
2006-01-01
VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.
Trends and challenges in VLSI technology scaling towards 100 nm
Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram
Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm
Design and Implementation of Navigation Algorithm for Intelligent Racing Car
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Praween Sinha
2011-02-01
Full Text Available Design and implementation of navigation algorithm for intelligent racing car. The paper describes the implementation of intelligent racing car that can recognize the track automatically to run onthe specifically designed complex racing track. The objective is to recognize and and modify the actual performance of the movements of the car during its pathway by getting information in real time from IRsensors in the system. The travel trajectory consists of continuous black line of about 25 millimeters in width, on a white background in order to have acceptable functioning. Analyzing of the sensor readingswas done during the travel, capturing data at the fixed sampling rate and this data was used as inputs to the newly developed algorithm to achieve corrections on the decision speed and control movements. Amicrocontroller assigns the required movement turn and speeds to optimize the performance in order to get a closer behavior as humans could do it without a vision system to catch its environment. The task of this work was to develop an efficient navigation algorithm and it has been successfully implemented in a Motorola S12X 16-bit microcontroller.
Design of PID Controller Simulator based on Genetic Algorithm
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Fahri VATANSEVER
2013-08-01
Full Text Available PID (Proportional Integral and Derivative controllers take an important place in the field of system controlling. Various methods such as Ziegler-Nichols, Cohen-Coon, Chien Hrones Reswick (CHR and Wang-Juang-Chan are available for the design of such controllers benefiting from the system time and frequency domain data. These controllers are in compliance with system properties under certain criteria suitable to the system. Genetic algorithms have become widely used in control system applications in parallel to the advances in the field of computer and artificial intelligence. In this study, PID controller designs have been carried out by means of classical methods and genetic algorithms and comparative results have been analyzed. For this purpose, a graphical user interface program which can be used for educational purpose has been developed. For the definite (entered transfer functions, the suitable P, PI and PID controller coefficients have calculated by both classical methods and genetic algorithms and many parameters and responses of the systems have been compared and presented numerically and graphically
Tele-Network Design Based on Queue Competition Algorithm
Institute of Scientific and Technical Information of China (English)
Huang Zhang-can; Wan Li-jun; Tang Tao; Chen Zheng-xu
2003-01-01
In this paper, we report research on how to design the tele-network. First of all, we defined the reliability of tele-network. According to the definition, we divide the whole reliability into two parts:the reliability of the mini-way and that of the whole system. Then we do algebra unintersection of the mini-way, deriving a function of reliability of tele-network. Also, we got a function of the cost of tele-network after analyzing the cost of arcs and points. Finally, we give a mathematical model to design a tele-network. For the algorithm, we define the distance of a network and adjacent area within certain boundaries . We present a new algorithm Queue Competition Algorithm(QCA)based on the adja cent area . The QCA correlates sequence of fitnesses in their fathergenerations with hunting zone of mutation and the number of individuals generated by mutation, making the stronger fitness in a small zone converge at a local extreme value, but the weaker one takes the advantage of lots of individuals and a big zone to hunt a new local extreme value. In this way, we get the overall extreme value. Numerical simulation shows that we can get the efficient hunting and exact solution by using QCA. The QCA efficient hunting and exact solution.
Online Optimal Controller Design using Evolutionary Algorithm with Convergence Properties
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Yousef Alipouri
2014-06-01
Full Text Available Many real-world applications require minimization of a cost function. This function is the criterion that figures out optimally. In the control engineering, this criterion is used in the design of optimal controllers. Cost function optimization has difficulties including calculating gradient function and lack of information about the system and the control loop. In this article, for the first time, gradient memetic evolutionary programming is proposed for minimization of non-convex cost functions that have been defined in control engineering. Moreover, stability and convergence of the proposed algorithm are proved. Besides, it is modified to be used in online optimization. To achieve this, the sign of the gradient function is utilized. For calculating the sign of the gradient, there is no need to know the cost-function’s shape. The gradient functions are estimated by the algorithm. The proposed algorithm is used to design a PI controller for nonlinear benchmark system CSTR (Continuous Stirred Tank Reactor by online and off-line approaches.
VLSI technology for smaller, cheaper, faster return link systems
Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John
1994-01-01
Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.
Efficient VLSI architecture for training radial basis function networks.
Fan, Zhe-Cheng; Hwang, Wen-Jyi
2013-03-19
This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
VLSI-based Video Event Triggering for Image Data Compression
Williams, Glenn L.
1994-01-01
Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.
Efficient VLSI Architecture for Training Radial Basis Function Networks
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Wen-Jyi Hwang
2013-03-01
Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Gravitation search algorithm: Application to the optimal IIR filter design
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Suman Kumar Saha
2014-01-01
Full Text Available This paper presents a global heuristic search optimization technique known as Gravitation Search Algorithm (GSA for the design of 8th order Infinite Impulse Response (IIR, low pass (LP, high pass (HP, band pass (BP and band stop (BS filters considering various non-linear characteristics of the filter design problems. This paper also adopts a novel fitness function in order to improve the stop band attenuation to a great extent. In GSA, law of gravity and mass interactions among different particles are adopted for handling the non-linear IIR filter design optimization problem. In this optimization technique, searcher agents are the collection of masses and interactions among them are governed by the Newtonian gravity and the laws of motion. The performances of the GSA based IIR filter designs have proven to be superior as compared to those obtained by real coded genetic algorithm (RGA and standard Particle Swarm Optimization (PSO. Extensive simulation results affirm that the proposed approach using GSA outperforms over its counterparts not only in terms of quality output, i.e., sharpness at cut-off, smaller pass band ripple, higher stop band attenuation, but also the fastest convergence speed with assured stability.
Genetic algorithms for optimal design and control of adaptive structures
Ribeiro, R; Dias-Rodrigues, J; Vaz, M
2000-01-01
Future High Energy Physics experiments require the use of light and stable structures to support their most precise radiation detection elements. These large structures must be light, highly stable, stiff and radiation tolerant in an environment where external vibrations, high radiation levels, material aging, temperature and humidity gradients are not negligible. Unforeseen factors and the unknown result of the coupling of environmental conditions, together with external vibrations, may affect the position stability of the detectors and their support structures compromising their physics performance. Careful optimization of static and dynamic behavior must be an essential part of the engineering design. Genetic Algorithms ( GA) belong to the group of probabilistic algorithms, combining elements of direct and stochastic search. They are more robust than existing directed search methods with the advantage of maintaining a population of potential solutions. There is a class of optimization problems for which Ge...
The Galileo Ground Segment Integrity Algorithms: Design and Performance
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Carlos Hernández Medel
2008-01-01
Full Text Available Galileo, the European Global Navigation Satellite System, will provide to its users highly accurate global positioning services and their associated integrity information. The element in charge of the computation of integrity messages within the Galileo Ground Mission Segment is the integrity processing facility (IPF, which is developed by GMV Aerospace and Defence. The main objective of this paper is twofold: to present the integrity algorithms implemented in the IPF and to show the achieved performance with the IPF software prototype, including aspects such as: implementation of the Galileo overbounding concept, impact of safety requirements on the algorithm design including the threat models for the so-called feared events, and finally the achieved performance with real GPS and simulated Galileo scenarios.
International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking
Shirur, Yasha; Prasad, Rekha
2013-01-01
This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.
Shape Design of Lifting body Based on Genetic Algorithm
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Yongyuan Li
2010-11-01
Full Text Available This paper briefly introduces the concept and history of lifting body, and puts forward a new method for the optimization of lifting body. This method has drawn lessons from the die line design of airplane is used to parametric numerical modeling for the lifting body, and extract the characterization of shape parameters as design variables, a combination of lifting body reentry vehicle aerodynamic conditions, aerodynamic heating, volumetric Rate and the stability of performance. Multi-objective hybrid genetic algorithm is adopted to complete the aerodynamic shape optimization and design of hypersonic lifting body vehicle when under more variable and constrained condition in order to obtain the Pareto optimal solution of Common Aero Vehicle shape.
Hardware Design and Simulation of Sobel Edge Detection Algorithm
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Sohag Kabir
2014-04-01
Full Text Available In this paper, a hardware system for Sobel Edge Detection Algorithm is designed and simulated for a 128 pixel, 8-bit monochrome line-scan camera. The system is designed to detect objects as they move along a conveyor belt in a manufacturing environment, the camera will observe dark objects on a light conveyor belt. The edge detector is required to detect horizontal and vertical edges using Sobel edge detection method. The Sobel operator requires 3 lines and takes 3 pixels per line, thus using a 3×3 input block to process each pixel. The centre pixel of the 3×3 pixel block can be classified as an edge point or otherwise by thresholding the value from the operator. The FPGA based Sobel edge detector is designed and simulated using Altera Quartus II 8.1 web edition by targeting Cyclone II development boards.
Optimal Design Of Existng Water Distribution Network Using Genetics Algorithms.
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A Saminu
2016-07-01
Full Text Available In this study EPANET, a widely used water distribution package was linked to OptiGa, a Visual Basic ActiveX control for implementation of genetic algorithm, through Visual Basic programming technique, to modify the computer software called OptiNetwork. OptiNetwork in its modifications, introduced means of selecting options for advanced genetic algorithm parameters (Top mate; Roulette cost; Random; Tournament methods; and one point crossover; two points crossover; uniform crossover methods and random seed number. Using Badarawa/Malali existing water distribution network consisting of 96 pipes of different materials, 75junctions, two tanks, and one overhead reservoir, and a source reservoir (i.e treatment plant from which water is pumped through a pumping main to the overhead reservoir and later distributed to the network by gravity .The modified software optiNetwork was applied to Badarawa / Malali networks distribution designs. The results obtained were compared with those obtained using commercial software package (OptiDesigner, The modified software has been able to obtained almost equal result with OptiDesigner software for the first optimization i.e before the application of advance GA, after the application of Advance GA It was observed that the least-cost design of $195,200.00 that satisfies the constraints requirements was obtained using optiNetwork, which is much lower than $435,118.00 obtained from OptiDesigner software. The results obtained show that the introduction of the advanced genetic parameters of OptiNetwork is justified. This is because, it has been able to improve the search method in terms of achieving the “least-cost” designed water distribution system that will supply sufficient water quantities at adequate pressure to the consumers.
二维DCT算法及其优化的VLSI设计%2-D DCT Algorithm and Its Optimized VLSI Design
Institute of Scientific and Technical Information of China (English)
魏本杰; 刘明业; 章晓莉
2006-01-01
提出了一种二维DCT算法及其优化的VLSI设计,即将二维DCT分离成2个一维DCT实现,只需一个一维DCT处理单元即可;进而通过对变换的系数矩阵进行化简,采用流水线技术,使用4个乘法器就可使电路达到高速;该电路结构具有模块化、布线简单、芯片面积小等优点,实验结果表明了VLSI设计的有效性.
Robust Bioinformatics Recognition with VLSI Biochip Microsystem
Lue, Jaw-Chyng L.; Fang, Wai-Chi
2006-01-01
A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.
Interleaver Design Method for Turbo Codes Based on Genetic Algorithm
Institute of Scientific and Technical Information of China (English)
Tan Ying; Sun Hong; Zhou Huai-bei
2004-01-01
This paper describes a new interleaver construction technique for turbo code. The technique searches as much as possible pseudo-random interleaving patterns under a certain condition using genetic algorithms(GAs). The new interleavers have the superiority of the S-random interleavers and this interleaver construction technique can reduce the time taken to generate pseudo-random interleaving patterns under a certain condition. Tbe results obtained indicate that the new interleavers yield an equal to or better performance than the Srandom interleavers. Compared to the S-random interleaver,this design requires a lower level of computational complexity.
Satellite constellation design with genetic algorithms based on system performance
Institute of Scientific and Technical Information of China (English)
Xueying Wang; Jun Li; Tiebing Wang; Wei An; Weidong Sheng
2016-01-01
Satelite constelation design for space optical sys-tems is essentialy a multiple-objective optimization problem. In this work, to tackle this chalenge, we first categorize the performance metrics of the space optical system by taking into account the system tasks (i.e., target detection and tracking). We then propose a new non-dominated sorting genetic algo-rithm (NSGA) to maximize the system surveilance perfor- mance. Pareto optimal sets are employed to deal with the conflicts due to the presence of multiple cost functions. Simulation results verify the validity and the improved per-formance of the proposed technique over benchmark meth-ods.
Design principles and algorithms for automated air traffic management
Erzberger, Heinz
1995-01-01
This paper presents design principles and algorithm for building a real time scheduler. The primary objective of the scheduler is to assign arrival aircraft to a favorable landing runway and schedule them to land at times that minimize delays. A further objective of the scheduler is to allocate delays between high altitude airspace far from the airport and low altitude airspace near the airport. A method of delay allocation is described that minimizes the average operating cost in the presence of errors in controlling aircraft to a specified landing time.
Conceptual space systems design using meta-heuristic algorithms
Kim, Byoungsoo
criteria. Two meta-heuristic optimization algorithms, Genetic Algorithms (GAs) and Simulated Annealing (SA), were used to optimize the formulated (simply bounded) Constrained Combinatorial Conceptual Space Systems Design Model. GAs and SA were demonstrated on the SAMPEX (Solar Anomalous & Magnetospheric Particle Explorer) Space System. The Conceptual Space Systems Design Model developed in this thesis can be used as an assessment tool to evaluate and validate Space System proposals.
Design Principles and Algorithms for Air Traffic Arrival Scheduling
Erzberger, Heinz; Itoh, Eri
2014-01-01
This report presents design principles and algorithms for building a real-time scheduler of arrival aircraft based on a first-come-first-served (FCFS) scheduling protocol. The algorithms provide the conceptual and computational foundation for the Traffic Management Advisor (TMA) of the Center/terminal radar approach control facilities (TRACON) automation system, which comprises a set of decision support tools for managing arrival traffic at major airports in the United States. The primary objective of the scheduler is to assign arrival aircraft to a favorable landing runway and schedule them to land at times that minimize delays. A further objective of the scheduler is to allocate delays between high-altitude airspace far away from the airport and low-altitude airspace near the airport. A method of delay allocation is described that minimizes the average operating cost in the presence of errors in controlling aircraft to a specified landing time. This report is a revision of an earlier paper first presented as part of an Advisory Group for Aerospace Research and Development (AGARD) lecture series in September 1995. The authors, during vigorous discussions over the details of this paper, felt it was important to the air-trafficmanagement (ATM) community to revise and extend the original 1995 paper, providing more detail and clarity and thereby allowing future researchers to understand this foundational work as the basis for the TMA's scheduling algorithms.
Library design using genetic algorithms for catalyst discovery and optimization
Clerc, Frederic; Lengliz, Mourad; Farrusseng, David; Mirodatos, Claude; Pereira, Sílvia R. M.; Rakotomalala, Ricco
2005-06-01
This study reports a detailed investigation of catalyst library design by genetic algorithm (GA). A methodology for assessing GA configurations is described. Operators, which promote the optimization speed while being robust to noise and outliers, are revealed through statistical studies. The genetic algorithms were implemented in GA platform software called OptiCat, which enables the construction of custom-made workflows using a tool box of operators. Two separate studies were carried out (i) on a virtual benchmark and (ii) on real surface response which is derived from HT screening. Additionally, we report a methodology to model a complex surface response by binning the search space in small zones that are then independently modeled by linear regression. In contrast to artificial neural networks, this approach allows one to obtain an explicit model in an analogical form that can be further used in Excel or entered in OptiCat to perform simulations. While speeding the implementation of a hybrid algorithm combining a GA with a knowledge-based extraction engine is described, while speeding up the optimization process by means of virtual prescreening the hybrid GA enables one to open the "black-box" by providing knowledge as a set of association rules.
MICRONEEDLE STRUCTURE DESIGN AND OPTIMIZATION USING GENETIC ALGORITHM
Directory of Open Access Journals (Sweden)
N. A. ISMAIL
2015-07-01
Full Text Available This paper presents a Genetic Algorithm (GA based microneedle design and analysis. GA is an evolutionary optimization technique that mimics the natural biological evolution. The design of microneedle structure considers the shape of microneedle, material used, size of the array, the base of microneedle, the lumen base, the height of microneedle, the height of the lumen, and the height of the drug container or reservoir. The GA is executed in conjunction with ANSYS simulation system to assess the design specifications. The GA uses three operators which are reproduction, crossover and mutation to manipulate the genetic composition of the population. In this research, the microneedle is designed to meet a number of significant specifications such as nodal displacement, strain energy, equivalent stress and flow rate of the fluid / drug that flow through its channel / lumen. A comparison study is conducted to investigate the design of microneedle structure with and without the implementation of GA model. The results showed that GA is able to optimize the design parameters of microneedle and is capable to achieve the required specifications with better performance.
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test
Directory of Open Access Journals (Sweden)
C. Wu
2011-06-01
Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.
Directory of Open Access Journals (Sweden)
MEGHANA A. HASAMNIS
2012-05-01
Full Text Available An Advanced Standard Encryption Algorithm (AES is widely used in modern consumer electronicproducts for security. The IEEE 802.15.4 Low-Rate wireless sensor networks also use AES algorithm wherelow power consumption is the priority. To reduce the time taken for encryption of huge data, the algorithm hasto be implemented in hardware. To meet the requirement for low area the algorithm has to be implemented insoftware. Hence, a balance has to be achieved between hardware and software implementations in terms of areaand speed, so as to improve the overall performance of the system. Also with the co-design methodology totalthermal power dissipation is reduced. In this paper, 128 bit AES algorithm is implemented with hardware incombination with software using Altera NIOS II Processor platform. Altera’s Quartus II environment is used fordesign of the system. Cyclone II FPGA is used as a development platform. Software program is written in C language. NIOS II ntegrated Development Environment (IDE is used to integrate hardware and software together. By adopting hardware / software co-design methodology for implementation of AES, results show that a onsiderable improvement in speed can be achieved as compared to software only approach. Further, the significant reduction in area is achieved as compared to hardware only approach. By the approach of co-design an optimized design in terms of speed and area is achieved and also the thermal power dissipation is reduced
Energy Technology Data Exchange (ETDEWEB)
Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)
2014-01-31
The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.
Optimal Design of RF Energy Harvesting Device Using Genetic Algorithm
Mori, T.; Sato, Y.; Adriano, R.; Igarashi, H.
2015-11-01
This paper presents optimal design of an RF energy harvesting device using genetic algorithm (GA). In the present RF harvester, a planar spiral antenna (PSA) is loaded with matching and rectifying circuits. On the first stage of the optimal design, the shape parameters of PSA are optimized using . Then, the equivalent circuit of the optimized PSA is derived for optimization of the circuits. Finally, the parameters of RF energy harvesting circuit are optimized to maximize the output power using GA. It is shown that the present optimization increases the output power by a factor of five. The manufactured energy harvester starts working when the input electric field is greater than 0.5 V/m.
A Novel Parser Design Algorithm Based on Artificial Ants
Maiti, Deepyaman; Konar, Amit; Ramadoss, Janarthanan
2008-01-01
This article presents a unique design for a parser using the Ant Colony Optimization algorithm. The paper implements the intuitive thought process of human mind through the activities of artificial ants. The scheme presented here uses a bottom-up approach and the parsing program can directly use ambiguous or redundant grammars. We allocate a node corresponding to each production rule present in the given grammar. Each node is connected to all other nodes (representing other production rules), thereby establishing a completely connected graph susceptible to the movement of artificial ants. Each ant tries to modify this sentential form by the production rule present in the node and upgrades its position until the sentential form reduces to the start symbol S. Successful ants deposit pheromone on the links that they have traversed through. Eventually, the optimum path is discovered by the links carrying maximum amount of pheromone concentration. The design is simple, versatile, robust and effective and obviates ...
Departure Traj ectory Design Based on Pareto Ant Colony Algorithm
Institute of Scientific and Technical Information of China (English)
SunFanrong; HanSongchen; QianGe
2016-01-01
Due to the ever-increasing air traffic flow,the influence of aircraft noise around the airport has become significant.As most airlines are trying to decrease operation cost,stringent requirements for more simple and effi-cient departure traj ectory are on a rise.Therefore,a departure traj ectory design was established for performance-based navigation technology,and a multi-obj ective optimization model was developed,with constraints of safety and noise influence,as well as optimization targets of efficiency and simplicity.An improved ant colony algorithm was then proposed to solve the optimization problem.Finally,an experiment was conducted using the Lanzhou ter-minal airspace operation data,and the results showed that the designed departure traj ectory was feasible and effi-cient in decreasing the aircraft noise influence.
Single Spin Logic Implementation of VLSI Adders
Shukla, Soumitra
2011-01-01
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.
Computational Tools and Algorithms for Designing Customized Synthetic Genes
Directory of Open Access Journals (Sweden)
Nathan eGould
2014-10-01
Full Text Available Advances in DNA synthesis have enabled the construction of artificial genes, gene circuits, and genomes of bacterial scale. Freedom in de-novo design of synthetic constructs provides significant power in studying the impact of mutations in sequence features, and verifying hypotheses on the functional information that is encoded in nucleic and amino acids. To aid this goal, a large number of software tools of variable sophistication have been implemented, enabling the design of synthetic genes for sequence optimization based on rationally defined properties. The first generation of tools dealt predominantly with singular objectives such as codon usage optimization and unique restriction site incorporation. Recent years have seen the emergence of sequence design tools that aim to evolve sequences toward combinations of objectives. The design of optimal protein coding sequences adhering to multiple objectives is computationally hard, and most tools rely on heuristics to sample the vast sequence design space. In this review we study some of the algorithmic issues behind gene optimization and the approaches that different tools have adopted to redesign genes and optimize desired coding features. We utilize test cases to demonstrate the efficiency of each approach, as well as identify their strengths and limitations.
A Parallel Genetic Algorithm for Automated Electronic Circuit Design
Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris
2000-01-01
Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency
A Simple Application and Design of Genetic Algorithm in Card Problem
Institute of Scientific and Technical Information of China (English)
顾鹏程
2016-01-01
According to traditional card problem solving which is based on the idea of genetic algorithm(GA), a set of algorithms is designed to find final solution. For each process in genetic algorithm, including choices of fitness function, parameters deter-mination and coding scheme selection,classic algorithm is used to realize the various steps, and ultimately to find solution of problems.
Application of Modified Genetic Algorithm to Optimal Design of Supporting Structure
Institute of Scientific and Technical Information of China (English)
ZHOU Rui-zhong; PAN Shi-wei
2003-01-01
The modified genetic algorithm was used for the optimal design of supporting structure in deep pits.Based on the common genetic algorithm, using niche technique and reserving the optimum individual the modified genetic algorithm was presented. By means of the practical engineering, the modified genetic algorithm not only has more expedient convergence, but also can enhance security and operation efficiency.
Wavelength-encoded OCDMA system using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal
2007-07-01
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
Design and Analysis of New Symmetric Block Cipher Algorithm
Directory of Open Access Journals (Sweden)
KALAICHELVI V
2015-10-01
Full Text Available Cryptography provides many methods and techniques for secure communication. Currently there are many encryption/decryption algorithms such as DES, AES (Rijndael, Blowfish, etc., are published. However, they are fairly complex and require that one spend a lot of time to comprehend and implement them. This paper introduces simple encryption /decryption algorithm that works fast and fairly secure. In this paper, a new symmetric block cipher algorithm has been developed and is compared with the existing popular algorithms. Simulation results are given to demonstrate the effectiveness of each algorithm. Blowfish and the newly developed algorithms exhibit better performance than other popular existing algorithms.
Performance Trend of Different Algorithms for Structural Design Optimization
Patnaik, Surya N.; Coroneos, Rula M.; Guptill, James D.; Hopkins, Dale A.
1996-01-01
Nonlinear programming algorithms play an important role in structural design optimization. Fortunately, several algorithms with computer codes are available. At NASA Lewis Research Center, a project was initiated to assess performance of different optimizers through the development of a computer code CometBoards. This paper summarizes the conclusions of that research. CometBoards was employed to solve sets of small, medium and large structural problems, using different optimizers on a Cray-YMP8E/8128 computer. The reliability and efficiency of the optimizers were determined from the performance of these problems. For small problems, the performance of most of the optimizers could be considered adequate. For large problems however, three optimizers (two sequential quadratic programming routines, DNCONG of IMSL and SQP of IDESIGN, along with the sequential unconstrained minimizations technique SUMT) outperformed others. At optimum, most optimizers captured an identical number of active displacement and frequency constraints but the number of active stress constraints differed among the optimizers. This discrepancy can be attributed to singularity conditions in the optimization and the alleviation of this discrepancy can improve the efficiency of optimizers.
Performance-Based Seismic Design of Steel Frames Utilizing Colliding Bodies Algorithm
Directory of Open Access Journals (Sweden)
H. Veladi
2014-01-01
Full Text Available A pushover analysis method based on semirigid connection concept is developed and the colliding bodies optimization algorithm is employed to find optimum seismic design of frame structures. Two numerical examples from the literature are studied. The results of the new algorithm are compared to the conventional design methods to show the power or weakness of the algorithm.
Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W
2006-01-01
We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.
Design and Performance Evaluation of Sequence Partition Algorithms
Institute of Scientific and Technical Information of China (English)
Bing Yang; Jing Chen; En-Yue Lu; Si-Qing Zheng
2008-01-01
Tradeoffs between time complexities and solution optimalities are important when selecting algorithms for an NP-hard problem in different applications. Also, the distinction between theoretical upper bound and actual solution optimality for realistic instances of an NP-hard problem is a factor in selecting algorithms in practice. We consider the problem of partitioning a sequence of n distinct numbers into minimum number of monotone (increasing or decreasing) case. We introduce a new algorithm, the modified version of the Yehuda-Fogel algorithm, that computes a solution of no on three algorithms, a known approximation algorithm of approximation ratio 1.71 and time complexity O(n3), a known greedy algorithm of time complexity O(n1.5 log n), and our new modified Yehuda-Fogel algorithm. Our results show that the solutions computed by the greedy algorithm and the modified Yehuda-Fogel algorithm are close to that computed by the approximation algorithm even though the theoretical worst-case error bounds of these two algorithms are not proved to be within a constant time of the optimal solution. Our study indicates that for practical use the greedy algorithm and the modified Yehuda-Fogel algorithm can be good choices if the running time is a major concern.
Singh, R.; Verma, H. K.
2013-12-01
This paper presents a teaching-learning-based optimization (TLBO) algorithm to solve parameter identification problems in the designing of digital infinite impulse response (IIR) filter. TLBO based filter modelling is applied to calculate the parameters of unknown plant in simulations. Unlike other heuristic search algorithms, TLBO algorithm is an algorithm-specific parameter-less algorithm. In this paper big bang-big crunch (BB-BC) optimization and PSO algorithms are also applied to filter design for comparison. Unknown filter parameters are considered as a vector to be optimized by these algorithms. MATLAB programming is used for implementation of proposed algorithms. Experimental results show that the TLBO is more accurate to estimate the filter parameters than the BB-BC optimization algorithm and has faster convergence rate when compared to PSO algorithm. TLBO is used where accuracy is more essential than the convergence speed.
District Heating Network Design and Configuration Optimization with Genetic Algorithm
Directory of Open Access Journals (Sweden)
Hongwei Li
2013-12-01
Full Text Available In this paper, the configuration of a district heating network which connects from the heating plant to the end users is optimized. Each end user in the network represents a building block. The connections between the heat generation plant and the end users are represented with mixed integer and the pipe friction and heat loss formulations are non-linear. In order to find the optimal district heating network configuration, genetic algorithm which handles the mixed integer nonlinear programming problem is chosen. The network configuration is represented with binary and integer encoding and is optimized in terms of the net present cost. The optimization results indicates that the optimal DH network configuration is determined by multiple factors such as the consumer heating load, the distance between the heating plant to the consumer, the design criteria regarding the pressure and temperature limitation, as well as the corresponding network heat loss.
Entropy-Based Search Algorithm for Experimental Design
Malakar, N K
2010-01-01
The scientific method relies on the iterated processes of inference and inquiry. The inference phase consists of selecting the most probable models based on the available data; whereas the inquiry phase consists of using what is known about the models to select the most relevant experiment. Optimizing inquiry involves searching the parameterized space of experiments to select the experiment that promises, on average, to be maximally informative. In the case where it is important to learn about each of the model parameters, the relevance of an experiment is quantified by Shannon entropy of the distribution of experimental outcomes predicted by a probable set of models. If the set of potential experiments is described by many parameters, we must search this high-dimensional entropy space. Brute force search methods will be slow and computationally expensive. We present an entropy-based search algorithm, called nested entropy sampling, to select the most informative experiment for efficient experimental design. ...
Social Welfare in Algorithmic Mechanism Design Without Money
DEFF Research Database (Denmark)
Filos-Ratsikas, Aris
strategically, in order to manipulate the outcomes in their favor. In this thesis, we consider the well-known objective of social welfare, i.e. the sum of individual utilities as the social objective and following the agenda of algorithmic mechanism design, we study how well our objectives can be approximated......-sided matching problem. We study both truthful and non-truthful mechanisms and prove that some very well-known mechanisms in literature are asymptotically optimal among all mechanisms. Finally, in the last part of the thesis, we study social welfare maximization for the problem of allocating divisible items...... by mechanisms that prevent or predict the effects of the agents' strategic nature. We adopt two approaches; on one hand, we study truthful mechanisms and bound their approximation ratios and on the other hand, we study the effect of strategic play on non-truthful mechanisms, by bounding their price of anarchy...
Optimal design of pressure vessel using an improved genetic algorithm
Institute of Scientific and Technical Information of China (English)
Peng-fei LIU; Ping XU; Shu-xin HAN; Jin-yang ZHENG
2008-01-01
As the idea of simulated annealing(SA) is introduced into the fitness function,an improved genetic algorithm(GA) is proposed to perform the optimal design of a pressure vessel which aims to attain the minimum weight under burst pressure constraint.The actual burst pressure is calculated using the arc-length and restart analysis in finite element analysis(FEA).A penalty function in the fitness function is proposed to denl with the constrained problem.The erects of the population size and the number of generations in the GA on the weight and burst pressure of the vessel are explored.The optimization results using the proposed GA are also compared with those using the simple GA and the conventional Monte Carlo method.
Energy-aware system design algorithms and architectures
Kyung, Chong-Min
2011-01-01
Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore’s law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from ...
Directory of Open Access Journals (Sweden)
Tugrul Talaslioglu
2009-01-01
Full Text Available A new genetic algorithm (GA methodology, Bipopulation-Based Genetic Algorithm with Enhanced Interval Search (BGAwEIS, is introduced and used to optimize the design of truss structures with various complexities. The results of BGAwEIS are compared with those obtained by the sequential genetic algorithm (SGA utilizing a single population, a multipopulation-based genetic algorithm (MPGA proposed for this study and other existing approaches presented in literature. This study has two goals: outlining BGAwEIS's fundamentals and evaluating the performances of BGAwEIS and MPGA. Consequently, it is demonstrated that MPGA shows a better performance than SGA taking advantage of multiple populations, but BGAwEIS explores promising solution regions more efficiently than MPGA by exploiting the feasible solutions. The performance of BGAwEIS is confirmed by better quality degree of its optimal designations compared to algorithms proposed here and described in literature.
Efficient VLSI architecture of CAVLC decoder with power optimized
Institute of Scientific and Technical Information of China (English)
CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min
2009-01-01
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.
Efficient Genetic Algorithm sets for optimizing constrained building design problem
National Research Council Canada - National Science Library
Wright, Jonathan; Alajmi, Ali
2016-01-01
.... This requires trying large possible solutions which need heuristic optimization algorithms. A comparison between several heuristic optimization algorithms showed that Genetic Algorithm (GA) is robust on getting the optimum(s) simulation ( Wetter and Wright, 2004; Brownlee et al., 2011; Bichiou and Krarti, 2011; Sahu et al., 2012 ) while the building simulat...
Development of hybrid genetic algorithms for product line designs.
Balakrishnan, P V Sundar; Gupta, Rakesh; Jacob, Varghese S
2004-02-01
In this paper, we investigate the efficacy of artificial intelligence (AI) based meta-heuristic techniques namely genetic algorithms (GAs), for the product line design problem. This work extends previously developed methods for the single product design problem. We conduct a large scale simulation study to determine the effectiveness of such an AI based technique for providing good solutions and bench mark the performance of this against the current dominant approach of beam search (BS). We investigate the potential advantages of pursuing the avenue of developing hybrid models and then implement and study such hybrid models using two very distinct approaches: namely, seeding the initial GA population with the BS solution, and employing the BS solution as part of the GA operator's process. We go on to examine the impact of two alternate string representation formats on the quality of the solutions obtained by the above proposed techniques. We also explicitly investigate a critical managerial factor of attribute importance in terms of its impact on the solutions obtained by the alternate modeling procedures. The alternate techniques are then evaluated, using statistical analysis of variance, on a fairy large number of data sets, as to the quality of the solutions obtained with respect to the state-of-the-art benchmark and in terms of their ability to provide multiple, unique product line options.
低成本可调FFT处理器的超大规模集成电路设计%Low Cost VLSI Design of a Flexible FFT Processor
Institute of Scientific and Technical Information of China (English)
戴亦奇
2011-01-01
In this paper, a radix-22/23 based pipeline structure is presented, in order to implement a low-cost VLSI fast Fourier transform （FFT） processor. As well as reducing the steps of normal complex multiplications, it minimizes the memory words to get the FFT results with the single-path delay feedback （SDF） memory access method. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements.%文章提出了一种以基-22／23为基础的流水线结构，用以实现低成本、超大规模集成电路（VLSI）的快速傅里叶变换（FFT）处理器设计。该处理器在减少普通复数乘法器级数的同时，通过单路延时反馈（SDF）存取方式，以最少的存储字来获得FFT结果。对于数据通路，我们采用了混合浮点的数据缩放方式，在保证信噪比的同时，降低了数据长度和RAM容量的需求。
Directory of Open Access Journals (Sweden)
Hyo Seon Park
2014-01-01
Full Text Available Since genetic algorithm-based optimization methods are computationally expensive for practical use in the field of structural optimization, a resizing technique-based hybrid genetic algorithm for the drift design of multistory steel frame buildings is proposed to increase the convergence speed of genetic algorithms. To reduce the number of structural analyses required for the convergence, a genetic algorithm is combined with a resizing technique that is an efficient optimal technique to control the drift of buildings without the repetitive structural analysis. The resizing technique-based hybrid genetic algorithm proposed in this paper is applied to the minimum weight design of three steel frame buildings. To evaluate the performance of the algorithm, optimum weights, computational times, and generation numbers from the proposed algorithm are compared with those from a genetic algorithm. Based on the comparisons, it is concluded that the hybrid genetic algorithm shows clear improvements in convergence properties.
Application of Particle Swarm Optimization Algorithm in Design of Multilayered Planar Shielding Body
Institute of Scientific and Technical Information of China (English)
FUJiwei; HOUChaozhen; DOULihua
2005-01-01
Based on the basic electromagnetic wave propagation theory in this article, the Particle swarm optimization algorithm (PSO) is used in the design of the multilayered composite materials and the thickness of shielding body by the existent multilayered planar composite elec-tromagnetic shielding materials model, the different shielding materials of each layer can be designed under some kinds of circumstances: the prespecified Shielding effectiveness (SE), different incident angle and the prespecified band of frequencies. Finally the algorithm is simulated. At the same time the similar procedure can be implemented by Genetic algorithm (GA). The results acquired by particle swarm optimization algorithm are compared with there sults acquired by the genetic algorithm. The results indicate that: the particle swarm optimization algorithm is much better than the genetic algorithm not only in convergence speed but also in simplicity. So a more effective method (Particle Swarm Optimization algorithm) is offered for the design of the multilayered composite shielding materials.
VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless
Directory of Open Access Journals (Sweden)
Di Wu
2010-01-01
Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.
New approach to the design of digital algorithms for electric power measurements
Energy Technology Data Exchange (ETDEWEB)
Kezunovic, M. (Texas A and M Univ., TX (US)); Perunicic, B. (Univ. of Sarajevo (YU))
1991-04-01
This paper introduces a new approach to the design of digital algorithms for electric power measurements. Digital algorithms for electric power measurements are represented as 2D digital FIR filters applied on voltage and current samples. Based on this approach, a new technique for algorithm design is developed. As the main advantage, the technique provides a convenient way to design new algorithms for measuring the electric power components according to various definitions in both sinusoidal and non-sinusoidal conditions. Several new algorithms are derived by using the proposed design technique. The existing algorithms for power measurements are also derived by using the new approach. The algorithm performance is tested using actual signal recordings.
Designing and implementing of improved cryptographic algorithm using modular arithmetic theory
Directory of Open Access Journals (Sweden)
Maryam Kamarzarrin
2015-05-01
Full Text Available Maintaining the privacy and security of people information are two most important principles of electronic health plan. One of the methods of creating privacy and securing of information is using Public key cryptography system. In this paper, we compare two algorithms, Common And Fast Exponentiation algorithms, for enhancing the efficiency of public key cryptography. We express that a designed system by Fast Exponentiation Algorithm has high speed and performance but low power consumption and space occupied compared with Common Exponentiation algorithm. Although designed systems by Common Exponentiation algorithm have slower speed and lower performance, designing by this algorithm has less complexity, and easier designing compared with Fast Exponentiation algorithm. In this paper, we will try to examine and compare two different methods of exponentiation, also observe performance Impact of these two approaches in the form of hardware with VHDL language on FPGA.
Adaptive symbiotic organisms search (SOS algorithm for structural design optimization
Directory of Open Access Journals (Sweden)
Ghanshyam G. Tejani
2016-07-01
Full Text Available The symbiotic organisms search (SOS algorithm is an effective metaheuristic developed in 2014, which mimics the symbiotic relationship among the living beings, such as mutualism, commensalism, and parasitism, to survive in the ecosystem. In this study, three modified versions of the SOS algorithm are proposed by introducing adaptive benefit factors in the basic SOS algorithm to improve its efficiency. The basic SOS algorithm only considers benefit factors, whereas the proposed variants of the SOS algorithm, consider effective combinations of adaptive benefit factors and benefit factors to study their competence to lay down a good balance between exploration and exploitation of the search space. The proposed algorithms are tested to suit its applications to the engineering structures subjected to dynamic excitation, which may lead to undesirable vibrations. Structure optimization problems become more challenging if the shape and size variables are taken into account along with the frequency. To check the feasibility and effectiveness of the proposed algorithms, six different planar and space trusses are subjected to experimental analysis. The results obtained using the proposed methods are compared with those obtained using other optimization methods well established in the literature. The results reveal that the adaptive SOS algorithm is more reliable and efficient than the basic SOS algorithm and other state-of-the-art algorithms.
Kanagaraj, G.; Ponnambalam, S. G.; Jawahar, N.; Mukund Nilakantan, J.
2014-10-01
This article presents an effective hybrid cuckoo search and genetic algorithm (HCSGA) for solving engineering design optimization problems involving problem-specific constraints and mixed variables such as integer, discrete and continuous variables. The proposed algorithm, HCSGA, is first applied to 13 standard benchmark constrained optimization functions and subsequently used to solve three well-known design problems reported in the literature. The numerical results obtained by HCSGA show competitive performance with respect to recent algorithms for constrained design optimization problems.
Target Impact Detection Algorithm Using Computer-aided Design (CAD) Model Geometry
2014-09-01
UNCLASSIFIED AD-E403 558 Technical Report ARMET-TR-13024 TARGET IMPACT DETECTION ALGORITHM USING COMPUTER-AIDED DESIGN ( CAD ...DETECTION ALGORITHM USING COMPUTER-AIDED DESIGN ( CAD ) MODEL GEOMETRY 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6...This report documents a method and algorithm to export geometry from a three-dimensional, computer-aided design ( CAD ) model in a format that can be
A Library of Optimization Algorithms for Organizational Design
2005-01-01
platform m. Ril = resource requirement of type l for task i. T = mission completion time found using a heuristic algorithm (or set to infinity). 0 = task...equal to the maximum among the completion times of all tasks. It is also not greater than the solution obtained by a heuristic algorithm . Therefore...Luenberger. Linear and Nonlinear Programming. 1984 [Madsen et al., 1995] O.B.G. Madsen et al. A Heuristic Algorithm for a Dial-a-ride Problem with Time
Optical Design of Multilayer Achromatic Waveplate by Simulated Annealing Algorithm
Institute of Scientific and Technical Information of China (English)
Jun Ma; Jing-Shan Wang; Carsten Denker; Hai-Min Wang
2008-01-01
We applied a Monte Carlo method-simulated annealing algorithm-to carry out the design of multilayer achromatic waveplate. We present solutions for three-, six-and ten-layer achromatic waveplates. The optimized retardance settings are found to be 89°51'39"±0°33'37" and 89°54'46"±0°22'4" for the six-and ten-layer waveplates, respectively, for a wavelength range from 1000nm to 1800nm. The polarimetric properties of multilayer waveplates are investigated based on several numerical experiments. In contrast to previously proposed three-layer achromatic waveplate, the fast axes of the new six-and ten-layer achromatic waveplate remain at fixed angles, independent of the wavelength. Two applications of multilayer achromatic waveplate are discussed, the general-purpose phase shifter and the birefringent filter in the Infrared Imaging Magnetograph (IRIM) system of the Big Bear Solar Observatory (BBSO). We also checked an experimental method to measure the retardance of waveplates.
The use of a genetic algorithm in optical thin film design and optimisation
Directory of Open Access Journals (Sweden)
Efrem K. Ejigu
2010-07-01
Full Text Available We used a genetic algorithm in the design and optimisation of optical thin films and present the effects of the choice of variables, refractive index and optical thickness, in both applications of this algorithm, in this paper. The Fourier transform optical thin film design method was used to create a starting population, which was later optimised by the genetic algorithm. In the genetic algorithm design application, the effect of the choice of variable was not distinct, as it depended on the type of design specification. In the genetic algorithm optimisation application, the choice of refractive index as a variable showed a better performance than that of optical thickness. The results of this study indicate that a genetic algorithm is more effective in the design application than in the optimisation application of optical thin film synthesis.
A new algorithm for designing developable Bézier surfaces
Institute of Scientific and Technical Information of China (English)
ZHANG Xing-wang; WANG Guo-jin
2006-01-01
A new algorithm is presented that generates developable Bézier surfaces through a Bézier curve called a directrix. The algorithm is based on differential geometry theory on necessary and sufficient conditions for a surface which is developable, and on degree evaluation formula for parameter curves and linear independence for Bernstein basis. No nonlinear characteristic equations have to be solved. Moreover the vertex for a cone and the edge of regression for a tangent surface can be obtained easily.Aumann's algorithm for developable surfaces is a special case of this paper.
Roth, J. P.
1972-01-01
Methods for development of logic design together with algorithms for failure testing, a method for design of logic for ultra-large-scale integration, extension of quantum calculus to describe the functional behavior of a mechanism component-by-component and to computer tests for failures in the mechanism using the diagnosis algorithm, and the development of an algorithm for the multi-output 2-level minimization problem are discussed.
Boumediene ALLAOUA; Laoufi, Abdellah; Brahim GASBAOUI; Nasri, Abdelfatah; Abdessalam ABDERRAHMANI
2008-01-01
In this paper, an intelligent controller of the DC (Direct current) Motor drive is designed using fuzzy logic-genetic algorithms optimization. First, a controller is designed according to fuzzy rules such that the systems are fundamentally robust. To obtain the globally optimal values, parameters of the fuzzy controller are improved by genetic algorithms optimization model. Computer MATLAB work space demonstrate that the fuzzy controller associated to the genetic algorithms approach became ve...
Non-dominated Sorting Genetic Algorithms for Heterogeneous Embedded System Design
Directory of Open Access Journals (Sweden)
A. K. Rath
2006-01-01
Full Text Available The design of complex embedded systems involves the simultaneous optimization of several conflicting and competing objectives. Instead of a single global optimal solution, there exist a set of Pareto optimal solutions. In this study we have used a multi-objective evolutionary optimization algorithms called non-dominated sorting genetic algorithm (NSGA, which will suit to the requirements of designing a complex heterogeneous embedded system. Further, the algorithm is rigorously tested using Video Codec as a case study
Optimal design of low-density SNP arrays for genomic prediction: algorithm and applications
Low-density (LD) single nucleotide polymorphism (SNP) arrays provide a cost-effective solution for genomic prediction and selection, but algorithms and computational tools are needed for their optimal design. A multiple-objective, local optimization (MOLO) algorithm was developed for design of optim...
ALGORITHMIC FACILITIES AND SOFTWARE FOR VIRTUAL DESIGN OF ANTI-BLOCK AND COUNTER-SLIPPING SYSTEMS
Directory of Open Access Journals (Sweden)
N. N. Hurski
2009-01-01
Full Text Available The paper considers algorithms of designing a roadway covering for virtual test of mobile machine movement dynamics; an algorithm of forming actual values of forces/moments in «road–wheel–car» contact and their derivatives, and also a software for virtual designing of mobile machine dynamics.
Theory, Design, and Algorithms for Optimal Control of wireless Networks
2010-06-09
significantly outperform existing protocols (such as AODV ) in terms of total network cost Furthermore, we have shown that even when components of our...achieved through distributed control algorithms that jointly optimize power control, routing , and congestion factors. A second stochastic model approach...updates the network queue state, node-transmission powers amongst others, allowing for power control, scheduling, and routing algorithms to maximize
DESIGN AND EXAMINATION OF ALGORITHMS FOR SOLVING THE KNAPSACK PROBLEM
Directory of Open Access Journals (Sweden)
S. Kantsedal
2015-07-01
Full Text Available The use of methods of branches and boundaries as well as the methods of dynamic programming at solving the problem of «knapsack» is grounded. The main concepts are expounded. The methods and algorithms development for solving the above specified problem are described. Recommendations on practical application of constructed algorithms based on their experimental investigation and carrying out charactheristics comparison are presented.
VLSI digital PSK demodulator for space communication
Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten
1993-02-01
This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.
Directory of Open Access Journals (Sweden)
Fazal NOORBASHA
2012-08-01
Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.
Digital Image Encryption Algorithm Design Based on Genetic Hyperchaos
Directory of Open Access Journals (Sweden)
Jian Wang
2016-01-01
Full Text Available In view of the present chaotic image encryption algorithm based on scrambling (diffusion is vulnerable to choosing plaintext (ciphertext attack in the process of pixel position scrambling, we put forward a image encryption algorithm based on genetic super chaotic system. The algorithm, by introducing clear feedback to the process of scrambling, makes the scrambling effect related to the initial chaos sequence and the clear text itself; it has realized the image features and the organic fusion of encryption algorithm. By introduction in the process of diffusion to encrypt plaintext feedback mechanism, it improves sensitivity of plaintext, algorithm selection plaintext, and ciphertext attack resistance. At the same time, it also makes full use of the characteristics of image information. Finally, experimental simulation and theoretical analysis show that our proposed algorithm can not only effectively resist plaintext (ciphertext attack, statistical attack, and information entropy attack but also effectively improve the efficiency of image encryption, which is a relatively secure and effective way of image communication.
Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.
Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert
2004-01-01
Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.
Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.
1987-01-01
A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.
Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses
Directory of Open Access Journals (Sweden)
Shriram Raghunathan
2011-05-01
Full Text Available Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms.
A Metropolis algorithm combined with Nelder-Mead Simplex applied to nuclear reactor core design
Energy Technology Data Exchange (ETDEWEB)
Sacco, Wagner F. [Depto. de Modelagem Computacional, Instituto Politecnico, Universidade do Estado do Rio de Janeiro, R. Alberto Rangel, s/n, P.O. Box 972285, Nova Friburgo, RJ 28601-970 (Brazil)], E-mail: wfsacco@iprj.uerj.br; Filho, Hermes Alves; Henderson, Nelio [Depto. de Modelagem Computacional, Instituto Politecnico, Universidade do Estado do Rio de Janeiro, R. Alberto Rangel, s/n, P.O. Box 972285, Nova Friburgo, RJ 28601-970 (Brazil); Oliveira, Cassiano R.E. de [Nuclear and Radiological Engineering Program, George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405 (United States)
2008-05-15
A hybridization of the recently introduced Particle Collision Algorithm (PCA) and the Nelder-Mead Simplex algorithm is introduced and applied to a core design optimization problem which was previously attacked by other metaheuristics. The optimization problem consists in adjusting several reactor cell parameters, such as dimensions, enrichment and materials, in order to minimize the average peak-factor in a three-enrichment-zone reactor, considering restrictions on the average thermal flux, criticality and sub-moderation. The new metaheuristic performs better than the genetic algorithm, particle swarm optimization, and the Metropolis algorithms PCA and the Great Deluge Algorithm, thus demonstrating its potential for other applications.
Design methodology for optimal hardware implementation of wavelet transform domain algorithms
Johnson-Bey, Charles; Mickens, Lisa P.
2005-05-01
The work presented in this paper lays the foundation for the development of an end-to-end system design methodology for implementing wavelet domain image/video processing algorithms in hardware using Xilinx field programmable gate arrays (FPGAs). With the integration of the Xilinx System Generator toolbox, this methodology will allow algorithm developers to design and implement their code using the familiar MATLAB/Simulink development environment. By using this methodology, algorithm developers will not be required to become proficient in the intricacies of hardware design, thus reducing the design cycle and time-to-market.
Application of an imperialist competitive algorithm to the design of a linear induction motor
Energy Technology Data Exchange (ETDEWEB)
Lucas, Caro [Center of Excellence, Control and Intelligent Processing, School of Electrical and Computer Engineering, University of Tehran, Tehran 4563-11155 (Iran, Islamic Republic of); Nasiri-Gheidari, Zahra, E-mail: z_nasiri_gh@yahoo.co [School of Electrical and Computer Eng., University of Tehran, Tehran 4563-11155 (Iran, Islamic Republic of); Tootoonchian, Farid [Department of Electrical Engineering, Iran University of Science and Technology, Tehran 16846-13114 (Iran, Islamic Republic of)
2010-07-15
In this paper a novel optimization algorithm based on imperialist competitive algorithm (ICA) is used for the design of a low speed single sided linear induction motor (LIM). This type of motors is used increasingly in industrial process specially in transportation systems. In these applications having high efficiency with high power factor is very important. So in this paper the objective function of design is presented considering both efficiency and power factor. Finally the results of ICA are compared with the ones of genetic algorithm and conventional design. Comparison shows the success of ICA for design of LIMs.
A fuzzy simulated evolution algorithm for integrated manufacturing system design
Directory of Open Access Journals (Sweden)
Michael Mutingi
2013-04-01
Full Text Available Integrated cell formation and layout (CFLP is an extended application of the group technology philosophy in which machine cells and cell layout are addressed simultaneously. The aim of this technological innovation is to improve both productivity and flexibility in modern manufacturing industry. However, due to its combinatorial complexity, the cell formation and layout problem is best solved by heuristic and metaheuristic approaches. As CFLP is prevalent in manufacturing industry, developing robust and efficient solution methods for the problem is imperative. This study seeks to develop a fuzzy simulated evolution algorithm (FSEA that integrates fuzzy-set theoretic concepts and the philosophy of constructive perturbation and evolution. Deriving from the classical simulated evolution algorithm, the search efficiency of the major phases of the algorithm is enhanced, including initialization, evaluation, selection and reconstruction. Illustrative computational experiments based on existing problem instances from the literature demonstrate the utility and the strength of the FSEA algorithm developed in this study. It is anticipated in this study that the application of the algorithm can be extended to other complex combinatorial problems in industry.
Design and Implementation of Image Encryption Algorithm Using Chaos
Directory of Open Access Journals (Sweden)
Sandhya Rani M.H.
2014-06-01
Full Text Available Images are widely used in diverse areas such as medical, military, science, engineering, art, advertising, entertainment, education as well as training, increasing the use of digital techniques for transmitting and storing images. So maintaining the confidentiality and integrity of images has become a major concern. This makes encryption necessary. The pixel values of neighbouring pixels in a plain image are strongly correlated. The proposed algorithm breaks this correlation increasing the entropy. Correlation is reduced by changing the pixel position this which is called confusion. Histogram is equalized by changing the pixel value this which is called diffusion. The proposed method of encryption algorithm is based on chaos theory. The plain-image is divided into blocks and then performs three levels of shuffling using different chaotic maps. In the first level the pixels within the block are shuffled. In the second level the blocks are shuffled and in the third level all the pixels in an image are shuffled. Finally the shuffled image is diffused using a chaotic sequence generated using symmetric keys, to produce the ciphered image for transmission. The experimental result demonstrates that the proposed algorithm can be used successfully to encrypt/decrypt the images with the secret keys. The analysis of the algorithm also shows that the algorithm gives larger key space and a high key sensitivity. The encrypted image has good encryption effect, information entropy and low correlation coefficient.
Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing
Khachab, Nabil Ibrahim
1990-01-01
The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.
Using a Genetic Algorithm to Design Nuclear Electric Spacecraft
Pannell, William P.
2003-01-01
The basic approach to to design nuclear electric spacecraft is to generate a group of candidate designs, see how "fit" the design are, and carry best design forward to the next generation. Some designs eliminated, some randomly modified and carried forward.
Optimum Performance-Based Seismic Design Using a Hybrid Optimization Algorithm
Directory of Open Access Journals (Sweden)
S. Talatahari
2014-01-01
Full Text Available A hybrid optimization method is presented to optimum seismic design of steel frames considering four performance levels. These performance levels are considered to determine the optimum design of structures to reduce the structural cost. A pushover analysis of steel building frameworks subject to equivalent-static earthquake loading is utilized. The algorithm is based on the concepts of the charged system search in which each agent is affected by local and global best positions stored in the charged memory considering the governing laws of electrical physics. Comparison of the results of the hybrid algorithm with those of other metaheuristic algorithms shows the efficiency of the hybrid algorithm.
An algorithm for motif-based network design
Mäki-Marttunen, Tuomo
2016-01-01
A determinant property of the structure of a biological network is the distribution of local connectivity patterns, i.e., network motifs. In this work, a method for creating directed, unweighted networks while promoting a certain combination of motifs is presented. This motif-based network algorithm starts with an empty graph and randomly connects the nodes by advancing or discouraging the formation of chosen motifs. The in- or out-degree distribution of the generated networks can be explicitly chosen. The algorithm is shown to perform well in producing networks with high occurrences of the targeted motifs, both ones consisting of 3 nodes as well as ones consisting of 4 nodes. Moreover, the algorithm can also be tuned to bring about global network characteristics found in many natural networks, such as small-worldness and modularity.
DEFF Research Database (Denmark)
Nica, Florin Valentin Traian; Ritchie, Ewen; Leban, Krisztina Monika
2013-01-01
, genetic algorithm and particle swarm are shortly presented in this paper. These two algorithms are tested to determine their performance on five different benchmark test functions. The algorithms are tested based on three requirements: precision of the result, number of iterations and calculation time......Nowadays the requirements imposed by the industry and economy ask for better quality and performance while the price must be maintained in the same range. To achieve this goal optimization must be introduced in the design process. Two of the best known optimization algorithms for machine design....... Both algorithms are also tested on an analytical design process of a Transverse Flux Permanent Magnet Generator to observe their performances in an electrical machine design application....
DEFF Research Database (Denmark)
Nica, Florin Valentin Traian; Ritchie, Ewen; Leban, Krisztina Monika
2013-01-01
, genetic algorithm and particle swarm are shortly presented in this paper. These two algorithms are tested to determine their performance on five different benchmark test functions. The algorithms are tested based on three requirements: precision of the result, number of iterations and calculation time......Nowadays the requirements imposed by the industry and economy ask for better quality and performance while the price must be maintained in the same range. To achieve this goal optimization must be introduced in the design process. Two of the best known optimization algorithms for machine design....... Both algorithms are also tested on an analytical design process of a Transverse Flux Permanent Magnet Generator to observe their performances in an electrical machine design application....
Channel—Optimized VQ Design Based on Partial Distortion Theorem Using Evolutionary Algorithm
Institute of Scientific and Technical Information of China (English)
LITianhao
2003-01-01
A partial distortion theorem based channel-optimized vector quantization(COVQ)design algorithm using the evolutionary algorithm on noisy algorithm is introduced into the design of COVQ to achieve a significant improvement of vector quantization(VQ)performance for given noisy channel status.The evolutionary strategy is utilized to adjust the subdistortion of each region determined by each codevector in order to improve the total expected distortion.Finally,compared with other conventional codebook design algorithms,the presented algorithm better adjusts the subdistortion of each region and achieves significant gains in average distortion due to hannel errors,over other conventional VQ design methods,as confirmed by the experimental results.
A Novel Disassemble Algorithm Designed for Malicious File
Directory of Open Access Journals (Sweden)
Di Sun
2013-02-01
Full Text Available In order to avoid being static analyzed, hacker rely on various obfuscation techniques to hide its malicious characters. These techniques are very effective against common disassembles, preventing binary file from being disassembled correctly. The study presents novel disassemble algorithm which based on analyzed Control Flow Graph (CFG and Data Flow Graph (DFG information improve the ability of the disassembly. The proposed algorithm was verified on varied binary files. The experiment shows that the method not only improves the accuracy of disassemble but also greatly deal with malicious files.
[Optimizing algorithm design of piecewise linear classifier for spectra].
Lan, Tian-Ge; Fang, Yong-Hua; Xiong, Wei; Kong, Chao; Li, Da-Cheng; Dong, Da-Ming
2008-11-01
Being able to identify pollutant gases quickly and accurately is a basic request of spectroscopic technique for envirment monitoring for spectral classifier. Piecewise linear classifier is simple needs less computational time and approachs nonlinear boundary beautifully. Combining piecewise linear classifier and linear support vector machine which is based on the principle of maximizing margin, an optimizing algorithm for single side piecewise linear classifier was devised. Experimental results indicate that the piecewise linear classifier trained by the optimizing algorithm proposed in this paper can approach nonolinear boundary with fewer super_planes and has higher veracity for classification and recognition.
Design and Implementation of GPU-Based Prim's Algorithm
Directory of Open Access Journals (Sweden)
Wei Wang
2011-07-01
Full Text Available Minimum spanning tree is a classical problem in graph theory that plays a key role in a broad domain of applications. This paper proposes a minimum spanning tree algorithm using Prim's approach on Nvidia GPU under CUDA architecture. By using new developed GPU-based Min-Reduction data parallel primitive in the key step of the algorithm, higher efficiency is achieved. Experimental results show that we obtain about 2 times speedup on Nvidia GTX260 GPU over the CPU implementation and 3 times speedup over non-primitives GPU implementation.
AN ITERATIVE ALGORITHM FOR OPTIMAL DESIGN OF NON-FREQUENCY-SELECTIVE FIR DIGITAL FILTERS
Institute of Scientific and Technical Information of China (English)
Duan Miyi; Sun Chunlai; Liu Xin; Tian Xinguang
2008-01-01
This paper proposes a novel iterative algorithm for optimal design of non-frequency-se-lective Finite Impulse Response (FIR) digital filters based on the windowing method. Different from the traditional optimization concept of adjusting the window or the filter order in the windowing design of an FIR digital filter,the key idea of the algorithm is minimizing the approximation error by succes-sively modifying the design result through an iterative procedure under the condition of a fixed window length. In the iterative procedure,the known deviation of the designed frequency response in each iteration from the ideal frequency response is used as a reference for the next iteration. Because the approximation error can be specified variably,the algorithm is applicable for the design of FIR digital filters with different technical requirements in the frequency domain. A design example is employed to illustrate the efficiency of the algorithm.
VLSI micro- and nanophotonics science, technology, and applications
Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati
2011-01-01
Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe
Graph Transformation and Designing Parallel Sparse Matrix Algorithms beyond Data Dependence Analysis
Directory of Open Access Journals (Sweden)
H.X. Lin
2004-01-01
Full Text Available Algorithms are often parallelized based on data dependence analysis manually or by means of parallel compilers. Some vector/matrix computations such as the matrix-vector products with simple data dependence structures (data parallelism can be easily parallelized. For problems with more complicated data dependence structures, parallelization is less straightforward. The data dependence graph is a powerful means for designing and analyzing parallel algorithms. However, for sparse matrix computations, parallelization based on solely exploiting the existing parallelism in an algorithm does not always give satisfactory results. For example, the conventional Gaussian elimination algorithm for the solution of a tri-diagonal system is inherently sequential, so algorithms specially for parallel computation has to be designed. After briefly reviewing different parallelization approaches, a powerful graph formalism for designing parallel algorithms is introduced. This formalism will be discussed using a tri-diagonal system as an example. Its application to general matrix computations is also discussed. Its power in designing parallel algorithms beyond the ability of data dependence analysis is shown by means of a new algorithm called ACER (Alternating Cyclic Elimination and Reduction algorithm.
VLSI Architecture Of A Binary Up/Down Counter
Hsu, In-Shek; Truong, Trieu-Kie; Reed, I. S.
1988-01-01
Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.
District Heating Network Design and Configuration Optimization with Genetic Algorithm
DEFF Research Database (Denmark)
Li, Hongwei; Svendsen, Svend
2013-01-01
and the pipe friction and heat loss formulations are non-linear. In order to find the optimal district heating network configuration, genetic algorithm which handles the mixed integer nonlinear programming problem is chosen. The network configuration is represented with binary and integer encoding...
District Heating Network Design and Configuration Optimization with Genetic Algorithm
DEFF Research Database (Denmark)
Li, Hongwei; Svendsen, Svend
2011-01-01
the heating plant location is allowed to vary. The connection between the heat generation plant and the end users can be represented with mixed integer and the pipe friction and heat loss formulations are non-linear. In order to find the optimal DH distribution pipeline configuration, the genetic algorithm...
District Heating Network Design and Configuration Optimization with Genetic Algorithm
DEFF Research Database (Denmark)
Li, Hongwei; Svendsen, Svend
2011-01-01
the heating plant location is allowed to vary. The connection between the heat generation plant and the end users can be represented with mixed integer and the pipe friction and heat loss formulations are non-linear. In order to find the optimal DH distribution pipeline configuration, the genetic algorithm...
VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces
Wooley, Bruce A.
1991-04-01
The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.
An optimized outlier detection algorithm for jury-based grading of engineering design projects
DEFF Research Database (Denmark)
Thompson, Mary Kathryn; Espensen, Christina; Clemmensen, Line Katrine Harder
2016-01-01
This work characterizes and optimizes an outlier detection algorithm to identify potentially invalid scores produced by jury members while grading engineering design projects. The paper describes the original algorithm and the associated adjudication process in detail. The impact of the various...... conditions in the algorithm on the false positive and false negative rates is explored. Aresponse surface design is performed to optimize the algorithm using a data set from Fall 2010. Finally, the results are tested against a data set from Fall 2011. It is shown that all elements of the original algorithm......, but no true optimum seems to exist. The performance of the best optimizations and the original algorithm are similar. Therefore, it should be possible to choose new coefficient values for jury populations in other cultures and contexts logically and empirically without a full optimization as long...
Moini, A
2002-01-01
In this paper, genetic algorithms are used in the design and robustification various mo el-ba ed/non-model-based fuzzy-logic controllers for robotic manipulators. It is demonstrated that genetic algorithms provide effective means of designing the optimal set of fuzzy rules as well as the optimal domains of associated fuzzy sets in a new class of model-based-fuzzy-logic controllers. Furthermore, it is shown that genetic algorithms are very effective in the optimal design and robustification of non-model-based multivariable fuzzy-logic controllers for robotic manipulators.
Short Range Top Attack Trajectory Optimum Design Based on Genetic Algorithm
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
A flying-body is considered as the reference model, the optimized mathematical model is established. The genetic operators are designed and algorithm parameters are selected reasonably. The scheme control signal in short range top attack flight trajectory is optimized by using genetic algorithm. The short range top attack trajectory designed meets the design requirements, with the increase of the falling angle and the decrease of the minimum range. The application of genetic algorithm to top attack trajectory optimization is proved to be feasibly and effectively according to the analyses of results.
Design of delay insensitive circuits using multi-ring structures
DEFF Research Database (Denmark)
Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael
1992-01-01
The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...... into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial...
An integrated approach to structural design of buildings using genetic algorithms
Energy Technology Data Exchange (ETDEWEB)
Rafiq, M.Y.; Mathews, J.D. [Univ. of Plymouth (United Kingdom)
1996-12-31
This paper presents an evolutionary approach to the integration of design activities, in the area of structural design of buildings, using Genetic Algorithms (GA). Integration process is viewed in two contexts: (i) Integration across the design activities within a particular discipline, and (ii) Integration across of the disciplines involved in the design. Particular advantages of the integration of design activities during the conceptual stage of the design process are highlighted.
Optimal design of hydraulic manifold blocks based on niching genetic simulated annealing algorithm
Institute of Scientific and Technical Information of China (English)
Jia Chunqiang; Yu Ling; Tian Shujun; Gao Yanming
2007-01-01
To solve the combinatorial optimization problem of outer layout and inner connection integrated schemes in the design of hydraulic manifold blocks(HMB),a hybrid genetic simulated annealing algorithm based on niche technology is presented.This hybrid algorithm,which combines genetic algorithm,simulated annealing algorithm and niche technology,has a strong capability in global and local search,and all extrema can be found in a short time without strict requests for preferences.For the complex restricted solid spatial layout problems in HMB,the optimizing mathematical model is presented.The key technologies in the integrated layout and connection design of HMB,including the realization of coding,annealing operation and genetic operation,are discussed.The framework of HMB optimal design system based on hybrid optimization strategy is proposed.An example is given to testify the effectiveness and feasibility of the algorithm.
Real-time Design Constraints in Implementing Active Vibration Control Algorithms
Institute of Scientific and Technical Information of China (English)
Mohammed Alamgir Hossain; Mohammad Osman Tokhi
2006-01-01
Although computer architectures incorporate fast processing hardware resources, high performance real-time implementation of a complex control algorithm requires an efficient design and software coding of the algorithm so as to exploit special features of the hardware and avoid associated architecture shortcomings. This paper presents an investigation into the analysis and design mechanisms that will lead to reduction in the execution time in implementing real-time control algorithms. The proposed mechanisms are exemplified by means of one algorithm, which demonstrates their applicability to real-time applications. An active vibration control (AVC) algorithm for a flexible beam system simulated using the finite difference (FD) method is considered to demonstrate the effectiveness of the proposed methods. A comparative performance evaluation of the proposed design mechanisms is presented and discussed through a set of experiments.
Multi-objective optimization design of bridge piers with hybrid heuristic algorithms
Institute of Scientific and Technical Information of China (English)
Francisco J. MARTINEZ-MARTIN; Femando GONZALEZ-VIDOSA; Antonio HOSPITALER; Victor YEPES
2012-01-01
This paper describes one approach to the design of reinforced concrete (RC) bridge piers,using a three-hybrid multiobjective simulated annealing (SA) algorithm with a neighborhood move based on the mutation operator from the genetic algorithms (GAs),namely MOSAMO1,MOSAMO2 and MOSAMO3.The procedure is applied to three objective functions:the economic cost,the reinforcing steel congestion and the embedded CO2 emissions.Additional results for a random walk and a descent local search multi-objective algorithm are presented.The evaluation of solutions follows the Spanish Code for structural concrete.The methodology was applied to a typical bridge pier of 23,97 m in height.This example involved 110 design variables.Results indicate that algorithm MOSAMO2 outperforms other algorithms regarding the definition of Pareto fronts.Further,the proposed procedure will help structural engineers to enhance their bridge pier designs.
Use of Algorithm of Changes for Optimal Design of Heat Exchanger
Tam, S. C.; Tam, H. K.; Chio, C. H.; Tam, L. M.
2010-05-01
For economic reasons, the optimal design of heat exchanger is required. Design of heat exchanger is usually based on the iterative process. The design conditions, equipment geometries, the heat transfer and friction factor correlations are totally involved in the process. Using the traditional iterative method, many trials are needed for satisfying the compromise between the heat exchange performance and the cost consideration. The process is cumbersome and the optimal design is often depending on the design engineer's experience. Therefore, in the recent studies, many researchers, reviewed in [1], applied the genetic algorithm (GA) [2] for designing the heat exchanger. The results outperformed the traditional method. In this study, the alternative approach, algorithm of changes, is proposed for optimal design of shell-tube heat exchanger [3]. This new method, algorithm of changes based on I Ching (???), is developed originality by the author. In the algorithms, the hexagram operations in I Ching has been generalized to binary string case and the iterative procedure which imitates the I Ching inference is also defined. On the basis of [3], the shell inside diameter, tube outside diameter, and baffles spacing were treated as the design (or optimized) variables. The cost of the heat exchanger was arranged as the objective function. Through the case study, the results show that the algorithm of changes is comparable to the GA method. Both of method can find the optimal solution in a short time. However, without interchanging information between binary strings, the algorithm of changes has advantage on parallel computation over GA.
Satellite Constellation Design with Adaptively Continuous Ant System Algorithm
Institute of Scientific and Technical Information of China (English)
He Quan; Han Chao
2007-01-01
The ant system algorithm (ASA) has proved to be a novel meta-heuristic algorithm to solve many multivariable problems. In this paper, the earth coverage of satellite constellation is analyzed and a (n + 1)-fold coverage rate is put forward to evaluate the coverage performance of a satellite constellation. An optimization model of constellation parameters is established on the basis of the coverage performance. As a newly developed method, ASA can be applied to optimize the constellation parameters. In order to improve the ASA,a rule for adaptive number of ants is proposed, by which the search range is obviously enlarged and the convergence speed increased.Simulation results have shown that the ASA is more quick and efficient than other methods.
Algorithm Of Revitalization Programme Design For Housing Estates
Directory of Open Access Journals (Sweden)
Ostańska Anna
2015-09-01
Full Text Available Demographic problems, obsolescence of existing buildings, unstable economy, as well as misunderstanding of the mechanism that turn city quarters into areas in need for intervention result in the implementation of improvement measures that prove inadequate. The paper puts forward an algorithm of revitalization program for housing developments and presents its implementation. It also showed the effects of periodically run (10 years three-way diagnostic tests in correlation with the concept of settlement management.
Algorithm Of Revitalization Programme Design For Housing Estates
Ostańska, Anna
2015-09-01
Demographic problems, obsolescence of existing buildings, unstable economy, as well as misunderstanding of the mechanism that turn city quarters into areas in need for intervention result in the implementation of improvement measures that prove inadequate. The paper puts forward an algorithm of revitalization program for housing developments and presents its implementation. It also showed the effects of periodically run (10 years) three-way diagnostic tests in correlation with the concept of settlement management.
Algorithms and Array Design Criteria for Robust Imaging in Interferometry
2016-04-01
from the esteemed Harvard faculty. In particular, I would like to thank Prof. Yue Lu. I was very fortunate to be enrolled in the Statistical Inference... parents , Jean and Tom Kurien. xvi Introduction The use of optical interferometry as a multi-aperture imaging approach is attracting in- creasing...on the scene’s compactness, sparsity, or smoothness). In particular, a myriad of so-called self -calibration algorithms have been developed (see, e.g
Tran, Huu-Khoa; Chiou, Juing -Shian; Peng, Shou-Tao
2016-01-01
In this paper, the feasibility of a Genetic Algorithm Optimization (GAO) education software based Fuzzy Logic Controller (GAO-FLC) for simulating the flight motion control of Unmanned Aerial Vehicles (UAVs) is designed. The generated flight trajectories integrate the optimized Scaling Factors (SF) fuzzy controller gains by using GAO algorithm. The…
DEFF Research Database (Denmark)
Saadi, Dorthe Bodholt; Egstrup, Kenneth; Branebjerg, Jens;
2012-01-01
We have designed and optimized an automatic QRS complex detection algorithm for electrocardiogram (ECG) signals recorded with the DELTA ePatch platform. The algorithm is able to automatically switch between single-channel and multi-channel analysis mode. This preliminary study includes data from ...
Tran, Huu-Khoa; Chiou, Juing -Shian; Peng, Shou-Tao
2016-01-01
In this paper, the feasibility of a Genetic Algorithm Optimization (GAO) education software based Fuzzy Logic Controller (GAO-FLC) for simulating the flight motion control of Unmanned Aerial Vehicles (UAVs) is designed. The generated flight trajectories integrate the optimized Scaling Factors (SF) fuzzy controller gains by using GAO algorithm. The…
Algorithme intelligent d'optimisation d'un design structurel de grande envergure
Dominique, Stephane
The implementation of an automated decision support system in the field of design and structural optimisation can give a significant advantage to any industry working on mechanical designs. Indeed, by providing solution ideas to a designer or by upgrading existing design solutions while the designer is not at work, the system may reduce the project cycle time, or allow more time to produce a better design. This thesis presents a new approach to automate a design process based on Case-Based Reasoning (CBR), in combination with a new genetic algorithm named Genetic Algorithm with Territorial core Evolution (GATE). This approach was developed in order to reduce the operating cost of the process. However, as the system implementation cost is quite expensive, the approach is better suited for large scale design problem, and particularly for design problems that the designer plans to solve for many different specification sets. First, the CBR process uses a databank filled with every known solution to similar design problems. Then, the closest solutions to the current problem in term of specifications are selected. After this, during the adaptation phase, an artificial neural network (ANN) interpolates amongst known solutions to produce an additional solution to the current problem using the current specifications as inputs. Each solution produced and selected by the CBR is then used to initialize the population of an island of the genetic algorithm. The algorithm will optimise the solution further during the refinement phase. Using progressive refinement, the algorithm starts using only the most important variables for the problem. Then, as the optimisation progress, the remaining variables are gradually introduced, layer by layer. The genetic algorithm that is used is a new algorithm specifically created during this thesis to solve optimisation problems from the field of mechanical device structural design. The algorithm is named GATE, and is essentially a real number
Carvajal, Gonzalo; Figueroa, Miguel
2014-07-01
Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.
CMOS VLSI Layout and Verification of a SIMD Computer
Zheng, Jianqing
1996-01-01
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
刘彦佩
2001-01-01
This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.
Tungsten and other refractory metals for VLSI applications II
Energy Technology Data Exchange (ETDEWEB)
Broadbent, E.K.
1987-01-01
This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.
An Interactive Multimedia Learning Environment for VLSI Built with COSMOS
Angelides, Marios C.; Agius, Harry W.
2002-01-01
This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…
An Algorithmic Perspective on Some Network Design, Construction and Analysis Problems
Andreica, Mugurel Ionut; Andreica, Romulus; Andreica, Angela
2009-01-01
Efficient network design, construction and analysis are important topics, considering the highly dynamic environment in which data communication occurs nowadays. In this paper we address several problems concerning these topics from an algorithmic point of view.
Design optimization of brushed permanent magnet D C motor by genetic algorithm
Amini, S
2002-01-01
Because of field winding replacement with permanent magnet in brushed permanent magnet D C (PMDC) motors, field losses are eliminated and the structure of the motor is more simple. Efficiency of these motors is therefore increased and the manufacturing process is simplified. Hence, these motors are commonly used in low power applications and their design and optimization is an important consideration. Genetic algorithms are proposed for design optimization of PMD motors because of their independence to objective function structure and its derivative. In this paper genetic algorithms are evaluated for PMDC motor design optimization. an introduction is first presented about PMDC motors, general design procedure and elements of their optimization. Genetic algorithms are then briefly described. Finally results of optimization by genetic algorithms are compared with the one obtained using a conventional method.
An Algorithm for the Design of an Axial Flow Compressor of a Power ...
African Journals Online (AJOL)
An Algorithm for the Design of an Axial Flow Compressor of a Power Generation ... speed, number of stages, pressure ratio, ambient air temperature and pressure etc. ... The blade camber angles for each stage of the compressor were also ...
DEFF Research Database (Denmark)
Larsen, Niels Vesterdal
2007-01-01
A printed drooping dipole array is designed and constructed. The design is based on a genetic algorithm optimisation procedure used in conjunction with the software programme AWAS. By optimising the array G/T for specific combinations of scan angles and frequencies an optimum design is obtained...
Optimal Design of the Transverse Flux Machine Using a Fitted Genetic Algorithm with Real Parameters
DEFF Research Database (Denmark)
Argeseanu, Alin; Ritchie, Ewen; Leban, Krisztina Monika
2012-01-01
This paper applies a fitted genetic algorithm (GA) to the optimal design of transverse flux machine (TFM). The main goal is to provide a tool for the optimal design of TFM that is an easy to use. The GA optimizes the analytic basic design of two TFM topologies: the C-core and the U-core. First...
DEFF Research Database (Denmark)
Larsen, Niels Vesterdal
2007-01-01
A printed drooping dipole array is designed and constructed. The design is based on a genetic algorithm optimisation procedure used in conjunction with the software programme AWAS. By optimising the array G/T for specific combinations of scan angles and frequencies an optimum design is obtained...
Algorithm Design and Test of the Solar Guide Telescope
Institute of Scientific and Technical Information of China (English)
Wei-Bin Wen; Sheng-Zhen Jin
2004-01-01
The Solar Guide Telescope (SGT), an important solar attitude sensor of the SST (Space Solar Telescope, a space solar observing instrument being developed in China), can accurately produce pointing error signals of the SST for attitude control at high speed. We analyze in detail the error algorithm of the heliocentric coordinates and the edge judging of solar images. The measuring accuracy of ±0.5arcsec of the SGT is verified by experiments on the tracking of the Sun and by testing a sun simulator. Some factors causing the pointing errors are examined.
1981-07-01
1p^^i-J\\\\^3^\\\\^. TECHNICAL LIBRARY AD^y^.q ijg. TECHNICAL REPORT ARBRL-TR-02346 COMPUTER ALGORITHMS FOR THE DESIGN AND IMPLEMENTATION OF LINEAR...INSTRUCTIONS BEFORE COMPLETI?>G FORM 1. REPORT NUMBER TECHNICAL REPORT ARBRL-TR-n2.^46 i. GOVT ACCESSION NO. *. TITLE fand Sijfam;»; COMPUTER ... ALGORITHMS FOR THE DESIGN AND IMPLEMENTATION OF LINEAR PHASE FINPTE IMPULSE RESPONSE DIGITAL FILTERS 7. AUTHORf*; James N. Walbert 9
Design and manufacture of a biped robot to implement the inverted pendulum foot placement algorithm
Vargas Matín, Elliot
2014-01-01
This project aims to design and manufacture a bipedal robot speci cally designed to be controlled with the Inverted Pendulum Foot Placement algorithm. This algorithm, models the robot as an inverted pendulum. This inverted pendulum is formed from the support points of the leg of the robot with the ground, to the center of gravity of the robot. Then using the kinetic and potential energy of the inverted pendulum, the correct position of the point that represent the center of gra...