WorldWideScience

Sample records for vlsi description language

  1. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  2. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  3. Epsilon. A System Description Language

    DEFF Research Database (Denmark)

    Jensen, Kurt; Kyng, Morten

    This paper discusses the use of Petri nets as a semantic tool in the design of languages and in the construction and analysis of system descriptions. The topics treated are: -- Languages based on nets. -- The problem of time in nets. -- Nets and related models. -- Nets and formal semantics. -- Pa...

  4. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  5. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  6. Natural Language Description of Emotion

    Science.gov (United States)

    Kazemzadeh, Abe

    2013-01-01

    This dissertation studies how people describe emotions with language and how computers can simulate this descriptive behavior. Although many non-human animals can express their current emotions as social signals, only humans can communicate about emotions symbolically. This symbolic communication of emotion allows us to talk about emotions that we…

  7. Addressing the Language Description Deficit

    Directory of Open Access Journals (Sweden)

    M. Ali Bolgiin

    2010-01-01

    Full Text Available Well-described language features are key to successful teaching and learning, especially for achieving advanced levels of proficiency. Other measures, such as simply increasing the number of reading and listening passages in a language program alone are not enough to bring the student to a higher level in a given skill. In fact, even being present in the target culture does not suffice. Angelelli and Degueldre (2002 argue that at advanced levels, even spending time in a country where the language is spoken is not necessarily sufficient for learners: "They do not need just exposure; they need answers to questions and explanations that they can rarely get by simply being immersed in a language/ culture." Less commonly taught languages (LCTLs lack descriptions that have such answers and explanations (cf. Fotos, 2002. It is argued in this paper that corpuslinguistic analyses help to provide actual usage-based, rather than intuition-based, descriptions and explanations of language features. Such approach is illustrated through English and Turkish examples.

  8. The Geometry Description Markup Language

    Institute of Scientific and Technical Information of China (English)

    RadovanChytracek

    2001-01-01

    Currently,a lot of effort is being put on designing complex detectors.A number of simulation and reconstruction frameworks and applications have been developed with the aim to make this job easier.A very important role in this activity is played by the geometry description of the detector apparatus layout and its working environment.However,no real common approach to represent geometry data is available and such data can be found in various forms starting from custom semi-structured text files,source code (C/C++/FORTRAN),to XML and database solutions.The XML(Extensible Markup Language)has proven to provide an interesting approach for describing detector geometries,with several different but incompatible XML-based solutions existing.Therefore,interoperability and geometry data exchange among different frameworks is not possible at present.This article introduces a markup language for geometry descriptions.Its aim is to define a common approach for sharing and exchanging of geometry description data.Its requirements and design have been driven by experience and user feedback from existing projects which have their geometry description in XML.

  9. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  10. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  11. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  12. Object Oriented Programming Constructs' in VHSIC Hardware Description Language ‘Why & How’

    Directory of Open Access Journals (Sweden)

    Deepak Jain

    2007-01-01

    Full Text Available Object Oriented Programming Structure (OOPS has proved its importance in software development in terms of advantages like Abstraction, Encapsulation, Polymorphism, Concurrency, Modularity and Reusability. Also the Object Oriented codes are found to be more verifiable & maintainable. Hence they allow reduction in efforts for development, testing & maintenance of the software. In current scenario, digital-VLSI design life cycle begins with modeling using some Hardware Description Language (HDL followed by functional verification of the HDL-model by its simulation. Often, VLSI-developers show interest in getting software that simulates the functional behavior of the hardware for its analysis from different points of concern. For the sack of effort minimization in co-designing of Digital VLSI chips and their simulating software, it is of interest to introduce automation in code conversion from HDL to OOPS and vise versa. Author’s efforts in this direction are summarized in this document. The outcome of this paper may be developed as a code converter from C++ to VHDL and vise versa.

  13. Pedagogical Descriptions of Language: Lexis.

    Science.gov (United States)

    Cowie, A. P.

    1989-01-01

    An examination is made of the advances, trends, and future developments in pedagogical lexicography with specific discussions concerning lexical research projects and language learners' dictionaries. (46 references) (GLR)

  14. CODE: Description Language for Wireless Collaborating Objects

    NARCIS (Netherlands)

    Marin Perianu, Raluca; Scholten, Johan; Havinga, Paul J.M.

    2005-01-01

    This paper introduces CODE, a Description Language for Wireless Collaborating Objects (WCO), with the specific aim of enabling service management in smart environments. WCO extend the traditional model of wireless sensor networks by transferring additional intelligence and responsibility from the

  15. CODE: description language for wireless collaborating objects

    NARCIS (Netherlands)

    Marin Perianu, Raluca; Scholten, Johan; Havinga, Paul J.M.

    2005-01-01

    This paper introduces CODE, a Description Language for Wireless Collaborating Objects (WCO), with the specific aim of enabling service management in smart environments. WCO extend the traditional model of wireless sensor networks by transferring additional intelligence and responsibility from the

  16. VIRTUAL INSTRUMENT SYSTEM SOFTWARE ARCHITECTURE DESCRIPTION LANGUAGE

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    In software engineering, an architecture description language (ADL) is intended to aid designers in defining software architectures in terms of abstractions that they find useful, and in making a smooth transi- tion to code. Based on ADL, the concept and models of the Virtual instrunent system Software architecture Description Language (VSDL) is provided in this paper. The VSDL put forward provides a new method for vir- tual instrunent system's application design and development by describing the virtual instrument system soft- ware architecture effectively. In this paper, the model description、component description and line description are analyzed in detail, and the structure language based on the model is also provided. VSDL provides a smooth interface to graphic software platform, and has been applied to many virtual instrument systems' inte- gration and already yielded good results both in technology and economy.

  17. The Athena Data Dictionary and Description Language

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    We have developed a data object description tool suite and service for Athena consisting of :a language grammar based upon an extended proper subset of IDL 2.0,a compiler front end based upon this language grammar,JavaCC,and a Java Reflection API-like interface,and several compiler back ends which meet specific needs in ATLAS such as automatic generation of object converters and data object scripting interfaces.We present here details of our work and experience to date on the Athena Definition Language and Athena Data Dictionary.

  18. Descriptive complexity for pictures languages (extended abstract)

    CERN Document Server

    Grandjean, Etienne; richard, Gaétan

    2012-01-01

    This paper deals with descriptive complexity of picture languages of any dimension by syntactical fragments of existential second-order logic. - We uniformly generalize to any dimension the characterization by Giammarresi et al. \\cite{GRST96} of the class of \\emph{recognizable} picture languages in existential monadic second-order logic. - We state several logical characterizations of the class of picture languages recognized in linear time on nondeterministic cellular automata of any dimension. They are the first machine-independent characterizations of complexity classes of cellular automata. Our characterizations are essentially deduced from normalization results we prove for first-order and existential second-order logics over pictures. They are obtained in a general and uniform framework that allows to extend them to other "regular" structures. Finally, we describe some hierarchy results that show the optimality of our logical characterizations and delineate their limits.

  19. PHONOLOGICAL AND LEXICAL DESCRIPTION OF MODEBUR LANGUAGE

    Directory of Open Access Journals (Sweden)

    La Ino

    2013-03-01

    Full Text Available This article, in which the theory structural phonology was used, discusses the phonological and lexical description of Modebur language, one of the local languages in Pantar Island. The result of analysis shows that the Modebur language has five vowels; they are /i/, /e/, /a/, /o/, and /u/. They all can distribute in the initial, medial and final position of words. It has sixteen phonemes and sixteen consonants, many of which can distribute in the beginning of words, some can distribute in the initial and medial position of words only, and one can only distribute in the final position of words. The consonants which can distribute completely are /p/, /b/, /m/, /t/, /n/, /s/, /l/, /k/, /?/, /g/, and the ones which can distribute in the initial and medial position of words are /j/, /h/, /w/, and the one which can distribute in the final position of words is /?/.  

  20. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  1. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  2. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  3. Design and Implementation of Test Flow Description Language

    Institute of Scientific and Technical Information of China (English)

    MENG Chen; WANG Cheng; YANG Suo-chang

    2009-01-01

    A test flow description language is designed for the description of test flow. The design concept, composition, program structure and syntax structure of statement are presented. The development and impletementation processes of the language are also described. This language is independent of hardware, which can be used for different platforms, and can be extended. The language is used to describe the test flow easily. It simplifies the development process of test software and reduces the difficulty of software maintenance greatly.

  4. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  5. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  6. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  7. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  8. IVOA recommendation: Parameter Description Language Version 1.0

    CERN Document Server

    Zwolf, Carlo Maria; Garrido, Julian; Ruiz, Jose Enrique; Petit, Franck Le

    2015-01-01

    This document discusses the definition of the Parameter Description Language (PDL). In this language parameters are described in a rigorous data model. With no loss of generality, we will represent this data model using XML. It intends to be a expressive language for self-descriptive web services exposing the semantic nature of input and output parameters, as well as all necessary complex constraints. PDL is a step forward towards true web services interoperability.

  9. Production Logistics Simulation Supported by Process Description Languages

    Directory of Open Access Journals (Sweden)

    Bohács Gábor

    2016-03-01

    Full Text Available The process description languages are used in the business may be useful in the optimization of logistics processes too. The process description languages would be the obvious solution for process control, to handle the main sources of faults and to give a correct list of what to do during the logistics process. Related to this, firstly, the paper presents the main features of the frequent process description languages. The following section describes the currently most used process modelling languages, in the areas of production and construction logistics. In addition, the paper gives some examples of logistics simulation, as another very important field of logistics system modelling. The main edification of the paper, the logistics simulation supported by process description languages. The paper gives a comparison of a Petri net formal representation and a Simul8 model, through a construction logistics model, as the major contribution of the research.

  10. The Language of Civil Engineering: Descriptive, Prescriptive, and Persuasive.

    Science.gov (United States)

    Machauf, Liora

    1990-01-01

    Focuses on the language of civil engineering as manifested in the professional journal "Civil Engineering ASCE." Articles are analyzed, both syntactically and lexically, in terms of three major rhetorical functions: description, prescription, and persuasion. (17 references) (GLR)

  11. A Petri Net Definition of a System Description Language

    DEFF Research Database (Denmark)

    Jensen, Kurt; Kyng, Morten; Madsen, Ole Lehrmann

    1979-01-01

    This paper introduces a language for the description of systems with concurrency, and presents a formal definition of its semantics. The language is based on Delta and the semantic model is an extension of Petri nets with a data part and with expressions attached to transitions and to places....

  12. Natural Language Video Description using Deep Recurrent Neural Networks

    Science.gov (United States)

    2015-11-23

    videos by exploiting temporal structure. arXiv:1502.08029v4, 2015. 15, 17, 18, 19, 20, 27 [108] Haonan Yu and Jeffrey Mark Siskind. Grounded language ...Examples 32 Translating Videos to Natural Language CNN [Venugopalan et. al. NAACL’15] 33 Does not consider temporal sequence of frames. Can our model be...Natural Language Video Description using Deep Recurrent Neural Networks Subhashini Venugopalan University of Texas at Austin vsub@cs.utexas.edu

  13. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    ... to Device Independent Designs with Complex Programmable Logic Devices ... in the very large scale integration (VLSI) market segments, hardware engineers ... the device independent architecture (Ultra 3700 CPLD series) for synthesis, ...

  14. LISp-Miner Control Language description of scripting language implementation

    Directory of Open Access Journals (Sweden)

    Milan Simunek

    2014-04-01

    Full Text Available This paper introduces the LISp-Miner Control Language – a scripting language for the LISp-Miner system, an academic system for knowledge discovery in databases. The main purpose of this language is to provide programmable means to all the features of the LISp-Miner system and mainly to automate the main phases of data mining – from data introduction and preprocessing, formulation of analytical tasks, to discovery of the most interesting patterns. In this sense, the language is a necessary prerequisite for the EverMiner project of data mining automation. Language will serve other purposes too – for an automated verification of the LISp-Miner system functionality before a new version is released and as an educational tool in advanced data mining courses.

  15. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  16. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  17. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  18. Using the Network Description Language in Optical Networks

    NARCIS (Netherlands)

    Ham, J.J. van der; Grosso, P.; Pol, R. van der; Toonk, A.; Laat, C. de

    2007-01-01

    Current research networks allow end users to build their own application-specific connections (lightpaths) and Optical Private Networks (OPNs). This requires a clear communication between the requesting application and the network. The Network Description Language (NDL) is a vocabulary designed to d

  19. Generating natural language descriptions using speaker-dependent information

    NARCIS (Netherlands)

    Castro Ferreira, Thiago; Paraboni, Ivandré

    2017-01-01

    This paper discusses the issue of human variation in natural language referring expression generation. We introduce a model of content selection that takes speaker-dependent information into account to produce descriptions that closely resemble those produced by each individual, as seen in a number

  20. Analog Hardware Description Language and Its Relations to VHDL

    Directory of Open Access Journals (Sweden)

    J. Popelek

    1996-09-01

    Full Text Available Primary motivations for analogue hardware description language (VHDL-A is to support the modelling of physical systems. The VHDL-A must therefore allow to model the physical conservation laws, such as the energy conservation law, which states that energy can neither be created nor destroyed, but it can only change its form.

  1. Towards a Bernsteinian Language of Description for Mathematics Classroom Discourse

    Science.gov (United States)

    Straehler-Pohl, Hauke; Gellert, Uwe

    2013-01-01

    This article aims at developing an external language of description to investigate the problem of why particular groups of students are systematically not provided access to school mathematical knowledge. Based on Basil Bernstein's conceptualisation of power in classification, we develop a three-dimensional model that operationalises the…

  2. Prolog as description and implementation language in computer science teaching

    DEFF Research Database (Denmark)

    Christiansen, Henning

    Prolog is a powerful pedagogical instrument for theoretical elements of computer science when used as combined description language and experimentation tool. A teaching methodology based on this principle has been developed and successfully applied in a context with a heterogeneous student...

  3. Prototypes and Idealizations in Natural Language Shape Descriptions.

    Science.gov (United States)

    Heidorn, P. Bryan

    1998-01-01

    Describes a graphic modeling, natural language processing system, VerbalImage, which mimics features of human shape reasoning. Subjects read the same text description and were able to recognize the image generated by the computer from among a series of other computer-generated images. Performance on task was as good as for a control group…

  4. Corpus-Based Approaches to Language Description for Specialized Academic Writing

    Science.gov (United States)

    Flowerdew, John

    2017-01-01

    Language description is a fundamental requirement for second language (L2) syllabus design. The greatest advances in language description in recent decades have been done with the help of electronic corpora. Such language description is the theme of this article. The article first introduces some basic concepts and principles in corpus research.…

  5. Corpus-Based Approaches to Language Description for Specialized Academic Writing

    Science.gov (United States)

    Flowerdew, John

    2017-01-01

    Language description is a fundamental requirement for second language (L2) syllabus design. The greatest advances in language description in recent decades have been done with the help of electronic corpora. Such language description is the theme of this article. The article first introduces some basic concepts and principles in corpus research.…

  6. Descriptive markup languages and the development of digital humanities

    Directory of Open Access Journals (Sweden)

    Boris Bosančić

    2012-11-01

    Full Text Available The paper discusses the role of descriptive markup languages in the development of digital humanities, a new research discipline that is part of social sciences and humanities, which focuses on the use of computers in research. A chronological review of the development of digital humanities, and then descriptive markup languages is exposed, through several developmental stages. It is shown that the development of digital humanities since the mid-1980s and the appearance of SGML, markup language that was the foundation of TEI, a key standard for the encoding and exchange of humanities texts in the digital environment, is inseparable from the development of markup languages. Special attention is dedicated to the presentation of the Text Encoding Initiative – TEI development, a key organization that developed the titled standard, both from organizational and markup perspectives. By this time, TEI standard is published in five versions, and during 2000s SGML is replaced by XML markup language. Key words: markup languages, digital humanities, text encoding, TEI, SGML, XML

  7. Prolog as description and implementation language in computer science teaching

    DEFF Research Database (Denmark)

    Christiansen, Henning

    Prolog is a powerful pedagogical instrument for theoretical elements of computer science when used as combined description language and experimentation tool. A teaching methodology based on this principle has been developed and successfully applied in a context with a heterogeneous student...... population with uneven mathematical backgrounds. % Definitional interpreters, compilers, and other models of computation are defined in a systematic way as Prolog programs, and as a result, formal descriptions become running prototypes that can be tested and modified by the students. These programs can...

  8. Specification of photonic circuits using Quantum Hardware Description Language

    CERN Document Server

    Tezak, Nikolas; Pavlichin, Dmitri S; Sarma, Gopal; Mabuchi, Hideo

    2011-01-01

    Following the simple observation that the interconnection of a set of quantum optical input-output devices can be specified using structural mode VHSIC Hardware Description Language (VHDL), we demonstrate a computer-aided schematic capture workflow for modeling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

  9. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  10. A Descriptive Characterization of Tree-Adjoining Languages (Full Version)

    CERN Document Server

    Rogers, J

    1998-01-01

    Since the early Sixties and Seventies it has been known that the regular and context-free languages are characterized by definability in the monadic second-order theory of certain structures. More recently, these descriptive characterizations have been used to obtain complexity results for constraint- and principle-based theories of syntax and to provide a uniform model-theoretic framework for exploring the relationship between theories expressed in disparate formal terms. These results have been limited, to an extent, by the lack of descriptive characterizations of language classes beyond the context-free. Recently, we have shown that tree-adjoining languages (in a mildly generalized form) can be characterized by recognition by automata operating on three-dimensional tree manifolds, a three-dimensional analog of trees. In this paper, we exploit these automata-theoretic results to obtain a characterization of the tree-adjoining languages by definability in the monadic second-order theory of these three-dimens...

  11. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  12. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  13. Ontology-supported and XML-based knowledge description language

    Institute of Scientific and Technical Information of China (English)

    王向华; 覃征; 何坚; 王志敏

    2004-01-01

    Differences in the structure and semantics of knowledge that is created and maintained by the various actors on the World Wide Web make its exchange and utilization a problematic task. This is an important issue facing organizations undertaking knowledge management initiatives. An XML-based and ontology-supported knowledge description language (KDL) is presented, which has three-tier structure (core KDL, extended KDL and complex KDL), and takes advantages of strong point of ontology, XML, description logics, frame-based systems. And then, the framework and XMLbased syntax of KDL are introduced, and the methods of translating KDL into first order logic (FOL) are presented. At last, the implementation of KDL on the Web is described, and the reasoning ability of KDL proved by experiment is illustrated in detail.

  14. Acceptance Testing Of Web Applications With Test Description Language

    Directory of Open Access Journals (Sweden)

    Łukasz Olek

    2014-01-01

    Full Text Available Acceptance tests are usually created by a client after a part of a system is implemented. However, some methodologies propose the elaboration of test cases before implementing a system. This approach increases the probability of system implementation that fulfills requirements, but may be problematic for customers and testers. To allow acceptance testing in such conditions, we propose to define test cases by recording them on an interactive mockup (a low detailed user-interface prototype. The paper focuses on Test Description Language, a notation used to store test cases.

  15. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  16. Geometry Description Markup Language for Physics Simulation And Analysis Applications.

    Energy Technology Data Exchange (ETDEWEB)

    Chytracek, R.; /CERN; McCormick, J.; /SLAC; Pokorski, W.; /CERN; Santin, G.; /European Space Agency

    2007-01-23

    The Geometry Description Markup Language (GDML) is a specialized XML-based language designed as an application-independent persistent format for describing the geometries of detectors associated with physics measurements. It serves to implement ''geometry trees'' which correspond to the hierarchy of volumes a detector geometry can be composed of, and to allow to identify the position of individual solids, as well as to describe the materials they are made of. Being pure XML, GDML can be universally used, and in particular it can be considered as the format for interchanging geometries among different applications. In this paper we will present the current status of the development of GDML. After having discussed the contents of the latest GDML schema, which is the basic definition of the format, we will concentrate on the GDML processors. We will present the latest implementation of the GDML ''writers'' as well as ''readers'' for either Geant4 [2], [3] or ROOT [4], [10].

  17. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  18. SDL—TRAN—An Interactive Generator for Formal Description Language SDL

    Institute of Scientific and Technical Information of China (English)

    张尧学; 陈桦; 等

    1996-01-01

    SDL(Specification and Description Language)is an international standard formal description language which has been widely used for the specification and description of communication systems.SDL is based on the concept of the state oriented description technique-FSM(Finite State Machine).This paper reports an interactive generator for SDL,named SDL-TRAN,which can automatically translate FSM expression into SDL description.Except for its automatic translation part,SDL-TRAN includes an user-friendly graphical editor which is used to get the other part of SDL description which cannot be automatically translated.

  19. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  20. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  1. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  2. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  3. Content-Based Human Motion Retrieval with Scene Description Language

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    As commercial motion capture systems are widely used, more and more 3D motion libraries become available, reinforcing the demand for efficient indexing and retrieving methods. Usually, the user will only have a sketchy idea of which kind of motion to look for in the motion database. As a result, how to clearly describe the user's demands is a bottleneck for motion retrieval system. This paper presented a framework that can handle this problem effectively for motion retrieval. This content-based retrieval system supports two kinds of query modes:textual query mode and query-by-example mode. In both query modes, user's input is translated into scene description language first, which can be processed by the system efficiently. By using various kinds of qualitative features and adaptive segments of motion capture data stream, indexing and retrieval methods are carried out at the segment level rather than at the frame level, making them quite efficient. Some experimental examples are given to demonstrate the effectiveness and efficiency of the proposed algorithms.

  4. Teacher Language Competence Description: Towards a New Framework of Evaluation

    Science.gov (United States)

    Sokolova, Nataliya

    2012-01-01

    The article is centred around the concept of "language competence of a foreign language (FL) teacher" and the ways it can be evaluated. Though the definition of teacher language competence might sound obvious it has not yet been clearly structured and, therefore, no component has been thoroughly described. I use this fact as a starting…

  5. SELECTION OF ONTOLOGY FOR WEB SERVICE DESCRIPTION LANGUAGE TO ONTOLOGY WEB LANGUAGE CONVERSION

    Directory of Open Access Journals (Sweden)

    J. Mannar Mannan

    2014-01-01

    Full Text Available Semantic web is to extend the current human readable web to encoding some of the semantic of resources in a machine processing form. As a Semantic web component, Semantic Web Services (SWS uses a mark-up that makes the data into detailed and sophisticated machine readable way. One such language is Ontology Web Language (OWL. Existing conventional web service annotation can be changed to semantic web service by mapping Web Service Description Language (WSDL with the semantic annotation of OWL-S. In this conversion of WSDL to OWL process, the ontology plays a vital role. Ontology can be stored and retrieved from local repository and selecting the appropriate ontology is a complicated process and this can be achieved by Ontology Searching and Property Matching (OSPM engine. Ontology is stored in the local repository as ontology document and exact matching of ontology for the requested query can be searched using semantic similarity ranking method. High ranked classes of ontology will undergo property matching; here requested concept will be matched with the resulting property. OSPM engine act as the backbone for selecting an exact ontology and reduce the conflict that occurs while selecting the ontology for annotation purpose.

  6. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  7. Design automation, languages, and simulations

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume covers a broad range of topics relevant to design automation, languages, and simulations. These include a collaborative framework that coordinates distributed design activities through the Internet, an overview of the Verilog hardware description language and its use in a design environment, hardware/software co-design, syst

  8. Descriptions of Spoken Language for Higher Level Learners: The Example of Questioning.

    Science.gov (United States)

    Basturkmen, Helen

    2001-01-01

    Focuses on question-response sequences in academic and work settings and examines the type of description of questioning conventionally offered in published English language teaching materials for higher-level learners. (Author/VWL)

  9. Reproducible computational biology experiments with SED-ML--the Simulation Experiment Description Markup Language

    National Research Council Canada - National Science Library

    Waltemath, Dagmar; Adams, Richard; Bergmann, Frank T; Hucka, Michael; Kolpakov, Fedor; Miller, Andrew K; Moraru, Ion I; Nickerson, David; Sahle, Sven; Snoep, Jacky L; Le Novère, Nicolas

    2011-01-01

    .... In this article, we present the Simulation Experiment Description Markup Language (SED-ML). SED-ML encodes in a computer-readable exchange format the information required by MIASE to enable reproduction of simulation experiments...

  10. Approaches and Methods in Language Teaching: A Description and Analysis.

    Science.gov (United States)

    Richards, Jack C.; Rodgers, Theodore S.

    Each major trend in 20th-century second language teaching is explained, and similarities and differences are highlighted. An introductory chapter offers a brief history of second language teaching. The second chapter outlines a model for examining and comparing the different approaches. This model is used in subsequent chapters to describe methods…

  11. Descriptions of Selected Career-Related College Language Courses

    Science.gov (United States)

    Knodel, Arthur J.; And Others

    1977-01-01

    Seven courses or programs at different colleges emphasizing specific career applications of languages are described. They include: Technical French; Spanish for Law Enforcement and Correctional Personnel; Executive German; Proyecto Desarrollo Economico; Spanish for Medical Professions; Elements of Foreign Language, and Business French and Business…

  12. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  13. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  14. Automated management of life cycle for future network experiment based on description language

    Science.gov (United States)

    Niu, Hongxia; Liang, Junxue; Lin, Zhaowen; Ma, Yan

    2016-12-01

    Future network is a complex resources pool including multiple physical resources and virtual resources. Establishing experiment on future network is complicate and tedious. That achieving the automated management of future network experiments is so important. This paper brings forward the way for researching and managing the life cycle of experiment based on the description language. The description language uses the framework, which couples with a low hierarchical structure and a complete description of the network experiment. In this way, the experiment description template can be generated by this description framework accurately and completely. In reality, we can also customize and reuse network experiment by modifying the description template. The results show that this method can achieve the aim for managing the life cycle of network experiment effectively and automatically, which greatly saves time, reduces the difficulty, and implements the reusability of services.

  15. Using Open Geographic Data to Generate Natural Language Descriptions for Hydrological Sensor Networks

    OpenAIRE

    Martin Molina; Javier Sanchez-Soriano; Oscar Corcho

    2015-01-01

    Providing descriptions of isolated sensors and sensor networks in natural language, understandable by the general public, is useful to help users find relevant sensors and analyze sensor data. In this paper, we discuss the feasibility of using geographic knowledge from public databases available on the Web (such as OpenStreetMap, Geonames, or DBpedia) to automatically construct such descriptions. We present a general method that uses such information to generate sensor descriptions in natural...

  16. Rapid prototyping of datapath intensive architectures with HML: an abstract hardware description language

    Science.gov (United States)

    Leeser, Miriam E.; Tarafdar, Shantanu; Li, Yanbing

    1996-10-01

    HML allows us to specify hardware at a very abstract level, and automatically generate VHDL from our specifications. The VHDL is used along with commercial CAD tools to generate field programmable logic. In this paper we present HML, a hardware description language based on SML, and discuss the translation process from HML to VHDL. As an example we use HML to specify a DTMF receiver. We present the HML for a Booth multiplier and discuss the design flow from HML to an FPGA implementation of that multiplier. HML is the only language available that applies advances in programming languages and type theory to hardware description.

  17. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  18. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  19. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  20. Domain-specific language design requires feature descriptions

    NARCIS (Netherlands)

    A. van Deursen (Arie); P. Klint (Paul)

    2001-01-01

    textabstractA domain-specific language (DSL) provides a notation tailored towards an application domain and is based on the relevant concepts and features of that domain. As such, a DSL is a means to describe and generate members of a family of programs in the domain. A prerequisite for the design

  1. Using Open Geographic Data to Generate Natural Language Descriptions for Hydrological Sensor Networks.

    Science.gov (United States)

    Molina, Martin; Sanchez-Soriano, Javier; Corcho, Oscar

    2015-07-03

    Providing descriptions of isolated sensors and sensor networks in natural language, understandable by the general public, is useful to help users find relevant sensors and analyze sensor data. In this paper, we discuss the feasibility of using geographic knowledge from public databases available on the Web (such as OpenStreetMap, Geonames, or DBpedia) to automatically construct such descriptions. We present a general method that uses such information to generate sensor descriptions in natural language. The results of the evaluation of our method in a hydrologic national sensor network showed that this approach is feasible and capable of generating adequate sensor descriptions with a lower development effort compared to other approaches. In the paper we also analyze certain problems that we found in public databases (e.g., heterogeneity, non-standard use of labels, or rigid search methods) and their impact in the generation of sensor descriptions.

  2. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  3. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  4. Meta Architecting: Toward a New Generation of Architecture Description Languages

    OpenAIRE

    Adel Smeda; Tahar Khammaci; Mourad Oussalah

    2005-01-01

    The techniques of meta-modeling and meta-levels have become a mature concept and have been largely used to solve real problems in programming languages, distributed environments, knowledge representation, or data bases. In this article it is shown how the same techniques can be applied in component-based software architecture. It also shown the need to propose mechanisms of reflexivity within the domain of software architecture meta-modeling. The outcome of this is a meta-meta-architecture wi...

  5. TDL : a type description language for HPSG. - Part 2: user guide

    OpenAIRE

    Krieger, Hans-Ulrich; Schäfer, Ulrich

    1994-01-01

    This documentation serves as a user's guide to the type description language TDL which is employed in natural language projects at the DFKI. It is intended as a guide for grammar writers rather than as a comprehensive internal documentation. Some familiarity with grammar formalisms/theories such as Head-Driven Phrase Structure Grammar (HPSG) is assumed. The manual describes the syntax of the TDL formalism, the user-accessible control functions and variables, and the various tools such as type...

  6. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  7. Towards a Pattern Language Approach to Document Description

    Directory of Open Access Journals (Sweden)

    Robert Waller

    2012-07-01

    Full Text Available Pattern libraries, originating in architecture, are a common way to share design solutions in interaction design and software engineering. Our aim in this paper is to consider patterns as a way of describing commonly-occurring document design solutions to particular problems, from two points of view. First, we are interested in their use as exemplars for designers to follow, and second, we suggest them as a means of understanding linguistic and graphical data for their organization into corpora that will facilitate descriptive work. We discuss the use of patterns across a range of disciplines before suggesting the need to place patterns in the context of genres, with each potentially belonging to a “home genre” in which it originates and to which it makes an implicit intertextual reference intended to produce a particular reader response in the form of a reading strategy or interpretative stance. We consider some conceptual and technical issues involved in the descriptive study of patterns in naturally-occurring documents, including the challenges involved in building a document corpus.

  8. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  9. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  10. UNI-SPEC:An Instruction Set Description Language

    Institute of Scientific and Technical Information of China (English)

    Zhu Dexin(朱德新); Cheng Xu; Song Chuanhua

    2003-01-01

    Microprocessor development emphasizes hardware and software co-design. Hw/Sw co-design is a modern technique aimed at shortening the time-to-market in designing the real-time and embedded systems. Key feature of this approach is simultaneous development of the program tools and the target processor to match software application. An effective co-design flow must therefore support automatic software toolkits generation, without loss of optimizing efficiency. This has resulted in a paradigm shift towards a language-based design methodology for microprocessor optimization and exploration. This paper proposes a formal grammar, UNI-SPEC, which supports the automatic generation of assemblers, to describe the translation rules from assembly to binary. Based on UNI-SPEC, it implements two typical applications, i.e., automatically generating the assembler and the test suites.

  11. The carbohydrate sequence markup language (CabosML): an XML description of carbohydrate structures.

    Science.gov (United States)

    Kikuchi, Norihiro; Kameyama, Akihiko; Nakaya, Shuuichi; Ito, Hiromi; Sato, Takashi; Shikanai, Toshihide; Takahashi, Yoriko; Narimatsu, Hisashi

    2005-04-15

    Bioinformatics resources for glycomics are very poor as compared with those for genomics and proteomics. The complexity of carbohydrate sequences makes it difficult to define a common language to represent them, and the development of bioinformatics tools for glycomics has not progressed. In this study, we developed a carbohydrate sequence markup language (CabosML), an XML description of carbohydrate structures. The language definition (XML Schema) and an experimental database of carbohydrate structures using an XML database management system are available at http://www.phoenix.hydra.mki.co.jp/CabosDemo.html kikuchi@hydra.mki.co.jp.

  12. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  13. TOWARDS THE DESCRIPTION OF LANGUAGE OF RUSSIAN RELIGIOUS PHILOSOPHY

    Directory of Open Access Journals (Sweden)

    N. V. Kozlovskaia

    2014-01-01

    Full Text Available The article addresses the problem of lexicographic presentation of philosophical terms that constitute the core of the lexical structure of Russian religious and philosophical text. This terminology has not been described in modern linguistic literature, which results in the interest in compiling a composite differential diachronic dictionary. The textual basis of the dictionary includes works of thinkers closely linked to the religious world: N. Fedorov, K. Leontiev, Vl. Soloviev, S. Bulgakov, P. Florensky, L. Shestov, N. Berdyaev, S. Frank.Complexity of the description of philosophical terms is largely due to the uncertainty of their meaning; a philosophical term often correlates not only with a certain idea, but the idea in general. Semantic volume (extensional of philosophical term is much higher than a semantic scope of terms which belong to other specialized areas of knowledge. The article analyzes the philosophical terms «vsemstvo» (L. Shestov and “vizantizm” (K. Leont’ev.The dictionary of Russian philosophers should include commentaries, which explain the relation of terms to ancient and western philosophy, the Bible, theological texts, Russian and foreign literature. Besides, lexicographic representation of individual philosophical terms must take into account ssemantic relation of the particular word in the whole philosophical term system.

  14. Differences between young and older adults' spoken language production in descriptions of negative versus neutral pictures.

    Science.gov (United States)

    Castro, Nichol; James, Lori E

    2014-01-01

    Young and older participants produced oral picture descriptions that were analyzed to determine the impact of negative emotional content on spoken language production. An interaction was found for speech disfluencies: young adults' disfluencies did not vary, whereas older adults' disfluencies increased, for negative compared to neutral pictures. Young adults adopted a faster speech rate while describing negative compared to neutral pictures, but older adults did not. Reference errors were uncommon for both age groups, but occurred more during descriptions of negative than neutral pictures. Our findings indicate that negative content can be differentially disruptive to older adults' spoken language production, and add to the literature on aging, emotion, and cognition by exploring effects within the domain of language production.

  15. Automatic derivation of programs for image processing from natural language descriptions

    Science.gov (United States)

    Ren, Fuji; Zaima, Yasumichi

    1999-10-01

    In this paper we describe AIDPG, an interactive prototype system, which derives computer programs from their natural language descriptions. AIDPG shows how to analyze natural language, resolve ambiguities using knowledge, and generates programs. AIDPG consists of a natural language input model, a natural language analysis model, a program generation model (PGG-Model) and a human machine interface control model. The PGG model has three sub-models, program structure manage sub-model, a data structure and type manage sub- model, and program base manage sub-model. We used an arithmetic problem, which, described in Japanese, was passed to AIDPG and got run-possible C programs. Although AIDPG is basic currently we got a significant result.

  16. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  17. Teaching of science and language by elementary teachers who emphasize the integrated language approach: A descriptive study

    Science.gov (United States)

    Blouch, Kathleen Kennedy

    This research involved investigating the nature of science and language instruction in 13 elementary classrooms where teachers have restructured their language programs to reflect an integrated or holistic view of language instruction. The teachers were identified by school administrators and other professionals as teachers who have implemented instructional reforms described in the Pennsylvania Framework for Reading, Writing and Speaking Across the Curriculum (PCRPII), (Lytle & Botel, 1900). The instruction utilized by these teachers was described as atypical when compared to that of teachers utilizing the more traditional didactic skills oriented approach to language literacy. The research involved observing, recording and categorizing teaching behaviors during both science and language instruction. Videotaped observations were followed by analyses and descriptions of these behaviors. Interviews were also conducted to ascertain the basis for selection of the various instructional approaches. The instruction was compared on four dimensions: participation patterns, time the behaviors were practiced, type of tasks and levels of questioning. The instruction was then described in light of constructivist teaching practices: student collaboration, student autonomy, integration and higher order thinking. Constructivist practices differed among teachers for science and language instruction. During science instruction teachers spent more time involved in teacher-whole group participation patterns with more direct questioning as compared to language instruction in which children participated alone or in groups and had opportunity to initiate conversations and questions. Student inquiry was evidenced during language instruction more so than during science. The 13 teachers asked a variety of levels and types of questions both in science and language instruction. More hands-on science experiences were observed when science was taught separately compared to when integrated with

  18. Systems Biology Graphical Notation: Process Description language Level 1 Version 1.3.

    Science.gov (United States)

    Moodie, Stuart; Le Novère, Nicolas; Demir, Emek; Mi, Huaiyu; Villéger, Alice

    2015-09-04

    The Systems Biological Graphical Notation (SBGN) is an international community effort for standardized graphical representations of biological pathways and networks. The goal of SBGN is to provide unambiguous pathway and network maps for readers with different scientific backgrounds as well as to support efficient and accurate exchange of biological knowledge between different research communities, industry, and other players in systems biology. Three SBGN languages, Process Description (PD), Entity Relationship (ER) and Activity Flow (AF), allow for the representation of different aspects of biological and biochemical systems at different levels of detail. The SBGN Process Description language represents biological entities and processes between these entities within a network. SBGN PD focuses on the mechanistic description and temporal dependencies of biological interactions and transformations. The nodes (elements) are split into entity nodes describing, e.g., metabolites, proteins, genes and complexes, and process nodes describing, e.g., reactions and associations. The edges (connections) provide descriptions of relationships (or influences) between the nodes, such as consumption, production, stimulation and inhibition. Among all three languages of SBGN, PD is the closest to metabolic and regulatory pathways in biological literature and textbooks, but its well-defined semantics offer a superior precision in expressing biological knowledge.

  19. Reproducible computational biology experiments with SED-ML--the Simulation Experiment Description Markup Language.

    Science.gov (United States)

    Waltemath, Dagmar; Adams, Richard; Bergmann, Frank T; Hucka, Michael; Kolpakov, Fedor; Miller, Andrew K; Moraru, Ion I; Nickerson, David; Sahle, Sven; Snoep, Jacky L; Le Novère, Nicolas

    2011-12-15

    The increasing use of computational simulation experiments to inform modern biological research creates new challenges to annotate, archive, share and reproduce such experiments. The recently published Minimum Information About a Simulation Experiment (MIASE) proposes a minimal set of information that should be provided to allow the reproduction of simulation experiments among users and software tools. In this article, we present the Simulation Experiment Description Markup Language (SED-ML). SED-ML encodes in a computer-readable exchange format the information required by MIASE to enable reproduction of simulation experiments. It has been developed as a community project and it is defined in a detailed technical specification and additionally provides an XML schema. The version of SED-ML described in this publication is Level 1 Version 1. It covers the description of the most frequent type of simulation experiments in the area, namely time course simulations. SED-ML documents specify which models to use in an experiment, modifications to apply on the models before using them, which simulation procedures to run on each model, what analysis results to output, and how the results should be presented. These descriptions are independent of the underlying model implementation. SED-ML is a software-independent format for encoding the description of simulation experiments; it is not specific to particular simulation tools. Here, we demonstrate that with the growing software support for SED-ML we can effectively exchange executable simulation descriptions. With SED-ML, software can exchange simulation experiment descriptions, enabling the validation and reuse of simulation experiments in different tools. Authors of papers reporting simulation experiments can make their simulation protocols available for other scientists to reproduce the results. Because SED-ML is agnostic about exact modeling language(s) used, experiments covering models from different fields of research

  20. Reproducible computational biology experiments with SED-ML - The Simulation Experiment Description Markup Language

    Science.gov (United States)

    2011-01-01

    Background The increasing use of computational simulation experiments to inform modern biological research creates new challenges to annotate, archive, share and reproduce such experiments. The recently published Minimum Information About a Simulation Experiment (MIASE) proposes a minimal set of information that should be provided to allow the reproduction of simulation experiments among users and software tools. Results In this article, we present the Simulation Experiment Description Markup Language (SED-ML). SED-ML encodes in a computer-readable exchange format the information required by MIASE to enable reproduction of simulation experiments. It has been developed as a community project and it is defined in a detailed technical specification and additionally provides an XML schema. The version of SED-ML described in this publication is Level 1 Version 1. It covers the description of the most frequent type of simulation experiments in the area, namely time course simulations. SED-ML documents specify which models to use in an experiment, modifications to apply on the models before using them, which simulation procedures to run on each model, what analysis results to output, and how the results should be presented. These descriptions are independent of the underlying model implementation. SED-ML is a software-independent format for encoding the description of simulation experiments; it is not specific to particular simulation tools. Here, we demonstrate that with the growing software support for SED-ML we can effectively exchange executable simulation descriptions. Conclusions With SED-ML, software can exchange simulation experiment descriptions, enabling the validation and reuse of simulation experiments in different tools. Authors of papers reporting simulation experiments can make their simulation protocols available for other scientists to reproduce the results. Because SED-ML is agnostic about exact modeling language(s) used, experiments covering models from

  1. Reproducible computational biology experiments with SED-ML - The Simulation Experiment Description Markup Language

    Directory of Open Access Journals (Sweden)

    Waltemath Dagmar

    2011-12-01

    Full Text Available Abstract Background The increasing use of computational simulation experiments to inform modern biological research creates new challenges to annotate, archive, share and reproduce such experiments. The recently published Minimum Information About a Simulation Experiment (MIASE proposes a minimal set of information that should be provided to allow the reproduction of simulation experiments among users and software tools. Results In this article, we present the Simulation Experiment Description Markup Language (SED-ML. SED-ML encodes in a computer-readable exchange format the information required by MIASE to enable reproduction of simulation experiments. It has been developed as a community project and it is defined in a detailed technical specification and additionally provides an XML schema. The version of SED-ML described in this publication is Level 1 Version 1. It covers the description of the most frequent type of simulation experiments in the area, namely time course simulations. SED-ML documents specify which models to use in an experiment, modifications to apply on the models before using them, which simulation procedures to run on each model, what analysis results to output, and how the results should be presented. These descriptions are independent of the underlying model implementation. SED-ML is a software-independent format for encoding the description of simulation experiments; it is not specific to particular simulation tools. Here, we demonstrate that with the growing software support for SED-ML we can effectively exchange executable simulation descriptions. Conclusions With SED-ML, software can exchange simulation experiment descriptions, enabling the validation and reuse of simulation experiments in different tools. Authors of papers reporting simulation experiments can make their simulation protocols available for other scientists to reproduce the results. Because SED-ML is agnostic about exact modeling language(s used

  2. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  3. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  4. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  5. Neural systems language: a formal modeling language for the systematic description, unambiguous communication, and automated digital curation of neural connectivity.

    Science.gov (United States)

    Brown, Ramsay A; Swanson, Larry W

    2013-09-01

    Systematic description and the unambiguous communication of findings and models remain among the unresolved fundamental challenges in systems neuroscience. No common descriptive frameworks exist to describe systematically the connective architecture of the nervous system, even at the grossest level of observation. Furthermore, the accelerating volume of novel data generated on neural connectivity outpaces the rate at which this data is curated into neuroinformatics databases to synthesize digitally systems-level insights from disjointed reports and observations. To help address these challenges, we propose the Neural Systems Language (NSyL). NSyL is a modeling language to be used by investigators to encode and communicate systematically reports of neural connectivity from neuroanatomy and brain imaging. NSyL engenders systematic description and communication of connectivity irrespective of the animal taxon described, experimental or observational technique implemented, or nomenclature referenced. As a language, NSyL is internally consistent, concise, and comprehensible to both humans and computers. NSyL is a promising development for systematizing the representation of neural architecture, effectively managing the increasing volume of data on neural connectivity and streamlining systems neuroscience research. Here we present similar precedent systems, how NSyL extends existing frameworks, and the reasoning behind NSyL's development. We explore NSyL's potential for balancing robustness and consistency in representation by encoding previously reported assertions of connectivity from the literature as examples. Finally, we propose and discuss the implications of a framework for how NSyL will be digitally implemented in the future to streamline curation of experimental results and bridge the gaps among anatomists, imagers, and neuroinformatics databases.

  6. Proceedings of the of the Eleventh Workshop on Language Descriptions, Tools and Applications (LDTA 2011)

    DEFF Research Database (Denmark)

    . A primary focus of LDTA is grammarware that is generated from high-level grammar-centric specifications and thus submissions on parser generation, attribute grammar systems, term/graph rewriting systems, and other grammar-related meta-programming tools, techniques, and formalisms were encouraged. For 2011......, as well as techniques and tools, to the test in a new way in the form of the LDTA Tool Challenge. Tool developers were invited to participate in the Challenge by developing solutions to a range of language processing tasks over a simple but evolving set of imperative programming languages. Tool challenge......This volume contains the proceedings of the Eleventh Workshop on Language Descriptions, Tools and Applications (LDTA 2011), held in Saarbrücken, Germany on March 26 & 27, 2011. LDTA is a two-day satellite event of ETAPS (European Joint Conferences on Theory and Practice of Software) and organized...

  7. Root system markup language: toward a unified root architecture description language.

    Science.gov (United States)

    Lobet, Guillaume; Pound, Michael P; Diener, Julien; Pradal, Christophe; Draye, Xavier; Godin, Christophe; Javaux, Mathieu; Leitner, Daniel; Meunier, Félicien; Nacry, Philippe; Pridmore, Tony P; Schnepf, Andrea

    2015-03-01

    The number of image analysis tools supporting the extraction of architectural features of root systems has increased in recent years. These tools offer a handy set of complementary facilities, yet it is widely accepted that none of these software tools is able to extract in an efficient way the growing array of static and dynamic features for different types of images and species. We describe the Root System Markup Language (RSML), which has been designed to overcome two major challenges: (1) to enable portability of root architecture data between different software tools in an easy and interoperable manner, allowing seamless collaborative work; and (2) to provide a standard format upon which to base central repositories that will soon arise following the expanding worldwide root phenotyping effort. RSML follows the XML standard to store two- or three-dimensional image metadata, plant and root properties and geometries, continuous functions along individual root paths, and a suite of annotations at the image, plant, or root scale at one or several time points. Plant ontologies are used to describe botanical entities that are relevant at the scale of root system architecture. An XML schema describes the features and constraints of RSML, and open-source packages have been developed in several languages (R, Excel, Java, Python, and C#) to enable researchers to integrate RSML files into popular research workflow.

  8. Putting the Plain into Pain Language in English for Medical Purposes: Learner Inquiry into Patients' Online Descriptive Accounts

    Science.gov (United States)

    Plastina, Anna Franca

    2016-01-01

    The need to teach medical students plain language for their future engagement in pain communication can no longer be underestimated. Pain education has traditionally neglected the teaching of pain language, yet patients' descriptive accounts have been acknowledged as the standard in medical care. English for Medical Purposes (EMP) can make its…

  9. Using Specification and Description Language for Life Cycle Assesment in Buildings

    Directory of Open Access Journals (Sweden)

    Pau Fonseca i Casas

    2017-06-01

    Full Text Available The definition of a Life Cycle Assesment (LCA for a building or an urban area is a complex task due to the inherent complexity of all the elements that must be considered. Furthermore, a multidisciplinary approach is required due to the different sources of knowledge involved in this project. This multidisciplinary approach makes it necessary to use formal language to fully represent the complexity of the used models. In this paper, we explore the use of Specification and Description Language (SDL to represent the LCA of a building and residential area. We also introduce a tool that uses this idea to implement an optimization and simulation mechanism to define the optimal solution for the sustainability of a specific building or residential.

  10. Proceedings of the of the Tenth Workshop on Language Descriptions, Tools and Applications (LDTA 2010)

    DEFF Research Database (Denmark)

    Brabrand, Claus

    2010-01-01

    This volume contains the proceedings of the Tenth Workshop on Language Descriptions, Tools and Applications (LDTA 2010), held in Paphos, Cyprus on March 28--29, 2010. LDTA is a two-day satellite event of ETAPS (European Joint Conferences on Theory and Practice of Software) organized in cooperatio...... members of the program committee. In addition, the program committee sought the opinions of additional referees, selected because of their expertise on particular topics. The final selection of papers was made during the first week of February 2010....

  11. Efficiency of Picture Description and Storytelling Methods in Language Sampling According to the Mean Length of Utterance Index

    Directory of Open Access Journals (Sweden)

    Salime Jafari

    2012-10-01

    Full Text Available Background and Aim: Due to limitation of standardized tests for Persian-speakers with language disorders, spontaneous language sampling collection is an important part of assessment of languageprotocol. Therefore, selection of a language sampling method, which will provide information of linguistic competence in a short time, is important. Therefore, in this study, we compared the languagesamples elicited with picture description and storytelling methods in order to determine the effectiveness of the two methods.Methods: In this study 30 first-grade elementary school girls were selected with simple sampling. To investigate picture description method, we used two illustrated stories with four pictures. Languagesamples were collected through storytelling by telling a famous children’s story. To determine the effectiveness of these two methods the two indices of duration of sampling and mean length ofutterance (MLU were compared.Results: There was no significant difference between MLU in description and storytelling methods(p>0.05. However, duration of sampling was shorter in the picture description method than the storytelling method (p<0.05.Conclusion: Findings show that, the two methods of picture description and storytelling have the same potential in language sampling. Since, picture description method can provide language samples with the same complexity in a shorter time than storytelling, it can be used as a beneficial method forclinical purposes.

  12. A Logic Design Automation System for Generating Logic Diagram from Hardware Description

    Institute of Scientific and Technical Information of China (English)

    刘明业; 郭书明; 杨淮; 贾良玉; 洪恩宇

    1989-01-01

    This paper discusses a logic design automation system (LODAS) implemented on APOLLO DOMAIN workstation. LODAS can generate VLSI logic diagram from the hardware description. The system accepts many kinds of input description such as DDL or AHPL language description, functinual array (truth table), covering array , Boolean equations or state transition tables. The system first simulates the functional description to verify the functional description of the system designed, then the translator translates the fnnctional descriptong into register transfer equations, Boolean equatinos and state transition equations antomatically.Logic synthesis software partitions the translation result into a series of blocks, and transforma every small block into a mnlti-level NAND/NOR network according to the fan - in and fan - out restriction.

  13. A Logic Design Automation System for Generating Logic Diagram from Hardware Description

    Institute of Scientific and Technical Information of China (English)

    刘明业; 郭书明; 等

    1989-01-01

    This paper discusses a logic design automation system(LODAS) implemented on APOLLO DOMAIN workstation.LODAS can generate VLSI logic diagram from the hardware description.The system accepts many kinds of input description such as DDL or AHPL language description.Functional array(truth table).covering array,Boolean equations or state transition tables,The system first simulates the functional desecription to verify the functional description of the system designed.then translator translates the functional description into resgister transfer equation.Boolean equations and state transition equations automatically.Logic synthesis software partitions the translation result into a series of blocks,and transforms every small block into a multi-level NAND /NOR network according to the fan-in and fan-out restriction.

  14. Simulation Experiment Description Markup Language (SED-ML) Level 1 Version 2.

    Science.gov (United States)

    Bergmann, Frank T; Cooper, Jonathan; Le Novère, Nicolas; Nickerson, David; Waltemath, Dagmar

    2015-09-04

    The number, size and complexity of computational models of biological systems are growing at an ever increasing pace. It is imperative to build on existing studies by reusing and adapting existing models and parts thereof. The description of the structure of models is not sufficient to enable the reproduction of simulation results. One also needs to describe the procedures the models are subjected to, as recommended by the Minimum Information About a Simulation Experiment (MIASE) guidelines. This document presents Level 1 Version 2 of the Simulation Experiment Description Markup Language (SED-ML), a computer-readable format for encoding simulation and analysis experiments to apply to computational models. SED-ML files are encoded in the Extensible Markup Language (XML) and can be used in conjunction with any XML-based model encoding format, such as CellML or SBML. A SED-ML file includes details of which models to use, how to modify them prior to executing a simulation, which simulation and analysis procedures to apply, which results to extract and how to present them. Level 1 Version 2 extends the format by allowing the encoding of repeated and chained procedures.

  15. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  16. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  17. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  18. Flexible Description Language for HPC based Processing of Remote Sense Data

    Science.gov (United States)

    Nandra, Constantin; Gorgan, Dorian; Bacu, Victor

    2016-04-01

    When talking about Big Data, the most challenging aspect lays in processing them in order to gain new insight, find new patterns and gain knowledge from them. This problem is likely most apparent in the case of Earth Observation (EO) data. With ever higher numbers of data sources and increasing data acquisition rates, dealing with EO data is indeed a challenge [1]. Geoscientists should address this challenge by using flexible and efficient tools and platforms. To answer this trend, the BigEarth project [2] aims to combine the advantages of high performance computing solutions with flexible processing description methodologies in order to reduce both task execution times and task definition time and effort. As a component of the BigEarth platform, WorDeL (Workflow Description Language) [3] is intended to offer a flexible, compact and modular approach to the task definition process. WorDeL, unlike other description alternatives such as Python or shell scripts, is oriented towards the description topologies, using them as abstractions for the processing programs. This feature is intended to make it an attractive alternative for users lacking in programming experience. By promoting modular designs, WorDeL not only makes the processing descriptions more user-readable and intuitive, but also helps organizing the processing tasks into independent sub-tasks, which can be executed in parallel on multi-processor platforms in order to improve execution times. As a BigEarth platform [4] component, WorDeL represents the means by which the user interacts with the system, describing processing algorithms in terms of existing operators and workflows [5], which are ultimately translated into sets of executable commands. The WorDeL language has been designed to help in the definition of compute-intensive, batch tasks which can be distributed and executed on high-performance, cloud or grid-based architectures in order to improve the processing time. Main references for further

  19. Performance of Language-Coordinated Collective Systems: A Study of Wine Recognition and Description

    Science.gov (United States)

    Zubek, Julian; Denkiewicz, Michał; Dębska, Agnieszka; Radkowska, Alicja; Komorowska-Mach, Joanna; Litwin, Piotr; Stępień, Magdalena; Kucińska, Adrianna; Sitarska, Ewa; Komorowska, Krystyna; Fusaroli, Riccardo; Tylén, Kristian; Rączaszek-Leonardi, Joanna

    2016-01-01

    Most of our perceptions of and engagements with the world are shaped by our immersion in social interactions, cultural traditions, tools and linguistic categories. In this study we experimentally investigate the impact of two types of language-based coordination on the recognition and description of complex sensory stimuli: that of red wine. Participants were asked to taste, remember and successively recognize samples of wines within a larger set in a two-by-two experimental design: (1) either individually or in pairs, and (2) with or without the support of a sommelier card—a cultural linguistic tool designed for wine description. Both effectiveness of recognition and the kinds of errors in the four conditions were analyzed. While our experimental manipulations did not impact recognition accuracy, bias-variance decomposition of error revealed non-trivial differences in how participants solved the task. Pairs generally displayed reduced bias and increased variance compared to individuals, however the variance dropped significantly when they used the sommelier card. The effect of sommelier card reducing the variance was observed only in pairs, individuals did not seem to benefit from the cultural linguistic tool. Analysis of descriptions generated with the aid of sommelier cards shows that pairs were more coherent and discriminative than individuals. The findings are discussed in terms of global properties and dynamics of collective systems when constrained by different types of cultural practices. PMID:27729875

  20. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  1. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  2. Event Structure Influences Language Production: Evidence from Structural Priming in Motion Event Description

    Science.gov (United States)

    Bunger, Ann; Papafragou, Anna; Trueswell, John C.

    2013-01-01

    This priming study investigates the role of conceptual structure during language production, probing whether English speakers are sensitive to the structure of the event encoded by a prime sentence. In two experiments, participants read prime sentences aloud before describing motion events. Primes differed in 1) syntactic frame, 2) degree of lexical and conceptual overlap with target events, and 3) distribution of event components within frames. Results demonstrate that conceptual overlap between primes and targets led to priming of (a) the information that speakers chose to include in their descriptions of target events, (b) the way that information was mapped to linguistic elements, and (c) the syntactic structures that were built to communicate that information. When there was no conceptual overlap between primes and targets, priming was not successful. We conclude that conceptual structure is a level of representation activated during priming, and that it has implications for both Message Planning and Linguistic Formulation. PMID:24072953

  3. Automatic Circuit Extractor for HDL Description Using Program Slicing

    Institute of Scientific and Technical Information of China (English)

    Tun Li; Yang Guo; Si-Kun Li

    2004-01-01

    Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification,simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.

  4. A Coherent VLSI Design Environment.

    Science.gov (United States)

    2014-09-26

    physical devices from which physical circuits are fabricated. By analogy with context-free languages , a class of circuits is generated by a phrase-structure... language called CLU [131. It consists of SPICE interface, minimization, and matrix manipulation program modules. These modules contain 3200, 1800, and...greatly simplify the optimization problem. They reformulated the original problem, a minimization subject to nonlinear constraints, as an

  5. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  6. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  7. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  8. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  9. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  10. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  11. Psicopatologia descritiva: existe uma linguagem comum? Descriptive psychopathology: is there a common language?

    Directory of Open Access Journals (Sweden)

    Elie Cheniaux

    2005-06-01

    Full Text Available Com o objetivo de examinar se existe uma uniformidade entre os diversos autores quanto aos conceitos e termos da psicopatologia descritiva, foi realizada uma revisão de alguns dos principais livros dessa área, tanto brasileiros como internacionais. Constatou-se que não há verdadeiramente uma linguagem comum: determinados conceitos são considerados por alguns autores mas ignorados por outros; um mesmo termo é utilizado com diferentes sentidos; e um mesmo conceito é designado por termos diferentes. Alguns pontos de divergência entre os diversos psicopatólogos são aqui exemplificados e discutidos.We elaborated a review of some of the main books of descriptive psychopathology, Brazilian and international ones, with the objective of examining if there is uniformity among the various authors about concepts and terminology. We observed that there is not truly a common language: some concepts are used by some authors but are ignored by others; a same term is utilized with different meanings; and a same concept is assigned by different terms. Here some points of divergence among the various authors are presented and discussed.

  12. Performance of language-coordinated collective systems: A study of wine recognition and description

    Directory of Open Access Journals (Sweden)

    Julian Zubek

    2016-09-01

    Full Text Available Most of our perceptions of and engagements with the world are shaped by our immersion in socialinteractions, cultural traditions, tools and linguistic categories. In this study we experimentallyinvestigate the impact of two types of language-based coordination on the recognition anddescription of complex sensory stimuli: that of red wine. Participants were asked to taste,remember and successively recognize samples of wines within a larger set in a two-by-twoexperimental design: 1 either individually or in pairs, and 2 with or without the support of asommelier card – a cultural linguistic tool designed for wine description. Both effectiveness ofrecognition and the kinds of errors in the four conditions were analyzed. While our experimentalmanipulations did not impact recognition accuracy, bias-variance decomposition of error revealsnon-trivial differences in how participants solved the task. Pairs generally displayed reduced biasand increased variance compared to individuals, however the variance dropped significantly whenthey used the sommelier card. The effect of card reducing the variance was observed only inpairs, individuals did not seem to benefit from the cultural linguistic tool. Subsequent analysis ofdescriptions generated with the aid of card by individuals and pairs showed that they were moreconsistent and discriminative in the case of pairs. The findings are discussed in terms of globalproperties and dynamics of collective systems when constrained by different types of culturalpractices.

  13. Description of the Assessment of Basic Language and Learning Skills Revisited (ABLLS-R

    Directory of Open Access Journals (Sweden)

    Semenovich M.L.

    2015-12-01

    Full Text Available Diagnostics and assessment of the functional skills of children with disabilities and autism spectrum disorders are to be conducted to develop comprehensive remedial educational programmes. The described Methodology of the Assessment of Basic Language and Learning Skills — Revisited (ABLLS-R allows to simplify and make the diagnostics more efficient, to conduct a comprehensive examination of the child in different areas of development, detect the formed and deficit skills. The second and final part of the description of the methodology offers recommendations on the filling of the Table of the Results of Initial and Repeated Testing and on the choice of goals of correctional work with a child on the basis of performance of individual test scales. The pattern of the table filled after the initial and repeated testing is given. In drawing up of the programme of individual development the willingness of the child to the development of that skill should be considered. Regular practice of selected skills in various situations and the preventive measures against the regression of skills are also important. Conclusive part. Beginning in № 3 (48, 2015

  14. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  15. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  16. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  17. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  18. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  19. The Experience of Teaching of Descriptive Geometry and Engineering Graphics in Russian Language as a Foreign Language

    Science.gov (United States)

    Voronina, Marianna V.; Tretyakova, Zlata O.

    2017-01-01

    The article considers the peculiarities of training foreign students subject "Descriptive geometry and Engineering Graphics" in a modern engineering university of Russia. The relevance of the problem conditioned by the fact that virtually there are no special studies of teaching Descriptive Geometry and Engineering Graphics in Russian…

  20. The New Reynell Developmental Language Scales: Descriptive Account and Illustrative Case Study

    Science.gov (United States)

    Letts, Carolyn; Edwards, Susan; Schaefer, Blanca; Sinka, Indra

    2014-01-01

    This article describes the development of new scales for assessing the status of a young child's language comprehension and production. Items and sections on the scales were included to reflect advances in research on language acquisition and impairment. The New Reynell Developmental Language Scales (NRDLS) were trialled on 301 children and then…

  1. 现代语言的叙述与描写%Narration and Description of Modern Language

    Institute of Scientific and Technical Information of China (English)

    刘恪

    2014-01-01

    从中外理论比较的角度探讨叙述语言与描写语言的特征、功能、含义及文体建构,特别从理论深度去触摸叙述与描写的结构形态及其运用,透彻地阐释了形式语言学中两大表现方法。%This paper discusses the features,function,meaning and genre construction of narrative language and descriptive language from the comparative perspective of Chinese and foreign theories,especially studies the morphology and its application of narration and description from the theoretical depth,and thoroughly explains two major manifestations in formal linguistics.

  2. Measuring information acquisition from sensory input using automated scoring of natural-language descriptions.

    Directory of Open Access Journals (Sweden)

    Daniel R Saunders

    Full Text Available Information acquisition, the gathering and interpretation of sensory information, is a basic function of mobile organisms. We describe a new method for measuring this ability in humans, using free-recall responses to sensory stimuli which are scored objectively using a "wisdom of crowds" approach. As an example, we demonstrate this metric using perception of video stimuli. Immediately after viewing a 30 s video clip, subjects responded to a prompt to give a short description of the clip in natural language. These responses were scored automatically by comparison to a dataset of responses to the same clip by normally-sighted viewers (the crowd. In this case, the normative dataset consisted of responses to 200 clips by 60 subjects who were stratified by age (range 22 to 85 y and viewed the clips in the lab, for 2,400 responses, and by 99 crowdsourced participants (age range 20 to 66 y who viewed clips in their Web browser, for 4,000 responses. We compared different algorithms for computing these similarities and found that a simple count of the words in common had the best performance. It correctly matched 75% of the lab-sourced and 95% of crowdsourced responses to their corresponding clips. We validated the measure by showing that when the amount of information in the clip was degraded using defocus lenses, the shared word score decreased across the five predetermined visual-acuity levels, demonstrating a dose-response effect (N = 15. This approach, of scoring open-ended immediate free recall of the stimulus, is applicable not only to video, but also to other situations where a measure of the information that is successfully acquired is desirable. Information acquired will be affected by stimulus quality, sensory ability, and cognitive processes, so our metric can be used to assess each of these components when the others are controlled.

  3. Measuring information acquisition from sensory input using automated scoring of natural-language descriptions.

    Science.gov (United States)

    Saunders, Daniel R; Bex, Peter J; Rose, Dylan J; Woods, Russell L

    2014-01-01

    Information acquisition, the gathering and interpretation of sensory information, is a basic function of mobile organisms. We describe a new method for measuring this ability in humans, using free-recall responses to sensory stimuli which are scored objectively using a "wisdom of crowds" approach. As an example, we demonstrate this metric using perception of video stimuli. Immediately after viewing a 30 s video clip, subjects responded to a prompt to give a short description of the clip in natural language. These responses were scored automatically by comparison to a dataset of responses to the same clip by normally-sighted viewers (the crowd). In this case, the normative dataset consisted of responses to 200 clips by 60 subjects who were stratified by age (range 22 to 85 y) and viewed the clips in the lab, for 2,400 responses, and by 99 crowdsourced participants (age range 20 to 66 y) who viewed clips in their Web browser, for 4,000 responses. We compared different algorithms for computing these similarities and found that a simple count of the words in common had the best performance. It correctly matched 75% of the lab-sourced and 95% of crowdsourced responses to their corresponding clips. We validated the measure by showing that when the amount of information in the clip was degraded using defocus lenses, the shared word score decreased across the five predetermined visual-acuity levels, demonstrating a dose-response effect (N = 15). This approach, of scoring open-ended immediate free recall of the stimulus, is applicable not only to video, but also to other situations where a measure of the information that is successfully acquired is desirable. Information acquired will be affected by stimulus quality, sensory ability, and cognitive processes, so our metric can be used to assess each of these components when the others are controlled.

  4. Evaluating Pragmatic Competence in Nigerian Undergraduates' Language Errors within Descriptive ESL Writing

    Science.gov (United States)

    Muhammad, Anas Sa'idu; Nair, Subadrah Madhawa

    2017-01-01

    This study investigates the level of pragmatic competence for ESL writing skills among Nigerian undergraduates. Methodologically, it adopts descriptive research design within the explanatory framework of the QUAN-Qual model. The instruments used are descriptive essay text and focus group interview questions. In writing the descriptive essays, a…

  5. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  6. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  7. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  8. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  9. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  10. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  11. Agent Based Models of Language Competition: Macroscopic descriptions and Order-Disorder transitions

    CERN Document Server

    Vazquez, F; Miguel, M San

    2010-01-01

    We investigate the dynamics of two agent based models of language competition. In the first model, each individual can be in one of two possible states, either using language $X$ or language $Y$, while the second model incorporates a third state XY, representing individuals that use both languages (bilinguals). We analyze the models on complex networks and two-dimensional square lattices by analytical and numerical methods, and show that they exhibit a transition from one-language dominance to language coexistence. We find that the coexistence of languages is more difficult to maintain in the Bilinguals model, where the presence of bilinguals in use facilitates the ultimate dominance of one of the two languages. A stability analysis reveals that the coexistence is more unlikely to happen in poorly-connected than in fully connected networks, and that the dominance of only one language is enhanced as the connectivity decreases. This dominance effect is even stronger in a two-dimensional space, where domain coar...

  12. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  13. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  14. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  15. Behavioral interface description of an object-oriented language with futures and promises

    NARCIS (Netherlands)

    I. Grabe (Immo); E. Abraham; A. Gruener; M. Steffen

    2009-01-01

    textabstractThis paper formalizes the observable interface behavior of a concurrent, object-oriented language with futures and promises. The calculus captures the core of Creol, a language, featuring in particular asynchronous method calls and, since recently, first-class futures. The focus of the

  16. The Evolution of Foreign Language AP Exam Candidates: A 36-Year Descriptive Study

    Science.gov (United States)

    Brown, Alan V.; Thompson, Gregory L.

    2016-01-01

    Using a data set exclusively prepared for and licensed to them by the College Board, the authors examined the growth of the Advanced Placement program in foreign languages and overall trends in regard to the number of candidates who sat for the foreign language exams, their gender, their scores, and their ethnicity over the 36-year period covering…

  17. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  18. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  19. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  20. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  1. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  2. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  3. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  4. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  5. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  6. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  7. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  8. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  9. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  10. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  11. Proceedings of the of the Eleventh Workshop on Language Descriptions, Tools and Applications (LDTA 2011)

    DEFF Research Database (Denmark)

    , as well as techniques and tools, to the test in a new way in the form of the LDTA Tool Challenge. Tool developers were invited to participate in the Challenge by developing solutions to a range of language processing tasks over a simple but evolving set of imperative programming languages. Tool challenge...... participants presented highlights of their solution during special sessions of the workshop and will contribute to a joint paper on the Tool Challenge and proposed solutions to be co-authored by all participants after the workshop....

  12. THE AUDITORY LANGUAGE COMPREHENSION PROGRAM - A DESCRIPTION AND CASE-STUDY

    NARCIS (Netherlands)

    BASTIAANSE, R; TACONIS, M

    1993-01-01

    The Auditory Language Comprehension Programme is a Dutch therapy programme at the word level, especially developed for severely aphasic patients. The programme consists of 420 items divided over three parts. Each item consists of a larger word and three distractors. One spoken target word at a time

  13. From oral traditions to elementary textbooks: a description of the maternal languages project in Niger.

    Science.gov (United States)

    Stephens, C L

    1983-12-01

    Niger is experimenting with maternal language instruction in grades 1-3, within a broader context of educational reform. In these early grades, some 25 experimental schools distributed throughout the country are using 1 of 5 national languages -- Hausa, Zarma-Songhai, Fulfulde, Tamajaq, or Kanuri -- as the language of instruction and of standardized examinations, as in traditional schools. The curriculum in these experimental schools for the early grades is also innovative and favors an interdisciplinary approach. Lessons in various subjects are linked at any given time by a them selected by teachers and students. Niger's national pedagogical institute, in collaboration with the US Agency for International Development (USAID), designed a testbook project which was built around a recorded collection of oral traditions. Once assembled, this collection served as a resource to draw on for production of readers for grades 1 through 3. These readers provide content appropriate to the curriculum and serve as an archive of oral traditions for future use. The Institute's procedure for producing elementary readers in maternal languages has not only yielded the desired books but has also facilitated institutional development in several organizations committed to producing national language materials. The project has had several phases, including the collection, transcription, and cataloging of oral materials; the preselection, adaptation, final editing, and illustration of tests; the publication of the textbooks; and the evaluation of the textbooks. Over 70 primary school teachers participated in the collection phase during the summer vacation of 1981. The teachers were selected to assure a distribution of regions and dialects for each of the 5 languages. Before returning to their villages, trainees were issued Panasonic RQ 230 9A tape recorders, batteries, and a box of 20 cassettes. Supervisory teams composed of at least 1 linguist and 1 pedagogical advisor visited each

  14. Integration of literacy into speech-language therapy: a descriptive analysis of treatment practices.

    Science.gov (United States)

    Tambyraja, Sherine R; Schmitt, Mary Beth; Justice, Laura M; Logan, Jessica A R; Schwarz, Sadie

    2014-01-01

    The purpose of the present study was: (a) to examine the extent to which speech-language therapy provided to children with language disorders in the schools targets code-based literacy skills (e.g., alphabet knowledge and phonological awareness) during business-as-usual treatment sessions, and (b) to determine whether literacy-focused therapy time was associated with factors specific to children and/or speech-language pathologists (SLPs). Participants were 151 kindergarten and first-grade children and 40 SLPs. Video-recorded therapy sessions were coded to determine the amount of time that addressed literacy. Assessments of children's literacy skills were administered as well as questionnaires regarding characteristics of SLPs (e.g., service delivery, professional development). Results showed that time spent addressing code-related literacy across therapy sessions was variable. Significant predictors included SLP years of experience, therapy location, and therapy session duration, such that children receiving services from SLPs with more years of experience, and/or who utilized the classroom for therapy, received more literacy-focused time. Additionally, children in longer therapy sessions received more therapy time on literacy skills. There is considerable variability in the extent to which children received literacy-focused time in therapy; however, SLP-level factors predict time spent in literacy more than child-level factors. Further research is needed to understand the nature of literacy-focused therapy in the public schools. Readers will be able to: (a) define code-based literacy skills, (b) discuss the role that speech-language pathologists have in fostering children's literacy development, and (c) identify key factors that may currently influence the inclusion of literacy targets in school-based speech-language therapy. Copyright © 2014 Elsevier Inc. All rights reserved.

  15. A descriptive study of culture related terms in translation of Harry Potter Novel from English to Urdu language

    Directory of Open Access Journals (Sweden)

    Sana Mansoor

    2016-05-01

    Full Text Available Translation of children fantasy novels and problems faced by translators in translating these novels into different languages is one of the core issues in the field of translation studies. This issue has got attention of many researchers and an extensive study has been carried out on various novels. The Harry Potter series of novels written by British author J.K. Rowling is one of the famous children fantasy novels that gained popularity worldwide and was translated into 73 languages. The use of various cultural terms and made up words in the novel has posed a great challenge for the translators. The purpose of the present study is to identify these cultural related terms and made up words in the novel “Harry Potter and the Chamber of Secrets” and to investigate the strategies used by the translator in translating them into Urdu language. A descriptive analysis of the translation of culture related items and made up words was made using the strategies proposed by Davies (2003. The findings of this research showed that translator mostly emphasized and predominantly used localization and transformation strategies for food items, magical objects and imaginative words.

  16. Towards "Thick Description" of Educational Transfer: Understanding a Japanese Institution's "Import" of European Language Policy

    Science.gov (United States)

    Rappleye, Jeremy; Imoto, Yuki; Horiguchi, Sachiko

    2011-01-01

    Globalisation and convergence in educational policy worldwide has reinvigorated, while rendering more complex, the classic theme of educational transfer. Framed by this wider pursuit of new understandings of a changing transfer/context puzzle, this paper explores how an ethnographic "thick description" might complement and extend recent research.…

  17. Corpus-based Grammar and the Heineken Effect: Lexico-grammatical Description for Language Learners.

    Science.gov (United States)

    Owen, Charles

    1993-01-01

    The current status of corpus-based lexico-grammar is assessed. Particular reference is to the one substantial descriptive grammar of English to have made use of the new computational techniques, the Collins COBUILD English Grammar. (39 references) (Author/LB)

  18. 一个轻量级多设备用户界面描述语言MDUIDL%Lightweight multi-device user interface description language MDUIDL

    Institute of Scientific and Technical Information of China (English)

    吴昊; 华庆一; 常言说; 朱海阳; 杨建峰

    2011-01-01

    To adapt for the requirement of user interface development in multi-device environment and address the problem that current UIDL has,this paper designs and implements a lightweight multi-device user interface description language MDU-IDL.This language is divided into abstract interface description language,specific interface description language,event description language and device description language, which respectively describe the different sides of user interface of multi-device application system.By a case study,this paper shows that the language has a good ability of description interface and supports for multi-device environment,and it is so simple that one can learn and use easily.%为适应多设备环境下用户界面开发的需求,解决当前UIDL存在的一些问题,设计并实现了一个轻量级多设备用户界面描述语言MDUIDL.该语言分为抽象界面描述语言、具体界面描述语言、事件描述语言和设备描述语言,分别从不同侧面对多设备应用系统的用户界面进行描述.通过实例研究,表明该语言具有良好的界面表达能力和对多设备环境的支持,且简单易学,易于使用.

  19. Software dependability modeling using an industry-standard architecture description language

    CERN Document Server

    Rugina, Ana-Elena; Kanoun, Karama; Kaaniche, Mohamed

    2008-01-01

    Performing dependability evaluation along with other analyses at architectural level allows both making architectural tradeoffs and predicting the effects of architectural decisions on the dependability of an application. This paper gives guidelines for building architectural dependability models for software systems using the AADL (Architecture Analysis and Design Language). It presents reusable modeling patterns for fault-tolerant applications and shows how the presented patterns can be used in the context of a subsystem of a real-life application.

  20. Using the Unified Modelling Language (UML) to guide the systemic description of biological processes and systems.

    Science.gov (United States)

    Roux-Rouquié, Magali; Caritey, Nicolas; Gaubert, Laurent; Rosenthal-Sabroux, Camille

    2004-07-01

    One of the main issues in Systems Biology is to deal with semantic data integration. Previously, we examined the requirements for a reference conceptual model to guide semantic integration based on the systemic principles. In the present paper, we examine the usefulness of the Unified Modelling Language (UML) to describe and specify biological systems and processes. This makes unambiguous representations of biological systems, which would be suitable for translation into mathematical and computational formalisms, enabling analysis, simulation and prediction of these systems behaviours.

  1. PyDecay/GraphPhys: A Unified Language and Storage System for Particle Decay Process Descriptions

    Energy Technology Data Exchange (ETDEWEB)

    Dunietz, Jesse N.; /MIT /SLAC

    2011-06-22

    To ease the tasks of Monte Carlo (MC) simulation and event reconstruction (i.e. inferring particle-decay events from experimental data) for long-term BaBar data preservation and analysis, the following software components have been designed: a language ('GraphPhys') for specifying decay processes, common to both simulation and data analysis, allowing arbitrary parameters on particles, decays, and entire processes; an automated visualization tool to show graphically what decays have been specified; and a searchable database storage mechanism for decay specifications. Unlike HepML, a proposed XML standard for HEP metadata, the specification language is designed not for data interchange between computer systems, but rather for direct manipulation by human beings as well as computers. The components are interoperable: the information parsed from files in the specification language can easily be rendered as an image by the visualization package, and conversion between decay representations was implemented. Several proof-of-concept command-line tools were built based on this framework. Applications include building easier and more efficient interfaces to existing analysis tools for current projects (e.g. BaBar/BESII), providing a framework for analyses in future experimental settings (e.g. LHC/SuperB), and outreach programs that involve giving students access to BaBar data and analysis tools to give them a hands-on feel for scientific analysis.

  2. An assessment of pre-service language teachers’ practicum observation forms: descriptive observation vs. critical observation

    OpenAIRE

    Genc, Bilal; Buyukkarci, Kagan

    2013-01-01

    Practicing the role of teacher and auditing/observing experienced teachers are essential parts of practicum studies of pre-service teachers. Regarding observation we differentiate between two kinds of practice: descriptive observation and critical observation. In this paper we reported on 38 pre-service teachers’ weekly practicum study observation reports of the classes they taught and audited over a twelve week period during their practicum study. The study examined the level of critical obs...

  3. Systemic functional grammar in natural language generation linguistic description and computational representation

    CERN Document Server

    Teich, Elke

    1999-01-01

    This volume deals with the computational application of systemic functional grammar (SFG) for natural language generation. In particular, it describes the implementation of a fragment of the grammar of German in the computational framework of KOMET-PENMAN for multilingual generation. The text also presents a specification of explicit well-formedness constraints on syntagmatic structure which are defined in the form of typed feature structures. It thus achieves a model of systemic functional grammar that unites both the strengths of systemics, such as stratification, functional diversification

  4. An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

    CERN Document Server

    Mücke, M; Jacobsson, R

    2007-01-01

    Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that funct...

  5. A Method for Cyber-Physical System Behavior Modeling and Safety Verification Based on Extended Hybrid System Description Language

    Directory of Open Access Journals (Sweden)

    Tuo Ming Fu

    2016-01-01

    Full Text Available The safety of Cyber-physical system(CPS is up to its behavior, and it is a key property for CPS to be applied in critical application fields. A method for CPS behavior modeling and safety verification is put forward in this paper. The behavior model of CPS is described by extended hybrid system description language(EHYSDEL. The formal definition of hybrid program(HP is given, and the behavior model is transformed to HP based on the definition. The safety of CPS is verified by inputting the HP to KeYmarea. The advantage of the approach is that it models CPS intuitively and verify it’s safety strictly avoiding the state space explosion

  6. Performance of language-coordinated collective systems: A study of wine recognition and description

    DEFF Research Database (Denmark)

    Zubek, Julian; Denkiewicz, Michał; Dębska, Agnieszka

    2016-01-01

    of complex sensory stimuli: that of red wine. Participants were asked to taste, remember and successively recognize samples of wines within a larger set in a two-by-two experimental design: 1) either individually or in pairs, and 2) with or without the support of a sommelier card – a cultural linguistic tool...... designed for wine description. Both effectiveness of recognition and the kinds of errors in the four conditions were analyzed. While our experimental manipulations did not impact recognition accuracy, bias-variance decomposition of error reveals non-trivial differences in how participants solved the task...

  7. Do Decision Rules Matter? A Descriptive Study of English Language Proficiency Assessment Classifications for English-Language Learners and Native English Speakers in Fifth Grade

    Science.gov (United States)

    Carroll, Patricia E.; Bailey, Alison L.

    2016-01-01

    English language proficiency assessments (ELPA) are used in the United States to measure annually the English language progress and proficiency of English-language learners (ELLs), a subgroup of language minority students who receive language acquisition support mandated and largely funded by Title III (NCLB, 2001). ELPA proficient and…

  8. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  9. Beyond description. Comment on "Approaching human language with complex networks" by Cong and Liu

    Science.gov (United States)

    Ferrer-i-Cancho, R.

    2014-12-01

    In their historical overview, Cong & Liu highlight Sausurre as the father of modern linguistics [1]. They apparently miss G.K. Zipf as a pioneer of the view of language as a complex system. His idea of a balance between unification and diversification forces in the organization of natural systems, e.g., vocabularies [2], can be seen as a precursor of the view of complexity as a balance between order (unification) and disorder (diversification) near the edge of chaos [3]. Although not mentioned by Cong & Liu somewhere else, trade-offs between hearer and speaker needs are very important in Zipf's view, which has inspired research on the optimal networks mapping words into meanings [4-6]. Quantitative linguists regard G.K. Zipf as the funder of modern quantitative linguistics [7], a discipline where statistics plays a central role as in network science. Interestingly, that centrality of statistics is missing Saussure's work and that of many of his successors.

  10. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  11. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  12. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  13. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  14. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  15. Descriptive Metaphysics, Natural Language Metaphysics, Sapir-Whorf, and All That Stuff: Evidence from the Mass-Count Distinction

    Directory of Open Access Journals (Sweden)

    Francis Jeffry Pelletier

    2010-12-01

    Full Text Available Strawson (1959 described ‘descriptive metaphysics’, Bach (1986a described ‘natural language metaphysics’, Sapir (1929 and Whorf (1940a,b, 1941 describe, well, Sapir-Whorfianism. And there are other views concerning the relation between correct semantic analysis of linguistic phenomena and the “reality” that is supposed to be thereby described. I think some considerations from the analyses of the mass-count distinction can shed some light on that very dark topic.ReferencesBach, Emmon. 1986a. ‘Natural Language Metaphysics’. In Ruth Barcan Marcus, G.J.W. Dorn & Paul Weingartner (eds. ‘Logic, Methodology, and Philosophy of Science, VII’, 573–595. Amsterdam: North Holland.Bach, Emmon. 1986b. ‘The Algebra of Events’. Linguistics and Philosophy 9: 5–16.Berger, Peter & Luckmann, Thomas. 1966. The Social Construction of Reality: A Treatise in the Sociology of Knowledge. New York: Doubleday.Boroditsky, Lera, Schmidt, Lauren & Phillips, Webb. 2003. ‘Sex, Syntax, and Semantics’. In Dedre Gentner & Susan Goldin-Meadow (eds. ‘Language in Mind: Advances in the Study of Language and Cognition’, 59–80. Cambridge, MA: MIT Press.Cheng, L. & Sybesma, R. 1999. ‘Bare and Not-So-Bare Nouns and the structure of NP’. Linguistic Inquiry 30: 509–542.http://dx.doi.org/10.1162/002438999554192Chierchia, Gennaro. 1998a. ‘Reference to Kinds across Languages’. Natural Language Semantics 6: 339–405.http://dx.doi.org/10.1023/A:1008324218506Chierchia, Gennaro. 1998b. ‘Plurality of Mass Nouns and the Notion of ‘Semantic Parameter’ ’. In S. Rothstein (ed. ‘Events and Grammar’, 53–103. Dordrecht: Kluwer.Chierchia, Gennaro. 2010. ‘Mass Nouns, Vagueness and Semantic Variation’. Synthèse 174: 99–149.http://dx.doi.org/10.1007/s11229-009-9686-6Doetjes, Jenny. 1997. Quantifiers and Selection: On the Distribution of Quantifying Expressions in French, Dutch and English. Ph.D. thesis, University of Leiden, Holland

  16. Text-Based Argumentation with Multiple Sources: A Descriptive Study of Opportunity to Learn in Secondary English Language Arts, History, and Science

    Science.gov (United States)

    Litman, Cindy; Marple, Stacy; Greenleaf, Cynthia; Charney-Sirott, Irisa; Bolz, Michael J.; Richardson, Lisa K.; Hall, Allison H.; George, MariAnne; Goldman, Susan R.

    2017-01-01

    This study presents a descriptive analysis of 71 videotaped lessons taught by 34 highly regarded secondary English language arts, history, and science teachers, collected to inform an intervention focused on evidence-based argumentation from multiple text sources. Studying the practices of highly regarded teachers is valuable for identifying…

  17. Text-Based Argumentation with Multiple Sources: A Descriptive Study of Opportunity to Learn in Secondary English Language Arts, History, and Science

    Science.gov (United States)

    Litman, Cindy; Marple, Stacy; Greenleaf, Cynthia; Charney-Sirott, Irisa; Bolz, Michael J.; Richardson, Lisa K.; Hall, Allison H.; George, MariAnne; Goldman, Susan R.

    2017-01-01

    This study presents a descriptive analysis of 71 videotaped lessons taught by 34 highly regarded secondary English language arts, history, and science teachers, collected to inform an intervention focused on evidence-based argumentation from multiple text sources. Studying the practices of highly regarded teachers is valuable for identifying…

  18. From a concept to a word in a syntactically complete sentence: an fMRI study on spontaneous language production in an overt picture description task.

    Science.gov (United States)

    Grande, Marion; Meffert, Elisabeth; Schoenberger, Eva; Jung, Stefanie; Frauenrath, Tobias; Huber, Walter; Hussmann, Katja; Moormann, Mareike; Heim, Stefan

    2012-07-02

    Spontaneous language has rarely been subjected to neuroimaging studies. This study therefore introduces a newly developed method for the analysis of linguistic phenomena observed in continuous language production during fMRI. Most neuroimaging studies investigating language have so far focussed on single word or - to a smaller extent - sentence processing, mostly due to methodological considerations. Natural language production, however, is far more than the mere combination of words to larger units. Therefore, the present study aimed at relating brain activation to linguistic phenomena like word-finding difficulties or syntactic completeness in a continuous language fMRI paradigm. A picture description task with special constraints was used to provoke hesitation phenomena and speech errors. The transcribed speech sample was segmented into events of one second and each event was assigned to one category of a complex schema especially developed for this purpose. The main results were: conceptual planning engages bilateral activation of the precuneus. Successful lexical retrieval is accompanied - particularly in comparison to unsolved word-finding difficulties - by the left middle and superior temporal gyrus. Syntactic completeness is reflected in activation of the left inferior frontal gyrus (IFG) (area 44). In sum, the method has proven to be useful for investigating the neural correlates of lexical and syntactic phenomena in an overt picture description task. This opens up new prospects for the analysis of spontaneous language production during fMRI.

  19. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  20. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  1. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  2. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  3. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  4. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  5. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  6. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  7. A production-quality UNIX Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) subset analyzer

    Science.gov (United States)

    Bratton, Randolph M.

    1987-12-01

    This paper describes the design and implementation of the Air Force Institute of Technology's (AFIT's) UNIX-based VHDL Analyzer. The purpose of this tool is to facilitate the introduction of VHDL into the academic environment, which may not be able to use the Department of Defense's VMS-based software. This research emphasized two areas: the criteria for a production-quality software product and the design of an efficient Intermediate Representation (IR) that serves as an interface between the Analyzer and other tools in the AFIT VHDL Environment (AVE). Background on other UNIX VHDL analyzers, as well as other IRs, was presented. A two-part IR, based on Dallen's Patois hardware description language and named the VHDL Intermediate Access (VIA), was designed, and examples were given that illustrate its use. Test results showed that the Analyzer passed over 75 percent of the conformance tests from the VHDL VMS Analyzer Test Suite and performed well in the areas of compile time, memory usage, and disk usage. Recommendations for future research include adding user options to the Analyzer and implementing a design library for VHDL designs.

  8. Language

    DEFF Research Database (Denmark)

    Sanden, Guro Refsum

    2016-01-01

    Purpose: – The purpose of this paper is to analyse the consequences of globalisation in the area of corporate communication, and investigate how language may be managed as a strategic resource. Design/methodology/approach: – A review of previous studies on the effects of globalisation on corporate...... communication and the implications of language management initiatives in international business. Findings: – Efficient language management can turn language into a strategic resource. Language needs analyses, i.e. linguistic auditing/language check-ups, can be used to determine the language situation...... of a company. Language policies and/or strategies can be used to regulate a company’s internal modes of communication. Language management tools can be deployed to address existing and expected language needs. Continuous feedback from the front line ensures strategic learning and reduces the risk of suboptimal...

  9. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  10. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  11. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  12. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  13. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  14. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  15. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  16. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  17. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  18. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  19. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  20. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  1. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  2. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  3. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  4. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  5. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  6. Automatic classification of written descriptions by healthy adults: An overview of the application of natural language processing and machine learning techniques to clinical discourse analysis

    Directory of Open Access Journals (Sweden)

    Cíntia Matsuda Toledo

    Full Text Available Discourse production is an important aspect in the evaluation of brain-injured individuals. We believe that studies comparing the performance of brain-injured subjects with that of healthy controls must use groups with compatible education. A pioneering application of machine learning methods using Brazilian Portuguese for clinical purposes is described, highlighting education as an important variable in the Brazilian scenario.OBJECTIVE: The aims were to describe how to: (i develop machine learning classifiers using features generated by natural language processing tools to distinguish descriptions produced by healthy individuals into classes based on their years of education; and (ii automatically identify the features that best distinguish the groups.METHODS: The approach proposed here extracts linguistic features automatically from the written descriptions with the aid of two Natural Language Processing tools: Coh-Metrix-Port and AIC. It also includes nine task-specific features (three new ones, two extracted manually, besides description time; type of scene described - simple or complex; presentation order - which type of picture was described first; and age. In this study, the descriptions by 144 of the subjects studied in Toledo18 were used, which included 200 healthy Brazilians of both genders.RESULTS AND CONCLUSION:A Support Vector Machine (SVM with a radial basis function (RBF kernel is the most recommended approach for the binary classification of our data, classifying three of the four initial classes. CfsSubsetEval (CFS is a strong candidate to replace manual feature selection methods.

  7. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  8. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  9. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  10. Is there a domain-general cognitive structuring system? Evidence from structural priming across music, math, action descriptions, and language.

    Science.gov (United States)

    Van de Cavey, Joris; Hartsuiker, Robert J

    2016-01-01

    Cognitive processing in many domains (e.g., sentence comprehension, music listening, and math solving) requires sequential information to be organized into an integrational structure. There appears to be some overlap in integrational processing across domains, as shown by cross-domain interference effects when for example linguistic and musical stimuli are jointly presented (Koelsch, Gunter, Wittfoth, & Sammler, 2005; Slevc, Rosenberg, & Patel, 2009). These findings support theories of overlapping resources for integrational processing across domains (cfr. SSIRH Patel, 2003; SWM, Kljajevic, 2010). However, there are some limitations to the studies mentioned above, such as the frequent use of unnaturalistic integrational difficulties. In recent years, the idea has risen that evidence for domain-generality in structural processing might also be yielded though priming paradigms (cfr. Scheepers, 2003). The rationale behind this is that integrational processing across domains regularly requires the processing of dependencies across short or long distances in the sequence, involving respectively less or more syntactic working memory resources (cfr. SWM, Kljajevic, 2010), and such processing decisions might persist over time. However, whereas recent studies have shown suggestive priming of integrational structure between language and arithmetics (though often dependent on arithmetic performance, cfr. Scheepers et al., 2011; Scheepers & Sturt, 2014), it remains to be investigated to what extent we can also find evidence for priming in other domains, such as music and action (cfr. SWM, Kljajevic, 2010). Experiment 1a showed structural priming from the processing of musical sequences onto the position in the sentence structure (early or late) to which a relative clause was attached in subsequent sentence completion. Importantly, Experiment 1b showed that a similar structural manipulation based on non-hierarchically ordered color sequences did not yield any priming effect

  11. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  12. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  13. LANGUAGE

    Institute of Scientific and Technical Information of China (English)

    朱妤

    2009-01-01

    @@ The word"language"comes from the Latin(拉丁语)word"lingua",which means"tongue".The tongue is used in more sound combinations(结合)than any other organ(器官)of speech.A broader(概括性的)interpretation(解释)of"language"is that it is any form of expression.This includes(包括)writing,sign(手势)language,dance,music,painting,and mathematics.But the basic(基本的)form of language is speech.

  14. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  15. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  16. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  17. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  18. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  19. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  20. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  1. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  2. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  3. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  4. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  5. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  6. Programmer's manual for IOSYM: an input-oriented simulation language for continuous systems. Volume 2: subprogram description

    Energy Technology Data Exchange (ETDEWEB)

    Smith, D.M.

    1981-06-01

    IOSYM is an extension of the GASP IV simulation language. It permits systems which are sequences of continuous processes to be modeled graphically. Normally the system can be described by data input only. The language permits stochastic sequencing and termination criteria for processes and allows crossing conditions for ending operations that are more general than GASP IV. Extensive capability exists for conditional branching and logical modification of the network. IOSYM has been used to model the cost of geothermal drilling where the various costly processes of drilling are represented by IOSYM operations. The language is much more general however; it retains more of GASP IV's discrete event capabilities and permits easy modeling of continuous processes.

  7. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  8. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  9. VHDL-AMS :An Analog/Mixed Signal Hardware Description Language%模拟混合信号硬件描述语言VHDL-AMS综述

    Institute of Scientific and Technical Information of China (English)

    韩泽耀; 叶润涛

    2001-01-01

    介绍了VHDL-AMS(VHDL 1076.1)-一种完全集成的混合信号设计语言,针对该 语言的要素进行了探讨,通过描述该语言的理论基础、混合建模、语言和应用范围等,阐述了VHDL-AMS硬件描述语言在模拟和数字混合信号领域应用中的必要性及其优点等。%VHDL-AMS(VHDL 1076. 1), an entirely integrated mixed signal design language, is presented in the paper. Discussions are made based on its substantial elements. The necessity of VHDL-AMS hardware description language in the application of analog/digital mixed signal IC's and its advantages are explained through the description of its theoretical basis, principle of mixed modeling and its application scopes.

  10. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  11. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  12. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  13. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  14. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  15. 面向中国手语合成的视频语义描述方法%Video Semantic Description Method for Chinese Sign Language Synthesis

    Institute of Scientific and Technical Information of China (English)

    王茹; 尹宝才; 王立春; 孔德慧

    2012-01-01

    To improve synthesis realistic of sign language videos,a method to describe sign language video semantics is proposed,and the sign language video database based on semantic description for sign language synthesis is constructed.Chinese sign language videos in specific research field are captured,then sign language video units and multi-dimensional transition units are cut from the captured sign language videos.By describing the semantic information of every frame in sign language videos,which include locations,hand shapes and rhythm information,their multi-dimensional semantic models are constructed.During sign language video synthesis,useful information can be used in real-time by parsing multi-dimensional semantic models.This method provides real-time and coherent semantic information for sign language video synthesis,and in the process of joining two sign language videos,different rhythm information can be parsed out from their semantic models,then interpolated locations of transition frames can be moderately adjusted to make the rhythm in transition frames gradually change.%为提高手语合成视频的真实感,提出一种面向手语合成的视频语义描述方法,并基于语义描述构建出相应的视频数据库.采集特定研究领域的手语视频数据,按照词义把源视频切分成词条基元和基于人体-部件的多层次过渡基元,通过对视频基元每帧图像进行语义描述来建立它们的多维语义模型.每个视频基元的多维语义模型代表了该视频每帧图像所包含的具体手语信息,包括位置、手形、韵律等.在手语合成过程中,通过解析视频的多维语义模型即可实时地调用有用的信息.该视频语义描述方法可为手语合成提供实时一致的语义理解,并且在拼接2段不同韵律的手语视频时,可通过解析出的韵律信息适当地调整过渡帧的插值位置,进而合成韵律一致的过渡视频.

  16. Ontology Language to Support Description of Experiment Control System Semantics, Collaborative Knowledge-Base Design and Ontology Reuse

    Energy Technology Data Exchange (ETDEWEB)

    Vardan Gyurjyan, D Abbott, G Heyes, E Jastrzembski, B Moffit, C Timmer, E Wolin

    2009-10-01

    In this paper we discuss the control domain specific ontology that is built on top of the domain-neutral Resource Definition Framework (RDF). Specifically, we will discuss the relevant set of ontology concepts along with the relationships among them in order to describe experiment control components and generic event-based state machines. Control Oriented Ontology Language (COOL) is a meta-data modeling language that provides generic means for representation of physics experiment control processes and components, and their relationships, rules and axioms. It provides a semantic reference frame that is useful for automating the communication of information for configuration, deployment and operation. COOL has been successfully used to develop a complete and dynamic knowledge-base for experiment control systems, developed using the AFECS framework.

  17. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  18. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  19. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  20. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  1. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  2. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  3. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  4. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  5. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  6. A Production-Quality Unix Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) Subset Analyzer.

    Science.gov (United States)

    1987-12-01

    generally prefers UNIX . Using common UNIX tools, such as the programming language C ( Kernighan and Ritchie, 1978) and compiler-compilers like yacc...081S 832 A PfODUCTION-GUALITY UNIX VERY HIGH SPEED INTEGRATED 2 CIRCUIT (VHSIC) HARD..(U) AIR FORCE INST OF TECH HRIGHT-PATTERSON AFI OH SCHOOL OF...Base, Ohio glt -e bowSV a 3 88 2 4 046 -Vsr AFITIGCS/NA/87D-1 A PRODUCTION-QUALITY UNIX VERY HIGH SPEED INTEGRATED CIRCUIT (VISIC) HARDWARE

  7. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  8. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  9. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  10. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  11. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  12. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  13. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  14. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  15. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  16. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  17. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  18. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  19. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  20. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  1. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  2. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  3. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  4. Revealing Dimensions of Thinking in Open-Ended Self-Descriptions: An Automated Meaning Extraction Method for Natural Language.

    Science.gov (United States)

    2008-02-01

    A new method for extracting common themes from written text is introduced and applied to 1,165 open-ended self-descriptive narratives. Drawing on a lexical approach to personality, the most commonly-used adjectives within narratives written by college students were identified using computerized text analytic tools. A factor analysis on the use of these adjectives in the self-descriptions produced a 7-factor solution consisting of psychologically meaningful dimensions. Some dimensions were unipolar (e.g., Negativity factor, wherein most loaded items were negatively valenced adjectives); others were dimensional in that semantically opposite words clustered together (e.g., Sociability factor, wherein terms such as shy, outgoing, reserved, and loud all loaded in the same direction). The factors exhibited modest reliability across different types of writ writing samples and were correlated with self-reports and behaviors consistent with the dimensions. Similar analyses with additional content words (adjectives, adverbs, nouns, and verbs) yielded additional psychological dimensions associated with physical appearance, school, relationships, etc. in which people contextualize their self-concepts. The results suggest that the meaning extraction method is a promising strategy that determines the dimensions along which people think about themselves.

  5. Unified Modeling Language description of the object-oriented multi-scale adaptive finite element method for Step-and-Flash Imprint Lithography Simulations

    Science.gov (United States)

    Paszyński, Maciej; Gurgul, Piotr; Sieniek, Marcin; Pardo, David

    2010-06-01

    In the first part of the paper we present the multi-scale simulation of the Step-and-Flash Imprint Lithography (SFIL), a modern patterning process. The simulation utilizes the hp adaptive Finite Element Method (hp-FEM) coupled with Molecular Statics (MS) model. Thus, we consider the multi-scale problem, with molecular statics applied in the areas of the mesh where the highest accuracy is required, and the continuous linear elasticity with thermal expansion coefficient applied in the remaining part of the domain. The degrees of freedom from macro-scale element's nodes located on the macro-scale side of the interface have been identified with particles from nano-scale elements located on the nano-scale side of the interface. In the second part of the paper we present Unified Modeling Language (UML) description of the resulting multi-scale application (hp-FEM coupled with MS). We investigated classical, procedural codes from the point of view of the object-oriented (O-O) programming paradigm. The discovered hierarchical structure of classes and algorithms makes the UML project as independent on the spatial dimension of the problem as possible. The O-O UML project was defined at an abstract level, independent on the programming language used.

  6. A Description Logic Primer

    CERN Document Server

    Krötzsch, Markus; Horrocks, Ian

    2012-01-01

    This paper provides a self-contained first introduction to description logics (DLs). The main concepts and features are explained with examples before syntax and semantics of the DL SROIQ are defined in detail. Additional sections review light-weight DL languages, discuss the relationship to the Web Ontology Language OWL and give pointers to further reading.

  7. Beyond gender stereotypes in language comprehension: self sex-role descriptions affect the brain's potentials associated with agreement processing

    Directory of Open Access Journals (Sweden)

    Paolo eCanal

    2015-12-01

    Full Text Available We recorded Event-Related Potentials to investigate differences in the use of gender information during the processing of reflexive pronouns. Pronouns either matched the gender provided by role nouns (such as king or engineer or did not. We compared two types of gender information, definitional information, which is semantic in nature (a mother is female, or stereotypical (a nurse is likely to be female. When they followed definitional role-nouns, gender-mismatching pronouns elicited a P600 effect reflecting a failure in the agreement process. When instead the gender violation occurred after stereotypical role-nouns the ERP response was biphasic, being positive in parietal electrodes and negative in anterior left electrodes. The use of a correlational approach showed that those participants with more feminine or expressive self sex-role descriptions showed a P600 response for stereotype violations, suggesting that they experienced the mismatch as an agreement violation; whereas less expressive participants showed an Nref effect, indicating more effort spent in linking the pronouns with the possible, although less likely, counter-stereotypical referent.

  8. Beyond Gender Stereotypes in Language Comprehension: Self Sex-Role Descriptions Affect the Brain's Potentials Associated with Agreement Processing.

    Science.gov (United States)

    Canal, Paolo; Garnham, Alan; Oakhill, Jane

    2015-01-01

    We recorded Event-Related Potentials to investigate differences in the use of gender information during the processing of reflexive pronouns. Pronouns either matched the gender provided by role nouns (such as "king" or "engineer") or did not. We compared two types of gender information, definitional information, which is semantic in nature (a mother is female), or stereotypical (a nurse is likely to be female). When they followed definitional role-nouns, gender-mismatching pronouns elicited a P600 effect reflecting a failure in the agreement process. When instead the gender violation occurred after stereotypical role-nouns the Event Related Potential response was biphasic, being positive in parietal electrodes and negative in anterior left electrodes. The use of a correlational approach showed that those participants with more "feminine" or "expressive" self sex-role descriptions showed a P600 response for stereotype violations, suggesting that they experienced the mismatch as an agreement violation; whereas less "expressive" participants showed an Nref effect, indicating more effort spent in linking the pronouns with the possible, although less likely, counter-stereotypical referent.

  9. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  10. Software Architecture Description and UML

    NARCIS (Netherlands)

    Avgeriou, Paris; Guelfi, Nicolas; Medvidovic, Nenad

    2005-01-01

    The description of software architectures has always been concerned with the definition of the appropriate languages for designing the various architectural artifacts. Over the past ten years, formal or less formal Architecture Description Languages (ADLs) and supporting methods and tools have been

  11. La Description des langues naturelles en vue d'applications linguistiques: Actes du colloque (The Description of Natural Languages with a View to Linguistic Applications: Conference Papers). Publication K-10.

    Science.gov (United States)

    Ouellon, Conrad, Comp.

    Presentations from a colloquium on applications of research on natural languages to computer science address the following topics: (1) analysis of complex adverbs; (2) parser use in computerized text analysis; (3) French language utilities; (4) lexicographic mapping of official language notices; (5) phonographic codification of Spanish; (6)…

  12. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  13. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  14. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  15. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  16. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  17. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  18. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  19. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  20. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  1. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  2. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  3. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  4. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  5. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  6. A brief description and comparison of programming languages FORTRAN, ALGOL, COBOL, PL/1, and LISP 1.5 from a critical standpoint

    Science.gov (United States)

    Mathur, F. P.

    1972-01-01

    Several common higher level program languages are described. FORTRAN, ALGOL, COBOL, PL/1, and LISP 1.5 are summarized and compared. FORTRAN is the most widely used scientific programming language. ALGOL is a more powerful language for scientific programming. COBOL is used for most commercial programming applications. LISP 1.5 is primarily a list-processing language. PL/1 attempts to combine the desirable features of FORTRAN, ALGOL, and COBOL into a single language.

  7. Code-generation-supported Architecture Description Language%支持代码生成的体系结构描述语言

    Institute of Scientific and Technical Information of China (English)

    吴桂阳; 万建成

    2004-01-01

    该文介绍了一种以支持软件工程中代码生成为目的的软件体系结构描述语言CGS-ADL(Code-Generation-Supported Architecture Description Language),由此语言生成的描述体系可为软件自动生成系统提供宏观指导.从实际应用角度出发,讨论了它的构成元素的定义并给出了此语言的可视化表示.随后,利用基于此语言的界面自动生成工具AUI(Auto-generation of User Interface)对一个电力系统的体系结构进行了描述,初步证明此语言体系能很好地支持工程代码生成.

  8. WSC/ADL:Web Services组合系统体系结构描述语言%WSC/ADL: An Architecture Description Language for Web Services Composition System

    Institute of Scientific and Technical Information of China (English)

    杨鑫; 陈俊亮

    2006-01-01

    Web services组合是Web services领域的研究热点,虽然已经提出了很多组合的方法,但从体系结构方面去研究Web services组合,则是一个新的研究角度.BPEL4WS是当前工业界主流的Web services组合描述语言.给出了基于BPEL4WS的Web services组合系统体系结构风格,并针对这种风格设计了体系结构描述语言WSC/ADL(Web services composition/architecture description language),WSC/ADL是基于体系结构的、自顶向下的Web services组合开发的研究基础,其组成包含描述Web services的服务构件、描述Web services之间交互的连接件以及建立服务构件和连接件实例联系的配置.给出了WSC/ADL的详细分析介绍和实例说明,并与相关工作进行了比较.

  9. 网格环境下基于任务通信的作业描述语言设计%Design of Job Description Language Based on Task Communication Under Grid

    Institute of Scientific and Technical Information of China (English)

    高志君

    2012-01-01

    Job management has been a hot issue in grid technology. The job description is the first task in the job management. This paper analyzes the job description, designs the job description language(CJDL) based on task communication. CJDL based on the XML language, with scalability, its advantages is that it can describe the communication between tasks and demands on resources. It can accomplish the automatic parallelization of job and resource matching further, and lay a foundation for job spawn and running and so on.%作业管理一直是网格技术中的热点问题,其中对于作业的描述是作业管理中的首要任务.本文针对作业描述展开分析,设计基于任务通信的作业描述语言CJDL(Communication Job Description Language).CJDL以XML语言为基础,具有可扩展性,其优势在于可以描述各任务之间的通信关系以及对资源的需求,从而可以进一步完成作业的自动并行化和资源的匹配,为作业的分派、运行等过程奠定基础.

  10. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  11. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  12. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  13. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  14. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  15. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  16. 线面目标自然语言空间关系集成表达与描述方法研究%Integrated Representation and Description of Natural-language Spatial Relations Between a Line and an Area

    Institute of Scientific and Technical Information of China (English)

    黄雪萍; 邓敏; 吴静; 马杭英

    2013-01-01

    It is difficult to express and distinguish complex location relationship information of two spatial objects through single topological relations, directional relations and distance relations. Using natural language as the description tool, the positional description of a line and an area is studied. We propose an integrated representation method of natural-language spatial relations between a line and an area according to the decomposition-combination measure. Firstly, n characteristic points and n - 1 characteristic lines would be obtained from refining and decomposing the linear object, whose spatial relations with the areal objects could be built by contraposing each of the characteristic points and lines according to the descriptive habits of natural-language. Secondly, we integrate the description of the topological relations, directional relations and distance relations according to the rules of the describing of natural-language spatial relations between lines and regions in the sequence of the directions of the lineal object. Finally, comprehensive experiments are performed to demonstrate the feasibility and efficiency of the transformation between graphic spatial relations and natural-language spatial relations.%提出了一种基于自然语言的线/面目标空间关系集成表达方法.首先,将线目标进行细化分解得到n个特征点和n—1条特征线,根据自然语言的描述习惯分别针对每个特征点和特征线建立线与面目标之间的空间关系,然后按照自然语言以线目标的走向为顺序对线面间空间关系进行描述的规则,对拓扑、方向、度量关系进行集成描述.实验验证了本文方法的可行性.

  17. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  18. Research on Access Control Policy Description Method Based on Ponder2 Language%Ponder2语言的访问控制策略描述方法研究

    Institute of Scientific and Technical Information of China (English)

    周捷; 禹明刚

    2012-01-01

    目前Ponder2策略语言主要应用在网络QoS服务质量管理方面,而对于安全方面的研究较少.本文分析Ponder2描述义务策略的方法,结合访问控制策略自身的特点,提出一种具体的基于Ponder2语言的描述访问控制策略的方法.%Currently, Ponder2 policy language mainly applies on QoS of network management, but the research of security is fewer. This paper analyzes the description method of obligation policy in Ponder2. Combining the character of access control policy, an access control policy description method based on Ponder2 language is proposed.

  19. Development Approach Based on Extensible User Interface Description Language%E-UIDL用户界面描述语言下的开发方法

    Institute of Scientific and Technical Information of China (English)

    杜一; 田丰; 戴国忠

    2015-01-01

    当前的用户界面开发过程需要产品经理、交互设计师、视觉设计师及用户界面开发工程师等多个角色的共同参与,各个角色的分工越来越细致,并且不同的角色在开发过程中使用的工具各不相同,这导致了界面开发过程中沟通成本的增加以及工作效率的降低.介绍了一种基于用户界面描述语言的开发方法,该方法能够降低用户界面开发过程中不同角色之间的沟通成本及转换成本,提高用户界面开发的效率.首先介绍E-UIDL(extensible user interface description language)——一种新的用户界面描述语言,并在此基础上设计了基于E-UIDL的开发方法及辅助开发工具,最后,通过实例介绍了利用基于E-UIDL的开发工具进行界面开发的过程,证明了基于用户界面描述语言的开发方法的可行性及优势.

  20. The Fundamental Scale of Descriptions

    CERN Document Server

    Febres, Gerardo

    2014-01-01

    The complexity of a system description is a function of the entropy of its symbolic description. Prior to computing the entropy of the system description, an observation scale has to be assumed. In natural language texts, typical scales are binary, characters, and words. However, considering languages as structures built around certain preconceived set of symbols, like words or characters, is only a presumption. This study depicts the notion of the Description Fundamental Scale as a set of symbols which serves to analyze the essence a language structure. The concept of Fundamental Scale is tested using English and MIDI music texts by means of an algorithm developed to search for a set of symbols, which minimizes the system observed entropy, and therefore best expresses the fundamental scale of the language employed. Test results show that it is possible to find the Fundamental Scale of some languages. The concept of Fundamental Scale, and the method for its determination, emerges as an interesting tool to fac...

  1. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  2. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  3. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  4. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  5. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  6. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  7. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  8. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  9. The NCL natural constraint language

    CERN Document Server

    Zhou, Jianyang

    2012-01-01

    This book presents the Natural Constraint Language (NCL) language, a description language in conventional mathematical logic for modeling and solving constraint satisfaction problems. It uses illustrations and tutorials to detail NCL and its applications.

  10. French Sign Language Gesture Description Formatlism for the Generation of Virtual Signer Motion Formalisme de description des gestes de la langue des signes française pour la génération du mouvement de signeurs virtuels

    Directory of Open Access Journals (Sweden)

    Alexis Héloir

    2009-04-01

    Full Text Available This paper presents a model for generating French sign language gestures, which is based on both a semi-formal modelling approach, and on a specification formalism yielding to the translation of an utterance into a continuous data flow for the control of a virtual character. This approach benefits from knowledge of structural linguistics proper to sign language, and results of motion capture analysis.

  11. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  12. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  13. 编辑人工语言中符号描述句的应用研究%Application of symbolic description in editorial artificial language

    Institute of Scientific and Technical Information of China (English)

    张祖尧; 徐石勇; 张会巍

    2013-01-01

    In scientific literature, not enough signs and symbols can be found to describe abundant objects and concepts, and in reality, proper application of signs and symbols is very complicated. Research on symbolic description focuses on how the meanings of signs and symbols and their forms of expression are related. It is found that signs and symbols can be categorized into referential symbols and functional symbols in terms of meanings, and word symbols, number symbols, punctuation symbols and special symbols in terms of forms. The paper explores some inner links between meanings and forms of symbols; for instance, referential symbols should have words as major symbols with corresponding typefaces or variations, while functional symbols use special symbols and punctuations more. Finally, the paper discusses the relationship between editorial artificial language and its standardized processing.%在科技文献中,需要描述的事物和概念远比可用的符号多,现实中符号的合理应用和表达是相当复杂的.研究符号描述句的重点是,探讨符号的应用(语义)和符号的表达形式之间的关系.结果表明:就符号的语义可有指称概念符号和表述功能的符号;就符号的形式可有文字符号、数字符号、标点符号和特种符号.文章探讨符号的语义与形式之间存在的某些规律,如指称符号必须以文字符号作主符号并配以相应的字体或变化;功能符号多使用特种符号和标点符号;等等.探讨了编辑人工语言与标准化规范化加工的关系.

  14. Le Bilinguisme chez l'Enfant et l'Apprentissage d'une Langue Seconde: Bibliographie Analytique (Child Bilingualism and Second Language Learning: A Descriptive Bibliography).

    Science.gov (United States)

    Afendras, Evangelos A.; Pianarosa, Albertina

    This annotated bibliography on child bilingualism and second language acquisition contains 1,661 references. Preceding the bibliographic entries are a list of the major conceptual fields covered by the bibliography, a subject index and an index of languages, countries and peoples dealt with in the bibliography. The indices refer to the entries in…

  15. The Effectiveness of Corpus-Based Approach to Language Description in Creating Corpus-Based Exercises to Teach Writing Personal Statements

    Science.gov (United States)

    Almutairi, Norah Dhawi

    2016-01-01

    Using corpora in language teaching has revolutionized language research with its "authentic" appeal. Corpus tools have enabled linguistic researchers and teachers to investigate actual usages and the characteristics of certain genres in order to improve syllabus design and infer more effective classroom exercises. From this perspective,…

  16. The Compiler Implementation of the Inheritance in Software Evolution Process Descriptive Language%软件演化过程描述语言中继承语法的编译实现

    Institute of Scientific and Technical Information of China (English)

    姜娜; 孔浩

    2013-01-01

    With its stronger description and easier realization in computer,a software evolution process description language is used to describe software evolution processes.As the emphasis of the software evolution process descriptive language,inheritance of the software process and activity is clearly defined by the EPDL grammar.This paper describes the compiler implementation of the software processes and activities.It also provides a theoretical basis for the compiler implementation.%软件演化过程描述语言对软件演化过程进行形式化的建模,更容易描述软件过程并在计算机中实现。软件演化过程描述语言的语法描述明确定义了有继承特性的软件过程和活动,继承是整个软件演化过程描述语言的重点之一。本文阐述了软件过程和活动在软件演化过程描述语言编译器中的实现方法,是整个编译器的核心,并为编译器的实现提供了理论基础。

  17. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  18. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  19. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  20. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  1. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  2. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  3. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  4. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  5. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  6. Influence Of Specialized Mathematical Language On Secondary ...

    African Journals Online (AJOL)

    Influence Of Specialized Mathematical Language On Secondary School Students ... the relationship between mathematical language and learners\\' achievement in ... Descriptive statistics and correlations were used to analyse data collected.

  7. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  8. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  9. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  10. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  11. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  12. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  13. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  14. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  15. Description logic rules

    CERN Document Server

    Krötzsch, M

    2010-01-01

    Ontological modelling today is applied in many areas of science and technology,including the Semantic Web. The W3C standard OWL defines one of the most important ontology languages based on the semantics of description logics. An alternative is to use rule languages in knowledge modelling, as proposed in the W3C's RIF standard. So far, it has often been unclear how to combine both technologies without sacrificing essential computational properties. This book explains this problem and presents new solutions that have recently been proposed. Extensive introductory chapters provide the necessary

  16. Language Pathology.

    Science.gov (United States)

    Fletcher, Paul

    1989-01-01

    Discusses the role of linguistics in the investigation of language disorders, focusing on the application of phonetics, descriptive grammatic frameworks, grammatical theory, and concepts from semantics and pragmatics to a variety of disorders and their remediation. Some trends and examples from the field of clinical linguistics are discussed. (GLR)

  17. Descriptive Analyses of English Language Learner Student Enrollment Data in Kentucky, Tennessee, Virginia, and West Virginia. REL Technical Brief. REL 2012-No. 024

    Science.gov (United States)

    Zehler, Annette M.; Yin, Chengbin; Donovan, Anne

    2012-01-01

    State administrators in the Regional Educational Laboratory Appalachia Region (Kentucky, Tennessee, Virginia, and West Virginia) are responding to increased enrollment of English language learner (ELL) students in grades K-12, including in school districts that previously did not enroll ELL students or enrolled only a small number of them. ELL…

  18. The Pearl Side of Online Portfolios: A Descriptive Study on the Rich Experience of Using PearlTrees by Master Students of Teaching English as a Foreign Language

    Science.gov (United States)

    Albaiz, Tahany

    2016-01-01

    Teaching English to ESL teachers is a challenging task for a number of reasons, the lack of connection between the target language and the native one being one of the most challenging factors (Ferlazzo & Sypnieski, 2013). Therefore, teachers are supposed to be innovators in creating the tools that could boost the learning process, as well as…

  19. Study on Function and Characteristic of the Software Evolution Process Description Language%浅析软件演化过程描述语言的作用及特点

    Institute of Scientific and Technical Information of China (English)

    姜娜; 孔浩

    2012-01-01

    在整个软件生命周期中,软件演化已成为其中一个日益重要的研究方向.软件演化过程用来建立软件演化的整体任务框架,可以提高软件演化的效率,但其描述力不足,难以在计算机中实现.软件演化过程描述语言作为面向对象的形式化建模语言,其较强的描述力和易于在计算机中实现的特性,使它可以在不同的抽象层次上描述演化过程,且有利于对软件演化过程的控制、分析、度量和改进.%The software evolution is a very important morph during software life cycle. Software evolution process is used to establish the whole task framework of software evolution to improve the efficiency of software evolution, but it has not powerful descriptive power and is hard to process in computer. A software evolution process description language is an object oriented formal language which is of stronger description and easier realization in computer, can model software evolution processes at different abstract levels, meanwhile, it has advantage of control, analysis, measurement and improvement on software evolution process.

  20. Descriptions of the Structure and Ordering of Language in the Mod 2 Kindergarten Stories. Technical Note No. 2-72-34.

    Science.gov (United States)

    Fiege-Kollman, Laila

    A detailed description of the syntax in the Southwest Regional Laboratory (SWRL) Mod 2 Kindergarten stories is presented to aid in the formulation of comprehension assessment and instruction. The lexicon and surface structures of the sentences appearing in the stories were classified and tabled in terms of types of elements and functions. The new…

  1. 基于XML的组安全策略描述%GSPML: A Group Security Policy Description Language Based on XML

    Institute of Scientific and Technical Information of China (English)

    尹青; 周伟; 王清贤

    2003-01-01

    Development of applications built on multi-party communication has made the need for the management ofpolicy. Security Policies are used to bridge the gap between static implementations and user requirements. A securitypolicy defines the security relevant behaviors, access control parameters, and security mechanisms used to implementthe group. A policy specification language defines both how a policy is represented and the rules with which the repre-sentation is interpreted. This paper describes the design space of security policy, and presents Group Security PolicyMarkup Language(GSPML)specification based on XML. GSPML, which is oriented to both people and computers,will be flexible and expressive and enough to support different secure requirements.

  2. Descriptive Research

    DEFF Research Database (Denmark)

    Wigram, Anthony Lewis

    2003-01-01

    Descriptive research is described by Lathom-Radocy and Radocy (1995) to include Survey research, ex post facto research, case studies and developmental studies. Descriptive research also includes a review of the literature in order to provide both quantitative and qualitative evidence of the effect...... starts will allow effect size calculations to be made in order to evaluate effect over time. Given the difficulties in undertaking controlled experimental studies in the creative arts therapies, descriptive research methods offer a way of quantifying effect through descriptive statistical analysis...

  3. Phonological development of first language isiXhosa-speaking children aged 3;0-6;0 years: a descriptive cross-sectional study.

    Science.gov (United States)

    Maphalala, Zinhle; Pascoe, Michelle; Smouse, Mantoa Rose

    2014-03-01

    Standardized assessments of children's isiXhosa phonology have not yet been developed and there is limited information about developmental norms in this language. This article reports on the phonological development of 24 typically developing first language isiXhosa-speaking children aged 3;0-6;0 years, in Cape Town, South Africa. The order and age of acquisition of isiXhosa phonemes, emergence and elimination of phonological processes and percentage consonants and vowels correct are described. A set of culturally and linguistically appropriate pictures was used to elicit single word responses that were recorded and transcribed. The study found that children had acquired most isiXhosa phonemes by 3;0 years although aspirated plosives, affricates, fricatives and clicks were still developing. In particular, the affricates and aspirated plosives were still developing in the 5-year-old children in this sample, suggesting that these may be the latest acquired segments. Children were able to produce basic word shapes by 3;0 years, but some of the words of 4-6 syllables were still being mastered by the 4- and 5-year-old children. Phonological processes that have been well documented for other languages were used by children in this sample (e.g. deaffrication, stopping and gliding of liquids). Findings presented for this pre-school-aged sample are related to theories of phonological acquisition to provide normative data on phonological development in isiXhosa-speaking children.

  4. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  5. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  6. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  7. An enhanced LAMBDA description language oriented to combined attack effectiveness evaluation%一种面向组合攻击效能评估的Enhanced LAMBDA描述语言

    Institute of Scientific and Technical Information of China (English)

    彭子枚; 赵文涛; 邹荣念

    2013-01-01

    Modeling attack actions with description language can depict the details of the attack more effectively.By evaluating the effectiveness of network attacks,the qualitative and quantitative evaluation of the effect of network attacks is concluded,and it can test the effectiveness of attack actions and help to establish effective security policy of network.Based on the LAMBDA description language,this paper expands its expressiveness on time constraints and effectiveness constraints,proposes an enhanced attack description language,the enhanced LAMBDA,and then gives an application example of the enhanced LAMBDA.In the end,this paper uses DARPA data set,the LLDOS1.0,to construct a test scenario of combined attack of network and evaluates its effectiveness based on the enhanced LAMBDA.The experimental results indicate that Enhanced LAMBDA can effectively support the evaluation of effectiveness of combined attacks.%利用描述语言进行攻击建模能够更有效地刻画攻击细节.通过对网络攻击效能进行评估,可以对网络攻击的效果给出定性和定量的评价,检验攻击行为的有效性,有助于制定有效的网络安全策略.基于LAMBDA语言,扩充了时间约束和效能约束方面的描述能力,提出了一种增强的攻击描述语言Enhanced LAMBDA,并给出了Enhanced LAMBDA的应用实例.最后,利用DARPA数据集LLDOS1.0 构造了网络组合攻击的测试场景,基于Enhanced LAMBDA对其进行效能评估.实验结果表明,Enhanced LAMBDA能有效支持网络组合攻击的效能评估.

  8. Scaffold: Quantum Programming Language

    Science.gov (United States)

    2012-07-24

    included popular classical high-level imperative programming languages (C/C++, Java) [16, 25, 11], hardware description languages ( Verilog ) [13], C-to...hardware languages (System-C) [14] and existing quantum programming languages (QCL) [23]. • Variant of C and Verilog : Scaffold syntax was chosen to be...very similar to C (and to some extent Verilog HDL.) This reflects our belief that expressing computations in terms of familiar iterative and imperative

  9. Languages and Employability

    OpenAIRE

    DE SOUSA LOBO BORGES DE ARAUJO LUISA; DINIS MOTA DA COSTA PATRICIA; FLISI SARA; SOTO CALVO ELENA

    2015-01-01

    This report reviews evidence regarding the foreign language competences of European citizens and presents new findings about the relationship between foreign language skills and the likelihood of being in employment. In view of providing research evidence that can inform European Union (EU) policy initiatives, it reviews studies that frame knowledge of languages as a form of human capital, presents descriptive statistics about language knowledge and investigates whether this knowledge is rela...

  10. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  11. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  12. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  13. New Metric Based Algorithm for Test Vector Generation in VLSI Testing

    Directory of Open Access Journals (Sweden)

    M. V. Atre

    1995-07-01

    Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.

  14. Spike-based VLSI modeling of the ILD system in the echolocating bat.

    Science.gov (United States)

    Horiuchi, T; Hynna, K

    2001-01-01

    The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.

  15. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  16. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  17. Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.

    Science.gov (United States)

    1984-10-01

    analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI

  18. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  19. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  20. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  1. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  2. Research of the Language of Special Information's Description in Grid GIS%网格GIS中空间信息描述语言的研究

    Institute of Scientific and Technical Information of China (English)

    刘建英; 徐爱萍

    2006-01-01

    在网格GIS系统中,分布在不同位置的数据、信息、互操作、协同等需要具有一种标准的语言,使相互之间能够进行对话和交流,GridGML(Grid Geographic Markup Language)将是解决这些问题的关键技术.在XML技术、网格体系结构技术及OGC的GML3标准的基础上,对GridGML进行了研究,提出了其设计思想.

  3. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  4. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  5. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  6. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    Science.gov (United States)

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.

  7. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  8. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  9. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  10. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  11. The digi-neocognitron: a digital neocognitron neural network model for VLSI.

    Science.gov (United States)

    White, B A; Elmasry, M I

    1992-01-01

    One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

  12. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  13. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  14. Estudio descriptivo del desarrollo de la competencia narrativa en lengua de señas chilena (Descriptive study on narrative competence development in Chilean Sign Language

    Directory of Open Access Journals (Sweden)

    María Rosa Lissi

    2012-12-01

    Full Text Available El objetivo de este estudio consiste en determinar una evolución en el desarrollo de la competencia narrativa de un grupo de niños sordos, que usan la lengua de señas chilena como su lengua natural y que se encuentran en la etapa escolar (primero a cuarto año básico. Se trata de un estudio de caso, en el que se obtiene una producción narrativa por parte de cada niño en tres momentos distintos con una diferencia de un año entre cada una. Estas narraciones son analizadas, enfocándose en dos aspectos: la organización formal del texto narrativo, es decir su superestructura, y la organización del contenido en relación al uso de recursos lingüísticos para establecer cohesión textual. El estudio se enfoca en las formas empleadas al establecer referencia y correferencia, cuando se trata de introducir, mantener o reintroducir el foco sobre los personajes de la historia que narran. Aun cuando los niños ocupan todos los elementos de cohesión desde las primeras narraciones, hay un cambio que está determinado por las funciones para las cuales son usados. Se demuestracómo los niños desarrollan gradualmente la capacidad para construir narraciones, teniendo en cuenta la información que requiere su audiencia. El conocimiento sobre este aspecto del proceso de adquisición de la lengua de señas en niños sordos cobra importancia en el marco de la educación bilingüe, donde se asume que el desarrollo de habilidades de la lectura y escritura tienen una base importante en la consolidación de habilidades relacionadas con el desarrollo de la competencia en la lengua natural de las personas sordas de nuestro país, esto es, la lengua de señas chilena. (The purpose of this study was to evaluate the narrative competence development of a group of deaf children who use sign language as their natural language. Children in this study were in the elementary grades, 1st to 4th. This three-year case study obtained narratives from each child three times

  15. Language-in-Education Policy and Planning.

    Science.gov (United States)

    Paulston, Christina Bratt; McLaughlin, Susanne

    1994-01-01

    A descriptive review of research on language-in-education policy and planning is offered. It covers national languages (North America, Southern Africa, Central Asia); minority languages (New Zealand, North America); European minority languages and language policies in the European Community; testing and evaluation; teacher education; and literacy.…

  16. Descriptive Research

    DEFF Research Database (Denmark)

    Wigram, Anthony Lewis

    2003-01-01

    Descriptive research is described by Lathom-Radocy and Radocy (1995) to include Survey research, ex post facto research, case studies and developmental studies. Descriptive research also includes a review of the literature in order to provide both quantitative and qualitative evidence of the effect...... of music therapy with a specific population (Gold, Voracek & Wigram, Wigram, 2002). The collection of such evidence, through surveys of the literature and documentation of music therapy studies that show effect with a specified population are becoming increasingly important in order to underpin music...

  17. Linguistic Corpora and Language Teaching.

    Science.gov (United States)

    Murison-Bowie, Simon

    1996-01-01

    Examines issues raised by corpus linguistics concerning the description of language. The article argues that it is necessary to start from correct descriptions of linguistic units and the contexts in which they occur. Corpus linguistics has joined with language teaching by sharing a recognition of the importance of a larger, schematic view of…

  18. Generative Studies in Romance Languages.

    Science.gov (United States)

    Casagrande, Jean, Ed.; Saciuk, Bohdan, Ed.

    This book represents, in part, the written record of the "Linguistic Symposium of Romance Languages: Application of Generative Grammar to Their Description and Teaching," held at the University of Florida, Gainesville, in February 1971. The aim of the Symposium was to bring forth contributions in the description of Romance languages, to draw…

  19. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

  20. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  1. VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.

    Science.gov (United States)

    Hoang, Linh; Yang, Zhi; Liu, Wentai

    2009-01-01

    An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.

  2. A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.

    Science.gov (United States)

    Mill, R; Sheik, S; Indiveri, G; Denham, S L

    2011-10-01

    Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.

  3. VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.

    Science.gov (United States)

    Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V

    2007-03-01

    A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

  4. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  5. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  6. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  7. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  8. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  9. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  10. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  11. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  12. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  13. Real-time motion detection using an analog VLSI zero-crossing chip

    Science.gov (United States)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  14. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  15. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    Science.gov (United States)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  16. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  17. Analyzing VLSI component test results of a GenRad GR125 tester

    Science.gov (United States)

    Zulaica, D.; Lee, C.-H.

    1995-06-01

    The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.

  18. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  19. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    Science.gov (United States)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  20. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  1. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  2. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  3. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  4. VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

    Science.gov (United States)

    Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

    2014-01-01

    Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

  5. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  6. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  7. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  8. Sign language typology: The contribution of rural sign languages

    NARCIS (Netherlands)

    C. de Vos; R. Pfau

    2014-01-01

    Since the 1990s, the field of sign language typology has shown that sign languages exhibit typological variation at all relevant levels of linguistic description. These initial typological comparisons were heavily skewed toward the urban sign languages of developed countries, mostly in the Western w

  9. Petri Nets and Semantics of System Descriptions

    DEFF Research Database (Denmark)

    Jensen, Kurt; Kyng, Morten

    1982-01-01

    This paper discusses the use of Petri nets as a semantic tool in the design of languages and in the construction and analysis of system descriptions. The topics treated are: Languages based on nets. The problem of time in nets. Nets and related models. Nets and formal semantics. Parallel program...

  10. A W-Grammar Description for ADA.

    Science.gov (United States)

    1986-12-01

    Language Reference Manual. In MT opinion, the W- gramars fall short of this goal since they are less readable than BNF for determining Ada’s syntax, and...37 Summary . . . . . . . . . . . . . . .... . 39 V. Conclusion .. . . . . . . . . . .. . . .* . . . . 40 Ada Constructs Not Covered in W- gramar B...library unit. The problem with the Language Reference Manual description is not that BNF is too antiquated for language definition, but that English

  11. 基于B方法的体系结构描述语言的精化研究%Research on Refinement of Architecture Description Language based on B Method

    Institute of Scientific and Technical Information of China (English)

    丁湘陵

    2012-01-01

    This paper presents a formal software refinement method.The method combines the extended event mechanism of B and the Architecture description language,which provides a formal path from design to implementation with transformation of notation or the definition of a new calculus.%通过分析B方法和软件体系结构描述语言各自的特点,提出了一种使两者无缝集成的精化开发方法:首先定义精化约束和规则保证在精化过程中模型系统的一致性;然后对ABC/ADL复合构件和复杂连接子使用定义的精化约束和规则逐步精化,直到可执行程序,最后给出实例加以说明该方法的可行性.

  12. A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-12-07

    A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

  13. High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug

    2006-07-24

    Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

  14. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  15. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    Science.gov (United States)

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-04

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.

  16. A Methodology for Mapping and Partitioning Arbitrary N—Dimensional Nested Loops into 2—Dimensional VLSI Arrays

    Institute of Scientific and Technical Information of China (English)

    刘弘; 王文红; 等

    1993-01-01

    A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.

  17. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  18. Language, Language Teaching and Language Testing

    Institute of Scientific and Technical Information of China (English)

    吴文华

    2002-01-01

    Departing from a brief presentation of the various views of language, this article elaborates the influence of views of languageon language teaching and language testing. This will help us have background knowledge on language teaching and language testing.

  19. System Description:

    DEFF Research Database (Denmark)

    Schürmann, Carsten; Poswolsky, Adam

    2009-01-01

    Delphin is a functional programming language [Adam Poswolsky and Carsten Schürmann. Practical programming with higher-order encodings and dependent types. In European Symposium on Programming (ESOP), 2008] utilizing dependent higher-order datatypes. Delphin's two-level type-system cleanly separates...... data from computation, allowing for decidable type checking. The data level is LF [Robert Harper, Furio Honsell, and Gordon Plotkin. A framework for defining logics. Journal of the Association for Computing Machinery, 40(1):143-184, January 1993], which allows for the specification of deductive systems...

  20. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  1. VLSI Research

    Science.gov (United States)

    1984-04-01

    massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly

  2. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  3. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  4. Introducing Sign Language Systems to Parents of Young Deaf Children.

    Science.gov (United States)

    Moser, Barbara Walsh

    1987-01-01

    The three major sign language systems (American Sign Language, Pidgin Sign English, and Manual English) are compared in table form. A brief description of each language highlights salient points that parents of deaf children need to understand. (DB)

  5. The Language Question in Namibian Schools.

    Science.gov (United States)

    Brock-Utne, Birgit

    1997-01-01

    Builds on a consultancy report dealing primarily with the status of the African languages in Namibian schools after Independence in 1990. Contains a description of the Namibian languages, the language policy, and the status of the languages in Namibian schools. (42 citations) (VWC)

  6. Language, Consciousness, and the Problem of Description

    African Journals Online (AJOL)

    User

    illuminate, they are more like a soothing musical accompaniment ... with patients in psychotherapy who are able to recall details of their .... is usually the scholar with the best memory for the shadows of .... reference to the surface effect these cause: an algorism .... themselves into pure melody if they did not maintain a primal ...

  7. Understanding Natural Language Descriptions of Physical Phenomena

    Science.gov (United States)

    2004-05-07

    Szpakowicz, 1995) and the HAIKU semantic interpretation module (Barker, 1998). DIPETT is a syntactic parser that tries to construct complete parse trees for...part-of-speech tagger on the corpus material. This approach results in a smaller lexicon, tailored towards a particular corpus. The HAIKU semantic...Barker, 1996), and a module for analyzing relationships between connected clauses (Barker, 1994; Barker & Szpakowicz, 1995). HAIKU uses only a

  8. SCO-GADL:A Grid Workflow Description Language for Scientific Computing%SCO-GADL:一种用于科学计算的网格工作流描述语言

    Institute of Scientific and Technical Information of China (English)

    黄震春

    2011-01-01

    The difficulty of grid-enabled application development is one of the obstacles to employ grid as infrastructure of scientific computing. Although there are many projects, especially grid workflow projects, trying to make grid-enabled application development easier and quicker, the process-based application description model adopted by most of the gridenabled applications still bothers scientists who are usually beginner in programming. In this paper,a data dependency based application description model was proposed,which describes a grid-enabled application via dependency among data items in the application,and much close to the thinking pattern of scientists. Based on this model, a scientific computing oriented grid application description language (SCO-GADL) was proposed, and an engine for supporting its execution was designed and implemented. The extensible plug-in architecture adopted by SCO-GADL and its engine makes them support different grid and non-grid platforms easily. At last, a test shows that grid-enabled scientific applications can be developed easily in SCO-GADL,and executed correctly on the application engine.%应用开发的难度一直是制约网格技术成为科学计算基础设施的主要因素之一.虽然网格工作流等诸多技术的使用能够在一定程度上降低网格应用开发的难度,但是大多数网格应用所采用的基于流程的应用描述模型仍然是网格应用开发的一个主要障碍--尤其是对那些通常情况下不擅长编程的科学家们.为了降低网格应用开发的难度,提出了一种基于数据依赖关系的网格应用描述模型,力图使网格应用的描述更加符合科学工作者的思维习惯.在此基础上,设计和实现了一种被称作SCO-GADL的工作流描述语言及其执行引擎.该引擎采用核心-插件体系结构,能够使用在多种网格平台之中,为科学工作者提供一种方便、易用和快捷的网格应用开发工具,以便使网格中聚

  9. Language Contact.

    Science.gov (United States)

    Nelde, Peter Hans

    1995-01-01

    Examines the phenomenon of language contact and recent trends in linguistic contact research, which focuses on language use, language users, and language spheres. Also discusses the role of linguistic and cultural conflicts in language contact situations. (13 references) (MDM)

  10. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  11. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  12. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  13. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  14. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  15. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Science.gov (United States)

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  16. A compact 3D VLSI classifier using bagging threshold network ensembles.

    Science.gov (United States)

    Bermak, A; Martinez, D

    2003-01-01

    A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

  17. A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.

    Science.gov (United States)

    Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

    2011-04-01

    Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.

  18. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  19. Deep sub-micron stud-via technology for superconductor VLSI circuits

    Science.gov (United States)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  20. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  1. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  2. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  3. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  4. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  5. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  6. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  7. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  8. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  9. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Directory of Open Access Journals (Sweden)

    McEwan Alistair

    2003-01-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  10. Advances in VLSI testing at MultiGb per second rates

    Directory of Open Access Journals (Sweden)

    Topisirović Dragan

    2005-01-01

    Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

  11. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  12. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  13. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  14. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  15. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  16. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  17. Context-descriptive Prototypes and Their Application to Medicine Administration

    DEFF Research Database (Denmark)

    Bossen, Claus; Jørgensen, Jens Bæk

    2004-01-01

    A context-descriptive prototype is an interactive graphical animation, driven by a formal, executable engine, implemented in some programming or modelling language. The two main properties of a context-descriptive prototype are: (1) it is an integrated description that describes system, work...

  18. Which Methodology Works Better? English Language Teachers' Awareness of the Innovative Language Learning Methodologies

    Science.gov (United States)

    Kurt, Mustafa

    2015-01-01

    The present study investigated whether English language teachers were aware of the innovative language learning methodologies in language learning, how they made use of these methodologies and the learners' reactions to them. The descriptive survey method was employed to disclose the frequencies and percentages of 175 English language teachers'…

  19. Which Methodology Works Better? English Language Teachers' Awareness of the Innovative Language Learning Methodologies

    Science.gov (United States)

    Kurt, Mustafa

    2015-01-01

    The present study investigated whether English language teachers were aware of the innovative language learning methodologies in language learning, how they made use of these methodologies and the learners' reactions to them. The descriptive survey method was employed to disclose the frequencies and percentages of 175 English language teachers'…

  20. Abstraction Mechanisms in the BETA Programming Language

    DEFF Research Database (Denmark)

    Kristensen, Bent Bruun; Madsen, Ole Lehrmann; Møller-Pedersen, Birger

    1983-01-01

    . It is then necessary that the abstraction mechanisms are powerful in order to define more specialized constructs. BETA is an object oriented language like SIMULA 67 ([SIMULA]) and SMALLTALK ([SMALLTALK]). By this is meant that a construct like the SIMULA class/subclass mechanism is fundamental in BETA. In contrast...... to SMALLTALK, BETA is a language in the ALGOL 60 ([ALGOL]) family. SIMULA 67 is a system description and a programming language. The DELTA language ([DELTA]) is a system description language only, allowing description of full concurrency, continuous change and component interaction, developed from a SIMULA......The BETA programming language is developed as part of the BETA project. The purpose of this project is to develop concepts, constructs and tools in the field of programming and programming languages. BETA has been developed from 1975 on and the various stages of the language are documented in [BETA...

  1. Classification of correlated patterns with a configurable analog VLSI neural network of spiking neurons and self-regulating plastic synapses.

    Science.gov (United States)

    Giulioni, Massimilian; Pannunzi, Mario; Badoni, Davide; Dante, Vittorio; Del Giudice, Paolo

    2009-11-01

    We describe the implementation and illustrate the learning performance of an analog VLSI network of 32 integrate-and-fire neurons with spike-frequency adaptation and 2016 Hebbian bistable spike-driven stochastic synapses, endowed with a self-regulating plasticity mechanism, which avoids unnecessary synaptic changes. The synaptic matrix can be flexibly configured and provides both recurrent and external connectivity with address-event representation compliant devices. We demonstrate a marked improvement in the efficiency of the network in classifying correlated patterns, owing to the self-regulating mechanism.

  2. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  3. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  4. 基于GPU的VLSI的DRC加速系统%DRC Accelerated System of VLSI Based on GPU

    Institute of Scientific and Technical Information of China (English)

    池凤彬; 潘日华; 陈扉; 赵冬晖

    2007-01-01

    在超大规模集成电路(VLSI)设计流程中,设计规则检查(DRC)是关键一环.多年来,设计人员为DRC设计了许多硬件加速的方法,但是都局限于成本等诸多原因而不能得到推广.因此提出了基于GPU平台的DRC方法,大幅提高了DRC效率.

  5. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  6. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  7. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  8. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  9. Language Revitalization.

    Science.gov (United States)

    Hinton, Leanne

    2003-01-01

    Surveys developments in language revitalization and language death. Focusing on indigenous languages, discusses the role and nature of appropriate linguistic documentation, possibilities for bilingual education, and methods of promoting oral fluency and intergenerational transmission in affected languages. (Author/VWL)

  10. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  11. A Brief Introduction to Communicative Language Teaching

    Institute of Scientific and Technical Information of China (English)

    JIN Fan

    2016-01-01

    Communicative language teaching (CLT) advances and advocates language is acquired through communications,i.e., using a language to learn it.. Ever since the introduction of CLT in the late 1970s, disparate definitions and interpretations of the communicative approach to language instruction continually come into being. In today's process of language teaching, incorpora-tion of CLT has become mandatory in teaching almost any language. While the majority of descriptions of CLT accentuate the communication of messages and meaning, there is divergence as to whether CLT should be concerned about the analysis and practice of language structures.

  12. Space between Languages

    Science.gov (United States)

    Feist, Michele I.

    2008-01-01

    What aspects of spatial relations influence speakers' choice of locative? This article presents a study of static spatial descriptions from 24 languages. The study reveals two kinds of spatial terms evident cross-linguistically: specific spatial terms and general spatial terms (GSTs). Whereas specific spatial terms--including English…

  13. Restandardisation defined as democratising language planning1

    African Journals Online (AJOL)

    aims to define restandardisation as democratising language planning, i.e. a .... disintegration of the Soviet Union of Yugoslavia, the opening of borders in Europe, and the ..... descriptive framework for standardisation as a language planning process. .... belonging to the same language group in order to form one common ...

  14. Discussion on English Vocabulary and Description

    Institute of Scientific and Technical Information of China (English)

    Shen Lan; Zhang Shiying

    2013-01-01

    Compared with the study of Grammar, syntax, the description on vocabulary is comparatively slower than them. The related theories of vocabulary description have fast developed since the 1980s and 1990s have experienced a growing interest in vocabulary learning and teaching----The vocabulary size, text coverage, word list, meaning of vocabulary in context, and collocation have been discovered and described, which helped new insights in arrange of different research fields have all added to our understanding of vocabulary development. Vocabulary acquisition research, based on vocabulary description, has established itself as a central research focus for language acquisition researchers and contributed to the focus of practical teaching and learning in English.

  15. LANGUAGE TRAINING

    CERN Multimedia

    2004-01-01

    If you wish to participate in one of the following courses, please discuss with your supervisor and apply electronically directly from the course description pages that can be found on the Web at: http://www.cern.ch/Training/ or fill in an "application for training" form available from your Divisional Secretariat or from your DTO (Divisional Training Officer). Applications will be accepted in the order of their receipt. LANGUAGE TRAINING Françoise Benz tel. 73127 language.training@cern.ch FRENCH TRAINING General and Professional French Courses The next session will take place from 26 January to 02 April 2004. These courses are open to all persons working on the Cern site, and to their spouses. For registration and further information on the courses, please consult our Web pages: http://cern.ch/Training or contact Mrs. Benz: Tel. 73127. Writing Professional Documents in French The next session will take place from 26 January to 02 April 2004. This course is designed for people wi...

  16. LANGUAGE TRAINING

    CERN Multimedia

    2004-01-01

    If you wish to participate in one of the following courses, please discuss with your supervisor and apply electronically directly from the course description pages that can be found on the Web at: http://www.cern.ch/Training/ or fill in an "application for training" form available from your Divisional Secretariat or from your DTO (Divisional Training Officer). Applications will be accepted in the order of their receipt. LANGUAGE TRAINING Françoise Benz tel. 73127 language.training@cern.ch FRENCH TRAINING General and Professional French Courses The next session will take place from 26 January to 02 April 2004. These courses are open to all persons working on the Cern site, and to their spouses. For registration and further information on the courses, please consult our Web pages: http://cern.ch/Training or contact Mrs. Benz : Tel. 73127. Writing Professional Documents in French The next session will take place from 26 January to 02 April 2004. This course is designed for peop...

  17. Language Contact and Language Conflict in Autochthonous Language Minority Settings in the EU: A Preliminary Round-Up of Guiding Principles and Research Desiderata

    Science.gov (United States)

    Darquennes, Jeroen

    2010-01-01

    This contribution deals with language contact and language conflict in autochthonous language minority settings in the European Union. It rounds up a number of concepts that guide macro-socio-linguistic and macrocontact-linguistic research on language minorities. The description of these concepts results in a list of research desiderata.

  18. Audio Description as a Pedagogical Tool

    Directory of Open Access Journals (Sweden)

    Georgina Kleege

    2015-05-01

    Full Text Available Audio description is the process of translating visual information into words for people who are blind or have low vision. Typically such description has focused on films, museum exhibitions, images and video on the internet, and live theater. Because it allows people with visual impairments to experience a variety of cultural and educational texts that would otherwise be inaccessible, audio description is a mandated aspect of disability inclusion, although it remains markedly underdeveloped and underutilized in our classrooms and in society in general. Along with increasing awareness of disability, audio description pushes students to practice close reading of visual material, deepen their analysis, and engage in critical discussions around the methodology, standards and values, language, and role of interpretation in a variety of academic disciplines. We outline a few pedagogical interventions that can be customized to different contexts to develop students' writing and critical thinking skills through guided description of visual material.

  19. Construction by description in discourse representation

    NARCIS (Netherlands)

    van Leusen, N.; Muskens, R.A.; Peregrin, J.

    2003-01-01

    This paper uses classical logic for a simultaneous description of the syntax and semantics of a fragment of English and it is argued that such an approach to natural language allows procedural aspects of linguistic theory to get a purely declarative formulation. In particular, it will be shown how c

  20. A DESCRIPTIVE INDONESIAN GRAMMAR--PRELIMINARY EDITION.

    Science.gov (United States)

    DYEN, ISIDORE

    THIS PRELIMINARY EDITION COMPRISES A DESCRIPTIVE GRAMMAR OF INDONESIAN (BAHASA INDONESIA), THE OFFICIAL LANGUAGE OF THE REPUBLIC OF INDONESIA. THE THREE SECTIONS--PHONOLOGY, SYNTAX, AND MORPHOLOGY--PRESENT A COMPREHENSIVE LINGUISTIC ANALYSIS OF INDONESIAN, WITH OCCASIONAL CONTRASTIVE REFERENCE TO MALAY, JAVANESE, SUNDANESE, AND SUMATRAN. THIS…