WorldWideScience

Sample records for vlsi complexity results

  1. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  2. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  3. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  4. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  5. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  6. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    Science.gov (United States)

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.

  7. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  8. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  9. Analyzing VLSI component test results of a GenRad GR125 tester

    Science.gov (United States)

    Zulaica, D.; Lee, C.-H.

    1995-06-01

    The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.

  10. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  11. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  12. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  13. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  14. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  15. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  16. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  17. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  18. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  19. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  20. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  1. Test beam results for silicon microstrip detectors with VLSI read-out

    Energy Technology Data Exchange (ETDEWEB)

    Adolphsen, C.; Litke, A.; Schwarz, A.; Turala, M.; Lueth, V.; Breakstone, A.; Parker, S.

    1986-04-01

    A telescope consisting of three silicon microstrip detectors has been tested in a high energy positron beam at SLAC. Each detector has trips with 25 micron pitch and is read out by two 128-channel NMOS integrated circuits (''Microplex''). Results on the signal-to-noise ratio, spatial resolution, and two-track separation are given.

  2. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  3. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  4. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  5. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  6. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  7. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  8. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  9. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  10. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  11. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  12. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  13. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  14. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  15. Complexity Results in Epistemic Planning

    DEFF Research Database (Denmark)

    Bolander, Thomas; Jensen, Martin Holm; Schwarzentruber, Francois

    2015-01-01

    Epistemic planning is a very expressive framework that extends automated planning by the incorporation of dynamic epistemic logic (DEL). We provide complexity results on the plan existence problem for multi-agent planning tasks, focusing on purely epistemic actions with propositional preconditions......-hardness of the plan verification problem, which strengthens previous results on the complexity of DEL model checking....

  16. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  17. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  18. Complexity Results in Epistemic Planning

    DEFF Research Database (Denmark)

    Bolander, Thomas; Jensen, Martin Holm; Schwarzentruber, Francois

    2015-01-01

    Epistemic planning is a very expressive framework that extends automated planning by the incorporation of dynamic epistemic logic (DEL). We provide complexity results on the plan existence problem for multi-agent planning tasks, focusing on purely epistemic actions with propositional preconditions....... We show that moving from epistemic preconditions to propositional preconditions makes it decidable, more precisely in EXPSPACE. The plan existence problem is PSPACE-complete when the underlying graphs are trees and NP-complete when they are chains (including singletons). We also show PSPACE......-hardness of the plan verification problem, which strengthens previous results on the complexity of DEL model checking....

  19. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  20. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  1. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  2. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  3. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  4. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  5. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  6. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  7. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  8. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  9. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  10. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  11. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  12. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  13. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  14. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  15. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  16. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  17. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  18. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  19. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  20. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  1. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  2. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  3. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  4. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  5. Assessing Complexity Results in Feature Theories

    CERN Document Server

    Trautwein, M

    1995-01-01

    In this paper, we assess the complexity results of formalisms that describe the feature theories used in computational linguistics. We show that from these complexity results no immediate conclusions can be drawn about the complexity of the recognition problem of unification grammars using these feature theories. On the one hand, the complexity of feature theories does not provide an upper bound for the complexity of such unification grammars. On the other hand, the complexity of feature theories need not provide a lower bound. Therefore, we argue for formalisms that describe actual unification grammars instead of feature theories. Thus the complexity results of these formalisms judge upon the hardness of unification grammars in computational linguistics.

  6. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  7. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  8. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  9. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  10. Statistics on VLSI Designs.

    Science.gov (United States)

    1980-04-17

    been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE

  11. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  12. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  13. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  14. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  15. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  16. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  17. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  18. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  19. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  20. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  1. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  2. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  3. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  4. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  5. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

  6. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  7. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  8. Recent results on complex Cartan spaces

    Science.gov (United States)

    Aldea, Nicoleta; Munteanu, Gheorghe

    2016-08-01

    In this paper, we first provide an updated survey of the geometry of complex Cartan spaces. New characterizations for some particular classes of complex Cartan spaces are pointed out, e.g. Landsberg-Cartan, strongly Berwald-Cartan and others. We introduce the Cartan-Randers spaces which offer examples of Berwald-Cartan and strongly Berwald-Cartan spaces. Then, we investigate the complex geodesic curves of a complex Cartan space, using the image by Legendre transformation (L-duality) of complex geodesic curves of a complex Finsler space. Assuming the weakly Kähler condition for a complex Cartan space, we establish that its complex geodesic curves derive from Hamilton-Jacobi equations. Also, by L-duality, we introduce the corespondent notion of the projectively related complex Finsler metrics, on the complex Cartan spaces. Various descriptions of the projectively related complex Cartan metrics are given. As applications, the projectiveness of a complex Cartan-Randers metric and the locally projectively flat complex Cartan metrics are analyzed.

  9. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  10. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  11. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  12. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  13. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  14. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  15. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  16. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  17. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  18. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  19. Some results on uniform arithmetic circuit complexity

    DEFF Research Database (Denmark)

    Frandsen, Gudmund Skovbjerg; Valence, Mark; Barrington, David A. Mix

    1994-01-01

    We introduce a natural set of arithmetic expressions and define the complexity class AE to consist of all those arithmetic functions (over the fieldsF 2n) that are described by these expressions. We show that AE coincides with the class of functions that are computable with constant depth...... that if some such representation is X-uniform (where X is P or DLOGTIME), then the arithmetic complexity of a function (measured with X-uniform unbounded fan-in arithmetic circuits) is identical to the Boolean complexity of this function (measured with X-uniform threshold circuits). We show the existence...... and polynomial-size unbounded fan-in arithmetic circuits satisfying a natural uniformity constraint (DLOGTIME-uniformity). A 1-input and 1-output arithmetic function over the fieldsF2n may be identified with ann-input andn-output Boolean function when field elements are represented as bit strings. We prove...

  20. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  1. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  2. Complexity Results on Graphs with Few Cliques

    Directory of Open Access Journals (Sweden)

    Bill Rosgen

    2007-01-01

    Full Text Available A graph class has few cliques if there is a polynomial bound on the number of maximal cliques contained in any member of the class. This restriction is equivalent to the requirement that any graph in the class has a polynomial sized intersection representation that satisfies the Helly property. On any such class of graphs, some problems that are NP-complete on general graphs, such as the maximum clique problem and the maximum weighted clique problem, admit polynomial time algorithms. Other problems, such as the vertex clique cover and edge clique cover problems remain NP-complete on these classes. Several classes of graphs which have few cliques are discussed, and the complexity of some partitioning and covering problems are determined for the class of all graphs which have fewer cliques than a given polynomial bound.

  3. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  4. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  5. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  6. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  7. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  8. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  9. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  10. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  11. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  12. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  13. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  14. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  15. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  16. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  17. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  18. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  19. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  20. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  1. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  2. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  3. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  4. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  5. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  6. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  7. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  8. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  9. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  10. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  11. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  12. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  13. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  14. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  15. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  16. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  17. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  18. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  19. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  20. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  1. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  2. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  3. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  4. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  5. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  6. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  7. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  8. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  9. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  10. A Methodology for Mapping and Partitioning Arbitrary N—Dimensional Nested Loops into 2—Dimensional VLSI Arrays

    Institute of Scientific and Technical Information of China (English)

    刘弘; 王文红; 等

    1993-01-01

    A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.

  11. Three complexity results on coloring $P_k$-free graphs

    NARCIS (Netherlands)

    Broersma, Haitze J.; Fomin, Vedor V.; Golovach, Petr A.; Paulusma, Daniël

    2013-01-01

    We prove three complexity results on vertex coloring problems restricted to $P_k$-free graphs, i.e., graphs that do not contain a path on k vertices as an induced subgraph. First of all, we show that the pre-coloring extension version of 5-coloring remains NP-complete when restricted to P6-free

  12. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  13. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  14. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  15. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  16. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  17. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  18. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  19. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  20. Familial complex chromosomal rearrangement resulting in a recombinant chromosome.

    Science.gov (United States)

    Berend, Sue Ann; Bodamer, Olaf A F; Shapira, Stuart K; Shaffer, Lisa G; Bacino, Carlos A

    2002-05-15

    Familial complex chromosomal rearrangements (CCRs) are rare and tend to involve fewer breakpoints and fewer chromosomes than CCRs that are de novo in origin. We report on a CCR identified in a child with congenital heart disease and dysmorphic features. Initially, the child's karyotype was thought to involve a straightforward three-way translocation between chromosomes 3, 8, and 16. However, after analyzing the mother's chromosomes, the mother was found to have a more complex rearrangement that resulted in a recombinant chromosome in the child. The mother's karyotype included an inverted chromosome 2 and multiple translocations involving chromosomes 3, 5, 8, and 16. No evidence of deletion or duplication that could account for the clinical findings in the child was identified.

  1. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  2. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  3. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  4. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  5. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  6. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  7. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  8. A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-12-07

    A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

  9. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    Science.gov (United States)

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-04

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.

  10. The effect of query complexity on Web searching results

    Directory of Open Access Journals (Sweden)

    B.J. Jansen

    2000-01-01

    Full Text Available This paper presents findings from a study of the effects of query structure on retrieval by Web search services. Fifteen queries were selected from the transaction log of a major Web search service in simple query form with no advanced operators (e.g., Boolean operators, phrase operators, etc. and submitted to 5 major search engines - Alta Vista, Excite, FAST Search, Infoseek, and Northern Light. The results from these queries became the baseline data. The original 15 queries were then modified using the various search operators supported by each of the 5 search engines for a total of 210 queries. Each of these 210 queries was also submitted to the applicable search service. The results obtained were then compared to the baseline results. A total of 2,768 search results were returned by the set of all queries. In general, increasing the complexity of the queries had little effect on the results with a greater than 70% overlap in results, on average. Implications for the design of Web search services and directions for future research are discussed.

  11. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  12. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  13. Algorithms and Complexity Results for Exact Bayesian Structure Learning

    CERN Document Server

    Ordyniak, Sebastian

    2012-01-01

    Bayesian structure learning is the NP-hard problem of discovering a Bayesian network that optimally represents a given set of training data. In this paper we study the computational worst-case complexity of exact Bayesian structure learning under graph theoretic restrictions on the super-structure. The super-structure (a concept introduced by Perrier, Imoto, and Miyano, JMLR 2008) is an undirected graph that contains as subgraphs the skeletons of solution networks. Our results apply to several variants of score-based Bayesian structure learning where the score of a network decomposes into local scores of its nodes. Results: We show that exact Bayesian structure learning can be carried out in non-uniform polynomial time if the super-structure has bounded treewidth and in linear time if in addition the super-structure has bounded maximum degree. We complement this with a number of hardness results. We show that both restrictions (treewidth and degree) are essential and cannot be dropped without loosing uniform ...

  14. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  15. Recent development of glacier complex Adygine and resulting risks

    Science.gov (United States)

    Falatkova, Kristyna; Sobr, Miroslav; Engel, Zbynek; Jansky, Bohumir

    2015-04-01

    Recent development of glacier complex Adygine and resulting risks Falátková, K., Šobr, M., Engel, Z., Janský, B. Charles University in Prague, Faculty of Science, Prague, Czech republic Glacier complex Adygine (3,400-4,200 m asl) is situated on the northern flank of the Kyrgyz Range, Tien Shan, Kyrgyzstan. The valley downstream is part of National Park Ala Archa, which is popular with tourists, and is heading towards the country's capital - Bishkek. At the study site there is a glacier which is observed since 1960's. The glacier has been monitored by satellite imagery and in last 10 years by on-site geodetic measurement as well. Due to glacier shrinkage several glacial lakes of different genetic types (moraine-dammed, moraine- and rock-dammed, termokarst) have appeared at the site. Nowadays, the lakes are situated on three levels in front of the glacier's terminus and form a cascade, they are also hydrologically connected. The lakes were subjected to detailed bathymetric measurement and some parts of the dams were surveyed by geophysical methods. Especially the newest lakes in proximity of the terminus has been undergoing dynamic changes and may pose a threat in the near future. The risks arising together with changing climatic conditions and retreat of the glacier are associated with mainly three of the lakes. The largest one with area of 3.2 ha is dammed by a rock step overlaid by a moraine. Geophysical research of the dam revealed buried ice and seepage channels in its western part. It is the capacity of these subsurface channels, which are draining the lake throughout the year that represents a weak point in terms of dam stability. The second lake, a termokarst one, is a similar case but drained solely by subsurface channels. Very steep slopes of the lake basin are covered with loose material which could slide down and block the drainage channels. The lake would then fill all the basin (approx. 50,000 m3) very quickly as it is supplied with water from the

  16. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  17. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  18. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  19. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  20. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  1. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  2. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  3. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  4. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  5. Echocardiographic screening results in patients with tuberous sclerosis complex.

    NARCIS (Netherlands)

    Adriaensen, M.E.; Cramer, M.J.; Brouha, M.E.; Schaefer-Prokop, C.M.; Prokop, M.; Doevendans, P.A.; Zonnenberg, B.A.; Feringa, H.H.

    2010-01-01

    We sought to examine the frequency of abnormal echocardiographic findings in patients with tuberous sclerosis complex. In a retrospective cohort study, we included all patients with known tuberous sclerosis complex who had been sent to our cardiology department for echocardiographic screening from 1

  6. Complex VLSI Feature Comparison for Commercial Microelectronics Verification

    Science.gov (United States)

    2014-03-27

    verification of untrusted circuits using industry-standard and custom software. The process developed under TRUST and implemented at the AFRL Mixed Signal...79 5.2.3 SCR and Other Netlists . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.4 Additional Tools...Reliability of Integrated Circuits LVS layout versus schematic MOSIS the Metal Oxide Semiconductor Implementation Service MSDC Mixed Signal Design

  7. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  8. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  9. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  10. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  11. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  12. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  13. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  14. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  15. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  16. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  17. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  18. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  19. Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform

    Institute of Scientific and Technical Information of China (English)

    Xiong Chengyi; Tian Jinwen; Liu Jian

    2006-01-01

    Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.

  20. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  1. RESULTS OF APPLYING POLYVITAMIN COMPLEX FOR CHILDREN WITH ATOPIC DERMATITIS

    Directory of Open Access Journals (Sweden)

    N.A. Ivanova

    2007-01-01

    Full Text Available The article presents findings of applying vitamin-and-mineral complex (VMC for children frequently suffering from diseases and children with atopic dermatitis. It shows that usage of VMC within a complex therapy promotes regression of subnormal vitamin provision symptoms, as well as symptoms of the core disease. This happens against heightened vitamin content in child's organism — which was proven with the test of A and E vitamins content in blood. The research has demonstrated a quite good tolerance of VMC by children suffering from atopic dermatitis.Key words: children frequently suffering from diseases, atopic dermatitis, vitamins, treatment.

  2. Preliminary palaeomagnetic results from the Fen carbonatite complex, S. Norway

    NARCIS (Netherlands)

    Poorter, R.P.E.

    1972-01-01

    Samples from a hematite carbonate rock of the Eocambrian-Lower Cambrian Fen carbonatite-alkaline rock complex in southern Norway, yield a stable NRM with a direction after magnetic cleaning of D = 205°, I = −56° (N = 19, (k = 138, α95 = 3°). This corresponds with a palaeomagnetic pole position at

  3. Does the complex Langevin method give unbiased results?

    CERN Document Server

    Salcedo, L L

    2016-01-01

    We investigate whether the stationary solution of the Fokker-Planck equation of the complex Langevin algorithm reproduces the correct expectation values. When the complex Langevin algorithm for an action $S(x)$ is convergent, it produces an equivalent complex probability distribution $P(x)$ which ideally would coincide with $e^{-S(x)}$. We show that the projected Fokker-Planck equation fulfilled by $P(x)$ may contain an anomalous term whose form is made explicit. Such term spoils the relation $P(x)=e^{-S(x)}$, introducing a bias in the expectation values. Through the analysis of several periodic and non-periodic one-dimensional problems, using either exact or numerical solutions of the Fokker-Planck equation on the complex plane, it is shown that the anomaly is present quite generally. In fact, an anomaly is expected whenever the Langevin walker needs only a finite time to go to infinity and come back, and this is the case for typical actions. We conjecture that the anomaly is the rule rather than the excepti...

  4. Does the complex Langevin method give unbiased results?

    Science.gov (United States)

    Salcedo, L. L.

    2016-12-01

    We investigate whether the stationary solution of the Fokker-Planck equation of the complex Langevin algorithm reproduces the correct expectation values. When the complex Langevin algorithm for an action S (x ) is convergent, it produces an equivalent complex probability distribution P (x ) which ideally would coincide with e-S (x ). We show that the projected Fokker-Planck equation fulfilled by P (x ) may contain an anomalous term whose form is made explicit. Such a term spoils the relation P (x )=e-S (x ), introducing a bias in the expectation values. Through the analysis of several periodic and nonperiodic one-dimensional problems, using either exact or numerical solutions of the Fokker-Planck equation on the complex plane, it is shown that the anomaly is present quite generally. In fact, an anomaly is expected whenever the Langevin walker needs only a finite time to go to infinity and come back, and this is the case for typical actions. We conjecture that the anomaly is the rule rather than the exception in the one-dimensional case; however, this could change as the number of variables involved increases.

  5. Simplified microprocessor design for VLSI control applications

    Science.gov (United States)

    Cameron, K.

    1991-01-01

    A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

  6. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  7. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  8. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  9. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  10. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  11. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  12. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  13. A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.

    Science.gov (United States)

    Mill, R; Sheik, S; Indiveri, G; Denham, S L

    2011-10-01

    Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.

  14. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  15. Radiation damage studies of a recycling integrator VLSI chip for dosimetry and control of therapeutical beams

    Science.gov (United States)

    Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.

    2002-04-01

    A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.

  16. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    Science.gov (United States)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  17. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  18. Design of a reliable and self-testing VLSI datapath using residue coding techniques

    Science.gov (United States)

    Sayers, I. L.; Kinniment, D. J.; Chester, E. G.

    1986-05-01

    The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.

  19. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  20. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  1. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  2. VLSI Implementation of Digital Fourier Transforms.

    Science.gov (United States)

    1982-11-01

    23) which , coplte the proofi .t)0 !/*!, R,.),ta , ’,.[ ](5 ".: - 10- We now look at the structure of Theorem 1 for three cases. Cow 1: n -k = k...phase devices have reasonable signal ban- dung capabilities. From three phases on up the signal handling is very good, but the problem of routing all...Tompsett, Choarge Transfer Demices, Academic Press Inc. (1975). 4. J. W. Cooley and J. W. Tukey, "An Algorithm for the Machine Calculation of Complex

  3. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  4. Varfarin in the complex treatment of antiphospholipid syndrome: preliminary results

    Directory of Open Access Journals (Sweden)

    T M Reshetnyak

    2003-01-01

    Full Text Available Objective. To assess efficacy and tolerance of varfarin in prophylaxis and therapy of thrombotic complications in patients with antiphospholipid syndrome (APS. Methods. 20 pts with APS (5 male and 15 female received varfarin during a year. 8 of them had primary APS (PAPS and 12 -systemic lupus erythematosus with APS (SLE+APS. 2 other pts (I with SLE+APS and I with PAPS received varfarin during the last 4 years. Nobody from 9 pts with PAPS received corticosteroids (CS. In SLE+APS pts CS dose varied from 4 to 20 mg/day and was not increased during follow up. During the study prothrombine time (PT was examined with thromboplastin ( manufactured by Renam having international sensitivity index 1,2 and international normalization relation (INR. Depending on treatment scheme APS pts were divided into 3 groups. Group 1 included 8 pts with INR<2,0, Group 2-7 with INR >3,0, group 3 - 7 pts with INR<2,0 receiving as additional treatment thrombo ASS 100 mg/day and vasonit from 600 to 1200 mg/day. Results. Two pts with INR = 1,8 had thrombosis recurrence (due to leg thrombophlebitis. There were no recurrences in other groups. 2 from 22 pts had "large" bleedings. "Small" bleedings episodes were noted in 7 from 22 pts. Largely that were subcutaneous bleedings (in 4 pts no more than 5 cm of size. Two pts receiving varfarin with INR 1,8 and 2,4 had renal colic. Conclusion. Our preliminary results prove the necessity of inclusion of varfarin in the treatment of pts with APS and thrombosis but intensive anticoagulant effect is not always desired.

  5. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  6. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  7. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  8. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  9. VLSI digital PSK demodulator for space communication

    Science.gov (United States)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  10. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  11. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  12. Efficient FM Algorithm for VLSI Circuit Partitioning

    Directory of Open Access Journals (Sweden)

    M.RAJESH

    2013-04-01

    Full Text Available In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if theinitial partitioning matrix is close to the final partitioning then the computation time (iteration required is small . Here we have proposed novel approach to arrive at initial partitioning by using spectralfactorization method the results was verified using several circuits.

  13. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  14. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  15. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  16. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  17. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  18. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  19. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  20. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  1. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  2. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  3. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  4. Neuromorphic VLSI realization of the hippocampal formation.

    Science.gov (United States)

    Aggarwal, Anu

    2016-05-01

    The medial entorhinal cortex grid cells, aided by the subicular head direction cells, are thought to provide a matrix which is utilized by the hippocampal place cells for calculation of position of an animal during spatial navigation. The place cells are thought to function as an internal GPS for the brain and provide a spatiotemporal stamp on episodic memories. Several computational neuroscience models have been proposed to explain the place specific firing patterns of the cells of the hippocampal formation - including the GRIDSmap model for grid cells and Bayesian integration for place cells. In this work, we present design and measurement results from a first ever system of silicon circuits which successfully realize the function of the hippocampal formation of brain based on these models.

  5. Vlsi Implementation of Edge Detection for Images

    Directory of Open Access Journals (Sweden)

    T. Mahalakshmi

    2012-12-01

    Full Text Available Edge is the boundary between the image and its background. Edge detection in general is defined as the local maxima obtained from high pass filters, but an optimized edge detector should mark the edges with respect to luminance or brightness changes. It is easy to obtain them in software implementation but for hardware implementation there is an issue with percentage of accuracy and processing time. This study discusses various edge detection algorithms and proposes an optimized edge detector which provides the solution for mentioned above issue. Since FPGA provides practical solutions for most of the image processing problems, the proposed architecture has been developed using Matlab System generator. Experimental results show the accuracy of edge detected using proposed architecture.

  6. Lossless compression of VLSI layout image data.

    Science.gov (United States)

    Dai, Vito; Zakhor, Avideh

    2006-09-01

    We present a novel lossless compression algorithm called Context Copy Combinatorial Code (C4), which integrates the advantages of two very disparate compression techniques: context-based modeling and Lempel-Ziv (LZ) style copying. While the algorithm can be applied to many lossless compression applications, such as document image compression, our primary target application has been lossless compression of integrated circuit layout image data. These images contain a heterogeneous mix of data: dense repetitive data better suited to LZ-style coding, and less dense structured data, better suited to context-based encoding. As part of C4, we have developed a novel binary entropy coding technique called combinatorial coding which is simultaneously as efficient as arithmetic coding, and as fast as Huffman coding. Compression results show C4 outperforms JBIG, ZIP, BZIP2, and two-dimensional LZ, and achieves lossless compression ratios greater than 22 for binary layout image data, and greater than 14 for gray-pixel image data.

  7. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  8. Complex Predicates : Verbal Complexes, Resultative Constructions, and Particle Verbs in German

    NARCIS (Netherlands)

    Müller, Stefan

    2002-01-01

    In this book, I presented analyses for auxiliaries, subject and object control verbs, subject and object raising verbs, copula constructions, subject and object predicative constructions, depictive predicates, resultative predicate constructions, and particle verbs. The depictive predicates were ana

  9. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  10. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  11. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  12. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  13. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  14. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  15. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  16. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  17. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  18. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  19. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  20. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  1. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  2. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  3. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  4. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  5. Deep sub-micron stud-via technology for superconductor VLSI circuits

    Science.gov (United States)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  6. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  7. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  8. Acceptable results using plug for the treatment of complex anal fistulas

    DEFF Research Database (Denmark)

    Kleif, Jakob; Hagen, Kikke; Wille-Jørgensen, Peer

    2011-01-01

    The management of complex fistula-in-ano remains a surgical challenge. Previously published studies on the treatment of fistula-in-ano with the anal fistula plug (AFP) have reported a success rate reaching 35-87%. The aim of this study was to assess the results of the AFP procedure in a group...... of Danish patients with complex fistulas, and to analyse if the results were compatible with previous international findings....

  9. Generalized contraction resulting tripled fixed point theorems in complex valued metric spaces

    Directory of Open Access Journals (Sweden)

    Madhu Singh

    2016-10-01

    Full Text Available Owning the concept of complex valued metric spaces introduced by Azam et al.[1] many authors prove several fixed point results for mappings satisfying certain contraction conditions. Coupled and tripled fixed point problems have attracted much attention in recent times. In this note, common tripled fixed point theorems for a pairs of mappings satisfying certain rational contraction in complex valued metric spaces are proved. Some illustrative examples are also given which demonstrate the validity of the hypotheses of our results.

  10. Trichotomy and Dichotomy Results on the Complexity of Reasoning with Disjunctive Logic Programs

    CERN Document Server

    Truszczynski, Miroslaw

    2010-01-01

    We present trichotomy results characterizing the complexity of reasoning with disjunctive logic programs. To this end, we introduce a certain definition schema for classes of programs based on a set of allowed arities of rules. We show that each such class of programs has a finite representation, and for each of the classes definable in the schema we characterize the complexity of the existence of an answer set problem. Next, we derive similar characterizations of the complexity of skeptical and credulous reasoning with disjunctive logic programs. Such results are of potential interest. On the one hand, they reveal some reasons responsible for the hardness of computing answer sets. On the other hand, they identify classes of problem instances, for which the problem is "easy" (in P) or "easier than in general" (in NP). We obtain similar results for the complexity of reasoning with disjunctive programs under the supported-model semantics.

  11. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Science.gov (United States)

    Sabatini, Silvio P.; Solari, Fabio; Cavalleri, Paolo; Bisio, Giacomo Mario

    2003-12-01

    We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth), from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations) on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  12. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  13. An Opto-VLSI-based reconfigurable optical adddrop multiplexer employing an off-axis 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Ahderom, Selam; Alameh, Kamal

    2009-08-03

    A novel reconfigurable optical add-drop multiplexer (ROADM) structure is proposed and demonstrated experimentally. The ROADM structure employs two arrayed waveguide gratings (AWGs), an array of optical fiber pairs, an array of 4-f imaging microlenses that are offset in relation to the axis of symmetry of the fiber pairs, and a reconfigurable Opto-VLSI processor that switches various wavelength channels between the fiber pairs to achieve add or drop multiplexing. Experimental results are shown, which demonstrate the principle of add/drop multiplexing with crosstalk of less than -27dB and insertion loss of less than 8dB over the Cband for drop and through operation modes.

  14. Distinct rhythmic locomotor patterns can be generated by a simple adaptive neural circuit: biology, simulation, and VLSI implementation.

    Science.gov (United States)

    Ryckebusch, S; Wehr, M; Laurent, G

    1994-12-01

    Rhythmic motor patterns can be induced in leg motor neurons of isolated locust thoracic ganglia by bath application of pilocarpine. We observed that the relative phases of levators and depressors differed in the three thoracic ganglia. Assuming that the central pattern generating circuits underlying these three segmental rhythms are probably very similar, we developed a simple model circuit that can produce any one of the three activity patterns and characteristic phase relationships by modifying a single synaptic weight. We show results of a computer simulation of this circuit using the neuronal simulator NeuraLOG/Spike. We built and tested an analog VLSI circuit implementation of this model circuit that exhibits the same range of "behaviors" as the computer simulation. This multidisciplinary strategy will be useful to explore the dynamics of central pattern generating networks coupled to physical actuators, and ultimately should allow the design of biologically realistic walking robots.

  15. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  16. Dynamics of nanoparticle-protein corona complex formation: analytical results from population balance equations.

    Directory of Open Access Journals (Sweden)

    Faryad Darabi Sahneh

    Full Text Available BACKGROUND: Nanoparticle-protein corona complex formation involves absorption of protein molecules onto nanoparticle surfaces in a physiological environment. Understanding the corona formation process is crucial in predicting nanoparticle behavior in biological systems, including applications of nanotoxicology and development of nano drug delivery platforms. METHOD: This paper extends the modeling work in to derive a mathematical model describing the dynamics of nanoparticle corona complex formation from population balance equations. We apply nonlinear dynamics techniques to derive analytical results for the composition of nanoparticle-protein corona complex, and validate our results through numerical simulations. RESULTS: The model presented in this paper exhibits two phases of corona complex dynamics. In the first phase, proteins rapidly bind to the free surface of nanoparticles, leading to a metastable composition. During the second phase, continuous association and dissociation of protein molecules with nanoparticles slowly changes the composition of the corona complex. Given sufficient time, composition of the corona complex reaches an equilibrium state of stable composition. We find analytical approximate formulae for metastable and stable compositions of corona complex. Our formulae are very well-structured to clearly identify important parameters determining corona composition. CONCLUSION: The dynamics of biocorona formation constitute vital aspect of interactions between nanoparticles and living organisms. Our results further understanding of these dynamics through quantitation of experimental conditions, modeling results for in vitro systems to better predict behavior for in vivo systems. One potential application would involve a single cell culture medium related to a complex protein medium, such as blood or tissue fluid.

  17. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  18. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  19. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  20. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  1. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  2. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  3. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  4. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  5. Some Ramsey-type results on intrinsic linking of n-complexes

    CERN Document Server

    Tuffley, Christopher

    2011-01-01

    Define the complete n-complex on N vertices to be the n-skeleton of an (N-1)-simplex. We show that embeddings of sufficiently large complete n-complexes in R^{2n+1} necessarily exhibit complicated linking behaviour, such as nontrivial r-component links, or 2-component links with large linking number. This extends known results on embeddings of large complete graphs in R^3 (the case n=1) to higher dimensions. Our results include one previously unknown for embeddings of graphs in R^3: namely, given a natural number q, we show that every embedding of a sufficiently large complete n-complex in R^{2n+1} contains a 2-component link with linking number a nonzero multiple of q. For n=1 this was previously known only in the cases q=3, and q a power of two. For fixed n the number of vertices required for this last result grows at most polynomially in q.

  6. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  7. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  8. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  9. Acceptable results using plug for the treatment of complex anal fistulas

    DEFF Research Database (Denmark)

    Kleif, Jakob; Hagen, Kikke; Wille-Jørgensen, Peer

    2011-01-01

    The management of complex fistula-in-ano remains a surgical challenge. Previously published studies on the treatment of fistula-in-ano with the anal fistula plug (AFP) have reported a success rate reaching 35-87%. The aim of this study was to assess the results of the AFP procedure in a group...

  10. 低成本可调FFT处理器的超大规模集成电路设计%Low Cost VLSI Design of a Flexible FFT Processor

    Institute of Scientific and Technical Information of China (English)

    戴亦奇

    2011-01-01

    In this paper, a radix-22/23 based pipeline structure is presented, in order to implement a low-cost VLSI fast Fourier transform (FFT) processor. As well as reducing the steps of normal complex multiplications, it minimizes the memory words to get the FFT results with the single-path delay feedback (SDF) memory access method. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements.%文章提出了一种以基-22/23为基础的流水线结构,用以实现低成本、超大规模集成电路(VLSI)的快速傅里叶变换(FFT)处理器设计。该处理器在减少普通复数乘法器级数的同时,通过单路延时反馈(SDF)存取方式,以最少的存储字来获得FFT结果。对于数据通路,我们采用了混合浮点的数据缩放方式,在保证信噪比的同时,降低了数据长度和RAM容量的需求。

  11. Treatment of complex PTSD: results of the ISTSS expert clinician survey on best practices.

    Science.gov (United States)

    Cloitre, Marylene; Courtois, Christine A; Charuvastra, Anthony; Carapezza, Richard; Stolbach, Bradley C; Green, Bonnie L

    2011-12-01

    This study provides a summary of the results of an expert opinion survey initiated by the International Society for Traumatic Stress Studies Complex Trauma Task Force regarding best practices for the treatment of complex posttraumatic stress disorder (PTSD). Ratings from a mail-in survey from 25 complex PTSD experts and 25 classic PTSD experts regarding the most appropriate treatment approaches and interventions for complex PTSD were examined for areas of consensus and disagreement. Experts agreed on several aspects of treatment, with 84% endorsing a phase-based or sequenced therapy as the most appropriate treatment approach with interventions tailored to specific symptom sets. First-line interventions matched to specific symptoms included emotion regulation strategies, narration of trauma memory, cognitive restructuring, anxiety and stress management, and interpersonal skills. Meditation and mindfulness interventions were frequently identified as an effective second-line approach for emotional, attentional, and behavioral (e.g., aggression) disturbances. Agreement was not obtained on either the expected course of improvement or on duration of treatment. The survey results provide a strong rationale for conducting research focusing on the relative merits of traditional trauma-focused therapies and sequenced multicomponent approaches applied to different patient populations with a range of symptom profiles. Sustained symptom monitoring during the course of treatment and during extended follow-up would advance knowledge about both the speed and durability of treatment effects. Copyright © 2011 International Society for Traumatic Stress Studies.

  12. Results on the heavy-dense QCD phase diagram using complex Langevin

    CERN Document Server

    Aarts, Gert; Jäger, Benjamin; Sexty, Dénes

    2016-01-01

    Complex Langevin simulations have been able to successfully reproduce results from Monte Carlo methods in the region where the sign problem is mild and make predictions when it is exponentially hard. We present here our study of the QCD phase diagram and the boundary between the confined and deconfined phases in the limit of heavy and dense quarks (HDQCD) for 3 different lattice volumes. We also briefly discuss instabilities encountered in our simulations.

  13. Results of an inter and intra laboratory exercise on the assessment of complex autosomal DNA profiles.

    Science.gov (United States)

    Benschop, Corina C G; Connolly, Edward; Ansell, Ricky; Kokshoorn, Bas

    2017-01-01

    The interpretation of complex DNA profiles may differ between laboratories and reporting officers, which can lead to discrepancies in the final reports. In this study, we assessed the intra and inter laboratory variation in DNA mixture interpretation for three European ISO17025-accredited laboratories. To this aim, 26 reporting officers analyzed five sets of DNA profiles. Three main aspects were considered: 1) whether the mixed DNA profiles met the criteria for comparison to a reference profile, 2) the actual result of the comparison between references and DNA profiling data and 3) whether the weight of the DNA evidence could be assessed. Similarity in answers depended mostly on the complexity of the tasks. This study showed less variation within laboratories than between laboratories which could be the result of differences between internal laboratory guidelines and methods and tools available. Results show the profile types for which the three laboratories report differently, which informs indirectly on the complexity threshold the laboratories employ. Largest differences between laboratories were caused by the methods available to assess the weight of the DNA evidence. This exercise aids in training forensic scientists, refining laboratory guidelines and explaining differences between laboratories in court. Undertaking more collaborative exercises in future may stimulate dialog and consensus regarding interpretation. For training purposes, DNA profiles of the mixed stains and questioned references are made available. Copyright © 2016 The Chartered Society of Forensic Sciences. Published by Elsevier Ireland Ltd. All rights reserved.

  14. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  15. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  16. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  17. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  18. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  19. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  20. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  1. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  2. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  3. [The results of complex social and ecologic study in the city of Ufa].

    Science.gov (United States)

    Zakharov, I D; Magasumov, A M; Simonova, N I; Eĭdel'man, Ia L; Simenido, Iu V

    1997-01-01

    The authors present results of social and ecologic study carried out in Ufa. The results describe the course of ecologically important processes and phenomena in correlation with the public subjective understanding. Public health is influenced by hygienic parameters of food and water quality as well as a complex of social, economic and psychologic factors. Weak correlation between those parameters and ambient air pollution necessitates more accurate approach to ecologic mapping of cities and to manipulation with data on lower atmosphere pollution with chemical hazards.

  4. The Study for Results of Complex Cystic Breast Masses by Biopsy on Ultrasound

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Hye Kyoung [Dept. of Radiology, Yangji General Hospital, Kwangju (Korea, Republic of); Dong, Kyung Rae [Dept. of Radiological Technology, Gwangju Health College, Kwangju (Korea, Republic of)

    2008-06-15

    We examined the roles of Ultrasonography conductors by analyzing the results of tissue biopsy of complex cystic masse under the guidance of breast US. This study was performed to a group of 178 who showed breast US indicating complex cystic masses among 342 patients who were definitely diagnosed by tissue biopsies and operations in our hospital from June 30th, 2003 to June 30th, 2007. The evaluation of tissues around, calcification, the distribution state of blood flow were excluded from the analysis subjects and logic 200 made by GE corporation and gun for core biopsy(Kimal corp., K7/MBD23) were used in this study. The biopsy results of 178 subjects showed FCC (fibrocystic change)(n=56 : 31.4%), Fibrosis (n=41 : 23.0%), Fibroadenoma (n=20 : 11.2%), Epithelial hyperplasia (n=17 : 9.6%), Carcinoma (n=15 : 8.4%), Fibroadipose (n=8 : 4.5%), Sclerosing adenosis (n=7 : 3.9%), Duct ectasia (n=5 : 2.8%), Papiloma (n=5 : 2.8%), and Fat necrosis (n=1 : 0.6%), Hemangioma (n=1 : 0.6%), Abscess (n=1 : 0.6%), Dystrophic calcification(n=1 : 0.6%). The US showed that the results of the tissue biopsy of complex cystic masses were mostly carcinoma(8.4%). Most of them were benign and only 9.6% of epithelial hyperplasia which has high progression rate into malignant tumors epidemically showed malignancy. Most of them were included in the spectrum of fibrous cystic nodule. Even though these results are confirmed, further studies are required. As a result, a nodule which is not certified by US should be right to take the tissue biopsy, but if it's difficult due to patients or another reasons, re-check tests in three months are required. And systemic ultrasonography evaluation should be well recognized to conduct more careful and specific tests.

  5. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  6. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  7. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  8. Preliminary assessment of the Long Island National Wildlife Refuge Complex environmental contaminants background study: Fourth year results

    Data.gov (United States)

    US Fish and Wildlife Service, Department of the Interior — This report represents the results of the fourth year of the multi-year study, the Long Island National Wildlife Refuge Complex (Complex) Environmental Contaminants...

  9. Preliminary assessment of the Long Island National Wildlife Refuge Complex Environmental contaminants background survey: Second year results

    Data.gov (United States)

    US Fish and Wildlife Service, Department of the Interior — This report represents the preliminary results of the second year of the multiyear study, The Long Island National Wildlife Refuge Complex (Complex) Environmental...

  10. Preliminary assessment of the Long Island National Wildlife Refuge Complex environmental contaminants background study: Fifth year results

    Data.gov (United States)

    US Fish and Wildlife Service, Department of the Interior — This report represents the preliminary results of the fifth year of the multiyear study entitled, "The Long Island National Wildlife Refuge Complex (Complex)...

  11. VLSI circuits implementing computational models of neocortical circuits.

    Science.gov (United States)

    Wijekoon, Jayawan H B; Dudek, Piotr

    2012-09-15

    This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.

  12. How to build VLSI-efficient neural chips

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-02-01

    This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

  13. Purification of Ovine Respiratory Complex I Results in a Highly Active and Stable Preparation.

    Science.gov (United States)

    Letts, James A; Degliesposti, Gianluca; Fiedorczuk, Karol; Skehel, Mark; Sazanov, Leonid A

    2016-11-18

    NADH-ubiquinone oxidoreductase (complex I) is the largest (∼1 MDa) and the least characterized complex of the mitochondrial electron transport chain. Because of the ease of sample availability, previous work has focused almost exclusively on bovine complex I. However, only medium resolution structural analyses of this complex have been reported. Working with other mammalian complex I homologues is a potential approach for overcoming these limitations. Due to the inherent difficulty of expressing large membrane protein complexes, screening of complex I homologues is limited to large mammals reared for human consumption. The high sequence identity among these available sources may preclude the benefits of screening. Here, we report the characterization of complex I purified from Ovis aries (ovine) heart mitochondria. All 44 unique subunits of the intact complex were identified by mass spectrometry. We identified differences in the subunit composition of subcomplexes of ovine complex I as compared with bovine, suggesting differential stability of inter-subunit interactions within the complex. Furthermore, the 42-kDa subunit, which is easily lost from the bovine enzyme, remains tightly bound to ovine complex I. Additionally, we developed a novel purification protocol for highly active and stable mitochondrial complex I using the branched-chain detergent lauryl maltose neopentyl glycol. Our data demonstrate that, although closely related, significant differences exist between the biochemical properties of complex I prepared from ovine and bovine mitochondria and that ovine complex I represents a suitable alternative target for further structural studies.

  14. Clinical results of the complex prevention of the acute postoperative pancreatitis at the surgical gastroenterology

    Directory of Open Access Journals (Sweden)

    Kotenko К.V.

    2013-12-01

    Full Text Available The article aims to study the results of the complex prevention of the acute postoperative pancreatitis in the surgical gastroenterology. Material and methods. 2968 patients with various disorders of the digestive system were operated. Empirical preventing of the acute postoperative pancreatitis was used in the control group. Complex prevention of the acute postoperative pancreatitis in the main group of patients included the use of Dalargin, intravenous infusion of Octreotide, duodenal trypsin enzyme inhibition; intraduodenal reversal of pancreatic secret; intraductal injection of Lidocaine and external transnasal drainage of the pancreatic and biliary ducts. Results. The frequency of acute postoperative pancreatitis was 12.2% in the main group. The frequency of acute postoperative pancreatitis was 36.9% in the control group. Increased frequency of a mild form of the acute postoperative pancreatitis observed in the main group compared with the control. At the same time reducing the frequency of the moderate severity and severity forms of the acute postoperative pancreatitis observed in the main group compared with the control. Reduction of the morbidity (13.6% vs. 25.1%, hospital mortality (1.6% vs. 3.5%, the duration of the postoperative hospital bed-day (12.1±0.4 vs. 16.7±0.6 were identified in the main group patients compared with the control group. Conclusion. The use of the given scheme for the complex prevention of the acute postoperative pancreatitis allowed significantly reduce the frequency and severity of illness, morbidity, reduce the duration of postoperative hospital bed-day and hospital mortality, as well as the frequency of both mild and severity, and fatal postoperative complications in all investigated groups of patients.

  15. Preliminary Results of the Herschel Gould Belt Survey in the Orion B Complex

    Science.gov (United States)

    Könyves, Vera; André, Philippe; Palmeirim, Pedro; Schneider, Nicola; Arzoumanian, Doris; Men'shchikov, Alexander

    As a preliminary result of the Herschel Gould Belt survey (André et al. 2010) in the Orion B cloud complex we find a clear connection between the locations of the detected prestellar cores and the column density values. We find that the vast majority of the gravitationally bound prestellar cores are detected above a high column density of about 6-7 × 1021 cm-2 (A V ˜ 6-7). This is in very good agreement with dense core formation thresholds found in other regions. For Orion B, a similar limit appears both in the distribution of background column density values of the prestellar cores, and in the column density PDF of the region. Within our core formation scenario, the found threshold can be translated as the column density above which the filaments become gravitationally unstable and fragment into cores.

  16. Promising results after single-stage reconstruction of the nipple and areola complex

    DEFF Research Database (Denmark)

    Børsen-Koch, Mikkel; Bille, Camilla; Thomsen, Jørn B

    2013-01-01

    Introduction: Reconstruction of the nipple-areola complex (NAC) traditionally marks the end of breast reconstruction. Several different surgical techniques have been described, but most are staged procedures. This paper describes a simple single-stage approach. Material and Methods: We used...... a technique based on a local flap for reconstruction of the nipple in combination with immediate intradermal tattooing for reconstruction of the areola. Results: We reviewed the outcome of 22 cases of women who had simple single-stage reconstruction over a period of one year. We found no major and only two...... reconstruction was 43 min. (30-50 min.). Conclusion: This simple single-stage NAC reconstruction seems beneficial for both patient and surgeon as it seems to be associated with faster reconstruction and reduced procedure-related time without compromising the aesthetic outcome or the morbidity associated...

  17. T-SPOT.TB Test(R) results in adults with Mycobacterium avium complex pulmonary disease.

    Science.gov (United States)

    Adams, Lisa V; Waddell, Richard D; Von Reyn, C Fordham

    2008-01-01

    The tuberculin skin test is limited by its inability to distinguish between infection with Mycobacterium tuberculosis and non-tuberculous mycobacteria (NTM). Newer interferon-gamma release assays using ESAT-6 and CFP-10 antigens should have a higher specificity for tuberculosis but have not been widely tested in adults with pulmonary disease due to NTM. In this study, we tested the T-SPOT.TB Test in patients with pulmonary disease due to Mycobacterium avium complex (MAC), the most common disease-causing NTM. Fourteen patients with prior culture-confirmed pulmonary disease due to MAC, 10 patients with prior culture-confirmed tuberculosis and 4 healthy controls were interviewed and tested with the T-SPOT.TB Test. 13 patients with MAC disease and 4 healthy subjects (negative controls) had non-reactive T-SPOT.TB results and 10 patients with prior tuberculosis (positive controls) had reactive results. One patient with MAC disease had a minimally reactive result on initial testing and a non-reactive result on re-testing. The T-SPOT.TB Test had a specificity of 94% for distinguishing between patients with prior MAC disease and prior tuberculosis disease, and will be useful in low tuberculosis prevalence settings where most mycobacterial infections are due to MAC. Reactions to the T-SPOT.TB Test may persist months to years after treatment of tuberculosis.

  18. Complex Behavior of Aqueous α-Cyclodextrin Solutions. Interfacial Morphologies Resulting from Bulk Aggregation.

    Science.gov (United States)

    Hernandez-Pascacio, Jorge; Piñeiro, Ángel; Ruso, Juan M; Hassan, Natalia; Campbell, Richard A; Campos-Terán, José; Costas, Miguel

    2016-07-05

    The spontaneous aggregation of α-cyclodextrin (α-CD) molecules in the bulk aqueous solution and the interactions of the resulting aggregates at the liquid/air interface have been studied at 283 K using a battery of techniques: transmission electron microscopy, dynamic light scattering, dynamic surface tensiometry, Brewster angle microscopy, neutron reflectometry, and ellipsometry. We show that α-CD molecules spontaneously form aggregates in the bulk that grow in size with time. These aggregates adsorb to the liquid/air interface with their size in the bulk determining the adsorption rate. The material that reaches the interface coalesces laterally to form two-dimensional domains on the micrometer scale with a layer thickness on the nanometer scale. These processes are affected by the ages of both the bulk and the interface. The interfacial layer formed is not in fast dynamic equilibrium with the subphase as the resulting morphology is locked in a kinetically trapped state. These results reveal a surprising complexity of the parallel physical processes taking place in the bulk and at the interface of what might have seemed initially like a simple system.

  19. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  20. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  1. Results of the Gore Hybrid Vascular Graft in Challenging Aortic Branch Revascularization during Complex Aneurysm Repair.

    Science.gov (United States)

    Tsilimparis, Nikolaos; Larena-Avellaneda, Axel; Krause, Benjamin; Wipper, Sabine; Diener, Holger; Kölbel, Tilo; Debus, E Sebastian

    2015-10-01

    Prolonged organ ischemia during complex aortic surgery is associated with increased morbidity and mortality. A novel hybrid graft (Gore Hybrid Vascular Graft) as composite of expanded polytetrafluorethylene vascular prosthesis that has a section reinforced with nitinol was investigated for feasibility and effectiveness during aortic repair. Retrospective analysis of all consecutive patients treated with the hybrid vascular graft (HVG). Indication for graft implantation was surgeon's preference for branch revascularization in challenging aortic repair. Within 26 months, 25 Gore HVGs and 17 conventional grafts were implanted in 12 patients (age, 73 years; range, 33-79 years, 8 men). Eleven patients were treated for thoracoabdominal aortic aneurysms and one for aortoiliac aneurysm (elective = 6, urgent = 6). Nine visceral debranching procedures, 2 Crawford procedures, and 1 repair of an internal iliac aneurysm were performed. The distribution of HVG use was left renal artery = 10, right renal artery = 9, superior mesenteric artery = 4, celiac trunk = 1, and internal iliac artery = 1. Time to restore visceral blood flow during visceral debranching was 7 ± 4 min for the Gore HVG vs. 12 ± 6 min for conventional grafts (P Gore HVG offers a new, simplified, and time-sparing technique for visceral anastomoses during complex aneurysm repair. However, long-term results are still lacking and need to be awaited. Copyright © 2015 Elsevier Inc. All rights reserved.

  2. Iron Isotope Systematics of the Bushveld Complex, South Africa: Initial Results

    Science.gov (United States)

    Stausberg, N.; Lesher, C. E.; Hoffmann-Barfod, G.; Glessner, J. J.; Tegner, C.

    2014-12-01

    Iron isotopes show systematic changes in igneous rocks that have been ascribed to fractional crystallization, partial melting, as well as, diffusion effects. Layered mafic intrusions, such as the Paleoproterozoic Bushveld Igneous Complex, are ideally suited to investigate stable isotope fractionation arising principally by fractional crystallization. The upper 2.1km of the Bushveld Complex (Upper and Upper Main Zone, UUMZ) crystallized from a basaltic magma produced by a major recharge event, building up a sequence of tholeiitic, Fe-rich, gabbroic cumulate rocks that display systematic variations in mineralogy and mineral compositions consistent with fractional crystallization. Within this sequence, magnetite joins the liquidus assemblage at ˜260m, followed by olivine at 460m and apatite at 1000m. Here, we present iron isotope measurements of bulk cumulate rocks from the Bierkraal drill core of UUMZ of the western limb. Iron was chemically separated from its matrix and analyzed for δ56Fe (relative to IRMM- 014) with a Nu plasma MC-ICPMS at the University of California, Davis, using (pseudo-) high resolution and sample-standard bracketing. The δ56Fe values for Bushveld cumulates span a range from 0.04‰ to 0.36‰, and systematically correlate with the relative abundance of pyroxene + olivine, magnetite and plagioclase. Notably, the highest δ56Fe values are found in plagioclase-rich cumulates that formed prior to magnetite crystallization. δ56Fe is also high in magnetite-rich cumulates at the onset of magnetite crystallization, while subsequent cumulates exhibit lower and variable δ56Fe principally reflecting fractionation of and modal variations in magnetite, pyroxene and fayalitic olivine. The overall relationships for δ56Fe are consistent with positive mineral - liquid Fe isotope fractionation factors for magnetite and plagioclase, and negative to near zero values for pyroxene and olivine. These initial results are being integrated into a forward model of

  3. Complex conductivity results to silver nanoparticles in partically saturated laboratory columns

    Data.gov (United States)

    U.S. Environmental Protection Agency — Laboratory complex conductivity data from partially saturated sand columns with silver nanoparticles. This dataset is not publicly accessible because: It involves...

  4. Time Complexity of Evolutionary Algorithms for Combinatorial Optimization: A Decade of Results

    Institute of Scientific and Technical Information of China (English)

    Pietro S. Oliveto; Jun He; Xin Yao

    2007-01-01

    Computational time complexity analyzes of evolutionary algorithms (EAs) have been performed since the mid-nineties. The first results were related to very simple algorithms, such as the (1+1)-EA, on toy problems. These efforts produced a deeper understanding of how EAs perform on different kinds of fitness landscapes and general mathematical tools that may be extended to the analysis of more complicated EAs on more realistic problems. In fact, in recent years, it has been possible to analyze the (1+1)-EA on combinatorial optimization problems with practical applications and more realistic population-based EAs on structured toy problems. This paper presents a survey of the results obtained in the last decade along these two research lines. The most common mathematical techniques are introduced, the basic ideas behind them are discussed and their elective applications are highlighted. Solved problems that were still open are enumerated as are those still awaiting for a solution. New questions and problems arisen in the meantime are also considered.

  5. First results from the International Urban Energy Balance Model Comparison: Model Complexity

    Science.gov (United States)

    Blackett, M.; Grimmond, S.; Best, M.

    2009-04-01

    A great variety of urban energy balance models has been developed. These vary in complexity from simple schemes that represent the city as a slab, through those which model various facets (i.e. road, walls and roof) to more complex urban forms (including street canyons with intersections) and features (such as vegetation cover and anthropogenic heat fluxes). Some schemes also incorporate detailed representations of momentum and energy fluxes distributed throughout various layers of the urban canopy layer. The models each differ in the parameters they require to describe the site and the in demands they make on computational processing power. Many of these models have been evaluated using observational datasets but to date, no controlled comparisons have been conducted. Urban surface energy balance models provide a means to predict the energy exchange processes which influence factors such as urban temperature, humidity, atmospheric stability and winds. These all need to be modelled accurately to capture features such as the urban heat island effect and to provide key information for dispersion and air quality modelling. A comparison of the various models available will assist in improving current and future models and will assist in formulating research priorities for future observational campaigns within urban areas. In this presentation we will summarise the initial results of this international urban energy balance model comparison. In particular, the relative performance of the models involved will be compared based on their degree of complexity. These results will inform us on ways in which we can improve the modelling of air quality within, and climate impacts of, global megacities. The methodology employed in conducting this comparison followed that used in PILPS (the Project for Intercomparison of Land-Surface Parameterization Schemes) which is also endorsed by the GEWEX Global Land Atmosphere System Study (GLASS) panel. In all cases, models were run

  6. Care complexity in the general hospital - Results from a European study

    NARCIS (Netherlands)

    de Jonge, P; Huyse, FJ; Slaets, JPJ; Herzog, T; Lobo, A; Lyons, JS; Opmeer, BC; Stein, B; Arolt, [No Value; Balogh, N; Cardoso, G; Fink, P; Rigatelli, M; van Dijck, R; Mellenbergh, GJ

    2001-01-01

    There is increasing pressure to effectively treat patients with complex care needs from the moment of admission to the general hospital. In this study, the authors developed a measurement strategy for hospital-based care complexity. The authors' four-factor model describes the interrelations between

  7. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  8. New Metric Based Algorithm for Test Vector Generation in VLSI Testing

    Directory of Open Access Journals (Sweden)

    M. V. Atre

    1995-07-01

    Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.

  9. Spike-based VLSI modeling of the ILD system in the echolocating bat.

    Science.gov (United States)

    Horiuchi, T; Hynna, K

    2001-01-01

    The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.

  10. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  11. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  12. Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.

    Science.gov (United States)

    1984-10-01

    analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI

  13. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  14. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  15. Clinical heterogeneity of human neurocysticercosis results from complex interactions among parasite, host and environmental factors.

    Science.gov (United States)

    Fleury, Agnès; Escobar, Alfonso; Fragoso, Gladis; Sciutto, Edda; Larralde, Carlos

    2010-04-01

    Human neurocysticercosis (NC) is endemic in most countries of Latin America, Asia and Africa and is re-emerging in some industrialized nations. Both within and among endemic countries, NC is very variable in its clinical and radiological features, as well as in the intensity of the immuno-inflammatory reactions of the hosts. This review, focusing on the Mexican experience, describes and interprets the heterogeneity of NC as the result of different combinations among factors associated with the parasite, host and environment. The review may serve to foster similar descriptive efforts in other endemic areas of the world in order to facilitate the identification of the distinct factors that participate in the complex pathogenesis and diverse clinical outcomes of NC. In particular, it is necessary to understand the precise physiopathology of the inflammatory reaction associated with NC, as inflammation is one of the characteristics of those NC cases that are clinically more severe and less responsive to current treatments. Devising new medical interventions through the use of molecular regulators of the innate and adaptive immune responses of the host is a largely unexplored approach that could improve the existing forms of treatment. Copyright 2010 Royal Society of Tropical Medicine and Hygiene. Published by Elsevier Ltd. All rights reserved.

  16. SAFARI - RANDOMISED TRIAL ON COMPLEX THERAPY OF ARTERIAL HYPERTENSION AND DISLIPIDEMY. THE MAIN RESULTS

    Directory of Open Access Journals (Sweden)

    S. Y. Martsevich

    2016-01-01

    Full Text Available Aim. To evaluate possibility of complex pharmaceutical effect simultaneously on 2 risk factors – arterial hypertension (HT and hypercholesterolemia (HH in patients with high risk of cardiovascular complications (CVC.Material and methods. 101 patients with HT of 1-2 stage, HH and high risk of CVC (SCORE>5 were included in the study. Patients were randomized in 2 groups: active therapy group (ATG and control group (CG. ATG patients were actively treated for HT and HH control. The long-acting nifedipine (Nifecard XL, LEK 30 mg once daily (OD was prescribed as start antihypertensive drug. Hydrochlorothiazide 12,5 mg/day OD and bisiprolol 5 mg OD was added if antihypertensive effect was insufficient. Atorvastatin (Tulip, LEK 20-40 mg OD was prescribed for HH control. Management of CG patients was performed by doctors of out-patient clinics. The study duration was 12 weeks.Results. Systolic and diastolic blood pressure (BP levels in ATG patients were lower than these in CG patients. Target BP level was reached in 88,4% of ATG patients and only in 48,9% of CG patients. Cholesterol of low density lipoprotein (CH LPLD level was also lower in ATG patients than this in CG patients. Target CH LPLD level was reached in 37,2 % of ATG patients and in 8,3 % of CG patients. Relative risk of CVC was significantly lower in ATG patients than this in CG patients.Conclusion. SAFARI trial shows that effective pharmaceutical simultaneous control of 2 key risk factors, HT and HH, results in risk reduction of CVC.

  17. Complexity

    CERN Document Server

    Gershenson, Carlos

    2011-01-01

    The term complexity derives etymologically from the Latin plexus, which means interwoven. Intuitively, this implies that something complex is composed by elements that are difficult to separate. This difficulty arises from the relevant interactions that take place between components. This lack of separability is at odds with the classical scientific method - which has been used since the times of Galileo, Newton, Descartes, and Laplace - and has also influenced philosophy and engineering. In recent decades, the scientific study of complexity and complex systems has proposed a paradigm shift in science and philosophy, proposing novel methods that take into account relevant interactions.

  18. Coordination of cassava starch to metal ions and thermolysis of resulting complexes

    Directory of Open Access Journals (Sweden)

    Piotr Tomasik

    2003-12-01

    Full Text Available Cassava starch formed Werner-type complexes with ions of metals from the transition groups. This was proven by conductivity and electron paramagnetic resonance measurements. The coordination of starch to central metal ions influenced the thermal decomposition of starch. As a rule complexes started to decompose at lower temperature than did starch. On the other hand, the decomposition proceeded at a lower rate than the decomposition of non-coordinated starch.

  19. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Science.gov (United States)

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  20. Beyond-Binary Arithmetic: Algorithms and VLSI Implementations

    OpenAIRE

    Aoki, Takafumi; Higuchi, Tatsuo

    2000-01-01

    Beyond-binary arithmetic algorithms are defined as a new class of computer arithmetic algorithms which employ non-binary data representations to achieve higher performances beyond those of conventional binary algorithms. This paper presents prominent examples of beyond-binary arithmetic algorithms: examples include (i) a high-radix redundant division algorithm without using lookup tables, (ii) a high-radix redundant CORDIC algorithm for fast vector rotation, and (iii) redundant complex arithm...

  1. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  2. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  3. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  4. The digi-neocognitron: a digital neocognitron neural network model for VLSI.

    Science.gov (United States)

    White, B A; Elmasry, M I

    1992-01-01

    One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

  5. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  6. A melt inclusion study of the Sudbury Igneous Complex (Ontario, Canada): preliminary results

    Science.gov (United States)

    Watts, Kathleen; Hanley, Jacob; Kontak, Daniel; Ames, Doreen

    2013-04-01

    The 1.85 Ga Sudbury Igneous Complex (SIC), Ontario, Canada, is an intrusive complex representing the crystallized melt sheet that formed within a large impact crater. The SIC has been extensively studied due to its rich endowment in magmatic sulfide ores (Ni-Cu-PGEs). The nature and origin of the SIC melt sheet and its subsequent evolution still remain controversial. In this study, analyses of primary melt inclusions hosted in cumulus apatite within three mafic units of the SIC (gabbro, norite and sublayer quartz diorite) are used to decipher the thermometric and chemical characteristics of the evolving melt sheet as it crystallized. Apatite-hosted melt inclusions commonly display a negative crystal shape, occur parallel to the c-axis, and often occur within a central growth zone, which suggest a primary origin. The compositions of coeval (co-entrapped) melt inclusions are distinct and may represent either the products of immiscibility (low or high temperature field; c.f. the Skaergaard Intrusion: Jakobsen et al., Geology, 2005), or a product of early, high-temperature, impact-generated emulsification (prior to and independent of crystallization of the melt sheet). The compositions of homogenized (1100-1200oC for 3 hrs) melt inclusions, determined by SEM-EDS and EMP analyses of opened, homogenized melt inclusions, equate to two distinct compositions: (1) Type-I are SiO2-rich, ranging from tonalitic to granodioritic in composition (60-70 wt% SiO2, up to 11 wt% FeO); and (2) Type-II are Fe-rich with syenogabbroic to essexitic to alkali gabbroic compositions (27-49 wt% SiO2, 16-44 wt% FeO). Trace element data, obtained by LA-ICPMS analyses of single inclusions and surrounding host apatite, are used to infer D values between apatite and the two melt types, and between the coexisting melt types. Apparent Dap-melt values for both Type-I and Type-II inclusions show that the REE, Sr, and Y are compatible in apatite, and As is weakly compatible or incompatible in apatite

  7. The complexity of Orion: an ALMA view. I. Data and first results

    Science.gov (United States)

    Pagani, L.; Favre, C.; Goldsmith, P. F.; Bergin, E. A.; Snell, R.; Melnick, G.

    2017-07-01

    Context. We wish to improve our understanding of the Orion central star formation region (Orion-KL) and disentangle its complexity. Aims: We collected data with ALMA during cycle 2 in 16 GHz of total bandwidth spread between 215.1 and 252.0 GHz with a typical sensitivity of 5 mJy/beam (2.3 mJy/beam from 233.4 to 234.4 GHz) and a typical beam size of 1.̋7 × 1.̋0 (average position angle of 89°). We produced a continuum map and studied the emission lines in nine remarkable infrared spots in the region including the hot core and the compact ridge, plus the recently discovered ethylene glycol peak. Methods: We present the data, and report the detection of several species not previously seen in Orion, including n- and i-propyl cyanide (C3H7CN), and the tentative detection of a number of other species including glycolaldehyde (CH2(OH)CHO). The first detections of gGg' ethylene glycol (gGg' (CH2OH)2) and of acetic acid (CH3COOH) in Orion are presented in a companion paper. We also report the possible detection of several vibrationally excited states of cyanoacetylene (HC3N), and of its 13C isotopologues. We were not able to detect the 16O18O line predicted by our detection of O2 with Herschel, due to blending with a nearby line of vibrationally excited ethyl cyanide. We do not confirm the tentative detection of hexatriynyl (C6H) and cyanohexatriyne (HC7N) reported previously, or of hydrogen peroxide (H2O2) emission. Results: We report a complex velocity structure only partially revealed before. Components as extreme as -7 and +19 km s-1 are detected inside the hot region. Thanks to different opacities of various velocity components, in some cases we can position these components along the line of sight. We propose that the systematically redshifted and blueshifted wings of several species observed in the northern part of the region are linked to the explosion that occurred 500 yr ago. The compact ridge, noticeably farther south displays extremely narrow lines ( 1 km s

  8. Effects of alkaline earth metal ion complexation on amino acid zwitterion stability: Results from infrared action spectroscopy

    NARCIS (Netherlands)

    Bush, M. F.; Oomens, J.; Saykally, R. J.; Williams, E. R.

    2008-01-01

    The structures of isolated alkaline earth metal cationized amino acids are investigated using infrared multiple photon dissociation (IRMPD) spectroscopy and theory. These results indicate that arginine, glutamine, proline, serine, and valine all adopt zwitterionic structures when complexed with diva

  9. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  10. Complex

    African Journals Online (AJOL)

    CLEMENT O BEWAJI

    Schiff bases and their complex compounds have been studied for their .... establishing coordination of the N–(2 – hydroxybenzyl) - L - α - valine Schiff base ..... (1967); “Spectrophotometric Identification of Organic Compounds”, Willey, New.

  11. Complex Values in Different Cultures: Some Research Results of Psycholinguistic Experiments with Russian and Swedish Students

    Science.gov (United States)

    Shabes, Vladimir; Troshchenkova, Ekaterina; Potapova, Tamara; Ivarsson, Lena; Damber, Ulla; Bostedt, Goran

    2012-01-01

    In the article on the basis of the psycholinguistic experimental data obtained in 2009-2010 from Russian and Swedish students, we consider internal features of several complex values ("Harmony", "Freedom", "Democracy", "Tolerance" and "Patriotism") and analyze their external systemic organization, taking into account both specificity of the two…

  12. Mental disturbances and perceived complexity of nursing care in medical inpatients : results from a European study

    NARCIS (Netherlands)

    De Jonge, P; Zomerdijk, MM; Huyse, FJ; Fink, P; Herzog, T; Lobo, A; Slaets, JPJ; Arolt, [No Value; Balogh, N; Cardoso, G; Rigatelli, M

    2001-01-01

    Aims and objectives. The relationship between mental disturbances-anxiety and depression, somatization and alcohol abuse-on admission to internal medicine units and perceived complexity of care as indicated by the nurse at discharge was studied. The goal Was to Study the utility of short screeners f

  13. Neuromorphic VLSI vision system for real-time texture segregation.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2008-10-01

    The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

  14. Preliminary results of modeling fluid flow in the Hellenic accretionary complex, Eastern Mediterranean

    Science.gov (United States)

    Kufner, S. K.; Huepers, A.; Kopf, A.; Wenzel, F.

    2011-12-01

    Being the fastest growing accretionary complex in the world, the Mediterranean Ridge provides an excellent possibility to study the linkage between tectonic activity and fluid transport processes at convergent plate margins. Abundant mud volcanism provides evidence for mass transfer from depth to the ocean floor. Seismic and bathymetric profiles indicate active deformation in the entire region. We combine seismic data, laboratory measurements of hydrological properties and finite element modeling to characterize fluid migration and fluid pressures in a 2D cross-section perpendicular to the Hellenic trench. The results might give constraints on mass fluxes and mechanics in the upper portion of the Hellenic subduction zone including the up-dip limit of the seismogenic zone. At the Hellenic subduction zone the African plate subducts obliquely toward the northeast beneath the Eurasian lithosphere. The current subduction rate is about 16mm/year. The plate convergence between Africa and Eurasia led to the accretion of a sedimentary prism since approx. 19Ma. The upper part of ocean sediments was scraped off and accreted to the overriding Eurasian plate whereas the lower part was underthrust. Nowadays, in the central part of the Mediterranean Ridge, the prism is pushed over its backstop, because of initiated continent-continent collision, whereas a thick sequence of oceanic sediments still enters the subducting system in the east near the Island of Crete. We used a numerical model of fluid flow to estimate fluid fluxes and fluid pressures in the shallow part of the Hellenic subduction zone. The modeled domain in the present study comprises the accreted sediment section and the underthrust sequence. The wedge geometry is obtained from seismic cross-sections and bathymetric maps. Input into the hydro-geological model include the compaction fluid source, the dehydration source and sediment permeability. The compaction source is obtained from porosity-depth relationships

  15. Complex Number Representation in RCBNS Form for Arithmetic Operations and Conversion of the Result into Standard Binary Form

    Directory of Open Access Journals (Sweden)

    Hatim Zaini

    2004-12-01

    Full Text Available paper introduces a novel method for complex number representation. The proposed Redundant Complex Binary Number System (RCBNS is developed by combining a Redundant Binary Number and a complex number in base (-1+j. Donald [1] and Walter Penny [2,3] represented complex numbers using base –j and (-1+j in the classified algorithmic models. A Redundant Complex Binary Number System consists of both real and imaginary-radix number systems that form a redundant integer digit set. This system is formed by using complex radix of (-1+j and a digit set of á= 3, where á assumes a value of -3, -2, -1, 0, 1, 2, 3. The arithmetic operations of complex numbers with this system treat the real and imaginary parts as one unit. The carry-free addition has the advantage of Redundancy in number representation in the arithmetic operations. Results of the arithmetic operations are in the RCBNS form. The two methods for conversion from the RCBNS form to the standard binary number form have been presented. In this paper the RCBNS reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

  16. Oceanic core complexes in the Philippine Sea: results from Japan's extended continental shelf mapping

    Science.gov (United States)

    Ohara, Y.; Yoshida, T.; Nishizawa, A.

    2013-12-01

    The United Nations Commission on the Limits of the Continental Shelf (CLCS) issued its recommendations on Japan's extended continental shelf in April 2012, confirming Japan's rights over the vast areas within the Philippine Sea and Pacific Plates. Japan submitted information on the limits of its continental shelf beyond the EEZ to the CLCS on November 2008, which was the result of 25 years of nation's continental shelf survey project since 1983, involving all of Japan's agency relevant to geosciences. The huge geological and geophysical data obtained through the project give the scientists unprecedented opportunity to study the geology and tectonics of the Philippine Sea and Pacific Plates. In this contribution, we show such an example from the Philippine Sea Plate, relevant to the global mid-ocean ridge problem. Oceanic core complexes (OCC) are dome-shaped bathymetric highs identified in mid-ocean ridges, interpreted as portions of the lower crust and/or upper mantle denuded via low-angle detachment faulting. OCCs are characterized morphologically by axis-normal striations (corrugations, or mullion structure) on the dome, and exposures of mantle peridotite and/or lower crustal gabbro. A strikingly giant OCC (named 'Godzilla Megamullion') was discovered in the Parece Vela Basin by the continental shelf survey project in 2001. Godzilla Megamullion is morphologically the largest OCC in the world, consisting mainly of fertile mantle peridotite along its entire length of over 125 km. Following its discovery in 2001, several academic cruises investigated the structure in detail, providing numerous important findings relevant to mid-ocean ridge tectono-magmatic processes and Philippine Sea evolution, including the slow- to ultraslow-spreading environment for denudation of the detachment fault (< 2.5 cm/y) and associated decreasing degree of partial melting of the peridotites towards the termination of Godzilla Megamullion. In addition to Godzilla Megamullion, several

  17. The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

    Institute of Scientific and Technical Information of China (English)

    骆祖莹; 闵应骅; 杨士元; 李晓维

    2002-01-01

    The authors theoretically describe the monotonic increasing relationship between averagepowers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, whichcan be fast computed, has been used as the evaluation criterion for the power of a practical circuit withdelay, which needs more computing time, in such fields as fast estimation for the average power and themaximum power, and fast optimization for the Iow test power. The authors propose a novel simulationapproach that uses delay-free power to compact a long input vector pair sequence into a short sequenceand then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. Incomparison with the traditional simulation approach that uses an un-compacted input sequence to simu-late the average (or maximum) power, experiment results demonstrate that in the field of fast estimationfor the average power, the present approach can be 6-10 times faster without significant loss in accuracy(less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach canbe 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast op-timization for the test power, the authors propose a novel delay-free power optimization approach for thetest power. Experiment results demonstrate that, in comparison with the approach of direct optimizationand the approach of Hamming distance optimization, this approach is of the highest optimization effi-ciency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% testpower).

  18. Principles of VLSI RTL design a practical guide

    CERN Document Server

    Churiwala, Sanjay; Gianfagna, Mike

    2011-01-01

    This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

  19. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    Science.gov (United States)

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763.

  20. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.

  1. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

    Science.gov (United States)

    Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

    2003-01-01

    Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

  2. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  3. “Bolshie Klyuchishi” (Ulyanovsk Oblast as a New Archaeological Complex: Preliminary Results

    Directory of Open Access Journals (Sweden)

    Vorobeva Elena E.

    2016-03-01

    Full Text Available The authors introduce for discussion materials of archaeological studies conducted by the team of the Volga Archaeological Expedition of the Mari State University in Ulyanovsk Oblast of the Russian Federation in 2010. Two of the studied archaeological sites seem to be most interesting: they are situated near Bolshie Klyuchishi village (Ulyanovsk District, Ulyanovsk Oblast. Archaeological materials collected during the excavations of these settlements have a very broad time span, which allows suggesting that Bolshie Klyuchishi is a multilayered archaeological complex. Both settlements yielded the Srubnaya culture handmade ceramics of 16th – 13th centuries BC. Moreover, Bolshie Klyuchishi-7 contained items of iron and slag, and Bolshie Klyuchishi-8 yielded sherds of 13th – 14th centuries wheel- made Bulgarian ceramics.

  4. Crosstalk Model and Estimation Formula for VLSI Interconnect Wires

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from the S field to the time domain. The exact 3 order coefficients in S field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.

  5. VLSI Neural Networks Help To Compress Video Signals

    Science.gov (United States)

    Fang, Wai-Chi; Sheu, Bing J.

    1996-01-01

    Advanced analog/digital electronic system for compression of video signals incorporates artificial neural networks. Performs motion-estimation and image-data-compression processing. Effectively eliminates temporal and spatial redundancies of sequences of video images; processes video image data, retaining only nonredundant parts to be transmitted, then transmits resulting data stream in form of efficient code. Reduces bandwidth and storage requirements for transmission and recording of video signal.

  6. Cascaded VLSI neural network architecture for on-line learning

    Science.gov (United States)

    Duong, Tuan A. (Inventor); Daud, Taher (Inventor); Thakoor, Anilkumar P. (Inventor)

    1995-01-01

    High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

  7. VLSI synthesis of digital application specific neural networks

    Science.gov (United States)

    Beagles, Grant; Winters, Kel

    1991-01-01

    Neural networks tend to fall into two general categories: (1) software simulations, or (2) custom hardware that must be trained. The scope of this project is the merger of these two classifications into a system whereby a software model of a network is trained to perform a specific task and the results used to synthesize a standard cell realization of the network using automated tools.

  8. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  9. VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.

    Science.gov (United States)

    Hoang, Linh; Yang, Zhi; Liu, Wentai

    2009-01-01

    An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.

  10. VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.

    Science.gov (United States)

    Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V

    2007-03-01

    A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

  11. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  12. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  13. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  14. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  15. Real-time motion detection using an analog VLSI zero-crossing chip

    Science.gov (United States)

    Bair, Wyeth; Koch, Christof

    1991-07-01

    The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.

  16. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  17. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  18. A VLSI optimal constructive algorithm for classification problems

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V. [Los Alamos National Lab., NM (United States); Draghici, S.; Sethi, I.K. [Wayne State Univ., Detroit, MI (United States)

    1997-10-01

    If neural networks are to be used on a large scale, they have to be implemented in hardware. However, the cost of the hardware implementation is critically sensitive to factors like the precision used for the weights, the total number of bits of information and the maximum fan-in used in the network. This paper presents a version of the Constraint Based Decomposition training algorithm which is able to produce networks using limited precision integer weights and units with limited fan-in. The algorithm is tested on the 2-spiral problem and the results are compared with other existing algorithms.

  19. Efficient Interconnection Schemes for VLSI and Parallel Computation

    Science.gov (United States)

    1989-08-01

    MTTl/LjCS/TR-456 NOOO14-87-K-0825 and NOOO14-86-K-0593 6a. NAME OF "ERFORMING ORGANIZATION I6b. OFFICE SYMBOL 7a. NAME OF MONITORING ORGANIZATION HIIT ...generally abstracted away, and the simulation results are expressed in terms of the running time for the chosen message routing algorithm. Chapter 4...messages on fat-trees. The running times of these algorithms are expressed as a function of the load factor of a set of messages to be routed, the load

  20. VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

    Science.gov (United States)

    Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip

    2014-01-01

    Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

  1. The Complex Outgassing of Comets and the Resulting Coma, a Direct Simulation Monte-Carlo Approach

    Science.gov (United States)

    Fougere, Nicolas

    During its journey, when a comet gets within a few astronomical units of the Sun, solar heating liberates gases and dust from its icy nucleus forming a rarefied cometary atmosphere, the so-called coma. This tenuous atmosphere can expand to distances up to millions of kilometers representing orders of magnitude larger than the nucleus size. Most of the practical cases of coma studies involve the consideration of rarefied gas flows under non-LTE conditions where the hydrodynamics approach is not valid. Then, the use of kinetic methods is required to properly study the physics of the cometary coma. The Direct Simulation Monte-Carlo (DSMC) method is the method of choice to solve the Boltzmann equation, giving the opportunity to study the cometary atmosphere from the inner coma where collisions dominate and is in thermodynamic equilibrium to the outer coma where densities are lower and free flow conditions are verified. While previous studies of the coma used direct sublimation from the nucleus for spherically symmetric 1D models, or 2D models with a day/night asymmetry, recent observations of comets showed the existence of local small source areas such as jets, and extended sources via sublimating icy grains, that must be included into cometary models for a realistic representation of the physics of the coma. In this work, we present, for the first time, 1D, 2D, and 3D models that can take into account the full effects of conditions with more complex sources of gas with jets and/or icy grains. Moreover, an innovative work in a full 3D description of the cometary coma using a kinetic method with a realistic nucleus and outgassing is demonstrated. While most of the physical models used in this study had already been developed, they are included in one self-consistent coma model for the first time. The inclusion of complex cometary outgassing processes represents the state-of-the-art of cometary coma modeling. This provides invaluable information about the coma by

  2. A VLSI decomposition of the deBruijn graph

    Science.gov (United States)

    Collins, Oliver; Dolinar, Sam; Mceliece, Robert; Pollara, Fabrizio

    1992-01-01

    The nth order deBruijn graph Bn is the state diagram for an n-stage binary shift register. It is a directed graph with 2 to the n vertices, each labeled with an n-bit binary string, and 2 to the n+1 edges, each labeled with an (n+1)-bit binary string. It is shown that Bn can be built by appropriately connecting together with extra edges many isomorphic copies of a fixed graph, which is called a building block for Bn. The efficiency of such a building block is refined as the fraction of the edges of Bn which are present in the copies of the building block. It is then shown that for any alpha less than 1, there exists a graph which is a building block for Bn of efficiency greater than alpha for all sufficiently large n. The results are illustrated by showing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder which will be used on the Galileo mission.

  3. Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Directory of Open Access Journals (Sweden)

    Danielle S Bassett

    2010-04-01

    Full Text Available Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.

  4. High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug

    2006-07-24

    Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

  5. VLSI Research

    Science.gov (United States)

    1984-04-01

    massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly

  6. Spatially averaging cross-wind sensors and numerical-model results for nocturnal drainage winds in complex terrain

    Energy Technology Data Exchange (ETDEWEB)

    Porch, W.M.; Lange, R.

    1982-11-01

    Recent studies in The Geysers region of Northern California have concentrated on drainage wind effects on tracer transport and diffusion in complex terrain, as part of the Atmospheric Studies in Complex Terrain (ASCOT) project. These studies combined tracer measurements, conventional tower and remote sensing meteorological measurements, and numerical wind field transport and diffusion models. One part of the meteorological measurement support used eight optical cross-path wind sensors across the principle air drainage valleys. These sensors had varying optical path lengths within the drainage layer of approx. 300 m to 3 km. Results of this study indicate that the combination of spatially averaged cross-path optical wind sensor and conventional tower mounted cup-vane anemometer data into a numerical plume transport and diffusion model for complex terrain has provided useful results. The most important of these results is an independent measure of wind data on a spatial scale compatible with necessarily large grid scales in numerical wind field models with topography. This allows assessment of terrain associated exposure problems for tower anemometers in complex terrain. The optical cross wind data can be used to compare necessary averaging times, and spatial distribution of point sensors and provide verification data to improve the logistics of instrument placement in combination with numerical models.

  7. Impulse propagation over a complex site: a comparison of experimental results and numerical predictions.

    Science.gov (United States)

    Dragna, Didier; Blanc-Benon, Philippe; Poisson, Franck

    2014-03-01

    Results from outdoor acoustic measurements performed in a railway site near Reims in France in May 2010 are compared to those obtained from a finite-difference time-domain solver of the linearized Euler equations. During the experiments, the ground profile and the different ground surface impedances were determined. Meteorological measurements were also performed to deduce mean vertical profiles of wind and temperature. An alarm pistol was used as a source of impulse signals and three microphones were located along a propagation path. The various measured parameters are introduced as input data into the numerical solver. In the frequency domain, the numerical results are in good accordance with the measurements up to a frequency of 2 kHz. In the time domain, except a time shift, the predicted waveforms match the measured waveforms with a close agreement.

  8. Tribofilm Formation As a Result of Complex Interaction at the Tool/Chip Interface during Cutting

    Directory of Open Access Journals (Sweden)

    German S. Fox-Rabinovich

    2014-07-01

    Full Text Available Tribofilms are dynamic structures that form at the interface during frictional sliding. These films play a significant role in friction control, particularly under heavy loaded/high temperature conditions, such as those found at the cutting tool/chip interface. The thermodynamic aspects of tribofilm formation are discussed here. Thermodynamic analysis of entropy production during friction shows that there are two types of tribofilms that affect the wear behavior of a cutting tool: (1 tribofilms forming as a result of the surface modification of the cutting tools with further tribo-oxidation; and (2 tribofilms that form as a result of material transfer from the contacting frictional body (the workpiece during the tool/chip interaction. Experimental examples are presented, outlining the beneficial role of both types of tribofilms.

  9. Algorithmic and complexity results for decompositions of biological networks into monotone subsystems.

    Science.gov (United States)

    DasGupta, Bhaskar; Enciso, German Andres; Sontag, Eduardo; Zhang, Yi

    2007-01-01

    A useful approach to the mathematical analysis of large-scale biological networks is based upon their decompositions into monotone dynamical systems. This paper deals with two computational problems associated to finding decompositions which are optimal in an appropriate sense. In graph-theoretic language, the problems can be recast in terms of maximal sign-consistent subgraphs. The theoretical results include polynomial-time approximation algorithms as well as constant-ratio inapproximability results. One of the algorithms, which has a worst-case guarantee of 87.9% from optimality, is based on the semidefinite programming relaxation approach of Goemans-Williamson [Goemans, M., Williamson, D., 1995. Improved approximation algorithms for maximum cut and satisfiability problems using semidefinite programming. J. ACM 42 (6), 1115-1145]. The algorithm was implemented and tested on a Drosophila segmentation network and an Epidermal Growth Factor Receptor pathway model, and it was found to perform close to optimally.

  10. Long-term results of complex left ventricular reconstruction surgery: case report.

    Science.gov (United States)

    Letsou, George V; Forrester, Matthew; Frazier, O H

    2011-01-01

    Left ventricular reconstruction is advocated as a surgical option for patients with severe congestive heart failure. Despite initial enthusiasm for this procedure, reports of long-term results are sparse. Herein, we describe a particularly gratifying case of left ventricular reconstruction in a 43-year-old man, who continues to have excellent left ventricular function 10 years postoperatively. This approach may be a reasonable alternative to cardiac transplantation in patients who lack other treatment options.

  11. Promising results after single-stage reconstruction of the nipple and areola complex

    DEFF Research Database (Denmark)

    Børsen-Koch, Mikkel; Bille, Camilla; Thomsen, Jørn B

    2013-01-01

    a technique based on a local flap for reconstruction of the nipple in combination with immediate intradermal tattooing for reconstruction of the areola. Results: We reviewed the outcome of 22 cases of women who had simple single-stage reconstruction over a period of one year. We found no major and only two...... minor complications including one case of partial flap necrosis and one case of infection. Only three patients needed additional tattooing after a three-month period. The cosmetic outcome was satisfactory and none of the patients needed corrective procedures. The mean procedure time for unilateral...

  12. Low-complexity systolic architecture for inversion

    Institute of Scientific and Technical Information of China (English)

    Yuan Danshou; Rong Mengtian

    2006-01-01

    A modified extended binary Euclid's algorithm which is more regularly iterative for computing an inversion in GF(2m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O(m), latency of 5m-2, and throughput of 1/m. Compared with other serial systolic architectures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design.

  13. New magnetotelluric soundings in the Mt. Somma-Vesuvius volcanic complex. Preliminary results

    Energy Technology Data Exchange (ETDEWEB)

    Manzella, A.; Volpi, G. [Consiglio Nazionale delle Ricerche, Pisa (Italy). Ist. Internazionale per le Ricerche Geotermiche; Zaja, A. [Padua Univ., Padua (Italy). Dipt. di Geologia, Paleontologia e Geofisica

    2000-04-01

    The work reports the preliminary results of ten magnetotelluric (MT) soundings recorded in single-site mode above the Mt. Somma-Vesuvius volcanic area in 1997. The quality of data decreases going further from the caldera and approaching the sources of electromagnetic incoherent noise such as villages, antennas and repeaters. After a very accurate data analysis, the apparent resistivity and phase curves were interpreted with a 1D modelling instead a 2D one as it seems a more appropriate interpretative approach looking at the morphology of the curves and taking into account the 3 D geological conditions of the area. The results show an extended conductive structure at a depth of 0.3-1.2 km. It could be connected with a change in the physico-chemical characteristics of the volcano-sedimentary define the response MT curves for sites above this particular volcanic structure. This approach seems to be very interesting in view of specific interpretative targets, such as dimension and position of the magma chamber, when planning future MT surveys.

  14. Sorption of phosphate onto calcite; results from batch experiments and surface complexation modeling

    DEFF Research Database (Denmark)

    Sø, Helle Ugilt; Postma, Dieke; Jakobsen, Rasmus;

    2011-01-01

    The adsorption of phosphate onto calcite was studied in a series of batch experiments. To avoid the precipitation of phosphate-containing minerals the experiments were conducted using a short reaction time (3h) and low concentrations of phosphate (⩽50μM). Sorption of phosphate on calcite...... was studied in 11 different calcite-equilibrated solutions that varied in pH, PCO2, ionic strength and activity of Ca2+, CO32- and HCO3-. Our results show strong sorption of phosphate onto calcite. The kinetics of phosphate sorption onto calcite are fast; adsorption is complete within 2–3h while desorption...... of a high degree of super-saturation with respect to hydroxyapatite (SIHAP⩽7.83). The amount of phosphate adsorbed varied with the solution composition, in particular, adsorption increases as the CO32- activity decreases (at constant pH) and as pH increases (at constant CO32- activity). The primary effect...

  15. Fistulotomy and sphincter reconstruction in the treatment of complex fistula-in-ano: long-term clinical and manometric results.

    Science.gov (United States)

    Arroyo, Antonio; Pérez-Legaz, Juan; Moya, Pedro; Armañanzas, Laura; Lacueva, Javier; Pérez-Vicente, Francisco; Candela, Fernando; Calpena, Rafael

    2012-05-01

    To evaluate the long-term clinical and manometric results of fistulotomy and sphincter reconstruction for the treatment of complex fistula-in-ano. Complex fistula-in-ano is difficult to treat due to the occurrence of postoperative anal incontinence and the high rate of recurrence. Seventy patients who were diagnosed with complex fistula-in-ano and underwent fistulotomy and sphincter reconstruction between October 2000 and October 2006 were analyzed in the present study. Preoperative assessment included physical examination, anorectal manometry, and anal endosonography. Appointments were scheduled every 6 months during the first and second year of treatment and every 2 years thereafter. Recurrence and incontinence were evaluated during each visit. Continence was assessed according to the Wexner continence grading scale. Anal manometry was performed 3 and 12 months after treatment and every 2 years thereafter. Anal endosonography was conducted 6 months after treatment. Fistulas were classified as medium-high trans-sphincteric in 64 patients (91.42%) and were recurrent in 22 patients (32%). Before surgery, 22 patients (32%) reported fecal incontinence, which improved after surgery in 15 cases (70%), from 6.75 to 1.88 (P Fistulotomy with sphincter reconstruction is an effective technique for the treatment of complex fistula-in-ano. Continence and anal manometry results were improved in incontinent patients and were not jeopardized in continent ones. Fistulotomy with sphincter reconstruction is an especially suitable technique for incontinent patients with recurrent fistulas.

  16. Inhibition of parvalbumin-expressing interneurons results in complex behavioral changes.

    Science.gov (United States)

    Brown, J A; Ramikie, T S; Schmidt, M J; Báldi, R; Garbett, K; Everheart, M G; Warren, L E; Gellért, L; Horváth, S; Patel, S; Mirnics, Károly

    2015-12-01

    Reduced expression of the Gad1 gene-encoded 67-kDa protein isoform of glutamic acid decarboxylase (GAD67) is a hallmark of schizophrenia. GAD67 downregulation occurs in multiple interneuronal sub-populations, including the parvalbumin-positive (PVALB+) cells. To investigate the role of the PV-positive GABAergic interneurons in behavioral and molecular processes, we knocked down the Gad1 transcript using a microRNA engineered to target specifically Gad1 mRNA under the control of Pvalb bacterial artificial chromosome. Verification of construct expression was performed by immunohistochemistry. Follow-up electrophysiological studies revealed a significant reduction in γ-aminobutyric acid (GABA) release probability without alterations in postsynaptic membrane properties or changes in glutamatergic release probability in the prefrontal cortex pyramidal neurons. Behavioral characterization of our transgenic (Tg) mice uncovered that the Pvalb/Gad1 Tg mice have pronounced sensorimotor gating deficits, increased novelty-seeking and reduced fear extinction. Furthermore, NMDA (N-methyl-d-aspartate) receptor antagonism by ketamine had an opposing dose-dependent effect, suggesting that the differential dosage of ketamine might have divergent effects on behavioral processes. All behavioral studies were validated using a second cohort of animals. Our results suggest that reduction of GABAergic transmission from PVALB+ interneurons primarily impacts behavioral domains related to fear and novelty seeking and that these alterations might be related to the behavioral phenotype observed in schizophrenia.

  17. Design and commissioning test results for the hypervelocity launcher research complex battery power supply

    Science.gov (United States)

    Cornette, James B.; Sterrett, John D.; Lippert, Jack R.; Williams, Robert W.

    1989-08-01

    The preliminary design of the battery power supply (BPS) was reported to the 6th IEEE Pulsed Power conference. In 1987, the final design was completed, assembled, and sequentially verified during approximately 1750 operational verification tests. These experiments consisted of single string verifications at 1000 amperes to a system discharge of 2,150,000 amperes. Final system design is very similar to the preliminary design previously presented. System fabrication is complete and at the present time consists of 858, 16 battery series strings resulting in 13,728 operational batteries. The final switching design has evolved into several levels of redundancy at varying current levels. These include 36 pneumatic, 100,000 ampere switches that control 24, 16 battery strings in parallel. These switches are used for the primary make and break of system current to charge the inductor. There are also 18 pneumatic crowbar switches at the 24 string level that are used to short the inductor from the BPS prior to system opening. At the string level there are 2000 ampere dc contactors that are used as a secondary current break and to pre-set the BPS in the appropriate parallel/series configuration prior to a discharge sequence. Explosively driven opening and closing switches are also employed at the interface junction to any Hypervelocity launcher test article.

  18. Algorithmic and Complexity Results for Cutting Planes Derived from Maximal Lattice-Free Convex Sets

    CERN Document Server

    Basu, Amitabh; Köppe, Matthias

    2011-01-01

    We study a mixed integer linear program with m integer variables and k non-negative continuous variables in the form of the relaxation of the corner polyhedron that was introduced by Andersen, Louveaux, Weismantel and Wolsey [Inequalities from two rows of a simplex tableau, Proc. IPCO 2007, LNCS, vol. 4513, Springer, pp. 1--15]. We describe the facets of this mixed integer linear program via the extreme points of a well-defined polyhedron. We then utilize this description to give polynomial time algorithms to derive valid inequalities with optimal l_p norm for arbitrary, but fixed m. For the case of m=2, we give a refinement and a new proof of a characterization of the facets by Cornuejols and Margot [On the facets of mixed integer programs with two integer variables and two constraints, Math. Programming 120 (2009), 429--456]. The key point of our approach is that the conditions are much more explicit and can be tested in a more direct manner, removing the need for a reduction algorithm. These results allow ...

  19. New magnetotelluric soundings in the Mt. Somma-Vesuvius volcanic complex: preliminary results

    Directory of Open Access Journals (Sweden)

    A. Zaja

    2000-06-01

    Full Text Available During 1997 ten magnetotelluric (MT soundings were recorded in single-site mode above the Mt. Somma-Vesuvius volcanic area. A first campaign of MT measurements was carried out, during spring, by the researchers of the University of Padua with their MSPM acquisition system. During autumn, the researchers of the International Institute of Geothermal Research (CNR Pisa with their Phoenix equipment performed a second campaign. A teach site, the horizontal components of the electrical and magnetic fields were recorded in the frequency band between 300-0.003 Hz. The MSPM system could record signals up to the frequency of 800 Hz. Data were recorded at one common site with both the different equipments to verify the compatibility of the two different acquisition systems. The soundings over the area of the volcano's caldera show a continuous morphology of the apparent resistivity and phase curves with small error bars: it means a good correlation between the orthogonal electrical and magnetic fields. The quality of data decreases going further from the caldera and approaching the sources of electromagnetic incoherent noise such as villages, antennas and repeaters. After a very accurate data analysis, the apparent resistivity and phase curves were interpreted with a 1D modelling instead a 2D one as it seems a more appropriate interpretative approach looking at the morphology of the curves and taking into account the 3D geological conditions of the area. The results show an extended conductive structure at a depth of 0.3-1.2 km. It could be connected with a change in the physico-chemical characteristics of the volcano-sedimentary cover (alteration paragenesis and possible hydrothermalism. A 3D MT forward modelling was then used to define the response MT curves for sites above this particular volcanic structure. This approach seems to be very interesting in view of specific interpretative targets, such as dimension and position of the magma chamber, when

  20. Effect of Semi-quantitative Culture Results from Complex Host Surgical Wounds on Dehiscence Rates.

    Science.gov (United States)

    Elmarsafi, Tammer; Garwood, Caitlin S; Steinberg, John S; Evans, Karen K; Attinger, Christopher E; Kim, Paul J

    2017-01-16

    The primary aim of this study was to determine the effect of positive bacterial cultures at the time of closure on dehiscence rates. Pre and post-débridement wound cultures from patients undergoing serial surgical débridement of infected wounds were compared with outcomes 30 days postoperatively. One-hundred patients were enrolled; 35 were excluded for incomplete culture data. Sixty-five patients were evaluated for species counts, including Coagulase negative Staphylococcus, and semi-quantitative culture data for each débridement. The post-débridement cultures on the date of closure had no growth in 42 patients (64.6%) of which 6 dehisced (14.3%), and 36 remained closed; with no statistically significant difference in dehiscence rates (p=0.0664). Pre-débridement cultures from the 1(st) débridement of the 65 patients showed 8 patients had no growth, 29 grew 1 species, 19 grew 2 species, and 9 had 3-5 species. There was a reduction in the number of species and improvement of semi-quantitative cultures with each subsequent débridement. The dehiscence rate for those who had 2 débridements (n=42) was 21.4% at 30 day follow-up and 21.7% in those who had 3 débridements (n=23). The number of débridements had no statistical significance on dehiscence rates. The presence of Coagulase negative Staphylococcus (CoNS) on the day of closure was a statistically significant risk for dehiscence within 30 days (p=0.0091) postoperatively. This data demonstrates: (1) positive post-débridement cultures (scant/rare, growth in enrichment broth) at the time of closure did not affect overall dehiscence rates (p=0.0664), (2) the number of species and semi-quantitiative culture results both improved with each subsequent débridement, (3) the number of surgical débridement did not influence post-closure dehiscence rates. (4) Positive cultures containing Coagulase negative Staphylococcus at the time of closure is a risk factor for dehiscence (p=0.0091). This article is protected by

  1. Mapping Microbial Populations Relative to Sites of Ongoing Serpentinization: Results from the Tablelands Ophiolite Complex, Canada

    Science.gov (United States)

    Schrenk, M. O.; Brazelton, W. J.; Woodruff, Q.; Szponar, N.; Morrill, P. L.

    2010-12-01

    assemblages consisting of diverse taxa at neutral pH background sites. Terrestrial serpentinite-hosted microbial ecosystems with their accessibility, their low phylogenetic diversity, and limited range of energetic resources provide an excellent opportunity to explore the interplay between geochemical energy and life and to elucidate the native serpentinite subsurface biosphere. From the perspective of Mars exploration, studies of serpentinite ecosystems provide the opportunity to pinpoint the organisms and physiological adaptations specifically associated with serpentinization and to directly measure their geochemical impacts. Both of these results will inform modeling and life detection efforts of the Martian subsurface environment.

  2. Glutathione deficiency in Gclm null mice results in complex I inhibition and dopamine depletion following paraquat administration.

    Science.gov (United States)

    Liang, Li-Ping; Kavanagh, Terrance J; Patel, Manisha

    2013-08-01

    Depletion of glutathione has been shown to occur in autopsied brains of patients with Parkinson's disease (PD) and in animal models of PD. The goal of this study was to determine whether chronic glutathione (GSH) deficiency per se resulted in complex I inhibition and/or dopamine depletion and whether these indices were further potentiated by aging or administration of paraquat, a redox-cycling herbicide that produces a PD-like neurodegeneration model in rodents (Brooks, A. I., Chadwick, C. A., Gelbard, H. A., Cory-Slechta, D. A., and Federoff, H. J. [1999]. Paraquat elicited neurobehavioral syndrome caused by dopaminergic neuron loss. Brain Res. 823, 1-10; McCormack, A. L., Thiruchelvam, M., Manning-Bog, A. B., Thiffault, C., Langston, J. W., Cory-Slechta, D. A., and Di Monte, D. A. [2002]. Environmental risk factors and Parkinson's disease: Selective degeneration of nigral dopaminergic neurons caused by the herbicide paraquat. Neurobiol. Dis. 10, 119-127.) Deletion of the rate-limiting GSH synthesis gene, glutamate-cysteine ligase modifier subunit (Gclm), leads to significantly lower GSH concentrations in all tissues including brain. Gclm null (Gclm (-/-)) mice provide a model of prolonged GSH depletion to explore the relationship between GSH, complex I inhibition, and dopamine loss in vivo. Despite ~60% depletion of brain GSH in Gclm (-/-) mice of ages 3-5 or 14-16 months, striatal complex I activity, dopamine levels, 3-nitrotyroine/tyrosine ratios, aconitase activity, and CoASH remained unchanged. Administration of paraquat (10mg/kg, twice/week, 3 weeks) to 3- to 5-month-old Gclm (-/-) mice resulted in significantly decreased aconitase activity, complex I activity, and dopamine levels but not in 3- to 5-month-old Gclm (+/+) mice. Furthermore, paraquat-induced inhibition of complex I and aconitase activities in Gclm (-/-) mice was observed in the striatum but not in the cortex. The results suggest that chronic deficiency of GSH in Gclm (-/-) mice was not

  3. Complex ultrasound diagnostic assessment of the results of neoadjuvant chemotherapy for locally advanced cervical cancer (Stages IIB–IIIB

    Directory of Open Access Journals (Sweden)

    L. A. Ashrafyan

    2015-01-01

    Full Text Available Background. Current complex ultrasound diagnosis using novel imaging techniques can assess, to a high accuracy, different tumor parameters during neoadjuvant chemotherapy (NCT for locally advanced cervical cancer (CC (Stages IIB–IIB. This assessment is very important and necessary to define further treatment policy.Materials and methods. A total of 199 patients diagnosed with Stages IIB–IIIB CC, including 60 patients with Stage IIB (T2bN0M0, 4 with Stage IIIА (T3aN0M0, and 135 with Stage IIIВ (T2bN1M0, T3aN1M0, T3bN0–1M0 (according to the International Federationof Gynecology and Obstetrics (FIGO classification, who received NCT at Stage 1 of treatment, were examined. Complex ultrasound study was conducted before treatment initiation and after each NCT cycle. The therapeutic pathomorphism of a tumor was evaluated in surgically treated patients.Results. The criteria have been determined for evaluating the efficiency of NCT for locally advanced CC, which are based on current ultrasonographic techniques including B-mode, Doppler ultrasound (power, spectral, three-dimensional ones, as well as on the results of therapeutic pathomorphism.Conclusion. The criteria for evaluating the efficiency of NCT for CC should be based on current complex ultrasonographic techniques.

  4. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  5. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  6. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Science.gov (United States)

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  7. A compact 3D VLSI classifier using bagging threshold network ensembles.

    Science.gov (United States)

    Bermak, A; Martinez, D

    2003-01-01

    A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

  8. A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.

    Science.gov (United States)

    Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V

    2011-04-01

    Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.

  9. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  10. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  11. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  12. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  13. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  14. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  15. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  16. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Directory of Open Access Journals (Sweden)

    McEwan Alistair

    2003-01-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  17. Advances in VLSI testing at MultiGb per second rates

    Directory of Open Access Journals (Sweden)

    Topisirović Dragan

    2005-01-01

    Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

  18. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  19. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  20. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  1. Structural plasticity: how intermetallics deform themselves in response to chemical pressure, and the complex structures that result.

    Science.gov (United States)

    Berns, Veronica M; Fredrickson, Daniel C

    2014-10-06

    Interfaces between periodic domains play a crucial role in the properties of metallic materials, as is vividly illustrated by the way in which the familiar malleability of many metals arises from the formation and migration of dislocations. In complex intermetallics, such interfaces can occur as an integral part of the ground-state crystal structure, rather than as defects, resulting in such marvels as the NaCd2 structure (whose giant cubic unit cell contains more than 1000 atoms). However, the sources of the periodic interfaces in intermetallics remain mysterious, unlike the dislocations in simple metals, which can be associated with the exertion of physical stresses. In this Article, we propose and explore the concept of structural plasticity, the hypothesis that interfaces in complex intermetallic structures similarly result from stresses, but ones that are inherent in a defect-free parent structure, rather than being externally applied. Using DFT-chemical pressure analysis, we show how the complex structures of Ca2Ag7 (Yb2Ag7 type), Ca14Cd51 (Gd14Ag51 type), and the 1/1 Tsai-type quasicrystal approximant CaCd6 (YCd6 type) can all be traced to large negative pressures around the Ca atoms of a common progenitor structure, the CaCu5 type with its simple hexagonal 6-atom unit cell. Two structural paths are found by which the compounds provide relief to the Ca atoms' negative pressures: a Ca-rich pathway, where lower coordination numbers are achieved through defects eliminating transition metal (TM) atoms from the structure; and a TM-rich path, along which the addition of spacer Cd atoms provides the Ca coordination environments greater independence from each other as they contract. The common origins of these structures in the presence of stresses within a single parent structure highlights the diverse paths by which intermetallics can cope with competing interactions, and the role that structural plasticity may play in navigating this diversity.

  2. The treatment of complex proximal humeral fractures: analysis of the results of 55 cases treated with PHILOS plate.

    Science.gov (United States)

    Fattoretto, D; Borgo, A; Iacobellis, C

    2016-08-01

    Complex proximal humerus fractures are often difficult to treat. Their frequency is high, especially in the elderly, and their treatment is still controversial. The aim of this study was to analyze the clinical and radiological results achieved by patients with complex proximal humerus fractures, treated with PHILOS plate only. A cohort of 55 patients was selected. The mean age was 63.4 (range 33-89), while the mean follow-up time was 21.5 months (range 6-75). Clinical outcome was evaluated with the "Constant-Murley shoulder score." All the informations about the presence of complications were gathered, and radiological images were used to calculate the head-shaft angle. The overall mean Constant score was 61.93 ± 18.59, the Individual CS was 70 ± 20 % and the Relative CS was 83 ± 23 %. No significant differences were found between fractures Neer 3 and Neer 4 and between the surgical approaches (delta-split vs. delto-pectoral). Six patients had a fracture with dislocation, seven patients (12.7 %) had complications while in four patients a head-shaft angle beyond the normal range was found. Osteosynthesis with PHILOS plate is stable in the greater part of the cases, and it allows an earlier rehabilitation and so a good functional result, which could be compromised by a prolonged immobilization. Therefore, PHILOS plate is a good option for the treatment of complex proximal humerus fractures.

  3. The First Results of the Photometric Observation of Selected Asteroids on KT-50 Telescope of Mobitel Complex of RI MAO

    Directory of Open Access Journals (Sweden)

    Pomazan, A.V.

    2017-01-01

    Full Text Available The first results of the photometric observations of asteroids performed on the telescope KT-50 of Mobitel complex (SRI MAO during 2016 are presented in the paper. Asteroids were selected based on the infrared survey NEOWISE, moving objects catalog SDSS MOC-3 and MPC database. Selected asteroids have a relatively high albedo (pV>0.2 and are located in the Outer Main Belt (semi-major axis a>0.28a.u.. The observations were made using filter close to the Rc standard band of Cousins system. Standard deviations of the instrumental differential magnitude measurements were in the range of 0.01m-0.03m for a 10m-15.5m reference stars. The light curve based on the results of the differential aperture photometry was obtained from long series of observations of the asteroid (2144 Marietta.

  4. Classification of correlated patterns with a configurable analog VLSI neural network of spiking neurons and self-regulating plastic synapses.

    Science.gov (United States)

    Giulioni, Massimilian; Pannunzi, Mario; Badoni, Davide; Dante, Vittorio; Del Giudice, Paolo

    2009-11-01

    We describe the implementation and illustrate the learning performance of an analog VLSI network of 32 integrate-and-fire neurons with spike-frequency adaptation and 2016 Hebbian bistable spike-driven stochastic synapses, endowed with a self-regulating plasticity mechanism, which avoids unnecessary synaptic changes. The synaptic matrix can be flexibly configured and provides both recurrent and external connectivity with address-event representation compliant devices. We demonstrate a marked improvement in the efficiency of the network in classifying correlated patterns, owing to the self-regulating mechanism.

  5. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  6. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  7. 基于GPU的VLSI的DRC加速系统%DRC Accelerated System of VLSI Based on GPU

    Institute of Scientific and Technical Information of China (English)

    池凤彬; 潘日华; 陈扉; 赵冬晖

    2007-01-01

    在超大规模集成电路(VLSI)设计流程中,设计规则检查(DRC)是关键一环.多年来,设计人员为DRC设计了许多硬件加速的方法,但是都局限于成本等诸多原因而不能得到推广.因此提出了基于GPU平台的DRC方法,大幅提高了DRC效率.

  8. Mutations in Two Genes Encoding Different Subunits of a Receptor Signaling Complex Result in an Identical Disease Phenotype

    Science.gov (United States)

    Paloneva, Juha; Manninen, Tuula; Christman, Grant; Hovanes, Karine; Mandelin, Jami; Adolfsson, Rolf; Bianchin, Marino; Bird, Thomas; Miranda, Roxana; Salmaggi, Andrea; Tranebjærg, Lisbeth; Konttinen, Yrjö; Peltonen, Leena

    2002-01-01

    Polycystic lipomembranous osteodysplasia with sclerosing leukoencephalopathy (PLOSL), also known as “Nasu-Hakola disease,” is a globally distributed recessively inherited disease leading to death during the 5th decade of life and is characterized by early-onset progressive dementia and bone cysts. Elsewhere, we have identified PLOSL mutations in TYROBP (DAP12), which codes for a membrane receptor component in natural-killer and myeloid cells, and also have identified genetic heterogeneity in PLOSL, with some patients carrying no mutations in TYROBP. Here we complete the molecular pathology of PLOSL by identifying TREM2 as the second PLOSL gene. TREM2 forms a receptor signaling complex with TYROBP and triggers activation of the immune responses in macrophages and dendritic cells. Patients with PLOSL have no defects in cell-mediated immunity, suggesting a remarkable capacity of the human immune system to compensate for the inactive TYROBP-mediated activation pathway. Our data imply that the TYROBP-mediated signaling pathway plays a significant role in human brain and bone tissue and provide an interesting example of how mutations in two different subunits of a multisubunit receptor complex result in an identical human disease phenotype. PMID:12080485

  9. Results from 10 Years of a CBT Pain Self-Management Outpatient Program for Complex Chronic Conditions

    Directory of Open Access Journals (Sweden)

    Kathryn A. Boschen

    2016-01-01

    Full Text Available Background. Traditional unimodal interventions may be insufficient for treating complex pain, as they do not address cognitive and behavioural contributors to pain. Cognitive Behavioural Therapy (CBT and physical exercise (PE are empirically supported treatments that can reduce pain and improve quality of life. Objectives. To examine the outcomes of a pain self-management outpatient program based on CBT and PE at a rehabilitation hospital in Toronto, Ontario. Methods. The pain management group (PMG consisted of 20 sessions over 10 weeks. The intervention consisted of four components: education, cognitive behavioural skills, exercise, and self-management strategies. Outcome measures included the sensory, affective, and intensity of pain experience, depression, anxiety, pain disability, active and passive coping style, and general health functioning. Results. From 2002 to 2011, 36 PMGs were run. In total, 311 patients entered the program and 214 completed it. Paired t-tests showed significant pre- to posttreatment improvements in all outcomes measured. Patient outcomes did not differ according to the number or type of diagnoses. Both before and after treatment, women reported more active coping than men. Discussion. The PMGs improved pain self-management for patients with complex pain. Future research should use a randomized controlled design to better understand the outcomes of PMGs.

  10. Deletion of potD, encoding a putative spermidine-binding protein, results in a complex phenotype in Legionella pneumophila.

    Science.gov (United States)

    Nasrallah, Gheyath K; Abdelhady, Hany; Tompkins, Nicholas P; Carson, Kaitlyn R; Garduño, Rafael A

    2014-07-01

    L. pneumophila is an intracellular pathogen that replicates in a membrane-bound compartment known as the Legionella-containing vacuole (LCV). We previously observed that the polyamine spermidine, produced by host cells or added exogenously, enhances the intracellular growth of L. pneumophila. To study this enhancing effect and determine whether polyamines are used as nutrients, we deleted potD from L. pneumophila strain JR32. The gene potD encodes a spermidine-binding protein that in other bacteria is essential for the function of the PotABCD polyamine transporter. Deletion of potD did not affect L. pneumophila growth in vitro in the presence or absence of spermidine and putrescine, suggesting that PotD plays a redundant or no role in polyamine uptake. However, deletion of potD resulted in a puzzlingly complex phenotype that included defects in L. pneumophila's ability to form filaments, tolerate Na(+), associate with macrophages and amoeba, recruit host vesicles to the LCV, and initiate intracellular growth. Moreover, the ΔpotD mutant was completely unable to grow in L929 cells treated with a pharmacological inhibitor of spermidine synthesis. These complex and disparate effects suggest that the L. pneumophila potD encodes either: (i) a multifunctional protein, (ii) a protein that interacts with, or regulates a, multifunctional protein, or (iii) a protein that contributes (directly or indirectly) to a regulatory network. Protein function studies with the L. pneumophila PotD protein are thus warranted.

  11. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  12. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  13. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  14. Estimation of global daily irradiation in complex topography zones using digital elevation models and meteosat images: Comparison of the results

    Energy Technology Data Exchange (ETDEWEB)

    Martinez-Durban, M. [Dpto. de Lenguajes y Computacion, Universidad de Almeria, 04120 Almeria (Spain); Zarzalejo, L.F.; Polo, J. [Dpto. de Energia, CIEMAT, 28040 Madrid (Spain); Bosch, J.L.; Rosiek, S.; Batlles, F.J. [Dpto. Fisica Aplicada, Universidad de Almeria, 04120 Almeria (Spain)

    2009-09-15

    The knowledge of the solar irradiation in a certain place is fundamental for the suitable location of solar systems, both thermal and photovoltaic. On the local scale, the topography is the most important modulating factor of the solar irradiation on the surface. In this work the global daily irradiation is estimated concerning various sky conditions, in zones of complex topography. In order to estimate the global daily irradiation we use a methodology based on a Digital Terrain Model (DTM), on one hand making use of pyranometer measurements and on the other hand utilizing satellite images. We underline that DTM application employing pyranometer measurements produces better results than estimation using satellite images, though accuracy of the same order is obtained in both cases for Root Mean Square Error (RMSE) and Mean Bias Error (MBE). (author)

  15. CR2-mediated activation of the complement alternative pathway results in formation of membrane attack complexes on human B lymphocytes

    DEFF Research Database (Denmark)

    Nielsen, C H; Marquart, H V; Prodinger, W M;

    2001-01-01

    Normal human B lymphocytes activate the alternative pathway of complement via complement receptor type 2 (CR2, CD21), that binds hydrolysed C3 (iC3) and thereby promotes the formation of a membrane-bound C3 convertase. We have investigated whether this might lead to the generation of a C5...... convertase and consequent formation of membrane attack complexes (MAC). Deposition of C3 fragments and MAC was assessed on human peripheral B lymphocytes in the presence of 30% autologous serum containing 4.4 mM MgCl2/20 mM EGTA, which abrogates the classical pathway of complement without affecting...... the alternative pathway. Blockade of the CR2 ligand-binding site with the monoclonal antibody FE8 resulted in 56 +/- 13% and 71 +/- 9% inhibition of the C3-fragment and MAC deposition, respectively, whereas the monoclonal antibody HB135, directed against an irrelevant CR2 epitope, had no effect. Blockade...

  16. A Motion Adaptive De-interlacing Technique and VLSI Architecture%一种运动自适应去隔行技术及其VLSI结构

    Institute of Scientific and Technical Information of China (English)

    普玉伟; 叶兵; 曾德瑞; 蒋特林

    2011-01-01

    An efficient motion adaptive de-interlacing is proposed in this paper. The mixing pixels is classified to fast motion, slow motion or static region according to the motion detection of the same parity field, the corresponding interpolation method is used in different motion region. The edge detection uses the improved ELA algorithm which overcomes the traditional ELA algorithm's deficiency at processing horizontal edge, and the edge is preserved effectively. Compared with motion compensated algorithm, our proposed algorithm required lower computational complexity, and it is easier to implement by VLSI .The experiment shows that the proposed algorithm gains better de-interlacing and high peak signal-to-noise ratio.%提出一种有效的运动自适应去隔行算法.该算法通过对同极性的相邻场进行运动检测,把插值点所处的区域分为快速运动区域、慢速运动区域和静止区域,对不同的区域采用不同的插值算法.在边缘检测方面,采用改进型ELA算法克服了传统的ELA算法处理水平边缘方面的不足,使边缘得到有效保护.与运动补偿算法相比,该算法计算复杂度较低,易于VLSI实现.实验结果显示,该算法取得了良好的去隔行效果和较高的峰值信噪比.

  17. [Immunologic study of subacute infectious endocarditis through the search for circulating immune complexes. Preliminary results apropos of 13 cases].

    Science.gov (United States)

    Herreman, G; Godeau, P; Cabane, J; Digeon, M; Laver, M; Bach, J F

    1975-10-04

    The detection of circulating immune complexes by precipitation by polyethylene glycol represents a valuable technique of study in sub-acute bacterial endocarditis. In a series of 13 patients, this measurement was carried out, confirming the quasi-constant presence of circulating immune complexes in active S.B.E. This might be of diagnostic value in forms with negative blood culture and, further, make it possible, subsequently, to find the antigen responsible by dissociation of the circulating immune complexes.

  18. VLSI based FFT Processor with Improvement in Computation Speed and Area Reduction

    Directory of Open Access Journals (Sweden)

    M.Sheik Mohamed

    2013-06-01

    Full Text Available In this paper, a modular approach is presented to develop parallel pipelined architectures for the fast Fourier transform (FFT processor. The new pipelined FFT architecture has the advantage of underutilized hardware based on the complex conjugate of final stage results without increasing the hardware complexity. The operating frequency of the new architecture can be decreased that in turn reduces the power consumption. A comparison of area and computing time are drawn between the new design and the previous architectures. The new structure is synthesized using Xilinx ISE and simulated using ModelSim Starter Edition. The designed FFT algorithm is realized in our processor to reduce the number of complex computations.

  19. Deletion of flbA results in increased secretome complexity and reduced secretion heterogeneity in colonies of Aspergillus niger.

    Science.gov (United States)

    Krijgsheld, Pauline; Nitsche, Benjamin M; Post, Harm; Levin, Ana M; Müller, Wally H; Heck, Albert J R; Ram, Arthur F J; Altelaar, A F Maarten; Wösten, Han A B

    2013-04-05

    Aspergillus niger is a cell factory for the production of enzymes. This fungus secretes proteins in the central part and at the periphery of the colony. The sporulating zone of the colony overlapped with the nonsecreting subperipheral zone, indicating that sporulation inhibits protein secretion. Indeed, strain ΔflbA that is affected early in the sporulation program secreted proteins throughout the colony. In contrast, the ΔbrlA strain that initiates but not completes sporulation did not show altered spatial secretion. The secretome of 5 concentric zones of xylose-grown ΔflbA colonies was assessed by quantitative proteomics. In total 138 proteins with a signal sequence for secretion were identified in the medium of ΔflbA colonies. Of these, 18 proteins had never been reported to be part of the secretome of A. niger, while 101 proteins had previously not been identified in the culture medium of xylose-grown wild type colonies. Taken together, inactivation of flbA results in spatial changes in secretion and in a more complex secretome. The latter may be explained by the fact that strain ΔflbA has a thinner cell wall compared to the wild type, enabling efficient release of proteins. These results are of interest to improve A. niger as a cell factory.

  20. In Vitro Interactions between 17β-Estradiol and DNA Result in Formation of the Hormone-DNA Complexes

    Directory of Open Access Journals (Sweden)

    Zbynek Heger

    2014-07-01

    Full Text Available Beyond the role of 17β-estradiol (E2 in reproduction and during the menstrual cycle, it has been shown to modulate numerous physiological processes such as cell proliferation, apoptosis, inflammation and ion transport in many tissues. The pathways in which estrogens affect an organism have been partially described, although many questions still exist regarding estrogens’ interaction with biomacromolecules. Hence, the present study showed the interaction of four oligonucleotides (17, 20, 24 and/or 38-mer with E2. The strength of these interactions was evaluated using optical methods, showing that the interaction is influenced by three major factors, namely: oligonucleotide length, E2 concentration and interaction time. In addition, the denaturation phenomenon of DNA revealed that the binding of E2 leads to destabilization of hydrogen bonds between the nitrogenous bases of DNA strands resulting in a decrease of their melting temperatures (Tm. To obtain a more detailed insight into these interactions, MALDI-TOF mass spectrometry was employed. This study revealed that E2 with DNA forms non-covalent physical complexes, observed as the mass shifts for app. 270 Da (Mr of E2 to higher molecular masses. Taken together, our results indicate that E2 can affect biomacromolecules, as circulating oligonucleotides, which can trigger mutations, leading to various unwanted effects.

  1. 超大规模集成电路可调试性设计综述%Survey of Design-for-Debug of VLSI

    Institute of Scientific and Technical Information of China (English)

    钱诚; 沈海华; 陈天石; 陈云霁

    2012-01-01

    随着硬件复杂度的不断提高和并行软件调试的需求不断增长,可调试性设计已经成为集成电路设计中的重要内容.一方面,仅靠传统的硅前验证已经无法保证现代超大规模复杂集成电路设计验证的质量,因此作为硅后验证重要支撑技术的可调试性设计日渐成为大规模集成电路设计领域的研究热点.另一方面,并行程序的调试非常困难,很多细微的bug无法直接用传统的单步、断点等方法进行调试,如果没有专门的硬件支持,需要耗费极大的人力和物力.全面分析了现有的可调试性设计,在此基础上归纳总结了可调试性设计技术的主要研究方向并介绍了各个方向的研究进展,深入探讨了可调试性结构设计研究中的热点问题及其产生根源,给出了可调试性结构设计领域的发展趋势.%Design-for-debug (DFD) has become an important feature of modern VLSI. On the one hand, traditional pre-silicon verification methods are not sufficient to enssure the quality of modern complex VLSI designs, thus employing DFD to facilitate post-silicon verification has attracted wide interests from both academia and industry; on the other hand, debugging parallel program is a worldwide difficult problem, which cries out for DFD hardware supports. In this paper, we analyze the existing structures of DFD comprehensively and introduce different fields of DFD for debugging hardware and software. These fields contain various kinds of DFD infrastructures, such as the DFD infrastructure for the pipe line of processor, the system-on-chips (SOC) and the networks on multi-cores processor. We also introduce the recent researches on how to design the DFD infrastructures with certain processor architecture and how to use the DFD infrastructures to solve the debug problems in these different fields. The topologic of the whole infrastructure, the hardware design of components, the methods of analyzing signals, the

  2. Knowledge-based remote sensing of complex objects: Recognition of spatial patterns resulting from natural hydrocarbon seepages

    NARCIS (Netherlands)

    Werff, Harald Michael Arnout van der

    2006-01-01

    This thesis outlines the development of four image processing algorithms that combine spectral and spatial information for the detection of complex objects on the Earth' surface by remote sensing. Complex objects are objects that are composed of several smaller parts. These smaller parts may not be

  3. High-contrast imager for complex aperture telescopes (HiCAT): 3. first lab results with wavefront control

    Science.gov (United States)

    N'Diaye, Mamadou; Mazoyer, Johan; Choquet, Élodie; Pueyo, Laurent; Perrin, Marshall D.; Egron, Sylvain; Leboulleux, Lucie; Levecq, Olivier; Carlotti, Alexis; Long, Chris A.; Lajoie, Rachel; Soummer, Rémi

    2015-09-01

    HiCAT is a high-contrast imaging testbed designed to provide complete solutions in wavefront sensing, control and starlight suppression with complex aperture telescopes. The pupil geometry of such observatories includes primary mirror segmentation, central obstruction, and spider vanes, which make the direct imaging of habitable worlds very challenging. The testbed alignment was completed in the summer of 2014, exceeding specifications with a total wavefront error of 12nm rms over a 18mm pupil. The installation of two deformable mirrors for wavefront control is to be completed in the winter of 2015. In this communication, we report on the first testbed results using a classical Lyot coronagraph. We also present the coronagraph design for HiCAT geometry, based on our recent development of Apodized Pupil Lyot Coronagraph (APLC) with shaped-pupil type optimizations. These new APLC-type solutions using two-dimensional shaped-pupil apodizer render the system quasi-insensitive to jitter and low-order aberrations, while improving the performance in terms of inner working angle, bandpass and contrast over a classical APLC.

  4. Preliminary Results of Helical Tomotherapy in Patients with Complex-Shaped Meningiomas Close to the Optic Pathway

    Energy Technology Data Exchange (ETDEWEB)

    Schiappacasse, Luis, E-mail: lschiap@gmail.com; Cendales, Ricardo; Sallabanda, Kita; Schnitman, Franco; Samblas, Jose

    2011-01-01

    Meningiomas are the most common benign intracranial tumor. Meningiomas close to the optic pathway represent a treatment challenge both for surgery and radiotherapy. The aim of this article is to describe early results of helical tomotherapy treatment in complex-shaped meningiomas close to the optic pathway. Twenty-eight patients were consecutively treated. All patients were immobilized with a thermoplastic head mask and planned with the aid of a magnetic resonance imaging-computed tomography fusion. All treatments included daily image guidance. Pretreatment symptoms and acute toxicity were recorded. Median age was 57.5 years, and 92.8% patients had Eastern Cooperative Oncology Group performance status scale {<=}1. The most common localizations were the sella turcica, followed by the cavernous sinus and the sphenoid. The most common symptoms were derived from cranial nerve deficits. Tomotherapy was administered as primary treatment in 35.7% of patients, as an adjuvant treatment in 32.4%, and as a rescue treatment after postsurgical progression in 32.1% patients. Most patients were either inoperable or Simpson IV. Total dose varied between 5000 and 5400 cGy; fractionation varied between 180 and 200 cGy. Median dose to the planning target volume was 51.7 Gy (range, 50.2-55.9 Gy). Median coverage index was 0.89 (range, 0.18-0.97). Median homogeneity index was 1.05 (range, 1-1.12). Acute transient toxicity was grade 1 and included headache in 35.7% patients, ocular pain/dryness in 28.5%, and radiation dermatitis in 25%. Thus far, with a maximal follow-up of 3 years, no late effects have been seen and all patients have a radiological stabilization of the disease. Helical tomotherapy offered a safe and effective therapeutic alternative for patients with inoperable or subtotally resected complex-shaped meningiomas close to the optic pathway. Acceptable coverage and homogeneity indexes were achieved with appropriate values for maximal doses delivered to the eyes, lenses

  5. Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments

    Science.gov (United States)

    Loinaz, Marc Joseph

    1995-11-01

    This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-μm CMOS technology. Each channel includes a wideband amplifier, a

  6. Multiheteromacrocycles that Complex Metal Ions. Ninth Progress Report (includes results of last three years), 1 May 1980 -- 30 April 1983

    Science.gov (United States)

    Cram, D. J.

    1982-09-15

    The overall objective of this research is to design, synthesize, and evaluate cyclic and polycyclic host organic compounds for the abilities to complex and lipophilize guest metal ions, their complexes, and their clusters. Host organic compounds consist of strategically placed solvating, coordinating, and ion-pairing sites tied together by covalent bonds through hydrocarbon units around cavities shaped to be occupied by guest metal ions, or by metal ions plus their ligands. Specificity in complexation is sought by matching the following properties of host and guest: cavity and metal ion sizes; geometric arrangements of binding sites; numbers of binding sites; characters of binding sites; and valences. The hope is to synthesize new classes of compounds useful in the separation of metal ions, their complexes, and their clusters.

  7. Optimization of assured result in dynamical model of management of innovation process in the enterprise of agricultural production complex

    Directory of Open Access Journals (Sweden)

    Andrey Fedorovich Shorikov

    2014-03-01

    Full Text Available Research and the problem solution of management of innovative process at the enterprise (UIPP demands the development of the dynamic economic-mathematical model considering the control action, uncontrolled parameters (risks, modeling errors, etc. and deficit of information. At the same time, the existing approaches to the solution of similar problems are generally based on the static models and use the device of stochastic modeling, which requires knowledge of probabilistic characteristics of key parameters of the model and special conditions on realization of considered process. It is significant that the strict conditions are necessary for the use of the stochastic modeling, but in practice it is not possible. In the article, it is offered to use the determined approach for the modeling and solution of an initial problems in the form of dynamic problem of program minimax control (optimization of the guaranteed result IPP on the set timepoint taking into account risks. At the same time, the risks in the system of UIPP are understood as the factors, which influence negatively or catastrophically on the results of the processes considered in the system. To solve the problem of minimax program control of IPP at risks, the method to implement the solutions of the final number of the problem of linear and convex mathematical programming and a problem of discrete optimization is offered. The offered method gives the chance to develop the effective numerical procedures allowing to realize computer modeling of dynamics considered problem, to create program minimax control of IPP, and to receive the optimum guaranteed result. The results presented in the article are based on the research [2, 3, 7-10] and can be used for economic-mathematical modeling and the solution of other problems of data forecasting process optimization and management at the deficit of information and at risks, and also for development of the corresponding software and

  8. Prograde garnet growth along complex P T t paths: results from numerical experiments on polyphase garnet from the Wölz Complex (Austroalpine basement)

    Science.gov (United States)

    Gaidies, F.; de Capitani, C.; Abart, R.; Schuster, R.

    2008-06-01

    Garnet in metapelites from the Wölz Complex of the Austroalpine crystalline basement east of the Tauern Window characteristically consists of two growth phases, which preserve a comprehensive record of the geothermal history during polymetamorphism. From numerical modelling of garnet formation, detailed information on the pressure temperature time ( P T t) evolution during prograde metamorphism is obtained. In that respect, the combined influences of chemical fractionation associated with garnet growth, modification of the original growth zoning through intragranular diffusion and the nucleation history on the chemical zoning of garnet as P and T change during growth are considered. The concentric chemical zoning observed in garnet and the homogenous rock matrix, which is devoid of chemical segregation, render the simulation of garnet growth through successive equilibrium states reliable. Whereas the first growth phase of garnet was formed at isobaric conditions of ˜3.8 kbar at low heating/cooling rates, the second growth phase grew along a Barrovian P T path marked with a thermal peak of ˜625°C at ˜10 kbar and a maximum in P of ˜10.4 kbar at ˜610°C. For the heating rate during the growth of the second phase of garnet, average rates faster than 50°C Ma-1 are obtained. From geochronological investigations the first growth phase of garnet from the Wölz Complex pertains to the Permian metamorphic event. The second growth phase grew in the course of Eo-Alpine metamorphism during the Cretaceous.

  9. An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

    Directory of Open Access Journals (Sweden)

    Tze-Yun Sung

    2010-01-01

    Full Text Available Discrete Cosine transform (DCT and inverse DCT (IDCT have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array and SoC (system on chip. The linear-array DCT/IDCT processor with the computation complexity O(5N/8 and hardware complexity O(5N/8 is fully pipelined and scalable for variable-length DCT/IDCT computations.

  10. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  11. Temperature sensitive influenza A virus genome replication results from low thermal stability of polymerase-cRNA complexes

    Directory of Open Access Journals (Sweden)

    Tiley Laurence S

    2006-08-01

    Full Text Available Abstract Background The RNA-dependent RNA polymerase of Influenza A virus is a determinant of viral pathogenicity and host range that is responsible for transcribing and replicating the negative sense segmented viral genome (vRNA. Transcription produces capped and polyadenylated mRNAs whereas genome replication involves the synthesis of an alternative plus-sense transcript (cRNA with unmodified termini that is copied back to vRNA. Viral mRNA transcription predominates at early stages of viral infection, while later, negative sense genome replication is favoured. However, the "switch" that regulates the transition from transcription to replication is poorly understood. Results We show that temperature strongly affects the balance between plus and minus-sense RNA synthesis with high temperature causing a large decrease in vRNA accumulation, a moderate decrease in cRNA levels but (depending on genome segment either increased or unchanged levels of mRNA. We found no evidence implicating cellular heat shock protein activity in this effect despite the known association of hsp70 and hsp90 with viral polymerase components. Temperature-shift experiments indicated that polymerase synthesised at 41°C maintained transcriptional activity even though genome replication failed. Reduced polymerase association with viral RNA was seen in vivo and in confirmation of this, in vitro binding assays showed that temperature increased the rate of dissociation of polymerase from both positive and negative sense promoters. However, the interaction of polymerase with the cRNA promoter was particularly heat labile, showing rapid dissociation even at 37°C. This suggested that vRNA synthesis fails at elevated temperatures because the polymerase does not bind the promoter. In support of this hypothesis, a mutant cRNA promoter with vRNA-like sequence elements supported vRNA synthesis at higher temperatures than the wild-type promoter. Conclusion The differential stability of

  12. VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme

    Directory of Open Access Journals (Sweden)

    G. Seetharaman

    2008-01-01

    Full Text Available A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP. A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25–1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15–1.39 at the cost of an increase in the number of registers by a factor of 1.78–2.73, increase in the number of LEs by a factor of 1.11–1.32 and it increases the clock routing complexity.

  13. The first dating results for gabbro of the dunite-clinopyroxenite-gabbro complex of the Chistop massif (North Urals)

    Science.gov (United States)

    Petrova, G. A.; Ronkin, Yu. L.; Lvov, P. A.; Maslov, A. V.

    2017-08-01

    The first data on the Late Riphean age by U-Pb and Sm-Nd analysis (≥922 ± 14 and 686 ± 19 Ma, respectively) were obtained for rocks of the dunite-clinopyroxenite-gabbro complex of the Chistop massif in the Patinum-bearing Belt of the Urals. These data allow one to assume that the formation of the Ural paleoocean probably started immediately after the break-up of Rodinia.

  14. Impact of Complex Orography on Wake Development: Simulation Results for the Planned WindForS Test Site

    Science.gov (United States)

    Lutz, Thorsten; Schulz, Christoph; Letzgus, Patrick; Rettenmeier, Andreas

    2017-05-01

    In Southern Germany a test site will be erected in complex terrain. The purpose is to enable detailed scientific studies of terrain impact on the characteristics of two research wind turbines and to demonstrate new technologies. Within preparatory studies an appropriate site was identified and examined by field tests and numerical studies in more detail. The present paper summarizes CFD analyses on the impact of the local test site orography on the wake development of a virtual wind turbine. The effects of the orography are identified by comparative simulations for the same turbine using comparative wind situation in flat terrain.

  15. Final results from the ''investigation of design aspects and design options for wind turbines operating in complex terrain environments'' project

    Energy Technology Data Exchange (ETDEWEB)

    Fragoulis, A.N. [SPA Hellas Engineering S.A., Attiki (Greece); Markkilde, P.S.; Voutsinas, S.; Cuerva, A.; Winkelaar, D.; Ganander, H.

    1999-07-01

    Complex terrain sites are a major and critical market for wind energy development and knowledge regarding the wind structure and the WT response to it is insufficient. The paper presents the work and the final results of the COMTERID project (JOR3-CT95-0033), the successor and the follow-up of MOUNTURB, which was undertaken within the JOULE-III program by a number of National European R and D institutes and universities (CRES, NTUA, CIEMAT, RISO, ECN), consultants, designers and manufacturers (TG, LTL, VESTAS, ECOTECNIA, NWP) with the main objective to identify and quantify the complex terrain environment and its effects in the operation of WTs. The work identified and quantified the complex terrain wind structure conditions which were found to be different from the flat terrain standards and through the development of a parameter identification methodology it identified, evaluated and quantified the machine's performance sensitivity to the Wind-WT parameters. Increased turbulence was found in the vertical and lateral directions on all complex terrain sites studied and smaller length scales compared to the flat terrain standards. These parameters along with the difference in coherence and the small Weibull shape factors encountered (less than 2) are responsible for the increased fatigue loading that WTs experience at complex terrain environments. The project results indicate directions for new machine concepts, specifically for complex terrain operation, that will be both technically and economically efficient. (author)

  16. Synthesis and characterisation of estrogenic carriers for cytotoxic Pt(II) fragments: biological activity of the resulting complexes.

    Science.gov (United States)

    Gabano, Elisabetta; Cassino, Claudio; Bonetti, Samuele; Prandi, Cristina; Colangelo, Donato; Ghiglia, Annalisa; Osella, Domenico

    2005-10-07

    This paper describes the synthesis and the spectroscopic characterisation of cis-dichloro[N-(4-(17alpha-ethynylestradiolyl)-benzyl)-ethylenediamine]platinum(II) and cis-diamino[2-(4-(17alpha-ethynylestradiolyl)-benzoylamino)-malonato]platinum(II). These complexes were synthesised in good yield according to multi-step procedures based on the classical and non-classical Sonogashira coupling reaction, respectively. These compounds retain an acceptable degree of relative binding affinity (RBA) for the alpha form of estrogen receptor. Combined treatment of breast cancer cell lines, namely hormone-sensitive MCF-7 and hormone-insensitive MDA-MB-231 cell lines, indicates that these compounds maintain agonistic activity so that the potential advantage in vehiculation of the cytotoxic moiety by means of the receptor system is counteracted by the proliferative effect of the estrogenic component of the entire molecule, especially at low concentrations.

  17. Results of treatment of infertility in men by complex acetyl-L-carnitine and L-carnitine

    Directory of Open Access Journals (Sweden)

    V. V. Mikhaylichenko

    2014-12-01

    Full Text Available 100 patients with various forms of patozoospermii were randomly divided equally into 2 groups. First group of patients administered complex of acetyl-L-carnitine and L-carnitine (SpermAktin ® and alpha-tocopherol acetate for 3 months, in the second group of patients was carried out single-agent alpha-tocopherol acetate duration of 3 months. Ejaculate volume, viscosity and pH of seminal plasma, the concentration, motility and morphology were evaluated after 1.5 and 3 months of starting treatment. In the first group of infertile men showed a significant improvement in the quality and quantity of semen compared with the second patient group.

  18. Results of treatment of infertility in men by complex acetyl-L-carnitine and L-carnitine

    Directory of Open Access Journals (Sweden)

    V. V. Mikhaylichenko

    2014-01-01

    Full Text Available 100 patients with various forms of patozoospermii were randomly divided equally into 2 groups. First group of patients administered complex of acetyl-L-carnitine and L-carnitine (SpermAktin ® and alpha-tocopherol acetate for 3 months, in the second group of patients was carried out single-agent alpha-tocopherol acetate duration of 3 months. Ejaculate volume, viscosity and pH of seminal plasma, the concentration, motility and morphology were evaluated after 1.5 and 3 months of starting treatment. In the first group of infertile men showed a significant improvement in the quality and quantity of semen compared with the second patient group.

  19. High-contrast imager for Complex Aperture Telescopes (HiCAT): 2. Design overview and first light results

    CERN Document Server

    N'Diaye, Mamadou; Egron, Sylvain; Pueyo, Laurent; Leboulleux, Lucie; Levecq, Olivier; Perrin, Marshall D; Elliot, Erin; Wallace, J Kent; Hugot, Emmanuel; Marcos, Michel; Ferrari, Marc; Long, Chris A; Anderson, Rachel; DiFelice, Audrey; Soummer, Rémi

    2014-01-01

    We present a new high-contrast imaging testbed designed to provide complete solutions in wavefront sensing, control and starlight suppression with complex aperture telescopes. The testbed was designed to enable a wide range of studies of the effects of such telescope geometries, with primary mirror segmentation, central obstruction, and spiders. The associated diffraction features in the point spread function make high-contrast imaging more challenging. In particular the testbed will be compatible with both AFTA-like and ATLAST-like aperture shapes, respectively on-axis monolithic, and on-axis segmented telescopes. The testbed optical design was developed using a novel approach to define the layout and surface error requirements to minimize amplitude-induced errors at the target contrast level performance. In this communication we compare the as-built surface errors for each optic to their specifications based on end-to-end Fresnel modeling of the testbed. We also report on the testbed optical and optomechani...

  20. Metallogenic Series Related to Permian Mafic Complex in North Xinjiang: Post-collisional Stage or Mantle Plume Result?

    Institute of Scientific and Technical Information of China (English)

    WANG Yuwang; WANG Jingbin; WANG Lijuan; LONG Lingli

    2008-01-01

    There are four deposit types related to a Permian mafic complex in northern Xinjiang, i.e.,copper-nickel sulfide deposit, vanadic titanomagnetite deposit, magnetite (-cobalt) deposit and Cu-Ni-VTiFe composite deposit. The deposits are distributed spanning tectonic units with dose andconsecutive metallogenic ages. A transitional deposit type can occur among the end-member deposits.Trace elements of host rocks show that they can derive from similar source area. Hence, theyconstitute a particular metallogenic series related to a mafic-ultramafic complex that is also a symbolseries of the post-collisional stage of the Central Asia Metallogenic Province (CAMP). Themetallogenic ages of the series are between 260 Ma and 300 Ma throughout the Permian. Unlikemineralization from a mantle plume, the metallogenic period of this series spans at least 40 Ma.Compared with related deposits of the Emeishan mantle plume, the North Xinjiang series has asimilar ore-forming element assemblage but has preferably developed Cu-Ni sulfide deposits ratherthan vanadic titanomagnetite deposits. In concomitance with this series, North Xinjiang area hasdeveloped a set of syntectonic Au-Cu-Mo metailogenic series related to a felsic volcanic-intrusivecomplex, which might indicate that there is no direct relationship with mantle plume activity. Fromearly to late, i.e., the sequence of copper-nickel sulfide to magnetite (-cobalt) to vanadictitanomagnetite deposit, the host rock series evolves from mafic-ultramafic and tholeiite series tomafic and alkalic series, the ∑REE content tends to increase with increasing of REE fractionation, andsome of the trace elements (particularly LIL) also show an increasing tendency. The aboveevolutionary regularity possibly reflects a course where the magma source deepens and thermalinterface moves down, energy gradually exhausts, and neo-continentai crust forming in the post-collision stage tends to stabilize.

  1. Soil moisture monitoring results at the radioactive waste management complex of the Idaho National Engineering Laboratory, FY-1993

    Energy Technology Data Exchange (ETDEWEB)

    McElroy, D.L.

    1993-11-01

    In FY-1993, two tasks were performed for the Radioactive Waste Management Complex (RWMC) Low Level Waste Performance Assessment to estimate net infiltration from rain and snow at the Subsurface Disposal Area (SDA) and provide soil moisture data for hydrologic model calibration. The first task was to calibrate the neutron probe to convert neutron count data to soil moisture contents. A calibration equation was developed and applied to four years of neutron probe monitoring data (November 1986 to November 1990) at W02 and W06 to provide soil moisture estimates for that period. The second task was to monitor the soils at two neutron probe access tubes (W02 and W06) located in the SDA of the RWMC with a neutron probe to estimate soil moisture contents. FY-1993 monitoring indicated net infiltration varied widely across the SDA. Less than 1.2 in. of water drained into the underlying basalts near W02 in 1993. In contrast, an estimated 10.9 in. of water moved through the surficial sediments and into the underlying basalts at neutron probe access tube W06. Net infiltration estimates from the November 1986 to November 1990 neutron probe monitoring data are critical to predictive contaminant transport modeling and should be calculated and compared to the FY-1993 net infiltration estimates. In addition, plans are underway to expand the current neutron probe monitoring system in the SDA to address the variability in net infiltration across the SDA.

  2. Barriers to and facilitators of implementing complex workplace dietary interventions: process evaluation results of a cluster controlled trial.

    Science.gov (United States)

    Fitzgerald, Sarah; Geaney, Fiona; Kelly, Clare; McHugh, Sheena; Perry, Ivan J

    2016-04-21

    Ambiguity exists regarding the effectiveness of workplace dietary interventions. Rigorous process evaluation is vital to understand this uncertainty. This study was conducted as part of the Food Choice at Work trial which assessed the comparative effectiveness of a workplace environmental dietary modification intervention and an educational intervention both alone and in combination versus a control workplace. Effectiveness was assessed in terms of employees' dietary intakes, nutrition knowledge and health status in four large manufacturing workplaces. The study aimed to examine barriers to and facilitators of implementing complex workplace interventions, from the perspectives of key workplace stakeholders and researchers involved in implementation. A detailed process evaluation monitored and evaluated intervention implementation. Interviews were conducted at baseline (27 interviews) and at 7-9 month follow-up (27 interviews) with a purposive sample of workplace stakeholders (managers and participating employees). Topic guides explored factors which facilitated or impeded implementation. Researchers involved in recruitment and data collection participated in focus groups at baseline and at 7-9 month follow-up to explore their perceptions of intervention implementation. Data were imported into NVivo software and analysed using a thematic framework approach. Four major themes emerged; perceived benefits of participation, negotiation and flexibility of the implementation team, viability and intensity of interventions and workplace structures and cultures. The latter three themes either positively or negatively affected implementation, depending on context. The implementation team included managers involved in coordinating and delivering the interventions and the researchers who collected data and delivered intervention elements. Stakeholders' perceptions of the benefits of participating, which facilitated implementation, included managers' desire to improve company

  3. Long-Term Use of Everolimus in Patients with Tuberous Sclerosis Complex: Final Results from the EXIST-1 Study.

    Directory of Open Access Journals (Sweden)

    David N Franz

    Full Text Available Everolimus, a mammalian target of rapamycin (mTOR inhibitor, has demonstrated efficacy in treating subependymal giant cell astrocytomas (SEGAs and other manifestations of tuberous sclerosis complex (TSC. However, long-term use of mTOR inhibitors might be necessary. This analysis explored long-term efficacy and safety of everolimus from the conclusion of the EXIST-1 study (NCT00789828.EXIST-1 was an international, prospective, double-blind, placebo-controlled phase 3 trial examining everolimus in patients with new or growing TSC-related SEGA. After a double-blind core phase, all remaining patients could receive everolimus in a long-term, open-label extension. Everolimus was initiated at a dose (4.5 mg/m2/day titrated to a target blood trough of 5-15 ng/mL. SEGA response rate (primary end point was defined as the proportion of patients achieving confirmed ≥50% reduction in the sum volume of target SEGA lesions from baseline in the absence of worsening nontarget SEGA lesions, new target SEGA lesions, and new or worsening hydrocephalus. Of 111 patients (median age, 9.5 years who received ≥1 dose of everolimus (median duration, 47.1 months, 57.7% (95% confidence interval [CI], 47.9-67.0 achieved SEGA response. Of 41 patients with target renal angiomyolipomas at baseline, 30 (73.2% achieved renal angiomyolipoma response. In 105 patients with ≥1 skin lesion at baseline, skin lesion response rate was 58.1%. Incidence of adverse events (AEs was comparable with that of previous reports, and occurrence of emergent AEs generally decreased over time. The most common AEs (≥30% incidence suspected to be treatment-related were stomatitis (43.2% and mouth ulceration (32.4%.Everolimus use led to sustained reduction in tumor volume, and new responses were observed for SEGA and renal angiomyolipoma from the blinded core phase of the study. These findings support the hypothesis that everolimus can safely reverse multisystem manifestations of TSC in a

  4. Qualitative and Quantitative Detection of Botulinum Neurotoxins from Complex Matrices: Results of the First International Proficiency Test

    Directory of Open Access Journals (Sweden)

    Sylvia Worbs

    2015-11-01

    Full Text Available In the framework of the EU project EQuATox, a first international proficiency test (PT on the detection and quantification of botulinum neurotoxins (BoNT was conducted. Sample materials included BoNT serotypes A, B and E spiked into buffer, milk, meat extract and serum. Different methods were applied by the participants combining different principles of detection, identification and quantification. Based on qualitative assays, 95% of all results reported were correct. Successful strategies for BoNT detection were based on a combination of complementary immunological, MS-based and functional methods or on suitable functional in vivo/in vitro approaches (mouse bioassay, hemidiaphragm assay and Endopep-MS assay. Quantification of BoNT/A, BoNT/B and BoNT/E was performed by 48% of participating laboratories. It turned out that precise quantification of BoNT was difficult, resulting in a substantial scatter of quantitative data. This was especially true for results obtained by the mouse bioassay which is currently considered as “gold standard” for BoNT detection. The results clearly demonstrate the urgent need for certified BoNT reference materials and the development of methods replacing animal testing. In this context, the BoNT PT provided the valuable information that both the Endopep-MS assay and the hemidiaphragm assay delivered quantitative results superior to the mouse bioassay.

  5. Qualitative and Quantitative Detection of Botulinum Neurotoxins from Complex Matrices: Results of the First International Proficiency Test

    Science.gov (United States)

    Worbs, Sylvia; Fiebig, Uwe; Zeleny, Reinhard; Schimmel, Heinz; Rummel, Andreas; Luginbühl, Werner; Dorner, Brigitte G.

    2015-01-01

    In the framework of the EU project EQuATox, a first international proficiency test (PT) on the detection and quantification of botulinum neurotoxins (BoNT) was conducted. Sample materials included BoNT serotypes A, B and E spiked into buffer, milk, meat extract and serum. Different methods were applied by the participants combining different principles of detection, identification and quantification. Based on qualitative assays, 95% of all results reported were correct. Successful strategies for BoNT detection were based on a combination of complementary immunological, MS-based and functional methods or on suitable functional in vivo/in vitro approaches (mouse bioassay, hemidiaphragm assay and Endopep-MS assay). Quantification of BoNT/A, BoNT/B and BoNT/E was performed by 48% of participating laboratories. It turned out that precise quantification of BoNT was difficult, resulting in a substantial scatter of quantitative data. This was especially true for results obtained by the mouse bioassay which is currently considered as “gold standard” for BoNT detection. The results clearly demonstrate the urgent need for certified BoNT reference materials and the development of methods replacing animal testing. In this context, the BoNT PT provided the valuable information that both the Endopep-MS assay and the hemidiaphragm assay delivered quantitative results superior to the mouse bioassay. PMID:26703724

  6. Qualitative and Quantitative Detection of Botulinum Neurotoxins from Complex Matrices: Results of the First International Proficiency Test.

    Science.gov (United States)

    Worbs, Sylvia; Fiebig, Uwe; Zeleny, Reinhard; Schimmel, Heinz; Rummel, Andreas; Luginbühl, Werner; Dorner, Brigitte G

    2015-11-26

    In the framework of the EU project EQuATox, a first international proficiency test (PT) on the detection and quantification of botulinum neurotoxins (BoNT) was conducted. Sample materials included BoNT serotypes A, B and E spiked into buffer, milk, meat extract and serum. Different methods were applied by the participants combining different principles of detection, identification and quantification. Based on qualitative assays, 95% of all results reported were correct. Successful strategies for BoNT detection were based on a combination of complementary immunological, MS-based and functional methods or on suitable functional in vivo/in vitro approaches (mouse bioassay, hemidiaphragm assay and Endopep-MS assay). Quantification of BoNT/A, BoNT/B and BoNT/E was performed by 48% of participating laboratories. It turned out that precise quantification of BoNT was difficult, resulting in a substantial scatter of quantitative data. This was especially true for results obtained by the mouse bioassay which is currently considered as "gold standard" for BoNT detection. The results clearly demonstrate the urgent need for certified BoNT reference materials and the development of methods replacing animal testing. In this context, the BoNT PT provided the valuable information that both the Endopep-MS assay and the hemidiaphragm assay delivered quantitative results superior to the mouse bioassay.

  7. Counselees' Perspectives of Genomic Counseling Following Online Receipt of Multiple Actionable Complex Disease and Pharmacogenomic Results: a Qualitative Research Study.

    Science.gov (United States)

    Sweet, Kevin; Hovick, Shelly; Sturm, Amy C; Schmidlen, Tara; Gordon, Erynn; Bernhardt, Barbara; Wawak, Lisa; Wernke, Karen; McElroy, Joseph; Scheinfeldt, Laura; Toland, Amanda E; Roberts, J S; Christman, Michael

    2016-12-05

    Genomic applications raise multiple challenges including the optimization of genomic counseling (GC) services as part of the results delivery process. More information on patients' motivations, preferences, and informational needs are essential to guide the development of new, more efficient practice delivery models that capitalize on the existing strengths of a limited genetic counseling workforce. Semi-structured telephone interviews were conducted with a subset of counselees from the Coriell Personalized Medicine Collaborative following online receipt of multiple personalized genomic test reports. Participants previously had either in-person GC (chronic disease cohort, n = 20; mean age 60 years) or telephone GC (community cohort, n = 31; mean age 46.8 years). Transcripts were analyzed using a Grounded Theory framework. Major themes that emerged from the interviews include 1) primary reasons for seeking GC were to clarify results, put results into perspective relative to other health-related concerns, and to receive personalized recommendations; 2) there is need for a more participant driven approach in terms of mode of GC communication (in-person, phone, video), and refining the counseling agenda pre-session; and 3) there was strong interest in the option of follow up GC. By clarifying counselees' expectations, views and desired outcomes, we have uncovered a need for a more participant-driven GC model when potentially actionable genomic results are received online.

  8. EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

    Directory of Open Access Journals (Sweden)

    N. A. Avdeev

    2015-01-01

    Full Text Available A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.

  9. Kinetic Results for Mutations of Conserved Residues H304 and R309 of Human Sulfite Oxidase Point to Mechanistic Complexities

    Science.gov (United States)

    Davis, Amanda C.; Johnson-Winters, Kayunta; Arnold, Anna R.; Tollin, Gordon; Enemark, John H.

    2014-01-01

    Several point mutations in the gene of human sulfite oxidase (hSO) result in isolated sulfite oxidase deficiency, an inherited metabolic disorder. Three conserved residues (H304, R309, K322) are hydrogen bonded to the phosphate group of the molybdenum cofactor, and the R309H and K322R mutations are responsible for isolated sulfite oxidase deficiency. The kinetic effects of the K322R mutation have been previously reported (Rajapakshe et al. 2012, Chem. Biodiversity 9, 1621-1634); here we investigate several mutants of H304 and R309 by steady-state kinetics, laser flash photolysis studies of intramolecular electron transfer (IET), and spectroelectrochemistry. An unexpected result is that all of the mutants show decreased rates of IET but increased steady-state rates of catalysis. However, in all cases the rate of IET is greater than the overall turnover rate, showing that IET is not the rate determining step for any of the mutations. PMID:24968320

  10. Changes to channel sediments resulting from complex human impacts in a gravel-bed river, Polish Carpathians

    Science.gov (United States)

    Zawiejska, Joanna; Wyżga, Bartłomiej; Hajdukiewicz, Hanna; Radecki-Pawlik, Artur; Mikuś, Paweł

    2016-04-01

    During the second half of the twentieth century, many sections of the Czarny Dunajec River, Polish Carpathians, were considerably modified by channelization as well as gravel-mining and the resultant channel incision (up to 3.5 m). This paper examines changes to the longitudinal pattern of grain size and sorting of bed material in an 18-km-long river reach. Surface bed-material grain size was established on 47 gravel bars and compared with a reference downstream fining trend of bar sediments derived from the sites with average river width and a vertically stable channel. Contrary to expectations, the extraction of cobbles from the channel bed in the upper part of the study reach, conducted in the past decades, has resulted in the marked coarsening of bed material in this river section. The extraction facilitated entrainment of exposed finer grains and has led to rapid bed degradation, whereas the concentration of flood flows in the increasingly deep and narrow channel has increased their competence and enabled a delivery of the coarse particles previously typical of the upstream reach. The middle section of the study reach, channelized to prevent sediment delivery to a downstream reservoir, now transfers the bed material flushed out from the incising upstream section. With considerably increased transport capacity of the river and with sediment delivery from bank erosion eliminated by bank reinforcements, bar sediments in the channelized section are typified by increased size of the finer fraction and better-than-average sorting. In the wide, multi-thread channel in the lower part of the reach, low unit stream power and high channel-form roughness facilitate sediment deposition and are reflected in relatively fine grades of bar gravels. The study showed that selective extraction of larger particles from the channel bed leads to channel incision at and upstream of the mining site. However, unlike bulk gravel mining, selective extraction does not result in sediment

  11. Analysis of boundary point (break point) in Linear Delay Model for nanoscale VLSI standard cell library characterization at PVT corners

    CERN Document Server

    Agarwal, Gaurav Kumar

    2014-01-01

    In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay is picked from Look Up Tables (LUT) rather than conventional SPICE simulations. But accuracy of this method depends upon the underlying delay model with which LUT was characterized. Non Linear Delay Model (NLDM) based LUTs are quite common in industries. These LUT requires huge amount to time during characterization because of huge number of SPICE simulations done at arbitrary points. To improve this people proposed various other delay models like alpha-power and piecewise linear delay models. Bulusu et al proposed Linear Delay Model(LDM) which reduces LUT generation time to 50 percent. LDM divides delay curve w.r.t input rise time(trin) into two different region one is linear and other is non-linear. This boundary point between linear and non- linear region was called break point (trb). Linear region will be done if we simulate at only two points. This advantage...

  12. VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate

    Directory of Open Access Journals (Sweden)

    M. Agarwal

    2016-12-01

    Full Text Available Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using allpass filters. In this paper, design and minimum multiplier implementation of a fixed point lattice wave digital filter (WDF based on three port parallel adaptor allpass structure is proposed. Here, the second-order allpass sections are implemented with three port parallel adaptor allpass structures. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers. Three design examples are included to analyze the effectiveness of the proposed approach. These are implemented in verilog HDL language and mapped to a standard cell library in a 0.18 μm CMOS process. The functionality of the implementations have been verified by applying number of different input vectors. Results and simulations demonstrate that the proposed design method leads to an efficient lattice WDF in terms of maximum sampling frequency. The cost to pay is small area overhead. The postlayout simulations have been done by HSPICE with CMOS transistors.

  13. VLSI systems energy management from a software perspective – A literature survey

    Directory of Open Access Journals (Sweden)

    Prasada Kumari K.S.

    2016-09-01

    Full Text Available The increasing demand for ultra-low power electronic systems has motivated research in device technology and hardware design techniques. Experimental studies have proved that the hardware innovations for power reduction are fully exploited only with the proper design of upper layer software. Also, the software power and energy modelling and analysis – the first step towards energy reduction is complex due to the inter and intra dependencies of processors, operating systems, application software, programming languages and compilers. The subject is too vast; the paper aims to give a consolidated view to researchers in arriving at solutions to power optimization problems from a software perspective. The review emphasizes the fact that software design and implementation is to be viewed from system energy conservation angle rather than as an isolated process. After covering a global view of end to end software based power reduction techniques for micro sensor nodes to High Performance Computing systems, specific design aspects related to battery powered Embedded computing for mobile and portable systems are addressed in detail. The findings are consolidated into 2 major categories – those related to research directions and those related to existing industry practices. The emerging concept of Green Software with specific focus on mainframe computing is also discussed in brief. Empirical results on power saving are included wherever available. The paper concludes that only with the close co-ordination between hardware architect, software architect and system architect low energy systems can be realized.

  14. The results of complex optical measurements of vertical temperature profile of the atmos-phere in the winter in Yakutsk

    Science.gov (United States)

    Nikolashkin, Semyen; Ignatyev, V. M.; Ammosov, Petr; Koltovskoy, Igor; Titov, Semen; Reshetnikov, Alexander

    The results of simultaneous measurements of atmospheric temperature from 0 to 100 km by lidar, spectrometric and interferometric methods in winter 2008 in Yakutsk are presented. Temperature measurements for the surface layer from 0 to 20-25 km were obtained from radio-sonde data on upper-air station in Yakutsk. Measuring the temperature of the middle atmosphere from 25 to 55-60 km made using Rayleigh Lidar near Yakutsk, with the following parameters: a transmitter Nd-YAG laser at a wavelength of 532 nm and a pulse energy of 200 mJ receiver - a telescope with a primary mirror diameter of 60 cm and a focal length of 200 cm, with a photon counting system and a spectrum analyzer. The temperature of the upper atmosphere was meas-ured at three altitude levels: by hydroxyl emission layer at the mesopause (6,2 band) , molecular oxygen radiation using an infrared spectrograph with a CCD camera and atomic oxygen emission line 557.7 nm with Fabry-Perot spectrometer (FPS) at the Maimaga optic range. FPS aperture was 15 cm, gap 1.5 cm, plate’s reflectance 0.85 and finess12. Thus, in this work, we covered by the temperature measuring most of the atmosphere ex-cept for a layer of the mesosphere from 60 to 87 km. For comparison, also are used CIRA model and the AURA MLS instrument (MicroLimb Sounder) temperature profiles data. Data analysis showed that there is a wave-like change in the vertical temperature profile, which is the result of vertical transmission features planetary waves during a stratospheric warming. This work is supported by the Integration project of the SB RAS No. 106 and RFBR grant No. 12-05-98547-r-vostok-a.

  15. Disentangling the complexity of nitrous oxide cycling in coastal sediments: Results from a novel multi-isotope approach

    Science.gov (United States)

    Wankel, S. D.; Buchwald, C.; Charoenpong, C.; Ziebis, W.

    2014-12-01

    Although marine environments contribute approximately 30% of the global atmospheric nitrous oxide (N2O) flux, coastal systems appear to comprise a disproportionately large majority of the ocean-atmosphere flux. However, there exists a wide range of estimates and future projections of N2O production and emission are confounded by spatial and temporal variability of biological sources and sinks. As N2O is produced as an intermediate in both oxidative and reductive microbial processes and can also be consumed as an electron acceptor, a mechanistic understanding of the regulation of these pathways remains poorly understood. To improve our understanding of N2O dynamics in coastal sediments, we conducted a series of intact flow-through sediment core incubations (Sylt, Germany), while manipulating both the O2 and NO3- concentrations in the overlying water. Steady-state natural abundance isotope fluxes (δ15N and δ18O) of nitrate, nitrite, ammonium and nitrous oxide were monitored throughout the experiments. We also measured both the isotopomer composition (site preference (SP) of the 15N in N2O) as well as the Δ17O composition in experiments conducted with the addition of NO3- with an elevated Δ17O composition (19.5‰), which provide complementary information about the processes producing and consuming N2O. Results indicate positive N2O fluxes (to the water column) across all conditions and sediment types. Decreasing dissolved O2 to 30% saturation resulted in reduced N2O fluxes (5.9 ± 6.5 μmol m2 d-1) compared to controls (17.8 ± 6.5 μmol m-2 d-1), while the addition of 100 μM NO3- yielded higher N2O fluxes (49.0 ± 18.5 μmol m-2 d-1). In all NO3- addition experiments, the Δ17O signal from the NO3- was clearly observed in the N2O efflux implicating denitrification as a large source of N2O. However, Δ17O values were always lower (1.9 to 8.6‰) than the starting NO3- indicating an important role for nitrification-based N2O production and/or O isotope exchange

  16. An analysis of complex multiple-choice science-technology-society items: Methodological development and preliminary results

    Science.gov (United States)

    Vázquez-Alonso, Ángel; Manassero-Mas, María-Antonia; Acevedo-Díaz, José-Antonio

    2006-07-01

    The scarce attention to the assessment and evaluation in science education research has been especially harmful for teaching science-technology-society (STS) issues, due to the dialectical, tentative, value-laden, and polemic nature of most STS topics. This paper tackles the methodological difficulties of the instruments that monitor views related to STS topics and rationalizes a quantitative methodology and an analysis technique to improve the utility of an empirically developed multiple-choice item pool, the Questionnaire of Opinions on STS. This methodology embraces an item-scaling psychometrics based on the judgments by a panel of experts, a multiple response model, a scoring system, and the data analysis. The methodology finally produces normalized attitudinal indices that represent the respondent's reasoned beliefs toward STS statements, the respondent's position on an item that comprises several statements, or the respondent's position on an entire STS topic that encompasses a set of items. Some preliminary results show the methodology's ability to evaluate the STS attitudes in a qualitative and quantitative way and for statistical hypothesis testing. Lastly, some applications for teacher training and STS curriculum development in science classrooms are discussed.

  17. Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT in a Digital Radio Mondiale (DRM and DRM+ Receiver

    Directory of Open Access Journals (Sweden)

    Sheau-Fang Lei

    2013-05-01

    Full Text Available This paper presents a compact structure of recursive discrete Fourier transform (RDFT with prime factor (PF and common factor (CF algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051 and 11.5 (or 0.1176 mW at 25 (or 0.273 MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications.

  18. Variation of the isotopic composition of complexing reaction products as a result of isotopically selective excitation of the molecules of one of the reagents

    Energy Technology Data Exchange (ETDEWEB)

    Kapralova, G.A.; Makharinskii, L.E.; Trofimova, E.M.; Chaikin, A.M.

    1980-05-05

    The possibility of influencing the complexing reaction rate by laser radiation was examined. The variation of the isotopic composition of BCl/sub 3/ in the reaction BCl/sub 3/+N(CH/sub 3/)/sub 3/=BCl/sub 3/N(CH/sub 3/)/sub 3/ was shown experimentally as a result of selective excitation of /sup 11/BCl/sub 3/ by CO/sub 2/ laser radiation.

  19. A unified approach to VLSI layout automation and algorithm mapping on processor arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.

    1993-01-01

    Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.

  20. Ligation of the intersphincteric fistula tract (LIFT): a minimally invasive procedure for complex anal fistula: two-year results of a prospective multicentric study.

    Science.gov (United States)

    Sileri, Pierpaolo; Giarratano, Gabriella; Franceschilli, Luana; Limura, Elsa; Perrone, Federico; Stazi, Alessandro; Toscana, Claudio; Gaspari, Achille Lucio

    2014-10-01

    The surgical management of anal fistulas is still a matter of discussion and no clear recommendations exist. The present study analyses the results of the ligation of the intersphincteric fistula tract (LIFT) technique in treating complex anal fistulas, in particular healing, fecal continence, and recurrence. Between October 2010 and February 2012, a total of 26 consecutive patients underwent LIFT. All patients had a primary complex anal fistula and preoperatively all underwent clinical examination, proctoscopy, transanal ultrasonography/magnetic resonance imaging, and were treated with the LIFT procedure. For the purpose of this study, fistulas were classified as complex if any of the following conditions were present: tract crossing more than 30% of the external sphincter, anterior fistula in a woman, recurrent fistula, or preexisting incontinence. Patient's postoperative complications, healing time, recurrence rate, and postoperative continence were recorded during follow-up. The minimum follow-up was 16 months. Five patients required delayed LIFT after previous seton. There were no surgical complications. Primary healing was achieved in 19 patients (73%). Seven patients (27%) had recurrence presenting between 4 and 8 weeks postoperatively and required further surgical treatment. Two of them (29%) had previous insertion of a seton. No patients reported any incontinence postoperatively and we did not observe postoperative continence worsening. In our experience, LIFT appears easy to perform, is safe with no surgical complication, has no risk of incontinence, and has a low recurrence rate. These results suggest that LIFT as a minimally invasive technique should be routinely considered for patients affected by complex anal fistula. © The Author(s) 2013.

  1. Recent Results with a segmented Hybrid Photon Detector for a novel parallax-free PET Scanner for Brain Imaging

    CERN Document Server

    Braem, André; Joram, Christian; Mathot, Serge; Séguinot, Jacques; Weilhammer, Peter; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

    2007-01-01

    We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is laid on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

  2. Recent results with a segmented Hybrid Photon Detector for a novel, parallax-free PET Scanner for Brain Imaging

    Energy Technology Data Exchange (ETDEWEB)

    Braem, A. [CERN, PH Department, CH-1211 Geneva (Switzerland); Chesi, E. [CERN, PH Department, CH-1211 Geneva (Switzerland); Joram, C. [CERN, PH Department, CH-1211 Geneva (Switzerland); Mathot, S. [CERN, PH Department, CH-1211 Geneva (Switzerland); Seguinot, J. [CERN, PH Department, CH-1211 Geneva (Switzerland); Weilhammer, P. [CERN, PH Department, CH-1211 Geneva (Switzerland)]. E-mail: Peter.Weilhammer@cern.ch; Ciocia, F. [INFN, Sezione di Bari and University of Bari, Bari (Italy); De Leo, R. [INFN, Sezione di Bari and University of Bari, Bari (Italy); Nappi, E. [INFN, Sezione di Bari and University of Bari, Bari (Italy); Vilardi, I. [INFN, Sezione di Bari and University of Bari, Bari (Italy); Argentieri, A. [INFN, Sezione di Bari and Politechnic of Bari, Bari (Italy); Corsi, F. [INFN, Sezione di Bari and Politechnic of Bari, Bari (Italy); Dragone, A. [INFN, Sezione di Bari and Politechnic of Bari, Bari (Italy); Pasqua, D. [INFN, Sezione di Bari and Politechnic of Bari, Bari (Italy)

    2007-02-01

    We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is laid on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

  3. Tuning of superconducting nanowire single-photon detector parameters for VLSI circuit testing using time-resolved emission

    Science.gov (United States)

    Bahgat Shehata, A.; Stellari, F.

    2015-01-01

    Time-Resolved Emission (TRE) is a truly non-invasive technique based on the detection of intrinsic light emitted by integrated circuits that is used for the detection of timing related faults from the backside of flip-chip VLSI circuits. Single-photon detectors with extended sensitivity in the Near Infrared (NIR) are used to perform time-correlated single-photon counting measurements and retrieve the temporal distribution of the emitted photons, thus identifying gates switching events. The noise, efficiency and jitter performance of the detector are crucial to enable ultra-low voltage waveform sensitivity. For this reason, cryogenically cooled Superconducting Nanowire Single-Photon Detectors (SNSPDs) offer superior performance compared to state-of-the-art Single-Photon Avalanche Diodes (SPADs). In this paper we will discuss how detector front-end electronics parameters, such as bias current, RF attenuation and comparator threshold, can be tailored to optimize the measurement Signal-to-Noise Ratio (SNR), defined as the ratio between the switching emission peak amplitude and the standard deviation of the noise in the time interval in which there are no photons emitted from the circuit. For example, reducing the attenuation and the threshold of the comparator used to detect switching events may lead to an improvement of the jitter, due to the better discrimination of the detector firing, but also a higher sensitivity to external electric noise disturbances. Similarly, by increasing the bias current, both the detection efficiency and the jitter improve, but the noise increases as well. For these reasons an optimization of the SNR is necessary. For this work, TRE waveforms were acquired from a 32 nm Silicon On Insulator (SOI) chip operating down to 0.4 V using different generations of SNSPD systems.

  4. A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.

    Science.gov (United States)

    Tseng, Yu-Cheng; Hsu, Po-Hsiung; Chang, Tian-Sheuan

    2011-11-01

    This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.

  5. VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

    Science.gov (United States)

    Satheeskumaran, S.; Sabrigiriraj, M.

    2016-06-01

    Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.

  6. Kissing-Y stenting for endovascular treatment of complex wide necked bifurcation aneurysms using Acandis Acclino stents: results and literature review.

    Science.gov (United States)

    Brassel, Friedhelm; Melber, Katharina; Schlunz-Hendann, Martin; Meila, Dan

    2016-04-01

    Y-configured stent assisted coiling is a promising therapeutic option to ensure safe coil embolization and preserve the affected arteries in complex wide necked aneurysms. We present our experience with self-expanding Acandis Acclino stents for the treatment of complex aneurysms using the kissing-Y technique. We retrospectively reviewed seven patients with seven complex aneurysms (three anterior communicating artery (AcomA), two middle cerebral artery, one basilar artery/superior cerebellar artery, and one vertebral artery/posterior inferior cerebellar artery) who were treated with the kissing-Y technique by stent assisted coiling from June 2013 to July 2014, with follow-up until January 2015. DSA follow-up was up to 17 months, with a mean follow-up period of 10 months. Six patients were treated electively and one in the acute phase of a subarachnoid hemorrhage. In all cases, closed cell Acandis Acclino stents were used. We evaluated procedural complications, clinical outcomes, and mid term angiographic follow-up. Additionally, a literature review is provided. In all patients, stents were successfully placed and implanted. One patient developed a periprocedural thromboembolic complication not directly related to the stents. No other periprocedural or postprocedural complications were encountered. Follow-up examinations showed stable and total occlusion of all coiled aneurysms. The results of our study show that the kissing-Y technique using closed cell Acandis Acclino stents followed by coil embolization is a feasible treatment option for selected complex bifurcation aneurysms. Published by the BMJ Publishing Group Limited. For permission to use (where not already granted under a licence) please go to http://www.bmj.com/company/products-services/rights-and-licensing/

  7. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  8. Bucolic Complexes

    CERN Document Server

    Brešar, Bostjan; Chepoi, Victor; Gologranc, Tanja; Osajda, Damian

    2012-01-01

    In this article, we introduce and investigate bucolic complexes, a common generalization of systolic complexes and of CAT(0) cubical complexes. This class of complexes is closed under Cartesian products and amalgamations over some convex subcomplexes. We study various approaches to bucolic complexes: from graph-theoretic and topological viewpoints, as well as from the point of view of geometric group theory. Bucolic complexes can be defined as locally-finite simply connected prism complexes satisfying some local combinatorial conditions. We show that bucolic complexes are contractible, and satisfy some nonpositive-curvature-like properties. In particular, we prove a version of the Cartan-Hadamard theorem, the fixed point theorem for finite group actions, and establish some results on groups acting geometrically on such complexes. We also characterize the 1-skeletons (which we call bucolic graphs) and the 2-skeletons of bucolic complexes. In particular, we prove that bucolic graphs are precisely retracts of Ca...

  9. Design and implementation of efficient low complexity biomedical artifact canceller for nano devices

    Directory of Open Access Journals (Sweden)

    Md Zia Ur RAHMAN

    2016-07-01

    Full Text Available In the current day scenario, with the rapid development of communication technology remote health care monitoring becomes as an intense research area. In remote health care monitoring, the primary aim is to facilitate the doctor with high resolution biomedical data. In order to cancel various artifacts in clinical environment in this paper we propose some efficient adaptive noise cancellation techniques. To obtain low computational complexity we combine clipping the data or error with Least Mean Square (LMS algorithm. This results sign regressor LMS (SRLMS, sign LMS (SLMS and sign LMS (SSLMS algorithms. Using these algorithms, we design Very-large-scale integration (VLSI architectures of various Biomedical Noise Cancellers (BNCs. In addition, the filtering capabilities of the proposed implementations are measured using real biomedical signals. Among the various BNCs tested, SRLMS based BNC is found to be better with reference to convergence speed, filtering capability and computational complexity. The main advantage of this technique is it needs only one multiplication to compute next weight. In this manner SRLMS based BNC is independent of filter length with reference to its computations. Whereas, the average signal to noise ratio achieved in the noise cancellation experiments are recorded as 7.1059dBs, 7.1776dBs, 6.2795dBs and 5.8847dBs for various BNCs based on LMS, SRLMS, SLMS and SSSLMS algorithms respectively. Based on the filtering characteristics, convergence and computational complexity, the proposed SRLMS based BNC architecture is well suited for nanotechnology applications.

  10. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  11. Ca(2+) -complex stability of GAPAGPLIVPY peptide in gas and aqueous phase, investigated by affinity capillary electrophoresis and molecular dynamics simulations and compared to mass spectrometric results.

    Science.gov (United States)

    Nachbar, Markus; El Deeb, Sami; Mozafari, Mona; Alhazmi, Hassan A; Preu, Lutz; Redweik, Sabine; Lehmann, Wolf Dieter; Wätzig, Hermann

    2016-03-01

    Strong, sequence-specific gas-phase bindings between proline-rich peptides and alkaline earth metal ions in nanoESI-MS experiments were reported by Lehmann et al. (Rapid Commun. Mass Spectrom. 2006, 20, 2404-2410), however its relevance for physiological-like aqueous phase is uncertain. Therefore, the complexes should also be studied in aqueous solution and the relevance of the MS method for binding studies be evaluated. A mobility shift ACE method was used for determining the binding between the small peptide GAPAGPLIVPY and various metal ions in aqueous solution. The findings were compared to the MS results and further explained using computational methods. While the MS data showed a strong alkaline earth ion binding, the ACE results showed nonsignificant binding. The proposed vacuum state complex also decomposed during a molecular dynamic simulation in aqueous solution. This study shows that the formed stable peptide-metal ion adducts in the gas phase by ESI-MS does not imply the existence of analogous adducts in the aqueous phase. Comparing peptide-metal ion interaction under the gaseous MS and aqueous ACE conditions showed huge difference in binding behavior.

  12. Forest, Trees, Dynamics: Results from a novel Wisconsin Card Sorting Test variant Protocol for Studying Global-Local Attention and Complex Cognitive Processes

    Directory of Open Access Journals (Sweden)

    Benjamin eCowley

    2016-02-01

    Full Text Available BackgroundRecognition of objects and their context relies heavily on the integrated functioning of global and local visual processing. In a realistic setting such as work, this processing becomes a sustained activity, implying a consequent interaction with executive functions.MotivationThere have been many studies of either global-local attention or executive functions; however it is relatively novel to combine these processes to study a more ecological form of attention. We aim to explore the phenomenon of global-local processing during a task requiring sustained attention and working memory.MethodsWe develop and test a novel protocol for global-local dissociation, with task structure including phases of divided ('rule search' and selective ('rule found' attention, based on the Wisconsin Card Sorting Task.We test it in a laboratory study with 25 participants, and report on behaviour measures (physiological data was also gathered, but not reported here. We develop novel stimuli with more naturalistic levels of information and noise, based primarily on face photographs, with consequently more ecological validity.ResultsWe report behavioural results indicating that sustained difficulty when participants test their hypotheses impacts matching-task performance, and diminishes the global precedence effect. Results also show a dissociation between subjectively experienced difficulty and objective dimension of performance, and establish the internal validity of the protocol.ContributionWe contribute an advance in the state of the art for testing global-local attention processes in concert with complex cognition. With three results we establish a connection between global-local dissociation and aspects of complex cognition. Our protocol also improves ecological validity and opens options for testing additional interactions in future work.

  13. A low-power VLSI implementation for variable length decoder in MPEG-1 Layer III

    Science.gov (United States)

    Tsai, Tsung-Han; Liu, Chun-Nan; Chen, Wen-Cheng

    2004-04-01

    MPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.

  14. Crosstalk between Fibroblast Growth Factor (FGF Receptor and Integrin through Direct Integrin Binding to FGF and Resulting Integrin-FGF-FGFR Ternary Complex Formation

    Directory of Open Access Journals (Sweden)

    Seiji Mori

    2013-08-01

    Full Text Available Fibroblast growth factors (FGFs play a critical role in diverse physiological processes and the pathogenesis of diseases. Integrins are involved in FGF signaling, since integrin antagonists suppress FGF signaling. This is called integrin-FGF crosstalk, while the specifics of the crosstalk are unclear. This review highlights recent findings that FGF1 directly interacts with integrin αvβ3, and the resulting integrin-FGF-fibroblast growth factor receptor (FGFR ternary complex formation is essential for FGF1-induced cell proliferation, migration and angiogenesis. An integrin-binding defective FGF1 mutant (Arg-50 to Glu, R50E is defective in ternary complex formation and in inducing cell proliferation, migration and angiogenesis, while R50E still binds to the FGF receptor and heparin. In addition, R50E suppressed tumorigenesis in vivo, while wild-type (WT FGF1 enhanced it. Thus, the direct interaction between FGF1 and integrin αvβ3 is a potential therapeutic target, and R50E is a potential therapeutic agent.

  15. Photodeflection signal formation in photothermal measurements: comparison of the complex ray theory, the ray theory, the wave theory, and experimental results.

    Science.gov (United States)

    Kobyli Ska, Dorota Korte; Bukowski, Roman J; Burak, Boguslaw; Bodzenta, Jerzy; Kochowski, Stanislaw

    2007-08-01

    A comparison is made of three methods for modeling the interaction of a laser probe beam with the temperature field of a thermal wave. The three methods include: (1) a new method based on complex ray theory, which allows us to take into account the disturbance of the amplitude and phase of the electric field of the probe beam, (2) the ray deflection averaging theory of Aamodt and Murphy, and (3) the wave theory (WT) of Glazov and Muratikov. To carry out this comparison, it is necessary to reformulate the description of the photodeflection signal in either the WT or the ray deflection averaging theory. It is shown that the differences between calculated signals using the different theories are most pronounced when the radius of the probe beam is comparable with the length of the thermal wave in the region of their interaction. Predictions of the theories are compared with experimental results. A few parameters of the experimental setup are determined through multiparameter fitting of the theoretical curves to the experimental data. A least-squares procedure was chosen as a fitting method. The conclusion is that the calculation of the photodeflection signal in the framework of the complex ray theory is a more accurate approach than the ray deflection averaging theory or the wave one.

  16. Results of volume-staged fractionated Gamma Knife radiosurgery for large complex arteriovenous malformations: obliteration rates and clinical outcomes of an evolving treatment paradigm.

    Science.gov (United States)

    Franzin, Alberto; Panni, Pietro; Spatola, Giorgio; Vecchio, Antonella Del; Gallotti, Alberto L; Gigliotti, Carmen R; Cavalli, Andrea; Donofrio, Carmine A; Mortini, Pietro

    2016-12-01

    OBJECTIVE There are few reported series regarding volume-staged Gamma Knife radiosurgery (GKRS) for the treatment of large, complex, cerebral arteriovenous malformations (AVMs). The object of this study was to report the results of using volume-staged Gamma Knife radiosurgery for patients affected by large and complex AVMs. METHODS Data from 20 patients with large AVMs were prospectively included in the authors' AVM database between 2004 and 2012. A staging strategy was used when treating lesion volumes larger than 10 cm(3). Hemorrhage and seizures were the presenting clinical feature for 6 (30%) and 8 (40%) patients, respectively. The median AVM volume was 15.9 cm(3) (range 10.1-34.3 cm(3)). The mean interval between stages (± standard deviation) was 15 months (± 9 months). The median margin dose for each stage was 20 Gy (range 18-25 Gy). RESULTS Obliteration was confirmed in 8 (42%) patients after a mean follow-up of 45 months (range 19-87 months). A significant reduction (> 75%) of the original nidal volume was achieved in 4 (20%) patients. Engel Class I-II seizure status was reported by 75% of patients presenting with seizures (50% Engel Class I and 25% Engel Class II) after radiosurgery. After radiosurgery, 71.5% (5/7) of patients who had presented with a worsening neurological deficit reported a complete resolution or amelioration. None of the patients who presented acutely because of hemorrhage experienced a new bleeding episode during follow-up. One (5%) patient developed radionecrosis that caused sensorimotor hemisyndrome. Two (10%) patients sustained a bleeding episode after GKRS, although only 1 (5%) was symptomatic. High nidal flow rate and a time interval between stages of less than 11.7 months were factors significantly associated with AVM obliteration (p = 0.021 and p = 0.041, respectively). Patient age younger than 44 years was significantly associated with a greater than 75% reduction in AVM volume but not with AVM obliteration (p = 0

  17. VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

    Science.gov (United States)

    Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

    2017-08-01

    Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

  18. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

    Directory of Open Access Journals (Sweden)

    Giacomo Indiveri

    2008-09-01

    Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  19. Results of psychodynamically oriented trauma-focused inpatient treatment for women with complex posttraumatic stress disorder (PTSD) and borderline personality disorder (BPD).

    Science.gov (United States)

    Sachsse, Ulrich; Vogel, Christina; Leichsenring, Falk

    2006-01-01

    In a naturalistic outcome study, the authors evaluated the results of a specific psychodynamically oriented trauma-focused inpatient treatment for women with complex posttraumatic stress disorder and concomitant borderline personality disorder, self-mutilating behavior, and depression. At admission, the frequency of self-mutilating behavior and the amount of inpatient treatment (an average of 68 days annually) of the sample was high, characterizing this patient group as "previously therapy resistant." Treatment outcome was assessed both at the end of treatment and in a 1-year follow-up. In comparison with a treatment-as-usual control group, the treatment program brought about significant and stable improvements both in trauma-specific symptoms (e.g. dissociation, intrusion, avoidance) and in general psychiatric symptoms (e.g., general symptom distress, frequency of self-mutilating behavior, number of hospitalizations). The frequency of inpatient treatments (hospitalizations) decreased dramatically (< 10 days annually; effect size: d = 2.88).

  20. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)