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Sample records for vlsi cmos circuit

  1. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  2. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  3. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  4. The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

    Institute of Scientific and Technical Information of China (English)

    骆祖莹; 闵应骅; 杨士元; 李晓维

    2002-01-01

    The authors theoretically describe the monotonic increasing relationship between averagepowers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, whichcan be fast computed, has been used as the evaluation criterion for the power of a practical circuit withdelay, which needs more computing time, in such fields as fast estimation for the average power and themaximum power, and fast optimization for the Iow test power. The authors propose a novel simulationapproach that uses delay-free power to compact a long input vector pair sequence into a short sequenceand then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. Incomparison with the traditional simulation approach that uses an un-compacted input sequence to simu-late the average (or maximum) power, experiment results demonstrate that in the field of fast estimationfor the average power, the present approach can be 6-10 times faster without significant loss in accuracy(less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach canbe 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast op-timization for the test power, the authors propose a novel delay-free power optimization approach for thetest power. Experiment results demonstrate that, in comparison with the approach of direct optimizationand the approach of Hamming distance optimization, this approach is of the highest optimization effi-ciency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% testpower).

  5. Analysis of Leakages and Leakage Reduction Methods in UDSM CMOS VLSI Circuits.

    Directory of Open Access Journals (Sweden)

    Sagar Ekade

    2014-04-01

    Full Text Available This is the era of portable devices which need to be powered by battery. Due to scarcity of space and leakages in chips, battery life is a serious concern. As technology advances, scaling of transistor feature size and supply voltage has improved the performance, increased the transistor density and reduced the power required by the chip. The maximum power consumed by the chip is the function of its technology along with its implementation. As technology is scaling down and CMOS circuits are supplied with lower supply voltages, the static power i.e. standby leakage current becomes very crucial. In Ultra Deep-submicron regime scaling has reduced the threshold voltage and that has led to increase in leakage current in sub-threshold region and hence rise in static power dissipation. This paper presents a critical analysis of leakages and leakage reduction techniques.

  6. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  7. A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Pushpa Saini

    2012-10-01

    Full Text Available Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In this paper, a technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature.

  8. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  9. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  10. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  11. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  12. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  13. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  14. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments practical design aspects

    CERN Document Server

    Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    1999-01-01

    We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).

  15. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Sudarshan Tiwari

    2012-05-01

    Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.

  16. A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

    Science.gov (United States)

    Smith, Edwyn D.

    1991-01-01

    Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

  17. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  18. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  19. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  20. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  1. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  2. CMOS Nonlinear Signal Processing Circuits

    OpenAIRE

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  3. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  4. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  5. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  6. Ground Bounce Noise Reduction in Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Vipin Kumar Sharma

    2015-12-01

    Full Text Available : Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.

  7. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  8. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  9. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  10. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  11. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  12. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  13. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  14. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  15. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  16. VLSI circuits implementing computational models of neocortical circuits.

    Science.gov (United States)

    Wijekoon, Jayawan H B; Dudek, Piotr

    2012-09-15

    This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.

  17. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  18. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  19. A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

    DEFF Research Database (Denmark)

    Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

    As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...

  20. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  1. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  2. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  3. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  4. Statistical circuit design for yield improvement in CMOS circuits

    Science.gov (United States)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  5. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  6. Low power SEU immune CMOS memory circuits

    Science.gov (United States)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  7. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  8. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  9. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  10. Efficient FM Algorithm for VLSI Circuit Partitioning

    Directory of Open Access Journals (Sweden)

    M.RAJESH

    2013-04-01

    Full Text Available In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if theinitial partitioning matrix is close to the final partitioning then the computation time (iteration required is small . Here we have proposed novel approach to arrive at initial partitioning by using spectralfactorization method the results was verified using several circuits.

  11. Bridging faults in BiCMOS circuits

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  12. Low-power VLSI circuits and systems

    CERN Document Server

    Pal, Ajit

    2015-01-01

    The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.

  13. Design of High Performance Dynamic CMOS Circuits in Deep Submicron Technology

    Directory of Open Access Journals (Sweden)

    Salendra.Govindarajulu

    2010-07-01

    Full Text Available Technology scaling of transistor feature size has provided a remarkable advancement in silicon industry for the last three decades. The demand and popularity of portable electronics is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic logic design implementations of 16-bit Ripple carry adder, 16-bit Comparator and Linear Feedback Shift Register (LFSR in terms of CMOS layout power consumption, delay, power delay product, area for 65 nm and 45 nm technologies. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH3 CMOS layout CAD tools.

  14. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  15. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  16. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  17. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  18. Analog CMOS circuit implementation of a pulse-coupled phase oscillator system and observation of synchronization phenomena

    Science.gov (United States)

    Matsuzaka, Kenji; Tohara, Takashi; Nakada, Kazuki; Morie, Takashi

    Analog CMOS circuit implementation of a system of pulse-coupled phase oscillators is proposed. A CMOS circuit that achieves the dynamics of pulse-coupled oscillators has been designed and fabricated using a 0.25-µm CMOS technology. The proposed oscillator circuits with continuous-time operation interact with each other via a pulse at each firing time. Update of the oscillator state is achieved by integrating the phase sensitivity function with the pulse width time span. The phase sensitivity function is generated by the combination of binary functions, while the function consists of three-values {-1,0,1}. Introducing a zero-value span in the function leads to fast synchronization and robustness to parameter fluctuation due to LSI device mismatches, which facilitates VLSI implementation. Using the fabricated CMOS circuit, we have observed not only in- and anti-phase but also out-of-phase synchronization.

  19. Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey

    Directory of Open Access Journals (Sweden)

    V.Sri Sai Harsha

    2015-09-01

    Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.

  20. RF Circuit Design in Nanometer CMOS

    OpenAIRE

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer C...

  1. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  2. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

    Directory of Open Access Journals (Sweden)

    Omnia S. Fadl

    2016-01-01

    Full Text Available Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

  3. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  4. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  5. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  6. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    OpenAIRE

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal a...

  7. A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

    DEFF Research Database (Denmark)

    Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

    As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...... transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results...

  8. Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

    OpenAIRE

    Yoshikawa, Nobuyuki; Tomida, T.; Tokuda, A.; Liu, Q.; Meng, X.(Institute of High Energy Physics, Beijing, China); Whiteley, SR.; VanDuzer, T.

    2005-01-01

    Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 mu m, 0.25 mu m, and 0.35 mu m commercial CMOS processes. Their static IN characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured...

  9. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    Science.gov (United States)

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  10. Ultra High-Speed CMOS Circuits Beyond 100 GHz

    CERN Document Server

    Gharavi, Sam

    2012-01-01

    The book covers the CMOS-based millimeter wave circuits and devices and presents methods and design techniques to use CMOS technology for circuits operating beyond 100 GHz.� Coverage includes a detailed description of both active and passive devices, including modeling techniques and performance optimization. Various mm-wave circuit blocks are discussed, emphasizing their design distinctions from low-frequency design methodologies. This book also covers a device-oriented circuit design technique that is essential for ultra high speed circuits and gives some examples of device/circuit co-design that can be used for mm-wave technology. Offers a detailed description of high frequency device modeling from a circuit designer perspective; Presents a set of techniques for optimizing the performance of CMOS for mm-wave technology, including noise and low noise design for mm-wave; Introduces circuit/device co-design techniques. �

  11. Design of Multivalued Circuits Based on an Algebra for Current—Mode CMOS Multivalued Circuits

    Institute of Scientific and Technical Information of China (English)

    陈偕雄; ClaudioMoraga

    1995-01-01

    An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed.this paper discusses its application in the design of multivalued circuits.Several current-mode CMOS quaternary and quinary circuits are designed by algebraic means.The design method based on this algebra may offer a design simpler than the previously known ones.

  12. A CMOS readout circuit for microstrip detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  13. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  14. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  15. Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments

    Science.gov (United States)

    Loinaz, Marc Joseph

    1995-11-01

    This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-μm CMOS technology. Each channel includes a wideband amplifier, a

  16. Graphene/Si CMOS hybrid hall integrated circuits.

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  17. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  18. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  19. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  20. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  1. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  2. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  3. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication

    Science.gov (United States)

    2008-08-25

    This approach combines a semiconductor transistor system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each...hybrid CMOS/nanodevice integrated circuits [10-12]. Such circuit combines a semiconductor transistors system with a nanowire crossbar, with simple two...both with and without embedded metallic clusters), self-assembled molecular monolayers, and thin chalcogenide and crystalline perovskite layers [20

  4. Scalable Testing Platform for CMOS Read In Integrated Circuits

    Science.gov (United States)

    2016-03-31

    Distribution A Approved for Public Release – Distribution is unlimited Scalable Testing Platform for CMOS Read-In Integrated Circuits Miguel...research group. This paper describes a single scalable testing platform (STP) capable of testing all of our RIICs. This approach reduces the design...time and risk associated with RIIC testing . On the hardware side, our platform consists of several custom printed circuit boards. On the software

  5. Chopper amplifier circuit with CMOS switches and amplifier FETs

    NARCIS (Netherlands)

    Huijsing, J.H.; Bakker, A.

    1997-01-01

    Abstract of NL 1001231 (C2) The input voltage is fed to the inputs of an operational amplifier via a chopping reversal switchThe CMOS operational amplifier has a current source and a current mirror. The operational amplifier output is fed to an output circuit. The possible offset voltage is supp

  6. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  7. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  8. State assignment approach to asynchronous CMOS circuit design

    Science.gov (United States)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  9. An Approach for Self-Timed Synchronous CMOS Circuit Design

    Science.gov (United States)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  10. An inductorless CMOS realization of Chua's circuit

    Energy Technology Data Exchange (ETDEWEB)

    Radwan, Ahmed G.; Soliman, Ahmed M.; El-Sedeek, Abdel-Latif

    2003-09-01

    In this paper, an inductorless CMOS realization of Chua's circuit [IEEE Trans. Circ. Syst.--I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua's circuit and can generate Rossler or double-scroll attractors by changing a single capacitor's value. Variables are represented in the current domain to facilitate adding or subtracting variables. New G{sub m}-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as {+-}1.5 V. Transistor-level simulation results using PSpice in 0.5 {mu}m Mietec process are presented.

  11. Secondary Side CMOS Feedback Control Integrated Circuit

    Science.gov (United States)

    1990-06-01

    Temperature ( Celc ~us) Figure 5.1: Experimental Temperature Dependence cf Untrimmed Bandgap Circuit 104 1. I I ’ - ’ 0 0.9 . -0-0 Ouput Voit -ge ---.o M...Schlecht and L.F. Casey, "Comparison of the Square-Wave and Quasi- Resonant Topologies," IEEE PESC Record, 1987, pp. 124-134. 132

  12. Analog VLSI Circuits for Short-Term Dynamic Synapses

    Directory of Open Access Journals (Sweden)

    Shih-Chii Liu

    2003-06-01

    Full Text Available Short-term dynamical synapses increase the computational power of neuronal networks. These synapses act as additional filters to the inputs of a neuron before the subsequent integration of these signals at its cell body. In this work, we describe a model of depressing and facilitating synapses derived from a hardware circuit implementation. This model is equivalent to theoretical models of short-term synaptic dynamics in network simulations. These circuits have been added to a network of leaky integrate-and-fire neurons. A cortical model of direction-selectivity that uses short-term dynamic synapses has been implemented with this network.

  13. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  14. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  15. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  16. Trade-offs in Specific CMOS RF Communication Circuits

    Institute of Scientific and Technical Information of China (English)

    李效龙; 田雨波

    2009-01-01

    The design trade-off in the front-end of the transceiver, such as LNA, mixer, local oscillator and PA, is concerned. The advantages and limitations of the circuit topologies and key parameters of the state-of-the-art CMOS transceiver building blocks are discussed in order to gain more insight about a specific block design. A normalized formula of the figures of merit for each building block is also proposed to evaluate the overall performance of various circuits for fair comparison.

  17. Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits.

    Science.gov (United States)

    1987-06-01

    Voltage Dviders. .. .. .. .. .. .. .. .. .. 47 2.7TTwo Differently Raloednverters...................... 49 2.6 MOS Trasistor SybolWith Zxpict C.andC...Inverter Cell. Current doesn’t flow between nets. This has two intertwined benefits. First, net behavior is a wedge by which we can modularize a circuit’s...that that the current flow through the gate is eucessive. Ratio bugs can be modeiled because transistors are modelled s resistors whose resistance is

  18. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  19. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  20. Analog CMOS contrastive Hebbian networks

    Science.gov (United States)

    Schneider, Christian; Card, Howard

    1992-09-01

    CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

  1. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  2. Leakage Current Estimation of CMOS Circuit with Stack Effect

    Institute of Scientific and Technical Information of China (English)

    Yong-Jun Xu; Zu-Ying Luo; Xiao-Wei Li; Li-Jian Li; Xian-Long Hong

    2004-01-01

    Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.

  3. Power comparison of CMOS and adiabatic full adder circuit

    CERN Document Server

    Reddy, Sunil Gavaskar; 10.5121/vlsic.2011.2306

    2011-01-01

    Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

  4. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  5. GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

    Institute of Scientific and Technical Information of China (English)

    Lu Junming; Lin Zhenghui

    2002-01-01

    In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.

  6. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  7. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  8. Variation-aware adaptive voltage scaling for digital CMOS circuits

    CERN Document Server

    Wirnshofer, Martin

    2013-01-01

    Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engine...

  9. Neutron-induced soft errors in CMOS circuits

    Energy Technology Data Exchange (ETDEWEB)

    Hazucha, P

    1999-09-01

    The subject of this thesis is a systematic study of soft errors occurring in CMOS integrated circuits when being exposed to radiation. The vast majority of commercial circuits operate in the natural environment ranging from the sea level to aircraft flight altitudes (less than 20 km), where the errors are caused mainly by interaction of atmospheric neutrons with silicon. Initially, the soft error rate (SER) of a static memory was measured for supply voltages from 2V to 5V when irradiated by 14 MeV and 100 MeV neutrons. Increased error rate due to the decreased supply voltage has been identified as a potential hazard for operation of future low-voltage circuits. A novel methodology was proposed for accurate SER characterization of a manufacturing process and it was validated by measurements on a 0.6 {mu}m process and 100 MeV neutrons. The methodology can be applied to theprediction of SER in the natural environment.

  10. Nanotube substituted source/drain regions for carbon nanotube transistors for VLSI circuits.

    Science.gov (United States)

    Dutta, Shibesh; Shankar, Balakrishnan

    2011-12-01

    Aggressive scaling of silicon technology over the years has pushed CMOS devices to their fundamental limits. Pioneering works on carbon nanotube during the last decade possessing exceptional electrical properties have provided an intriguing solution for high performance integrated circuits. So far, at best, carbon nanotubes have been considered only for the channel, with metal electrodes being used for source/drain. Here, alternative schemes of 'All-Nanotube' transistor are presented where even the transistor components are derived from carbon nanotubes which hold the promise for smaller, faster, denser and more power efficient electronics.

  11. GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

    Institute of Scientific and Technical Information of China (English)

    LuJunming; LinZhenghui

    2002-01-01

    In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.

  12. Deep sub-micron stud-via technology for superconductor VLSI circuits

    Science.gov (United States)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  13. A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

    Directory of Open Access Journals (Sweden)

    Trong-Tu Bui

    2013-01-01

    Full Text Available We present a compact and low-power rank-order searching (ROS circuit that can be used for building associative memories and rank-order filters (ROFs by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

  14. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  15. Analog CMOS circuit design and characterization for optical coherence tomography signal processing.

    Science.gov (United States)

    Kariya, Rajesh; Mathine, David L; Barton, Jennifer K

    2004-12-01

    We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 microm low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.

  16. Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

    Science.gov (United States)

    Bennett, K.; Lala, P. K.; Busaba, F.

    1997-01-01

    Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

  17. Noise in Large-Signal, Time-Varying RF CMOS Circuits: Theory & Design

    OpenAIRE

    Murphy, David Patrick

    2012-01-01

    RF CMOS design is now a mature field and CMOS radio transceivers have become standard in most consumer wireless devices. Like any wireless RF design, at the heart of the endeavor is the requirement to frequency translate signals between baseband and RF with minimal introduction of noise and distortion. This translation is generally accomplished using time-varying, strongly nonlinear circuits, whose operation and noise performance cannot be understood using standard LTI circuit analysis techni...

  18. Distinct rhythmic locomotor patterns can be generated by a simple adaptive neural circuit: biology, simulation, and VLSI implementation.

    Science.gov (United States)

    Ryckebusch, S; Wehr, M; Laurent, G

    1994-12-01

    Rhythmic motor patterns can be induced in leg motor neurons of isolated locust thoracic ganglia by bath application of pilocarpine. We observed that the relative phases of levators and depressors differed in the three thoracic ganglia. Assuming that the central pattern generating circuits underlying these three segmental rhythms are probably very similar, we developed a simple model circuit that can produce any one of the three activity patterns and characteristic phase relationships by modifying a single synaptic weight. We show results of a computer simulation of this circuit using the neuronal simulator NeuraLOG/Spike. We built and tested an analog VLSI circuit implementation of this model circuit that exhibits the same range of "behaviors" as the computer simulation. This multidisciplinary strategy will be useful to explore the dynamics of central pattern generating networks coupled to physical actuators, and ultimately should allow the design of biologically realistic walking robots.

  19. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  20. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  1. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  2. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  3. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    Directory of Open Access Journals (Sweden)

    Rita M. Shende

    2012-01-01

    Full Text Available Analog-to-digital converters (ADCs are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since theADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially powerconsumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

  4. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  5. Digitally-assisted analog and RF CMOS circuit design for software-defined radio

    CERN Document Server

    Okada, Kenichi

    2011-01-01

    This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

  6. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  7. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  8. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  9. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    Science.gov (United States)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-02-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  10. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    Science.gov (United States)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-01-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

  11. Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE

    Directory of Open Access Journals (Sweden)

    Mugdha Sathe

    2014-07-01

    Full Text Available According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.

  12. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    Energy Technology Data Exchange (ETDEWEB)

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  13. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  14. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  15. High-Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

    CERN Document Server

    Mak, Pui-In

    2012-01-01

    This book presents high-/mixed-voltage analog and radio frequency (RF) circuit techniques for developing low-cost multistandard wireless receivers in nm-length CMOS processes.  Key benefits of high-/mixed-voltage RF and analog CMOS circuits are explained, state-of-the-art examples are studied, and circuit solutions before and after voltage-conscious design are compared. Three real design examples are included, which demonstrate the feasibility of high-/mixed-voltage circuit techniques.    Provides a valuable summary and real case studies of the state-of-the-art in high-/mixed-voltage circuits and systems; Includes novel high-/mixed-voltage analog and RF circuit techniques – from concept to practice; Describes the first high-voltage-enabled mobile-TVRF front-end in 90nm CMOS and the first mixed-voltage full-band mobile-TV Receiver in 65nm CMOS; Demonstrates the feasibility of high-/mixed-voltage circuit techniques with real design examples.  

  16. Lower Power Design for UHF RF CMOS Circuits Based on the Power Consumption Acuity

    Directory of Open Access Journals (Sweden)

    Niu Xiang-jie

    2014-01-01

    Full Text Available Excessive energy consumption of UHF tag is the bottleneck of energy saving in its wide range of applications. To address this issue, a lower power design for UHF RF CMOS circuits based on power consumption acuity is proposed in this paper. Through in-depth analysis of the static and dynamic power generation principle of UHF RF circuits in the work, the power consumption acuity can be calculated by using the correlation of circuit power and input vector. Subsequently, under the guide of this acuity, the UHF RF CMOS circuits with better energy saving can be designed. Furthermore, according to the performance indicators of EPC CIG2 UHF RFID in UHF identification, the corresponding circuit is designed and implemented. The test results show that the design of UHF RF circuit based on the acuity of power consumption can reduce 35%–40% power consumption.

  17. Design and test challenges in Nano-scale analog and mixed CMOS technology

    OpenAIRE

    2011-01-01

    The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS)technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. ...

  18. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  19. Design of a 12-Bit 200MS/S CMOS Sample-and-Hold Circuit

    Directory of Open Access Journals (Sweden)

    Hamid Mahmoodian

    2014-07-01

    Full Text Available In this paper, a new 12bit, 200MS/s fully differential sample and hold circuit is presented. In order to increase the linearity and input voltage dynamic range; bootstrapped-switches are used for sampling the input signal. Furthermore, a tunable gain buffer is used as the output stage of the circuit to prevent the loading effects of the succeeding stages on the proposed circuit. The circuit is simulated in HSPICE using 0.35µm CMOS technology parameters. As it is discussed in the paper, simulation results justify the good performance of the proposed circuit for using in 12bit, 200MS/s applications.

  20. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  1. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  2. Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

    Science.gov (United States)

    Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

    2009-01-01

    This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

  3. Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

    Institute of Scientific and Technical Information of China (English)

    陈继伟; 石秉学

    2000-01-01

    A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.

  4. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  5. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  6. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  7. Nano-scale CMOS analog circuits models and CAD techniques for high-level design

    CERN Document Server

    Pandit, Soumya; Patra, Amit

    2014-01-01

    Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database.Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physic

  8. Stochastic process variation in deep-submicron CMOS circuits and algorithms

    CERN Document Server

    Zjajo, Amir

    2014-01-01

    One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

  9. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Directory of Open Access Journals (Sweden)

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  10. Simulations of a typical CMOS amplifier circuit using the Monte Carlo method

    OpenAIRE

    Borges, Jacques Cousteau da Silva

    2016-01-01

    In the present paper of Microelectronics, some simulations of a typical circuit of amplification, using a CMOS transistor, through the computational tools were performed. At that time, PSPICE® was used, where it was possible to observe the results, which are detailed in this work. The imperfections of the component due to manufacturing processes were obtained from simulations using the Monte Carlo method. The circuit operating point, mean and standard deviation were obtained and the influence...

  11. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-04-08

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  12. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Directory of Open Access Journals (Sweden)

    Brian Aull

    2016-04-01

    Full Text Available This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  13. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    OpenAIRE

    Brian Aull

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  14. A High Performance CMOS Current Mirror Circuit with Neuron MOSFETs and a Transimpedance Amplifier

    Science.gov (United States)

    Shimizu, Akio; Ishikawa, Yohei; Fukai, Sumio; Aikawa, Masayoshi

    In this paper, we propose a high accuracy current mirror circuit suitable for a low-voltage operation. The proposed circuit has a novel negative feedback that is composed of neuron MOSFETs and a transimpedance amplifier. As a result, the proposed circuit achieves a high accuracy current mirror circuit. At the same time, the proposed circuit monitors an error current by a low voltage because the negative feedback operates in a current-mode. The performance of the proposed circuit is evaluated using HSPICE simulation with On-Semiconductor 1.48μm CMOS device parameters. Simulation results show that the output resistance of the proposed circuit is 5.79[GΩ] and minimum operating range is 0.3[V].

  15. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  16. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    OpenAIRE

    2016-01-01

    This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k) and strained silicon FET...

  17. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2010-10-01

    Full Text Available For low-noise complementary metal-oxide-semiconductor (CMOS image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e- for the simple integration CMS and 75 dB and 2.2 e- for the folding integration CMS, respectively, are obtained.

  18. A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

    Science.gov (United States)

    Moradi, Behzad; Mirzaei, Abdolreza

    2016-11-01

    A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

  19. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Science.gov (United States)

    Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained. PMID:22163400

  20. A Full CMOS Integration Including ISFET Microsensors and Interface Circuit for Biochemical Applications

    Institute of Scientific and Technical Information of China (English)

    Jinbao Wei; Haigang Yang; Hongguang Sun; Zengjin Lin; Shanhong Xia

    2006-01-01

    One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems. This article presents a full integration of ISFET chip containing the ISFET/REFET (reference FET) pair, ISFET/REFET amplifiers, bias current generator, as well as a reference electrode structure, all integrated on the same chip based on CMOS technology. The sensor chip was fabricated in a standard 0.35 μm CMOS process (Chartered Semiconductor, Singapore). The extra post processing steps have been developed and added for depositing membranes. Finally, the pH response of the integrated sensor was measured with the interface circuit.

  1. Leakage Power Reduction and Analysis of CMOS Sequential Circuits

    Directory of Open Access Journals (Sweden)

    M. Janaki Rani

    2012-02-01

    Full Text Available A significant portion of the total power consumption in high performance digital circuits in deep sub micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

  2. CMOS DESIGN OF A MULTI_INPUT ANALOG MULTIPLIER AND DIVIDER CIRCUIT

    OpenAIRE

    2014-01-01

    This paper proposes a CMOS current-mode multi_input analog multiplier and divider circuit based on a new method. Exponential and logarithmic functions are employed to realize the circuit which is used in neural network and fuzzy integrated systems. The major advantages of this multiplier are ability of having multi_input signals, and low Total Harmonic Distortion (THD). The circuit is designed and simulated using MATLAB software and HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35μm ...

  3. Noise tolerant voltage-controlled LC oscillator circuits for deep submicron VLSI system-on-a-chip radio circuits

    OpenAIRE

    Typpö, Jukka

    2003-01-01

    This thesis studies the problems with maintaining the spectral purity of fully integrated VCO circuits for radio frequency synthesizers in single-chip system designs. LC tank circuit oscillator circuits are shown to convert amplitude variation in the tank circuit voltage into frequency modulation, if voltage dependent capacitances are present in the tank circuit. Since the parasitic capacitances of the gain transistors and the capacitance of the varactor device in a VCO circuit are voltage de...

  4. Enhancement in open-circuit voltage of implantable CMOS-compatible glucose fuel cell by improving the anodic catalyst

    Science.gov (United States)

    Niitsu, Kiichi; Ando, Takashi; Kobayashi, Atsuki; Nakazato, Kazuo

    2017-01-01

    This paper presents an implantable CMOS-compatible glucose fuel cell that generates an open-circuit voltage (OCV) of 880 mV. The developed fuel cell is solid-catalyst-based and manufactured from biocompatible materials; thus, it can be implanted to the human body. Additionally, since the cell can be manufactured using a semiconductor (CMOS) fabrication process, it can also be manufactured together with CMOS circuits on a single silicon wafer. In the literature, an implantable CMOS-compatible glucose fuel cell has been reported. However, its OCV is 192 mV, which is insufficient for CMOS circuit operation. In this work, we have enhanced the performance of the fuel cell by improving the electrocatalytic ability of the anode. The prototype with the newly proposed Pt/carbon nanotube (CNT) anode structure successfully achieved an OCV of 880 mV, which is the highest ever reported.

  5. High-Precision CMOS Analog Computational Circuits Based on a New Linearly Tunable OTA

    Directory of Open Access Journals (Sweden)

    A. Naderi Saatlo

    2016-06-01

    Full Text Available Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed trans-conductance amplifier provides a constant Gm over a wide range of input voltage which allows the implementation of high precision computational circuits including square rooting, squaring, multiplication and division functions. Layout pattern of the proposed circuit confirms that the circuit can be implemented in 102μm*69μm active area. In order to verify the performance of the circuits, the post layout simulation results are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3 parameters for 0.18 μm CMOS technology, where under supply voltage of 1.8 V, the maximum relative error of the circuits within 500 µA of input range is about 11 μA (2.2 % error and the THD remains as low as 1.2 % for the worst case. Moreover, the power dissipation of the complete structure is found to be 0.66 mW.

  6. Low Power, Reduced Dynamic Voltage Swing Domino Logic Circuits

    OpenAIRE

    Salendra.Govindarajulu; Dr.T.Jayachandra Prasad; Rangappa, P

    2010-01-01

    Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. In this work, new reduced – swing domino logic techniques which provide significant low power dissipation as compared to traditional domino cir...

  7. System and Circuit Design Aspects for CMOS Wireless Handset Receivers

    DEFF Research Database (Denmark)

    Mikkelsen, Jan H.

    contributor to LO leakage. To minimize the coupling to and from inductors the traditional approach is to use guard-ring structures. While guard-rings improve isolation they also form a trade-off between device area and performance. The relation between guard-ring area and inductor performance is evaluated...... of different receiver architectures is given and a discussion of some fundamental problems in relation to CMOS integration is addressed. Based on the standards provided for Universal Mobile Telephone System (UMTS) a set of requirements is derived for a UTRA/FDD (UMTS Terrestial Radio Access - Frequency...... Division Duplex) direct-conversion receiver (DCR). The wideband nature of the UMTS signal opens up for simple DC-offset cancellation schemes. In line of this the use of highpass filtering as a means to reduce the DC-offset is pursued using link simulations. To simplify receiver planning it is common...

  8. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  9. A single-ended CMOS sensing circuit for MEMS gyroscope with noise cancellation

    KAUST Repository

    Elsayed, Mohannad Yomn

    2010-06-01

    In this work, a complete single-ended readout circuit for capacitive MEMS gyroscope using chopper stabilization technique is presented. A novel noise cancellation technique is used to get rid of the bias noise. The circuit offers superior performance over state of the art readout circuits in terms of cost, gain, and noise for the given area and power consumption. The full circuit exhibits a gain of 58dB, a power dissipation of 1.3mW and an input referred noise of 12nV/√Hz. This would significantly improve the overall sensitivity of the gyroscope. The full circuit has been fabricated in 0.6um CMOS technology and it occupies an area of 0.4mm × 1mm. © 2010 IEEE.

  10. Analog Circuits in Ultra-Deep-Submicron CMOS

    NARCIS (Netherlands)

    Annema, Anne-Johan; Nauta, Bram; Langevelde, van Ronald; Tuinhout, Hans

    2005-01-01

    Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasin

  11. Assessing Design Activity in Complex CMOS Circuit Design.

    Science.gov (United States)

    Biswas, Gautam; And Others

    This report characterizes human problem solving in digital circuit design. Protocols of 11 different designers with varying degrees of training were analyzed by identifying the designers' problem solving strategies and discussing activity patterns that differentiate the designers. These methods are proposed as a tentative basis for assessing…

  12. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  13. Indium bump array fabrication on small CMOS circuit for flip-chip bonding

    Institute of Scientific and Technical Information of China (English)

    Huang Yuyang; Zhang Yuxiang; Yin Zhizhen; Cui Guoxin; Liu H C; Bian Lifeng; Yang Hui; Zhang Yaohui

    2011-01-01

    We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000 μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64 × 64 indium arrays with 20 μm-high,30 μm-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip.

  14. Neural CMOS-integrated circuit and its application to data classification.

    Science.gov (United States)

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  15. Custom CMOS Reed Solomon coder for the Hubble Space Telescope

    Science.gov (United States)

    Whitaker, S.; Cameron, K.; Owsley, P.; Maki, G.

    1990-01-01

    A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

  16. Design of a co-integrated CMOS/NEMS oscillator with a simple electronic circuit

    OpenAIRE

    Arndt, Grégory; Colinet, Eric; Juillard, Jérôme

    2010-01-01

    This paper presents the theoretical study of a monolithically integrated NEMS/CMOS oscillator with electrostatic actuation and piezoresistive detection. A feedback circuit based on a single active transistor is implemented. The proposed architecture is so compact that it can be implemented with ease in a sensor array application for example. A brief description of the NEMS resonator is given and the conditions for oscillation build-up are stated. We show how the co-integration allows the use ...

  17. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Science.gov (United States)

    2016-01-20

    bump bonds or through-silicon vias used in some wafer stacking processes. The process can be...function as bump bonds, but are much smaller) are patterned on each wafer and planarized along with the bonding oxide. When the wafers are bonded and...pads, the APD array is integrated with a CMOS readout circuit, using either bump bonding or a 3D integration technique. During this process

  18. A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

    Science.gov (United States)

    Srivastava, Ashok; Pulendra, Vani K.; Yellampalli, Siva

    2005-05-01

    A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at +/- 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (IPS) through the power supply voltage, VDD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, IPS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

  19. Simulations of a typical CMOS amplifier circuit using the Monte Carlo method

    Directory of Open Access Journals (Sweden)

    Borges, Jacques Cousteau da Silva

    2016-11-01

    Full Text Available In the present paper of Microelectronics, some simulations of a typical circuit of amplification, using a CMOS transistor, through the computational tools were performed. At that time, PSPICE® was used, where it was possible to observe the results, which are detailed in this work. The imperfections of the component due to manufacturing processes were obtained from simulations using the Monte Carlo method. The circuit operating point, mean and standard deviation were obtained and the influence of the threshold voltage Vth was analyzed.

  20. Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Michael S. Hsiao

    2002-01-01

    Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

  1. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  2. Nano-scale Bias-scalable CMOS Analog Computational Circuits Using Margin Propagation

    Institute of Scientific and Technical Information of China (English)

    GU Ming

    2012-01-01

    Approximation techniques are useful for implementing pattern recognizers,communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance.In our previous work,we had proposed margin propagation (MP) as an efficient piece-wise linear (PWL) approximation technique to a Iog-sumexp function and had demonstrated its advantages for implementing probabilistic decoders.In this paper,we present a systematic and a generalized approach for synthesizing analog piecewiselinear (PWL) computing circuits using the MP principle.MP circuits use only addition,subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff' s current law.Thus,unlike the conventional translinear CMOS currentmode circuits,the operation of the MP circuits are functionally similar in weak,moderate and strong inversion regimes of the MOS transistor making the design approach bias-scalable.This paper presents measured results from MP circuits prototyped in a 0.5 μm standard CMOS process verifying the bias-scalable property.As an example,we apply the synthesis approach towards designing linear classifiers and verify its performance using measured results.

  3. 116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

    Science.gov (United States)

    Shanli, Long; Yan, Liu; Kejun, He; Xinggang, Tang; Qian, Chen

    2014-09-01

    A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is -116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm2 and the current is 3.5 mA.

  4. A NOVEL HIGH PRECISION LOW POWER CURRENT MODE CMOS WINNER-TAKE-ALL CIRCUIT

    Directory of Open Access Journals (Sweden)

    K.L.Baishnab

    2010-05-01

    Full Text Available The design and simulation of winner-take –all Current Mode (WTA circuit is proposed. Inputs and outputs of the Circuits are current and voltage respectively, which makes the circuit appropriated forlow voltage neural hardware computation. The circuit was designed and simulated using Cadence gpdk090. The proposed novel current mode CMOS WTA operates at 0.7v with resolution of 0.001nA and a dynamic range from input current 10nA---1μA, which are much better than existing realizations. It is also observed that dynamic range can be raised further with increasing of power supply. Simulation results along withappropriate mathematical relations are reported.

  5. Spatio-temporal simulation in subthreshold CMOS

    Science.gov (United States)

    Neeley, John; Harris, John G.

    1997-05-01

    This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua's circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit's dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.

  6. Tuning of superconducting nanowire single-photon detector parameters for VLSI circuit testing using time-resolved emission

    Science.gov (United States)

    Bahgat Shehata, A.; Stellari, F.

    2015-01-01

    Time-Resolved Emission (TRE) is a truly non-invasive technique based on the detection of intrinsic light emitted by integrated circuits that is used for the detection of timing related faults from the backside of flip-chip VLSI circuits. Single-photon detectors with extended sensitivity in the Near Infrared (NIR) are used to perform time-correlated single-photon counting measurements and retrieve the temporal distribution of the emitted photons, thus identifying gates switching events. The noise, efficiency and jitter performance of the detector are crucial to enable ultra-low voltage waveform sensitivity. For this reason, cryogenically cooled Superconducting Nanowire Single-Photon Detectors (SNSPDs) offer superior performance compared to state-of-the-art Single-Photon Avalanche Diodes (SPADs). In this paper we will discuss how detector front-end electronics parameters, such as bias current, RF attenuation and comparator threshold, can be tailored to optimize the measurement Signal-to-Noise Ratio (SNR), defined as the ratio between the switching emission peak amplitude and the standard deviation of the noise in the time interval in which there are no photons emitted from the circuit. For example, reducing the attenuation and the threshold of the comparator used to detect switching events may lead to an improvement of the jitter, due to the better discrimination of the detector firing, but also a higher sensitivity to external electric noise disturbances. Similarly, by increasing the bias current, both the detection efficiency and the jitter improve, but the noise increases as well. For these reasons an optimization of the SNR is necessary. For this work, TRE waveforms were acquired from a 32 nm Silicon On Insulator (SOI) chip operating down to 0.4 V using different generations of SNSPD systems.

  7. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    Energy Technology Data Exchange (ETDEWEB)

    Ganesh Saripalli

    2002-12-31

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35{micro} CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  8. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    Energy Technology Data Exchange (ETDEWEB)

    Saripalli, Ganesh [Iowa State Univ., Ames, IA (United States)

    2002-01-01

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35μ CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  9. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

  10. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    Science.gov (United States)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  11. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2010-04-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  12. A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-09-01

    Full Text Available In this paper, we propose a simulation-before-test (SBT fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS analog integrated circuits (ICs interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary.In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 μm technology and the most likely faults of open circuit type are deliberately injected and simulated at the layout level.

  13. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

    Science.gov (United States)

    Sharma, Vijay Kumar; Pattanaik, Manisha

    2015-11-01

    Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

  14. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

    Science.gov (United States)

    Li, Shu; Zhang, Tong

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  15. Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

    Energy Technology Data Exchange (ETDEWEB)

    Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

    2008-05-07

    Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

  16. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  17. Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

    OpenAIRE

    Balwinder Singh; Sukhleen Bindra Narang; Arun Khosla

    2011-01-01

    Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequenceshave more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flopsresults more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on te...

  18. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  19. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  20. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  1. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  2. CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

    CERN Document Server

    Hehn, Thorsten

    2014-01-01

    This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

  3. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    赵士彬; 姚素英; 聂凯明; 徐江涛

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

  4. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    Energy Technology Data Exchange (ETDEWEB)

    Herve, C. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France)]. E-mail: herve@esrf.fr; Dzahini, D. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Le Caer, T. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France); Richer, J.-P. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Torki, K. [Laboratoire TIMA, Grenoble (France)

    2005-03-21

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 K{omega}), bandwidth (25 MHz) and noise (1570 e{sup -}+95 e{sup -}/pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements.

  5. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    OpenAIRE

    Shoji Kawahito; Min-Woong Seo

    2016-01-01

    This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise...

  6. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    Directory of Open Access Journals (Sweden)

    A. Schmitz

    2005-01-01

    Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  7. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    Science.gov (United States)

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

  8. Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Chen, Lei; Jürgen Mattausch, Hans

    2016-04-01

    As an alternative to conventional single-instruction-multiple-data (SIMD) mode solutions with massive parallelism for self-organizing-map (SOM) neural network models, this paper reports a memory-based proposal for the learning vector quantization (LVQ), which is a variant of SOM. A dual-mode LVQ system, enabling both on-chip learning and classification, is implemented by using a reconfigurable pipeline with parallel p-word input (R-PPPI) architecture. As a consequence of the reuse of R-PPPI for solving the most severe computational demands in both modes, power dissipation and Si-area consumption can be dramatically reduced in comparison to previous LVQ implementations. In addition, the designed LVQ ASIC has high flexibility with respect to feature-vector dimensionality and reference-vector number, allowing the execution of many different machine-learning applications. The fabricated test chip in 180 nm CMOS with parallel 8-word inputs and 102 K-bit on-chip memory achieves low power consumption of 66.38 mW (at 75 MHz and 1.8 V) and high learning speed of (R + 1) × \\lceil d/8 \\rceil + 10 clock cycles per d-dimensional sample vector where R is the reference-vector number.

  9. Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

    CERN Document Server

    Singh, Balwnder; Khosla, Arun; 10.5121/ijaia.2011.2302

    2011-01-01

    Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

  10. CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

    Directory of Open Access Journals (Sweden)

    Eitan N. Shauly

    2012-01-01

    Full Text Available Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed.

  11. BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count

    Institute of Scientific and Technical Information of China (English)

    Hafizur Rahaman; Debesh K. Das; Bhargab B. Bhattacharya

    2002-01-01

    This paper presents a built-in self-test (BIST) scheme for detecting all robustlytestable multiple stuck-open faults confined to any single complex cell of a CMOS circuit. Thetest pattern generator (TPG) generates all n @ 2n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n@ 2n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counterthat counts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design- or synthesis-for-testability techniques and/or additional control lines are needed.

  12. New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

    Institute of Scientific and Technical Information of China (English)

    LI Xin-yi; ZHAO Yi-qiang; YAO Su-ying

    2009-01-01

    A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.

  13. Ethanol Microsensors with a Readout Circuit Manufactured Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2015-01-01

    Full Text Available The design and fabrication of an ethanol microsensor integrated with a readout circuit on-a-chip using the complementary metal oxide semiconductor (CMOS-microelectro -mechanical system (MEMS technique are investigated. The ethanol sensor is made up of a heater, a sensitive film and interdigitated electrodes. The sensitive film is tin dioxide that is prepared by the sol-gel method. The heater is located under the interdigitated electrodes, and the sensitive film is coated on the interdigitated electrodes. The sensitive film needs a working temperature of 220 °C. The heater is employed to provide the working temperature of sensitive film. The sensor generates a change in capacitance when the sensitive film senses ethanol gas. A readout circuit is used to convert the capacitance variation of the sensor into the output frequency. Experiments show that the sensitivity of the ethanol sensor is 0.9 MHz/ppm.

  14. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the theorethical description of MOS Current Mode Logic, and it is found that it is more difficult to model and simulate the circuit with compare to standard CMOS because of the differential inputs and low voltage swing....

  15. A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-10-01

    Full Text Available In this paper, we propose a simulation-before-test (SBT fault diagnosis methodology based on the use of afault dictionary approach. This technique allows the detection and localization of the most likely defects ofopen-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS analog integratedcircuits (ICs interconnects. The fault dictionary is built by simulating the most likely defects causing thefaults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses andthe power consumption obtained by simulation are stored in a table which constitutes the fault dictionary.In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate aconsidered defect. When testing, the circuit under test is excited with the same stimulus, and the responsesobtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full customCMOS operational amplifier is implemented in 0.25 μm technology and the most likely faults of opencircuittype are deliberately injected and simulated at the layout level.

  16. Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits

    Science.gov (United States)

    1992-08-14

    more than cuit shown in Fig.5 taken from 17]. It has been shown one stuck-open trasistor in a path. Tberefore, the to- that no two partern test seqence...in Fig. 6 that inplc- trasistors . so additicinputb is required. As samed in the previous section. a non-cdeword (00 or 11) at ments t fuction F- (A.BXB...s-on faults. Tbhs has been achieved by adding just a few trasistors without af fectng the1 ,speed of the circwut. The problem of circuit delays andat

  17. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  18. EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

    Directory of Open Access Journals (Sweden)

    N. A. Avdeev

    2015-01-01

    Full Text Available A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.

  19. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  20. Low temperature radio-frequency transverse susceptibility measurements using a CMOS oscillator circuit

    Energy Technology Data Exchange (ETDEWEB)

    Figueroa, A.I., E-mail: figueroa@unizar.es [Instituto de Ciencia de Materiales de Aragon, CSIC-Universidad de Zaragoza, Departamento de Fisica de la Materia Condensada, E-50009 Zaragoza (Spain); Bartolome, J. [Instituto de Ciencia de Materiales de Aragon, CSIC-Universidad de Zaragoza, Departamento de Fisica de la Materia Condensada, E-50009 Zaragoza (Spain); Garcia del Pozo, J.M. [Servicio de Instrumentacion Electronica, Universidad de Zaragoza, E-50009 Zaragoza (Spain); Arauzo, A.; Guerrero, E. [Servicio de Medidas Fisicas, Universidad de Zaragoza, E-50009 Zaragoza (Spain); Tellez, P. [Servicio de Instrumentacion Electronica, Universidad de Zaragoza, E-50009 Zaragoza (Spain); Bartolome, F.; Garcia, L.M. [Instituto de Ciencia de Materiales de Aragon, CSIC-Universidad de Zaragoza, Departamento de Fisica de la Materia Condensada, E-50009 Zaragoza (Spain)

    2012-08-15

    A transverse susceptibility (TS) measurement system based on a simple inverter CMOS cell oscillator cross-coupled to a LC tank is presented. The system has been implemented to operate at a Quantum Design Physical Properties Measurement System (PPMS). We introduce several improvements with respect to similar currently operating TS measurement equipments. The electronics have been redesigned to use CMOS transistors as active devices, which simplifies the circuit design and enlarge the tuning range, thus making the proposed electronic block more feasible, predictable, and precise. Additionally, we propose a newly designed sample holder, which facilitates the procedure to change a sample and improves reproducibility of the circuit. Our design minimizes the thermal leak of the measuring probe by one order of magnitude, allowing to measure from 1.8 K in standard PPMS systems, thanks to the use of a low temperature beryllium-copper coaxial cable instead of the conventional RG402 Cu coaxial cable employed in the insert for the PPMS in similar systems. The data acquisition method is also simplified, so that the measuring sequences are implemented directly in the PPMS controller computer by programming them in the Quantum Design MultiVu software that controls the PPMS. We present the test measurements performed on the system without sample to study the background signal and stability of the circuit. Measurements on a Gd{sub 2}O{sub 3} calibrating sample yield to the estimation of the system sensitivity, which is found to be on the order of 10{sup -6} emu. Finally, measurements on a TmCo{sub 2} Laves phase sample with a ferrimagnetic transition temperature around 4 K are described, demonstrating that the developed system is well suited to explore interesting magnetic phenomena at this temperature scale. - Highlights: Black-Right-Pointing-Pointer An improved magnetic transverse susceptibility measurement equipment is presented. Black-Right-Pointing-Pointer The electronics of

  1. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  2. Technological and Physical Compatibilities in Hybrid Integration of Laser and Monolithic Integration of Waveguide, Photodetector and CMOS Circuits on Silicon

    NARCIS (Netherlands)

    Zhou, M.J.; Ikkink, T.; Chalmers, J.; Kranenburg, H. van; Albers, H.; Holleman, J.; Lambeck, P.V.; Joppe, J.L.; Bekman, H.H.P.T.; Krijger, A.J.T. de

    1994-01-01

    In this paper, technological and physical compatibilities in hybrid integration of AlInGaP laser and monolithic integration of ZnO monomode waveguide, pin-photodetector, CMOS circuits for laser power control and signal amplification on silicon substrate are studied. Prospective problems and their po

  3. Technological and physical compatibilities in hybrid integration of laser and monolithic integration of waveguide, photodetector and CMOS circuits on silicon

    NARCIS (Netherlands)

    Zhou, Ming-Jiang; Ikkink, Ton; Chalmers, John; Kranenburg, van Herma; Albers, Hans; Holleman, Jisk; Lambeck, Paul; Joppe, Jan Leendert; Bekman, Herman; Krijger, de Ton; Lambeck, P.V.

    1994-01-01

    In this paper, technological and physical compatibilities in hybrid integration of AlInGaP laser and monolithic integration of ZnO monomode waveguide, pin-photodetector, CMOS circuits for laser power control and signal amplification on silicon substrate are studied. Prospective problems and their po

  4. Novel design techniques for noise-tolerant power-gated CMOS circuits

    Science.gov (United States)

    Rastogi, Rumi; Pandey, Sujata

    2017-01-01

    In this paper we have investigated the single phase sleep signal modulation technique, step-wise {V}{gs} technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMOS circuits used in communication systems. The stacking technique is also implemented in this paper for the sleep transistor. The stacking approach helps to minimize leakage power. The mode transition noise minimization techniques have been applied to 32-bit dynamic TSPC adder with stacked sleep transistors in a standard 45-nm CMOS process. The reactivation noise, delay and energy consumption of all the three techniques have been evaluated. It has been shown that the three phase modulation technique significantly minimizes the reactivation delay when the peak noise level is maintained the same for all three techniques. The three phase modulation technique shows 67.3% and 35% reduction in delay compared to the single phase and step-wise {V}{gs} modulation techniques respectively. The reactivation energy is also suppressed by 49.3% and 39.14% with respect to the single-phase and stepwise {V}{gs} techniques.

  5. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

  6. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    ZHAO Shibin; YAO Suying; NIE Kaiming; XU Jiangtao

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN)cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp)sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

  7. Self-amplified CMOS image sensor using a current-mode readout circuit

    Science.gov (United States)

    Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

    2014-05-01

    The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

  8. A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG Signals

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  9. CMOS circuits for electromagnetic vibration transducers interfaces for ultra-low voltage energy harvesting

    CERN Document Server

    Maurath, Dominic

    2015-01-01

    Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100µW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over...

  10. A LOW POWER CMOS ANALOG CIRCUIT DESIGN FOR ACQUIRING MULTICHANNEL EEG SIGNALS

    Directory of Open Access Journals (Sweden)

    G. Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  11. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  12. Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

    Science.gov (United States)

    Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  13. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  14. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Science.gov (United States)

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  15. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  16. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  17. A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness

    Directory of Open Access Journals (Sweden)

    Biswabandhu Jana

    2013-10-01

    Full Text Available The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift register to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET.

  18. Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

    Directory of Open Access Journals (Sweden)

    David Bol

    2011-01-01

    Full Text Available Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

  19. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  20. Layout Design for CMOS Analog Circuit%CMOS模拟集成电路版图设计

    Institute of Scientific and Technical Information of China (English)

    解放; 罗闯

    2012-01-01

    由于模拟集成电路的性能与版图设计密切相关,着重介绍了CMOS模拟电路版图设计的一般思路,优化器件结构和平面布局使寄生效应对电路性能的影响降至最低.%Because the performance of analog circuit have great relationship with layout design, commonconsideration about layout design of CMOS analog circuit is introduced. Optimization of device structure and plane floorplan degrade the effect of parasitical to the minimum for circuit performance.

  1. 5.8 Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 μm BiCMOS

    DEFF Research Database (Denmark)

    Midtgaard, Jacob; Svensson, C.

    1994-01-01

    High speed time-division multiplexers and demultiplexers are important components of modern optical communication systems. They are needed to parallelize the data to allow most of the system to operate at much lower speeds. This paper describes a 16:1 multiplexer and a 1:16 demultiplexer implemen...... implemented on one IC in a 1.2 μm BiCMOS process. The IC combines fast ECL circuits with CMOS circuits, demonstrating that by utilizing the combination of bipolar and MOS transistors, a VLSI circuit with very high speed interface is feasible...

  2. Estimation of leakage power and delay in CMOS circuits using parametric variation

    Directory of Open Access Journals (Sweden)

    Preeti Verma

    2016-09-01

    Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

  3. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

    Institute of Scientific and Technical Information of China (English)

    Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

    2012-01-01

    Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

  4. A demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology

    CERN Document Server

    Anghinolfi, Francis; Campbell, M; Heijne, Erik H M; Jarron, Pierre; Meddeler, G; CERN. Geneva. Detector Research and Development Committee

    1990-01-01

    It is proposed to develop a demonstrator integrated circuit for particle detector analog signal processing using the advanced 1.2 micron HSOI3-HD Silicon-on-Insulator (SOI) CMOS radiation hard technology of Thomson-TMS, which has recently become accessible for selected civilian applications. The characteristics announced for this process promise survivability after a total dose in excess of 10 Mrad (SiO2) and 10**14 to 10**15 n/cm2, which is probably satisfactory for applications in LHC detector systems. The properties of such a SOI process look promising, in particular regarding speed. In view of the special analog requirements in the particle physics environment,one should verify the analog characteristics before and after irradiation by producing a demonstrator signal processing circuit which incorporates the most vital functional blocks. This demonstrator would consist of a low noise front-end amplifier, a comparator and an analog pipeline element with associated logic, following the scheme of the Hierarc...

  5. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  6. Noise analysis and characterization of a full differential CMOS interface circuit for capacitive closed-loop micro-accelerometer

    Institute of Scientific and Technical Information of China (English)

    LIU Xiao-wei; LI Hai-tao; YIN Liang; CHEN Wei-ping; SUO Chun-guang; ZHOU Zhi-ping

    2010-01-01

    To achieve a high precision capacitive closed-loop micro-accelerometer,a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit.This circuit consists of a balance-bridge module,a charge sensitive amplifier,a correlated-double-sampling module,and a logic timing control module.A special two-path feedback circuit configuration was given to improve the system linearity.The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit's noise,speed and accuracy.A detailed design method was given for this tradeoff.The noise performance optimized circuit has a noise root spectral density of 1.0 μV/√Hz,equivalent to rms noise root spectral density of1.63 μg/√Hz.Therefore,the sensor' s Brown noise becomes the main noise source in this design.This circuit is designed with 0.5 μm n-well CMOS process.Under a ± 5 V supply,the Hspice simulation shows that the system sensitivity achieves 0.616 V/g,the system offset is as low as 1.456 mV,the non-linearity is below0.03%,and the system linear range achieves ±5 g.

  7. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  8. Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

    CERN Document Server

    Mukhopadhyay, Saibal; Roy, Kaushik

    2011-01-01

    In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power in a logic circuit. Leakage components interact with each other in device level (through device geometry, doping profile) and also in the circuit level (through node voltages). Due to the circuit level interaction of the different leakage components, the leakage of a logic gate strongly depends on the circuit topology i.e. number and nature of the other logic gates connected to its input and output. In this paper, for the first time, we have analyzed loading effect on leakage and proposed a method to accurately estimate the total leakage in a logic circuit, from its logic level description considering the impact of loading and transistor stacking.

  9. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  10. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  11. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  12. Portable optical epidural needle-a CMOS-based system solution and its circuit design.

    Science.gov (United States)

    Gong, Cihun-Siyong Alex; Lin, Shih-Pin; Mandell, M Susan; Tsou, Mei-Yung; Chang, Yin; Ting, Chien-Kun

    2014-01-01

    Epidural anesthesia is a common anesthesia method yet up to 10% of procedures fail to provide adequate analgesia. This is usually due to misinterpreting the tactile information derived from the advancing needle through the complex tissue planes. Incorrect placement also can cause dural puncture and neural injury. We developed an optic system capable of reliably identifying tissue planes surrounding the epidural space. However the new technology was too large and cumbersome for practical clinical use. We present a miniaturized version of our optic system using chip technology (first generation CMOS-based system) for logic functions. The new system was connected to an alarm that was triggered once the optic properties of the epidural were identified. The aims of this study were to test our miniaturized system in a porcine model and describe the technology to build this new clinical tool. Our system was tested in a porcine model and identified the epidural space in the lumbar, low and high thoracic regions of the spine. The new technology identified the epidural space in all but 1 of 46 attempts. Experimental results from our fabricated integrated circuit and animal study show the new tool has future clinical potential.

  13. Portable optical epidural needle-a CMOS-based system solution and its circuit design.

    Directory of Open Access Journals (Sweden)

    Cihun-Siyong Alex Gong

    Full Text Available Epidural anesthesia is a common anesthesia method yet up to 10% of procedures fail to provide adequate analgesia. This is usually due to misinterpreting the tactile information derived from the advancing needle through the complex tissue planes. Incorrect placement also can cause dural puncture and neural injury. We developed an optic system capable of reliably identifying tissue planes surrounding the epidural space. However the new technology was too large and cumbersome for practical clinical use. We present a miniaturized version of our optic system using chip technology (first generation CMOS-based system for logic functions. The new system was connected to an alarm that was triggered once the optic properties of the epidural were identified. The aims of this study were to test our miniaturized system in a porcine model and describe the technology to build this new clinical tool. Our system was tested in a porcine model and identified the epidural space in the lumbar, low and high thoracic regions of the spine. The new technology identified the epidural space in all but 1 of 46 attempts. Experimental results from our fabricated integrated circuit and animal study show the new tool has future clinical potential.

  14. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  15. Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

    Science.gov (United States)

    Roever, Stefan

    2012-01-01

    A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

  16. Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors

    Science.gov (United States)

    Kawahito, Shoji; Itoh, Shinya

    2008-02-01

    A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.

  17. Bulk CMOS VLSI Technology Studies. Part 5. The Design and Implementation of a High Speed Integrated Circuit Functional Tester.

    Science.gov (United States)

    2014-09-26

    169 7404 Inverter Test ...... ................ 171 7482 Binary Adder Test .... .............. .174 REFERENCES ......... ......................... 176...tests run on a 7404 HEX INVERTER and a 7482 2-BIT BINARY FULL ADDER , are presented in Appendix E, TEST RESULTS...RAM, a 7404 HEX INVERTER, and a 7482 2-BIT FULL ADDER . These results indicate that the functional tester operates according to the specifications

  18. Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

    Directory of Open Access Journals (Sweden)

    Adhiyaman P1 ,

    2014-03-01

    Full Text Available In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF and a novel embedded logic module (DDFF-ELM based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.

  19. Flip-flop design in nanometer CMOS from high speed to low energy

    CERN Document Server

    Alioto, Massimo; Palumbo, Gaetano

    2015-01-01

    This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gai...

  20. SEMICONDUCTOR INTEGRATED CIRCUITS A novel 2.2 Gbps LVDS driver circuit design based on 0.35 μm CMOS

    Science.gov (United States)

    Hua, Cai; Ping, Li

    2010-10-01

    This paper presents a novel high-speed low voltage differential signaling (LVDS) driver design for point-to-point communication. The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased. A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage. The proposed driver was implemented in a standard 0.35 μm CMOS process with a die area of 0.15 mm2. The test result shows that the proposed driver works well at 2.2 Gbps with power consumption of only 23 mW and 21.35 ps peak-to-peak jitter under a 1.8 V power supply.

  1. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  2. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  3. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  4. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  5. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  6. A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 µm CMOS Process

    Directory of Open Access Journals (Sweden)

    Noor A.B.A. Taib

    2013-03-01

    Full Text Available Digital to (DAC is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 µm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 µm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

  7. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    KAUST Repository

    Alhoshany, Abdulaziz

    2017-08-23

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  8. New Programmable CMOS Fuzzifier and C2V Circuits Applicable in FLC Chip for Signal Processing of MEMS Glucose Sensors

    Directory of Open Access Journals (Sweden)

    Ghader Yosefi

    2015-08-01

    Full Text Available This paper presents the design and simulation of improved circuits of Fuzzifier and capacitance to voltage (C2V converter. The Fuzzifier circuit is designed based on analog advantages such as low die area, high accuracy, and simplicity which are added to the fuzzy system advantages. For implementing this idea, a programmable Membership Function Generator (MFG including differential pair circuit as a Fuzzifier is proposed. The MFG generates arbitrary forms of Gaussian, Trapezoidal, and Triangular shapes. The shape types are achieved using control switches and different reference voltages. This structure is also general purpose in tuning the slope of Membership Functions (MFs using scaled transistors with different W/L ratios. With a specific purpose in mind, we used it here to generate fuzzy language terms from sensed classic data of a blood glucose microsensor. Thus we proposed a C2V circuit to convert capacitance variations (from MEMS glucose microsensor to voltage values as classic data. The proposed mentioned circuits can be applicable in design of Fuzzy Logic Controller (FLC chips to detect blood glucose, process its data in Fuzzy environment, and control insulin injection of diabetic patients by MEMS micropumps. The simulation results are achieved by MATLAB and Hspice software in 0.35 μm CMOS standard technology.

  9. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  10. Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

    Directory of Open Access Journals (Sweden)

    Sun Lijie

    2015-01-01

    Full Text Available In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC and the temperature-dependent voltage characteristics (TDVC from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.

  11. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Science.gov (United States)

    Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

    2009-01-01

    This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

  12. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2009-02-01

    Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

  13. An Acetone Microsensor with a Ring Oscillator Circuit Fabricated Using the Commercial 0.18 μm CMOS Process

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2014-07-01

    Full Text Available This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

  14. Power management of digital circuits in deep sub-micron CMOS technologies

    CERN Document Server

    Henzler, Stephan

    2006-01-01

    In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. This book mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.

  15. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    Energy Technology Data Exchange (ETDEWEB)

    Ko, Hyoungho [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Sangjun [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Paik, Seung-Joon [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Choi, Byoung-doo [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Yonghwa [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Lee, Sangmin [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Kim, Sungwook [SML Electronics, Inc. (Korea, Republic of); Lee, Sang Chul [SML Electronics, Inc. (Korea, Republic of); Lee, Ahra [SML Electronics, Inc. (Korea, Republic of); Yoo, Kwangho [SML Electronics, Inc. (Korea, Republic of); Lim, Jaesang [SML Electronics, Inc. (Korea, Republic of); Cho, Dong-il [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of)

    2006-04-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 {mu}m BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 {mu}g/{radical}Hz, the bias instability of 490 {mu}g, the input range of {+-}10 g, and the output nonlinearity of {+-}0.5 %FSO.

  16. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

    Institute of Scientific and Technical Information of China (English)

    Liu Zhen; Jia Song; Wang Yuan; Ji Lijiu; Zhang Xing

    2009-01-01

    This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

  17. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  18. A VLSI Implementation of a New Low Voltage 5th Order Differential Gm-C Low-Pass Filter with Auto-Tuning Loop in CMOS Technology

    Directory of Open Access Journals (Sweden)

    BOZOMITU, R. G.

    2011-02-01

    Full Text Available In this paper a new low voltage 5th order Gm-C Bessel type low-pass filter (LPF with auto-tuning loop and higher dynamic range, designed in CMOS technology, is presented. The cut-off frequency can be tuned in (10-42MHz range by modifying the values of the grounded capacitors using a digital logic. The proposed structure is based on an auto-tuning loop in order to maintain the Gm/C ratio independent of the process, supply voltage and temperature variations, assuring the cut-off frequency of the LPF independently of these factors. The proposed 5th order Gm-C Bessel type low-pass filter provides 5% variation of the cut-off frequency in all critical corners, a 400mVpp(diff dynamic range, THD less than 1% and 21.6mW power consumption from 1.8V supply voltage. The simulations performed in 65nm CMOS process confirm the theoretical results.

  19. Analog preprocessing in a SNS 2 micrometers low-noise CMOS folding ADC

    Science.gov (United States)

    Carr, Richard D.

    1994-12-01

    Significant research in high performance analog-to-digital converters (ADC's) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can be used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and power consumption of the ADC. This thesis examines a Very Large Scale Integrated (VLSI) design for a folding circuit for a SNS analog preprocessing architecture in a 9-bit folding ADC with a total of 23 comparators. The analog folding circuit layout uses the Orbit 2 micrometers CMOS N-well double-metal, double-poly low-noise analog process. The effects of Spice level 2 parameter tolerances during fabrication on the operation of the folding circuit are investigated numerically. The frequency response of the circuit is also quantified. An Application Specific Integrated Circuit (ASIC) is designed.

  20. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  1. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Science.gov (United States)

    Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

    2017-09-01

    Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  2. A novel offset cancellation based on parasitic-insensitive switched-capacitor sensing circuit for the out-of-plane single-Gimbaled decoupled CMOS-MEMS gyroscope.

    Science.gov (United States)

    Chang, Ming-Hui; Huang, Han-Pang

    2013-03-14

    This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement.

  3. A Novel Offset Cancellation Based on Parasitic-Insensitive Switched-Capacitor Sensing Circuit for the Out-of-Plane Single-Gimbaled Decoupled CMOS-MEMS Gyroscope

    Directory of Open Access Journals (Sweden)

    Han-Pang Huang

    2013-03-01

    Full Text Available This paper presents a novel parasitic-insensitive switched-capacitor (PISC sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG. According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement.

  4. Four-Bit Cmos Full Adder Design in Submicron Technology with Low Leakage Power and Ground Bounce Noise Reduction Using Dual Sleep Approach

    Directory of Open Access Journals (Sweden)

    Jagadeesh Yabaku

    2013-03-01

    Full Text Available In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using dual stack approach without being penalized in area requirement and circuit performance.

  5. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  6. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    Science.gov (United States)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  7. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

    Science.gov (United States)

    Kawahito, Shoji; Seo, Min-Woong

    2016-11-06

    This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e(-)rms) when compared with the CMS gain of two (2.4 e(-)rms), or 16 (1.1 e(-)rms).

  8. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2016-11-01

    Full Text Available This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs. This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC. The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median: 0.29 e−rms when compared with the CMS gain of two (2.4 e−rms, or 16 (1.1 e−rms.

  9. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  10. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  11. Research and Design of Anti-radiation Analog CMOS Integrated Circuits%抗辐射模拟CMOS集成电路研究与设计

    Institute of Scientific and Technical Information of China (English)

    赵源; 徐立新; 赵琦; 金星

    2013-01-01

    The characteristics and effects of analog CMOS integrated circuit on spacecraft were analyzed in the radiation environment.Based on the generation of radiation effect,the main anti-radiation design methods were introduced for the analog CMOS integrated circuit designing and processing.In the outer space,threshold voltage deviation,transdiode decreasing,substrate leakage current increasing and corner noise amplitude increasing occur to the CMOS semiconductor components in the analog CMOS integrated circuit.As a result,there are three kinds of methods proposed to protect against radiation of the analog integrated circuits,including anti-radiation analog CMOS integrated circuit',anti-radiation PCB' and silicon on insulator anti-radiation processing.Accordingly,the designed anti-radiation analog CMOS integrated circuits obtain the ideal effect in anti-radiation function.%为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法.在宇宙环境中,卫星中的模拟CMOS集成电路存在CMOS半导体元器件阈值电压偏离、线性跨导减小、衬底的漏电流增加和转角1/f噪声幅值增加.所以提出了3种对模拟CMOS集成电路进行抗辐射加固的方法:1)抗辐射模拟CMOS集成电路的设计;2)抗辐射集成电路版图设计;3)单晶半导体硅膜(Silicon on Insulator,SOI)抗辐射工艺与加固设计.根据上面的设计方法研制了抗辐射加固模拟CMOS集成电路,可以取得较好的抗辐射效果.

  12. A Transistor Sizing Tool for Optimization of Analog CMOS Circuits: TSOp

    Directory of Open Access Journals (Sweden)

    Y.C.Wong

    2015-02-01

    Full Text Available Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. It is highly desirable to automate the transistor sizing process towards being able to rapidly design high performance integrated circuit. Presented here is a simple but effective algorithm for automatically optimizing the circuit parameters by exploiting the relationships among the genetic algorithm's coefficient values derived from the analog circuit design variables. Simulation results demonstrate that the proposed algorithm (TSOp converges to optimal solutions efficiently for the circuits which contain discrete or discontinuous parameters constraints in a large search spaces. The robustness of TSOp has been verified by using a cascaded amplifier assisted inverter and an operational amplifier circuitries based on TSMC 0.25um process technology. Even though with a large number of design variables, TSOp successfully converges to a range of optimum solution for the targeted circuit performance. TSOp achieves optimum solutions and simplifies the design steps in developing an analog circuit, thereby significantly improving the time to market for an integrated circuit chip.

  13. Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

    Science.gov (United States)

    Morita, Yukinori; Fukuda, Koichi; Liu, Yongxun; Mori, Takahiro; Mizubayashi, Wataru; O'uchi, Shin-ichi; Fuketa, Hiroshi; Otsuka, Shintaro; Migita, Shinji; Masahara, Meishoku; Endo, Kazuhiko; Ota, Hiroyuki; Matsukawa, Takashi

    2017-04-01

    We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

  14. Turn-on circuits based on standard CMOS technology for active RFID labels

    Science.gov (United States)

    Hall, David; Ranasinghe, Damith C.; Jamali, Behnam; Cole, Peter H.

    2005-06-01

    The evolution of RFID Systems has lead to the development of a class hierarchy in which the battery powered labels are a set of higher class labels referred to as active labels. The battery powering active transponders must last for an acceptable time, so the electronics of the label must have very low current consumption in order to prolong the life of the battery. However due to circuit complexity or the desired operating range the electronics may drain the battery more rapidly than desired but use of a turn-on circuit allows the battery to be connected only when communication is needed, thus lengthening the life of the battery. Two solutions available for the development of a turn on circuit use resonance in a label rectification circuit to provide a high sensitivity result. This paper presents the results of experiments conducted to evaluate resonance in a label rectification circuit and the designs of fully integrable turn-on circuits. We have also presented test results showing a successful practical implementation of one of the turn on circuit designs.

  15. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley, Colpitts, and Common-Source Cross-Coupled Differential Pair

    Directory of Open Access Journals (Sweden)

    Ilias Chlis

    2014-01-01

    Full Text Available This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  16. Comparative analyses of phase noise in 28 nm CMOS LC oscillator circuit topologies: Hartley, Colpitts, and common-source cross-coupled differential pair.

    Science.gov (United States)

    Chlis, Ilias; Pepe, Domenico; Zito, Domenico

    2014-01-01

    This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

  17. New Approach to Low-Power & Leakage Current Reduction Technique for CMOS Circuit Design

    Directory of Open Access Journals (Sweden)

    Sujata Prajapati

    2014-02-01

    Full Text Available Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap for Semiconductors (IRTS. This directly affects the battery operated devices as it has long idle times. Thus by scaling down the threshold voltage has tremendously increased the sub threshold leakage current thereby making the static power dissipation very high. To overcome this problem several techniques has been proposed to overcome this high leakage power dissipation. A comprehensive survey and analysis of various leakage power minimization techniques is presented in this paper. Of the available techniques, eight techniques are considered for the analysis namely, Multi Threshold CMOS (MTCMOS, Super Cut-off CMOS (SCCMOS, Forced Transistor Stacking (FTS and Sleepy Stack (SS, Sleepy keeper (SK, Dual Stack (OS, and LECTOR. From the results, it is observed that Lector techniques produces lower power dissipation than the other techniques due to the ability of power gating.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS: Low power CMOS preamplifier for neural recording applications

    Science.gov (United States)

    Xu, Zhang; Weihua, Pei; Beiju, Huang; Hongda, Chen

    2010-04-01

    A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

  19. Design of Traditional CMOS to Adiabatic CMOS Interface Circuit%传统CMOS到绝热CMOS接口电路的设计

    Institute of Scientific and Technical Information of China (English)

    郁军军; 汪鹏君

    2006-01-01

    通过对传统CMOS与绝热CMOS接口电路的研究,在分析传统CMOS信号和绝热信号的时序关系的基础上提出了三种传统CMOS到绝热CMOS(Traditional CMOS to Adiabatic CMOS,TC/AC)接口电路的设计方案,实现了将传统CMOS信号到绝热信号的转变.最后HSPICE模拟验证了所设计的三种TC/AC接口电路逻辑功能的正确性.

  20. SEMICONDUCTOR INTEGRATED CIRCUITS: Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

    Science.gov (United States)

    Xiushan, Wu; Zhigong, Wang; Zhiqun, Li; Jun, Xia; Qing, Li

    2010-08-01

    A fully integrated cross-coupled LC tank voltage-controlled oscillator (LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is -125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz, while the VCO core circuit draws only 640 μW from a 0.4-V supply. The designed VCO can cover a frequency range from 2.28 to 2.48 GHz. The tuning range of the circuit is 200 MHz (8.7%) and the FOM is -195.7 dB, which is suitable for an IEEE 802.11b receiver.

  1. A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.

    Science.gov (United States)

    Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo

    2013-09-01

    Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.

  2. 绝热CMOS与传统CMOS接口电路的设计%Design of adiabatic CMOS and traditional CMOS interface circuit

    Institute of Scientific and Technical Information of China (English)

    郁军军; 汪鹏君

    2007-01-01

    为了将绝热CMOS电路嵌入到传统电路系统中替代耗能较大的部件,本文研究并设计绝热CMOS电路和传统CMOS电路两者之间的接口电路:传统CMOS到绝热CMOS(Traditional CMOS to Adiabatic CMOS,TC/AC)的接口电路、绝热CMOS到传统CMOS(Adiabatic CMOS to Traditional CMOS,AC/TC)的接口电路.这样传统CMOS电路可以通过TC/AC接口电路来驱动绝热CMOS电路,绝热CMOS电路可以通过AC/TC接口电路来驱动传统CMOS电路,从而可以利用具低功耗特性的绝热CMOS电路来降低整个电路系统的功耗,增强绝热CMOS电路的实用性.最后计算机模拟验证了TC/AC接口电路和AC/TC接口电路逻辑功能的正确性.

  3. Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

    Science.gov (United States)

    You, Y.; Huang, D.; Chen, J.; Gong, D.; Liu, T.; Ye, J.

    2014-01-01

    We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

  4. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  5. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  6. CMOS-based carbon nanotube pass-transistor logic integrated circuits.

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-02-14

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

  7. Self-Biasing High Precision CMOS Current Subtractor for Current-Mode Circuits

    Directory of Open Access Journals (Sweden)

    ARSLAN, E.

    2013-11-01

    Full Text Available In this study, a novel, differential pair based, high performance and high bandwidth current subtractor is proposed. Very low equivalent impedances are obtained at input ports n and p by using source follower transistors. Furthermore, the proposed circuit is self-biasing which makes it resistant to process, supply voltage and temperature variations. The proposed current subtractor can be used as an input stage for current-mode active circuits like current differencing buffered amplifier (CDBA, operational transresistance amplifier (OTRA and current differencing transconductance amplifier (CDTA which employ current subtractors. A numeric figure-of-merit is defined and it is used to demonstrate the superior performance of the proposed circuit.

  8. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  9. Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

    CERN Document Server

    Gielen, Georges; Christie, Phillip; Draxelmayr, Dieter; Janssens, Edmond; Maex, Karen; Vucurevich, Ted

    2011-01-01

    This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

  10. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  11. 0.5μm Partially Depleted CMOS/SOI Device and Circuit%0.5μm SOI CMOS器件和电路

    Institute of Scientific and Technical Information of China (English)

    刘新宇; 孙海峰; 海朝和; 吴德馨

    2001-01-01

    研究了0.5μm SOI CMOS器件和电路,开发出成套的0.5μm SOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路,其中当工作电压为3V时,0.5μm 101级环振单级延迟为42ps.同时,对部分耗尽SOI器件特性,如“浮体”效应、“kink”效应和反常亚阈值特性进行了讨论.%The partially depleted CMOS/SOI device and circuit with channel length of 0.5μm have been studied,and the Complete 0.5μm CMOS/SOI technology been developed as well.Well-behaved devices and circuits are obtained,with the per-stage propagation delay of 101-stage 0.5μm CMOS/SOI ring oscillator being 42ps under 3V supply voltage.Some characteristics of the partially depleted CMOS/SOI device are also discussed,such as “float-body” effect,“kink” effect,and anomalous subthreshold characteristics,etc.

  12. Adiabatic Improved Efficient Charge Recovery Logic for Low Power CMOS Logic

    Directory of Open Access Journals (Sweden)

    Prof. Mukesh Tiwar

    2012-08-01

    Full Text Available Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from its switching activity, which is mainly influenced by the supply voltage and effective capacitance. The low-power requirements of present electronic systems have challenged the scientific research towards the study of technological, architectural and circuital solutions that allow a reduction of the energy dissipated by an electronic circuit. One of the main causes of energy dissipation in CMOS circuits is due to the charging and discharging of the node capacitances of the circuits, present both as a load and as parasitic. Such part of the total power dissipated by a circuit is called dynamic power. In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching technique is use. Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. The term adiabatic comes from thermodynamics, used to describe a process in which there is no exchange of heat with the environment. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. The adiabatic switching technique can achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. Power reduction is achieved by recovering the energy in the recover phase of the supply clock.

  13. How to deal with substrate bounce in analog circuits in epi-type CMOS technology

    NARCIS (Netherlands)

    Nauta, Bram; Hoogzaad, Gian; Donnay, S.; Gielen, G.

    2003-01-01

    Substrate noise is one of the key problems in mixed analog/digital ICs. Although measures are known to reduce substrate noise, the noise will never be completely eliminated since this requires larger chip area or exotic packages and thus higher cost. Analog circuits on digital ICs simply have to be

  14. Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model

    NARCIS (Netherlands)

    Wallinga, Hans; Bult, Klaas

    1989-01-01

    A graphical representation of a simple MOST (metal-oxide-semiconductor transistor) model for the analysis of analog MOS circuits operating in strong inversion is given. It visualizes the principles of signal-processing techniques depending on the characteristics of an MOS transistor. Several lineari

  15. Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator

    Directory of Open Access Journals (Sweden)

    Sushil Kumar

    2012-07-01

    Full Text Available This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS very large scale integrated circuits (VLSI is a challenging task for the integrated circuit(ICdesigner. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine stages. Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency of oscillation.

  16. Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator

    Directory of Open Access Journals (Sweden)

    Sushil Kumar

    2012-06-01

    Full Text Available This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS very large scale integrated circuits (VLSI is a challenging task for the integrated circuit(ICdesigner. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine stages. Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency of oscillation.

  17. Integrated Circuit of CMOS DC-DC Buck Converter with Differential Active Inductor

    Directory of Open Access Journals (Sweden)

    Kaoutar Elbakkar

    2011-11-01

    Full Text Available In this paper, we propose a new design of DC-DC buck converter (BC, which the spiral inductor is replaced by a differential gyrator with capacitor load (gyrator-C implemented in 0.18um CMOS process. The gyrator-C transforms the capacitor load (which is the parasitic capacitor of MOSFETS to differential active inductor DAI. The low-Q value of DAI at switching frequency of converter (few hundred kHz is boosted by adding a negative impedance converter (NIC. The transistor parameters of DAI and NIC can be properly chosen to achieve the desirable value of equivalent inductance L (few tens H, and the maximum-Q value at the switching frequency, and thus the efficiency of converter is improved. Experimental results show that the converter supplied with an input voltage of 1V, provides an output voltage of 0.74V and output ripple voltage of 10mV at 155 kHz and Q-value is maximum (#8776;4226 at this frequency.

  18. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  19. A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic Structure

    Directory of Open Access Journals (Sweden)

    PADMA KHARE

    2014-09-01

    Full Text Available Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy metric is used for the analysis of noise tolerance of proposed CGS. A 2- input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.

  20. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  1. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  2. SiGe BiCMOS front-end circuits for X-Band phased arrays

    OpenAIRE

    2012-01-01

    The current Transmit/Receive (T/R) modules have typically been implemented using GaAs- and InP-based discrete monolithic microwave integrated circuits (MMIC) to meet the high performance requirement of the present X-Band phased arrays. However their cost, size, weight, power consumption and complexity restrict phased array technology only to certain military and satellite applications which can tolerate these limitations. Therefore, next generation X-Band phased array radar systems aim to use...

  3. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-06-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range, analog and mixed integrated circuit (IC design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layout simulation results.

  4. Performance Analysis of Modified QSERL Circuit

    Directory of Open Access Journals (Sweden)

    Shipra Upadhyay

    2013-08-01

    Full Text Available This work is based on a new approach for minimizing energy consumption in quasi static energy recoverylogic (QSERL circuit which involves optimization by removing the non adiabatic losses completely.Energy recovering circuitry based on adiabatic principles is a promising technique leading towards lowpowerhigh performance circuit design. The efficiency of such circuits may be increased by reducing theadiabatic and non-adiabatic losses drawn by them during the charging and recovery operations. In thispaper, performance of the proposed logic style is analyzed and compared with CMOS in theirrepresentative inverters, gates, flip flops and adder circuits. All the circuits were simulated by VIRTUOSOSPECTRE simulator of Cadence in 0.18μm technology. In our proposed inverter the energy efficiency hasbeen improved to almost 30% & 20% upto 20MHz and 20fF external load capacitance in comparison toCMOS & QSERL circuits respectively. Our proposed circuit provides energy efficient performance up to100 MHz and thus it has proven to be used in high-performance VLSI circuitry.

  5. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  6. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  7. A new equivalent circuit model for on-chip spiral transformers in CMOS RFICs

    Institute of Scientific and Technical Information of China (English)

    Wei Jiaju; Wang Zhigong; Li Zhiqun; Tang Lu

    2012-01-01

    A new compact model has been introduced to model on-chip spiral transformers.Unlike conventional models,which are often a compound of two spiral inductor models (i.e.,the combination of two coupled Π or 2-Π sub-circuits),our new model only uses 12 elements to model the whole structure in the form ofT topology.The new model is based on the physical meaning,and the process of model derivation is also presented.In addition,a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization.In this procedure,a new method has been developed for the parameter extraction of the ladder circuit,which is commonly used to represent the skin effect.In order to verify the model's validity and accuracy,we have compared the simulated and measured self-inductance,quality factor,coupling coefficient and insertion loss,and an excellent agreement has been found over a broad frequency range up to the resonant frequency.

  8. Timing Simulation of Metastability and Soft Errors in CMOS Interface Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Prof. Soheb Munir

    2013-11-01

    Full Text Available Metastability is a widespread phenomenon and errors may occur in any synchronous circuit where an input signal can change randomly with respect to a reference signal. The reference signal may be either a voltage based reference, such as a bias voltage, or a time based reference, such as a clock signal. Circuits in which metastability can occur include analog-to-digital converters, memories, time digitizers, and bus controllers etc.. During the sampling phase, flip-flop accepts input data (D at an arbitrary time and produces output (Q that aligns to the clock signal (CLK. It has an aperture defined by the setup and hold time around the rising/falling edge of the clock. If the data transitions outside of the aperture, Q (Q_Stable should equal D. If the data changes during the aperture, the value of Q (Q_Metastable may enter the metastable region resulting in a long time for Q to resolve to a stable value and therefore an unpredictable final value of Q. Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state; at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.

  9. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  10. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  11. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  12. 用遗传算法 实现CMOS时序电路最大功耗估计%Maximum Power Estimation for CMOS Sequ ential Circuits by Genetic Algorithm

    Institute of Scientific and Technical Information of China (English)

    卢君明; 林争辉

    2001-01-01

    Estimation of maximum power dissipation is importa nt indesigning highly reliable VLSI systems. However, maximum power estimation for CMOS circuits is essentially a combination optimization pro blem, which has exponential complexity in the worst case. For large-scaled sequential circuits, due to the fact that the sequential rela tionship between the Primary Inputs and States must be considered, it is more CPU time intensive to exhaustively search for the optimal input patterns to induce maximum power. In this paper, a novel approach is proposed to obtain a lower bound of the maximum power consumption using Genetic Algorithm (GA). Experiments with ISCAS-89 benchmark circuits show that our approach generates the lower bound with the qua lity that cannot be achieved using simulation-based techniques. In addition, a Monte Carlo based technique to estimate maximum pow er dissipation is realized.%最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的。实际中,总是在有限的计算时间内获取一个近似最大功耗。文中用遗传算法来选择具有高功耗的输入及内部状态模型,对电路进行仿真,实现时序电路的最大功耗估算;同时,实现了基于统计的逻辑模拟最大功耗估计方法。基于ISCAS89基准时序电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高。而且新方法的计算时间基本上是电路逻辑门的线性关系。

  13. Fully Scaled 0.5 Micron CMOS Technology Using Variable Shaped Electron Beam Lithography

    Science.gov (United States)

    Coane, Philip; Rudeck, Paul; Wang, Li-Kong; Wilson, Alan; Hohn, Fritz

    1988-06-01

    Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpasssed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. In principle, variable shaped electron beam systems are capable of writing linewidths down to at least 0.1 micron. However, the successful application of sub-micron scaling principles to device fabrication involves an integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5 micron CMOS technology developed for VLSI appli-cations. Significant gains in both density and performance at reduced power supply levels are realized over previously reported 1.0 micron technology. The details of the integrated lithography strategy used to achieve these results are presented.

  14. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  15. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  16. Designing Low Power Circuits: A Review

    Directory of Open Access Journals (Sweden)

    Rohan M Joshi

    2012-09-01

    Full Text Available The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented.

  17. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  18. Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

    Science.gov (United States)

    Deshmukh, Jyoti; Khare, Kavita

    2012-12-01

    In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8 V, 75°C demonstrate power reduction by 59.4% in case of 1 bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1 bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45 V applied in active mode improves the maximum operating frequency by 16% in case of 1 bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.

  19. Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design

    Directory of Open Access Journals (Sweden)

    Kiran Agarwal Gupta

    2012-10-01

    Full Text Available Semiconductor technology has reached an end in the manufacture of conventional Metal Oxide semiconductor Field Effect Transistor (MOSFET. The continuous scaling of semiconductor devices has kept pace with Moore’s law and transistors below 1µm are grouped under deep sub-micron (DSM technology node. But this trend seem to end beyond deep sub micron levels due to main design constraints such as short channel effects (SCE , and variations in process design parameters leading to high leakage currents. Silicon material processes technology has undergone a change in process material and technology beyond 180nm node. For DSM technology nodes leakage current dominates the devices. Circuit designing using MOSFETs at deep sub micron levels, needs a careful study of the behaviour of short channel devices for the parameter variations such as threshold voltage, channel length leading to high leakage currents and poor performance of devices. In this paper we have presented the behaviour of NMOS metal oxide semiconductor field effect transistor (MOSFETs for 90nm technology node in detail and finally compared with 180nm and 45nm nodes. The simulations have been carried out using libraries from TSMC foundry and the device has been simulated using Virtuoso Cadence Spectre Simulator version 6.1.5 with HSPICE.

  20. Device Characterisation of Short Channel Devices and its Impact on CMOS Circuit Design

    Directory of Open Access Journals (Sweden)

    Kiran Agarwal Gupta

    2012-11-01

    Full Text Available Semiconductor technology has reached an end in the manufacture of conventional Metal Oxide semiconductor Field Effect Transistor (MOSFET. The continuous scaling of semiconductor devices has kept pace with Moore’s law and transistors below 1µm are grouped under deep sub-micron (DSM technology node. But this trend seem to end beyond deep sub micron levels due to main design constraints such as short channel effects (SCE , and variations in process design parameters leading to high leakage currents. Silicon material processes technology has undergone a change in process material and technology beyond 180nm node. For DSM technology nodes leakage current dominates the devices. Circuit designing using MOSFETs at deep sub micron levels, needs a careful study of the behaviour of short channel devices for the parameter variations such as threshold voltage, channel length leading to highleakage currents and poor performance of devices. In this paper we have presented the behaviour of NMOS metal oxide semiconductor field effect transistor (MOSFETs for 90nm technology node in detail and finally compared with 180nm and 45nm nodes. The simulations have been carried out using libraries fromTSMC foundry and the device has been simulated using Virtuoso Cadence Spectre Simulator version 6.1.5 with HSPICE.

  1. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  2. A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

    Science.gov (United States)

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-03-15

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

  3. 5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Science.gov (United States)

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  4. A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2013-03-01

    Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

  5. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  6. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  7. 一种自动体偏置多阈值电压高温 SOI CMOS电路%New auto- bulk- biased multi- threshold SOI CMOS circuit operating at high temperature

    Institute of Scientific and Technical Information of China (English)

    张海鹏; 魏同立; 杨国勇; 冯耀兰; 宋安飞

    2001-01-01

    提出了一种高温 SOI CMOS电路设计方法—自动体偏置多阈值电压 SOI CMOS(简称 ABB- MT- SOI CMOS: Auto- Bulk- Biased Multi- Threshold SOI CMOS)电路。文中主要讨论了 ABB- MT- SOI CMOS电路的结构与工作原理 ,设计与布局等,给出了内部电路电压和电流的模拟结果, 并简述了该电路的应用前景。%A new design method of SOI CMOS circuits, a auto- bulk- biased multi- threshold SOI CMOS circuit(Abbreviated as “ ABB- MT- SOI CMOS” ),is put forward. The concept and structure of circuit are presented at first,then followed by the circuit implementation and its operating principle at high temperature, the considerations of its design and layout and the application potential of this kind of SOI CMOS circuits.

  8. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  9. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  10. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  11. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-07-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layoutsimulation results.

  12. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  13. A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

    Energy Technology Data Exchange (ETDEWEB)

    Krit, Salahddine; Qjidaa, Hassan; Affar, Imad El; Khadija, Yafrah; Messghati, Ziani; El-Ghzizal, Yassir, E-mail: krit_salah@yahoo.f, E-mail: qjidah@yahoo.f [Faculty of Sciences Dhar El Mehraz, Laboratory of Electronic, Signal-Systymes and Informatic (LESSI) Fes (Morocco)

    2010-04-15

    This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-{mu}m CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm{sup 2}; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption. (semiconductor integrated circuits)

  14. Evaluation of 320x240 pixel LEC GaAs Schottky barrier X-ray imaging arrays, hybridized to CMOS readout circuit based on charge integration

    CERN Document Server

    Irsigler, R; Alverbro, J; Borglind, J; Froejdh, C; Helander, P; Manolopoulos, S; O'Shea, V; Smith, K

    1999-01-01

    320x240 pixels GaAs Schottky barrier detector arrays were fabricated, hybridized to silicon readout circuits, and subsequently evaluated. The detector chip was based on semi-insulating LEC GaAs material. The square shaped pixel detector elements were of the Schottky barrier type and had a pitch of 38 mu m. The GaAs wafers were thinned down prior to the fabrication of the ohmic back contact. After dicing, the chips were indium bump, flip-chip bonded to CMOS readout circuits based on charge integration, and finally evaluated. A bias voltage between 50 and 100 V was sufficient to operate the detector. Results on I-V characteristics, noise behaviour and response to X-ray radiation are presented. Images of various objects and slit patterns were acquired by using a standard dental imaging X-ray source. The work done was a part of the XIMAGE project financed by the European Community (Brite-Euram). (author)

  15. High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid;

    with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention...

  16. A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

    NARCIS (Netherlands)

    Bult, Klaas; Wallinga, Hans

    1979-01-01

    The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source v

  17. High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid

    with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention...

  18. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  19. Design and integration of a high accuracy multichannel analog CMOS peak detect and hold circuit for APD-based PET imaging.

    Science.gov (United States)

    Fang, Xiaochao; Brasse, David; Hu-Guo, Christine; Hu, Yann

    2012-04-01

    This paper presents the design of a high accuracy multichannel peak detect and hold (PDH) circuit. This PDH measures the energy of an event and is one part of a readout chain for avalanche photo diodes (APD)-based positron emission tomography (PET) imaging. The circuit is designed in a 0.35μm CMOS process. The proposed PDH is dedicated to ultra low amplitude, large amplitude range from several tens millivolts to 1.1 V, and fast peaking time (190 ns) semi-Gaussian pulses. The two-phase technique has been used to cancel the major error source of the classical CMOS PDH: offset. A two-gain OTA is applied to minimize the DC error. A peak error less 1% for a small input signal (amplitude is between 40 mV and 300 mV) and a peak error less than 0.2% for a large input signal (amplitude is between 300 mV and 1.1 V) have been obtained from test. The area of a PDH is equal to about 200 μm × 40 μm. In our PDH system, the drop rate is negligible.

  20. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  1. CMOS bulk-metal design handbook

    Science.gov (United States)

    Edge, T. M.

    1978-01-01

    User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

  2. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  3. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  4. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  5. Nanoelectronic circuit design and test

    Science.gov (United States)

    Simsir, Muzaffer Orkun

    Controlling power consumption in CMOS integrated circuits (ICs) during normal mode of operation is becoming one of the limiting factors to further scaling. In addition, it is a well known fact that during testing of a complex IC, power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to the fact that extreme temperature variations lead to changes in path delays. Therefore, even good chips can fail the test. For these reasons, thermal problems during test need to be identified to prevent the loss of yield in CMOS ICs. In this thesis, we propose a methodology for thermally characterizing circuits under test. Using this methodology, it is possible to simulate the thermal profiles of the chips during test and prevent possible yield loss because of thermal problems. In addition to the problems associated with power and temperature, a more important barrier is the scaling limitations of the CMOS technology. It has been predicted that in next decade, it will not be possible to scale it further. In the near future, rather than a transition to a completely new technology, extensions to CMOS seem to be more realistic. Double-gate CMOS technology is one of the most promising alternatives that offers a simple extension to CMOS. The transistors of this technology are formed by adding a second gate across the conventional CMOS transistor gate. Designing circuits using this technology has attracted a lot of attention. However, as circuit design methods mature, there is a need to identify how these circuits can be tested. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all defects in double-gate CMOS circuits. Therefore, fault models of this technology need to be defined to enable manufacturing-time testing. In this thesis, we

  6. 16nm planar process CMOS SRAM cell design: Analysis of Operating Voltage and Temperature Effect

    Directory of Open Access Journals (Sweden)

    Rohit Sharma

    2013-09-01

    Full Text Available Purpose: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies [1]. Low power static-random access memories (SRAM have become a critical component in modern VLSI systems. They occupy a large portion of area and accounts for a major component of power consumption in today’s VLSI circuits. In this paper we intend to analyse the performance of a traditional 6T SRAM cell of 16nm Complementary Metal Oxide Semiconductor (CMOS technology with change in Operating Voltage and Temperature. Aim: The aim of the paper is to study the effect of the SNM dependencies on the operating voltage and temperatureApproach: Conventional 6T SRAM are designed using predictive technology model developed by Arizona State University [2] of 16nm planar Low Power CMOS and variation of SNM with operating voltage and temperature are simulated and studied using hspice.Findings: Variations in the operating voltages and temperature strongly impact the stability of an SRAM cell at 16nm. Comparative study is done for predictive 16nm based conventional 6T SRAM cell by varying operating voltage and temperature. A methodology to select operating voltage is suggested which can be used in an early stage of a design cycle to optimise stability margins in nanometer regime

  7. SEMICONDUCTOR INTEGRATED CIRCUITS: A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Science.gov (United States)

    Leisheng, Gao; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

    2010-08-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 μm2. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

  8. 一种脉冲编码CMOS神经元电路的设计与实现%A Design of Pulse Coded CMOS Neuron Circuit

    Institute of Scientific and Technical Information of China (English)

    熊莹; 韩伟华; 张严波; 杨富华

    2011-01-01

    According to the electrochemical characteristics of biological neurons, this paper presents a new compact pulse coded CMOS neuron circuit based on I&F model to imitate a continuous pulse steam generated by neuron cell. We show that the model has been simplified greatly, it characterizes many aspects of real neurons. In the case that the fabrication parameters of transistors cannot be adjusted, the circuit construction and coupled weights can be controlled flexibly by the input signals, then the circuit realizes the pulse code modulation of the input signals. The results of HSPICE simulation show that this circuit can realize the weight identification of the binary square-wave input signal according to the frequency of output pulse stream. This new pulse coded CMOS neuron circuit would have great application prospects in the information transmission, the construction of image recognition neural network and signal modulation.%从生物神经元的电化学特性出发,基于积分发放(I&F)电路理论模型,提出了一种新型的结构紧凑的脉冲编码CMOS神经元电路,模仿神经元细胞体输出连续脉冲串.该模型的优点在于大大简化了模型结构,其运行结果很好地拟合了神经元的生理特性,且在工艺参数不可调节的情况下,可通过输入信号灵活控制电路结构,改变输入耦合权重,从而实现对输入信号的脉冲编码.HSPICE仿真结果表明,该电路可以通过输出脉冲串频率实现对多端输入的二进制方波信号的权重识别,在自适应耦合调整的信息传递,图像识别神经网络构建和信号调制方面具有很大的应用前景.

  9. The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.

    Science.gov (United States)

    Chen, Wei-Ming; Yang, Wen-Chia; Tsai, Tzung-Yun; Chiueh, Herming; Wu, Chung-Yu

    2011-01-01

    In this paper an 8-channel CMOS general-purpose analog front-end (AFE) circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFE consists of eight chopper stabilized pre-amplifiers, an 8-to-1 analog multiplexer, and a programmable gain amplifier. It can be used to sense and amplify different kinds of biopotential signals, such as electrocorticogram (ECoG), electrocardiogram (ECG) and electromyogram (EMG). The AFE chip is designed and fabricated in 0.18-μm CMOS technology. The measured maximum gain of AFE is 60.8 dB. The low cutoff frequency can achieve as low as 0.8 Hz and high cutoff frequency can be adjusted from 200 Hz to 10 kHz to suit for different kinds of biopotential signals. The measured input-referred noise is 0.9 μV(rms), with the power consumption of 18μW per channel at 1.8-V power supply. And the noise efficiency factor (NEF) is only 1.3 for pre-amplifier.

  10. SEMICONDUCTOR INTEGRATED CIRCUITS: Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

    Science.gov (United States)

    Keping, Wang; Zhigong, Wang; Xuemei, Lei

    2010-02-01

    A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S11 of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.

  11. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  12. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

    Science.gov (United States)

    Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

    2017-02-01

    In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

  13. SEMICONDUCTOR INTEGRATED CIRCUITS A 0.18 μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

    Science.gov (United States)

    Bing, Li; Yiqi, Zhuang; Zhenrong, Li; Gang, Jin

    2010-12-01

    This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

  14. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  15. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  16. SEMICONDUCTOR INTEGRATED CIRCUITS: A 6-9 GHz ultra-wideband CMOS PA for China's ultra-wideband standard

    Science.gov (United States)

    Zhendong, Gao; Zhiqiang, Li; Haiying, Zhang

    2010-09-01

    A 6-9 GHz ultra-wideband CMOS power amplifier (PA) for the high frequency band of China's UWB standard is proposed. Compared with the conventional band-pass filter wideband input matching methodology, the number of inductors is saved by the resistive feedback complementary amplifying topology presented. The output impendence matching network utilized is very simple but efficient at the cost of only one inductor. The measured S22 far exceeds that of similar work. The PA is designed and fabricated with TSMC 0.18 μm 1P6M RF CMOS technology. The implemented PA achieves a power gain of 10 dB with a ripple of 0.6 dB, and S11 < -10 dB over 6-9 GHz, S22 < -35 dB over 4-10 GHz. The measured output power at the 1 dB compression point is over 3.5 dBm from 6 to 9 GHz. The PA dissipates a total power of 21 mW from a 1.8 V power supply. The chip size is 1.1 × 0.8 mm2.

  17. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  18. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  19. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 2: Hardware design verification

    Science.gov (United States)

    Carlan, A. J.; Breuer, M. A.

    1982-10-01

    The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

  20. A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2010-03-15

    Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

  1. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  2. A compact 3D VLSI classifier using bagging threshold network ensembles.

    Science.gov (United States)

    Bermak, A; Martinez, D

    2003-01-01

    A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

  3. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  4. SEMICONDUCTOR INTEGRATED CIRCUITS A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    Science.gov (United States)

    Kefeng, Han; Shengguo, Cao; Xi, Tan; Na, Yan; Junyu, Wang; Zhangwen, Tang; Hao, Min

    2010-12-01

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.

  5. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  6. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  7. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  8. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  9. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  10. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  11. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  12. A New Opamp-less CMOS Bandgap Voltage Reference Circuit%一种新型无运放CMOS带隙基准电路

    Institute of Scientific and Technical Information of China (English)

    冯树; 王永禄; 张跃龙

    2012-01-01

    Theory of bandgap reference voltage and conventional bandgap reference circuits were presented, and a novel bandgap reference circuit without op-amp was designed. In the circuit, MOS current mirrors and negative feedback clamping technique were used to avoid the use of operational amplifier, thus eliminating effects of offset and power supply rejection ratio (PSRR) of the operational amplifier on accuracy of bandgap voltage reference. Based on 0. 18 μm standard CMOS process, the circuit was simulated using Spectre of Cadence. Simulation results showed that the bandgap voltage reference circuit had a temperature coefficient of 6. 73 ×10-6/℃ in the temperature range from -40 °C to 125 ℃, and a PSRR of 54. 8 dB, and it consumed 0. 25 mW of power from 2. 5 V supply.%介绍了带隙基准原理和常规的带隙基准电路,设计了一种新型无运放带隙基准电路.该电路利用MOS电流镜和负反馈箝位技术,避免了运放的使用,从而消除了运放带隙基准电路中运放的失调电压和电源抑制比等对基准源精度的影响.该新型电路比传统无运放带隙基准电路具有更高的精度和电源抑制比.基于0.18μm标准CMOS工艺,在Cadence Spectre环境下仿真.采用2.5V电源电压,在-40℃~125℃温度范围的温度系数为6.73×10-6/℃,电源抑制比为54.8dB,功耗仅有0.25 mW.

  13. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  14. Design of high-linear CMOS circuit using a constant transconductance method for gamma-ray spectroscopy system

    Energy Technology Data Exchange (ETDEWEB)

    Jung, I.I. [School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 156-756 (Korea, Republic of); Lee, J.H. [Institute of Innovative Functional Imaging, Chung-Ang University, Seoul 156-756 (Korea, Republic of); Lee, C.S. [Department of Physics, Chung-Ang University, Seoul 156-756 (Korea, Republic of); Choi, Y.-W., E-mail: ychoi@cau.ac.k [School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 156-756 (Korea, Republic of)

    2011-02-11

    We propose a novel circuit to be applied to the front-end integrated circuits of gamma-ray spectroscopy systems. Our circuit is designed as a type of current conveyor (ICON) employing a constant-g{sub m} (transconductance) method which can significantly improve the linearity in the amplified signals by using a large time constant and the time-invariant characteristics of an amplifier. The constant-g{sub m} method is obtained by a feedback control which keeps the transconductance of the input transistor constant. To verify the performance of the propose circuit, the time constant variations for the channel resistances are simulated with the TSMC 0.18{mu}m transistor parameters using HSPICE, and then compared with those of a conventional ICON. As a result, the proposed ICON shows only 0.02% output linearity variation and 0.19% time constant variation for the input amplitude up to 100 mV. These are significantly small values compared to a conventional ICON's 1.39% and 19.43%, respectively, for the same conditions.

  15. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  16. Integrated circuits in digital electronics (2nd revised and enlarged edition)

    Science.gov (United States)

    Barna, Arpad; Porat, Dan I.

    This book provides a link between elementary logic design theory and its practical applications. New information on Schottky TTL, ECL, and CMOS is given, along with a study of number systems and a detailed description of the design of sequential logic with emphasis on counters and shift registers and a discussion of arithmetic circuits. A chapter on latches and flip-flops emphasizes the differences between these two storage elements. A summary of coding, code conversion, and error detection and correction is given along with descriptions of digital-to-analog and analog-to-digital converters. Up-to-date treatment of LSI and VLSI circuits is given, including static and dynamic circuits, RASMs, ROMs, PLSAs, associative memories, and gate arrays. There is also a unified presentation of practical considerations in digital equipment design.

  17. Current induced annealing and electrical characterization of single layer graphene grown by chemical vapor deposition for future interconnects in VLSI circuits

    Science.gov (United States)

    Prasad, Neetu; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C.; Bhatia, C. S.

    2014-09-01

    Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ˜1.2 × 107 A/cm2 has been obtained for SLG (1 × 2.5 μm2) on SiO2/Si substrate, which is about an order higher than that of conventionally used copper interconnects.

  18. Design of a novel current-controlled CMOS oscillator circuit%一种新型电流控制CMOS振荡器电路设计

    Institute of Scientific and Technical Information of China (English)

    徐慧敏; 戴庆元; 罗超

    2012-01-01

    设计了一种基于华虹0.35μm BCD工艺的新型电流控制CMOS振荡器电路,中心频率为1 MHz,宽温度范围内具有占空比高稳定性.不同于传统电流控制CMOS振荡器拓扑,结构简单,通过反相器阈值电压控制电流对电容的充放电状态切换,消除了延迟时间引起的上冲、下冲问题,具有良好的可移植性.Cadence Spectre仿真结果表明:-45~125℃范围内,振荡频率和占空比相对中心值的上下偏差分别为5.01%(-)到3.31%(+)、1 95%(-)到1.84%(+);方差分别为0.000 9、0.000 1.%A novel current-controlled CMOS oscillator circuit with 1 MHz frequency was designed based on 0.35 μm BCD process which realized high stability of frequency and duty cycle. The key aspect of the circuit with a simple structure and good portability, was the different topology with conventional CMOS oscillator, in which the capacitor charge state switching was controlled by the inverter threshold voltage, eliminating the overshoot and undershoot caused by delay. The results from the Cadence spectra simulation show that, with temperature range from —45 ℃ to 125 ℃, the proposed oscillator has a frequency deviation of 5.01%(—) to 3.31%(+) and a duty cycle variation of 1.95%(-) to 1.84%(+), while variance are 0.0009 and 0.0001, respectively.

  19. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  20. BiCMOS operational amplifier with precise and stable dc gain for high-frequency switched capacitor circuits

    Science.gov (United States)

    Baschirotto, A.; Alini, R.; Castello, R.

    1991-07-01

    A novel approach in the design of high-frequency switched capacitor (SC) circuits is presented. It is based on the use of simple and fast amplifiers with low but precisely controlled gain value. The effect of the precisely known and stable opamp gain is compensated for by changing the capacitor values during the synthesis of the SC cell. An example of an opamp with these features and the synthesis of a biquadratic filter based on this approach are given.

  1. Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film

    Science.gov (United States)

    Gao, Pingqi; Zhang, Qing

    2014-02-01

    Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm2 V-1 s-1, a subthreshold slope as low as 150 mV dec-1, operating gate voltages less than 2 V, on/off ratios larger than 104 and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

  2. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  3. Current induced annealing and electrical characterization of single layer graphene grown by chemical vapor deposition for future interconnects in VLSI circuits

    Energy Technology Data Exchange (ETDEWEB)

    Prasad, Neetu, E-mail: neetu.prasad@south.du.ac.in, E-mail: neetu23686@gmail.com; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C. [Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110021 (India); Bhatia, C. S. [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore)

    2014-09-15

    Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ∼1.2 × 10{sup 7 }A/cm{sup 2} has been obtained for SLG (1 × 2.5 μm{sup 2}) on SiO{sub 2}/Si substrate, which is about an order higher than that of conventionally used copper interconnects.

  4. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  5. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  6. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    Energy Technology Data Exchange (ETDEWEB)

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  7. Capacitor-voltage converter circuit based on CMOS%基于CMOS的电容-电压转换电路的设计

    Institute of Scientific and Technical Information of China (English)

    曹俊杰; 邱成军

    2013-01-01

    在MEMS传感器的电容检测电路中,经常要采用电容—电压转换电路.本研究将两相不交叠时钟模块应用到设计中,使得该电路用单个时钟就能进行有效控制,并能够满足MEMS电容检测系统的要求.采用0.25 μm工艺库对电路进行优化并给定了电路仿真的相应结论.仿真结果表明,其CMOS运放部分的增益为77.76 dB,单位增益带宽为5.60 MHz,相位裕量为65.87°,输出摆幅为-2.0~1.89 V,输入共模范围为-1.0 ~1.93V,正摆率为+9.92 V·μs-1,负摆率为5.03 V·μs-,功耗为1.03 mW.该电路适合于pF量级范围内的电容变化,该变化范围为35~1 200 pF,且输出线性度良好.%In the MEMS sensor capacitance detection of circuit,capacitive-voltage conversion circuit is often used.Two phase non-overlapping clock module has been applied to the design,so the circuit can be effectively controlled by a single clock and also be satisfied to the requirements of MEMS capacitive detection system.Using 0.25 μm technology library to optimize the circuit,the appropriate conclusions have been given out to the circuit simulation.The results show that part of its CMOS opamp is gain of 77.76 dB,the bandwidth of unity gain is 5.60 MHz,the phase margin is 65.87°,the output swing is-2.0 ~ 1.89 V,the input common mode range is-1.0 ~ 1.93 V,the positive slew rate is 9.92 V · μ S-1,the negative slew rate is 5.03 V · μ s-1,the power consumption is 1.03 mW.The circuit is suitable for capacitance change in the order of pF within the range of 35 ~ 1 200 pF,and the output is in good linearity.

  8. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  9. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  10. CMOS Law-jitter Clock Driver Design

    OpenAIRE

    2012-01-01

    [ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. [CASTELLÀ] Diseño de un circuito integrado "clock driver" de bajo jitter y bajo ruido de fase en tecnología CMOS 40 nm. El trabajo se contextualiza en el campo del diseño de circuitos integrados analógicos en tecnologías CMOS nanométricas. [CATALÀ] Disseny d'un circuit "clock driver" de baix jitter i bai...

  11. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  12. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  13. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  14. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  15. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  16. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  17. VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

    Directory of Open Access Journals (Sweden)

    S. Karunakaran

    2012-01-01

    Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

  18. CMOS array design automation techniques

    Science.gov (United States)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  19. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  20. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  1. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  2. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  3. Research into Self-Timed VLSI Circuits.

    Science.gov (United States)

    1984-10-22

    without reorganization. and identical processors are spaced around the store. In the Gauss- Seidel method [8] the grid point Computer simulation of the...convergence rates intermediate between those of grid point values are used throughout each iteration. the Jacobi and Gauss- Seidel methods are obtained... Seidel method , number of processors) of 40-60% is achieved with as when it uses one processor per grid point, it reduces to many as N processors, where

  4. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  5. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  6. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  7. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  8. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  9. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  10. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  11. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  12. A time-domain CMOS oscillator-based thermostat with digital set-point programming.

    Science.gov (United States)

    Chen, Chun-Chi; Lin, Shih-Hao

    2013-01-29

    This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s.

  13. A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

    Directory of Open Access Journals (Sweden)

    Shih-Hao Lin

    2013-01-01

    Full Text Available This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s.

  14. Decimation of encoding errors in an optimum SNS 2 micron low-noise CMOS ADC

    Science.gov (United States)

    Schafer, Jeffrey L.

    1995-03-01

    Significant research in high performance analog-to-digital converters (ADC's) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can he used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and power consumption of the ADC. This thesis examines the issue of encoding errors that result when the separate channels m sub i are brought together to derive the input analog voltage. The Very Large Scale Integrated (VLSI) design for the comparators, error checking circuits and Programmable Logic Arrays (PLA's) use the Orbit 2 Micron CMOS N-well double-metal, double-poly fabrication process. Steady state transfer functions are shown which detail encoding errors that occur when the folded input samples lie at one of the code transition points. To discard the encoding errors that occur, a decimation band is constructed at each transition Point The effectiveness of the decimation band in eliminating the encoding errors and the linearity error is quantified. An Application Specific Integrated Circuit (ASIC) is designed.

  15. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  16. Nano CMOS

    OpenAIRE

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  17. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Science.gov (United States)

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  18. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  19. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  20. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  1. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  2. Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits

    Directory of Open Access Journals (Sweden)

    Rajani H.P

    2012-09-01

    Full Text Available Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The powerdissipation during inactive (standby mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipatinglower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.

  3. Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits

    Directory of Open Access Journals (Sweden)

    Rajani H.P

    2012-08-01

    Full Text Available Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.

  4. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  5. Identification of worst-case bias condition for total ionizing dose effect of CMOS circuits%CMOS电路总剂量效应最劣偏置甄别

    Institute of Scientific and Technical Information of China (English)

    丁李利; 郭红霞; 王忠明; 陈伟; 范如玉

    2012-01-01

    采用电路分析和解析建模方法研究了CMOS电路中甄别总剂量效应最劣辐照与测试偏置的问题.通过引入小规模模拟电路和数字电路的例子进行具体分析,获取了不同电路的最劣偏置情况.对于数字电路,引入了敏感因子的概念用于定量计算不同辐照与测试偏置组合下电路的总剂量效应敏感程度.利用实测数据或电路仿真结果对甄别结果进行了一一验证,得到相一致的结论,证明了该研究思路的正确性.%Using circuit analysis.and-theoretica) modeling, the problem of identifying worst-case irradiation and test bias for total ionizing dose (TID) .effect of CMOS circuits is studied. Small scale analog and digital circuits are introduced and analyzed, thus worst-case bias conditions are identified step by step. To digital circuits, the concept of the sensitive factor is introduced to calculate the sensitive level of circuits to TID effect under different combinations of bias during irradiation and during test. The results are validated and verified by experimental tests or circuit simulation, which proves the rationality of the identification method.

  6. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  7. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  8. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  9. MOS器件直接隧穿栅电流及其对CMOS逻辑电路的影响%Direct tunneling gate current of MOSFET and its impact on CMOS logic circuit

    Institute of Scientific and Technical Information of China (English)

    唐东峰; 张平; 龙志林; 胡仕刚; 吴笑峰

    2013-01-01

    With the scaling of MOS (metal-oxide-semiconductor) devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents, considering that, the direct tunneling current (DT) in MOSFET (metal-oxide-semiconductor field effect transistor) was studied based on reliability theory and simulation. Simultaneously, the static gate leakage current of two-input nor gate was studied and the impact of direct tunneling gate leakage current on CMOS (complementary metal oxide semiconductor) logic circuits was revealed. HSP1CE software was used as the simulation tool. MOS model parameter is BSIM4 and LEVEL 54. The thickness of the gate oxide is 1.4 nm. The results show that the edge direct tunneling is an important component of gate tunneling in a scaled MOS device. Drain bias and substrate bias can affect the gate current density by changing the surface potential. There are four common working states of MOS device in CMOS logic circuit, i.e. the linear region, saturation region, sub-threshold region and cut-off region. The gate leakage current of MOSFET in CMOS logic circuit is related to its working status. The simulation results agree well with theoretical analysis results, and the theory and simulation will contribute to integrated circuit design.%随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET (metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响.仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm.研究结果表明:边缘直接隧穿电流是

  10. Design of multi-functional digital chip's out buffer circuit in CMOS process%CMOS工艺多功能数字芯片的输出缓冲电路设计

    Institute of Scientific and Technical Information of China (English)

    周子昂; 姚遥; 徐坤; 张利红

    2012-01-01

    为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试.提出了一种基于CSMC2P2M0.6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0.6μmCMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC2P2M0.6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW(多项目晶圆)计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。%In order to improve the driving ability of the digital integrated circuit chip ,by optimizing the scale factor ratio buffer chain method,the design of output buffer circuit based on CSMC 2P2M 0.6 μm CMOS process is designed in this paper by simulation of Hspice Software and layout design testing, The paper complete system of electrical schematic design and layout design.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6μm CMOS (06 mixddct02v24), the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip, The chip area is 1 mmxl mm. The design has been successfully implemented by participating in the plan of the Multi Project Wafer. Measurements indicate that t the design can provide sufficient drive current, and short delay time, and small layout when the output load is very large.

  11. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  12. SEMICONDUCTOR INTEGRATED CIRCUITS: An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

    Science.gov (United States)

    Peijun, Gao; J, Oh N.; Hao, Min

    2009-08-01

    A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

  13. Large-scale circuit simulation

    Science.gov (United States)

    Wei, Y. P.

    1982-12-01

    The simulation of VLSI (Very Large Scale Integration) circuits falls beyond the capabilities of conventional circuit simulators like SPICE. On the other hand, conventional logic simulators can only give the results of logic levels 1 and 0 with the attendent loss of detail in the waveforms. The aim of developing large-scale circuit simulation is to bridge the gap between conventional circuit simulation and logic simulation. This research is to investigate new approaches for fast and relatively accurate time-domain simulation of MOS (Metal Oxide Semiconductors), LSI (Large Scale Integration) and VLSI circuits. New techniques and new algorithms are studied in the following areas: (1) analysis sequencing (2) nonlinear iteration (3) modified Gauss-Seidel method (4) latency criteria and timestep control scheme. The developed methods have been implemented into a simulation program PREMOS which could be used as a design verification tool for MOS circuits.

  14. A design method in CMOS analog circuit optimization based on an adaptive genetic algorithm%基于自适应遗传算法的模拟电路的优化设计方法

    Institute of Scientific and Technical Information of China (English)

    于健海; 毛志刚; 陈伟平

    2011-01-01

    针对在模拟电路设计中参数调整复杂性带来的困难,提出了一种新的针对CMOS模拟运算放大器参数优化方法.其特点是把模拟电路设计知识与遗传算法相结合,通过对遗传算法的自适应改进帮助其解决多目标优化和收敛的问题,并根据不同的性能指标要求,在相同结构下优化出不同用途的运算放大器.实验结果证明,该方法在相同结构下与其他优化方法相比较可以精确而有效地优化出高增益、高带宽、低噪声的运算放大器.该方法适用于模拟电路优化设计:由于其基于Hspice仿真结果,更贴近于实际电路设计,具有实用价值.%A new method for optimizing the parameters of a CMOS operational amplifier based on an adaptive GA ( genetic algorithm) was presented in order to solve the difficulty caused by parameter optimization in analog circuit design. The main advantage of the method is that the problems of convergence and multiple objective optimization tasks can be solved through combining the useful features of manual analog circuit design, and adjusting the GA with the evolution process. Operational amplifiers for different uses can also be developed depending on various performance specifications. The simulation results show that this method can accurately achieve high DC-gain, high bandwidth, low noise, and low power operational amplification, and it efficiently compares with other optimizing methods having the same circuit structure. The method is suitable for CMOS analog circuit optimization. Because it is based on the simulation results of Hspice, it is much more similar to actual circuit design and therefore more useful.

  15. 基于0.18μm CMOS工艺的电流型模拟运算电路%Current mode analog operational circuit based on 0.18 μm CMOS process

    Institute of Scientific and Technical Information of China (English)

    卢锦川; 詹小英

    2016-01-01

    A new CMOS current mode multifunction analog operational circuit with low voltage and low power consumption is proposed,which can run multiplier,squarer,divider and different types of controllable gain amplifiers. The design is based on translinear principle,in which MOSFET is adopted and runs in the subthreshold region. The proposed circuit is composed of six inter⁃matching transistors to form two overlapping tranlinear loops. The circuit is based on 0.18 μm CMOS process,and sup⁃plied with ± 0.6 V low voltage DC source. The circuit was verified by simulation of Tanner TSpice software. The simulation re⁃sults show that when the circuit is configured as an amplifier,its frequency is about 1.5 MHz at -3 dB,linear error is 0.63%, total harmonic distortion is 0.08%,and maximum power consumption is 1.16 μW.%提出了一种新的低电压低功耗CMOS电流型模拟多功能运算电路,该电路能够运行乘法器、求平方器、除法器以及不同类型的可控增益放大器。该设计基于跨导线性原则,使用场效晶体管(MOSFET)且运行在亚阈值区,其由6个相匹配的晶体管组成,并形成两个重叠的跨导线性回路,电路设计采用0.18μm CMOS技术,使用±0.6 V低压直流电源供电。通过Tanner TSpice软件进行了仿真验证,仿真结果表明,当将其配置为一个放大器时,-3 dB频率约为1.5 MHz,线性误差为0.63%,总谐波失真为0.08%,最大功耗为1.16μW。

  16. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  17. Statistics on VLSI Designs.

    Science.gov (United States)

    1980-04-17

    been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE

  18. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  19. 基于65nm CMOS工艺的高速串并转换电路设计%A Parallel-to-serial Conversion Circuit In 65nm CMOS Process

    Institute of Scientific and Technical Information of China (English)

    付秀兰; 孙立宏

    2012-01-01

    本文介绍了一种适用于高速差分数据接收的CMOS串并转换电路,该电路主要由时钟电路、1:2数据分割电路和1:5分接器组成。采用65nm工艺,仿真结果表明,在数据传输速度为5Gb/s时功耗为12mW。%In this paper,the implementation of a parallel-to-serial conversion circuit is presented.The circuits is composed of three main blocks,clock distribution network,two high speed 1:2 slicer and two 1:5 DEMUX.The proposed circuit is realized in a standard 65nm CMOS process.The simulation results show that total power consumption of 12 mW in 5Gb/s data rates under normal temperature.

  20. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  1. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  2. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  3. High Performance Linear 288×4 CMOS Readout Integrated Circuit with Time-Delay-Integration%具备时间延迟积分的高性能线阵288×4 CMOS读出电路

    Institute of Scientific and Technical Information of China (English)

    高峻; 鲁文高; 刘菁; 唐矩; 崔文涛; 赵宝瑛; 陈中建; 吉利久

    2004-01-01

    描述了一种高性能CMOS线阵288×4读出电路的设计.该读出电路是一个大规模混合信号电路,集成了时间延迟积分以提高信噪比,实现了缺陷像素剔除以提高阵列的可靠性.其他特征包括积分时间可调,多级增益,双向扫描,超采样,以及内建电测试.该芯片采用1.2μm双层多晶硅双层金属CMOS工艺.测量得到的总功耗约为24mW,工作电压5V.%A high performance CMOS linear 288×4 readout integrated circuit(ROIC)is detailed in this paper.It is a large-scale mixed-signal circuit with time-delay integration(TDI)function to enhance the signal to noise ratio(S/N),and defective element deselection(DED)function to decrease the probability of bad columns.The other features include adjustable integration time,multi gain,bi-direction of TDI scan,super-sample,and electrical test.Digital I/O ports are designed to control its work mode.It is fabricated using 1.2μm double poly double metal(DPDM)CMOS technology.The measured power consume is about 24mW at 5 V supply.

  4. A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

    Science.gov (United States)

    Nasir, Z.; Ruslan, S. H.

    2017-08-01

    A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

  5. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  6. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  7. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  8. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  9. High swing CMOS realization for third generation current conveyor (CCIII)

    OpenAIRE

    Minaei, Shahram; Yıldız, Merih; Türköz, Sait; Kuntman, Hakan

    2003-01-01

    In this paper a new CMOS realization for third generation current conveyor (CCIII) is proposed. The proposed circuit provides high swing range at terminals X and Y. The circuit has low input impedances at terminals X and Y and high output impedance at terminals Z+ and Z-. The circuit has 180MHz -3dB cutoff frequency in voltage follower mode. SPICE simulation results using MIETEC 1.2 CMOS process model are given.

  10. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  11. Caracterització elèctrica de circuits CMOS digitals amb defectes tipus pont: implicacions al test per corrent quiescent

    OpenAIRE

    Rodríguez Montañés, Rosa

    1992-01-01

    La tesis contribuye a los esfuerzos dirigidos a la consecución de modelaciones precisas de los fallos de tipo puente. La tecnología de los circuitos digitales considerados es la CMOS estática. En la tesis se utiliza un modelo eléctrico realista para los puentes consistentes en una conexión resistiva entre los nodos cortocircuitados. La elección del modelo se basa en un conjunto de medidas experimentales realizadas sobre circuitos monitores de defectos fabricados en un proceso industrial europ...

  12. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  13. Design of a High Precision Over-Temperature Protection Circuit Based on 0.13 μm CMOS Process%0.13μm CMOS高精度过温保护电路的设计

    Institute of Scientific and Technical Information of China (English)

    刘磊; 罗萍; 李航标

    2013-01-01

    An over-temperature protection (OTP) circuit was proposed based on 0.13 μm CMOS process.The circuit generated an OTP signal when temperature inside the chip exceeded 109 ℃ to stop the module from working.In order to prevent thermal oscillation,the OTP circuit was designed to turn off at 109 ℃ and turn on again at 78 ℃,resulting in a 31 ℃ hysteresis.Simulation results showed that the proposed OTP circuit bad a maximum drift error of only 2 ℃ at thermal shutdown and hysteresis threshold point when supply voltage fluctuated or process parameters shifted.%采用0.13 μm CMOS工艺,设计了一款过温保护电路.芯片内部温度超过109℃时,产生过温保护信号,电路停止工作,从而起到保护作用.为了防止产生热振荡,采用滞回方式.设计实现了在109℃时关断,78℃时再次开启,有31℃滞迟.仿真结果显示,在电源电压波动或工艺参数变化时,过温保护电路的热关断及迟滞阈值点漂移最大误差仅为2℃,稳定性好.

  14. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  15. CMOS current amplifiers : speed versus nonlinearity

    OpenAIRE

    2000-01-01

    This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived tha...

  16. Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

    Directory of Open Access Journals (Sweden)

    Edwin Becerra‐Álvarez

    2009-04-01

    Full Text Available This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA for the next generation of wireless hand‐held devicesby using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing thefulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such thatthe mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit underanalysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topologyincluding inductive‐source degeneration, MOS‐varactor based tuning networks, and programmable bias currents. This proposal,with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications;the LNA is designed to cope with the requirements of GSM (PCS1900, WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g. In orderto evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA featuresNF16dB, S11‐3.3 dBm over the 1.85‐2.48 GHz band. For all the standards understudy the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of thereconfigurable LNA occupies an area of 1.8mm2.

  17. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  18. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  19. Performance Enhancement of Multi-Output Carry Look-Ahead Cmos Csa

    Directory of Open Access Journals (Sweden)

    K. Ram Babu,

    2014-06-01

    Full Text Available Carry Select Adder (CSA is solitary of the best ever adders worn in numerous data-processing processors to complete speedy arithmetic functions. From the construction of the CSA, it is lucid that there is scope for sinking the vicinity and clout burning up in the CSA. This adder is based on both a static and compact multi-output carry look-ahead (CSA circuitof highly area-efficient CMOS carry-select adder (CSA with a regular and iterative-shared transistor structure very suitable for implementation in VLSI and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area. This paper uses a easy and proficient gate-level amendment to drastically diminish the vicinity and power of the CSA. Based on this modification different square-root CSA (SQRT CSA constructions have been developed and compared with the customary square-root architecture. The projected intend has reduced vicinity and power as compared with the regular Square Root CSA with only a slight increase in the delay. In this paper, conventional CSA is compared with Modified Carry select adder (MCSA, Regular Square Root CSLA (SQRT CSA, Modified SQRT CSA and Proposed SQRT CSA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSA.

  20. Bulk CMOS VLSI Technology Studies. Part 4. Design of a CMOS Microsequencer.

    Science.gov (United States)

    2014-09-26

    Refer to FIG.C.a which makes it clear that a pup transistor is possible with the n-type body as its base, while an npn transistor is possible with an n... Transistor VTP Threshold Voltage of a PNOS transistor VTN Threshold Voltage of an NIOS transistor VIL Width/Length Ratio of an K0S Transistor Y...and Logic Unit B Branch Field bit BC Byte Count EN Bets of an N-Channel transistor BP Beta of a P-Channel Transistor BR Beta ratio of an NOS inverter C

  1. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  2. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    Directory of Open Access Journals (Sweden)

    Chun-Chi Chen

    2016-01-01

    Full Text Available This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs. Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI system.

  3. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  4. SEMICONDUCTOR INTEGRATED CIRCUITS A 0.18 μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

    Science.gov (United States)

    Haiquan, Yuan; Fujiang, Lin; Zhongqian, Fu; Lu, Huang

    2010-12-01

    This paper presents an inductorless complementary-noise-canceling LNA (CNCLNA) for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best P1dB is -7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 × 0.2 mm2.

  5. SEMICONDUCTOR INTEGRATED CIRCUITS: A 3-5 GHz BPSK transmitter for IR-UWB in 0.18 μm CMOS

    Science.gov (United States)

    Delong, Fu; Lu, Huang; Li, Cai; Fujiang, Lin

    2010-09-01

    This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 μm CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 × 1.4 mm2.

  6. SEMICONDUCTOR INTEGRATED CIRCUITS: A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    Science.gov (United States)

    Jingchao, Wang; Chun, Zhang; Zhihua, Wang

    2010-08-01

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU—in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 × 3.8 mm2 including pads.

  7. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  8. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

    2016-01-01

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

  9. Failures Of CMOS Devices At Low Radiation-Dose Rates

    Science.gov (United States)

    Goben, Charles A.; Price, William E.

    1990-01-01

    Method for obtaining approximate failure-versus-dose-rate curves derived from experiments on failures of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated circuits irradiated by Co60 and Cs137 radioactive sources.

  10. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  11. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  12. Full differential CMOS interface circuit for closed-loop capacitive micro-accelerometers%闭环电容式微加速度计全差分CMOS接口电路

    Institute of Scientific and Technical Information of China (English)

    刘晓为; 尹亮; 李海涛; 周治平

    2011-01-01

    提出了一种用于电容式微加速度计的低噪声、高线性度全差分接口电路.基于开关电容检测技术,该电路采用一种新的双路反馈结构来提高系统线性度,并采用2 μm n阱CMOS工艺完成芯片设计.仿真结果证明,电路中采用的双路反馈和全差分检测结构使系统的线性度达到0.01%.加入经过优化设计的比例-微分-积分控制器后,有效减小了系统稳态误差,系统响应速度提高了31%,系统线性度提高了66.7%.在±5 V工作电压下,选取64 kHz作为电路采样频率时,其电路等效输入噪声为8 μg·Hz-(1)/(2),系统灵敏度为1.22 V/g,线性度为0.03%,测量范围为±2 g.测试结果显示,提出的电路达到高精度微加速度计系统设计要求,可以应用到地震监测、石油勘探等领域中.%A CMOS full differential interface circuit with low noise and high linearity was presented for closed-loop capacitive micro-accelerometers. Based on switched-capacitor detection, the circuit was designed to improve its linearity by a 0.5 μm n-well CMOS process technology. The simulation result shows that the proposed two-path feedback structure provides a good system linearity of 0.01%. The optimized designed PID controller was added into the system, which decreases the stabilization error effectively, increases the system responding speed by 31%, and the linearity by 66.7%. With a ±5 V supply and a sampling frequency of 64 kHz, the circuit can offer the equivalent input noise in 8μg ·Hz-(1/2), system sensitivity in 1.22 V/g, system linearity in 0.03%, and the work range in ±2 g·These results prove that this circuit is suitable for applications of high performance micro-accelerome-ters to seism detection, oil exploration,etc..

  13. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  14. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...... poor performance compared to the bipolar designs, but CMOS has a potential for CFB op-amp design if more ingenious circuit configurations are applied...

  15. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  16. Air-stable conversion of separated carbon nanotube thin-film transistors from p-type to n-type using atomic layer deposition of high-κ oxide and its application in CMOS logic circuits.

    Science.gov (United States)

    Zhang, Jialu; Wang, Chuan; Fu, Yue; Che, Yuchi; Zhou, Chongwu

    2011-04-26

    Due to extraordinary electrical properties, preseparated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable n-type nanotube TFTs with industry-compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the as-made p-type TFTs using preseparated semiconducting nanotubes into air-stable n-type transistors by adding a high-κ oxide passivation layer using atomic layer deposition (ALD). The n-type devices exhibit symmetric electrical performance compared with the p-type devices in terms of on-current, on/off ratio, and device mobility. Various factors affecting the conversion process, including ALD temperature, metal contact material, and channel length, have also been systematically studied by a series of designed experiments. A complementary metal-oxide-semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior, and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.

  17. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  18. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  19. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  20. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.