Chen, Wai-Kai
2009-01-01
Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.
Implementing neural architectures using analog VLSI circuits
Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.
1989-05-01
Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.
Associative Pattern Recognition In Analog VLSI Circuits
Tawel, Raoul
1995-01-01
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Self arbitrated VLSI asynchronous sequential circuits
Whitaker, S.; Maki, G.
1990-01-01
A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.
Relaxation Based Electrical Simulation for VLSI Circuits
Directory of Open Access Journals (Sweden)
S. Rajkumar
2012-06-01
Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.
Analog VLSI neural network integrated circuits
Kub, F. J.; Moon, K. K.; Just, E. A.
1991-01-01
Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.
VLSI Circuits for High Speed Data Conversion
1994-05-16
Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp
VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network
Directory of Open Access Journals (Sweden)
Mohd Asyraf Mansor
2016-09-01
Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.
VLSI circuits for high speed data conversion
Wooley, Bruce A.
1994-05-01
The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.
Low-power VLSI circuits and systems
Pal, Ajit
2015-01-01
The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.
Artificial immune system algorithm in VLSI circuit configuration
Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd
2017-08-01
In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.
A radial basis function neurocomputer implemented with analog VLSI circuits
Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul
1992-01-01
An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.
Trace-based post-silicon validation for VLSI circuits
Liu, Xiao
2014-01-01
This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...
Efficient FM Algorithm for VLSI Circuit Partitioning
Directory of Open Access Journals (Sweden)
M.RAJESH
2013-04-01
Full Text Available In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if theinitial partitioning matrix is close to the final partitioning then the computation time (iteration required is small . Here we have proposed novel approach to arrive at initial partitioning by using spectralfactorization method the results was verified using several circuits.
Ground Bounce Noise Reduction in Vlsi Circuits
Directory of Open Access Journals (Sweden)
Vipin Kumar Sharma
2015-12-01
Full Text Available : Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.
Custom VLSI circuits for high energy physics
Energy Technology Data Exchange (ETDEWEB)
Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)
1998-06-01
This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.
Testing interconnected VLSI circuits in the Big Viterbi Decoder
Onyszchuk, I. M.
1991-01-01
The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.
CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation
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Hussein CHIBLE,
2013-10-01
Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented
VLSI circuits implementing computational models of neocortical circuits.
Wijekoon, Jayawan H B; Dudek, Piotr
2012-09-15
This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.
High performance genetic algorithm for VLSI circuit partitioning
Dinu, Simona
2016-12-01
Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.
A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level
Institute of Scientific and Technical Information of China (English)
胡谋
1992-01-01
A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.
Basu, D K
2014-01-01
Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...
POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS
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D. I. Cheremisinov
2013-01-01
Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.
Synthesis of on-chip control circuits for mVLSI biochips
DEFF Research Database (Denmark)
Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin
2017-01-01
them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....
VLSI circuits for bidirectional interface to peripheral and visceral nerves.
Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V
2015-08-01
This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.
Starting Circuit For Erasable Programmable Logic Device
Cole, Steven W.
1990-01-01
Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.
Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications
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P. Mohan Krishna
2014-04-01
Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.
Current-mode subthreshold MOS circuits for analog VLSI neural systems
Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.
1991-03-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Current-mode subthreshold MOS circuits for analog VLSI neural systems.
Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K
1991-01-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Chandrasetty, Vikram Arkalgud
2011-01-01
This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam
2011-12-01
Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.
Analog VLSI Circuits for Short-Term Dynamic Synapses
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Shih-Chii Liu
2003-06-01
Full Text Available Short-term dynamical synapses increase the computational power of neuronal networks. These synapses act as additional filters to the inputs of a neuron before the subsequent integration of these signals at its cell body. In this work, we describe a model of depressing and facilitating synapses derived from a hardware circuit implementation. This model is equivalent to theoretical models of short-term synaptic dynamics in network simulations. These circuits have been added to a network of leaky integrate-and-fire neurons. A cortical model of direction-selectivity that uses short-term dynamic synapses has been implemented with this network.
Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits.
1987-06-01
Voltage Dviders. .. .. .. .. .. .. .. .. .. 47 2.7TTwo Differently Raloednverters...................... 49 2.6 MOS Trasistor SybolWith Zxpict C.andC...Inverter Cell. Current doesn’t flow between nets. This has two intertwined benefits. First, net behavior is a wedge by which we can modularize a circuit’s...that that the current flow through the gate is eucessive. Ratio bugs can be modeiled because transistors are modelled s resistors whose resistance is
VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces
Wooley, Bruce A.
1991-04-01
The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.
A multi coding technique to reduce transition activity in VLSI circuits
Vithyalakshmi, N.; Rajaram, M.
2014-02-01
Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
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V.Sri Sai Harsha
2015-09-01
Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.
Deep sub-micron stud-via technology for superconductor VLSI circuits
Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.
2014-05-01
A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.
Ryckebusch, S; Wehr, M; Laurent, G
1994-12-01
Rhythmic motor patterns can be induced in leg motor neurons of isolated locust thoracic ganglia by bath application of pilocarpine. We observed that the relative phases of levators and depressors differed in the three thoracic ganglia. Assuming that the central pattern generating circuits underlying these three segmental rhythms are probably very similar, we developed a simple model circuit that can produce any one of the three activity patterns and characteristic phase relationships by modifying a single synaptic weight. We show results of a computer simulation of this circuit using the neuronal simulator NeuraLOG/Spike. We built and tested an analog VLSI circuit implementation of this model circuit that exhibits the same range of "behaviors" as the computer simulation. This multidisciplinary strategy will be useful to explore the dynamics of central pattern generating networks coupled to physical actuators, and ultimately should allow the design of biologically realistic walking robots.
Mixed-Signal VLSI Circuits for Particle Detector Instrumentation in High-Energy Physics Experiments
Loinaz, Marc Joseph
1995-11-01
This research is concerned with the circuit design challenges presented by the electronics requirements at future colliding beam facilitates for high-energy physics research. The particle detectors to be used in the next generation of experiments depend on the realization of sophisticated instrumentation electronics that will enable the identification and characterization of the fundamental constituents of matter. The work presented here focuses on the monolithic VLSI integration of multiple, mixed-signal, front-end electronics channels for detector-mounted instrumentation. The use of high levels of integration is driven by the need for compactness, low cost, high reliability, and low power dissipation in the implementation of the hundreds of thousands of sensory channels required for future experiments. The specific application considered in this work is the front -end electronics for straw tube drift chambers. In this context, the function of the front-end electronics is to measure the occurrence time of an input pulse in relation to a system clock. Each front-end channel includes analog circuits that provide amplification and signal conditioning for input pulses as small as 1mV, a timing discriminator, and a time interval digitizer to measure input pulse arrival times with respect to the system clock. Performance requirements for the channel include a timing error less than 0.75ns RMS, average power dissipation in the tens of milliwatts, and event rates in the 50-100MHz range. Circuits must be designed to allow the implementation of high-sensitivity analog and fast digital functions on the same chip. Unwanted coupling between digital and analog circuits must be minimized along with channel-to-channel crosstalk. A multi-channel circuit that measures the occurrence times of input pulses with peak values in the 1-10mV range relative to a 62.5-MHz clock has been monolithically integrated in a 1.2-μm CMOS technology. Each channel includes a wideband amplifier, a
Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo; Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
DEFF Research Database (Denmark)
Rasmussen, Ole Steen
This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....
VLSI Universal Noiseless Coder
Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi
1989-01-01
Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.
Directory of Open Access Journals (Sweden)
Sidorenko V. P.
2012-08-01
Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.
The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits
Energy Technology Data Exchange (ETDEWEB)
Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))
1993-08-01
An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.
A Design Methodology for Optoelectronic VLSI
2007-01-01
it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a
Typpö, Jukka
2003-01-01
This thesis studies the problems with maintaining the spectral purity of fully integrated VCO circuits for radio frequency synthesizers in single-chip system designs. LC tank circuit oscillator circuits are shown to convert amplitude variation in the tank circuit voltage into frequency modulation, if voltage dependent capacitances are present in the tank circuit. Since the parasitic capacitances of the gain transistors and the capacitance of the varactor device in a VCO circuit are voltage de...
Einspruch, Norman G
1986-01-01
VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special
Institute of Scientific and Technical Information of China (English)
骆祖莹; 闵应骅; 杨士元; 李晓维
2002-01-01
The authors theoretically describe the monotonic increasing relationship between averagepowers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, whichcan be fast computed, has been used as the evaluation criterion for the power of a practical circuit withdelay, which needs more computing time, in such fields as fast estimation for the average power and themaximum power, and fast optimization for the Iow test power. The authors propose a novel simulationapproach that uses delay-free power to compact a long input vector pair sequence into a short sequenceand then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. Incomparison with the traditional simulation approach that uses an un-compacted input sequence to simu-late the average (or maximum) power, experiment results demonstrate that in the field of fast estimationfor the average power, the present approach can be 6-10 times faster without significant loss in accuracy(less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach canbe 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast op-timization for the test power, the authors propose a novel delay-free power optimization approach for thetest power. Experiment results demonstrate that, in comparison with the approach of direct optimizationand the approach of Hamming distance optimization, this approach is of the highest optimization effi-ciency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% testpower).
Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits
Directory of Open Access Journals (Sweden)
Michael S. Hsiao
2002-01-01
Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.
Bahgat Shehata, A.; Stellari, F.
2015-01-01
Time-Resolved Emission (TRE) is a truly non-invasive technique based on the detection of intrinsic light emitted by integrated circuits that is used for the detection of timing related faults from the backside of flip-chip VLSI circuits. Single-photon detectors with extended sensitivity in the Near Infrared (NIR) are used to perform time-correlated single-photon counting measurements and retrieve the temporal distribution of the emitted photons, thus identifying gates switching events. The noise, efficiency and jitter performance of the detector are crucial to enable ultra-low voltage waveform sensitivity. For this reason, cryogenically cooled Superconducting Nanowire Single-Photon Detectors (SNSPDs) offer superior performance compared to state-of-the-art Single-Photon Avalanche Diodes (SPADs). In this paper we will discuss how detector front-end electronics parameters, such as bias current, RF attenuation and comparator threshold, can be tailored to optimize the measurement Signal-to-Noise Ratio (SNR), defined as the ratio between the switching emission peak amplitude and the standard deviation of the noise in the time interval in which there are no photons emitted from the circuit. For example, reducing the attenuation and the threshold of the comparator used to detect switching events may lead to an improvement of the jitter, due to the better discrimination of the detector firing, but also a higher sensitivity to external electric noise disturbances. Similarly, by increasing the bias current, both the detection efficiency and the jitter improve, but the noise increases as well. For these reasons an optimization of the SNR is necessary. For this work, TRE waveforms were acquired from a 32 nm Silicon On Insulator (SOI) chip operating down to 0.4 V using different generations of SNSPD systems.
Energy Technology Data Exchange (ETDEWEB)
Zhang, B
1999-07-01
This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)
Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits
Balwinder Singh; Sukhleen Bindra Narang; Arun Khosla
2011-01-01
Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequenceshave more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flopsresults more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on te...
Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V
2016-01-01
A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.
GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
Institute of Scientific and Technical Information of China (English)
Lu Junming; Lin Zhenghui
2002-01-01
In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.
A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications
Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I
1999-01-01
An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.
Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits
Singh, Balwnder; Khosla, Arun; 10.5121/ijaia.2011.2302
2011-01-01
Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.
A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
Directory of Open Access Journals (Sweden)
Trong-Tu Bui
2013-01-01
Full Text Available We present a compact and low-power rank-order searching (ROS circuit that can be used for building associative memories and rank-order filters (ROFs by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.
Nanotube substituted source/drain regions for carbon nanotube transistors for VLSI circuits.
Dutta, Shibesh; Shankar, Balakrishnan
2011-12-01
Aggressive scaling of silicon technology over the years has pushed CMOS devices to their fundamental limits. Pioneering works on carbon nanotube during the last decade possessing exceptional electrical properties have provided an intriguing solution for high performance integrated circuits. So far, at best, carbon nanotubes have been considered only for the channel, with metal electrodes being used for source/drain. Here, alternative schemes of 'All-Nanotube' transistor are presented where even the transistor components are derived from carbon nanotubes which hold the promise for smaller, faster, denser and more power efficient electronics.
Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits
1992-08-14
more than cuit shown in Fig.5 taken from 17]. It has been shown one stuck-open trasistor in a path. Tberefore, the to- that no two partern test seqence...in Fig. 6 that inplc- trasistors . so additicinputb is required. As samed in the previous section. a non-cdeword (00 or 11) at ments t fuction F- (A.BXB...s-on faults. Tbhs has been achieved by adding just a few trasistors without af fectng the1 ,speed of the circwut. The problem of circuit delays andat
GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
Institute of Scientific and Technical Information of China (English)
LuJunming; LinZhenghui
2002-01-01
In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.
Einspruch, Norman G; Gildenblat, Gennady Sh
1987-01-01
VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec
Analysis of Leakages and Leakage Reduction Methods in UDSM CMOS VLSI Circuits.
Directory of Open Access Journals (Sweden)
Sagar Ekade
2014-04-01
Full Text Available This is the era of portable devices which need to be powered by battery. Due to scarcity of space and leakages in chips, battery life is a serious concern. As technology advances, scaling of transistor feature size and supply voltage has improved the performance, increased the transistor density and reduced the power required by the chip. The maximum power consumed by the chip is the function of its technology along with its implementation. As technology is scaling down and CMOS circuits are supplied with lower supply voltages, the static power i.e. standby leakage current becomes very crucial. In Ultra Deep-submicron regime scaling has reduced the threshold voltage and that has led to increase in leakage current in sub-threshold region and hence rise in static power dissipation. This paper presents a critical analysis of leakages and leakage reduction techniques.
Synaptic dynamics in analog VLSI.
Bartolozzi, Chiara; Indiveri, Giacomo
2007-10-01
Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.
VLSI Architectures for Computing DFT's
Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.
1986-01-01
Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.
Novel start-up circuit with enhanced power-up characteristic for bandgap references
DEFF Research Database (Denmark)
Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre
This paper presents a new start-up circuit for low-power bandgap reference (BGR) voltage generators. The BGR is designed for providing a stable 0.3 V power supply for application in low power wireless sensor nodes. The BGR has an enhanced power-up characteristic and demonstrates a reduction...... of the total stand-by current. Simulated results confirm that the proposed start-up circuit does not affect the performance of the BGR even though the supply voltage (VDD) is higher and has more stable power-up characteristic than the conventional start-up circuits. The new start-up circuit is designed with 65...
Novel start-up circuit with enhanced power-up characteristic for bandgap references
DEFF Research Database (Denmark)
Tuan Vu, Cao; Wisland, Dag T.; Lande, Tor Sverre;
This paper presents a new start-up circuit for low-power bandgap reference (BGR) voltage generators. The BGR is designed for providing a stable 0.3 V power supply for application in low power wireless sensor nodes. The BGR has an enhanced power-up characteristic and demonstrates a reduction...... of the total stand-by current. Simulated results confirm that the proposed start-up circuit does not affect the performance of the BGR even though the supply voltage (VDD) is higher and has more stable power-up characteristic than the conventional start-up circuits. The new start-up circuit is designed with 65...
Jiang, P C; Chen, H
2006-01-01
VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.
A novel high voltage start up circuit for an integrated switched mode power supply
Energy Technology Data Exchange (ETDEWEB)
Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)
2010-09-15
A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)
Hao, Hu; Xingbi, Chen
2010-09-01
A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.
VLSI implementations for image communications
Pirsch, P
1993-01-01
The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits
Chen, Wai-Kai
2007-01-01
Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe
A fast novel soft-start circuit for peak current-mode DC—DC buck converters
Jie, Li; Miao, Yang; Weifeng, Sun; Xiaoxia, Lu; Shen, Xu; Shengli, Lu
2013-02-01
A fully integrated soft-start circuit for DC—DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections: an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC—DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 μm CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 μs start-up time. The inductor current and the output voltage increase smoothly over the whole load range.
A fast novel soft-start circuit for peak current-mode DC-DC buck converters
Institute of Scientific and Technical Information of China (English)
Li Jie; Yang Miao; Sun Weifeng; Lu Xiaoxia; Xu Shen; Lu Shengli
2013-01-01
A fully integrated soft-start circuit for DC-DC buck converters is presented.The proposed high speed soft-start circuit is made of two sections:an overshoot suppression circuit and an inrush current suppression circuit.The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor.A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current.The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 μm CMOS process.Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 μs start-up time.The inductor current and the output voltage increase smoothly over the whole load range.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris; Verbauwhede, Ingrid
2007-01-01
Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...
VLSI electronics microstructure science
1982-01-01
VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t
Trends and challenges in VLSI technology scaling towards 100 nm
Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram
Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm
Kemeny, Sabrina E.
1994-01-01
Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional
A novel dimmable LED driver with soft-start and UVLO circuits
Jinguang, Jiang; Gaojian, Tan; Zeyu, Zhang; Xifeng, Zhou
2015-02-01
A fully integrated LED driver based on a current mode PWM boost DC—DC converter with constant output current is proposed. In order to suppress the inrush of current and the overshoot voltage at the start up state, a soft-start circuit is adopted. Additionally, to adjust the LED brightness without color variation over the full dimming range and achieve high efficiency, a PWM dimming circuit is presented. Furthermore, to keep the loop stability of the LED driver, an internal slope compensation network is designed to avoid the sub-harmonic oscillation when the duty cycle exceeds 50%. Finally, a UVLO circuit is adopted to improve the reliability of the LED driver against the input voltage changing. The LED driver has been fabricated with a standard 0.5 μm CMOS process, and only occupies 1.21 × 0.76 mm2. Experimental results show that the brightness of the LED can be adjusted by an off-chip PWM signal with a wide adjusting range. The inductor current and output current increase smoothly over the whole load range. The chip is in the UVLO condition when the input voltage is below 2.18 V and has achieved about 137 μs typical start-up time.
VLSI electronics microstructure science
1981-01-01
VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi
Einspruch, Norman G
1989-01-01
VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The
Energy Technology Data Exchange (ETDEWEB)
Hojat, S.
1986-01-01
The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.
Hadjam, Fatima; Moraga, Claudio
2014-01-01
Quantum computers are considered as a future alternative to circumvent the heat dissipation problem of VLSI circuits. The synthesis of reversible circuits is a very promising area of study considering the expected further technological advances towards quantum computing. In this report, we propose a linear genetic programming system to design reversible circuits -RIMEP2-. The system has evolved reversible circuits starting from scratch without resorting to a pre-existing library. The results ...
Design and Verification of High-Speed VLSI Physical Design
Institute of Scientific and Technical Information of China (English)
Dian Zhou; Rui-Ming Li
2005-01-01
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Compact MOSFET models for VLSI design
Bhattacharyya, A B
2009-01-01
Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.
Generating Weighted Test Patterns for VLSI Chips
Siavoshi, Fardad
1990-01-01
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
VLSI Processor For Vector Quantization
Tawel, Raoul
1995-01-01
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
Technology computer aided design simulation for VLSI MOSFET
Sarkar, Chandan Kumar
2013-01-01
Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and
Einspruch, Norman G
1984-01-01
VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section
Verweij, Jan F.
1993-01-01
Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was
VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.
1983-10-01
34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being
Directory of Open Access Journals (Sweden)
Sudarshan Tiwari
2012-05-01
Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.
VLSI Microsystem for Rapid Bioinformatic Pattern Recognition
Fang, Wai-Chi; Lue, Jaw-Chyng
2009-01-01
A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
NASA Space Engineering Research Center for VLSI systems design
1991-01-01
This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.
Single Spin Logic Implementation of VLSI Adders
Shukla, Soumitra
2011-01-01
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.
VLSI 'smart' I/O module development
Kirk, Dan
The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.
Einspruch, Norman G
1987-01-01
VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.
A coherent VLSI design environment
Penfield, Paul, Jr.
1988-05-01
The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
刘彦佩
2001-01-01
This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.
Carlan, A. J.; Breuer, M. A.
1982-10-01
The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.
VLSI design for fault-dictionary based testability
Miller, Charles D.
The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.
Smith, Edwyn D.
1991-01-01
Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.
Handbook of VLSI chip design and expert systems
Schwarz, A F
1993-01-01
Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.
Hybrid VLSI/QCA Architecture for Computing FFTs
Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew
2003-01-01
A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.
Communication Protocols Augmentation in VLSI Design Applications
Directory of Open Access Journals (Sweden)
Kanhu Charan Padhy
2015-05-01
Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
Prasad, Neetu; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C.; Bhatia, C. S.
2014-09-01
Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ˜1.2 × 107 A/cm2 has been obtained for SLG (1 × 2.5 μm2) on SiO2/Si substrate, which is about an order higher than that of conventionally used copper interconnects.
Crystal growth and evaluation of silicon for VLSI and ULSI
Eranna, Golla
2014-01-01
PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri
Energy Technology Data Exchange (ETDEWEB)
Prasad, Neetu, E-mail: neetu.prasad@south.du.ac.in, E-mail: neetu23686@gmail.com; Kumari, Anita; Bhatnagar, P. K.; Mathur, P. C. [Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110021 (India); Bhatia, C. S. [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore)
2014-09-15
Single layer graphene (SLG) grown by chemical vapor deposition (CVD) has been investigated for its prospective application as horizontal interconnects in very large scale integrated circuits. However, the major bottleneck for its successful application is its degraded electronic transport properties due to the resist residual trapped in the grain boundaries and on the surface of the polycrystalline CVD graphene during multi-step lithographic processes, leading to increase in its sheet resistance up to 5 MΩ/sq. To overcome this problem, current induced annealing has been employed, which helps to bring down the sheet resistance to 10 kΩ/sq (of the order of its initial value). Moreover, the maximum current density of ∼1.2 × 10{sup 7 }A/cm{sup 2} has been obtained for SLG (1 × 2.5 μm{sup 2}) on SiO{sub 2}/Si substrate, which is about an order higher than that of conventionally used copper interconnects.
Very Large Scale Integration (VLSI).
Yeaman, Andrew R. J.
Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…
Design of RF energy harvesting platforms for power management unit with start-up circuits
Costanzo, Alessandra; Masotti, Diego
2013-12-01
In this contribution we discuss an unconventional rectifier design dedicated to RF energy harvesting from ultra-low sources, such as ambient RF sources which are typically of the order of few to few tens of μW. In such conditions unsuccessful results may occur if the rectenna is directly connected to its actual load since either the minimum power or the minimum activation voltage may not be simultaneously available. For this reason a double-branch rectifier topology is considered for the power management unit (PMU), instead of traditional single-branch one. The new PMU, interposed between the rectenna and application circuits, allows the system to operate with significantly lower input power with respect to the traditional solution, while preserving efficiency during steady-state power conversion.
Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.
Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David
2005-11-01
A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.
McKenzie, Neil
1989-12-01
We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.
VLSI Design of a Turbo Decoder
Fang, Wai-Chi
2007-01-01
A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris
2011-01-01
This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.
VLSI signal processing technology
Swartzlander, Earl
1994-01-01
This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in...
Advanced symbolic analysis for VLSI systems methods and applications
Shi, Guoyong; Tlelo Cuautle, Esteban
2014-01-01
This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...
A novel 3D algorithm for VLSI floorplanning
Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira
2013-01-01
3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.
Research into Self-Timed VLSI Circuits.
1984-10-22
without reorganization. and identical processors are spaced around the store. In the Gauss- Seidel method [8] the grid point Computer simulation of the...convergence rates intermediate between those of grid point values are used throughout each iteration. the Jacobi and Gauss- Seidel methods are obtained... Seidel method , number of processors) of 40-60% is achieved with as when it uses one processor per grid point, it reduces to many as N processors, where
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel
2015-01-01
This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
2011-01-01
Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...
Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems
2015-01-01
This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...
Analog VLSI implementation of resonate-and-fire neuron.
Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo
2006-12-01
We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.
A special purpose silicon compiler for designing supercomputing VLSI systems
Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.
1991-01-01
Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.
Multi-net optimization of VLSI interconnect
Moiseev, Konstantin; Wimer, Shmuel
2015-01-01
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...
Kirk, David Blair
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Directory of Open Access Journals (Sweden)
Chávez-Bracamontes Ramón
2015-07-01
Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding
VLSI mixed signal processing system
Alvarez, A.; Premkumar, A. B.
1993-01-01
An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.
Fundamentals of Microelectronics Processing (VLSI).
Takoudis, Christos G.
1987-01-01
Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)
A fast neural-network algorithm for VLSI cell placement.
Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail
1998-12-01
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
Chen, Wai-Kai
2003-01-01
A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi
Large-scale circuit simulation
Wei, Y. P.
1982-12-01
The simulation of VLSI (Very Large Scale Integration) circuits falls beyond the capabilities of conventional circuit simulators like SPICE. On the other hand, conventional logic simulators can only give the results of logic levels 1 and 0 with the attendent loss of detail in the waveforms. The aim of developing large-scale circuit simulation is to bridge the gap between conventional circuit simulation and logic simulation. This research is to investigate new approaches for fast and relatively accurate time-domain simulation of MOS (Metal Oxide Semiconductors), LSI (Large Scale Integration) and VLSI circuits. New techniques and new algorithms are studied in the following areas: (1) analysis sequencing (2) nonlinear iteration (3) modified Gauss-Seidel method (4) latency criteria and timestep control scheme. The developed methods have been implemented into a simulation program PREMOS which could be used as a design verification tool for MOS circuits.
1980-04-17
been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE
The Fifth NASA Symposium on VLSI Design
1993-01-01
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.
Low-power Analog VLSI Implementation of Wavelet Transform
Institute of Scientific and Technical Information of China (English)
ZHANG Jiang-hong
2009-01-01
For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.
Efficient VLSI architecture for training radial basis function networks.
Fan, Zhe-Cheng; Hwang, Wen-Jyi
2013-03-19
This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Modeling selective attention using a neuromorphic analog VLSI device.
Indiveri, G
2000-12-01
Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.
Efficient VLSI Architecture for Training Radial Basis Function Networks
Directory of Open Access Journals (Sweden)
Wen-Jyi Hwang
2013-03-01
Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
VLSI Watermark Implementations and Applications
Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly
2008-01-01
This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...
一种适用于电源系统的无过冲软启动电路%Soft-start circuit without overshoot for power supply
Institute of Scientific and Technical Information of China (English)
樊海峰; 孙成峰; 贺顺生; 朱为朋
2015-01-01
提出了一种适用于快速响应电源管理系统中的软启动电路。该电路利用运算放大器钳位反馈原理，实现了平稳无过冲的软启动切换。基于0.25μm BCD（双极型晶体管、互补型金属氧化物场效应管及高功率双扩散半导体场效应管集成技术）工艺，对所设计电路进行了仿真验证。仿真结果表明，该电路在–40～+125℃的温度范围内都能够实现稳定的软启动切换。结合系统整体仿真结果分析，本电路的性能达到了使电源系统稳定启动的预期目标，可用于对响应速度要求较高的避雷器监测系统。%A kind of soft-start circuit without overshoot suitable for power management module of high-speed response system was proposed. The clamp feedback circuit was used to realize stable switch without overshoot during the whole soft start process. Based on 0.25μm BCD technique(a kind of silicon processes combines the bipolar device, CMOS and DMOS for power and high-voltage elements), the circuit was verified by simulation. The simulation results show that the circuit can realize stable soft-start switch in a given temperature fluctuation range (–40–+125℃).Combined with the analysis of the whole system simulation results, the performance of the circuit achieves the expected goal of stable soft-start, and the module can be implemented in lightning guard monitor system, which has a high demand of response speed.
Bozhko, V. V.; Gorin, A. V.; Zaitsev, I. V.; Kovalev, I. A.; Nosovitskii, I. A.; Orlik, V. G.; Lomagin, S. N.; Chernov, V. P.
2017-03-01
At turbine starts with low steam flow rates in idle mode, the low-pressure rotor blades consume energy, causing the ventilation heating of the stages and creating higher depression in them than in the condenser. This leads to the return steam flows in the exhaust of the low-pressure cylinder (LPC), reducing the heat due to the moisture of starting steam damps and cooling injections. It is shown that, as a result of upgrading with the transition to fully milled shroud platforms of rotor blades, the depression in the stages decreases and their cooling efficiency is reduced due to the removal of an elastic turn of the rotor blades under the action of centrifugal forces and seal of them by periphery. Heating the rotor blades of the last stages exceeds the temperature threshold of soldering resistance of stellite plates (150°C), and their mass strips begin. The start-up circuit providing both the temperature retention of the last stages lower the soldering resistance threshold due to overwetting the steam damps up to saturation condition and the high degree of removal from the dump steam of excessive erosive-dangerous condensed moisture was proposed, applied, and tested at the operating power unit. The investment in the development and application of the new start-up circuit are compensated in the course of a year owing to guaranteed prevention of the strips of stellite plates that lengthens the service life of the rotor blades of the last stages as well as increase of the rotor blade efficiency due to the sharp decrease of erosive wear of the profiles and reduction of their surface roughness. This reduces the annual consumption of equivalent fuel by approximately 1000 t for every 100 MW of installed capacity.
Surface and interface effects in VLSI
Einspruch, Norman G
1985-01-01
VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import
VLSI implementation of neural networks.
Wilamowski, B M; Binfet, J; Kaynak, M O
2000-06-01
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.
Circuit design for reliability
Cao, Yu; Wirth, Gilson
2015-01-01
This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.
Directory of Open Access Journals (Sweden)
Miss. Rachana R. Patil
2015-01-01
Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology
Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W
2006-01-01
We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.
New VLSI complexity results for threshold gate comparison
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1996-12-31
The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.
VLSI technology for smaller, cheaper, faster return link systems
Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John
1994-01-01
Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.
VLSI design techniques for floating-point computation
Energy Technology Data Exchange (ETDEWEB)
Bose, B. K.
1988-01-01
The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.
VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network
Hsieh, Hung-Yi; Tang, Kea-Tiong
2011-11-01
This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.
Fey, D; Kasche, B; Burkert, C; Tschäche, O
1998-01-10
A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.
New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Directory of Open Access Journals (Sweden)
M. V. Atre
1995-07-01
Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.
A Band Relaxation Algorithm for Reliable and Parallelizable Circuit Simulation
1988-08-01
Varga, Matriz Iterative Analysis, Prentice Hall, Englewood Cliffs, New Jersey, 1962. [WEB] D. M. Webber, A. Sangiovanni-Vincentelli, "Circuit Simulation...White, A. Sangiovanni-Vincentelli, Relazation Techniques for the Simulation of VLSI Circuits, Kluwer Pub., Boston , 1986. 11 (WIN] 0. wing, j. W. Huang
Low Power, Reduced Dynamic Voltage Swing Domino Logic Circuits
Salendra.Govindarajulu; Dr.T.Jayachandra Prasad; Rangappa, P
2010-01-01
Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. In this work, new reduced – swing domino logic techniques which provide significant low power dissipation as compared to traditional domino cir...
Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2011-03-01
Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.
Energy Technology Data Exchange (ETDEWEB)
Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)
2014-01-31
The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.
Institute of Scientific and Technical Information of China (English)
杜书平; 杨平
2013-01-01
This article through to XuJi ZFZ-822/A circuit breaker box start-up failure functional analysis, points out the circuit breaker box start-up failure functional advantages and disadvantages , and in the light of the shortcomings mentioned puts forward some improvement Suggestions, ensure circuit breaker failure protection correct action.%本文通过对许继 ZFZ-822/A 断路器操作箱起动失灵功能的分析，指出了操作箱起动失灵功能的优缺点，并针对所述缺点提出了改进建议，确保断路器失灵保护正确动作。
A Coherent VLSI Design Environment.
2014-09-26
physical devices from which physical circuits are fabricated. By analogy with context-free languages , a class of circuits is generated by a phrase-structure... language called CLU [131. It consists of SPICE interface, minimization, and matrix manipulation program modules. These modules contain 3200, 1800, and...greatly simplify the optimization problem. They reformulated the original problem, a minimization subject to nonlinear constraints, as an
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation
Massengill, Lloyd W.
1991-03-01
A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.
Alexander, George
1984-01-01
Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…
Motor Starting Control Circuit Fault Diagnosis and Elimination Methods%电动机启动控制线路的故障诊断与排除方法
Institute of Scientific and Technical Information of China (English)
胡永春
2015-01-01
电动机直接启动控制线路的常见故障有：按启动按钮后电动机不能启动；接通电源无须启动按钮控制，电动机自行运转；电动机启动运转后，手离开按钮电动机便停转；按下停机按钮，电动机不能停转，等等。本文阐述了Y-△降压启动控制线路的故障诊断与排除，自耦变压器降压启动线路的故障排除等问题。%the direct motor starting control circuit common fault are the main press the start button motor can not be started;the power supply is switched on without the start button control, motor bike;electric motor starts to work, the motor stops rotating hands off button; press the stop button, the motor can not stop etc.. This paper mainly introduces Y- reduced voltage starting control circuit fault diagnosis and elimination, autotransformer fault step-down start line to eliminate the problem.
Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2010-06-01
Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design
Brindley, Keith
2005-01-01
Starting Electronics is unrivalled as a highly practical introduction for hobbyists, students and technicians. Keith Brindley introduces readers to the functions of the main component types, their uses, and the basic principles of building and designing electronic circuits. Breadboard layouts make this very much a ready-to-run book for the experimenter; and the use of multimeter, but not oscilloscopes, puts this practical exploration of electronics within reach of every home enthusiast's pocket. The third edition has kept the simplicity and clarity of the original. New material
Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney
2006-01-01
We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
LIU; Yanpei(
2001-01-01
［1］Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.［2］Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.［3］Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.［4］Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.［5］Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.［6］Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.［7］Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.［8］Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.［9］Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.［10］Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.［11］Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.［12］Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.［13］Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
Directory of Open Access Journals (Sweden)
D.Yammenavar
2011-08-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.
Design and Analog VLSI Implementation of Artificial Neural Network
Directory of Open Access Journals (Sweden)
Prof. Bapuray.D.Yammenavar
2011-07-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.
Timing and Area Optimization for VLSI Circuit and Layout
1994-05-10
eigenvalues and eigenvectors of the matrices derived from the graph. A graph can be represented by the adjacency matriz A(G).I aii, if (vi, vi) E E •j =. (4.2...Design, vol. CAD-10, pp. 356-365, Mar. 1991. 3 [65] T. Saaao, ed., Logic Synthesis and Optimization. Boston , Massachussetts: Kluwer, 1993. [661 Y.-C. Ju
A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.
Rahimi Azghadi, Mostafa; Al-Sarawi, Said; Abbott, Derek; Iannella, Nicolangelo
2013-09-01
Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological experiments, while the PSTDP rule fails to reproduce them. Additionally, it has been shown that the behaviour inherent to the spike rate-based Bienenstock-Cooper-Munro (BCM) synaptic plasticity rule can also emerge from the TSTDP rule. This paper proposes an analogue implementation of the TSTDP rule. The proposed VLSI circuit has been designed using the AMS 0.35 μm CMOS process and has been simulated using design kits for Synopsys and Cadence tools. Simulation results demonstrate how well the proposed circuit can alter synaptic weights according to the timing difference amongst a set of different patterns of spikes. Furthermore, the circuit is shown to give rise to a BCM-like learning rule, which is a rate-based rule. To mimic an implementation environment, a 1000 run Monte Carlo (MC) analysis was conducted on the proposed circuit. The presented MC simulation analysis and the simulation result from fine-tuned circuits show that it is possible to mitigate the effect of process variations in the proof of concept circuit; however, a practical variation aware design technique is required to promise a high circuit performance in a large scale neural network. We believe that the proposed design can play a significant role in future VLSI implementations of both spike timing and rate based neuromorphic learning systems.
A Coherent VLSI Design Environment
1987-12-31
April 1, L0 A Mastiplexd Switched-Capacitor Filter Bank, Patrick Bosshart, MIT April 8, IM Analog Circuits in DOS PSI, Yannis Tsividis , Columbia...A.I. (Analog Intelligence), Yanni Tsividis , Columbia University, New York, NY December 2,1986 The Semiconductor Industry (Losing Sight of Your Added...Dept. of Elec. Eng. & Comp. Sci. 3:50 Yannis Tsividis and Dimitri A. Antoniadis, "A Mulitproject Chip i Approach to the Teaching of Analog MOS LSI and
Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
Directory of Open Access Journals (Sweden)
Ankush S. Patharkar
2014-07-01
Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.
Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En
2015-08-13
A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System
Directory of Open Access Journals (Sweden)
Horiuchi Timothy
2003-01-01
Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.
Harnessing VLSI System Design with EDA Tools
Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj
2012-01-01
This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...
Leak detection utilizing analog binaural (VLSI) techniques
Hartley, Frank T. (Inventor)
1995-01-01
A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.
Neuromorphic silicon neuron circuits
Directory of Open Access Journals (Sweden)
Giacomo eIndiveri
2011-05-01
Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.
Analogue VLSI for probabilistic networks and spike-time computation.
Murray, A
2001-02-01
The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.
Parallel optimization algorithms and their implementation in VLSI design
Lee, G.; Feeley, J. J.
1991-01-01
Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.
An introduction to logic circuit testing
Lala, Parag K
2008-01-01
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)
基于优化启动控制算法的电机驱动电路设计%Motor Drive Circuit Design Based on Optimization Start Control Algorithm
Institute of Scientific and Technical Information of China (English)
张福强
2013-01-01
针对复杂电机电路的驱动过程较为复杂、系统集成度高的特点，提出基于优化启动控制算法的电机驱动电路设计思路。通过建立电机的工作模型，设计了一种优化启动控制算法。该算法可以克服电机启动过程中，结构复杂带来的启动较慢的弊端；运用角速度和加速度的优化控制，解决了电机启动中的各项问题，使电机性能达到最优。计算机仿真实验结果表明，该算法能够实现电机的精确控制，优化效果明显。% According to the complex motor circuit driver process is relatively complex, system integration high character-istic, based on optimization start control algorithm of motor drive circuit design ideas, through the establishment of the motor working model. Designed a kind of optimization start control algorithm, can overcome the motor starting process, complicated structure brings the disadvantages of slow start. Using the angular velocity and acceleration, and the opti-mization control, solve the problem of the motor start, which makes the motor to achieve optimal performance. The com-puter simulation results show that the algorithm can realize accurate control of the motor and the optimization effect is ob-vious.
An Analog VLSI Saccadic Eye Movement System
1994-01-01
In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...
VLSI binary multiplier using residue number systems
Energy Technology Data Exchange (ETDEWEB)
Barsi, F.; Di Cola, A.
1982-01-01
The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.
Wavelength-encoded OCDMA system using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal
2007-07-01
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
The VLSI-PLM Board: Design, Construction, and Testing
1989-03-01
Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The
Bilinear Interpolation Image Scaling Processor for VLSI
Directory of Open Access Journals (Sweden)
Ms. Pawar Ashwini Dilip
2014-05-01
Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process
Optimization of reversible sequential circuits
Sayem, Abu Sadat Md
2010-01-01
In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.
The circuit designer's companion
Williams, Tim
2013-01-01
The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll
The 1992 4th NASA SERC Symposium on VLSI Design
Whitaker, Sterling R.
1992-01-01
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.
Interaction of algorithm and implementation for analog VLSI stereo vision
Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.
1991-07-01
Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...
NASA Space Engineering Research Center for VLSI System Design
1993-01-01
This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.
Directory of Open Access Journals (Sweden)
Fazal NOORBASHA
2012-08-01
Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.
Forecasting the Efficiency of Test Generation Algorithms for Combinational Circuits
Institute of Scientific and Technical Information of China (English)
徐拾义
2000-01-01
In this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit, choice of an algorithm from a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the Genetic Algorithm is used in order to construct an accurate model for some existing test generation algorithms that are being used everywhere in the world. Some objective quantitative measures are used as an effective tool in making such choice. Such measures are so important to the analysis of algorithms that they become one of the subjects of this work.
Design of delay insensitive circuits using multi-ring structures
DEFF Research Database (Denmark)
Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael
1992-01-01
The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...... into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial...
PLA realizations for VLSI state machines
Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.
1990-01-01
A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.
Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing
Khachab, Nabil Ibrahim
1990-01-01
The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.
New VLSI smart sensor for collision avoidance inspired by insect vision
Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran
1995-01-01
An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.
DEFF Research Database (Denmark)
Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid
As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...
2012-01-01
In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...
EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
Directory of Open Access Journals (Sweden)
N. A. Avdeev
2015-01-01
Full Text Available A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.
An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model
Directory of Open Access Journals (Sweden)
McEwan Alistair
2003-01-01
Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.
CMOS VLSI Active-Pixel Sensor for Tracking
Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie
2004-01-01
An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The
Advanced plasma etching processes for dielectric materials in VLSI technology
Wang, Juan Juan
Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the
Knowledge-based synthesis of custom VLSI physical design tools: First steps
Setliff, Dorothy E.; Rutenbar, Rob A.
A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.
VLSI design of 3D display processing chip for binocular stereo displays
Institute of Scientific and Technical Information of China (English)
Ge Chenyang; Zheng Nanning
2010-01-01
In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.
Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
Directory of Open Access Journals (Sweden)
HOO, C.-S.
2013-02-01
Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.
VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Li, Kang; Yu, Juebang; Li, Jian
In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
Design of a reliable and self-testing VLSI datapath using residue coding techniques
Sayers, I. L.; Kinniment, D. J.; Chester, E. G.
1986-05-01
The application of a residue code to check the data-path of a CPU is discussed. The structure of the data-path and the instruction set that it can perform are described, including the data-path registers, ALU, and control. The use of a mode 3 residue code to check the data-path is described in detail, giving logic diagrams and circuit layouts. The results are compared to those that might be obtained using Scan Path or BILBO techniques. The use of the residue code provides fault tolerance in a VLSI design at a small cost compared to triple modular redundancy and duplication techniques. A detailed evaluation of the increase in chip area required to produce a self-testing chip is also given.
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj
1993-01-01
Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.
A study of relaxation techniques for the transient analysis of digital circuits
Chia, W. K.
1985-06-01
In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a standard circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the standard simulation approach, namely, tearing decomposition and relaxation decomposition. This research is to study the numerical convergence and stability properties of several of the relaxation algorithms that have been proposed for the simulation of VLSI circuits. The time-point Gauss-Seidel method with prediction, the exploitation of latency and event scheduling algorithms are implemented into a general purpose circuit simulator SLATE-R (a Simulator with Latency and Tearing--Relaxed version). The performance of the SLATE-R program in the analysis of various types of integrated circuit technologies is studied.
VLSI digital demodulator co-processor
Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.
A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.
VLSI micro- and nanophotonics science, technology, and applications
Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati
2011-01-01
Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe
AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT
Directory of Open Access Journals (Sweden)
Y. Y. Lankevich
2015-01-01
Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.
A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.
Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang
2016-12-07
The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.
An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm
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Ying-Lun Chen
2015-08-01
Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search
Directory of Open Access Journals (Sweden)
Yuan-Jyun Chang
2016-12-01
Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.
Carry Select Adder Circuit with A Successively Incremented Carry Number Block
Deepak; Bal Krishan
2014-01-01
This paper reports a conditional carry select (CCS) adder circuit with a successively-incremented-carry-number block (SICNB) structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB) structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional Carry select adder based on the SPICE results
Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation
Institute of Scientific and Technical Information of China (English)
WANG Zhen; JIANG Jianhui; YANG Guang
2007-01-01
The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.
Cosp Vilella, Jordi; Martínez García, Herminio
2015-01-01
Hybrid DC-DC regulators are structures that combine both a linear voltage regulator and a switching DC-DC converter. The main objective of this hybrid topology is to converge, in a single circuit topology, the best of both alternatives: a small voltage output ripple, which is a common characteristic of linear regulator circuits, and good energy efficiency, as in switching alternatives. While the linear regulator fixes the required output voltage to a fixed value with negligible steady-state r...
Abramov, I. I.
2006-05-01
An automatic synthesis method of equivalent circuits of integrated circuit devices is described in the paper. This method is based on a physical approach to construction of finite-difference approximation to basic equations of semiconductor device physics. It allows to synthesize compact equivalent circuits of different devices automatically as alternative to, for example, sufficiently formal BSIM2 and BSIM3 models used in circuit simulation programs of SPICE type. The method is one of possible variants of general methodology for automatic synthesis of compact equivalent circuits of almost arbitrary devices and circuit-type structures of micro- and nanoelecronics [1]. The method is easily extended in the case of necessity to account thermal effects in integrated circuits. It was shown that its application would be especially perspective for analysis of integrated circuit fragments as a whole and for identification of significant collective physical effects, including parasitic effects in VLSI and ULSI. In the paper the examples illustrating possibilities of the method for automatic synthesis of compact equivalent circuits of some of semiconductor devices and integrated circuit devices are considered. Special attention is given to examples of integrated circuit devices for coarse grids of spatial discretization (less than 10 nodes).
Ramachandran, S
2007-01-01
Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs
Timergenerator circuits manual
Marston, R M
2013-01-01
Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen
CMOS VLSI Layout and Verification of a SIMD Computer
Zheng, Jianqing
1996-01-01
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
An efficient interpolation filter VLSI architecture for HEVC standard
Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang
2015-12-01
The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.
Tungsten and other refractory metals for VLSI applications II
Energy Technology Data Exchange (ETDEWEB)
Broadbent, E.K.
1987-01-01
This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.
An Interactive Multimedia Learning Environment for VLSI Built with COSMOS
Angelides, Marios C.; Agius, Harry W.
2002-01-01
This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…
Design of the Efficient Nanometric Reversible Subtractor Circuit
Directory of Open Access Journals (Sweden)
Mozhgan Shiri
2012-11-01
Full Text Available Reversible logic has comprehensive applications in communications, quantum computing, low power VLSI design, computer graphics, cryptography, nanotechnology, and optical computing. It has received significant attention in low power dissipating circuit design in the past few years. While several researchers have inspected the design of reversible logic units, there is not much reported works on reversible subtractors. In this paper we proposed the quantum equivalent circuit for SRK gate and we have computed the quantum cost of SRK gate. We also showed that how SRK gate can work singly as a half-subtractor circuit. It is being tried to design the circuit optimal in terms of number of reversible gates, number of garbage outputs, number of constant inputs, and quantum cost with compared to the existing circuits. At last we proposed an implementation of the new full-subtractor circuit based on SRK gate. All the designs have nanometric scales.
Designing Low Power Circuits: A Review
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Rohan M Joshi
2012-09-01
Full Text Available The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented.
Gate-Level Simulation of Quantum Circuits
Viamontes, G F; Markov, I L; Hayes, J P; Viamontes, George F.; Rajagopalan, Manoj; Markov, Igor L.; Hayes, John P.
2002-01-01
While thousands of experimental physicists and chemists are currently trying to build scalable quantum computers, it appears that simulation of quantum computation will be at least as critical as circuit simulation in classical VLSI design. However, since the work of Richard Feynman in the early 1980s little progress was made in practical quantum simulation. Most researchers focused on polynomial-time simulation of restricted types of quantum circuits that fall short of the full power of quantum computation. Simulating quantum computing devices and useful quantum algorithms on classical hardware now requires excessive computational resources, making many important simulation tasks infeasible. In this work we propose a new technique for gate-level simulation of quantum circuits which greatly reduces the difficulty and cost of such simulations. The proposed technique is implemented in a simulation tool called the Quantum Information Decision Diagram (QuIDD) and evaluated by simulating Grover's quantum search al...
Automatic Test Pattern Generation for Digital Circuits
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S. Hemalatha
2014-04-01
Full Text Available Digital circuits complexity and density are increasing and at the same time it should have more quality and reliability. It leads with high test costs and makes the validation more complex. The main aim is to develop a complete behavioral fault simulation and automatic test pattern generation (ATPG system for digital circuits modeled in verilog and VHDL. An integrated Automatic Test Generation (ATG and Automatic Test Executing/Equipment (ATE system for complex boards is developed here. An approach to use memristors (resistors with memory in programmable analog circuits. The Main idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor’s states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor -based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us. A multiplexer is developed to generate a class of minimum transition sequences. The entire hardware is realized as digital logical circuits and the test results are simulated in Model sim software. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC.
ESD analog circuits and design
Voldman, Steven H
2014-01-01
A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres
A compact 3D VLSI classifier using bagging threshold network ensembles.
Bermak, A; Martinez, D
2003-01-01
A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.
A neuromorphic VLSI device for implementing 2-D selective attention systems.
Indiveri, G
2001-01-01
Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.
Design of Analog VLSI Architecture for DCT
2012-01-01
When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...
Optimization of circuits using a constructive learning algorithm
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1997-05-01
The paper presents an application of a constructive learning algorithm to optimization of circuits. For a given Boolean function f. a fresh constructive learning algorithm builds circuits belonging to the smallest F{sub n,m} class of functions (n inputs and having m groups of ones in their truth table). The constructive proofs, which show how arbitrary Boolean functions can be implemented by this algorithm, are shortly enumerated An interesting aspect is that the algorithm can be used for generating both classical Boolean circuits and threshold gate circuits (i.e. analogue inputs and digital outputs), or a mixture of them, thus taking advantage of mixed analogue/digital technologies. One illustrative example is detailed The size and the area of the different circuits are compared (special cost functions can be used to closer estimate the area and the delay of VLSI implementations). Conclusions and further directions of research are ending the paper.
Performance Analysis of Modified QSERL Circuit
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Shipra Upadhyay
2013-08-01
Full Text Available This work is based on a new approach for minimizing energy consumption in quasi static energy recoverylogic (QSERL circuit which involves optimization by removing the non adiabatic losses completely.Energy recovering circuitry based on adiabatic principles is a promising technique leading towards lowpowerhigh performance circuit design. The efficiency of such circuits may be increased by reducing theadiabatic and non-adiabatic losses drawn by them during the charging and recovery operations. In thispaper, performance of the proposed logic style is analyzed and compared with CMOS in theirrepresentative inverters, gates, flip flops and adder circuits. All the circuits were simulated by VIRTUOSOSPECTRE simulator of Cadence in 0.18μm technology. In our proposed inverter the energy efficiency hasbeen improved to almost 30% & 20% upto 20MHz and 20fF external load capacitance in comparison toCMOS & QSERL circuits respectively. Our proposed circuit provides energy efficient performance up to100 MHz and thus it has proven to be used in high-performance VLSI circuitry.
VLSI physical design analyzer: A profiling and data mining tool
Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi
2015-03-01
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Embedded Processor Based Automatic Temperature Control of VLSI Chips
Directory of Open Access Journals (Sweden)
Narasimha Murthy Yayavaram
2009-01-01
Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.
VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION
Directory of Open Access Journals (Sweden)
John Moses C
2014-05-01
Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.
Opto-VLSI-based tunable single-mode fiber laser.
Xiao, Feng; Alameh, Kamal; Lee, Tongtak
2009-10-12
A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.
VLSI neural system architecture for finite ring recursive reduction.
Zhang, D; Jullien, G A
1996-12-01
The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.
A systematic method for configuring VLSI networks of spiking neurons.
Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney
2011-10-01
An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.
Opto-VLSI-based N × M wavelength selective switch.
Xiao, Feng; Alameh, Kamal
2013-07-29
In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.
Digital VLSI algorithms and architectures for support vector machines.
Anguita, D; Boni, A; Ridella, S
2000-06-01
In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.
Design of a VLSI Decoder for Partially Structured LDPC Codes
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Fabrizio Vacca
2008-01-01
of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.
Diseño digital : una perspectiva VLSI-CMOS
Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel
1996-01-01
Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.
Circuit analysis with Multisim
Baez-Lopez, David
2011-01-01
This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo
Lloris Ruiz, Antonio; Parrilla Roure, Luis; García Ríos, Antonio
2014-01-01
This book presents a complete and accurate study of algebraic circuits, digital circuits whose performance can be associated with any algebraic structure. The authors distinguish between basic algebraic circuits, such as Linear Feedback Shift Registers (LFSRs) and cellular automata, and algebraic circuits, such as finite fields or Galois fields. The book includes a comprehensive review of representation systems, of arithmetic circuits implementing basic and more complex operations, and of the residue number systems (RNS). It presents a study of basic algebraic circuits such as LFSRs and cellular automata as well as a study of circuits related to Galois fields, including two real cryptographic applications of Galois fields.
Radiation tolerant back biased CMOS VLSI
Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)
2003-01-01
A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.
Robust Bioinformatics Recognition with VLSI Biochip Microsystem
Lue, Jaw-Chyng L.; Fang, Wai-Chi
2006-01-01
A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.
Directory of Open Access Journals (Sweden)
S. Karunakaran
2012-01-01
Full Text Available Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW and clock cycle (ns of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW and clock cycle (ns are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.
Neuromorphic VLSI realization of the hippocampal formation.
Aggarwal, Anu
2016-05-01
The medial entorhinal cortex grid cells, aided by the subicular head direction cells, are thought to provide a matrix which is utilized by the hippocampal place cells for calculation of position of an animal during spatial navigation. The place cells are thought to function as an internal GPS for the brain and provide a spatiotemporal stamp on episodic memories. Several computational neuroscience models have been proposed to explain the place specific firing patterns of the cells of the hippocampal formation - including the GRIDSmap model for grid cells and Bayesian integration for place cells. In this work, we present design and measurement results from a first ever system of silicon circuits which successfully realize the function of the hippocampal formation of brain based on these models.
Design of Analog VLSI Architecture for DCT
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M.Thiruveni
2012-08-01
Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.
A VLSI Neural Monitoring System With Ultra-Wideband Telemetry for Awake Behaving Subjects.
Greenwald, E; Mollazadeh, M; Hu, C; Wei Tang; Culurciello, E; Thakor, V
2011-04-01
Long-term monitoring of neuronal activity in awake behaving subjects can provide fundamental information about brain dynamics for neuroscience and neuroengineering applications. Here, we present a miniature, lightweight, and low-power recording system for monitoring neural activity in awake behaving animals. The system integrates two custom designed very-large-scale integrated chips, a neural interface module fabricated in 0.5 μm complementary metal-oxide semiconductor technology and an ultra-wideband transmitter module fabricated in a 0.5 μm silicon-on-sapphire (SOS) technology. The system amplifies, filters, digitizes, and transmits 16 channels of neural data at a rate of 1 Mb/s. The entire system, which includes the VLSI circuits, a digital interface board, a battery, and a custom housing, is small and lightweight (24 g) and, thus, can be chronically mounted on small animals. The system consumes 4.8 mA and records continuously for up to 40 h powered by a 3.7-V, 200-mAh rechargeable lithium-ion battery. Experimental benchtop characterizations as well as in vivo multichannel neural recordings from awake behaving rats are presented here.
Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.
Yu, T; Sejnowski, T J; Cauwenberghs, G
2011-10-01
We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.
VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm
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Fazal Noorbasha
2014-04-01
Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.
Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm
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I. Hameem Shanavas
2014-01-01
Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
Advances in VLSI testing at MultiGb per second rates
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Topisirović Dragan
2005-01-01
Full Text Available Today's high performance manufacturing of digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps. Testing at Gbps needs high transfer rates among channels and functional units, and requires readdressing of data format and communication within a serial mode. This implies that a physical phenomena-jitter, is becoming very essential to tester operation. This establishes functional and design shift, which in turn dictates a corresponding shift in test and DFT (Design for Testability methods. We, here, review various approaches and discuss the tradeoffs in testing actual devices. For industry, volume-production stage and testing of multigigahertz have economic challenges. A particular solution based on the conventional ATE (Automated Test Equipment resources, that will be discussed, allows for accurate testing of ICs with many channels and this systems can test ICs at 2.5 Gbps over 144 cannels, with extensions planned that will have test rates exceeding 5 Gbps. Yield improvement requires understanding failures and identifying potential sources of yield loss. This text focuses on diagnosing of random logic circuits and classifying faults. An interesting scan-based diagnosis flow, which leverages the ATPG (Automatic Test Pattern Generator patterns originally generated for fault coverage, will be described. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.
Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute
Williams, John Michael
2014-01-01
This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics inclu...
VLSI design of an RSA encryption/decryption chip using systolic array based architecture
Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi
2016-09-01
This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.
High-performance VLSI architectures for turbo decoders with QPP interleaver
Verma, Shivani; Kumar, S.
2015-04-01
This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.
Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits
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Anindya Jana
2012-05-01
Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.
Lossless compression of VLSI layout image data.
Dai, Vito; Zakhor, Avideh
2006-09-01
We present a novel lossless compression algorithm called Context Copy Combinatorial Code (C4), which integrates the advantages of two very disparate compression techniques: context-based modeling and Lempel-Ziv (LZ) style copying. While the algorithm can be applied to many lossless compression applications, such as document image compression, our primary target application has been lossless compression of integrated circuit layout image data. These images contain a heterogeneous mix of data: dense repetitive data better suited to LZ-style coding, and less dense structured data, better suited to context-based encoding. As part of C4, we have developed a novel binary entropy coding technique called combinatorial coding which is simultaneously as efficient as arithmetic coding, and as fast as Huffman coding. Compression results show C4 outperforms JBIG, ZIP, BZIP2, and two-dimensional LZ, and achieves lossless compression ratios greater than 22 for binary layout image data, and greater than 14 for gray-pixel image data.
Design of a current Mode Sample and Hold Circuit at sampling rate of 150 MS/s
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Prity Yadav
2014-10-01
Full Text Available A current mode sample and hold circuit is presented in this paper at 180nm technology. The major concerns of VLSI are area, power, delay and speed. Hence, we have used a MOSFET in triode region in the proposed architecture for voltage to current conversion instead of a resistor being used in previously proposed circuit. The proposed circuit achieves high sampling frequency and with more accuracy than the previous one. The performance of the proposed circuit is depicted in the form of simulation results.
Imaging with polycrystalline mercuric iodide detectors using VLSI readout
Energy Technology Data Exchange (ETDEWEB)
Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J
1999-06-01
Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.
VLSI implementations of threshold logic-a comprehensive survey.
Beiu, V; Quintana, J M; Avedillo, M J
2003-01-01
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.
1992-01-01
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.
VLSI architectures for modern error-correcting codes
Zhang, Xinmiao
2015-01-01
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI
VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER
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Joseph Gladwin Sekar
2013-01-01
Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.
Formal verification an essential toolkit for modern VLSI design
Seligman, Erik; Kumar, M V Achutha Kiran
2015-01-01
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific
VLSI implementation of a fairness ATM buffer system
DEFF Research Database (Denmark)
Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard
1996-01-01
This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...
An adaptive, lossless data compression algorithm and VLSI implementations
Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu
1993-01-01
This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.
A VLSI Algorithm for Calculating the Treee to Tree Distance
Institute of Scientific and Technical Information of China (English)
徐美瑞; 刘小林
1993-01-01
Given two ordered,labeled trees βand α，to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.
Advanced field-solver techniques for RC extraction of integrated circuits
Yu, Wenjian
2014-01-01
Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...
Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips
Institute of Scientific and Technical Information of China (English)
WANGJun
2004-01-01
Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.
A VLSI design concept for parallel iterative algorithms
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C. C. Sun
2009-05-01
Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.
Carry Select Adder Circuit with A Successively Incremented Carry Number Block
Directory of Open Access Journals (Sweden)
Deepak
2014-04-01
Full Text Available This paper reports a conditional carry select (CCS adder circuit with a successively-incremented-carry-number block (SICNB structure for low-voltage VLSI implementation. Owing to the successively-incremented-carry-number block (SICNB structure, the new 16-bit SICNB CCS adder provides a 37% faster speed as compared to the conventional conditional Carry select adder based on the SPICE results
2008-03-27
Reconfigurable FPGAs”. IEICE Trans. Fundam. Electron . Commun. Comput. Sci., E89-A(12):3416–3426, 2006. ISSN 0916-8508. 42. Tseng, C. “Lock Your Designs...Implementation of the Advanced Encryption Standard”. IEEE Transactions on Computers, 52(4):493–505, April 2003. URL http://euler.ecs.umass.edu/research...Bushnell, Vishwani D. Agrawal. Essentials of Electronic Testing for Digital Memory & Mixed-Signal VLSI Circuits. Springer, 2000. ISBN 0-7923- 7991-8. 35
Directory of Open Access Journals (Sweden)
Urard Pascal
2006-01-01
Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.
Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D
2014-01-01
The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Directory of Open Access Journals (Sweden)
Omnia S. Fadl
2016-01-01
Full Text Available Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station
Kwatra, S. C.; King, Brent
1995-01-01
This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Directory of Open Access Journals (Sweden)
Cavallaro Joseph R
2006-01-01
Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.
Opto-VLSI-based reconfigurable free-space optical interconnects architecture
DEFF Research Database (Denmark)
Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;
2007-01-01
is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....
Real-time simulation of biologically realistic stochastic neurons in VLSI.
Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie
2010-09-01
Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.
Pop, Paul; Madsen, Jan
2016-01-01
This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...
International Conference on Nano-electronics, Circuits & Communication Systems
2017-01-01
This volume comprises select papers from the International Conference on Nano-electronics, Circuits & Communication Systems(NCCS). The conference focused on the frontier issues and their applications in business, academia, industry, and other allied areas. This international conference aimed to bring together scientists, researchers, engineers from academia and industry. The book covers technological developments and current trends in key areas such as VLSI design, IC manufacturing, and applications such as communications, ICT, and hybrid electronics. The contents of this volume will prove useful to researchers, professionals, and students alike.
Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.
Mustafa, Haithem; Xiao, Feng; Alameh, Kamal
2011-10-24
A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.
Resonance circuits for adiabatic circuits
Directory of Open Access Journals (Sweden)
C. Schlachta
2003-01-01
Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.
Carvajal, Gonzalo; Figueroa, Miguel
2014-07-01
Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.
A Circuit Extraction System and Graphical Display for VLSI (Very Large Scale Integrated) Design.
1989-12-01
drain ?source ? ? ?x ?y) (not (ntrans ? ?gate ?drain ?source ? ?)) (not (ntrans ? ?gate ?source ?drain ? ?)) (retract ?n) (assert (ntrans =( gensym ... gensym ) ?gate ?drain ?source ?x ?y))) ;; del-id-n deletes a n type transistor if it has already been asserted, with the same gate, source and drain...ptrans ? ?gate ?drain ?source ? ?)) (not (ptrans ? ?gate ?source ?drain ? ?)) (retract ?p) (assert (ptrans =( gensym ) ?gate ?drain ?source ?x ?y))) ;; del
Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit
Zhang, Xiangyu; An, Fengwei; Chen, Lei; Jürgen Mattausch, Hans
2016-04-01
As an alternative to conventional single-instruction-multiple-data (SIMD) mode solutions with massive parallelism for self-organizing-map (SOM) neural network models, this paper reports a memory-based proposal for the learning vector quantization (LVQ), which is a variant of SOM. A dual-mode LVQ system, enabling both on-chip learning and classification, is implemented by using a reconfigurable pipeline with parallel p-word input (R-PPPI) architecture. As a consequence of the reuse of R-PPPI for solving the most severe computational demands in both modes, power dissipation and Si-area consumption can be dramatically reduced in comparison to previous LVQ implementations. In addition, the designed LVQ ASIC has high flexibility with respect to feature-vector dimensionality and reference-vector number, allowing the execution of many different machine-learning applications. The fabricated test chip in 180 nm CMOS with parallel 8-word inputs and 102 K-bit on-chip memory achieves low power consumption of 66.38 mW (at 75 MHz and 1.8 V) and high learning speed of (R + 1) × \\lceil d/8 \\rceil + 10 clock cycles per d-dimensional sample vector where R is the reference-vector number.
A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits
Directory of Open Access Journals (Sweden)
Pushpa Saini
2012-10-01
Full Text Available Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In this paper, a technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature.
1984-01-31
T. Tsong, "The Role of Chlorine in the Gettering of Metallic Impurities from Silicon, Abstract #399, 160th Meeting of The Electrochemical Society , Denver...Diffusion of Oxygen from Czochralski Silicon," Abstract #335, 164th Meeting of The Electrochemical Society , Washington, D.C. (1983). 8. T. A. Baginski, D. A...34 Recent News Paper, 164th Meeting of The Electrochemical Society , Washington, D.C. (1983). 9. J. R. Monkowski, D. Heck, T. A. Baginski, D. Kenney, and R
Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design
Directory of Open Access Journals (Sweden)
Sumit Vaidya
2010-07-01
Full Text Available A typical processor central processing unit devotes a considerable amount of processing time inperforming arithmetic operations, particularly multiplication operations. Multiplication is one of thebasic arithmetic operations and it requires substantially more hardware resources and processing timethan addition and subtraction. In fact, 8.72% of all the instruction in typical processing units ismultiplication. In this paper, comparative study of different multipliers is done for low power requirementand high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient IndianVedic Mathematics which is utilized for multiplication to improve the speed, area parameters ofmultipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e.“Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.
Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices
1980-01-01
fast pulled with no Ar anneal. -19- C. Phv,,ical Modeling. of the Oxidation Pr’ocess Quantitative analysis was made of the Si -a x- cristobalite ...given in Fig. 14. In1 the same plot, the number n12 (0) of SiI defects in the a- cristobalite unit cell at the interface is given (here, Si and SiO 2...at the meeting. The GEMINI (formerly TANDEM) program was completed and prepared for release. As indicated in the Appendix, the entire second day of the
Cascaded VLSI Chips Help Neural Network To Learn
Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.
1993-01-01
Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.
Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.
Abdelhalim, K; Smolyakov, V; Genov, R
2011-10-01
A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.
Event-driven neural integration and synchronicity in analog VLSI.
Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert
2012-01-01
Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.
VLSI-based Video Event Triggering for Image Data Compression
Williams, Glenn L.
1994-01-01
Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
1992-01-01
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
Carbon nanotube based VLSI interconnects analysis and design
Kaushik, Brajesh Kumar
2015-01-01
The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.
Realistic model of compact VLSI FitzHugh-Nagumo oscillators
Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel
2014-02-01
In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.
Power Efficient Sub-Array in Reconfigurable VLSI Meshes
Institute of Scientific and Technical Information of China (English)
Ji-Gang Wu; Thambipillai Srikanthan
2005-01-01
Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.
Replacing design rules in the VLSI design cycle
Hurley, Paul; Kryszczuk, Krzysztof
2012-03-01
We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.
Parallel optical interconnects utilizing VLSI/FLC spatial light modulators
Genco, Sheryl M.
1991-12-01
Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
A digital neuron-type processor and its VLSI design
Akel, H.; Habib, Mahmoud K.
1989-05-01
A set of neuron-type circuits elements based on logic gate circuits with multiinput multifan output capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base, and the axon circuit. These three elements are cascaded to form a neuron-type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VSLI techniques.
DEFF Research Database (Denmark)
Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid
As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...... transistor to alleviate the sensitivity of the dynamic node to noise and results in improved performance. The new circuit has been added to conventional footed standard domino logic for highly improving leakage tolerance, especially at the beginning of the evaluation phase. According to simulation results...
Merrill, L.C.
1958-10-14
Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.
Panigrahy, Rina
2012-01-01
There is a vast supply of prior art that study models for mental processes. Some studies in psychology and philosophy approach it from an inner perspective in terms of experiences and percepts. Others such as neurobiology or connectionist-machines approach it externally by viewing the mind as complex circuit of neurons where each neuron is a primitive binary circuit. In this paper, we also model the mind as a place where a circuit grows, starting as a collection of primitive components at birth and then builds up incrementally in a bottom up fashion. A new node is formed by a simple composition of prior nodes when we undergo a repeated experience that can be described by that composition. Unlike neural networks, however, these circuits take "concepts" or "percepts" as inputs and outputs. Thus the growing circuits can be likened to a growing collection of lambda expressions that are built on top of one another in an attempt to compress the sensory input as a heuristic to bound its Kolmogorov Complexity.
Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis
2005-06-01
In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.
Complex VLSI Feature Comparison for Commercial Microelectronics Verification
2014-03-27
verification of untrusted circuits using industry-standard and custom software. The process developed under TRUST and implemented at the AFRL Mixed Signal...79 5.2.3 SCR and Other Netlists . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.4 Additional Tools...Reliability of Integrated Circuits LVS layout versus schematic MOSIS the Metal Oxide Semiconductor Implementation Service MSDC Mixed Signal Design
Automatic Circuit Extractor for HDL Description Using Program Slicing
Institute of Scientific and Technical Information of China (English)
Tun Li; Yang Guo; Si-Kun Li
2004-01-01
Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification,simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.
Research and design of the protection circuits in LD controller
Institute of Scientific and Technical Information of China (English)
SHAN Jiang-dong; TIAN Xiao-jian; DENG Jun; ZHANG Shuang
2006-01-01
According to the parameters and applications of laser diode (LD), three protection circuits were designed: the time-delay soft-start protection circuit, the power-on impulse protection circuit and the limit-current protection circuit. In this article, the structure and the principle of every protection circuit have been detailed. From several tests and feedbacks from customers, the expected goals have been completed.
Constant fan-in digital neural networks are VLSI-optimal
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1995-12-31
The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
High-energy heavy ion testing of VLSI devices for single event upsets and latch up
Indian Academy of Sciences (India)
S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra
2005-08-01
Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts
Scheibler, Robin; Chebira, Amina
2011-01-01
We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.
Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects
Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan
2016-03-01
In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.
Adaptive WTA with an analog VLSI neuromorphic learning chip.
Häfliger, Philipp
2007-03-01
In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.
VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement
Directory of Open Access Journals (Sweden)
Jigar Shah
2012-07-01
Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.
Efficient VLSI architecture of CAVLC decoder with power optimized
Institute of Scientific and Technical Information of China (English)
CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min
2009-01-01
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
A bioinspired collision detection algorithm for VLSI implementation
Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.
2005-06-01
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.
Parallel VLSI design for the fast -D DWT core algorithm
Institute of Scientific and Technical Information of China (English)
WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong
2007-01-01
By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.
DEFF Research Database (Denmark)
2010-01-01
A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...
Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.
Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak
2007-07-23
In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.
Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)
Institute of Scientific and Technical Information of China (English)
周涛; 吴行军; 白国强; 陈弘毅
2003-01-01
Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors
Directory of Open Access Journals (Sweden)
S. K. Nandy
1994-01-01
Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.
Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute
Williams, John
2008-01-01
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the
Research News: Are VLSI Microcircuits Too Hard to Design?
Robinson, Arthur L.
1980-01-01
This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)
A fast lightstripe rangefinding system with smart VLSI sensor
Gruss, Andrew; Carley, L. Richard; Kanade, Takeo
1989-01-01
The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.
A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar
Fang, W.
1994-01-01
For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.
Fully-depleted silicon-on-sapphire and its application to advanced VLSI design
Offord, Bruce W.
1992-01-01
In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.
VLSI chip-set for data compression using the Rice algorithm
Venbrux, J.; Liu, N.
1990-01-01
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A
1999-01-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
Bayoumi, Magdy
As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.
1999-05-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
1979-01-01
The U-shaped wire devices in the upper photo are Digi-Klipsm; aids to compact packaging of electrical and electronic devices. They serve as connectors linking the circuitry of one circuit board with another in multi-board systems. Digi-Klips were originally developed for Goddard Space Flight Center to meet a need for lightweight, reliable connectors to replace hand-wired connections formerly used in spacecraft. They are made of beryllium copper wire, noted for its excellent conductivity and its spring-like properties, which assure solid electrical contact over a long period of time.
IMPORTANT NOTICE: Cancellation of shuttle Circuit 3
2013-01-01
Circuit 3 of the CERN Shuttle Service (Point 5), which has served CMS since the start of LS1, will be cancelled with effect from Tuesday 16 April. This decision has been taken in consultation with CMS, as the circuit was seldom used. In response to increasing demand for Circuit 1 - Meyrin and feedback from passengers, the two Circuit 3 journeys will be switched to Circuit 1 – Meyrin (see new timetable below): Mornings: Four journeys instead of three. Circuit 1 now starts at 8:10 (instead of 8:19 a.m.) and runs until 9:27 a.m. (instead of 9:16 a.m.). Lunchtimes: Five journeys in place between 12:10 p.m. and 1:47 p.m. Evenings: Circuit starts at 5:23 p.m. (instead of 5:03 p.m.) and ends at 6:20 p.m. at Building 33. Please note that the circuit will depart from Building 13 instead of Building 33.
A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
Richstein, James K.
1993-12-01
Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.
Thermal Aware Floor planning Technique for Nano Circuits
Directory of Open Access Journals (Sweden)
G. Nallathambi
2014-09-01
Full Text Available The strongest challenge that a VLSI designer has to face today is the extremely high heat generation within a chip which not only degrades the performance but also the yield and reliability are greatly affected. The situation even became worse with the more number of wires in a single chip and due to path to path temperature variations within the chip. Nowadays VLSI circuits have immense variations in temperature and their linear relationship between metal resistance and temperature causes distinct delay through wires of the same length. The aim of this study is to analyze floor planning algorithms and wire plan methods to reduce the temperature dependent delay in global wires. We propose a temperature dependent wire delay estimation method for thermal aware floor planning algorithms, which takes into account the thermal effect on wire delay. The experiment results show that a shorter delay can be achieved, the congestion and reliability issues as they are closely related to routing and temperature using the proposed method.
Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Simplified design of filter circuits
Lenk, John
1999-01-01
Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets
Collective of mechatronics circuit
Energy Technology Data Exchange (ETDEWEB)
NONE
1987-02-15
This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.
Nanoelectronic circuit design and test
Simsir, Muzaffer Orkun
-alone nanowire circuits have been experimentally evaluated in research laboratories. In order to speed up development of nanowire circuits, and to increase the exposure to this technology, development of physical and logic-level design methodologies and tools for implementing VLSI designs are essential. In this thesis, we discuss an automated logic-to-layout design automation tool to fulfill this need for nanowires. The tool accepts a logic-level netlist and performs logic synthesis targeting nanowire cells. Then, since the defect levels in nanotechnologies are expected to be relatively high, it performs defect-aware placement and global routing. This is followed by the following steps: detailed routing, layout display, circuit extraction and SPICE simulation. We demonstrate preliminary results for area, delay and power for various benchmarks.
VLSI Architecture Of A Binary Up/Down Counter
Hsu, In-Shek; Truong, Trieu-Kie; Reed, I. S.
1988-01-01
Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.
He, Sailing; Zhang, Xizhou; He, Yingran
2013-12-16
Electronics circuits keep shrinking in dimensions, as requested by Moore's law. In contrast, photonic waveguides and circuit elements still have lateral dimensions on the order of the wavelength. A key to make photonics have a microelectronics-like development is a drastic reduction of size. To achieve this, we need a low-loss nanoscale waveguide with a drastically reduced mode area and an ultra-high effective refractive index. For this purpose, we propose here several low-loss waveguide structures based on graphene nano-ribbons. An extremely small mode area (~10(-7)λ(0)(2), one order smaller than the smallest mode area of any waveguide that has ever been reported in the literature; here λ(0) is the operating wavelength in vacuum) and an extremely large effective refractive index (several hundreds) are achieved. As a device example, a nano-ring cavity of ultra-small size (with a diameter of ~10(-2)λ(0)) is designed. Our study paves the way for future VLSI (very-large-scale integration) optoelectronics.
Integrated circuits in digital electronics (2nd revised and enlarged edition)
Barna, Arpad; Porat, Dan I.
This book provides a link between elementary logic design theory and its practical applications. New information on Schottky TTL, ECL, and CMOS is given, along with a study of number systems and a detailed description of the design of sequential logic with emphasis on counters and shift registers and a discussion of arithmetic circuits. A chapter on latches and flip-flops emphasizes the differences between these two storage elements. A summary of coding, code conversion, and error detection and correction is given along with descriptions of digital-to-analog and analog-to-digital converters. Up-to-date treatment of LSI and VLSI circuits is given, including static and dynamic circuits, RASMs, ROMs, PLSAs, associative memories, and gate arrays. There is also a unified presentation of practical considerations in digital equipment design.
An Optimized Device Sizing of Analog Circuits using Particle Swarm Optimization
Directory of Open Access Journals (Sweden)
K. Duraiswamy
2012-01-01
Full Text Available Problem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.. For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most challenging and time-consumed task, because it does not only consist of topology and layout synthesis but also of component sizing. Approach: A Particle Swarm Optimization (PSO technique for the optimal design of analog circuits. Analog signal processing finds many applications and widely uses OpAmp based amplifiers, mixers, comparators. and filters. Results: A two-stage opamp (Miller Operational Trans-conductance Amplifier (OTA is considered for the synthesis that satisfies certain design specifications. Performance has been evaluated with the Simulation Program with Integrated Circuit Emphasis (SPICE circuit simulator until optimal sizes of the transistors are found. Conclusion: The output of the simulation for the two-stage opamp shows that the PSO technique is an accurate and promising approach in determining the device sizes in an analog circuit.
A new wide range Euclidean distance circuit for neural network hardware implementations.
Gopalan, A; Titus, A H
2003-01-01
In this paper, we describe an analog very large-scale integration (VLSI) implementation of a wide range Euclidean distance computation circuit - the key element of many synapse circuits. This circuit is essentially a wide-range absolute value circuit that is designed to be as small as possible (80 /spl times/ 76 /spl mu/m) in order to achieve maximum synapse density while maintaining a wide range of operation (0.5 to 4.5 V) and low power consumption (less than 200 /spl mu/W). The circuit has been fabricated in 1.5-/spl mu/m technology through MOSIS. We present simulated and experimental results of the circuit, and compare these results. Ultimately, this circuit is intended for use as part of a high-density hardware implementation of a self-organizing map (SOM). We describe how this circuit can be used as part of the SOM and how the SOM is going to be used as part of a larger bio-inspired vision system based on the octopus visual system.
Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits
Directory of Open Access Journals (Sweden)
Rajani H.P
2012-09-01
Full Text Available Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The powerdissipation during inactive (standby mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipatinglower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits
Directory of Open Access Journals (Sweden)
Rajani H.P
2012-08-01
Full Text Available Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Xinjiang Dushanzi Project Started Construction Started Construction
Institute of Scientific and Technical Information of China (English)
无
2005-01-01
@@ Xinjiang Dushanzi petroleum refining and chemical integrated project,is the largest one so far in China, with a capacity of ten-million-ton petroleum refinery and onemillion-ton ethylene complex, directly under PetroChina Company Limited (PetroChina), was started construction along with laying a foundation on August 22, 2005.
Commutation circuit for an HVDC circuit breaker
Premerlani, William J.
1981-01-01
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.
Vertically Integrated Circuits at Fermilab
Energy Technology Data Exchange (ETDEWEB)
Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab
2009-01-01
The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.
Matsuzaka, Kenji; Tohara, Takashi; Nakada, Kazuki; Morie, Takashi
Analog CMOS circuit implementation of a system of pulse-coupled phase oscillators is proposed. A CMOS circuit that achieves the dynamics of pulse-coupled oscillators has been designed and fabricated using a 0.25-µm CMOS technology. The proposed oscillator circuits with continuous-time operation interact with each other via a pulse at each firing time. Update of the oscillator state is achieved by integrating the phase sensitivity function with the pulse width time span. The phase sensitivity function is generated by the combination of binary functions, while the function consists of three-values {-1,0,1}. Introducing a zero-value span in the function leads to fast synchronization and robustness to parameter fluctuation due to LSI device mismatches, which facilitates VLSI implementation. Using the fabricated CMOS circuit, we have observed not only in- and anti-phase but also out-of-phase synchronization.
Dynamic Power Reduction of Digital Circuits by ClockGating
Directory of Open Access Journals (Sweden)
Varsha Dewre
2017-04-01
Full Text Available In this paper we have presented clock gating process for low power VLSI (very large scale integration circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated
Analog circuit design designing dynamic circuit response
Feucht, Dennis
2010-01-01
This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.
Directory of Open Access Journals (Sweden)
Sneha Meryn Thomas
2014-08-01
Full Text Available It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL, offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Analog circuit design designing waveform processing circuits
Feucht, Dennis
2010-01-01
The fourth volume in the set Designing Waveform-Processing Circuits builds on the previous 3 volumes and presents a variety of analog non-amplifier circuits, including voltage references, current sources, filters, hysteresis switches and oscilloscope trigger and sweep circuitry, function generation, absolute-value circuits, and peak detectors.
Verheul, Ingrid; Thurik, Roy
2000-01-01
textabstractFemale and male entrepreneurs differ in the way they finance their businesses. This can be attributed to the type of business and the type of management and experience (indirect effect). Female start-ups may also experience other barriers based upon discriminatory effects (direct effect). Whether gender has an impact on size and composition of start-up capital, is the subject of the present paper. To test for these direct and indirect effects data of 2000 Dutch starting entreprene...
Harrison, R R; Koch, C
1999-10-01
Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.
A cost-effective methodology for the design of massively-parallel VLSI functional units
Venkateswaran, N.; Sriram, G.; Desouza, J.
1993-01-01
In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.
Xiao, Feng; Alameh, Kamal; Lee, Yong Tak
2009-12-07
A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.
VLSI architectures for computing multiplications and inverses in GF(2-m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.
1983-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
VLSI architectures for computing multiplications and inverses in GF(2m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.
1985-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
Las Vegas is better than determinism in VLSI and distributed computing
DEFF Research Database (Denmark)
Mehlhorn, Kurt; Schmidt, Erik Meineche
1982-01-01
to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...
International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking
Shirur, Yasha; Prasad, Rekha
2013-01-01
This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.
The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter
2001-09-01
December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60
Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.
Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz
2010-01-01
Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.
VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.
Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram
2010-01-01
In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.
Directory of Open Access Journals (Sweden)
Rachmad Vidya Wicaksana Putra
2016-06-01
Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
Neuromorphic VLSI vision system for real-time texture segregation.
Shimonomura, Kazuhiro; Yagi, Tetsuya
2008-10-01
The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.
A DRAM compiler algorithm for high performance VLSI embedded memories
Eldin, A. G.
1992-01-01
In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .
Handbook of VLSI microlithography principles, technology and applications
Glendinning, William B
1991-01-01
This handbook gives readers a close look at the entire technology of printing very high resolution and high density integrated circuit (IC) patterns into thin resist process transfer coatings-- including optical lithography, electron beam, ion beam, and x-ray lithography. The book's main theme is the special printing process needed to achieve volume high density IC chip production, especially in the Dynamic Random Access Memory (DRAM) industry. The book leads off with a comparison of various lithography methods, covering the three major patterning parameters of line/space, resolution, line e
Pridham, G J
2013-01-01
Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided
Simple Autonomous Chaotic Circuits
Piper, Jessica; Sprott, J.
2010-03-01
Over the last several decades, numerous electronic circuits exhibiting chaos have been proposed. Non-autonomous circuits with as few as two components have been developed. However, the operation of such circuits relies on the non-ideal behavior of the devices used, and therefore the circuit equations can be quite complex. In this paper, we present two simple autonomous chaotic circuits using only opamps and linear passive components. The circuits each use one opamp as a comparator, to provide a signum nonlinearity. The chaotic behavior is robust, and independent of nonlinearities in the passive components. Moreover, the circuit equations are among the algebraically simplest chaotic systems yet constructed.
Santiago, John
2013-01-01
Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help
Current limiter circuit system
Energy Technology Data Exchange (ETDEWEB)
Witcher, Joseph Brandon; Bredemann, Michael V.
2017-09-05
An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.
Simon, R. A.
1986-01-01
Electrical properties of solenoids imitated for tests of control circuits. Simulation circuit imitates voltage and current responses of two engine-controlling solenoids. Used in tests of programs of digital engine-control circuits, also provides electronic interface with circuits imitating electrical properties of pressure sensors and linear variable-differential transformers. Produces voltages, currents, delays, and discrete turnon and turnoff signals representing operation of solenoid in engine-control relay. Many such circuits used simulating overall engine circuitry.
Minnesota Department of Natural Resources — This table contains information about station starting locations. These locations indicate the reference point that was used as the origin for distance measurements...
U.S. Department of Health & Human Services — Longitudinal information from an evaluation where children were randomly assigned to Early Head Start or community services as usual;direct assessments and...
U.S. Department of Health & Human Services — Nationally representative, longitudinal information from an evaluation where children were randomly assigned to Head Start or community services as usual;direct...
Felicia, Patrick
2013-01-01
Getting Started with Unity is written in an easy-to-follow tutorial format.""Getting Started with Unity"" is for[ 3D game developers[/color] who would like to learn how to use Unity3D and become familiar with its core features. This book is also suitable for intermediate users who would like to improve their skills. No prior knowledge of Unity3D is required.
Psychiatric Advance Directives: Getting Started
... More... Home Getting Started National Resource Center on Psychiatric Advance Directives - Getting Started Getting Started Psychiatric advance directives (PADs) are relatively new legal instruments ...
Institute of Scientific and Technical Information of China (English)
CHEN Shennian
2005-01-01
Circuit theory is an extremely important basic theory in electrical and electronic sciences and technologies. Over more than a century, researchers have come to the conclusion that a fundamental law of circuits needs to satisfy the following three conditions: (1) Independency. It must be able to solve independently the basic problems of general solutions to the distribution of current and voltage in circuits. (2)Fundamentality. It cannot be derived from circuit theory and it must be the starting point for the establishment of circuit theory; it deduces the problem relevant to circuit theory by using purely logical inference, and establishes circuit theory into an independent deductive system. (3) Applicability. It must be widely applicable to all spheres of circuits,which includes sinusoidal steady-state linear and nonlinear networks, non-sinusoidal steady-state linear and nonlinear networks, transient-state processes, etc. From all networks to which the fundamental law of circuits applies, sinusoidal steady-state linear network is chosen as the most basic one to demonstrate that the two independent equations of circuits in integral form derived from Maxwell equations are able to meet these three conditions. Consequently, it is believed to be the fundamental law of circuits newly recognized today. This paper also makes the initiative to establish a circuit theory by which the basic rules of electromagnetic field govern the circuits, and the unity of electromagnetic fields and circuits is achieved.
Modelling of Human Glottis in VLSI for Low Power Architectures
Raj, Nikhil
2010-01-01
The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such as speech recognition and speech synthesis use the glottal closure and opening instants. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. General method concentrate on assessment of the glottis opening using optical, acoustical methods, or on visualization of the larynx position using ultrasound, computer tomography or magnetic resonance imaging techniques. In this work, circuit model of Human Glottis using MOS is designed by exploiting fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The glottis modeled as current source includes linear, non-linear impedances to represent laminar and turbulent flow respectively, in vocal tract. The MOS modelling and simula...
VLSI IMPLEMENTATION OF AN ANALOG MULTIPLIER FOR MODEM
Directory of Open Access Journals (Sweden)
SRIVIDYA .P,
2011-02-01
Full Text Available A modem (modulator-demodulator is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goalis to produce a signal that can be transmitted easily and decoded to reproduce the original digital data. Here there is a need to mix the signals of different frequencies or signals of different types, whichemphasizes the use of mixers or multipliers for different RF applications. In this paper, A CMOS analog multiplier, with less number of transistors which can operate at high frequencies with low power and high linearity is proposed. The multiplier works on the basis of parallel connected MOS operation circuit.
Design of High Performance Dynamic CMOS Circuits in Deep Submicron Technology
Directory of Open Access Journals (Sweden)
Salendra.Govindarajulu
2010-07-01
Full Text Available Technology scaling of transistor feature size has provided a remarkable advancement in silicon industry for the last three decades. The demand and popularity of portable electronics is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic logic design implementations of 16-bit Ripple carry adder, 16-bit Comparator and Linear Feedback Shift Register (LFSR in terms of CMOS layout power consumption, delay, power delay product, area for 65 nm and 45 nm technologies. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH3 CMOS layout CAD tools.
Hidden circuits and argumentation
Leinonen, Risto; Kesonen, Mikko H. P.; Hirvonen, Pekka E.
2016-11-01
Despite the relevance of DC circuits in everyday life and schools, they have been shown to cause numerous learning difficulties at various school levels. In the course of this article, we present a flexible method for teaching DC circuits at lower secondary level. The method is labelled as hidden circuits, and the essential idea underlying hidden circuits is in hiding the actual wiring of DC circuits, but to make their behaviour evident for pupils. Pupils are expected to find out the wiring of the circuit which should enhance their learning of DC circuits. We present two possible ways to utilise hidden circuits in a classroom. First, they can be used to test and enhance pupils’ conceptual understanding when pupils are expected to find out which one of the offered circuit diagram options corresponds to the actual circuit shown. This method aims to get pupils to evaluate the circuits holistically rather than locally, and as a part of that aim this method highlights any learning difficulties of pupils. Second, hidden circuits can be used to enhance pupils’ argumentation skills with the aid of argumentation sheet that illustrates the main elements of an argument. Based on the findings from our co-operating teachers and our own experiences, hidden circuits offer a flexible and motivating way to supplement teaching of DC circuits.
Chen, Jun; Shibata, Tadashi
2007-04-01
Pulse-coupled neural networks (PCNNs) are biologically inspired algorithms that have been shown to be highly effective for image feature generation. However, conventional PCNNs are software-oriented algorithms that are too complicated to implement as very-large-scale integration (VLSI) hardware. To employ PCNNs in image-feature-generation VLSIs, a hardware-implementation-friendly PCNN is proposed here. By introducing the concepts of exponentially decaying output and a one-branch dendritic tree, the new PCNN eliminates the large number of convolution operators and floating-point multipliers in conventional PCNNs without compromising its performance at image feature generation. As an analog VLSI implementation of the new PCNN, an image-feature-generation circuit is proposed. By employing floating-gate metal-oxide-semiconductor (MOS) technology, the circuit achieves a full voltage-mode implementation of the PCNN in a compact structure. Inheriting the merits of the PCNN, the circuit is capable of generating rotation-independent and translation-independent features for input patterns, which has been verified by SPICE simulation.
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test
Directory of Open Access Journals (Sweden)
C. Wu
2011-06-01
Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.
Intuitive analog circuit design
Thompson, Marc
2013-01-01
Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi
DEFF Research Database (Denmark)
Rasmussen, Erik Stavnsager; Tanev, Stoyan
2016-01-01
The risk of launching new products and starting new firms is known to be extremely high. The Lean Start-up approach is a way of reducing these risks and enhancing the chances for success by validating the products and services in the market with customers before launching it in full scale. The main...... point is to develop a Minimum Viable Product that can be tested by potential customers and then pivot the idea if necessary around these customer evaluations. This iterative process goes through a number of stages with the purpose of validating the customers’ problems, the suggested solution...
Induction motor starting current
Energy Technology Data Exchange (ETDEWEB)
Arneaud, J.M.; Langman, R.A. [Tasmania Univ., Hobart, TAS (Australia)
1995-12-31
Large errors may occur if leakage path saturation is neglected when reduced-voltage test results are used to predict the direct-on-line starting current of induction motors. The results of applying three existing and two new methods for starting current prediction are compared with test data from 52 motors. A quantitative assessment is made of the probable reduction in error that would be achieved by increasing the number of available sets of reduced-voltage, locked rotor test results or by including slot design data. Guidelines are given for selecting an appropriate predictive method. (author). 4 tabs., 1 fig., 6 refs.
1984-06-01
researchers, McCulloch and Pitts who studied neurological systems from a mathematical and logic stand- point) is a silicon compiler developed at the...point is given the label. Mextra does not recognize the CIF user extension w0. which is us-ed by MIT and Lincoln Labs programs (eg. mac- pitts ) to
2014-09-26
169 7404 Inverter Test ...... ................ 171 7482 Binary Adder Test .... .............. .174 REFERENCES ......... ......................... 176...tests run on a 7404 HEX INVERTER and a 7482 2-BIT BINARY FULL ADDER , are presented in Appendix E, TEST RESULTS...RAM, a 7404 HEX INVERTER, and a 7482 2-BIT FULL ADDER . These results indicate that the functional tester operates according to the specifications
Anelli, G; Delmastro, M; Faccio, F; Floria, S; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W
1999-01-01
We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs).
Directory of Open Access Journals (Sweden)
Adhiyaman P1 ,
2014-03-01
Full Text Available In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF and a novel embedded logic module (DDFF-ELM based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.
1987-12-01
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Juswardy, Budi; Xiao, Feng; Alameh, Kamal
2009-03-16
This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.
Directory of Open Access Journals (Sweden)
Md Mobarok Hossain Rubel
2016-07-01
Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.
Electrical Circuits and Water Analogies
Smith, Frederick A.; Wilson, Jerry D.
1974-01-01
Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)
2004-01-01
The first large active detector component was lowered into the ATLAS cavern on 1 March. It consisted of the 8 modules forming the lower part of the central barrel of the tile hadronic calorimeter. The work of assembling the barrel, which comprises 64 modules, started the following day.
Institute of Scientific and Technical Information of China (English)
2009-01-01
Goodwill to the Islamic world and willingness to mend ties highlight Barack Obama’s new Middle East policy u.S. President Barack Obama started to implement his new Middle East policy soon after he assumed office. He paid a
Palazzetti, Emanuele
2015-01-01
If you are an Android developer who wants to learn how to use UDOO to build Android applications that are capable of interacting with their surrounding environment, then this book is ideal for you. Learning UDOO is the next great step to start building your first real-world prototypes powered by the Android operating system.
I. Verheul (Ingrid); A.R. Thurik (Roy)
2000-01-01
textabstractFemale and male entrepreneurs differ in the way they finance their businesses. This can be attributed to the type of business and the type of management and experience (indirect effect). Female start-ups may also experience other barriers based upon discriminatory effects (direct
VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders
Directory of Open Access Journals (Sweden)
Georgios Passas
2012-01-01
Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.
Spike-based VLSI modeling of the ILD system in the echolocating bat.
Horiuchi, T; Hynna, K
2001-01-01
The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.
Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.
Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert
2004-01-01
Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.
VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.
1985-08-01
purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be
Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.
1984-10-01
analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI
VLSI Structure for an All Digital Receiver for CDMA PABX Handset
Institute of Scientific and Technical Information of China (English)
ZhouShidong; BiGuangguo
1995-01-01
In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S.
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.
Vlsi implementation of flexible architecture for decision tree classification in data mining
Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak
2017-07-01
The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.
DEFF Research Database (Denmark)
Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V
2006-01-01
We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching...... program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC0....
REA, Editors of
2012-01-01
REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph
Treu, Jr., Charles A.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.
Louwsma, S.M.; Vertregt, Maarten
2010-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converte
Louwsma, S.M.; Vertregt, Maarten
2011-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converte
DEFF Research Database (Denmark)
2009-01-01
A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...
Bergstra, J.A.; Ponse, A.
2010-01-01
Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of p
Louwsma, Simon Minze; Vertregt, Maarten
2011-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converte
Louwsma, Simon Minze; Vertregt, Maarten
2010-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converte
Time-domain analysis methodology for large-scale RLC circuits and its applications
Institute of Scientific and Technical Information of China (English)
LUO Zuying; CAI Yici; Sheldon X.-D Tan; HONG Xianlong; WANG Xiaoyi; PAN Zhu; FU Jingjing
2006-01-01
With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y to ( transformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.
Nonlinear electronic circuit with neuron like bursting and spiking dynamics.
Savino, Guillermo V; Formigli, Carlos M
2009-07-01
It is difficult to design electronic nonlinear devices capable of reproducing complex oscillations because of the lack of general constructive rules, and because of stability problems related to the dynamical robustness of the circuits. This is particularly true for current analog electronic circuits that implement mathematical models of bursting and spiking neurons. Here we describe a novel, four-dimensional and dynamically robust nonlinear analog electronic circuit that is intrinsic excitable, and that displays frequency adaptation bursting and spiking oscillations. Despite differences from the classical Hodgkin-Huxley (HH) neuron model, its bifurcation sequences and dynamical properties are preserved, validating the circuit as a neuron model. The circuit's performance is based on a nonlinear interaction of fast-slow circuit blocks that can be clearly dissected, elucidating burst's starting, sustaining and stopping mechanisms, which may also operate in real neurons. Our analog circuit unit is easily linked and may be useful in building networks that perform in real-time.
A New Soft Starting Method for Wound-Rotor Induction Motor
Sharifian, Mohammad Bagher Bannae; Feyzi, Mohammad Reza; Sabahi, Mehran; Farrokhifar, Meysam
2011-01-01
Starting of a three-phase Induction motor using a starter rheostat in rotor circuit has some disadvantages. A new method for starting of a three-phase motor by using a parallel combination of resistors, self-inductors and capacitors in rotor circuit is proposed in this paper. The proposed method ensures the soft and higher starting torque as well as limited starting current as compared to shorted rotor method. The characteristic curves for both methods (shorted rotor and rotor with added elements) are provided. The mathematical model based on the steady-state equivalent circuit of the induction motor is expanded in frequency domain and the required computer program is prepared using an optimization method. The values for added elements to rotor circuit are calculated in such a way that minimum starting time considering current and torque limitations are achieved.
Robinson, Martin
2013-01-01
his book is a fast-paced, practical guide full of step-by-step examples which are easy to follow and implement.This book is for programmers with a basic grasp of C++. The examples start at a basic level, making few assumptions beyond fundamental C++ concepts. Those without any experience with C++ should be able to follow and construct the examples, although you may need further support to understand the fundamental concepts.
Zamboni, Luca
2013-01-01
This practical and easy-to-understand learning tutorial is one big exciting exercise for students and engineers that are always short on their schedules and want to regain some lost time with the help of Simulink.This book is aimed at students and engineers who need a quick start with Simulink. Though it's not required in order to understand how Simulink works, knowledge of physics will help the reader to understand the exercises described.
Getting started with Hazelcast
Johns, Mat
2013-01-01
Written as a step-by-step guide, Getting Started with Hazelcast will teach you all you need to know to make your application data scalable.This book is a great introduction for Java developers, software architects, or developers looking to enable scalable and agile data within their applications. You should have programming knowledge of Java and a general familiarity with concepts like data caching and clustering.
Reversible Logic Circuit Synthesis
Shende, V V; Markov, I L; Prasad, A K; Hayes, John P.; Markov, Igor L.; Prasad, Aditya K.; Shende, Vivek V.
2002-01-01
Reversible, or information-lossless, circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement for quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We propose new constructions for reversible circuits composed of NOT, Controlled-NOT, and TOFFOLI gates (the CNT gate library) based on permutation theory. A new algorithm is given to synthesize optimal reversible circuits using an arbitrary gate library. We also describe much faster heuristic algorithms. We also pursue applications of the proposed techniques to the synthesis of quantum circuits.
DEFF Research Database (Denmark)
Hansen, Kristoffer Arnsfelt; Podolskii, Vladimir V.
2010-01-01
We initiate a systematic study of constant depth Boolean circuits built using exact threshold gates. We consider both unweighted and weighted exact threshold gates and introduce corresponding circuit classes. We next show that this gives a hierarchy of classes that seamlessly interleave with the ......We initiate a systematic study of constant depth Boolean circuits built using exact threshold gates. We consider both unweighted and weighted exact threshold gates and introduce corresponding circuit classes. We next show that this gives a hierarchy of classes that seamlessly interleave...... with the well-studied corresponding hierarchies defined using ordinary threshold gates. A major open problem in Boolean circuit complexity is to provide an explicit super-polynomial lower bound for depth two threshold circuits. We identify the class of depth two exact threshold circuits as a natural subclass...
Ochoa, Agustin
2016-01-01
This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...
Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene
2004-05-01
We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.
Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.
Yu, Theodore; Cauwenberghs, Gert
2010-06-01
We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.
On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
Lin, Meng-Chun; Dung, Lan-Rong
2008-02-01
This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.
Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.
Mitra, S; Fusi, S; Indiveri, G
2009-02-01
Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.
The digi-neocognitron: a digital neocognitron neural network model for VLSI.
White, B A; Elmasry, M I
1992-01-01
One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.
VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems
Energy Technology Data Exchange (ETDEWEB)
Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)
2009-07-15
The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.
Walker, Chris
2012-01-01
Start building electronics projects with Netduino, the popular open source hardware platform that's captured the imagination of makers and hobbyists worldwide. This easy-to-follow book provides the step-by-step guidance you need to experiment with Netduino and the .NET Micro Framework. Through a set of simple projects, you'll learn how to create electronic gadgets-including networked devices that communicate over TCP/IP. Along the way, hobbyists will pick up the basics of .NET programming, and programmers will discover how to work with electronics and microcontrollers. Follow the projects in
Banzi, Massimo
2011-01-01
Arduino is the open-source electronics prototyping platform that's taken the design and hobbyist world by storm. This thorough introduction, updated for Arduino 1.0, gives you lots of ideas for projects and helps you work with them right away. From getting organized to putting the final touches on your prototype, all the information you need is here! Inside, you'll learn about: Interaction design and physical computingThe Arduino hardware and software development environmentBasics of electricity and electronicsPrototyping on a solderless breadboardDrawing a schematic diagram Getting started
Long, Josh
2011-01-01
Spring Roo goes a step beyond the Spring Framework by bringing true Rapid Application Development to Java-just as Grails has done with Groovy. This concise introduction shows you how to build applications with Roo, using the framework's shell as an intelligent and timesaving code-completion tool. It's an ideal RAD tool because Roo does much of the tedious code maintenance. You'll get started by building a simple customer relationship management application, complete with step-by-step instructions and code examples. Learn how to control any part of the application with Roo's opt-in feature, w
DEFF Research Database (Denmark)
Sievertsen, Hans Henrik
I Danmark er det muligt at afvige fra reglen om, at barnet skal starte i skole det kalenderår, hvor barnet fylder 6 år. Det gør 10-15 procent af en årgang, mens 80-90 procent af børnene følger normen, og 2-3 procent starter i skole et år tidligere end normen, viser en analyse baseret på børn født i...
Getting Started with Processing
Reas, Casey
2010-01-01
Learn computer programming the easy way with Processing, a simple language that lets you use code to create drawings, animation, and interactive graphics. Programming courses usually start with theory, but this book lets you jump right into creative and fun projects. It's ideal for anyone who wants to learn basic programming, and serves as a simple introduction to graphics for people with some programming skills. Written by the founders of Processing, this book takes you through the learning process one step at a time to help you grasp core programming concepts. You'll learn how to sketch wi
用于混合信号VLSI的可扩展JTAG控制器IP核设计%Design of Extendable JTAG Controller IP Core for Mixed-signal VLSI
Institute of Scientific and Technical Information of China (English)
段延亮; 魏廷存; 高武; 许望洋
2012-01-01
The front-end read-out circuit for Positron Emission Tomography（PET） imaging system is a kind of digital-analog mixed-signal VLSI.Based on the features of multi-channel and high performances of these kinds of chip,the JTAG controller is adopted to realize the initial control and auxiliary test of the chip.An extendable JTAG controller IP core is designed using TSMC 0.18 μm CMOS process,which supports 14 groups of extendable control signal and also supports the reading and writing operations of 16 multi-bits registers scan chains,and joins with the customized substrate driving software.The designed JTAG controller IP core can be also used for the controlling and testing of other mixed-signal VLSI,and has good universality and engineering usage.%正电子发射断层成像系统（PET）前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值.
Directory of Open Access Journals (Sweden)
Danielle S Bassett
2010-04-01
Full Text Available Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.
Simplified design of micropower and battery circuits
Lenk, John
1995-01-01
'Simplified Design of Micropower and Battery Circuits' provides a simplified, step-by-step approach to micropower and supply cell circuit design. No previous experience in design is required to use the techniques described, thus making the book well suited for the beginner, student, or experimenter as well as the design professional.The book concentrates on the use of commercial micropower ICs by discussing selections of external components that modify the IC-package characteristics. The basic approach is to start design problems with approximations for trial-value components in expe
Regenerative feedback resonant circuit
Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.
2014-09-02
A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.
Dobkin, Bob
2012-01-01
Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <
Parallelizing quantum circuit synthesis
Di Matteo, Olivia; Mosca, Michele
2016-01-01
Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools which can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in t...
Hickman, Ian
2013-01-01
Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.
Missouri: Early Head Start Initiative
Center for Law and Social Policy, Inc. (CLASP), 2012
2012-01-01
Missouri's Early Head Start/Child Care Partnership Project expands access to Early Head Start (EHS) services for children birth to age 3 by developing partnerships between federal Head Start, EHS contractors, and child care providers. Head Start and EHS contractors that participate in the initiative provide services through community child care…
Electronic devices and circuits
Pridham, Gordon John
1968-01-01
Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th
Marston, R M
1995-01-01
CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu
Security electronics circuits manual
MARSTON, R M
1998-01-01
Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty
Wolfendale, E
2013-01-01
MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi
Printed circuit board industry.
LaDou, Joseph
2006-05-01
The printed circuit board is the platform upon which microelectronic components such as semiconductor chips and capacitors are mounted. It provides the electrical interconnections between components and is found in virtually all electronics products. Once considered low technology, the printed circuit board is evolving into a high-technology product. Printed circuit board manufacturing is highly complicated, requiring large equipment investments and over 50 process steps. Many of the high-speed, miniaturized printed circuit boards are now manufactured in cleanrooms with the same health and safety problems posed by other microelectronics manufacturing. Asia produces three-fourths of the world's printed circuit boards. In Asian countries, glycol ethers are the major solvents used in the printed circuit board industry. Large quantities of hazardous chemicals such as formaldehyde, dimethylformamide, and lead are used by the printed circuit board industry. For decades, chemically intensive and often sloppy manufacturing processes exposed tens of thousands of workers to a large number of chemicals that are now known to be reproductive toxicants and carcinogens. The printed circuit board industry has exposed workers to high doses of toxic metals, solvents, acids, and photolithographic chemicals. Only recently has there been any serious effort to diminish the quantity of lead distributed worldwide by the printed circuit board industry. Billions of electronics products have been discarded in every region of the world. This paper summarizes recent regulatory and enforcement efforts.
Multi-qubit circuit quantum electrodynamics
Energy Technology Data Exchange (ETDEWEB)
Viehmann, Oliver
2013-09-03
Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a
Directory of Open Access Journals (Sweden)
Zhiming Yang
2016-01-01
Full Text Available The reliability of Very Large Scale Integration (VLSI circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology. Some commonly used fault tolerance strategies require statistical methods to accurately estimate the fault rate in different parts of the logic circuit, and Monte Carlo (MC simulation is often applied to complete this task. However, the MC method suffers from impractical computation costs due to the size of the circuits. Furthermore, circuit aging effects, such as negative bias temperature instability (NBTI, will change the characteristics of the circuit during its lifetime, leading to a change in the circuit’s noise margin. This change will increase the complexity of transient fault rate estimation tasks. In this paper, an NBTI-aware statistical analysis method based on probability voltage transfer characteristics is proposed for combinational logic circuit. This method can acquire accurate fault rates using a discrete probability density function approximation process, thus resolving the computation cost problem of the MC method. The proposed method can also consider aging effects and analyze statistical changes in the fault rates. Experimental results demonstrate that, compared to the MC simulation, our method can achieve computation times that are two orders of magnitude shorter while maintaining an error rate less than 9%.
2011-01-01
This has been an excellent week for the LHC, with a succession of fills rapidly increasing the number of proton bunches to 194 per beam. This has allowed the experiments to reach a peak luminosity of 2.5 × 1032 cm-2s-1, thereby surpassing the record for 2010 where we reached 2.0 × 1032 cm-2s-1. At the time of writing, the integrated luminosity delivered by the LHC in 2011 is around 28 inverse picobarns, which is already more than half of the total 2010 dataset. These are impressive numbers, but what impresses me most is how quickly the LHC operators are now able to turn the machine around between fills, and how well LHC running has been incorporated into the overall operation of CERN’s accelerator complex. The flexibility of the LHC was illustrated on Thursday when we started a short phase of running at 1.38 TeV per beam, equivalent to the energy-per-nucleon of a lead-ion run. This lower energy data will be used by the experiments, in particular by ALICE, to compare...
Starting physiology: bioelectrogenesis.
Baptista, Vander
2015-12-01
From a Cartesian perspective of rational analysis, the electric potential difference across the cell membrane is one of the fundamental concepts for the study of physiology. Unfortunately, undergraduate students often struggle to understand the genesis of this energy gradient, which makes the teaching activity a hard task for the instructor. The topic of bioelectrogenesis encompasses multidisciplinary concepts, involves several mechanisms, and is a dynamic process, i.e., it never turns off during the lifetime of the cell. Therefore, to improve the transmission and acquisition of knowledge in this field, I present an alternative didactic model. The design of the model assumes that it is possible to build, in a series of sequential steps, an assembly of proteins within the membrane of an isolated cell in a simulated electrophysiology experiment. Initially, no proteins are inserted in the membrane and the cell is at a baseline energy state; the extracellular and intracellular fluids are at thermodynamic equilibrium. Students are guided through a sequence of four steps that add key membrane transport proteins to the model cell. The model is simple at the start and becomes progressively more complex, finally producing transmembrane chemical and electrical gradients. I believe that this didactic approach helps instructors with a more efficient tool for the teaching of the mechanisms of resting membrane potential while helping students avoid common difficulties that may be encountered when learning this topic.
Della Mussia, S
2004-01-01
The first large active detector component was lowered into the ATLAS cavern on 1st March. It consisted of the 8 modules forming the lower part of the central barrel of the tile hadronic calorimeter. The work of assembling the barrel, which comprises 64 modules, started the following day. Two road trailers each with 64 wheels, positioned side by side. This was the solution chosen to transport the lower part of the central barrel of ATLAS' tile hadronic calorimeter from Building 185 to the PX16 shaft at Point 1 (see Figure 1). The transportation, and then the installation of the component in the experimental cavern, which took place over three days were, to say the least, rather spectacular. On 25 February, the component, consisting of eight 6-metre modules, was loaded on to the trailers. The segment of the barrel was transported on a steel support so that it wouldn't move an inch during the journey. On 26 February, once all the necessary safety checks had been carried out, the convoy was able to leave Buildi...
2000-01-01
Since the end of November, various teams have been getting stuck into dismantling the LEP accelerator and its four experiments. After making the installations safe, the dismantling and removal of 40,000 tonnes of equipment is underway. Down in the tunnel, it is a solemn moment. It is 10 o'clock on 13 December and Daniel Regin, one of those heading the dismantling work, moves in on a magnet, armed with a hydraulic machine. Surrounded by teams gathered there for a course in dismantling, he makes the first cut into LEP. The great deconstruction has begun. In little over than a year, the accelerator will have been cleared away to make room for its successor, the LHC. The start of the operation goes back to 27 November. Because before setting about the machine with hydraulic shears and monkey wrenches, LEP had first to be made safe - it was important to make sure the machine could be taken apart without risk. All the SPS beam injection systems to LEP were cut off. The fluids used for cooling the magnets and superc...
A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
Yang, Yuning; Kamboh, Awais M; Mason, Andrew J
2014-04-30
This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.
Hoang, Linh; Yang, Zhi; Liu, Wentai
2009-01-01
An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.
A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.
Mill, R; Sheik, S; Indiveri, G; Denham, S L
2011-10-01
Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.
VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.
Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V
2007-03-01
A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.
Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.
2002-04-01
A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit
2016-09-01
The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
P.A.HarshaVardhini
2012-04-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
M.Madhavi Latha
2012-05-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
Real-time motion detection using an analog VLSI zero-crossing chip
Bair, Wyeth; Koch, Christof
1991-07-01
The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.
A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT
Liu, Kai; Li, YunSong; Belyaev, Eugeniy
2010-08-01
The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA
Directory of Open Access Journals (Sweden)
Nishi Pandey
2015-10-01
Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family
Analyzing VLSI component test results of a GenRad GR125 tester
Zulaica, D.; Lee, C.-H.
1995-06-01
The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard
Institute of Scientific and Technical Information of China (English)
Li Zhang; Don Xie; Di Wu
2006-01-01
The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.
An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips
Deutsch, L. J.
1985-01-01
A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.
Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)
1991-01-01
Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.
Synchronizing Hyperchaotic Circuits
DEFF Research Database (Denmark)
Tamasevicius, Arunas; Cenys, Antanas; Namajunas, Audrius
1997-01-01
Regarding possible applications to secure communications the technique of synchronizing hyperchaotic circuits with a single dynamical variable is discussed. Several specific examples including the fourth-order circuits with two positive Lyapunov exponents as well as the oscillator with a delay line...... characterized by multiple positive Lyapunov exponents are reviewd....
Genetic circuit design automation.
Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A
2016-04-01
Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization.
Vick, Matthew E.
2010-01-01
The University of Colorado's Physics Education Technology (PhET) website offers free, high-quality simulations of many physics experiments that can be used in the classroom. The Circuit Construction Kit, for example, allows students to safely and constructively play with circuit components while learning the mathematics behind many circuit…
VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.
Suriyasena Liyanage, Luckshitha; Xu, Xiaoqing; Pitner, Greg; Bao, Zhenan; Wong, H-S Philip
2014-01-01
Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.
Directory of Open Access Journals (Sweden)
Rozita Teymourzadeh
2010-01-01
Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.
Getting started with electronic projects
Pretty, Bill
2015-01-01
This book is aimed at hobbyists with basic knowledge of electronics circuits. Whether you are a novice electronics project builder, a ham radio enthusiast, or a BeagleBone tinkerer, you will love this book.
Approximate circuits for increased reliability
Energy Technology Data Exchange (ETDEWEB)
Hamlet, Jason R.; Mayo, Jackson R.
2015-08-18
Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.
Approximate circuits for increased reliability
Energy Technology Data Exchange (ETDEWEB)
Hamlet, Jason R.; Mayo, Jackson R.
2015-12-22
Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.
Shen, Mingya; Xiao, Feng; Alameh, Kamal
2009-12-07
A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.
High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug
2006-07-24
Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.
Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak
2008-08-04
A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.