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Sample records for vlsi circuit techniques

  1. A multi coding technique to reduce transition activity in VLSI circuits

    International Nuclear Information System (INIS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-01-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

  2. The test of VLSI circuits

    Science.gov (United States)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  3. A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

    Directory of Open Access Journals (Sweden)

    Trong-Tu Bui

    2013-01-01

    Full Text Available We present a compact and low-power rank-order searching (ROS circuit that can be used for building associative memories and rank-order filters (ROFs by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

  4. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  5. Electro-optic techniques for VLSI interconnect

    Science.gov (United States)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  6. Applications of VLSI circuits to medical imaging

    International Nuclear Information System (INIS)

    O'Donnell, M.

    1988-01-01

    In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

  7. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  8. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  9. PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    T. Tharaneeswaran

    2012-06-01

    Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

  10. Custom VLSI circuits for high energy physics

    International Nuclear Information System (INIS)

    Parker, S.

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner's guide through the maze, and that is the main purpose of this text

  11. Custom VLSI circuits for high energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  12. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  13. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  14. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  15. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  16. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

    2011-01-01

    -designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

  17. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  18. Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

    International Nuclear Information System (INIS)

    Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

    1992-01-01

    Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

  19. New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

    Energy Technology Data Exchange (ETDEWEB)

    Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

    1983-07-01

    This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

  20. CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

    International Nuclear Information System (INIS)

    Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

    1996-01-01

    In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

  1. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

    Science.gov (United States)

    Breuer, M. A.; Carlan, A. J.

    1982-10-01

    Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

  2. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  3. Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

    Energy Technology Data Exchange (ETDEWEB)

    Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

    1992-01-01

    The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

  4. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    International Nuclear Information System (INIS)

    Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

    1993-01-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

  5. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  6. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  7. An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

    Science.gov (United States)

    Corliss, Walter F., II

    1989-03-01

    The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

  8. Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Michael S. Hsiao

    2002-01-01

    Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

  9. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  10. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

  11. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  12. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  13. Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics.

    Science.gov (United States)

    1987-09-01

    level descrip- tion without human intervention. Although design rules and the layout function may not be checked, performance verification is still a...digital syvstems.- Proc. I1E1., vol. 69. no. 10. pp. 1200-1211. October 198 1. [2] A. Gupta, AT A circuit extractor." Proc. 20th Design Automiation

  14. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    International Nuclear Information System (INIS)

    Beccherle, R.; Cisternino, A.; Guerra, A. Del; Folli, M.; Marchesini, R.; Bisogni, M.G.; Ceccopieri, A.; Rosso, V.; Stefanini, A.; Tripiccione, R.; Kipnis, I.

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 μm CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution

  15. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  16. Parallel computation of nondeterministic algorithms in VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Hortensius, P D

    1987-01-01

    This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

  17. Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

    1985-01-01

    The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  18. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  19. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  20. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    National Research Council Canada - National Science Library

    Horiuchi, Timothy K; Krishnaprasad, P. S

    2007-01-01

    .... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

  1. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  2. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  3. Fast-prototyping of VLSI

    International Nuclear Information System (INIS)

    Saucier, G.; Read, E.

    1987-01-01

    Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

  4. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  5. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  6. An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

    Science.gov (United States)

    Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

    This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

  7. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  8. Lithography requirements in complex VLSI device fabrication

    International Nuclear Information System (INIS)

    Wilson, A.D.

    1985-01-01

    Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

  9. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  10. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  11. Heavy ion tests on programmable VLSI

    International Nuclear Information System (INIS)

    Provost-Grellier, A.

    1989-11-01

    The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

  12. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  13. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  14. Circuit design techniques for non-crystalline semiconductors

    CERN Document Server

    Sambandan, Sanjiv

    2012-01-01

    Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

  15. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  16. Linear circuit transfer functions an introduction to fast analytical techniques

    CERN Document Server

    Basso, Christophe P

    2016-01-01

    Linear Circuit Transfer Functions: An introduction to Fast Analytical Techniques teaches readers how to determine transfer functions of linear passive and active circuits by applying Fast Analytical Circuits Techniques. Building on their existing knowledge of classical loop/nodal analysis, the book improves and expands their skills to unveil transfer functions in a swift and efficient manner. Starting with simple examples, the author explains step-by-step how expressing circuits time constants in different configurations leads to writing transfer functions in a compact and insightful way. By learning how to organize numerators and denominators in the fastest possible way, readers will speed-up analysis and predict the frequency resp nse of simple to complex circuits. In some cases, they will be able to derive the final expression by inspection, without writing a line of algebra. Key features: * Emphasizes analysis through employing time constant-based methods discussed in other text books but not widely us...

  17. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  18. Multiband RF circuits and techniques for wireless transmitters

    CERN Document Server

    Chen, Wenhua; Ghannouchi, Fadhel M

    2016-01-01

    This book introduces systematic design methods for passive and active RF circuits and techniques, including state-of-the-art digital enhancement techniques. As the very first book dedicated to multiband RF circuits and techniques, this work provides an overview of the evolution of transmitter architecture and discusses current digital predistortion techniques. Readers will find a collection of novel research ideas and new architectures in concurrent multiband power dividers, power amplifiers and related digital enhancement techniques. This book will be of great interest to academic researchers, R&D engineers, wireless transmitter and protocol designers, as well as graduate students who wish to learn the core architectures, principles and methods of multiband RF circuits and techniques. .

  19. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  20. The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

    OpenAIRE

    Artem Ganiyev; Jan Vitasek

    2010-01-01

    This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

  1. Multi-valued LSI/VLSI logic design

    Science.gov (United States)

    Santrakul, K.

    A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

  2. Novel technique for reliability testing of silicon integrated circuits

    NARCIS (Netherlands)

    Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

    2001-01-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

  3. Circuit oriented electromagnetic modeling using the PEEC techniques

    CERN Document Server

    Ruehli, Albert; Jiang, Lijun

    2017-01-01

    This book provides intuitive solutions to electromagnetic problems by using the Partial Eelement Eequivalent Ccircuit (PEEC) method. This book begins with an introduction to circuit analysis techniques, laws, and frequency and time domain analyses. The authors also treat Maxwell's equations, capacitance computations, and inductance computations through the lens of the PEEC method. Next, readers learn to build PEEC models in various forms: equivalent circuit models, non orthogonal PEEC models, skin-effect models, PEEC models for dielectrics, incident and radiate field models, and scattering PEEC models. The book concludes by considering issues like such as stability and passivity, and includes five appendices some with formulas for partial elements.

  4. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  5. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  6. Parallel VLSI Architecture

    Science.gov (United States)

    Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

    1985-01-01

    Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

  7. Digital circuit testing a guide to DFT and other techniques

    CERN Document Server

    Wong, Francis C

    1991-01-01

    Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to

  8. Numerical analysis of electromigration in thin film VLSI interconnections

    NARCIS (Netherlands)

    Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

    1995-01-01

    Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

  9. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  10. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  11. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  12. Built-in self-repair of VLSI memories employing neural nets

    Science.gov (United States)

    Mazumder, Pinaki

    1998-10-01

    The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

  13. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  14. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  15. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  16. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    National Research Council Canada - National Science Library

    Altmeyer, Ronald

    2002-01-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

  17. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-01-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  18. Waste printed circuit board recycling techniques and product utilization

    International Nuclear Information System (INIS)

    Hadi, Pejman; Xu, Meng; Lin, Carol S.K.; Hui, Chi-Wai; McKay, Gordon

    2015-01-01

    Highlights: • There is a major environmental issue about the printed circuit boards throughout the world. • Different physical and chemical recycling techniques have been reviewed. • Nonmetallic fraction of PCBs is the unwanted face of this waste stream. • Several applications of the nonmetallic fraction of waste PCBs have been introduced. - Abstract: E-waste, in particular waste PCBs, represents a rapidly growing disposal problem worldwide. The vast diversity of highly toxic materials for landfill disposal and the potential of heavy metal vapors and brominated dioxin emissions in the case of incineration render these two waste management technologies inappropriate. Also, the shipment of these toxic wastes to certain areas of the world for eco-unfriendly “recycling” has recently generated a major public outcry. Consequently, waste PCB recycling should be adopted by the environmental communities as an ultimate goal. This article reviews the recent trends and developments in PCB waste recycling techniques, including both physical and chemical recycling. It is concluded that the physical recycling techniques, which efficiently separate the metallic and nonmetallic fractions of waste PCBs, offer the most promising gateways for the environmentally-benign recycling of this waste. Moreover, although the reclaimed metallic fraction has gained more attention due to its high value, the application of the nonmetallic fraction has been neglected in most cases. Hence, several proposed applications of this fraction have been comprehensively examined

  19. Waste printed circuit board recycling techniques and product utilization

    Energy Technology Data Exchange (ETDEWEB)

    Hadi, Pejman; Xu, Meng [Chemical and Biomolecular Engineering Department, Hong Kong University of Science and Technology, Clear Water Bay Road, Hong Kong Special Administrative Region (Hong Kong); Lin, Carol S.K. [School of Energy and Environment, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong Special Administrative Region (Hong Kong); Hui, Chi-Wai [Chemical and Biomolecular Engineering Department, Hong Kong University of Science and Technology, Clear Water Bay Road, Hong Kong Special Administrative Region (Hong Kong); McKay, Gordon, E-mail: kemckayg@ust.hk [Chemical and Biomolecular Engineering Department, Hong Kong University of Science and Technology, Clear Water Bay Road, Hong Kong Special Administrative Region (Hong Kong); Division of Sustainable Development, College of Science, Engineering and Technology, Hamad Bin Khalifa University, Qatar Foundation, Doha (Qatar)

    2015-02-11

    Highlights: • There is a major environmental issue about the printed circuit boards throughout the world. • Different physical and chemical recycling techniques have been reviewed. • Nonmetallic fraction of PCBs is the unwanted face of this waste stream. • Several applications of the nonmetallic fraction of waste PCBs have been introduced. - Abstract: E-waste, in particular waste PCBs, represents a rapidly growing disposal problem worldwide. The vast diversity of highly toxic materials for landfill disposal and the potential of heavy metal vapors and brominated dioxin emissions in the case of incineration render these two waste management technologies inappropriate. Also, the shipment of these toxic wastes to certain areas of the world for eco-unfriendly “recycling” has recently generated a major public outcry. Consequently, waste PCB recycling should be adopted by the environmental communities as an ultimate goal. This article reviews the recent trends and developments in PCB waste recycling techniques, including both physical and chemical recycling. It is concluded that the physical recycling techniques, which efficiently separate the metallic and nonmetallic fractions of waste PCBs, offer the most promising gateways for the environmentally-benign recycling of this waste. Moreover, although the reclaimed metallic fraction has gained more attention due to its high value, the application of the nonmetallic fraction has been neglected in most cases. Hence, several proposed applications of this fraction have been comprehensively examined.

  20. Switched-capacitor techniques for high-accuracy filter and ADC design

    NARCIS (Netherlands)

    Quinn, P.J.; Roermund, van A.H.M.

    2007-01-01

    Switched capacitor (SC) techniques are well proven to be excellent candidates for implementing critical analogue functions with high accuracy, surpassing other analogue techniques when embedded in mixed-signal CMOS VLSI. Conventional SC circuits are primarily limited in accuracy by a) capacitor

  1. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  2. Nano lasers in photonic VLSI

    NARCIS (Netherlands)

    Hill, M.T.; Oei, Y.S.; Smit, M.K.

    2007-01-01

    We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

  3. Advances in Current Rating Techniques for Flexible Printed Circuits

    Science.gov (United States)

    Hayes, Ron

    2014-01-01

    Twist Capsule Assemblies are power transfer devices commonly used in spacecraft mechanisms that require electrical signals to be passed across a rotating interface. Flexible printed circuits (flex tapes, see Figure 2) are used to carry the electrical signals in these devices. Determining the current rating for a given trace (conductor) size can be challenging. Because of the thermal conditions present in this environment the most appropriate approach is to assume that the only means by which heat is removed from the trace is thru the conductor itself, so that when the flex tape is long the temperature rise in the trace can be extreme. While this technique represents a worst-case thermal situation that yields conservative current ratings, this conservatism may lead to overly cautious designs when not all traces are used at their full rated capacity. A better understanding of how individual traces behave when they are not all in use is the goal of this research. In the testing done in support of this paper, a representative flex tape used for a flight Solar Array Drive Assembly (SADA) application was tested by energizing individual traces (conductors in the tape) in a vacuum chamber and the temperatures of the tape measured using both fine-gauge thermocouples and infrared thermographic imaging. We find that traditional derating schemes used for bundles of wires do not apply for the configuration tested. We also determine that single active traces located in the center of a flex tape operate at lower temperatures than those on the outside edges.

  4. A microelectromechanical accelerometer fabricated using printed circuit processing techniques

    Science.gov (United States)

    Rogers, J. E.; Ramadoss, R.; Ozmun, P. M.; Dean, R. N.

    2008-01-01

    A microelectromechanical systems (MEMS) capacitive-type accelerometer fabricated using printed circuit processing techniques is presented. A Kapton polymide film is used as the structural layer for fabricating the MEMS accelerometer. The accelerometer proof mass along with four suspension beams is defined in the Kapton polyimide film. The proof mass is suspended above a Teflon substrate using a spacer. The deflection of the proof mass is detected using a pair of capacitive sensing electrodes. The top electrode of the accelerometer is defined on the top surface of the Kapton film. The bottom electrode is defined in the metallization on the Teflon substrate. The initial gap height is determined by the distance between the bottom electrode and the Kapton film. For an applied external acceleration (normal to the proof mass), the proof mass deflects toward or away from the fixed bottom electrode due to inertial force. This deflection causes either a decrease or increase in the air-gap height thereby either increasing or decreasing the capacitance between the top and the bottom electrodes. An example PCB MEMS accelerometer with a square proof mass of membrane area 6.4 mm × 6.4 mm is reported. The measured resonant frequency is 375 Hz and the Q-factor in air is 0.52.

  5. A microelectromechanical accelerometer fabricated using printed circuit processing techniques

    International Nuclear Information System (INIS)

    Rogers, J E; Ramadoss, R; Ozmun, P M; Dean, R N

    2008-01-01

    A microelectromechanical systems (MEMS) capacitive-type accelerometer fabricated using printed circuit processing techniques is presented. A Kapton polymide film is used as the structural layer for fabricating the MEMS accelerometer. The accelerometer proof mass along with four suspension beams is defined in the Kapton polyimide film. The proof mass is suspended above a Teflon substrate using a spacer. The deflection of the proof mass is detected using a pair of capacitive sensing electrodes. The top electrode of the accelerometer is defined on the top surface of the Kapton film. The bottom electrode is defined in the metallization on the Teflon substrate. The initial gap height is determined by the distance between the bottom electrode and the Kapton film. For an applied external acceleration (normal to the proof mass), the proof mass deflects toward or away from the fixed bottom electrode due to inertial force. This deflection causes either a decrease or increase in the air-gap height thereby either increasing or decreasing the capacitance between the top and the bottom electrodes. An example PCB MEMS accelerometer with a square proof mass of membrane area 6.4 mm × 6.4 mm is reported. The measured resonant frequency is 375 Hz and the Q-factor in air is 0.52

  6. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  7. Microwave integrated circuit mask design, using computer aided microfilm techniques

    Energy Technology Data Exchange (ETDEWEB)

    Reymond, J.M.; Batliwala, E.R.; Ajose, S.O.

    1977-01-01

    This paper examines the possibility of using a computer interfaced with a precision film C.R.T. information retrieval system, to produce photomasks suitable for the production of microwave integrated circuits.

  8. Synthesis algorithm of VLSI multipliers for ASIC

    Science.gov (United States)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  9. DPL/Daedalus design environment (for VLSI)

    Energy Technology Data Exchange (ETDEWEB)

    Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

    1981-01-01

    The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

  10. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  11. Thin film circuits for future applications. Pt. 2. Evaporation technique

    Energy Technology Data Exchange (ETDEWEB)

    Haug, G; Houska, K H; Schmidt, H J; Sprengel, H P; Wohak, K

    1976-06-01

    Investigations of thin film diffusion processes and reactions with encapsulation materials resulted in improved long term stability of evaporated NiCr resistors, SiO capacitors and NiCr/Au conductors for thin film circuits. Stable NiCr resistor networks can be formed on ceramic substrates, and SiO capacitors of good quality can be deposited on the new very smooth ceramic substrates. The knowledge of the influence of evaporation parameters make the production of SiO capacitors with definite properties and good reproducibility possible. The range of capacitance of tantalum thin film circuits can be extended by integration with evaporated SiO capacitors.

  12. Technique for selection of transient radiation-hard junction-isolated integrated circuits

    International Nuclear Information System (INIS)

    Crowley, J.L.; Junga, F.A.; Stultz, T.J.

    1976-01-01

    A technique is presented which demonstrates the feasibility of selecting junction-isolated integrated circuits (JI/ICS) for use in transient radiation environments. The procedure guarantees that all PNPN paths within the integrated circuit are identified and describes the methods used to determine whether the paths represent latchup susceptible structures. Two examples of the latchup analysis are given involving an SSI and an LSI bipolar junction-isolated integrated circuit

  13. A study of radiation hardness screening techniques of integrated circuits

    International Nuclear Information System (INIS)

    Wang Xuli

    2002-01-01

    The principle and operational procedure of Integrated Circuits (ICs) screening with irradiation-and-anneal and multicomponent regression analysis are discussed. The key technology, advantages and shortcomings of the two methods are described in contrast, and some advices are given with the state-of-the-art of the screening technology

  14. E-Learning System Using Segmentation-Based MR Technique for Learning Circuit Construction

    Science.gov (United States)

    Takemura, Atsushi

    2016-01-01

    This paper proposes a novel e-Learning system using the mixed reality (MR) technique for technical experiments involving the construction of electronic circuits. The proposed system comprises experimenters' mobile computers and a remote analysis system. When constructing circuits, each learner uses a mobile computer to transmit image data from the…

  15. Emerging Applications for High K Materials in VLSI Technology

    Science.gov (United States)

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  16. Emerging Applications for High K Materials in VLSI Technology

    Directory of Open Access Journals (Sweden)

    Robert D. Clark

    2014-04-01

    Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

  17. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  18. VLSI Architecture and Design

    OpenAIRE

    Johnsson, Lennart

    1980-01-01

    Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible....

  19. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Science.gov (United States)

    McEwan, Alistair; van Schaik, André

    2003-12-01

    The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  20. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Directory of Open Access Journals (Sweden)

    Alistair McEwan

    2003-06-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  1. Simulation of worst-case operating conditions for integrated circuits operating in a total dose environment

    International Nuclear Information System (INIS)

    Bhuva, B.L.

    1987-01-01

    Degradations in the circuit performance created by the radiation exposure of integrated circuits are so unique and abnormal that thorough simulation and testing of VLSI circuits is almost impossible, and new ways to estimate the operating performance in a radiation environment must be developed. The principal goal of this work was the development of simulation techniques for radiation effects on semiconductor devices. The mixed-mode simulation approach proved to be the most promising. The switch-level approach is used to identify the failure mechanisms and critical subcircuits responsible for operational failure along with worst-case operating conditions during and after irradiation. For precise simulations of critical subcircuits, SPICE is used. The identification of failure mechanisms enables the circuit designer to improve the circuit's performance and failure-exposure level. Identification of worst-case operating conditions during and after irradiation reduces the complexity of testing VLSI circuits for radiation environments. The results of test circuits for failure simulations using a conventional simulator and the new simulator showed significant time savings using the new simulator. The savings in simulation time proved to be circuit topology-dependent. However, for large circuits, the simulation time proved to be orders of magnitude smaller than simulation time for conventional simulators

  2. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  3. Manipulator techniques and problems of their application in primary circuit maintenance

    International Nuclear Information System (INIS)

    Kertscher, F.; Popp, P.

    1985-01-01

    The fundamental structure and specifications of manipulators (in particular of industrial robots) are presented in order to derive the application conditions and fields for manipulators in primary circuit maintenance. The necessity of applying process-specific manipulator technique in the primary circuit maintenance is based on nuclear safety requirements and on decreasing of the radiation exposure of maintenance personnel. Synchronous manipulators and industrial robots are the types of manipulators used in materials testing, repairing and scrapping. The technical requirements of manipulators are discussed

  4. A technique for autologous priming of the veno-venous bypass circuit during liver transplantation.

    Science.gov (United States)

    Shackelford, Anthony G; Hodge, Ashley B; Chavin, Kenneth D; Baliga, Prabhakar K

    2011-06-01

    Orthotopic liver transplantations (OLT) have been associated with significant blood loss and hemodilution, necessitating significant homologous blood component replacement. Increasing administration of homologous blood products has been found to be inversely related to patient and graft survival. Various methods to reduce the amount of blood products patients receive during OLT, such as antifibrinolytic therapy, thromboelastography-guided transfusion, phlebotomy, reduced central venous pressures intraoperatively, and the use of the veno-venous bypass (VVB) circuit, have been explored.The asanguineous priming volume of the VVB circuit increases the likelihood of the patient receiving homologous blood products due to hemodilution. It was reasoned that autologous priming of the VVB circuit in OLT surgery was a plausible adjunctive blood conservation technique given its application to the extracorporeal circuit during cardiac surgery. We describe our technique of modifying the VVB circuit for autologous priming. This technique adds minimal risk and a small amount of cost to the procedure, requires slightly more communication among members of the surgical team, and with proper sequencing, adds no additional length to the surgical procedure. It is recommended that this technique be considered for addition to the arsenal of blood conservation techniques when VVB is used during OLT.

  5. Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

    NARCIS (Netherlands)

    Nauta, Bram; Annema, Anne J.

    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply

  6. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  7. A second generation 50 Mbps VLSI level zero processing system prototype

    Science.gov (United States)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  8. Adaptative Techniques to Reduce Power in Digital Circuits

    Directory of Open Access Journals (Sweden)

    Bharadwaj Amrutur

    2011-07-01

    Full Text Available CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS, Dynamic Voltage and Frequency Scaling (DVS and DVFS and Adaptive Voltage Scaling (AVS. Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing.

  9. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  10. VLSI structures for track finding

    International Nuclear Information System (INIS)

    Dell'Orso, M.

    1989-01-01

    We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

  11. 10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

    Science.gov (United States)

    Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

    1985-02-01

    An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

  12. Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

    Science.gov (United States)

    Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

    2017-12-01

    Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

  13. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  14. Study of Photosensitive Dry Films Absorption for Printed Circuit Boards by Photoacoustic Technique

    Science.gov (United States)

    Hernández, R.; Zaragoza, J. A. Barrientos; Jiménez-Pérez, J. L.; Orea, A. Cruz; Correa-Pacheco, Z. N.

    2017-08-01

    In this work, the study of photosensitive dry-type films by photoacoustic technique is proposed. The dry film photoresist is resistant to chemical etching for printed circuit boards such as ferric chloride, sodium persulfate or ammonium, hydrochloric acid. It is capable of faithfully reproducing circuit pattern exposed to ultraviolet light (UV) through a negative. Once recorded, the uncured portion is removed with alkaline solution. It is possible to obtain good results in surface mount circuits with tracks of 5 mm. Furthermore, the solid resin films are formed by three layers, two protective layers and a UV-sensitive optical absorption layer in the range of 325 nm to 405 nm. By means of optical absorption of UV-visible rays emitted by a low-power Xe lamp, the films transform this energy into thermal waves generated by the absorption of optical radiation and subsequently no-radiative de-excitation occurs. The photoacoustic spectroscopy is a useful technique to measure the transmittance and absorption directly. In this study, the optical absorption spectra of the three layers of photosensitive dry-type films were obtained as a function of the wavelength, in order to have a knowledge of the absorber layer and the protective layers. These analyses will give us the physical properties of the photosensitive film, which are very important in curing the dry film for applications in printed circuit boards.

  15. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

    Science.gov (United States)

    Sharma, Vijay Kumar; Pattanaik, Manisha

    2015-11-01

    Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

  16. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  17. Optimization long hole blast fragmentation techniques and detonating circuit underground uranium mine stope

    International Nuclear Information System (INIS)

    Li Qin; Yang Lizhi; Song Lixia; Qin De'en; Xue Yongshe; Wang Zhipeng

    2012-01-01

    Aim at high rate of large blast fragmentation, a big difficulty in long hole drilling and blasting underground uranium mine stope, it is pointed out at the same time of taking integrated technical management measures, the key is to optimize the drilling and blasting parameters and insure safety the act of one that primes, adopt 'minimum burden' blasting technique, renew the stope fragmentation process, and use new process of hole bottom indirect initiation fragmentation; optimize the detonating circuit and use safe, reliable and economically rational duplex non-electric detonating circuit. The production practice shows that under the guarantee of strictly controlled construction quality, the application of optimized blast fragmentation technique has enhanced the reliability of safety detonation and preferably solved the problem of high rate of large blast fragments. (authors)

  18. Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

    Directory of Open Access Journals (Sweden)

    Garcia-Leyva Lancelot

    2016-01-01

    In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other robust technique approaches. The methodology is totally different from the Von Neumann approaches, because element are not replicated N times, but instead, they check the coherence of redundant input data no allowing data propagation in case of discrepancy. This mechanism does not require voting devices.

  19. Application of source biasing technique for energy efficient DECODER circuit design: memory array application

    Science.gov (United States)

    Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

    2018-04-01

    Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

  20. An analog VLSI real time optical character recognition system based on a neural architecture

    International Nuclear Information System (INIS)

    Bo, G.; Caviglia, D.; Valle, M.

    1999-01-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

  1. An analog VLSI real time optical character recognition system based on a neural architecture

    Energy Technology Data Exchange (ETDEWEB)

    Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

    1999-03-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

  2. High performance VLSI telemetry data systems

    Science.gov (United States)

    Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

    1990-01-01

    NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

  3. Design of two easily-testable VLSI array multipliers

    Energy Technology Data Exchange (ETDEWEB)

    Ferguson, J.; Shen, J.P.

    1983-01-01

    Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

  4. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  5. Thermoreflectance temperature imaging of integrated circuits: calibration technique and quantitative comparison with integrated sensors and simulations

    International Nuclear Information System (INIS)

    Tessier, G; Polignano, M-L; Pavageau, S; Filloy, C; Fournier, D; Cerutti, F; Mica, I

    2006-01-01

    Camera-based thermoreflectance microscopy is a unique tool for high spatial resolution thermal imaging of working integrated circuits. However, a calibration is necessary to obtain quantitative temperatures on the complex surface of integrated circuits. The spatial and temperature resolutions reached by thermoreflectance are excellent (360 nm and 2.5 x 10 -2 K in 1 min here), but the precision is more difficult to assess, notably due to the lack of comparable thermal techniques at submicron scales. We propose here a Peltier element control of the whole package temperature in order to obtain calibration coefficients simultaneously on several materials visible on the surface of the circuit. Under high magnifications, movements associated with thermal expansion are corrected using a piezo electric displacement and a software image shift. This calibration method has been validated by comparison with temperatures measured using integrated thermistors and diodes and by a finite volume simulation. We show that thermoreflectance measurements agree within a precision of ±2.3% with the on-chip sensors measurements. The diode temperature is found to underestimate the actual temperature of the active area by almost 70% due to the thermal contact of the diode with the substrate, acting as a heat sink

  6. FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

    International Nuclear Information System (INIS)

    Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

    1998-01-01

    We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

  7. Geiger-Muller (GM) counters. Associated circuits and counting techniques; Les compteurs de Geiger-Muller (GM). Les circuits associes et techniques de comptage

    Energy Technology Data Exchange (ETDEWEB)

    Benoit, A.; Picard, E. [Commissariat a l' Energie Atomique, Centre d' Etudes Nucleaires de Saclay (France)

    1954-07-01

    This article presents the Geiger-Muller counters which present the great benefit of being simple and steady in comparison with other known sensors. The authors propose an overview of problems related to the use of Geiger-Muller counters (GM counters). They first describe their operation (discharge initiation, discharge propagation, collection of positive ions and current in the counter). They discuss their limitations which are related to the migration delay of primary electrons and positive ions. They describe the operation circuit for counters with organic vapour, and for counters associated with counters using halogens. They address the main properties of GM counters, and the different factors to be taken into account when using them to count radioactive sources. The main types of GM counters are then described (they are used to measure different types of radiation). Measurement techniques are discussed for beta radiation (relationship between the number of disintegrations and the noticed counting rate, case of backscattering, absorption and diffusion in the counter window and in the air, influence of absorption and backscattering in the source), for alpha radiation, and for gamma radiation.

  8. Integrated optical circuits for numerical computation

    Science.gov (United States)

    Verber, C. M.; Kenan, R. P.

    1983-01-01

    The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

  9. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  10. The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits

    CERN Document Server

    Arora, Mohit

    2012-01-01

    This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon.� Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.�� Describes techniques to help IP designers get it right the first time, creating designs optimized in terms of power, area and performance; Focuses on practical aspects of chip design and minimizes theory; Covers chip design in a consistent way, starting with basics and gradually developing advanced concepts, such as electromagnetic compatibility (EMC) design techniques and low-power design techniques such as dynamic voltage...

  11. Test methods of total dose effects in very large scale integrated circuits

    International Nuclear Information System (INIS)

    He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

    2004-01-01

    A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

  12. A Knowledge Based Approach to VLSI CAD

    Science.gov (United States)

    1983-09-01

    Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

  13. Measurement of liquid level in a natural circulation circuit using an ultrasonic technique

    International Nuclear Information System (INIS)

    Barbosa, Amanda Cardozo; Su, Jian

    2017-01-01

    The measurement by an ultrasonic technique of the water level in the expansion tank of the Natural Circulation Circuit (NCC) of the Experimental Thermo-Hydraulic Laboratory of the Institute of Nuclear Engineering is presented. In the single-phase NCC operation the water level in the expansion tank is stable. However, during the two-phase operation, oscillations occur in the water level due to temperature and vacuum fraction variations. Thus, the development of a technique that allows the measurement of these oscillations, will allow an estimation of the variation of the vacuum fraction of the circuit over time. The experimental set - up was performed on a test bench, using an ultrasonic transducer. The ultrasonic technique used is pulse-echo, in which the same transducer is the transmitter and receiver of the signal. The transducer-shoe assembly is part of an ultrasonic system consisting of an ultrasonic signal generating plate, transducers and a computer (PC) with a program in LabView to control the system. The program is able to calculate the transit time that the ultrasonic signals take to cross the tank base wall, the layer (level) of liquid and return to the transducer. Knowing the speed of the ultrasound in the wall and in the liquid it is possible to calculate the thickness of the wall and the height of the liquid. Measurements were made by filling the tank with a known volume of water and under varying temperature conditions, from room temperature to 90 deg C. The liquid heights are determined and the volume of water calculated by measuring the temperature with a digital thermometer. The volumes measured were highly accurate when compared to the known volumes

  14. VLSI architecture and design for the Fermat Number Transform implementation

    Energy Technology Data Exchange (ETDEWEB)

    Pajayakrit, A.

    1987-01-01

    A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

  15. Review of the OECD specialist meeting on continuous monitoring techniques for assuring coolant circuit integrity

    International Nuclear Information System (INIS)

    Thie, J.A.

    1986-01-01

    This article summarizes the OECD Specialist Meeting on Continuous Monitoring Techniques for Assuring Coolant Circuit Integrity held August 12-14, 1985, in London. The conference was organized by the Organization for Economic Cooperation and Development's (OECD's) Committee on the Safety for Nuclear Installations and hosted by Her Majesty's Nuclear Installation Inspectorate at King's College. Many other conferences have addressed analysis and inspection approaches to ensuring primary-system integrity, but the OECD meeting was structured to pay attention to the continuous monitoring approach - possibly the first conference to be so designed. The specific technologies represented were vibrations, noise (i.e., random fluctuations in signals), leaks, acoustic emission, and cyclic fatigue. Although water reactors dominate the papers, all reactor types were included. A diverse group of about 50 attendees from 11 countries participated, including representatives from utilities, suppliers, regulators, and researchers

  16. Microwave amplifier and active circuit design using the real frequency technique

    CERN Document Server

    Jarry, Pierre

    2016-01-01

    This book focuses on the authors' Real Frequency Technique (RFT) and its application to a wide variety of multi-stage microwave amplifiers and active filters, and passive equalizers for radar pulse shaping and antenna return loss applications. The first two chapters review the fundamentals of microwave amplifier design and provide a description of the RFT. Each subsequent chapter introduces a new type of amplifier or circuit design, reviews its design problems, and explains how the RFT can be adapted to solve these problems. The authors take a practical approach by summarizing the design steps and giving numerous examples of amplifier realizations and measured responses. Provides a complete description of the RFT as it is first used to design multistage lumped amplifiers using a progressive optimization of the equalizers, leading to a small umber of parameters to optimize simultaneously Presents modifications to the RFT to design trans-impedance microwave amplifiers that are used for photodiodes acti...

  17. How complex can integrated optical circuits become?

    NARCIS (Netherlands)

    Smit, M.K.; Hill, M.T.; Baets, R.G.F.; Bente, E.A.J.M.; Dorren, H.J.S.; Karouta, F.; Koenraad, P.M.; Koonen, A.M.J.; Leijtens, X.J.M.; Nötzel, R.; Oei, Y.S.; Waardt, de H.; Tol, van der J.J.G.M.; Khoe, G.D.

    2007-01-01

    The integration scale in Photonic Integrated Circuits will be pushed to VLSI-level in the coming decade. This will bring major changes in both application and manufacturing. In this paper developments in Photonic Integration are reviewed and the limits for reduction of device demensions are

  18. Design of delay insensitive circuits using multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

    1992-01-01

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

  19. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Science.gov (United States)

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  20. Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits.

    Science.gov (United States)

    1987-06-01

    Thoasietor R.AMbS .. ................... 166 12.2 Bootstrap Driver ... . .. .. .. .................. 167 List of Tables 1.1 TheSigalLvelVrusthe Dgtal Lvel ...THIS RESEARCH 35 Protocols Functional Lvel Sequential Systes 0io" L"ve Figure 1.7: Silica Pithecus’s place in the verifier community. The only direct...athematial structere underlyisg it behavior When thin mathematical structue is sot mae explicis a weaiw will eithe fadl or sakea very .Mg time. The

  1. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    Directory of Open Access Journals (Sweden)

    A. Schmitz

    2005-01-01

    Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  2. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  3. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Directory of Open Access Journals (Sweden)

    Huan-Yuan Chen

    2017-09-01

    Full Text Available This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

  4. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Science.gov (United States)

    Chen, Huan-Yuan; Chen, Chih-Chang

    2017-01-01

    This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

  5. VLSI-based video event triggering for image data compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-02-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  6. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  7. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  8. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  9. Draft of diagnostic techniques for primary coolant circuit facilities using control computer

    International Nuclear Information System (INIS)

    Suchy, R.; Procka, V.; Murin, V.; Rybarova, D.

    A method is proposed of in-service on-line diagnostics of primary circuit selected parts by means of a control computer. Computer processing will involve the measurements of neutron flux, pressure difference in pumps and in the core, and the vibrations of primary circuit mechanical parts. (H.S.)

  10. Analogue and Mixed-Signal Integrated Circuits for Space Applications

    CERN Document Server

    2014-01-01

    The purpose of AMICSA 2014 (organised in collaboration of ESA and CERN) is to provide an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

  11. Selection of the number of moderator circuits for Argos PHWR 380 by means of multicriteria decision aiding technique

    International Nuclear Information System (INIS)

    Espejo, J.A.

    1989-01-01

    One of the problems in the design of Argos PHWR 380 was the selection of the number of moderator circuits. Two options were proposed, one with three circuits and the other with two circuits. The multicriteria outranking technique was applied to choose the best option. This method has the ability to handle both commensurable and qualitative criteria. It was considered The following prior criteria were cosidered to estimate the weighting factors in decreasing order of importance: public safety, licensing risk, availability (from the point of view of service quality), investment, normal operating dose. The qualification of these factors is discussed in the report as well as the utility functions. For the criteria operating cost and normal operating dose the differences between the utility values of the two options are masked by other factors. For this reason these two criteria were excluded and the analysis was made taking into account the remainding four criteria. The utility matrix was made with the utility values. From the utility matrix and the weighting factors, the concordance and the discordance matrixes were obtained. Adopting appropriate thresholds, both options were compared with the aid of the code Mulcri - I. The result of the comparison, described in the report, shows that the option of three moderator circuits is preferable to the option of two circuits. With the help of code Mulcri - I, a sensitivity analysis by modifying the utility values one by one was made. The analysis shows those variations lower than 50 % which do not revert the result. Variations from 50 % to 80 % revert the result in only a few cases. This means that it is not necessary to go deeper in the analysis of the estimations of the utility values. It is concluded that the option of three circuits finally adopted in Argos PHWR 380 design is preferable to the option of two circuits. (Author)

  12. A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

    Science.gov (United States)

    Tuttle, Jeffery L.

    In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface

  13. CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

    International Nuclear Information System (INIS)

    Seidl, Albert; Klose, Helmut; Svoboda, Mildos

    2004-01-01

    1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

  14. A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

    Directory of Open Access Journals (Sweden)

    C. Wu

    2011-06-01

    Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

  15. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  16. Basic circuit compilation techniques for an ion-trap quantum machine

    International Nuclear Information System (INIS)

    Maslov, Dmitri

    2017-01-01

    We study the problem of compilation of quantum algorithms into optimized physical-level circuits executable in a quantum information processing (QIP) experiment based on trapped atomic ions. We report a complete strategy: starting with an algorithm in the form of a quantum computer program, we compile it into a high-level logical circuit that goes through multiple stages of decomposition into progressively lower-level circuits until we reach the physical execution-level specification. We skip the fault-tolerance layer, as it is not within the scope of this work. The different stages are structured so as to best assist with the overall optimization while taking into account numerous optimization criteria, including minimizing the number of expensive two-qubit gates, minimizing the number of less expensive single-qubit gates, optimizing the runtime, minimizing the overall circuit error, and optimizing classical control sequences. Our approach allows a trade-off between circuit runtime and quantum error, as well as to accommodate future changes in the optimization criteria that may likely arise as a result of the anticipated improvements in the physical-level control of the experiment. (paper)

  17. Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite

    Directory of Open Access Journals (Sweden)

    Takaya Handa

    2012-01-01

    Full Text Available Low-power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low-resistance state (LRS device and the RESET operation to high-resistance state (HRS device causes not only an increase in power but also the degradation of the write cycles due to repeatedly rewriting. Thus, in this paper, we proposed a novel automatic avoidance circuit for dealing with wasteful overwriting that uses a sense amplifier and estimated the energy consumption reduction rate by conducting a circuit simulation. As a result, this circuit helped to reliably avoid the wasteful overwriting operation to reduce about 99% and 97% of wasteful energy using VSRC and CSRC, respectively.

  18. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  19. Wavelength-encoded OCDMA system using opto-VLSI processors

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  20. Circuit and Measurement Technique for Radiation Induced Drift in Precision Capacitance Matching

    Science.gov (United States)

    Prasad, Sudheer; Shankar, Krishnamurthy Ganapathy

    2013-04-01

    In the design of radiation tolerant precision ADCs targeted for space market, a matched capacitor array is crucial. The drift of capacitance ratios due to radiation should be small enough not to cause linearity errors. Conventional methods for measuring capacitor matching may not achieve the desired level of accuracy due to radiation induced gain errors in the measurement circuits. In this work, we present a circuit and method for measuring capacitance ratio drift to a very high accuracy (<; 1 ppm) unaffected by radiation levels up to 150 krad.

  1. Comparison of Parametrization Techniques for an Electrical Circuit Model of Lithium-Sulfur Batteries

    DEFF Research Database (Denmark)

    Knap, Vaclav; Stroe, Daniel Loan; Teodorescu, Remus

    2015-01-01

    on the comparison of different parametrization methods of electrical circuit models (ECMs) for Li-S batteries. These methods are used to parametrize an ECM based on laboratory measurements performed on a Li-S pouch cell. Simulation results of ECMs are presented and compared against measurement values...

  2. Adaptive Backoff Synchronization Techniques

    Science.gov (United States)

    1989-07-01

    Percentage of synchronization and non- synchronisation references that cause invalidations in directory schemes with 2, 3, 4, 5, and 64 pointers...processors to arrive. The slight relative increase of synchronisation overhead in all cases when going from two to five pointers is because synchronization ...MASSACHUSETTS INSTITUTE OF TECHNOLOGY VLSI PUBLICATIONS q~JU VLSI Memo No. 89-547 It July 1989 Adaptive Backoff Synchronization Techniques Anant

  3. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  4. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  5. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  6. Development of a construction and manufacturing techniques of complementary transistors for the radiation tolerant integrated circuits

    Directory of Open Access Journals (Sweden)

    Gorban A. N.

    2011-06-01

    Full Text Available The construction of vertical complementary transistors with the full dielectric isolation is developed, new technolo-gical processes of creation on their basis the radiation tolerant integrated circuits with parameters which provide low values of a leakage current along with the considerable values of a forward current and breakdown voltage at the information signals exchange frequency of about 500 kHz are developed.

  7. A novel technique for CAD-optimization of analog circuits with bipolar transistors

    Directory of Open Access Journals (Sweden)

    B. Dimov

    2009-05-01

    Full Text Available In this paper, a novel approach for robust automatic optimization of analog circuits with bipolar transistors is presented. It includes additional formal parameters into the device model cards, which sweep the model parameters smoothly between the different device types. In this way, not only the sizing, but also the choice of the device type is committed to the optimization tool, thus improving the efficiency of the design process significantly.

  8. Airborne particle monitoring with urban closed-circuit television camera networks and a chromatic technique

    International Nuclear Information System (INIS)

    Kolupula, Y R; Jones, G R; Deakin, A G; Spencer, J W; Aceves-Fernandez, M A

    2010-01-01

    An economic approach for the preliminary assessment of 2–10 µm sized (PM10) airborne particle levels in urban areas is described. It uses existing urban closed-circuit television (CCTV) surveillance camera networks in combination with particle accumulating units and chromatic quantification of polychromatic light scattered by the captured particles. Methods for accommodating extraneous light effects are discussed and test results obtained from real urban sites are presented to illustrate the potential of the approach

  9. Nano devices and circuit techniques for low-energy applications and energy harvesting

    CERN Document Server

    2016-01-01

    This book describes the development of core technologies to address two of the most challenging issues in research for future IT platform development, namely innovative device design and reduction of energy consumption. Three key devices, the FinFET, the TunnelFET, and the electromechanical nanoswitch are described with extensive details of use for practical applications. Energy issues are also covered in a tutorial fashion from material physics, through device technology, to innovative circuit design. The strength of this book lies in its holistic approach dealing with material trends, state-of-the-art of key devices, new examples of circuits and systems applications.    This is the first of three books based on the Integrated Smart Sensors research project, which describe the development of innovative devices, circuits, and system-level enabling technologies.  The aim of the project was to develop common platforms on which various devices and sensors can be loaded, and to create systems offering signific...

  10. Improvement of diagnostic techniques and electrical circuit in azo dye degradation by high voltage electrical discharge

    International Nuclear Information System (INIS)

    Shen Yongjun; Lei Lecheng; Zhang Xingwang; Zhou Minghua; Zhang Yi

    2008-01-01

    Fast electrical diagnostics and improvement of electrical circuits for methyl orange (MO) degradation by high voltage pulsed electrical discharge were investigated. To eliminate electromagnetic radiation, several effective methods were employed. RG 218 coaxial cable was substituted for the common transmission lines to transmit high voltage pulses, and multi-lines in parallel were earthed to avoid electromagnetic interference and, additionally, to reduce the stray inductance of the electrical circuit and increase the pulse rise rate to reduce the energy losses in the transmission system. The problem of the differences in the bandwidths of voltage and current probes causing an error in the calculation of energy dissipation was avoided by reducing the bandwidths of voltage and current measurements to the same value. The real discharge current was obtained by subtracting the capacitive current from the total current. The energy per pulse obtained in the reactor before and after improvement of the diagnostics and electrical circuit were 15.5 mJ and 26.8 mJ, respectively, and the energy efficiencies of MO degradation were 1.34 x 10 -9 mol/J and 1.95 x 10 -9 mol/J, respectively

  11. Comparative Study of Crosstalk Reduction Techniques in RF Printed Circuit Board Using FDTD Method

    Directory of Open Access Journals (Sweden)

    Rajeswari Packianathan

    2015-01-01

    Full Text Available Miniaturization of the feature size in modern electronic circuits results from placing interconnections in close proximity with a high packing density. As a result, coupling between the adjacent lines has increased significantly, causing crosstalk to become an important concern in high-performance circuit design. In certain applications, microstriplines may be used in printed circuit boards for propagating high-speed signals, rather than striplines. Here, the electromagnetic coupling effects are analyzed for various microstrip transmission line structures, namely, microstriplines with a guard trace, double stub microstriplines, and parallel serpentine microstriplines using the finite-difference time-domain method. The numerical results are compared with simulation results, where the variants are simulated using an Ansoft high-frequency structure simulator. The analysis and simulation results are experimentally validated by fabricating a prototype and establishing a good correspondence between them. Numerical results are compared with simulation and experimental results, showing that double stub microstriplines reduce the far end crosstalk by 7 dB and increase the near end crosstalk by about 2 dB compared with the parallel microstriplines. Parallel serpentine microstriplines reduce the far end crosstalk by more than 10 dB and also reduce more than 15 mV of peak far end crosstalk voltage, compared with parallel microstriplines.

  12. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  13. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  14. VLSI Design of Trusted Virtual Sensors.

    Science.gov (United States)

    Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

    2018-01-25

    This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

  15. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  16. Design and fabrication of ZnO/TiO2-based thin-film inverter circuits using solution processing techniques

    International Nuclear Information System (INIS)

    Liau, Leo Chau-Kuang; Kuo, Juo-Wei; Chiang, Hsin-Ni

    2012-01-01

    Novel and cost-effective ceramic-based thin-film inverter circuits, based on two layers of TiO 2 and ZnO films to construct junction field-effect transistors (FETs), were designed and fabricated by solution coating techniques. The double layers of the sol–gel ZnO and TiO 2 films were coated and characterized as a diode according to the current–voltage performance. Two types of FETs, the p-channel (p-FET) and the n-channel (n-FET) devices, were produced using different coating sequences of ZnO and TiO 2 layers. Both of the transistor performances were evaluated by analyzing the source–drain current versus voltage (I ds –V ds ) data with the control of the gate voltage (V g ). The ZnO/TiO 2 -based inverter circuits, such as the complementary-FET device, were further fabricated using the integration of the p-FET and the n-FET. The voltage transfer characteristics of the inverters were estimated by the tests of the input voltage (V in ) versus the output voltage (V out ) for the thin-film inverter circuits. (paper)

  17. A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

    Science.gov (United States)

    Shi, Cong; Luo, Gang

    2018-04-01

    This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

  18. Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

    International Nuclear Information System (INIS)

    Ren Mei-Zhen; Zhang Jia-Shun; An Jun-Ming; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin XiaoJie; Hu Xiong-Wei

    2017-01-01

    The power consumption of a variable optical attenuator (VOA) array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner, the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment. (paper)

  19. Analog integrated circuit design automation placement, routing and parasitic extraction techniques

    CERN Document Server

    Martins, Ricardo; Horta, Nuno

    2017-01-01

    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures...

  20. A miniature rigid/flex salinity measurement device fabricated using printed circuit processing techniques

    International Nuclear Information System (INIS)

    Broadbent, H A; Ketterl, T P; Reid, C S

    2010-01-01

    The design, fabrication and initial performance of a single substrate, miniature, low-cost conductivity, temperature, depth (CTD) sensor board with interconnects are presented. In combination these sensors measure ocean salinity. The miniature CTD device board was designed and fabricated as the main component of a 50 mm × 25 mm × 25 mm animal-attached biologger. The board was fabricated using printed circuit processes and consists of two distinct regions on a continuous single liquid crystal polymer substrate: an 18 mm × 28 mm rigid multi-metal sensor section and a 72 mm long flexible interconnect section. The 95% confidence intervals for the conductivity, temperature and pressure sensors were demonstrated to be ±0.083 mS cm −1 , 0.01 °C, and ±0.135 dbar, respectively.

  1. Comparative Study of Online Open Circuit Voltage Estimation Techniques for State of Charge Estimation of Lithium-Ion Batteries

    Directory of Open Access Journals (Sweden)

    Hicham Chaoui

    2017-04-01

    Full Text Available Online estimation techniques are extensively used to determine the parameters of various uncertain dynamic systems. In this paper, online estimation of the open-circuit voltage (OCV of lithium-ion batteries is proposed by two different adaptive filtering methods (i.e., recursive least square, RLS, and least mean square, LMS, along with an adaptive observer. The proposed techniques use the battery’s terminal voltage and current to estimate the OCV, which is correlated to the state of charge (SOC. Experimental results highlight the effectiveness of the proposed methods in online estimation at different charge/discharge conditions and temperatures. The comparative study illustrates the advantages and limitations of each online estimation method.

  2. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  3. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  4. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  5. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  6. An innovative technique to improve safety of volatile anesthetics suction from the cardiopulmonary bypass circuit

    Directory of Open Access Journals (Sweden)

    Francesco De Simone

    2017-01-01

    Full Text Available Context: Myocardial injury during cardiac surgery on cardiopulmonary bypass (CPB is a major determinant of morbidity and mortality. Preclinical and clinical evidence of dose- and time-related cardioprotective effects of volatile anesthetic drugs exist and their use during the whole surgery duration could improve perioperative cardiac protection. Even if administering volatile agents during CPB are relatively easy, technical problems, such as waste gas scavenging, may prevent safe and manageable administration of halogenated vapors during CPB. Aims: The aim of this study is to improve the safe administration of volatile anesthesia during CPB. Settings and Design: Tertiary teaching hospital. Subjects and Methods: We describe an original device that collects and disposes of any volatile anesthetic vapors present in the exit stream of the oxygenator, hence preventing its dispersal into the operating theatre environment and adaptively regulates pressure of oxygenator chamber in the CPB circuit. Results: We have so far applied a prototype of this device in more than 1300 adult cardiac surgery patients who received volatile anesthetics during the CPB phase. Conclusions: Widespread implementation of scavenging system like the one we designed may facilitate the perfusionist and the anesthesiologist in delivering these cardioprotective drugs with beneficial impact on patients' outcome without compromising on safety.

  7. A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

    DEFF Research Database (Denmark)

    Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

    As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...

  8. An electron undulating ring for VLSI lithography

    International Nuclear Information System (INIS)

    Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

    1985-01-01

    The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

  9. Convolving optically addressed VLSI liquid crystal SLM

    Science.gov (United States)

    Jared, David A.; Stirk, Charles W.

    1994-03-01

    We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

  10. Development of XRMF techniques for measurement of multi-layer film thicknesses on semiconductors for VLSI and ULSI integrated circuits. Final CRADA report for CRADA number Y-1292-0130

    International Nuclear Information System (INIS)

    Carpenter, D.A.; Golijanin, D.L.; Wherry, D.

    1997-01-01

    A CRADA with Kevex Instruments was carried out to develop improved XRMF instrumentation for the nondestructive analysis of electronic components during manufacture. Experiments conducted at Y-12 proved the feasibility of a new Kevex x-ray tube design. Tests also show that the current commercial supply of straight glass capillaries is unreliable; however, other vendors of tapered single and multiple glass capillaries were identified. The stability of the Y-12 x-ray microprobe was significantly enhanced as a result of this CRADA

  11. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  12. Low Power CMOS Circuit Techniques for Optical Interconnects and High Speed Pulse Compression Radar

    OpenAIRE

    Li, Jun

    2015-01-01

    High performance computing and high resolution range sensor motivates the intelligent system innovations such as smart car, smart home/community and 3D motion games. Most importantly, 3D graphics technique requires high performance computation to provide high quality and vivid real-time videos. Accurate motion sensing requires high resolution radar sensor. However, in general, data transmission limits the large scale computation while high resolution radar signal processor limits the detectio...

  13. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  14. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  15. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  16. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  17. SEM technique for experimentally locating latch-up paths in integrated circuits

    International Nuclear Information System (INIS)

    Dressendorfer, P.V.; Armendariz, M.G.

    1980-01-01

    A technique is presented for using the scanning electron microscope (SEM) in the electron-beam-induced current (EBIC) mode to delineate latch-up paths in CMOS ICs. In the EBIC mode, the current produced by the collection and separation of the electron-beam-generated electron-hole pairs in the space charge regions of the device is measured and used to form an image. Since the collection of these carriers is dependent on space charge region width (and thus junction potential), anything that alters the depletion layer width will affect the collection efficiency. In a latch condition the junctions involved in the latch will be biased differently from those which are not, and thus the EBIC signal from those regions should be measurably different

  18. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  19. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  20. VLSI PARTITIONING ALGORITHM WITH ADAPTIVE CONTROL PARAMETER

    Directory of Open Access Journals (Sweden)

    P. N. Filippenko

    2013-03-01

    Full Text Available The article deals with the problem of very large-scale integration circuit partitioning. A graph is selected as a mathematical model describing integrated circuit. Modification of ant colony optimization algorithm is presented, which is used to solve graph partitioning problem. Ant colony optimization algorithm is an optimization method based on the principles of self-organization and other useful features of the ants’ behavior. The proposed search system is based on ant colony optimization algorithm with the improved method of the initial distribution and dynamic adjustment of the control search parameters. The experimental results and performance comparison show that the proposed method of very large-scale integration circuit partitioning provides the better search performance over other well known algorithms.

  1. Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2017-06-01

    Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

  2. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    International Nuclear Information System (INIS)

    Jian Haifang; Shi Yin

    2009-01-01

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  3. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  4. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  5. A self-adjusting delay circuit for pixel read-out chips

    International Nuclear Information System (INIS)

    Raith, B.

    1997-01-01

    A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

  6. A state-of-the-art review of continuous monitoring and surveillance techniques in relation to reactor pressure circuit integrity

    International Nuclear Information System (INIS)

    Nichols, R.W.

    1991-01-01

    This report reviews the present state of the art in the application to LWR primary circuit components of techniques for continuous monitoring and surveillance as an aid to structural integrity engineering assessments and to plant-life management. After discussing aspects related to the monitoring of plant operating conditions, particularly with respect to transient recording, the paper discusses neutron noise and vibration/noise measurements. The aspects of stress, temperature and chemical environment monitoring are discussed. Turning to measuring changes in mechanical properties of the structural materials the review first covers surveillance programmes for assessing irradiation embrittlement and then indicates a number of possibilities for the non-destructive monitoring of such changes although it is emphasized that none of these is ready for application without further development, calibration and plant trials. Moving on to the subject of monitoring structural damage the role of in-service inspection (ISI) using non-destructive testing methods is mentioned and the way that other methods, especially acoustic emission measurements, could supplement or in part replace such ISI is discussed. Other subjects covered include loose parts detection and leak detection which again often involve the use of acoustic emission. The paper ends with a short discussion and recommendations on future work and future possibilities

  7. Electric circuits essentials

    CERN Document Server

    REA, Editors of

    2012-01-01

    REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

  8. Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

    Science.gov (United States)

    2010-10-01

    spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

  9. Accelerated test techniques for micro-circuits: Evaluation of high temperature (473 k - 573 K) accelerated life test techniques as effective microcircuit screening methods

    Science.gov (United States)

    Johnson, G. M.

    1976-01-01

    The application of high temperature accelerated test techniques was shown to be an effective method of microcircuit defect screening. Comprehensive microcircuit evaluations and a series of high temperature (473 K to 573 K) life tests demonstrated that a freak or early failure population of surface contaminated devices could be completely screened in thirty two hours of test at an ambient temperature of 523 K. Equivalent screening at 398 K, as prescribed by current Military and NASA specifications, would have required in excess of 1,500 hours of test. All testing was accomplished with a Texas Instruments' 54L10, low power triple-3 input NAND gate manufactured with a titanium- tungsten (Ti-W), Gold (Au) metallization system. A number of design and/or manufacturing anomalies were also noted with the Ti-W, Au metallization system. Further study of the exact nature and cause(s) of these anomalies is recommended prior to the use of microcircuits with Ti-W, Au metallization in long life/high reliability applications. Photomicrographs of tested circuits are included.

  10. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  11. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  12. Area-Efficient Graph Layouts (for VLSI).

    Science.gov (United States)

    1980-08-13

    thle short side, then no rectangle is ew r generated x’.ho se aspect r~itho i s \\orse di ai aJ. ’I lie d i % ide-I mid -cimq tier clInt ruolIn in... Sutherland and Donald Oestrcichcr, "flow big should a printed circuit board be?," ILEEE, Transactions on Computers, Vol. C-22, May 1973, pp. 537-542. 22

  13. A VLSI image processor via pseudo-mersenne transforms

    International Nuclear Information System (INIS)

    Sei, W.J.; Jagadeesh, J.M.

    1986-01-01

    The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

  14. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  15. Passive surveillance: a technique to characterize the condition of power and control circuits in a nuclear plant

    International Nuclear Information System (INIS)

    Meininger, R.D.; Dinsel, M.R.

    1985-01-01

    This paper reports on progress by EG and G Idaho in examination of electrical circuits exposed to the accident environment at Three Mile Island Unit 2 (TMI-2) during and after the loss-of-coolant accident of March 28, 1979. Interpretations of the data collected suggest that the major functional impact on the electrical circuits (a) occurs very late in time, (b) is caused by moisture intrusion, and (c) can be detected by remote surveillance prior to functional failure. The electrical testing was performed from outside the TMI-2 Reactor Building at the penetrations using a special circuit characterization and diagnostic system developed by EG and G Idaho. This paper concentrates on representative data from those circuits which were recently retested. 12 refs., 9 figs

  16. A Readout Integrated Circuit (ROIC) employing self-adaptive background current compensation technique for Infrared Focal Plane Array (IRFPA)

    Science.gov (United States)

    Zhou, Tong; Zhao, Jian; He, Yong; Jiang, Bo; Su, Yan

    2018-05-01

    A novel self-adaptive background current compensation circuit applied to infrared focal plane array is proposed in this paper, which can compensate the background current generated in different conditions. Designed double-threshold detection strategy is to estimate and eliminate the background currents, which could significantly reduce the hardware overhead and improve the uniformity among different pixels. In addition, the circuit is well compatible to various categories of infrared thermo-sensitive materials. The testing results of a 4 × 4 experimental chip showed that the proposed circuit achieves high precision, wide application and high intelligence. Tape-out of the 320 × 240 readout circuit, as well as the bonding, encapsulation and imaging verification of uncooled infrared focal plane array, have also been completed.

  17. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  18. Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Zheng Xie

    2013-01-01

    Full Text Available The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict likely yield. Monte-Carlo- (MC- and quasi-MC- (QMC- based statistical techniques do this by analysing many randomised or quasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology, including “atomistic” effects without intradie correlation and effects with intradie correlation between neighbouring devices. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use of principal components analysis, behavioural modeling, and an implementation of “Statistical Blockade” (SB is shown to be capable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for a commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction, and this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The “yield prediction” analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using parameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained.

  19. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  20. The AMchip: A VLSI associative memory for track finding

    International Nuclear Information System (INIS)

    Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

    1992-01-01

    An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

  1. Drift chamber tracking with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

  2. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

  3. Analog circuits cookbook

    CERN Document Server

    Hickman, Ian

    2013-01-01

    Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

  4. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  5. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  6. An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1991-01-01

    A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

  7. GaAs integrated circuits and heterojunction devices

    Science.gov (United States)

    Fowlis, Colin

    1986-06-01

    The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

  8. Oscillator circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

  9. Measuring circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

  10. A novel configurable VLSI architecture design of window-based image processing method

    Science.gov (United States)

    Zhao, Hui; Sang, Hongshi; Shen, Xubang

    2018-03-01

    Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

  11. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  12. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  13. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  14. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  15. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  16. Point DCT VLSI Architecture for Emerging HEVC Standard

    OpenAIRE

    Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

    2012-01-01

    This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

  17. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  18. Power efficient and high performance VLSI architecture for AES algorithm

    Directory of Open Access Journals (Sweden)

    K. Kalaiselvi

    2015-09-01

    Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

  19. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2009-02-01

    Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

  20. Timergenerator circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

  1. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  2. Development of Radhard VLSI electronics for SSC calorimeters

    International Nuclear Information System (INIS)

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

  3. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  4. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  5. Global floor planning approach for VLSI design

    International Nuclear Information System (INIS)

    LaPotin, D.P.

    1986-01-01

    Within a hierarchical design environment, initial decisions regarding the partitioning and choice of module attributes greatly impact the quality of the resulting IC in terms of area and electrical performance. This dissertation presents a global floor-planning approach which allows designers to quickly explore layout issues during the initial stages of the IC design process. In contrast to previous efforts, which address the floor-planning problem from a strict module placement point of view, this approach considers floor-planning from an area planning point of view. The approach is based upon a combined min-cut and slicing paradigm, which ensures routability. To provide flexibility, modules may be specified as having a number of possible dimensions and orientations, and I/O pads as well as layout constraints are considered. A slicing-tree representation is employed, upon which a sequence of traversal operations are applied in order to obtain an area efficient layout. An in-place partitioning technique, which provides an improvement over previous min-cut and slicing-based efforts, is discussed. Global routing and module I/O pin assignment are provided for floor-plan evaluation purposes. A computer program, called Mason, has been developed which efficiently implements the approach and provides an interactive environment for designers to perform floor-planning. Performance of this program is illustrated via several industrial examples

  6. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  7. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  8. Electronic Circuit Analysis Language (ECAL)

    Science.gov (United States)

    Chenghang, C.

    1983-03-01

    The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

  9. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    Science.gov (United States)

    2007-03-31

    IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

  10. VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

    Science.gov (United States)

    Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

    1984-01-01

    Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

  11. VLSI and system architecture-the new development of system 5G

    Energy Technology Data Exchange (ETDEWEB)

    Sakamura, K.; Sekino, A.; Kodaka, T.; Uehara, T.; Aiso, H.

    1982-01-01

    A research and development proposal is presented for VLSI CAD systems and for a hardware environment called system 5G on which the VLSI CAD systems run. The proposed CAD systems use a hierarchically organized design language to enable design of anything from basic architectures of VLSI to VLSI mask patterns in a uniform manner. The cad systems will eventually become intelligent cad systems that acquire design knowledge and perform automatic design of VLSI chips when the characteristic requirements of VLSI chip is given. System 5G will consist of superinference machines and the 5G communication network. The superinference machine will be built based on a functionally distributed architecture connecting inferommunication network. The superinference machine will be built based on a functionally distributed architecture connecting inference machines and relational data base machines via a high-speed local network. The transfer rate of the local network will be 100 mbps at the first stage of the project and will be improved to 1 gbps. Remote access to the superinference machine will be possible through the 5G communication network. Access to system 5G will use the 5G network architecture protocol. The users will access the system 5G using standardized 5G personal computers. 5G personal logic programming stations, very high intelligent terminals providing an instruction set that supports predicate logic and input/output facilities for audio and graphical information.

  12. Point DCT VLSI Architecture for Emerging HEVC Standard

    Directory of Open Access Journals (Sweden)

    Ashfaq Ahmed

    2012-01-01

    Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

  13. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  14. Application of statistics to VLSI circuit manufacturing : test, diagnosis, and reliability

    NARCIS (Netherlands)

    Krishnan, Shaji

    2017-01-01

    Semiconductor product manufacturing companies strive to deliver defect free, and reliable products to their customers. However, with the down-scaling of technology, increasing the throughput at every stage of semiconductor product manufacturing becomes a harder challenge. To avoid process-related

  15. A comparison of 2 circuit exercise training techniques for eliciting matched metabolic responses in persons with paraplegia.

    Science.gov (United States)

    Nash, Mark S; Jacobs, Patrick L; Woods, Jeffrey M; Clark, James E; Pray, Tanya A; Pumarejo, Alex E

    2002-02-01

    To test whether acute metabolic (VO(2)), chronotropic (heart rate), and perceptual (rating of perceived exertion; RPE) responses to exercise by persons with paraplegia differ when the exercise is on a multistation isoinertial exercise system (MultiGym) or on a customized system of Thera-Band resistance bands (ElasticGym). Within-subjects comparison of 2 treatments. Academic medical center. Sixteen men and 1 woman with complete paraplegia (T4-L1), as defined by the American Spinal Injury Association. A circuit resistance training (CRT) program for persons with paraplegia was adapted to both a MultiGym and a customized ElasticGym. Exercises used for training and testing used 6 resistance maneuvers at 50% of the 1-repetition maximum (1-RM), with interposed rapid arm spinning. Subjects were habituated to both conditions for 2 weeks before testing on randomized nonconsecutive days. VO(2) (L/min) was measured by portable spirometry, heart rate (beats/min) by a chest strap monitor, and RPE by the Borg Scale of Perceived Exertion (6-20). No significant effects of test condition on average VO(2) or heart rate were observed, with differences between conditions reflecting only .08L/min and 6.4 beats/min, respectively. Average RPE was significantly higher in testing under the ElasticGym condition (P < .05). CRT on a customized ElasticGym system elicited acute metabolic and chronotropic responses that did not differ from responses to exercise on a MultiGym, though RPE was greater with the ElasticGym. Copyright 2002 by the American Congress of Rehabilitation Medicine and the American Academy of Physical Medicine and Rehabilitation

  16. Circuit analysis with Multisim

    CERN Document Server

    Baez-Lopez, David

    2011-01-01

    This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo

  17. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

  18. International Conference on Nano-electronics, Circuits & Communication Systems

    CERN Document Server

    2017-01-01

    This volume comprises select papers from the International Conference on Nano-electronics, Circuits & Communication Systems(NCCS). The conference focused on the frontier issues and their applications in business, academia, industry, and other allied areas. This international conference aimed to bring together scientists, researchers, engineers from academia and industry. The book covers technological developments and current trends in key areas such as VLSI design, IC manufacturing, and applications such as communications, ICT, and hybrid electronics. The contents of this volume will prove useful to researchers, professionals, and students alike.

  19. Practical guide to organic field effect transistor circuit design

    CERN Document Server

    Sou, Antony

    2016-01-01

    The field of organic electronics spans a very wide range of disciplines from physics and chemistry to hardware and software engineering. This makes the field of organic circuit design a daunting prospect full of intimidating complexities, yet to be exploited to its true potential. Small focussed research groups also find it difficult to move beyond their usual boundaries and create systems-on-foil that are comparable with the established silicon world.This book has been written to address these issues, intended for two main audiences; firstly, physics or materials researchers who have thus far designed circuits using only basic drawing software; and secondly, experienced silicon CMOS VLSI design engineers who are already knowledgeable in the design of full custom transistor level circuits but are not familiar with organic devices or thin film transistor (TFT) devices.In guiding the reader through the disparate and broad subject matters, a concise text has been written covering the physics and chemistry of the...

  20. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  1. Multi-Layer E-Textile Circuits

    Science.gov (United States)

    Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

    2012-01-01

    Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

  2. Advantages of the synthetic technique for the conduction of short circuit tests to breakers; Ventajas de la tecnica sintetica para realizar pruebas de corto circuito a interruptores

    Energy Technology Data Exchange (ETDEWEB)

    Sibilski, Henry [Instituto Electrotecnico de Varsovia, Varsovia (Poland); Ochoa Vivanco, Ruben [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1987-12-31

    In this article the operational principle of the synthetic test is described; specifically of the current injection circuit in parallel. Its utilization in the research and development of new breaker models and its wide possibilities regarding its testing characteristics is outlined. Likewise the different tests that can be performed by means of the synthetic technique are described. Finally the importance of the synthetic tests is outlined for the development of own technology in the area of interruption equipment and emphasis is made that in industrialized countries this technique is of common practice. [Espanol] En este articulo se describe el principio de operacion de la prueba sintetica; especificamente del circuito de inyeccion de corriente en paralelo. Se destaca su utilizacion en la investigacion y desarrollo de nuevos modelos de interruptores y sus amplias posibilidades en cuanto a caracteristicas de prueba. Asimismo, se describen las diferentes pruebas que pueden realizarse mediante la tecnica sintetica. Por ultimo, se destaca la importancia de las pruebas sinteticas para el desarrollo de tecnologia propia en el area de equipos de interrupcion, y se hace notar que en paises desarrollados, esta tecnica es practica comun.

  3. Advantages of the synthetic technique for the conduction of short circuit tests to breakers; Ventajas de la tecnica sintetica para realizar pruebas de corto circuito a interruptores

    Energy Technology Data Exchange (ETDEWEB)

    Sibilski, Henry [Instituto Electrotecnico de Varsovia, Varsovia (Poland); Ochoa Vivanco, Ruben [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1986-12-31

    In this article the operational principle of the synthetic test is described; specifically of the current injection circuit in parallel. Its utilization in the research and development of new breaker models and its wide possibilities regarding its testing characteristics is outlined. Likewise the different tests that can be performed by means of the synthetic technique are described. Finally the importance of the synthetic tests is outlined for the development of own technology in the area of interruption equipment and emphasis is made that in industrialized countries this technique is of common practice. [Espanol] En este articulo se describe el principio de operacion de la prueba sintetica; especificamente del circuito de inyeccion de corriente en paralelo. Se destaca su utilizacion en la investigacion y desarrollo de nuevos modelos de interruptores y sus amplias posibilidades en cuanto a caracteristicas de prueba. Asimismo, se describen las diferentes pruebas que pueden realizarse mediante la tecnica sintetica. Por ultimo, se destaca la importancia de las pruebas sinteticas para el desarrollo de tecnologia propia en el area de equipos de interrupcion, y se hace notar que en paises desarrollados, esta tecnica es practica comun.

  4. Role of non destructive techniques for monitoring structural integrity of primary circuit of pressurized water reactor nuclear power plant

    International Nuclear Information System (INIS)

    Sharma, P.K.; Sreenivas, P.

    2015-01-01

    The safety of nuclear installations is ensured by assessing status of primary equipment for performing the intended function reliably and maintaining the integrity of pressure boundaries. The pressure boundary materials undergo material degradation during the plant operation. Pressure boundary materials are subjected to operating stresses and material degradation that results in material properties changes, discontinuities initiation and increase in size of existing discontinuities. Pre-Service Inspection (PSI) is performed to generate reference base line data of initial condition of the pressure boundary. In-Service Inspections (ISI) are performed periodically to confirm integrity of pressure boundaries through comparison with respect to base line data. The non destructive techniques are deployed considering nature of the discontinuities expected to be generated through operating conditions and degradation mechanisms. The paper is prepared considering Pressurized Water Reactor (PWR) Nuclear Power Plant. The paper describes the degradation mechanisms observed in the PWR nuclear power plants and salient aspect of PSI and ISI and considerations in selecting non destructive testing. The paper also emphasises on application of acoustic emission (AE) based condition monitoring systems that can supplement in-service inspections for detecting and locating discontinuities in pressure boundaries. Criticality of flaws can be quantitatively evaluated by determining their size through in-service inspection. Challenges anticipated in deployment of AE based monitoring system and solutions to cater those challenges are also discussed. (author)

  5. Electronic circuit encyclopedia 2

    International Nuclear Information System (INIS)

    Park, Sun Ho

    1992-10-01

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  6. Electronic circuit encyclopedia 2

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sun Ho

    1992-10-15

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  7. A High Performance VLSI Computer Architecture For Computer Graphics

    Science.gov (United States)

    Chin, Chi-Yuan; Lin, Wen-Tai

    1988-10-01

    A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

  8. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  9. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  10. Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2004-09-01

    Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

  11. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    Ryu, C.; Boshier, M. G.

    2015-01-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  12. Evaluation of coagulation factors and platelet function from an off-line modified ultrafiltration technique for post-cardiopulmonary bypass circuit blood recovery.

    Science.gov (United States)

    Beckmann, S; Lynn, P; Miller, S; Harris, R; DiMarco, R F; Ross, J E

    2013-05-01

    Modified ultrafiltration (MUF) is a technique that hemoconcentrates residual CPB circuit blood and the patient at the same time. Hemoconcentration and MUF are Class 1-A recommendations in the anesthesia and surgical blood conservation guidelines. This study evaluated the off-line MUF process of the Hemobag (HB, Global Blood Resources, Somers, CT, USA) to quantitate coagulation factor levels, platelet (PLT) count and function in one facility and cellular growth factor concentrations of the final product that were transfused to the patient in another facility In two cardiac surgery facilities, after decannulation, the extracorporeal circuit (ECC) blood from 22 patients undergoing cardiac surgery was processed with the HB device. In eleven patients from the first facility by the study design, blood samples for coagulation factor levels and PLT aggregation were drawn from the reservoir of the MUF device pre- and post-processing. The samples (n = 11) were sent to a reference laboratory where testing for prothrombin time (PT), international normalized ratio (INR), activated partial thromboplastin time (aPTT), reptilase time, fibrinogen, clotting factors II, V, VII, VIII, IX, X, ADAMTS-13, protein C, protein S, antithrombin III, von Willebrand Factor (vWF), and platelet (PLT) aggregation were performed. A portion of the final concentrated HB blood samples (n = 5-10) from the second facility by design were evaluated for transforming and platelet-derived cellular growth factor concentrations. On average, approximately 800 - 2000 mls of whole blood were removed from the ECC post-CPB for processing in the HB device. After processing, there was, on the average, approximately 300 - 950 mls of concentrated whole blood salvaged for reinfusion. The PT and INR were significantly lower in the post-processing product compared to the pre-processing samples while the aPTT times were not significantly different. All coagulation factors and natural anti-coagulants were significantly

  13. Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

    International Nuclear Information System (INIS)

    Kim, D.S.; Seong, P.H.

    1994-01-01

    This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times

  14. Instrumentation and test gear circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

  15. Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

    Science.gov (United States)

    Makhijani, Vinod B.; Przekwas, Andrzej J.

    2002-10-01

    This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

  16. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  17. Clocking Scheme for Switched-Capacitor Circuits

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1998-01-01

    A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.......A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed....

  18. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  19. High-energy heavy ion testing of VLSI devices for single event ...

    Indian Academy of Sciences (India)

    Unknown

    per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

  20. Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

    Science.gov (United States)

    Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

    1991-01-01

    A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

  1. An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

    DEFF Research Database (Denmark)

    Paaske, Erik; Pedersen, Steen; Sparsø, Jens

    1991-01-01

    Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

  2. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  3. Arithmetic circuits for DSP applications

    CERN Document Server

    Stouraitis, Thanos

    2017-01-01

    Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

  4. FDTD technique based crosstalk analysis of bundled SWCNT interconnects

    International Nuclear Information System (INIS)

    Duksh, Yograj Singh; Kaushik, Brajesh Kumar; Agarwal, Rajendra P.

    2015-01-01

    The equivalent electrical circuit model of a bundled single-walled carbon nanotube based distributed RLC interconnects is employed for the crosstalk analysis. The accurate time domain analysis and crosstalk effect in the VLSI interconnect has emerged as an essential design criteria. This paper presents a brief description of the numerical method based finite difference time domain (FDTD) technique that is intended for estimation of voltages and currents on coupled transmission lines. For the FDTD implementation, the stability of the proposed model is strictly restricted by the Courant condition. This method is used for the estimation of crosstalk induced propagation delay and peak voltage in lossy RLC interconnects. Both functional and dynamic crosstalk effects are analyzed in the coupled transmission line. The effect of line resistance on crosstalk induced delay, and peak voltage under dynamic and functional crosstalk is also evaluated. The FDTD analysis and the SPICE simulations are carried out at 32 nm technology node for the global interconnects. It is observed that the analytical results obtained using the FDTD technique are in good agreement with the SPICE simulation results. The crosstalk induced delay, propagation delay, and peak voltage obtained using the FDTD technique shows average errors of 4.9%, 3.4% and 0.46%, respectively, in comparison to SPICE. (paper)

  5. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  6. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  7. Junction and circuit fabrication

    International Nuclear Information System (INIS)

    Jackel, L.D.

    1980-01-01

    Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

  8. Controllable circuit

    DEFF Research Database (Denmark)

    2010-01-01

    A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...

  9. Circuit Training.

    Science.gov (United States)

    Nelson, Jane B.

    1998-01-01

    Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

  10. VLSI Design Tools, Reference Manual, Release 2.0.

    Science.gov (United States)

    1984-08-01

    eder. 2.3 ITACV: Libary ofC readne. far oesumdg a layoit 1-,, tiling. V ~2.4 "QUILT: CeinS"Wbesa-i-M-8euar ray f atwok til 2.5 "TIL: Tockmeleff...8217patterns package was added so that complex and repetitive digital waveforms could be generated far more easily. The recently written program MTP (Multiple...circuit model to estimate timing delays through digital circuits. It also has a mode that allows it to be used as a switch (gate) level simulator

  11. High speed VLSI neural network for high energy physics

    NARCIS (Netherlands)

    Masa, P.; Masa, P.; Hoen, K.; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    A CMOS neural network IC is discussed which was designed for very high speed applications. The parallel architecture, analog computing and digital weight storage provides unprecedented computing speed combined with ease of use. The circuit classifies up to 70 dimensional vectors within 20

  12. Chaotic generation of PN sequences : a VLSI implementation

    NARCIS (Netherlands)

    Dornbusch, A.; Pineda de Gyvez, J.

    1999-01-01

    Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a

  13. A Fault Tolerant Integrated Circuit Memory

    OpenAIRE

    Barton, Anthony Francis

    1980-01-01

    Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

  14. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  15. Calculating and experimental technique for forecasting the bipolar digital integrated circuit response; Raschetno-ehksperimental`nyj metod prognozirovaniya reaktsii bipolyarnykh Ts IS

    Energy Technology Data Exchange (ETDEWEB)

    Butin, V I; Trofimov, Eh N

    1994-12-31

    Typical responses of the bipolar digital integrated circuits (DIC) of the combination type under the action of pulse gamma radiation are presented. Analysis of the DIC transients is carried out. A calculation-experimental method for forecasting the temporal serviceability loss of bipolar DIC is proposed. The reliability of the method is confirmed experimentally. 1 fig.

  16. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

  17. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Science.gov (United States)

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  18. Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

    Science.gov (United States)

    Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

    2011-09-01

    Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

  19. First results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

    1986-01-01

    A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

  20. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  1. LOGIC CIRCUIT

    Science.gov (United States)

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  2. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  3. The Maplin electronic circuits handbook

    CERN Document Server

    Tooley, Michael

    1990-01-01

    The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

  4. Neuromorphic VLSI vision system for real-time texture segregation.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2008-10-01

    The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

  5. Short- circuit tests of circuit breakers

    OpenAIRE

    Chorovský, P.

    2015-01-01

    This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

  6. Handbook of VLSI microlithography principles, technology and applications

    CERN Document Server

    Glendinning, William B

    1991-01-01

    This handbook gives readers a close look at the entire technology of printing very high resolution and high density integrated circuit (IC) patterns into thin resist process transfer coatings-- including optical lithography, electron beam, ion beam, and x-ray lithography. The book's main theme is the special printing process needed to achieve volume high density IC chip production, especially in the Dynamic Random Access Memory (DRAM) industry. The book leads off with a comparison of various lithography methods, covering the three major patterning parameters of line/space, resolution, line e

  7. VLSI for High-Speed Digital Signal Processing

    Science.gov (United States)

    1994-09-30

    particular, the design, layout and fab - rication of integrated circuits. The primary project for this grant has been the design and implementation of a...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

  8. A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

    Directory of Open Access Journals (Sweden)

    Xiaohui Fan

    2014-01-01

    Full Text Available With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF is proposed in this paper. Two high-Vth transistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

  9. Collective of mechatronics circuit

    International Nuclear Information System (INIS)

    1987-02-01

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  10. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  11. Improvement of CMOS VLSI rad tolerance by processing technics

    International Nuclear Information System (INIS)

    Guyomard, D.; Desoutter, I.

    1986-01-01

    The following study concerns the development of integrated circuits for fields requiring only relatively low radiation tolerance levels, and especially for the civil spatial district area. Process modifications constitute our basic study. They have been carried into effects. Our work and main results are reported in this paper. Well known 2.5 and 3 μm CMOS technologies are under our concern. A first set of modifications enables us to double the cumulative dose tolerance of a 4 Kbit SRAM, keeping at the same time the same kind of damage. We obtain memories which tolerate radiation doses as high as 16 KRad(Si). Repetitivity of the results, linked to the quality assurance of this specific circuit, is reported here. A second set of modifications concerns the processing of gate array. In particular, the choice of the silicon substrate type, (epitaxy substrate), is under investigation. On the other hand, a complete study of a test vehicule allows us to accurately measure the rad tolerance of various components of the Cell library [fr

  12. Circuit parties.

    Science.gov (United States)

    Guzman, R

    2000-03-01

    Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.

  13. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Hutcheson, L.D.

    1988-01-01

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  14. Simulation of a spiking neuron circuit using carbon nanotube transistors

    International Nuclear Information System (INIS)

    Najari, Montassar; El-Grour, Tarek; Jelliti, Sami; Hakami, Othman Mousa

    2016-01-01

    Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

  15. Simulation of a spiking neuron circuit using carbon nanotube transistors

    Energy Technology Data Exchange (ETDEWEB)

    Najari, Montassar, E-mail: malnjar@jazanu.edu.sa [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); IKCE unit, Jazan University, Jazan (Saudi Arabia); El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); Jelliti, Sami, E-mail: sjelliti@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Hakami, Othman Mousa, E-mail: omhakami@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Faculty of Sciences, Jazan University, Jazan (Saudi Arabia)

    2016-06-10

    Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

  16. Commutation circuit for an HVDC circuit breaker

    Science.gov (United States)

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  17. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  18. Trigger circuit

    International Nuclear Information System (INIS)

    Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

    1984-01-01

    A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

  19. A Streaming PCA VLSI Chip for Neural Data Compression.

    Science.gov (United States)

    Wu, Tong; Zhao, Wenfeng; Guo, Hongsun; Lim, Hubert H; Yang, Zhi

    2017-12-01

    Neural recording system miniaturization and integration with low-power wireless technologies require compressing neural data before transmission. Feature extraction is a procedure to represent data in a low-dimensional space; its integration into a recording chip can be an efficient approach to compress neural data. In this paper, we propose a streaming principal component analysis algorithm and its microchip implementation to compress multichannel local field potential (LFP) and spike data. The circuits have been designed in a 65-nm CMOS technology and occupy a silicon area of 0.06 mm. Throughout the experiments, the chip compresses LFPs by 10 at the expense of as low as 1% reconstruction errors and 144-nW/channel power consumption; for spikes, the achieved compression ratio is 25 with 8% reconstruction errors and 3.05-W/channel power consumption. In addition, the algorithm and its hardware architecture can swiftly adapt to nonstationary spiking activities, which enables efficient hardware sharing among multiple channels to support a high-channel count recorder.

  20. Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection

    Science.gov (United States)

    Luo, Aiwen; An, Fengwei; Zhang, Xiangyu; Chen, Lei; Huang, Zunkai; Jürgen Mattausch, Hans

    2018-04-01

    Feature extraction techniques are a cornerstone of object detection in computer-vision-based applications. The detection performance of vison-based detection systems is often degraded by, e.g., changes in the illumination intensity of the light source, foreground-background contrast variations or automatic gain control from the camera. In order to avoid such degradation effects, we present a block-based L1-norm-circuit architecture which is configurable for different image-cell sizes, cell-based feature descriptors and image resolutions according to customization parameters from the circuit input. The incorporated flexibility in both the image resolution and the cell size for multi-scale image pyramids leads to lower computational complexity and power consumption. Additionally, an object-detection prototype for performance evaluation in 65 nm CMOS implements the proposed L1-norm circuit together with a histogram of oriented gradients (HOG) descriptor and a support vector machine (SVM) classifier. The proposed parallel architecture with high hardware efficiency enables real-time processing, high detection robustness, small chip-core area as well as low power consumption for multi-scale object detection.

  1. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  2. Initial beam test results from a silicon-strip detector with VLSI readout

    International Nuclear Information System (INIS)

    Adolphsen, C.; Litke, A.; Schwarz, A.

    1986-01-01

    Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

  3. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  4. Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

    International Nuclear Information System (INIS)

    Jones, W.F.; Byars, L.G.; Casey, M.E.

    1988-01-01

    A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

  5. A Program of Research on Microfabrication Techniques for VLSI Magnetic Devices.

    Science.gov (United States)

    1981-10-01

    directions. The result is the perpendicular lattice expansion of a nonconstrained film. The mismatch is calculated using the following equation. 3d /d - -60...electrons from Mo to the 3d band of Co thereby lowering its moment (Hasegawa, at. &l. 1975). The exhange constant, A. which depends on the individual...encouraging comments. J. J. Fernandez de Castro also thanks the Mexican Government (CONSEJO NACIONAL DE CIENCIA Y TECNOLOGIA ) for the funds that it

  6. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  7. Circuit analysis for dummies

    CERN Document Server

    Santiago, John

    2013-01-01

    Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

  8. Current limiter circuit system

    Science.gov (United States)

    Witcher, Joseph Brandon; Bredemann, Michael V.

    2017-09-05

    An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

  9. A new integrated microwave SQUID circuit design

    International Nuclear Information System (INIS)

    Erne, S.N.; Finnegan, T.F.

    1980-01-01

    In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

  10. Remote crane control techniques and closed-circuit television for the U.S. Department of Energy, Defense Waste Processing Facility

    International Nuclear Information System (INIS)

    DaSilva, D.A.

    1988-01-01

    The Defense Waste Processing Facility (DWPF) located at the Savannah River Plant (SRP), South Carolina is a nuclear waste facility being built to vitrify and containerize high level radioactive waste products. DWPF has a unique requirement for an unmanned crane system to install and replace equipment in the high humidity, high radiation and harsh chemical environment of permanently inaccessible processing cells. A radio control system is provided to control a 117 ton capacity bridge crane that is equipped with various power tools for remote handling of crane replaceable and maintained equipment. High resolution black and white closed circuit television (CTV) assemblies mounted on the crane and on the walls of the various processing cells are provided for viewing the equipment during normal operations and maintenance. The main process cell (MPC) crane is designed as the vehicle to be the eyes, ears and hands for remote in-cell operations and maintenance. The crane runs on elevated rails above the process cells. A trailer-like-electrical equipment compartment (EEC) containing control and radio communications equipment for the crane; is dragged along on rails in a heavily shielded corridor by a drag bar mounted to the crane. A two way RF system is the communications link for all control and video signals between the crane and two stationary crane control consoles

  11. Analog circuit design art, science, and personalities

    CERN Document Server

    Williams, Jim

    1991-01-01

    Analog Circuit Design: Art, Science, and Personalities discusses the many approaches and styles in the practice of analog circuit design. The book is written in an informal yet informative manner, making it easily understandable to those new in the field. The selection covers the definition, history, current practice, and future direction of analog design; the practice proper; and the styles in analog circuit design. The book also includes the problems usually encountered in analog circuit design; approach to feedback loop design; and other different techniques and applications. The text is

  12. A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

    Science.gov (United States)

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2005-07-01

    In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

  13. Circuit modeling for electromagnetic compatibility

    CERN Document Server

    Darney, Ian B

    2013-01-01

    Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

  14. Multi-operation cryptographic engine: VLSI design and implementation

    International Nuclear Information System (INIS)

    Selimis, George; Koufopavlou, Odysseas

    2005-01-01

    The environment of smart card lacks of system resources but the commercial and economic transactions via smart cards demand the use of certificated and secure cryptographic methods. In this paper a cryptographic approach in hardware for smart cards is proposed. The proposed system supports two basic operations of cryptography, authentication and encryption. The basic component of system is the one round of DES algorithm which supports the DES, Triple DES and the ANSI X9.17 standards. The proposed system is efficient in terms of area resources and techniques for low power consumption have applied. Due to the fact that the system is for smart card applications the overall throughput outperforms the typical smart card throughput standards

  15. Grounding and shielding circuits and interference

    CERN Document Server

    Morrison, Ralph

    2016-01-01

    Applies basic field behavior in circuit design and demonstrates how it relates to grounding and shielding requirements and techniques in circuit design This book connects the fundamentals of electromagnetic theory to the problems of interference in all types of electronic design. The text covers power distribution in facilities, mixing of analog and digital circuitry, circuit board layout at high clock rates, and meeting radiation and susceptibility standards. The author examines the grounding and shielding requirements and techniques in circuit design and applies basic physics to circuit behavior. The sixth edition of this book has been updated with new material added throughout the chapters where appropriate. The presentation of the book has also been rearranged in order to reflect the current trends in the field.

  16. Multiplication circuit for particle identification

    International Nuclear Information System (INIS)

    Gerlier, Jean

    1962-01-01

    After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

  17. Vertically Integrated Circuits at Fermilab

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  18. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    1991-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  19. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1972-01-01

    Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

  20. Electrical Circuits and Water Analogies

    Science.gov (United States)

    Smith, Frederick A.; Wilson, Jerry D.

    1974-01-01

    Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

  1. Design, Analysis and Test of Logic Circuits Under Uncertainty

    CERN Document Server

    Krishnaswamy, Smita; Hayes, John P

    2013-01-01

    Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

  2. Piezoelectric drive circuit

    Science.gov (United States)

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  3. Load testing circuit

    DEFF Research Database (Denmark)

    2009-01-01

    A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

  4. Short-circuit logic

    NARCIS (Netherlands)

    Bergstra, J.A.; Ponse, A.

    2010-01-01

    Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

  5. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2011-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  6. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2010-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  7. Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access

    OpenAIRE

    Massad, Mohamed El; Garg, Siddharth; Tripunitara, Mahesh

    2017-01-01

    Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and obser...

  8. Operation of a Fast-RICH Prototype with VLSI readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

    1994-04-01

    We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

  9. Real time track finding in a drift chamber with a VLSI neural network

    International Nuclear Information System (INIS)

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-01-01

    In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

  10. Memristor Circuits and Systems

    KAUST Repository

    Zidan, Mohammed A.

    2015-05-01

    resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.

  11. Feedback in analog circuits

    CERN Document Server

    Ochoa, Agustin

    2016-01-01

    This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

  12. Efficient physical embedding of topologically complex information processing networks in brains and computer circuits.

    Directory of Open Access Journals (Sweden)

    Danielle S Bassett

    2010-04-01

    Full Text Available Nervous systems are information processing networks that evolved by natural selection, whereas very large scale integrated (VLSI computer circuits have evolved by commercially driven technology development. Here we follow historic intuition that all physical information processing systems will share key organizational properties, such as modularity, that generally confer adaptivity of function. It has long been observed that modular VLSI circuits demonstrate an isometric scaling relationship between the number of processing elements and the number of connections, known as Rent's rule, which is related to the dimensionality of the circuit's interconnect topology and its logical capacity. We show that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity. We further show that the estimated Rent exponent of human brain networks, derived from MRI data, can explain the allometric scaling relations between gray and white matter volumes across a wide range of mammalian species, again suggesting that these principles of nervous system design are highly conserved. For each of these fractal modular networks, the dimensionality of the interconnect topology was greater than the 2 or 3 Euclidean dimensions of the space in which it was embedded. This relatively high complexity entailed extra cost in physical wiring: although all networks were economically or cost-efficiently wired they did not strictly minimize wiring costs. Artificial and biological information processing systems both may evolve to optimize a trade-off between physical cost and topological complexity, resulting in the emergence of homologous principles of economical, fractal and modular design across many different kinds of nervous and computational networks.

  13. Monolithic readout circuits for RHIC

    International Nuclear Information System (INIS)

    O'Connor, P.; Harder, J.; Sippach, W.

    1991-10-01

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology

  14. Monolithic readout circuits for RHIC

    Energy Technology Data Exchange (ETDEWEB)

    O`Connor, P.; Harder, J. [Brookhaven National Laboratory, Upton, NY (United States)

    1991-12-31

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  15. VLSI Research

    Science.gov (United States)

    1984-04-01

    Interpretation of IMMEDIATE fields of instructions (except ldhi ): W (c) (d) (e) sssssssssssss s imml9 sssssssssssssssssss...s imml3 Destination REGISTER of a LDHI instruction: imml9 0000000000000 Data in REGISTERS when operated upon: 32-bit quantity...Oll x l OOOO OOOl calli sll OOlO getpsw sra xxzOOll getlpc srl OlOO putpsw ldhi OlOl and zzzOllO or ldxw stxw Olll xor

  16. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  17. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  18. Maximum Temperature Detection System for Integrated Circuits

    Science.gov (United States)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  19. Operational amplifier circuits analysis and design

    CERN Document Server

    Nelson, J C C

    1995-01-01

    This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

  20. Electric circuits and signals

    CERN Document Server

    Sabah, Nassir H

    2007-01-01

    Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

  1. [Shunt and short circuit].

    Science.gov (United States)

    Rangel-Abundis, Alberto

    2006-01-01

    Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

  2. Active Trimming of Hybrid Integrated Circuits

    OpenAIRE

    Németh, P.; Krémer, P.

    1984-01-01

    One of the more important fields of the microelectronics industry is the manufacturing of hybrid integrated circuits.An important part of the manufacturing process is concerned with the trimming of the hybrid integratedl circuits. This article deals with the basic principles of active trimming and introduces a microprocessor controlled trimming machine. By comparing active trimming with passive techniques, it can be shown that the active system has some advantages. This article outlines these...

  3. Regenerative feedback resonant circuit

    Science.gov (United States)

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  4. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  5. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1968-01-01

    Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

  6. Maximum Acceleration Recording Circuit

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1995-01-01

    Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

  7. Security electronics circuits manual

    CERN Document Server

    MARSTON, R M

    1998-01-01

    Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

  8. LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

    Energy Technology Data Exchange (ETDEWEB)

    Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

    1984-01-01

    Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

  9. Circuit for Communication Over Power Lines

    Science.gov (United States)

    Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

    2011-01-01

    Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

  10. Refractory silicides for integrated circuits

    International Nuclear Information System (INIS)

    Murarka, S.P.

    1980-01-01

    Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

  11. Wireless transceiver circuits system perspectives and design aspects

    CERN Document Server

    Rhee, Woogeun

    2015-01-01

    This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

  12. Advanced Microwave Circuits and Systems

    DEFF Research Database (Denmark)

    This book is based on recent research work conducted by the authors dealing with the design and development of active and passive microwave components, integrated circuits and systems. It is divided into seven parts. In the first part comprising the first two chapters, alternative concepts...... amplifier architectures. In addition, distortion analysis and power combining techniques are considered. Another key element in most microwave systems is a signal generator. It forms the heart of all kinds of communication and radar systems. The fourth part of this book is dedicated to signal generators...... push currently available technologies to the limits. Some considerations to meet the growing requirements are provided in the fifth part of this book. The following part deals with circuits based on LTCC and MEMS technologies. The book concludes with chapters considering application of microwaves...

  13. Foundations for microstrip circuit design

    CERN Document Server

    Edwards, Terry

    2016-01-01

    Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

  14. Parallel sparse direct solver for integrated circuit simulation

    CERN Document Server

    Chen, Xiaoming; Yang, Huazhong

    2017-01-01

    This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

  15. Circuits on Cylinders

    DEFF Research Database (Denmark)

    Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

    2006-01-01

    We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

  16. Technique and Calculation Results of Currents and Voltages in the Circuits of the Measuring Element of the Protection Device of the Transmission Line Based on the Control of Transient Processes

    Science.gov (United States)

    Lachugin, V. F.; Kulikov, A. L.; Platonov, P. S.; Vucolov, V. Yu.

    2017-12-01

    The specifics of generation of the signals of current and voltage in the circuits of a directional element of wave relay protection during short circuit (SC) in overhead power transmission lines are considered. The computing method of transient processes in the protection circuits, including frequency filters, that attenuate the parameters of currents and voltages of the mode taking into account the higher harmonic components and probable deviations of the frequency of transmission line from the rated value is presented. It is revealed that it is advisable to implement the measuring circuits of the directional elements of wave relay protection with the three-section filter attenuating the frequencies from 45 to 55 Hz and the low pass filter with cutoff frequency that does not exceed 1 kHz.

  17. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  18. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  19. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  20. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  1. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Science.gov (United States)

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  2. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  3. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  4. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Science.gov (United States)

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  5. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  6. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Gwyn, C.W.

    1976-09-01

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  7. Approximate circuits for increased reliability

    Science.gov (United States)

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-08-18

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  8. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  9. Introduction of circuit design on RFID system

    International Nuclear Information System (INIS)

    Pak, Sunho

    2007-06-01

    This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

  10. Introduction of circuit design on RFID system

    Energy Technology Data Exchange (ETDEWEB)

    Pak, Sunho

    2007-06-15

    This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

  11. Synthesis of multivalued quantum logic circuits by elementary gates

    Science.gov (United States)

    Di, Yao-Min; Wei, Hai-Rui

    2013-01-01

    We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.

  12. Troubleshooting analog circuits

    CERN Document Server

    Pease, Robert A

    1991-01-01

    Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

  13. Modern TTL circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

  14. 'Speedy' superconducting circuits

    International Nuclear Information System (INIS)

    Holst, T.

    1994-01-01

    The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

  15. Model reduction for circuit simulation

    CERN Document Server

    Hinze, Michael; Maten, E Jan W Ter

    2011-01-01

    Simulation based on mathematical models plays a major role in computer aided design of integrated circuits (ICs). Decreasing structure sizes, increasing packing densities and driving frequencies require the use of refined mathematical models, and to take into account secondary, parasitic effects. This leads to very high dimensional problems which nowadays require simulation times too large for the short time-to-market demands in industry. Modern Model Order Reduction (MOR) techniques present a way out of this dilemma in providing surrogate models which keep the main characteristics of the devi

  16. Universal programmable quantum circuit schemes to emulate an operator

    Energy Technology Data Exchange (ETDEWEB)

    Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

    2012-12-21

    Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

  17. Universal programmable quantum circuit schemes to emulate an operator

    International Nuclear Information System (INIS)

    Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

    2012-01-01

    Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

  18. Analogue circuits simulation

    Energy Technology Data Exchange (ETDEWEB)

    Mendo, C

    1988-09-01

    Most analogue simulators have evolved from SPICE. The history and description of SPICE-like simulators are given. From a mathematical formulation of the electronic circuit the following analysis are possible: DC, AC, transient, noise, distortion, Worst Case and Statistical.

  19. Printed circuit for ATLAS

    CERN Multimedia

    Laurent Guiraud

    1999-01-01

    A printed circuit board made by scientists in the ATLAS collaboration for the transition radiaton tracker (TRT). This will read data produced when a high energy particle crosses the boundary between two materials with different electrical properties.

  20. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  1. Peak reading detector circuit

    International Nuclear Information System (INIS)

    Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

    1975-01-01

    The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

  2. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  3. Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

    Science.gov (United States)

    Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

    2015-01-01

    Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

  4. Project Circuits in a Basic Electric Circuits Course

    Science.gov (United States)

    Becker, James P.; Plumb, Carolyn; Revia, Richard A.

    2014-01-01

    The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

  5. Electron beam effects on VLSI MOS conditions for testing and reconfiguration

    International Nuclear Information System (INIS)

    Girard, P.; Roche, F.M.; Pistoulet, B.

    1986-01-01

    Wafer scale integrated-MOS circuits problems related to test and reconfiguration by electron beams are analyzed. First of all the alterations in characteristics of MOS circuits submitted to an electron beam testing are considered. Then the capabilities of reconfiguration by an electron beam bombardment are discussed. The various phenomena involved are reviewed. Experimental data are reported and discussed on the light of data of the literature. (Auth.)

  6. VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme

    Directory of Open Access Journals (Sweden)

    G. Seetharaman

    2008-01-01

    Full Text Available A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP. A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25–1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15–1.39 at the cost of an increase in the number of registers by a factor of 1.78–2.73, increase in the number of LEs by a factor of 1.11–1.32 and it increases the clock routing complexity.

  7. Analog integrated circuits design for processing physiological signals.

    Science.gov (United States)

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  8. Short communication: Use of a portable, automated, open-circuit gas quantification system and the sulfur hexafluoride tracer technique for measuring enteric methane emissions in Holstein cows fed ad libitum or restricted.

    Science.gov (United States)

    Dorich, C D; Varner, R K; Pereira, A B D; Martineau, R; Soder, K J; Brito, A F

    2015-04-01

    The objective of this study was to measure enteric CH4 emissions using a new portable automated open-circuit gas quantification system (GQS) and the sulfur hexafluoride tracer technique (SF6) in midlactation Holstein cows housed in a tiestall barn. Sixteen cows averaging 176 ± 34 d in milk, 40.7 ± 6.1 kg of milk yield, and 685 ± 49 kg of body weight were randomly assigned to 1 out of 2 treatments according to a crossover design. Treatments were (1) ad libitum (adjusted daily to yield 10% orts) and (2) restricted feed intake [set to restrict feed by 10% of baseline dry matter intake (DMI)]. Each experimental period lasted 22d, with 14 d for treatment adaptation and 8d for data and sample collection. A common diet was fed to the cows as a total mixed ration and contained 40.4% corn silage, 11.2% grass-legume haylage, and 48.4% concentrate on a dry matter basis. Spot 5-min measurements using the GQS were taken twice daily with a 12-h interval between sampling and sampling times advanced 2h daily to account for diurnal variation in CH4 emissions. Canisters for the SF6 method were sampled twice daily before milking with 4 local background gas canisters inside the barn analyzed for background gas concentrations. Enteric CH4 emissions were not affected by treatments and averaged 472 and 458 g/d (standard error of the mean = 18 g/d) for ad libitum and restricted intake treatments, respectively (data not shown). The GQS appears to be a reliable method because of the relatively low coefficients of variation (ranging from 14.1 to 22.4%) for CH4 emissions and a moderate relationship (coefficient of determination = 0.42) between CH4 emissions and DMI. The SF6 resulted in large coefficients of variation (ranging from 16.0 to 111%) for CH4 emissions and a poor relationship (coefficient of determination = 0.17) between CH4 emissions and DMI, likely because of limited barn ventilation and high background gas concentration. Research with improved barn ventilation systems or

  9. Dynamics of pi-junction interferometer circuits

    DEFF Research Database (Denmark)

    Kornkev, V.K.; Mozhaev, P.B.; Borisenko, I.V.

    2002-01-01

    The pi-junction superconducting circuit dynamics was studied by means of numerical simulation technique. Parallel arrays consisting of Josephson junctions of both 0- and pi-type were studied as a model of high-T-c grain-boundary Josephson junction. The array dynamics and the critical current depe...

  10. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  11. Circuit and interconnect design for high bit-rate applications

    NARCIS (Netherlands)

    Veenstra, H.

    2006-01-01

    This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

  12. Otanps synapse linear relation multiplier circuit

    International Nuclear Information System (INIS)

    Chible, H.

    2008-01-01

    In this paper, a four quadrant VLSI analog multiplier will be proposed, in order to be used in the implementation of the neurons and synapses modules of the artificial neural networks. The main characteristics of this multiplier are the small silicon area and the low power consumption and the high value of the weight input voltage. (author)

  13. Ant colony optimisation-direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

    Science.gov (United States)

    Abd-El-Barr, Mostafa

    2010-12-01

    The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO-DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO-DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.

  14. A microcontroller-based interface circuit for lossy capacitive sensors

    International Nuclear Information System (INIS)

    Reverter, Ferran; Casas, Òscar

    2010-01-01

    This paper introduces and analyses a low-cost microcontroller-based interface circuit for lossy capacitive sensors, i.e. sensors whose parasitic conductance (G x ) is not negligible. Such a circuit relies on a previous circuit also proposed by the authors, in which the sensor is directly connected to a microcontroller without using either a signal conditioner or an analogue-to-digital converter in the signal path. The novel circuit uses the same hardware, but it performs an additional measurement and executes a new calibration technique. As a result, the sensitivity of the circuit to G x decreases significantly (a factor higher than ten), but not completely due to the input capacitances of the port pins of the microcontroller. Experimental results show a relative error in the capacitance measurement below 1% for G x x ) shows the effectiveness of the circuit

  15. Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Farouk Smith

    2015-07-01

    Full Text Available This paper propose a Virtual-Field Programmable Gate Array (V-FPGA architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA; and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm; applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

  16. Basic matrix algebra and transistor circuits

    CERN Document Server

    Zelinger, G

    1963-01-01

    Basic Matrix Algebra and Transistor Circuits deals with mastering the techniques of matrix algebra for application in transistors. This book attempts to unify fundamental subjects, such as matrix algebra, four-terminal network theory, transistor equivalent circuits, and pertinent design matters. Part I of this book focuses on basic matrix algebra of four-terminal networks, with descriptions of the different systems of matrices. This part also discusses both simple and complex network configurations and their associated transmission. This discussion is followed by the alternative methods of de

  17. Electromagnetic compatibility methods, analysis, circuits, and measurement

    CERN Document Server

    Weston, David A

    2016-01-01

    Revised, updated, and expanded, Electromagnetic Compatibility: Methods, Analysis, Circuits, and Measurement, Third Edition provides comprehensive practical coverage of the design, problem solving, and testing of electromagnetic compatibility (EMC) in electrical and electronic equipment and systems. This new edition provides novel information on theory, applications, evaluations, electromagnetic computational programs, and prediction techniques available. With sixty-nine schematics providing examples for circuit level electromagnetic interference (EMI) hardening and cost effective EMI problem solving, this book also includes 1130 illustrations and tables. Including extensive data on components and their correct implementation, the myths, misapplication, misconceptions, and fallacies that are common when discussing EMC/EMI will also be addressed and corrected.

  18. RF and microwave coupled-line circuits

    CERN Document Server

    Mongia, R K; Bhartia, P; Hong, J; Gupta, K C

    2007-01-01

    This extensively revised edition of the 1999 Artech House classic, RF and Microwave Coupled-Line Circuits, offers you a thoroughly up-to-date understanding of coupled line fundamentals, explaining their applications in designing microwave and millimeter-wave components used in today's communications, microwave, and radar systems. The Second Edition includes a wealth of new material, particularly relating to applications. You find brand new discussions on a novel simple design technique for multilayer coupled circuits, high pass filters using coupled lines, software packages used for filter des

  19. Small circuits for cryptography.

    Energy Technology Data Exchange (ETDEWEB)

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  20. Silicon integrated circuit process

    International Nuclear Information System (INIS)

    Lee, Jong Duck

    1985-12-01

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  1. Primer printed circuit boards

    CERN Document Server

    Argyle, Andrew

    2009-01-01

    Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

  2. Silicon integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Jong Duck

    1985-12-15

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  3. Electronic circuits fundamentals & applications

    CERN Document Server

    Tooley, Mike

    2015-01-01

    Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

  4. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001

    Energy Technology Data Exchange (ETDEWEB)

    Beetz, C.P.; Steinbeck, J.; Hsueh, K.L.

    2001-03-31

    The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.

  5. Unstable oscillators based hyperchaotic circuit

    DEFF Research Database (Denmark)

    Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

    1999-01-01

    A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

  6. An integrated circuit switch

    Science.gov (United States)

    Bonin, E. L.

    1969-01-01

    Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

  7. Automatic sweep circuit

    International Nuclear Information System (INIS)

    Keefe, D.J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input is described. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found

  8. Automatic sweep circuit

    Science.gov (United States)

    Keefe, Donald J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  9. "Printed-circuit" rectenna

    Science.gov (United States)

    Dickinson, R. M.

    1977-01-01

    Rectifying antenna is less bulky structure for absorbing transmitted microwave power and converting it into electrical current. Printed-circuit approach, using microstrip technology and circularly polarized antenna, makes polarization orientation unimportant and allows much smaller arrays for given performance. Innovation is particularly useful with proposed electric vehicles powered by beam microwaves.

  10. Het onzichtbare circuit

    NARCIS (Netherlands)

    Nauta, Bram

    2013-01-01

    De chip, of geïntegreerde schakeling, heeft in een razend tempo ons leven ingrijpend veranderd. Het lijkt zo vanzelfsprekend dat er weer een nieuwe generatie smartphones, tablets of computers is. Maar dat is het niet. Prof.dr.ir. Bram Nauta, hoogleraar Integrated Circuit Design, laat in zijn rede

  11. Voltage regulating circuit

    NARCIS (Netherlands)

    2005-01-01

    A voltage regulating circuit comprising a rectifier (2) for receiving an AC voltage (Vmains) and for generating a rectified AC voltage (vrec), and a capacitor (3) connected in parallel with said rectified AC voltage for providing a DC voltage (VDC) over a load (5), characterized by a unidirectional

  12. Streaming Reduction Circuit

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert

    2009-01-01

    Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths

  13. A Magnetic Circuit Demonstration.

    Science.gov (United States)

    Vanderkooy, John; Lowe, June

    1995-01-01

    Presents a demonstration designed to illustrate Faraday's, Ampere's, and Lenz's laws and to reinforce the concepts through the analysis of a two-loop magnetic circuit. Can be made dramatic and challenging for sophisticated students but is suitable for an introductory course in electricity and magnetism. (JRH)

  14. Thermal measurement a requirement for monolithic microwave integrated circuit design

    OpenAIRE

    Hopper, Richard; Oxley, C. H.

    2008-01-01

    The thermal management of structures such as Monolithic Microwave Integrated Circuits (MMICs) is important, given increased circuit packing densities and RF output powers. The paper will describe the IR measurement technology necessary to obtain accurate temperature profiles on the surface of semiconductor devices. The measurement procedure will be explained, including the device mounting arrangement and emissivity correction technique. The paper will show how the measurement technique has be...

  15. Spike timing precision of neuronal circuits.

    Science.gov (United States)

    Kilinc, Deniz; Demir, Alper

    2018-04-17

    Spike timing is believed to be a key factor in sensory information encoding and computations performed by the neurons and neuronal circuits. However, the considerable noise and variability, arising from the inherently stochastic mechanisms that exist in the neurons and the synapses, degrade spike timing precision. Computational modeling can help decipher the mechanisms utilized by the neuronal circuits in order to regulate timing precision. In this paper, we utilize semi-analytical techniques, which were adapted from previously developed methods for electronic circuits, for the stochastic characterization of neuronal circuits. These techniques, which are orders of magnitude faster than traditional Monte Carlo type simulations, can be used to directly compute the spike timing jitter variance, power spectral densities, correlation functions, and other stochastic characterizations of neuronal circuit operation. We consider three distinct neuronal circuit motifs: Feedback inhibition, synaptic integration, and synaptic coupling. First, we show that both the spike timing precision and the energy efficiency of a spiking neuron are improved with feedback inhibition. We unveil the underlying mechanism through which this is achieved. Then, we demonstrate that a neuron can improve on the timing precision of its synaptic inputs, coming from multiple sources, via synaptic integration: The phase of the output spikes of the integrator neuron has the same variance as that of the sample average of the phases of its inputs. Finally, we reveal that weak synaptic coupling among neurons, in a fully connected network, enables them to behave like a single neuron with a larger membrane area, resulting in an improvement in the timing precision through cooperation.

  16. Communication and Sensing Circuits on Cellulose

    Directory of Open Access Journals (Sweden)

    Federico Alimenti

    2015-06-01

    Full Text Available This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT era.

  17. Millimicrosecond pulse techniques

    CERN Document Server

    Lewis, Ian A D

    1959-01-01

    Millimicrosecond Pulse Techniques, Second Edition focuses on millimicrosecond pulse techniques and the development of devices of large bandwidth, extending down to comparatively low frequencies (1 Mc/s). Emphasis is on basic circuit elements and pieces of equipment of universal application. Specific applications, mostly in the field of nuclear physics instrumentation, are considered. This book consists of eight chapters and opens with an introduction to some of the terminology employed by circuit engineers as well as theoretical concepts, including the laws of circuit analysis, Fourier analysi

  18. Micromachined integrated quantum circuit containing a superconducting qubit

    Science.gov (United States)

    Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

    We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

  19. SEM-based characterization techniques

    International Nuclear Information System (INIS)

    Russell, P.E.

    1986-01-01

    The scanning electron microscope is now a common instrument in materials characterization laboratories. The basic role of the SEM as a topographic imaging system has steadily been expanding to include a variety of SEM-based analytical techniques. These techniques cover the range of basic semiconductor materials characterization to live-time device characterization of operating LSI or VLSI devices. This paper introduces many of the more commonly used techniques, describes the modifications or additions to a conventional SEM required to utilize the techniques, and gives examples of the use of such techniques. First, the types of signals available from a sample being irradiated by an electron beam are reviewed. Then, where applicable, the type of spectroscopy or microscopy which has evolved to utilize the various signal types are described. This is followed by specific examples of the use of such techniques to solve problems related to semiconductor technology. Techniques emphasized include: x-ray fluorescence spectroscopy, electron beam induced current (EBIC), stroboscopic voltage analysis, cathodoluminescnece and electron beam IC metrology. Current and future trends of some of the these techniques, as related to the semiconductor industry are discussed

  20. The LMT circuit and SPICE

    DEFF Research Database (Denmark)

    Lindberg, Erik; Murali, K.; Tamacevicius, Arunas

    2006-01-01

    The state equations of the LMT circuit are modeled as a dedicated analogue computer circuit and solved by means of PSpice. The nonlinear part of the system is studied. Problems with the PSpice program are presented....

  1. Resistor Combinations for Parallel Circuits.

    Science.gov (United States)

    McTernan, James P.

    1978-01-01

    To help simplify both teaching and learning of parallel circuits, a high school electricity/electronics teacher presents and illustrates the use of tables of values for parallel resistive circuits in which total resistances are whole numbers. (MF)

  2. Detecting short circuits during assembly

    Science.gov (United States)

    Deboo, G. J.

    1980-01-01

    Detector circuit identifies shorts between bus bars of electronic equipment being wired. Detector sounds alarm and indicates which planes are shorted. Power and ground bus bars are scanned continuously until short circuit occurs.

  3. BR-5 primary circuit decontamination

    International Nuclear Information System (INIS)

    Efimov, I.A.; Nikulin, M.P.; Smirnov-Averin, A.P.; Tymosh, B.S.; Shereshkov, V.S.

    1976-01-01

    Results and methodology of steam-water and acid decontamination of the primary coolant circuit SBR-5 reactor in 1971 are discussed. Regeneration process in a cold trap of the primary coolant circuit is discussed

  4. MOS voltage automatic tuning circuit

    OpenAIRE

    李, 田茂; 中田, 辰則; 松本, 寛樹

    2004-01-01

    Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

  5. Behavioral synthesis of asynchronous circuits

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard

    2005-01-01

    This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

  6. Selected collection of circuit drawings

    International Nuclear Information System (INIS)

    1977-01-01

    The many electronics circuits have been constracted in the Electronics Shop for use in nuclear experiments or other purposes of this Institute. The types of these circuits amount to about 500 items in total since 1968. This report describes the electronics circuit diagrams selected from this collection. The circuit details are not presented in this report, because these are already been published in the other technical reports. (auth.)

  7. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  8. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  9. Safety of steel vessel Magnox pressure circuits

    International Nuclear Information System (INIS)

    Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

    1991-01-01

    The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

  10. Analysis of Bernstein's factorization circuit

    NARCIS (Netherlands)

    Lenstra, A.K.; Shamir, A.; Tomlinson, J.; Tromer, E.; Zheng, Y.

    2002-01-01

    In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue

  11. High voltage MOSFET switching circuit

    Science.gov (United States)

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  12. Integrated circuit structure

    International Nuclear Information System (INIS)

    1981-01-01

    The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

  13. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  14. Integrated coincidence circuits

    International Nuclear Information System (INIS)

    Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

    1976-01-01

    The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

  15. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  16. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  17. Interface Circuit For Printer Port

    Science.gov (United States)

    Tucker, Jerry H.; Yadlowsky, Ann B.

    1991-01-01

    Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

  18. Changes to the shuttle circuits

    CERN Multimedia

    GS Department

    2011-01-01

    To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

  19. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  20. High-frequency analog integrated circuit design

    CERN Document Server

    1995-01-01

    To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

  1. Nonlinear analysis of ring oscillator circuits

    KAUST Repository

    Ge, Xiaoqing

    2010-06-01

    Using nonlinear systems techniques, we analyze the stability properties and synchronization conditions for ring oscillator circuits, which are essential building blocks in digital systems. By making use of its cyclic structure, we investigate local and global stability properties of an n-stage ring oscillator. We present a sufficient condition for global asymptotic stability of the origin and obtain necessity if the ring oscillator consists of identical inverter elements. We then give a synchronization condition for identical interconnected ring oscillators.

  2. Micro-circuits for high energy physics

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1978-01-01

    Microprogramming is an inherently elegant method for implementing many digital systems. It is a mixture of hardware and software techniques with the logic subsystems controlled by 'instructions' stored in a memory. In the past, designing microprogrammed systems was difficult, tedious, and expensive because the available components were capable of only limited number of functions. Today, however, large blocks of microprogrammed systems have been incorporated into a single integrated circuit, thus microprogramming has become a simple, practical method. (Auth.)

  3. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  4. Nonlinear analysis of ring oscillator circuits

    KAUST Repository

    Ge, Xiaoqing; Arcak, Murat; Salama, Khaled N.

    2010-01-01

    Using nonlinear systems techniques, we analyze the stability properties and synchronization conditions for ring oscillator circuits, which are essential building blocks in digital systems. By making use of its cyclic structure, we investigate local and global stability properties of an n-stage ring oscillator. We present a sufficient condition for global asymptotic stability of the origin and obtain necessity if the ring oscillator consists of identical inverter elements. We then give a synchronization condition for identical interconnected ring oscillators.

  5. Dynamic pulse difference circuit

    International Nuclear Information System (INIS)

    Erickson, G.L.

    1978-01-01

    A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry is disclosed which comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter

  6. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2007-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set

  7. Electric circuits problem solver

    CERN Document Server

    REA, Editors of

    2012-01-01

    Each Problem Solver is an insightful and essential study and solution guide chock-full of clear, concise problem-solving gems. All your questions can be found in one convenient source from one of the most trusted names in reference solution guides. More useful, more practical, and more informative, these study aids are the best review books and textbook companions available. Nothing remotely as comprehensive or as helpful exists in their subject anywhere. Perfect for undergraduate and graduate studies.Here in this highly useful reference is the finest overview of electric circuits currently av

  8. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  9. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  10. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  11. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  12. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  13. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  14. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  15. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2011-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea

  16. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    1999-01-01

    This manual is a useful single-volume guide specifically aimed at the practical design engineer, technician, and experimenter, as well as the electronics student and amateur. It deals with the subject in an easy to read, down to earth, and non-mathematical yet comprehensive manner, explaining the basic principles and characteristics of the best known devices, and presenting the reader with many practical applications and over 200 circuits. Most of the ICs and other devices used are inexpensive and readily available types, with universally recognised type numbers.The second edition

  17. Optically controllable molecular logic circuits

    International Nuclear Information System (INIS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-01-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

  18. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  19. Conductus makes high-Tc integrated circuit

    International Nuclear Information System (INIS)

    Anon.

    1991-01-01

    This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step

  20. Simple Cell Balance Circuit

    Science.gov (United States)

    Johnson, Steven D.; Byers, Jerry W.; Martin, James A.

    2012-01-01

    A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.

  1. Quantum-Circuit Refrigerator

    Science.gov (United States)

    MöTtöNen, Mikko; Tan, Kuan Y.; Masuda, Shumpei; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Silveri, Matti; Grabert, Hermann

    Quantum technology holds great potential in providing revolutionizing practical applications. However, fast and precise cooling of the functional quantum degrees of freedom on demand remains a major challenge in many solid-state implementations, such as superconducting circuits. We demonstrate direct cooling of a superconducting resonator mode using voltage-controllable quantum tunneling of electrons in a nanoscale refrigerator. In our first experiments on this type of a quantum-circuit refrigerator, we measure the drop in the mode temperature by electron thermometry at a resistor which is coupled to the resonator mode through ohmic losses. To eliminate unwanted dissipation, we remove the probe resistor and directly observe the power spectrum of the resonator output in agreement with the so-called P(E) theory. We also demonstrate in microwave reflection experiments that the internal quality factor of the resonator can be tuned by orders of magnitude. In the future, our refrigerator can be integrated with different quantum electric devices, potentially enhancing their performance. For example, it may prove useful in the initialization of superconducting quantum bits and in dissipation-assisted quantum annealing. We acknowledge European Research Council Grant SINGLEOUT (278117) and QUESS (681311) for funding.

  2. Quasi-Linear Circuit

    Science.gov (United States)

    Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth

    2013-01-01

    This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

  3. Entangled Coherent States Generation in two Superconducting LC Circuits

    International Nuclear Information System (INIS)

    Chen Meiyu; Zhang Weimin

    2008-01-01

    We proposed a novel pure electronic (solid state) device consisting of two superconducting LC circuits coupled to a superconducting flux qubit. The entangled coherent states of the two LC modes is generated through the measurement of the flux qubit states. The interaction of the flux qubit and two LC circuits is controlled by the external microwave control lines. The geometrical structure of the LC circuits is adjustable and makes a strong coupling between them achievable. This entangled coherent state generator can be realized by using the conventional microelectronic fabrication techniques which increases the feasibility of the experiment.

  4. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  5. High voltage generator circuit with low power and high efficiency applied in EEPROM

    International Nuclear Information System (INIS)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

  6. The VLSI design of the sub-band filterbank in MP3 decoding

    Science.gov (United States)

    Liu, Jia-Xin; Luo, Li

    2018-03-01

    The sub-band filterbank is one of the most important modules which has the largest amount of calculation in MP3 decoding. In order to save CPU resources and integrate the sub-band filterbank part into MP3 IP core, the hardware circuit of the sub-band filterbank module is designed in this paper. A fast algorithm suit for hardware implementation is proposed and achieved on FPGA development board. The results show that the sub-band filterbank function is correct in the case of using very few registers and the amount of calculation and ROM resources are reduced greatly.

  7. Reliability data collection on IC and VLSI devices tested under accelerated life conditions

    International Nuclear Information System (INIS)

    Barry, D.M.; Meniconi, M.

    1986-01-01

    As part of a more general investigation into the reliability and failure causes of semiconductor devices, statistical samples of integrated circuit devices (LM741C) and dynamic random access memory devices (TMS4116) were tested destructively to failure using elevated temperature as the accelerating stress. The devices were operated during the life test and the failure data generated were collected automatically using a multiple question-and-answer program and a process control computer. The failure data were modelled from the lognormal, inverse Gaussian and Weibull distribution using an Arrhenius reaction rate model. The failed devices were later decapsulated for failure cause determination. (orig./DG)

  8. Integrated circuit cooled turbine blade

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  9. Control circuit for transformer relay

    International Nuclear Information System (INIS)

    Wyatt, G.A.

    1984-01-01

    A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

  10. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    Science.gov (United States)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  11. The Solenarc circuit-breaker of high performance level

    International Nuclear Information System (INIS)

    Lehmann, J.M.

    1983-01-01

    After recalling the breaking principle involved in MV circuit-breakers manufactured by Merlin Gerin, it is showed how Solenarc technique enables specific problems to be solved that are set by the equipment of Eurodif plant at Tricastin and that represent constraints similar to those encountered with protective equipment for power station auxiliaries (high rated currents, long duration overloads, very high short-circuit currents, current breaks without natural passage through zero, etc.) [fr

  12. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    Science.gov (United States)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  13. Source-circuit design overview

    Science.gov (United States)

    Ross, R. G., Jr.

    1983-01-01

    The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

  14. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

  15. Four-junction superconducting circuit

    Science.gov (United States)

    Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

    2016-01-01

    We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

  16. VLSI implementation of a bio-inspired olfactory spiking neural network.

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2012-07-01

    This paper presents a low-power, neuromorphic spiking neural network (SNN) chip that can be integrated in an electronic nose system to classify odor. The proposed SNN takes advantage of sub-threshold oscillation and onset-latency representation to reduce power consumption and chip area, providing a more distinct output for each odor input. The synaptic weights between the mitral and cortical cells are modified according to an spike-timing-dependent plasticity learning rule. During the experiment, the odor data are sampled by a commercial electronic nose (Cyranose 320) and are normalized before training and testing to ensure that the classification result is only caused by learning. Measurement results show that the circuit only consumed an average power of approximately 3.6 μW with a 1-V power supply to discriminate odor data. The SNN has either a high or low output response for a given input odor, making it easy to determine whether the circuit has made the correct decision. The measurement result of the SNN chip and some well-known algorithms (support vector machine and the K-nearest neighbor program) is compared to demonstrate the classification performance of the proposed SNN chip.The mean testing accuracy is 87.59% for the data used in this paper.

  17. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

    Science.gov (United States)

    Indiveri, Giacomo

    2008-09-03

    Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  18. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

    Directory of Open Access Journals (Sweden)

    Giacomo Indiveri

    2008-09-01

    Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  19. Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

    Science.gov (United States)

    Wang, Tian; Cui, Xiaoxin; Ni, Yewen; Liao, Kai; Liao, Nan; Yu, Dunshan; Cui, Xiaole

    2017-04-01

    With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability. Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

  20. Basic electronic circuits

    CERN Document Server

    Buckley, P M

    1980-01-01

    In the past, the teaching of electricity and electronics has more often than not been carried out from a theoretical and often highly academic standpoint. Fundamentals and basic concepts have often been presented with no indication of their practical appli­ cations, and all too frequently they have been illustrated by artificially contrived laboratory experiments bearing little relationship to the outside world. The course comes in the form of fourteen fairly open-ended constructional experiments or projects. Each experiment has associated with it a construction exercise and an explanation. The basic idea behind this dual presentation is that the student can embark on each circuit following only the briefest possible instructions and that an open-ended approach is thereby not prejudiced by an initial lengthy encounter with the theory behind the project; this being a sure way to dampen enthusiasm at the outset. As the investigation progresses, questions inevitably arise. Descriptions of the phenomena encounte...