WorldWideScience

Sample records for vlsi cad algorithms

  1. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  2. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  3. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  4. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  5. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  6. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  7. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  8. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  9. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  10. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  11. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  12. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  13. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  14. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  15. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  16. Designing algorithms using CAD technologies

    Directory of Open Access Journals (Sweden)

    Alin IORDACHE

    2008-01-01

    Full Text Available A representative example of eLearning-platform modular application, ‘Logical diagrams’, is intended to be a useful learning and testing tool for the beginner programmer, but also for the more experienced one. The problem this application is trying to solve concerns young programmers who forget about the fundamentals of this domain, algorithmic. Logical diagrams are a graphic representation of an algorithm, which uses different geometrical figures (parallelograms, rectangles, rhombuses, circles with particular meaning that are called blocks and connected between them to reveal the flow of the algorithm. The role of this application is to help the user build the diagram for the algorithm and then automatically generate the C code and test it.

  17. Efficient FM Algorithm for VLSI Circuit Partitioning

    Directory of Open Access Journals (Sweden)

    M.RAJESH

    2013-04-01

    Full Text Available In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if theinitial partitioning matrix is close to the final partitioning then the computation time (iteration required is small . Here we have proposed novel approach to arrive at initial partitioning by using spectralfactorization method the results was verified using several circuits.

  18. A bioinspired collision detection algorithm for VLSI implementation

    Science.gov (United States)

    Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.

    2005-06-01

    In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

  19. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  20. High performance genetic algorithm for VLSI circuit partitioning

    Science.gov (United States)

    Dinu, Simona

    2016-12-01

    Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.

  1. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  2. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  3. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  4. VLSI chip-set for data compression using the Rice algorithm

    Science.gov (United States)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  5. Beyond-Binary Arithmetic: Algorithms and VLSI Implementations

    OpenAIRE

    Aoki, Takafumi; Higuchi, Tatsuo

    2000-01-01

    Beyond-binary arithmetic algorithms are defined as a new class of computer arithmetic algorithms which employ non-binary data representations to achieve higher performances beyond those of conventional binary algorithms. This paper presents prominent examples of beyond-binary arithmetic algorithms: examples include (i) a high-radix redundant division algorithm without using lookup tables, (ii) a high-radix redundant CORDIC algorithm for fast vector rotation, and (iii) redundant complex arithm...

  6. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  7. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  8. A VLSI optimal constructive algorithm for classification problems

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V. [Los Alamos National Lab., NM (United States); Draghici, S.; Sethi, I.K. [Wayne State Univ., Detroit, MI (United States)

    1997-10-01

    If neural networks are to be used on a large scale, they have to be implemented in hardware. However, the cost of the hardware implementation is critically sensitive to factors like the precision used for the weights, the total number of bits of information and the maximum fan-in used in the network. This paper presents a version of the Constraint Based Decomposition training algorithm which is able to produce networks using limited precision integer weights and units with limited fan-in. The algorithm is tested on the 2-spiral problem and the results are compared with other existing algorithms.

  9. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  10. New Metric Based Algorithm for Test Vector Generation in VLSI Testing

    Directory of Open Access Journals (Sweden)

    M. V. Atre

    1995-07-01

    Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.

  11. Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.

    Science.gov (United States)

    1984-10-01

    analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI

  12. Automated lung segmentation algorithm for CAD system of thoracic CT

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Objective: To design and test the accuracy and efficiency of our lung segmentation algorithm on thoracic CT image in computer-aided diagnostic (CAD) system, especially on the segmentation between left and right lungs. Methods: We put forward the base frame of our lung segmentation firstly. Then, using optimal thresholding and mathematical morphologic methods, we acquired the rough image of lung segmentation. Finally, we presented a fast self-fit segmentation refinement algorithm, adapting to the unsuccessful left-right lung segmentation of thredsholding. Then our algorithm was used to CT scan images of 30 patients and the results were compared with those made by experts. Results: Experiments on clinical 2-D pulmonary images showed the results of our algorithm were very close to the expert's manual outlines, and it was very effective for the separation of left and right lungs with a successful segmentation ratio 94.8%. Conclusion: It is a practicable fast lung segmentation algorithm for CAD system on thoracic CT image.

  13. A DRAM compiler algorithm for high performance VLSI embedded memories

    Science.gov (United States)

    Eldin, A. G.

    1992-01-01

    In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

  14. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

  15. Target Impact Detection Algorithm Using Computer-aided Design (CAD) Model Geometry

    Science.gov (United States)

    2014-09-01

    UNCLASSIFIED AD-E403 558 Technical Report ARMET-TR-13024 TARGET IMPACT DETECTION ALGORITHM USING COMPUTER-AIDED DESIGN ( CAD ...DETECTION ALGORITHM USING COMPUTER-AIDED DESIGN ( CAD ) MODEL GEOMETRY 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6...This report documents a method and algorithm to export geometry from a three-dimensional, computer-aided design ( CAD ) model in a format that can be

  16. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  17. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  18. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  19. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  20. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  1. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  2. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  3. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  4. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  5. Development of CAD implementing the algorithm of boundary elements’ numerical analytical method

    Directory of Open Access Journals (Sweden)

    Yulia V. Korniyenko

    2015-03-01

    Full Text Available Up to recent days the algorithms for numerical-analytical boundary elements method had been implemented with programs written in MATLAB environment language. Each program had a local character, i.e. used to solve a particular problem: calculation of beam, frame, arch, etc. Constructing matrices in these programs was carried out “manually” therefore being time-consuming. The research was purposed onto a reasoned choice of programming language for new CAD development, allows to implement algorithm of numerical analytical boundary elements method and to create visualization tools for initial objects and calculation results. Research conducted shows that among wide variety of programming languages the most efficient one for CAD development, employing the numerical analytical boundary elements method algorithm, is the Java language. This language provides tools not only for development of calculating CAD part, but also to build the graphic interface for geometrical models construction and calculated results interpretation.

  6. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  7. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  8. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  9. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  10. On flexible CAD of adaptive control and identification algorithms

    DEFF Research Database (Denmark)

    Christensen, Anders; Ravn, Ole

    1988-01-01

    SLLAB is a MATLAB-family software package for solving control and identification problems. This paper concerns the planning of a general-purpose subroutine structure for solving identification and adaptive control problems. A general-purpose identification algorithm is suggested, which allows...... a total redesign of the system within each sample. The necessary design parameters are evaluated and a decision vector is defined, from which the identification algorithm can be generated by the program. Using the decision vector, a decision-node tree structure is built up, where the nodes define...

  11. On flexible CAD of adaptive control and identification algorithms

    DEFF Research Database (Denmark)

    Christensen, Anders; Ravn, Ole

    1988-01-01

    SLLAB is a MATLAB-family software package for solving control and identification problems. This paper concerns the planning of a general-purpose subroutine structure for solving identification and adaptive control problems. A general-purpose identification algorithm is suggested, which allows a t...

  12. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  13. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  14. A unified approach to VLSI layout automation and algorithm mapping on processor arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.

    1993-01-01

    Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.

  15. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  16. Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Farouk Smith

    2015-07-01

    Full Text Available This paper propose a Virtual-Field Programmable Gate Array (V-FPGA architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA; and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm; applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

  17. Analysis and compensation of the effects of analog VLSI arithmetic on the LMS algorithm.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel; Sbarbaro, Daniel; Valenzuela, Waldo

    2011-07-01

    Analog very large scale integration implementations of neural networks can compute using a fraction of the size and power required by their digital counterparts. However, intrinsic limitations of analog hardware, such as device mismatch, charge leakage, and noise, reduce the accuracy of analog arithmetic circuits, degrading the performance of large-scale adaptive systems. In this paper, we present a detailed mathematical analysis that relates different parameters of the hardware limitations to specific effects on the convergence properties of linear perceptrons trained with the least-mean-square (LMS) algorithm. Using this analysis, we derive design guidelines and introduce simple on-chip calibration techniques to improve the accuracy of analog neural networks with a small cost in die area and power dissipation. We validate our analysis by evaluating the performance of a mixed-signal complementary metal-oxide-semiconductor implementation of a 32-input perceptron trained with LMS.

  18. An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

    Directory of Open Access Journals (Sweden)

    Tze-Yun Sung

    2010-01-01

    Full Text Available Discrete Cosine transform (DCT and inverse DCT (IDCT have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array and SoC (system on chip. The linear-array DCT/IDCT processor with the computation complexity O(5N/8 and hardware complexity O(5N/8 is fully pipelined and scalable for variable-length DCT/IDCT computations.

  19. VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

    Science.gov (United States)

    Satheeskumaran, S.; Sabrigiriraj, M.

    2016-06-01

    Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.

  20. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  1. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  2. Effect of different reconstruction algorithms on computer-aided diagnosis (CAD) performance in ultra-low dose CT colonography

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Eun Sun [Department of Radiology, Seoul National University Hospital (Korea, Republic of); Institute of Radiation Medicine, Seoul National University Hospital (Korea, Republic of); Kim, Se Hyung, E-mail: shkim7071@gmail.com [Department of Radiology, Seoul National University Hospital (Korea, Republic of); Institute of Radiation Medicine, Seoul National University Hospital (Korea, Republic of); Im, Jong Pil; Kim, Sang Gyun [Department of Internal Medicine, Seoul National University Hospital (Korea, Republic of); Shin, Cheong-il; Han, Joon Koo; Choi, Byung Ihn [Department of Radiology, Seoul National University Hospital (Korea, Republic of); Institute of Radiation Medicine, Seoul National University Hospital (Korea, Republic of)

    2015-04-15

    Highlights: •We assessed the effect of reconstruction algorithms on CAD in ultra-low dose CTC. •30 patients underwent ultra-low dose CTC using 120 and 100 kVp with 10 mAs. •CT was reconstructed with FBP, ASiR and Veo and then, we applied a CAD system. •Per-polyp sensitivity of CAD in ULD CT can be improved with the IR algorithms. •Despite of an increase in the number of FPs with IR, it was still acceptable. -- Abstract: Purpose: To assess the effect of different reconstruction algorithms on computer-aided diagnosis (CAD) performance in ultra-low-dose CT colonography (ULD CTC). Materials and methods: IRB approval and informed consents were obtained. Thirty prospectively enrolled patients underwent non-contrast CTC at 120 kVp/10 mAs in supine and 100 kVp/10 mAs in prone positions, followed by same-day colonoscopy. Images were reconstructed with filtered back projection (FBP), 80% adaptive statistical iterative reconstruction (ASIR80), and model-based iterative reconstruction (MBIR). A commercial CAD system was applied and per-polyp sensitivities and numbers of false-positives (FPs) were compared among algorithms. Results: Mean effective radiation dose of CTC was 1.02 mSv. Of 101 polyps detected and removed by colonoscopy, 61 polyps were detected on supine and on prone CTC datasets on consensus unblinded review, resulting in 122 visible polyps (32 polyps <6 mm, 52 6–9.9 mm, and 38 ≥ 10 mm). Per-polyp sensitivity of CAD for all polyps was highest with MBIR (56/122, 45.9%), followed by ASIR80 (54/122, 44.3%) and FBP (43/122, 35.2%), with significant differences between FBP and IR algorithms (P < 0.017). Per-polyp sensitivity for polyps ≥ 10 mm was also higher with MBIR (25/38, 65.8%) and ASIR80 (24/38, 63.2%) than with FBP (20/38, 58.8%), albeit without statistical significance (P > 0.017). Mean number of FPs was significantly different among algorithms (FBP, 1.4; ASIR, 2.1; MBIR, 2.4) (P = 0.011). Conclusion: Although the performance of stand-alone CAD

  3. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  4. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  5. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  6. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  7. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  8. VLSI Research

    Science.gov (United States)

    1984-04-01

    massive amounts of data pertaining to seismic exploration or weather observation require much more processing power. These scientific calculations...1« IC *• Number of Processors it 3* (a) 5g - *• * C > «i o •• u w »- a • c a. MM , / \\ i i T2C sp«r*ttoni •*l«y > M unit...algorithms can be divided into two categories; namely, single-input single-output (SISO) and multi-input multi- output ( MIMO ) systems. A highly

  9. Impact of image normalization and quantization on the performance of sonar computer-aided detection/computer-aided classification (CAD/CAC) algorithms

    Science.gov (United States)

    Ciany, Charles M.; Zurawski, William C.

    2007-04-01

    Raytheon has extensively processed high-resolution sonar images with its CAD/CAC algorithms to provide real-time classification of mine-like bottom objects in a wide range of shallow-water environments. The algorithm performance is measured in terms of probability of correct classification (Pcc) as a function of false alarm rate, and is impacted by variables associated with both the physics of the problem and the signal processing design choices. Some examples of prominent variables pertaining to the choices of signal processing parameters are image resolution (i.e., pixel dimensions), image normalization scheme, and pixel intensity quantization level (i.e., number of bits used to represent the intensity of each image pixel). Improvements in image resolution associated with the technology transition from sidescan to synthetic aperture sonars have prompted the use of image decimation algorithms to reduce the number of pixels per image that are processed by the CAD/CAC algorithms, in order to meet real-time processor throughput requirements. Additional improvements in digital signal processing hardware have also facilitated the use of an increased quantization level in converting the image data from analog to digital format. This study evaluates modifications to the normalization algorithm and image pixel quantization level within the image processing prior to CAD/CAC processing, and examines their impact on the resulting CAD/CAC algorithm performance. The study utilizes a set of at-sea data from multiple test exercises in varying shallow water environments.

  10. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  11. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  12. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  13. Effects of Iterative Reconstruction Algorithms on Computer-assisted Detection (CAD) Software for Lung Nodules in Ultra-low-dose CT for Lung Cancer Screening.

    Science.gov (United States)

    Nomura, Yukihiro; Higaki, Toru; Fujita, Masayo; Miki, Soichiro; Awaya, Yoshikazu; Nakanishi, Toshio; Yoshikawa, Takeharu; Hayashi, Naoto; Awai, Kazuo

    2017-02-01

    This study aimed to evaluate the effects of iterative reconstruction (IR) algorithms on computer-assisted detection (CAD) software for lung nodules in ultra-low-dose computed tomography (ULD-CT) for lung cancer screening. We selected 85 subjects who underwent both a low-dose CT (LD-CT) scan and an additional ULD-CT scan in our lung cancer screening program for high-risk populations. The LD-CT scans were reconstructed with filtered back projection (FBP; LD-FBP). The ULD-CT scans were reconstructed with FBP (ULD-FBP), adaptive iterative dose reduction 3D (AIDR 3D; ULD-AIDR 3D), and forward projected model-based IR solution (FIRST; ULD-FIRST). CAD software for lung nodules was applied to each image dataset, and the performance of the CAD software was compared among the different IR algorithms. The mean volume CT dose indexes were 3.02 mGy (LD-CT) and 0.30 mGy (ULD-CT). For overall nodules, the sensitivities of CAD software at 3.0 false positives per case were 78.7% (LD-FBP), 9.3% (ULD-FBP), 69.4% (ULD-AIDR 3D), and 77.8% (ULD-FIRST). Statistical analysis showed that the sensitivities of ULD-AIDR 3D and ULD-FIRST were significantly higher than that of ULD-FBP (P CAD software in ULD-CT was improved by using IR algorithms. In particular, the performance of CAD in ULD-FIRST was almost equivalent to that in LD-FBP. Copyright © 2017 The Association of University Radiologists. Published by Elsevier Inc. All rights reserved.

  14. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  15. Multi-site evaluation of a computer aided detection (CAD) algorithm for small acute intra-cranial hemorrhage and development of a stand-alone CAD system ready for deployment in a clinical environment

    Science.gov (United States)

    Deshpande, Ruchi R.; Fernandez, James; Lee, Joon K.; Chan, Tao; Liu, Brent J.; Huang, H. K.

    2010-03-01

    Timely detection of Acute Intra-cranial Hemorrhage (AIH) in an emergency environment is essential for the triage of patients suffering from Traumatic Brain Injury. Moreover, the small size of lesions and lack of experience on the reader's part could lead to difficulties in the detection of AIH. A CT based CAD algorithm for the detection of AIH has been developed in order to improve upon the current standard of identification and treatment of AIH. A retrospective analysis of the algorithm has already been carried out with 135 AIH CT studies with 135 matched normal head CT studies from the Los Angeles County General Hospital/ University of Southern California Hospital System (LAC/USC). In the next step, AIH studies have been collected from Walter Reed Army Medical Center, and are currently being processed using the AIH CAD system as part of implementing a multi-site assessment and evaluation of the performance of the algorithm. The sensitivity and specificity numbers from the Walter Reed study will be compared with the numbers from the LAC/USC study to determine if there are differences in the presentation and detection due to the difference in the nature of trauma between the two sites. Simultaneously, a stand-alone system with a user friendly GUI has been developed to facilitate implementation in a clinical setting.

  16. From Nonlinear Optimization to Convex Optimization through Firefly Algorithm and Indirect Approach with Applications to CAD/CAM

    Directory of Open Access Journals (Sweden)

    Akemi Gálvez

    2013-01-01

    Full Text Available Fitting spline curves to data points is a very important issue in many applied fields. It is also challenging, because these curves typically depend on many continuous variables in a highly interrelated nonlinear way. In general, it is not possible to compute these parameters analytically, so the problem is formulated as a continuous nonlinear optimization problem, for which traditional optimization techniques usually fail. This paper presents a new bioinspired method to tackle this issue. In this method, optimization is performed through a combination of two techniques. Firstly, we apply the indirect approach to the knots, in which they are not initially the subject of optimization but precomputed with a coarse approximation scheme. Secondly, a powerful bioinspired metaheuristic technique, the firefly algorithm, is applied to optimization of data parameterization; then, the knot vector is refined by using De Boor’s method, thus yielding a better approximation to the optimal knot vector. This scheme converts the original nonlinear continuous optimization problem into a convex optimization problem, solved by singular value decomposition. Our method is applied to some illustrative real-world examples from the CAD/CAM field. Our experimental results show that the proposed scheme can solve the original continuous nonlinear optimization problem very efficiently.

  17. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  18. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  19. TU-G-204-09: The Effects of Reduced- Dose Lung Cancer Screening CT On Lung Nodule Detection Using a CAD Algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Young, S; Lo, P; Kim, G; Hsu, W; Hoffman, J; Brown, M; McNitt-Gray, M [UCLA School of Medicine, Los Angeles, CA (United States)

    2015-06-15

    Purpose: While Lung Cancer Screening CT is being performed at low doses, the purpose of this study was to investigate the effects of further reducing dose on the performance of a CAD nodule-detection algorithm. Methods: We selected 50 cases from our local database of National Lung Screening Trial (NLST) patients for which we had both the image series and the raw CT data from the original scans. All scans were acquired with fixed mAs (25 for standard-sized patients, 40 for large patients) on a 64-slice scanner (Sensation 64, Siemens Healthcare). All images were reconstructed with 1-mm slice thickness, B50 kernel. 10 of the cases had at least one nodule reported on the NLST reader forms. Based on a previously-published technique, we added noise to the raw data to simulate reduced-dose versions of each case at 50% and 25% of the original NLST dose (i.e. approximately 1.0 and 0.5 mGy CTDIvol). For each case at each dose level, the CAD detection algorithm was run and nodules greater than 4 mm in diameter were reported. These CAD results were compared to “truth”, defined as the approximate nodule centroids from the NLST reports. Subject-level mean sensitivities and false-positive rates were calculated for each dose level. Results: The mean sensitivities of the CAD algorithm were 35% at the original dose, 20% at 50% dose, and 42.5% at 25% dose. The false-positive rates, in decreasing-dose order, were 3.7, 2.9, and 10 per case. In certain cases, particularly in larger patients, there were severe photon-starvation artifacts, especially in the apical region due to the high-attenuating shoulders. Conclusion: The detection task was challenging for the CAD algorithm at all dose levels, including the original NLST dose. However, the false-positive rate at 25% dose approximately tripled, suggesting a loss of CAD robustness somewhere between 0.5 and 1.0 mGy. NCI grant U01 CA181156 (Quantitative Imaging Network); Tobacco Related Disease Research Project grant 22RT-0131.

  20. Application of Fisher fusion techniques to improve the individual performance of sonar computer-aided detection/computer-aided classification (CAD/CAC) algorithms

    Science.gov (United States)

    Ciany, Charles M.; Zurawski, William C.

    2009-05-01

    Raytheon has extensively processed high-resolution sidescan sonar images with its CAD/CAC algorithms to provide classification of targets in a variety of shallow underwater environments. The Raytheon CAD/CAC algorithm is based on non-linear image segmentation into highlight, shadow, and background regions, followed by extraction, association, and scoring of features from candidate highlight and shadow regions of interest (ROIs). The targets are classified by thresholding an overall classification score, which is formed by summing the individual feature scores. The algorithm performance is measured in terms of probability of correct classification as a function of false alarm rate, and is determined by both the choice of classification features and the manner in which the classifier rates and combines these features to form its overall score. In general, the algorithm performs very reliably against targets that exhibit "strong" highlight and shadow regions in the sonar image- i.e., both the highlight echo and its associated shadow region from the target are distinct relative to the ambient background. However, many real-world undersea environments can produce sonar images in which a significant percentage of the targets exhibit either "weak" highlight or shadow regions in the sonar image. The challenge of achieving robust performance in these environments has traditionally been addressed by modifying the individual feature scoring algorithms to optimize the separation between the corresponding highlight or shadow feature scores of targets and non-targets. This study examines an alternate approach that employs principles of Fisher fusion to determine a set of optimal weighting coefficients that are applied to the individual feature scores before summing to form the overall classification score. The results demonstrate improved performance of the CAD/CAC algorithm on at-sea data sets.

  1. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  2. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  3. 2-D DCT Algorithm and Its Reduced VLSI Design%二维DCT算法及其精简的VLSI设计

    Institute of Scientific and Technical Information of China (English)

    陈伟; 卢贵主; 郑灵翔

    2008-01-01

    采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.

  4. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  5. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  6. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  7. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  8. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  9. An Enhanced Hybrid Genetic Simulated Annealing Algorithm for VLSI Standard Cell Placement%VLSI标准单元布局问题的增强型混合遗传模拟退火算法

    Institute of Scientific and Technical Information of China (English)

    陈雄峰; 吴景岚; 朱文兴

    2014-01-01

    A hybrid genetic simulated annealing algorithm is presented for solving the problem of VLSI standard cell placement with up to millions of cells. Firstly, to make genetic algorithm be capable of handling very large scale of standard cell placement, the strategies of small size population, dynamic updating population, and crossover localization are adopted, and the global search and local search of genetic algorithm are coordinated. Then, by introducing hill climbing ( HC) and simulated annealing ( SA) into the framework of genetic algorithm and the internal procedure of its operators, an effective crossover operator named Net Cycle Crossover and local search algorithms for the placement problem are designed to further improve the evolutionary efficiency of the algorithm and the quality of its placement results. In the algorithm procedure, HC method and SA method focus on array placement and non-array placement respectively. The experimental results on Peko suite3, Peko suite4 and ISPD04 benchmark circuits show that the proposed algorithm can handle array and non-array placements with 10,000 ~1,600,000 cells and 10,000~210,000 cells respectively, and can effectively improve the quality of placement results in a reasonable running time.%提出有效处理百万个VLSI标准单元布局问题的混合遗传模拟退火算法。首先采用小规模种群、动态更新种群和交叉局部化策略,并协调全局与局部搜索,使遗传算法可处理超大规模标准单元布局问题。然后为进一步提高算法进化效率和布局结果质量,将爬山和模拟退火方法引入遗传算法框架及其算子内部流程,设计高效的线网-循环交叉算子和局部搜索算法。标准单元阵列布局侧重使用爬山法,非阵列布局侧重使用模拟退火方法。 Peko suite3、Peko suite4和ISPD04标准测试电路的实验结果表明,该算法可在合理运行时间内有效提高布局结果质量。

  10. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  11. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  12. Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

    Institute of Scientific and Technical Information of China (English)

    周涛; 吴行军; 白国强; 陈弘毅

    2003-01-01

    Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

  13. Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

    CERN Document Server

    Scheibler, Robin; Chebira, Amina

    2011-01-01

    We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.

  14. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  15. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  16. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  17. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  18. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  19. Protein: CAD [Trypanosomes Database

    Lifescience Database Archive (English)

    Full Text Available CAD carbamoyl-phosphate synthetase 2, aspartate transcarbamylase, and dihydroorotaseCAD trifunctional prot...eincarbamoylphosphate synthetase 2/aspartate transcarbamylase/dihydroorotasemultifunctional prot

  20. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  1. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  2. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  3. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  4. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  5. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  6. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  7. Flexible Concurrency Control for Legacy CAD to Construct Collaborative CAD Environment

    Science.gov (United States)

    Cai, Xiantao; Li, Xiaoxia; He, Fazhi; Han, Soonhung; Chen, Xiao

    Collaborative CAD (Co-CAD) systems can be constructed based on either 3D kernel or legacy stand-alone CAD systems, which are typically commercial CAD systems such as CATIA, Pro/E and so on. Most of synchronous Co-CAD systems, especially these based on legacy stand-alone CAD systems, adopt the lock mechanism or the floor control as concurrency controls which are very restrictive and stagnant. A flexible concurrency control method is proposed to support the flexible concurrency control in Co-CAD systems based on legacy stand-alone CAD systems. At first, a model of operation relationship is proposed with special consideration for the concurrency control of these kinds of Co-CAD system. Then two types of data structure, the Collaborative Feature Dependent Graph (Co-FDG) and the Collaborative Feature Operational List (Co-FOL), are presented as the cornerstone of flexible concurrency control. Next a Flexible Concurrency Control Algorithm (FCCA) is proposed. Finally a Selective Undo/Redo Algorithm is proposed which can improve the flexibility of Co-CAD furthermore.

  8. Statistics on VLSI Designs.

    Science.gov (United States)

    1980-04-17

    been given by Shamos [1978], Bentley and Ottmann [1979] and Bentley and Wood [1980], but they are very complex to code and fail to exploit many of...Research in Integrated Circuits, January, 1980. Bentley, J.L. and T. Ottmann [1979]. "Algorithms for reporting and counting geometric intersections," IEEE

  9. AutoCAD

    DEFF Research Database (Denmark)

    Jensen, Henrik

    1998-01-01

    I 1998 var AutoCAD Arkitektskolens basale CAD-tilbud til de studerende. Kursets vægt ligger på konstruktion og strukturering af 3d-modeller og med udgangspunkt i dette, 2d-tegning. Kurset er opbygget over CAD Clasic skabelonen (se min forskning). Kompendiet kan bruges til selvstudium.......I 1998 var AutoCAD Arkitektskolens basale CAD-tilbud til de studerende. Kursets vægt ligger på konstruktion og strukturering af 3d-modeller og med udgangspunkt i dette, 2d-tegning. Kurset er opbygget over CAD Clasic skabelonen (se min forskning). Kompendiet kan bruges til selvstudium....

  10. A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar

    Science.gov (United States)

    Fang, W.

    1994-01-01

    For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.

  11. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  12. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  13. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  14. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  15. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  16. Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2011-03-01

    Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.

  17. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  18. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  19. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  20. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  1. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  2. A Methodology for Mapping and Partitioning Arbitrary N—Dimensional Nested Loops into 2—Dimensional VLSI Arrays

    Institute of Scientific and Technical Information of China (English)

    刘弘; 王文红; 等

    1993-01-01

    A new methodology is proposed for mapping and partitioning arbitrary n-dimensional nested loop algorithms into 2-dimensional fixed size systolic arrays.Since planar VLSI arrays are easy to implement,our approach has good feasibility and applicability.In the transformation process of an algorithm,we take into account not only data dependencies imposed by the original algorithm but also space dependencies dictated by the algorithm ransformation,Thus,any VLSI algorithm generated by our methodology has optimal parallel execution time and yet remains space-time conflict free.Moreover,a theory of the least complete set of interconnection matrices is proposed to reduce the computational complexity for finding all possible space transformations for a given algorithm.

  3. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  4. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  5. Algorithmically specialized parallel computers

    CERN Document Server

    Snyder, Lawrence; Gannon, Dennis B

    1985-01-01

    Algorithmically Specialized Parallel Computers focuses on the concept and characteristics of an algorithmically specialized computer.This book discusses the algorithmically specialized computers, algorithmic specialization using VLSI, and innovative architectures. The architectures and algorithms for digital signal, speech, and image processing and specialized architectures for numerical computations are also elaborated. Other topics include the model for analyzing generalized inter-processor, pipelined architecture for search tree maintenance, and specialized computer organization for raster

  6. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  7. A CAD System for Hemorrhagic Stroke.

    Science.gov (United States)

    Nowinski, Wieslaw L; Qian, Guoyu; Hanley, Daniel F

    2014-09-01

    Computer-aided detection/diagnosis (CAD) is a key component of routine clinical practice, increasingly used for detection, interpretation, quantification and decision support. Despite a critical need, there is no clinically accepted CAD system for stroke yet. Here we introduce a CAD system for hemorrhagic stroke. This CAD system segments, quantifies, and displays hematoma in 2D/3D, and supports evacuation of hemorrhage by thrombolytic treatment monitoring progression and quantifying clot removal. It supports seven-step workflow: select patient, add a new study, process patient's scans, show segmentation results, plot hematoma volumes, show 3D synchronized time series hematomas, and generate report. The system architecture contains four components: library, tools, application with user interface, and hematoma segmentation algorithm. The tools include a contour editor, 3D surface modeler, 3D volume measure, histogramming, hematoma volume plot, and 3D synchronized time-series hematoma display. The CAD system has been designed and implemented in C++. It has also been employed in the CLEAR and MISTIE phase-III, multicenter clinical trials. This stroke CAD system is potentially useful in research and clinical applications, particularly for clinical trials.

  8. AutoCAD workbook

    CERN Document Server

    Metherell, Phil

    1989-01-01

    AutoCAD Workbook helps new users learn the basics of AutoCad, providing guidance on most of the commonly used functions in which the program operates.This book discusses loading AutoCad and starting a drawing; drawing and erasing lines, circles, and arcs; and setting up the drawing environment. The topics on drawing and editing polylines; entering text and text styles; and layers, linetype, and color are also considered. This publication likewise covers creating and using blocks, hatching and extracting information, dimensioning drawings, 3D visualization, and plotting a drawing. Other

  9. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  10. CAD/CAM/CNC.

    Science.gov (United States)

    Domermuth, Dave; And Others

    1996-01-01

    Includes "Quick Start CNC (computer numerical control) with a Vacuum Filter and Laminated Plastic" (Domermuth); "School and Industry Cooperate for Mutual Benefit" (Buckler); and "CAD (computer-assisted drafting) Careers--What Professionals Have to Say" (Skinner). (JOW)

  11. MS AutoCad

    DEFF Research Database (Denmark)

    Andersen, Michael Rye; Heinicke, Hugo

    1996-01-01

    Formålet med dette notat er at give en introduktion til tegning af et generalarrangement ved anvendelse af CAD-programmet AutoCAD. Generalarrangementets formål er at skabe en overskuelig præsentation af et skibsprojekt. Det skal gøres indenfor de rammer, som ligger til grund for praktiskprojekter......Formålet med dette notat er at give en introduktion til tegning af et generalarrangement ved anvendelse af CAD-programmet AutoCAD. Generalarrangementets formål er at skabe en overskuelig præsentation af et skibsprojekt. Det skal gøres indenfor de rammer, som ligger til grund...

  12. MS AutoCad

    DEFF Research Database (Denmark)

    Andersen, Michael Rye; Heinicke, Hugo

    1996-01-01

    Formålet med dette notat er at give en introduktion til tegning af et generalarrangement ved anvendelse af CAD-programmet AutoCAD. Generalarrangementets formål er at skabe en overskuelig præsentation af et skibsprojekt. Det skal gøres indenfor de rammer, som ligger til grund for praktiskprojekter......Formålet med dette notat er at give en introduktion til tegning af et generalarrangement ved anvendelse af CAD-programmet AutoCAD. Generalarrangementets formål er at skabe en overskuelig præsentation af et skibsprojekt. Det skal gøres indenfor de rammer, som ligger til grund...

  13. CAD/CAM/CNC.

    Science.gov (United States)

    Domermuth, Dave; And Others

    1996-01-01

    Includes "Quick Start CNC (computer numerical control) with a Vacuum Filter and Laminated Plastic" (Domermuth); "School and Industry Cooperate for Mutual Benefit" (Buckler); and "CAD (computer-assisted drafting) Careers--What Professionals Have to Say" (Skinner). (JOW)

  14. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  15. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  16. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  17. A VLSI implementation of DCT using pass transistor technology

    Science.gov (United States)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  18. Research on remote sensing image pixel attribute data acquisition method in AutoCAD

    Science.gov (United States)

    Liu, Xiaoyang; Sun, Guangtong; Liu, Jun; Liu, Hui

    2013-07-01

    The remote sensing image has been widely used in AutoCAD, but AutoCAD lack of the function of remote sensing image processing. In the paper, ObjectARX was used for the secondary development tool, combined with the Image Engine SDK to realize remote sensing image pixel attribute data acquisition in AutoCAD, which provides critical technical support for AutoCAD environment remote sensing image processing algorithms.

  19. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  20. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  1. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  2. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  3. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  4. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  5. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  6. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  7. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  8. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  9. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  10. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  11. Annotation and retrieval system of CAD models based on functional semantics

    Science.gov (United States)

    Wang, Zhansong; Tian, Ling; Duan, Wenrui

    2014-11-01

    CAD model retrieval based on functional semantics is more significant than content-based 3D model retrieval during the mechanical conceptual design phase. However, relevant research is still not fully discussed. Therefore, a functional semantic-based CAD model annotation and retrieval method is proposed to support mechanical conceptual design and design reuse, inspire designer creativity through existing CAD models, shorten design cycle, and reduce costs. Firstly, the CAD model functional semantic ontology is constructed to formally represent the functional semantics of CAD models and describe the mechanical conceptual design space comprehensively and consistently. Secondly, an approach to represent CAD models as attributed adjacency graphs(AAG) is proposed. In this method, the geometry and topology data are extracted from STEP models. On the basis of AAG, the functional semantics of CAD models are annotated semi-automatically by matching CAD models that contain the partial features of which functional semantics have been annotated manually, thereby constructing CAD Model Repository that supports model retrieval based on functional semantics. Thirdly, a CAD model retrieval algorithm that supports multi-function extended retrieval is proposed to explore more potential creative design knowledge in the semantic level. Finally, a prototype system, called Functional Semantic-based CAD Model Annotation and Retrieval System(FSMARS), is implemented. A case demonstrates that FSMARS can successfully botain multiple potential CAD models that conform to the desired function. The proposed research addresses actual needs and presents a new way to acquire CAD models in the mechanical conceptual design phase.

  12. Annotation and Retrieval System of CAD Models Based on Functional Semantics

    Institute of Scientific and Technical Information of China (English)

    WANG Zhansong; TIAN Ling; DUAN Wenrui

    2014-01-01

    CAD model retrieval based on functional semantics is more significant than content-based 3D model retrieval during the mechanical conceptual design phase. However, relevant research is still not fully discussed. Therefore, a functional semantic-based CAD model annotation and retrieval method is proposed to support mechanical conceptual design and design reuse, inspire designer creativity through existing CAD models, shorten design cycle, and reduce costs. Firstly, the CAD model functional semantic ontology is constructed to formally represent the functional semantics of CAD models and describe the mechanical conceptual design space comprehensively and consistently. Secondly, an approach to represent CAD models as attributed adjacency graphs(AAG) is proposed. In this method, the geometry and topology data are extracted from STEP models. On the basis of AAG, the functional semantics of CAD models are annotated semi-automatically by matching CAD models that contain the partial features of which functional semantics have been annotated manually, thereby constructing CAD Model Repository that supports model retrieval based on functional semantics. Thirdly, a CAD model retrieval algorithm that supports multi-function extended retrieval is proposed to explore more potential creative design knowledge in the semantic level. Finally, a prototype system, called Functional Semantic-based CAD Model Annotation and Retrieval System(FSMARS), is implemented. A case demonstrates that FSMARS can successfully botain multiple potential CAD models that conform to the desired function. The proposed research addresses actual needs and presents a new way to acquire CAD models in the mechanical conceptual design phase.

  13. Beginning AutoCAD 2002

    CERN Document Server

    McFarlane, Bob

    2002-01-01

    New features in AutoCAD 2002 are covered in this book, making it a useful refresher course for anyone using AutoCAD at this level, and upgrading to the new software release. The material in the book is also relevant to anyone using other recent releases, including, AutoCAD 2000.

  14. AutoCAD 2014 and AutoCAD LT 2014

    CERN Document Server

    Gladfelter, Donnie

    2013-01-01

    A step-by-step tutorial introduction to AutoCAD As the only book to teach AutoCAD using a continuous tutorial which allows you to follow along sequentially or jump in at any exercise by downloading the drawing files, this Autodesk Official Press book is ideal for the AutoCAD novice. Industry expert and AutoCAD guru Donnie Gladfelter walks you through the powerful features of AutoCAD, provides you with a solid foundation of the basics, and shares the latest industry standards and techniques. The hands-on tutorial project inspired by real-world workflows that runs throughout the book

  15. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  16. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  17. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  18. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  19. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  20. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  1. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  2. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  3. False positive reduction for lung nodule CAD

    Science.gov (United States)

    Zhao, Luyin; Boroczky, Lilla; Drysdale, Jeremy; Agnihotri, Lalitha; Lee, Michael C.

    2007-03-01

    Computer-aided detection (CAD) algorithms 'automatically' identify lung nodules on thoracic multi-slice CT scans (MSCT) thereby providing physicians with a computer-generated 'second opinion'. While CAD systems can achieve high sensitivity, their limited specificity has hindered clinical acceptance. To overcome this problem, we propose a false positive reduction (FPR) system based on image processing and machine learning to reduce the number of false positive lung nodules identified by CAD algorithms and thereby improve system specificity. To discriminate between true and false nodules, twenty-three 3D features were calculated from each candidate nodule's volume of interest (VOI). A genetic algorithm (GA) and support vector machine (SVM) were then used to select an optimal subset of features from this pool of candidate features. Using this feature subset, we trained an SVM classifier to eliminate as many false positives as possible while retaining all the true nodules. To overcome the imbalanced nature of typical datasets (significantly more false positives than true positives), an intelligent data selection algorithm was designed and integrated into the machine learning framework, thus further improving the FPR rate. Three independent datasets were used to train and validate the system. Using two datasets for training and the third for validation, we achieved a 59.4% FPR rate while removing one true nodule on the validation datasets. In a second experiment, 75% of the cases were randomly selected from each of the three datasets and the remaining cases were used for validation. A similar FPR rate and true positive retention rate was achieved. Additional experiments showed that the GA feature selection process integrated with the proposed data selection algorithm outperforms the one without it by 5%-10% FPR rate. The methods proposed can be also applied to other application areas, such as computer-aided diagnosis of lung nodules.

  4. AutoCAD / AutoCAD LT 2014 fundamentals metric

    CERN Document Server

    ASCENT center for technical knowledge

    2014-01-01

    The objective of AutoCAD/AutoCAD LT 2014 Fundamentals is to enable students to create a basic 2D drawing in the AutoCAD software. Even at this fundamental level, the AutoCAD software is one of the most sophisticated computer applications that you are likely to encounter. Therefore learning to use it can be challenging. To make the process easier and provide flexibility for instructors and students, the training guide is divided into two parts that can be taken independently.

  5. CAD/CAE Integration Enhanced by New CAD Services Standard

    Science.gov (United States)

    Claus, Russell W.

    2002-01-01

    A Government-industry team led by the NASA Glenn Research Center has developed a computer interface standard for accessing data from computer-aided design (CAD) systems. The Object Management Group, an international computer standards organization, has adopted this CAD services standard. The new standard allows software (e.g., computer-aided engineering (CAE) and computer-aided manufacturing software to access multiple CAD systems through one programming interface. The interface is built on top of a distributed computing system called the Common Object Request Broker Architecture (CORBA). CORBA allows the CAD services software to operate in a distributed, heterogeneous computing environment.

  6. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  7. CAD: How it works, how to use it, performance

    Energy Technology Data Exchange (ETDEWEB)

    Regge, Daniele, E-mail: daniele.regge@ircc.it [Institute for Cancer Research and Treatment, Candiolo-Torino (Italy); Halligan, Steve, E-mail: s.halligan@ucl.ac.uk [University College Hospital London, London (United Kingdom)

    2013-08-15

    Computer-aided diagnosis (CAD) systems are software algorithms designed to assist radiologists (or other practitioners) in solving a diagnostic problem by using a visual prompt (or “CAD mark”) to direct the observer towards potential pathology. CT colonography is a recent arrival to CAD, but could represent one of its most fruitful applications in the future. In contrast to other organs, where a variety of different pathologies are equally represented, significant colorectal pathologies other than polyps and cancer are relatively uncommon. As we shall see, this simplifies the diagnostic task for artificial intelligence developers and also for radiologists who, ultimately, must make the final decision. This review aims to present the current state-of-the-art for CAD applied to CT colonography. A brief overview of the technical essentials and of the diagnostic performance of CAD in isolation, is followed by an explanation of how CAD is used in day-to-day practice. The last section will deal with the most controversial issues affecting CAD performance in clinical practice, with a focus on the interaction between human and artificial intelligence.

  8. CAD/CAM for optomechatronics

    Science.gov (United States)

    Zhou, Haiguang; Han, Min

    2003-10-01

    We focus at CAD/CAM for optomechatronics. We have developed a kind of CAD/CAM, which is not only for mechanics but also for optics and electronic. The software can be used for training and education. We introduce mechanical CAD, optical CAD and electrical CAD, we show how to draw a circuit diagram, mechanical diagram and luminous transmission diagram, from 2D drawing to 3D drawing. We introduce how to create 2D and 3D parts for optomechatronics, how to edit tool paths, how to select parameters for process, how to run the post processor, dynamic show the tool path and generate the CNC programming. We introduce the joint application of CAD&CAM. We aim at how to match the requirement of optical, mechanical and electronics.

  9. Octree Representation and Its Applications in CAD

    Institute of Scientific and Technical Information of China (English)

    唐泽圣

    1992-01-01

    In this paper,a survey of octree representation and its applications in CAD is presented.The octree representation may be categorized as pure octree representation and polytree(or extended octree),and the latter is actually a boundary representation decomposed by octree.Linear octree which is a variant of regular octree representation has the advantage of saving memory space.The mapping between Cartesian coordinates and node addresses in linear octree is discussed.Then,algorithms for converting a boundary representation of 3D object into an octree are investiged and major approaches for transforming an octree encoded object are presented.After that,some of the applications of octree representation in CAD are listed,in particular,the applications in solid modeling,in accelerating ray tracing and in generating meshes for FEM.

  10. CAD/CAM-assisted breast reconstruction

    Energy Technology Data Exchange (ETDEWEB)

    Melchels, Ferry; Hutmacher, Dietmar Werner [Institute of Health and Biomedical Innovation, Queensland University of Technology, 60 Musk Avenue, Kelvin Grove, QLD 4059 (Australia); Wiggenhauser, Paul Severin; Schantz, Jan-Thorsten [Department of Plastic and Hand Surgery, Klinikum rechts der Isar, Technische Universitaet Muenchen, Ismaninger Strasse 22, 81675 Munich (Germany); Warne, David; Barry, Mark [High Performance Computing and Research Support, Queensland University of Technology, Gardens Point Road, Brisbane, QLD 4000 (Australia); Ong, Fook Rhu; Chong, Woon Shin, E-mail: Dietmar.Hutmacher@qut.edu.au, E-mail: jtschantz@lrz.tu-muenchen.de [Singapore Polytechnic, 500 Dover Road, 139651 Singapore (Singapore)

    2011-09-15

    The application of computer-aided design and manufacturing (CAD/CAM) techniques in the clinic is growing slowly but steadily. The ability to build patient-specific models based on medical imaging data offers major potential. In this work we report on the feasibility of employing laser scanning with CAD/CAM techniques to aid in breast reconstruction. A patient was imaged with laser scanning, an economical and facile method for creating an accurate digital representation of the breasts and surrounding tissues. The obtained model was used to fabricate a customized mould that was employed as an intra-operative aid for the surgeon performing autologous tissue reconstruction of the breast removed due to cancer. Furthermore, a solid breast model was derived from the imaged data and digitally processed for the fabrication of customized scaffolds for breast tissue engineering. To this end, a novel generic algorithm for creating porosity within a solid model was developed, using a finite element model as intermediate.

  11. Beginning AutoCAD 2005

    CERN Document Server

    McFarlane, Bob

    2005-01-01

    Beginning AutoCAD 2005 is a course based on learning and practising the essentials of 2D drawing using AutoCAD. Bob McFarlane's hands-on approach is uniquely suited to independent learning and use on courses. The focus on 2D drawing in one book, ensures the reader gets a thorough grounding in the subject, with a greater depth of coverage than tends to be available from general introductions to AutoCAD. As a result, this book provides a true, step-by-step, detailed exploration of the AutoCAD functions required at each stage of producing a 2D drawing - an approach often

  12. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  13. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    LIU; Yanpei(

    2001-01-01

    [1]Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.[2]Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.[3]Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.[4]Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.[5]Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.[6]Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.[7]Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.[8]Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.[9]Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.[10]Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.[11]Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.[12]Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.[13]Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.

  14. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  15. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  16. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  17. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  18. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  19. Integrating CAD modules in a PACS environment using a wide computing infrastructure.

    Science.gov (United States)

    Suárez-Cuenca, Jorge J; Tilve, Amara; López, Ricardo; Ferro, Gonzalo; Quiles, Javier; Souto, Miguel

    2017-04-01

    The aim of this paper is to describe a project designed to achieve a total integration of different CAD algorithms into the PACS environment by using a wide computing infrastructure. The aim is to build a system for the entire region of Galicia, Spain, to make CAD accessible to multiple hospitals by employing different PACSs and clinical workstations. The new CAD model seeks to connect different devices (CAD systems, acquisition modalities, workstations and PACS) by means of networking based on a platform that will offer different CAD services. This paper describes some aspects related to the health services of the region where the project was developed, CAD algorithms that were either employed or selected for inclusion in the project, and several technical aspects and results. We have built a standard-based platform with which users can request a CAD service and receive the results in their local PACS. The process runs through a web interface that allows sending data to the different CAD services. A DICOM SR object is received with the results of the algorithms stored inside the original study in the proper folder with the original images. As a result, a homogeneous service to the different hospitals of the region will be offered. End users will benefit from a homogeneous workflow and a standardised integration model to request and obtain results from CAD systems in any modality, not dependant on commercial integration models. This new solution will foster the deployment of these technologies in the entire region of Galicia.

  20. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  1. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Directory of Open Access Journals (Sweden)

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  2. CAD/CAM data management

    Science.gov (United States)

    Bray, O. H.

    1984-01-01

    The role of data base management in CAD/CAM, particularly for geometric data is described. First, long term and short term objectives for CAD/CAM data management are identified. Second, the benefits of the data base management approach are explained. Third, some of the additional work needed in the data base area is discussed.

  3. 64006 CAD i Byggesektoren. Grundkursus

    DEFF Research Database (Denmark)

    Borchersen, Egil

    1998-01-01

    Overview on Computer Aided Design in Civil Engineering and introduction to AutoCAD version 13, layers, colours, blocks, attributes.......Overview on Computer Aided Design in Civil Engineering and introduction to AutoCAD version 13, layers, colours, blocks, attributes....

  4. CAD/CAM data management

    Science.gov (United States)

    Bray, O. H.

    1984-01-01

    The role of data base management in CAD/CAM, particularly for geometric data is described. First, long term and short term objectives for CAD/CAM data management are identified. Second, the benefits of the data base management approach are explained. Third, some of the additional work needed in the data base area is discussed.

  5. 64006 CAD i Byggesektoren. Grundkursus

    DEFF Research Database (Denmark)

    Borchersen, Egil

    1998-01-01

    Overview on Computer Aided Design in Civil Engineering and introduction to AutoCAD version 13, layers, colours, blocks, attributes.......Overview on Computer Aided Design in Civil Engineering and introduction to AutoCAD version 13, layers, colours, blocks, attributes....

  6. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  7. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  8. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  9. A multi coding technique to reduce transition activity in VLSI circuits

    Science.gov (United States)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  10. Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2011-01-01

    Full Text Available Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

  11. AutoCAD 2014 essentials

    CERN Document Server

    Onstott, Scott

    2013-01-01

    Learn crucial AutoCAD tools and techniques with this Autodesk Official Press Book Quickly become productive using AutoCAD 2014 and AutoCAD LT 2014 with this full color Autodesk Official Press guide. This unique learning resource features concise, straightforward explanations and real-world, hands-on exercises and tutorials. Following a quick discussion of concepts and goals, each chapter moves on to an approachable hands-on exercise designed to reinforce real-world tactics and techniques. Compelling, full-color screenshots illustrate tutorial steps, and chapters conclude with relat

  12. CAD-Based Monte Carlo Neutron Transport KSTAR Analysis for KSTAR

    Science.gov (United States)

    Seo, Geon Ho; Choi, Sung Hoon; Shim, Hyung Jin

    2017-09-01

    The Monte Carlo (MC) neutron transport analysis for a complex nuclear system such as fusion facility may require accurate modeling of its complicated geometry. In order to take advantage of modeling capability of the computer aided design (CAD) system for the MC neutronics analysis, the Seoul National University MC code, McCARD, has been augmented with a CAD-based geometry processing module by imbedding the OpenCASCADE CAD kernel. In the developed module, the CAD geometry data are internally converted to the constructive solid geometry model with help of the CAD kernel. An efficient cell-searching algorithm is devised for the void space treatment. The performance of the CAD-based McCARD calculations are tested for the Korea Superconducting Tokamak Advanced Research device by comparing with results of the conventional MC calculations using a text-based geometry input.

  13. Design and Implementation of VLSI Prime Factor Algorithm Processor.

    Science.gov (United States)

    1987-12-01

    for A, 1i ’ 1 1 Fh Ai ,,r equjAtIInI. art, ( , 4 10 4,t’ 4 ( - /’ cr tht, (-arr% sur ma% akL, be represented as Figure 36 Carry Select Adder Blocking... Select Adder Blocking .......................................................... 81 Figure 37: ALU Adder Cell...ALU Logic Implementation............................................................ 81 viii J,.. in List of Figures (continued) Figure 36: Carry

  14. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  15. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    Science.gov (United States)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  16. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    Science.gov (United States)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  17. Comprehensive BRL-CAD Primitive Database

    Science.gov (United States)

    2015-03-01

    going to save files in the .g format used by BRL–CAD. But other formats, such as STP, 3DM, and AutoCAD (ACAD), can be converted to a mesh of...ceros) CAD system’s file format (file extension .3dm) ACAD AutoCAD arb8 arb with 8 vertices ars arbitrary faceted solid bot Bag o

  18. AutoCAD 2014 for dummies

    CERN Document Server

    Fane, Bill

    2013-01-01

    Find your way around AutoCAD 2014 with this full-color, For Dummies guide!Put away that pencil and paper and start putting the power of AutoCAD 2014 to work in your CAD projects and designs. From setting up your drawing environment to using text, dimensions, hatching, and more, this guide walks you through AutoCAD basics and provides you with a solid understanding of the latest CAD tools and techniques. You'll also benefit from the full-color illustrations that mirror exactly what you'll see on your AutoCAD 2014 screen and highlight the importance of AutoCAD's Mode

  19. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  20. Role of computer aided detection (CAD) integration: case study with meniscal and articular cartilage CAD applications

    Science.gov (United States)

    Safdar, Nabile; Ramakrishna, Bharath; Saiprasad, Ganesh; Siddiqui, Khan; Siegel, Eliot

    2008-03-01

    Knee-related injuries involving the meniscal or articular cartilage are common and require accurate diagnosis and surgical intervention when appropriate. With proper techniques and experience, confidence in detection of meniscal tears and articular cartilage abnormalities can be quite high. However, for radiologists without musculoskeletal training, diagnosis of such abnormalities can be challenging. In this paper, the potential of improving diagnosis through integration of computer-aided detection (CAD) algorithms for automatic detection of meniscal tears and articular cartilage injuries of the knees is studied. An integrated approach in which the results of algorithms evaluating either meniscal tears or articular cartilage injuries provide feedback to each other is believed to improve the diagnostic accuracy of the individual CAD algorithms due to the known association between abnormalities in these distinct anatomic structures. The correlation between meniscal tears and articular cartilage injuries is exploited to improve the final diagnostic results of the individual algorithms. Preliminary results from the integrated application are encouraging and more comprehensive tests are being planned.

  1. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  2. Analysis list: cad [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cad Embryo + dm3 http://dbarchive.biosciencedbc.jp/kyushu-u/dm3/target/cad.1.tsv ht...tp://dbarchive.biosciencedbc.jp/kyushu-u/dm3/target/cad.5.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/dm3/target/cad....10.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/dm3/colo/cad.Embryo.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/dm3/colo/Embryo.gml ...

  3. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  4. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  5. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  6. CAD Services: an Industry Standard Interface for Mechanical CAD Interoperability

    Science.gov (United States)

    Claus, Russell; Weitzer, Ilan

    2002-01-01

    Most organizations seek to design and develop new products in increasingly shorter time periods. At the same time, increased performance demands require a team-based multidisciplinary design process that may span several organizations. One approach to meet these demands is to use 'Geometry Centric' design. In this approach, design engineers team their efforts through one united representation of the design that is usually captured in a CAD system. Standards-based interfaces are critical to provide uniform, simple, distributed services that enable the 'Geometry Centric' design approach. This paper describes an industry-wide effort, under the Object Management Group's (OMG) Manufacturing Domain Task Force, to define interfaces that enable the interoperability of CAD, Computer Aided Manufacturing (CAM), and Computer Aided Engineering (CAE) tools. This critical link to enable 'Geometry Centric' design is called: Cad Services V1.0. This paper discusses the features of this standard and proposed application.

  7. AutoCAD 2015 and AutoCAD LT 2015

    CERN Document Server

    Gladfelter, Donnie

    2014-01-01

    Learn AutoCAD by example with this tutorial-based guide from Autodesk Official Press Whether you are just starting out or an experienced user wanting to brush up on your skills, this Autodesk Official Press book provides you with concise explanations, focused examples, and step-by-step instructions through a hands-on tutorial project that runs throughout the book. As you progress through the project, the book introduces you to the Microsoft Windows-based AutoCAD interface and then guides you through basic commands and creating drawings. A downloadable file is available from the website so that

  8. Internet与AutoCAD%Internet and AutoCAD

    Institute of Scientific and Technical Information of China (English)

    李岩; 修立刚

    2009-01-01

    从Internet是国际上交流信息最重要的方法出发,介绍了AutoCAD的网络功能.即如何在Web上发布图形和在AutoCAD中进行网上的图形操作.%Is internationally exchanges the information most important method from Intemet to embark, introduced the AutoCAD network function, how namely on Web to issue that the graph and carries in-line graph operation in AutoCAD.

  9. 可制造性驱动的三维CAD模型相交制造特征识别方法%Manufacturability Driven Interacting Machining Feature Recognition Algorithms for 3D CAD Models

    Institute of Scientific and Technical Information of China (English)

    黄瑞; 张树生; 白晓亮

    2013-01-01

    To realize the effective integration of CAD,CAPP,and CAM system,we present a manufacturability driven interacting machining feature recognition method for 3D CAD models.Firstly,the accessibility cone for each machining face is computed based on heuristic rules.Machining region subgraphs are then constructed by machining face clustering method considering manufacturing semantics.With the dimension semantic information,interacting machining features are finally recognized based on the machining region subgraph that is used as a feature hint.The approach proposed is implemented and tested by hundreds of mechanical parts.Preliminary results show that the method can effectively realize machining feature recognition for complex interacting machining features and complex parts,and the efficiency can meet the requirement of engineering application.%为了实现CAD/CAPP/CAM系统的有效集成,提出一种可制造性驱动的三维CAD模型相交制造特征识别方法.首先通过启发式规则对加工面进行可达性分析,计算加工面可行刀具轴向空间;然后采用融合制造语义的加工面聚类算法构建加工区域子图;最后以加工区域子图为制造特征痕迹,结合标注语义信息对加工区域子图进行优化合并,从而实现制造特征的识别.实验结果表明,该方法能够有效地实现复杂相交制造特征和复杂零件的制造特征识别,制造特征识别性能可满足工程应用中的需求.

  10. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  11. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  12. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  13. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  14. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  15. AutoCAD 2010 For Dummies

    CERN Document Server

    Byrnes, David

    2009-01-01

    AutoCAD is the hot computer-aided design software known for both its powerful tools and its complexity. AutoCAD 2010 for Dummies is the bestselling guide that walks you through this complicated program so you can build complex 3D technical drawings, edit like a pro, enter new dimensions, and plot with style. AutoCAD 2010 for Dummies helps you navigate the program, use the AutoCAD Design Center, create a basic layout and work with dimension, and put your drawings on the Internet. You'll soon be setting up the AutoCAD environment, using the AutoCAD Ribbon, creating annotation and dimension drawi

  16. AutoCAD 2008 for dummies

    CERN Document Server

    Byrnes, David

    2007-01-01

    A gentle, humorous introduction to this fearsomely complex software that helps new users start creating 2D and 3D technical drawings right awayCovers the new features and enhancements in the latest AutoCAD version and provides coverage of AutoCAD LT, AutoCAD''s lower-cost siblingTopics covered include creating a basic layout, using AutoCAD DesignCenter, drawing and editing, working with dimensions, plotting, using blocks, adding text to drawings, and drawing on the InternetAutoCAD is the leading CAD software for architects, engineers, and draftspeople who need to create detailed 2D and 3D tech

  17. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  18. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    CERN Document Server

    Tiri, Kris

    2011-01-01

    This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.

  19. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  20. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  1. Intelligence in Clothing Pattern CAD System

    Institute of Scientific and Technical Information of China (English)

    LI Xu; ZHANG Zu-fang

    2007-01-01

    It analyzes three recognition methods for fiveelements, i.e. dot, line, loop, dothing pattern as well ascharacters, and also appfies intelligent points and tangentialcurve in the CAD system to solve the problem complained byCAD users. It indicates that recognition of five elements is afoundational technique of intelligence in clothing patternCAD system. Common functions in operation state such asmove, rotation, flip, measure, should precede ones inelement state as dot, line, and pattern. Moreover, it isrealized that the less skill the CAD user needs, the more theCAD software is high-tech.

  2. AutoCAD platform customization VBA

    CERN Document Server

    Ambrosius, Lee

    2015-01-01

    Boost productivity and streamline your workflow with expert AutoCAD: VBA programming instruction AutoCAD Platform Customization: VBA is the definitive guide to personalizing AutoCAD and the various programs that run on the AutoCAD platform, including AutoCAD Architecture, Civil 3D, Plant 3D, and more. Written by an Autodesk insider with years of customization and programming experience, this book features detailed discussions backed by real-world examples and easy-to-follow tutorials that illustrate each step in the personalization process. Readers gain expert guidance toward managing layout

  3. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  4. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  5. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  6. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  7. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  8. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  9. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  10. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  11. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  12. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  13. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  14. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  15. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  16. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  17. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  18. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  19. AutoCAD 2015 and AutoCAD LT 2015 bible

    CERN Document Server

    Finkelstein, Ellen

    2014-01-01

    The perfect reference for all AutoCAD users AutoCAD 2015 and AutoCAD LT 2015 Bible is the book you want to have close at hand to answer those day-to-day questions about this industry-leading software. Author and Autodesk University instructor Ellen Finkelstein guides readers through AutoCAD 2015 and AutoCAD LT 2015 with clear, easy-to-understand instruction and hands-on tutorials that allow even total beginners to create a design on their very first day. Although simple and fundamental enough to be used by those new to CAD, the book is so comprehensive that even Autodesk power u

  20. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  1. Algorithms, architectures and information systems security

    CERN Document Server

    Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya

    2008-01-01

    This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin

  2. Computing Mass Properties From AutoCAD

    Science.gov (United States)

    Jones, A.

    1990-01-01

    Mass properties of structures computed from data in drawings. AutoCAD to Mass Properties (ACTOMP) computer program developed to facilitate quick calculations of mass properties of structures containing many simple elements in such complex configurations as trusses or sheet-metal containers. Mathematically modeled in AutoCAD or compatible computer-aided design (CAD) system in minutes by use of three-dimensional elements. Written in Microsoft Quick-Basic (Version 2.0).

  3. Computing Mass Properties From AutoCAD

    Science.gov (United States)

    Jones, A.

    1990-01-01

    Mass properties of structures computed from data in drawings. AutoCAD to Mass Properties (ACTOMP) computer program developed to facilitate quick calculations of mass properties of structures containing many simple elements in such complex configurations as trusses or sheet-metal containers. Mathematically modeled in AutoCAD or compatible computer-aided design (CAD) system in minutes by use of three-dimensional elements. Written in Microsoft Quick-Basic (Version 2.0).

  4. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  5. VLSI Implementation of Digital Fourier Transforms.

    Science.gov (United States)

    1982-11-01

    23) which , coplte the proofi .t)0 !/*!, R,.),ta , ’,.[ ](5 ".: - 10- We now look at the structure of Theorem 1 for three cases. Cow 1: n -k = k...phase devices have reasonable signal ban- dung capabilities. From three phases on up the signal handling is very good, but the problem of routing all...Tompsett, Choarge Transfer Demices, Academic Press Inc. (1975). 4. J. W. Cooley and J. W. Tukey, "An Algorithm for the Machine Calculation of Complex

  6. Progress of computer-aided detection/diagnosis (CAD in dentistryCAD in dentistry

    Directory of Open Access Journals (Sweden)

    Akitoshi Katsumata

    2014-08-01

    CAD is also useful in the detection and evaluation of dental and maxillofacial lesions. Identifying alveolar bone resorption due to periodontitis and radiolucent jaw lesions (such as radicular and dentigerous cysts are important goals for CAD. CAD can be applied not only to panoramic radiography but also to dental cone-beam computed tomography (CBCT images. Linking of CAD and teleradiology will be an important issue.

  7. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  8. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  9. Modified Multi-Resolution Telescopic Search Algorithm for Block-Matching Motion Estimation

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    This paper presents a modified multi-resolution telescopic search algorithm (MRTlcSA) for the blockmatching motion estimation. A novel inverse telescopic search is substituted for the conventional telescopic search, that reduces the on-chip memory size and memory bandwidth for VLSI implementation. In addition, strategies of motion track and adaptive search window are applied to reduce the computational complexity of motion estimation. Simulation results show that, compared with the MRTlcSA, the proposed algorithm reduces the computational load to only 30%while preserving almost the same image quality. Comparisons on hardware cost and power consumption of the VLSI implementations using the two algorithms are also presented in the paper.``

  10. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  11. VLSI digital PSK demodulator for space communication

    Science.gov (United States)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  12. Lossless compression of VLSI layout image data.

    Science.gov (United States)

    Dai, Vito; Zakhor, Avideh

    2006-09-01

    We present a novel lossless compression algorithm called Context Copy Combinatorial Code (C4), which integrates the advantages of two very disparate compression techniques: context-based modeling and Lempel-Ziv (LZ) style copying. While the algorithm can be applied to many lossless compression applications, such as document image compression, our primary target application has been lossless compression of integrated circuit layout image data. These images contain a heterogeneous mix of data: dense repetitive data better suited to LZ-style coding, and less dense structured data, better suited to context-based encoding. As part of C4, we have developed a novel binary entropy coding technique called combinatorial coding which is simultaneously as efficient as arithmetic coding, and as fast as Huffman coding. Compression results show C4 outperforms JBIG, ZIP, BZIP2, and two-dimensional LZ, and achieves lossless compression ratios greater than 22 for binary layout image data, and greater than 14 for gray-pixel image data.

  13. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  14. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  15. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  16. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  17. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  18. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  19. Sharing the learning activity using intelligent CAD

    DEFF Research Database (Denmark)

    Duffy, S. M.; Duffy, Alex

    1996-01-01

    In this paper the need for Intelligent Computer Aided Design (Int.CAD) to jointly support design and learning assistance is introduced. The paper focuses on presenting and exploring the possibility of realizing ''learning'' assistance in Int.CAD by introducing a new concept called Shared Learning...

  20. Onzichtbare beugels dankzij CAD-CAM

    NARCIS (Netherlands)

    F.R. de Winter

    2011-01-01

    De introductie van de cad-cam-techniek in de tandheelkunde heeft in de orthodontie geleid tot het orthodontisch verplaatsen van gebitselementen met een serie opeenvolgende dieptrekplaten, ontworpen en gefabriceerd met behulp van cad-cam. Daarbij is iedere plaat een kleine stap in de richting van de

  1. Vlsi Implementation of Edge Detection for Images

    Directory of Open Access Journals (Sweden)

    T. Mahalakshmi

    2012-12-01

    Full Text Available Edge is the boundary between the image and its background. Edge detection in general is defined as the local maxima obtained from high pass filters, but an optimized edge detector should mark the edges with respect to luminance or brightness changes. It is easy to obtain them in software implementation but for hardware implementation there is an issue with percentage of accuracy and processing time. This study discusses various edge detection algorithms and proposes an optimized edge detector which provides the solution for mentioned above issue. Since FPGA provides practical solutions for most of the image processing problems, the proposed architecture has been developed using Matlab System generator. Experimental results show the accuracy of edge detected using proposed architecture.

  2. Computer-aided detection (CAD) of breast masses in mammography: combined detection and ensemble classification

    Science.gov (United States)

    Choi, Jae Young; Kim, Dae Hoe; Plataniotis, Konstantinos N.; Ro, Yong Man

    2014-07-01

    We propose a novel computer-aided detection (CAD) framework of breast masses in mammography. To increase detection sensitivity for various types of mammographic masses, we propose the combined use of different detection algorithms. In particular, we develop a region-of-interest combination mechanism that integrates detection information gained from unsupervised and supervised detection algorithms. Also, to significantly reduce the number of false-positive (FP) detections, the new ensemble classification algorithm is developed. Extensive experiments have been conducted on a benchmark mammogram database. Results show that our combined detection approach can considerably improve the detection sensitivity with a small loss of FP rate, compared to representative detection algorithms previously developed for mammographic CAD systems. The proposed ensemble classification solution also has a dramatic impact on the reduction of FP detections; as much as 70% (from 15 to 4.5 per image) at only cost of 4.6% sensitivity loss (from 90.0% to 85.4%). Moreover, our proposed CAD method performs as well or better (70.7% and 80.0% per 1.5 and 3.5 FPs per image respectively) than the results of mammography CAD algorithms previously reported in the literature.

  3. Automatic CAD of meniscal tears on MR imaging: a morphology-based approach

    Science.gov (United States)

    Ramakrishna, Bharath; Liu, Weimin; Safdar, Nabile; Siddiqui, Khan; Kim, Woojin; Juluru, Krishna; Chang, Chein-I.; Siegel, Eliot

    2007-03-01

    Knee-related injuries, including meniscal tears, are common in young athletes and require accurate diagnosis and appropriate surgical intervention. Although with proper technique and skill, confidence in the detection of meniscal tears should be high, this task continues to be a challenge for many inexperienced radiologists. The purpose of our study was to automate detection of meniscal tears of the knee using a computer-aided detection (CAD) algorithm. Automated segmentation of the sagittal T1-weighted MR imaging sequences of the knee in 28 patients with diagnoses of meniscal tears was performed using morphologic image processing in a 3-step process including cropping, thresholding, and application of morphological constraints. After meniscal segmentation, abnormal linear meniscal signal was extracted through a second thresholding process. The results of this process were validated by comparison with the interpretations of 2 board-certified musculoskeletal radiologists. The automated meniscal extraction algorithm process was able to successfully perform region of interest selection, thresholding, and object shape constraint tasks to produce a convex image isolating the menisci in more than 69% of the 28 cases. A high correlation was also noted between the CAD algorithm and human observer results in identification of complex meniscal tears. Our initial investigation indicates considerable promise for automatic detection of simple and complex meniscal tears of the knee using the CAD algorithm. This observation poses interesting possibilities for increasing radiologist productivity and confidence, improving patient outcomes, and applying more sophisticated CAD algorithms to orthopedic imaging tasks.

  4. A CAD Interface for GEANT4

    CERN Document Server

    Poole, Christopher M; Trapp, Jamie V; Langton, Christian M

    2011-01-01

    Typically used as a tool for Monte Carlo simulation of high energy physics experiments, GEANT4 is increasingly being employed for the simulation of complex radiotherapy treatments. Often the specification of components within a clinical linear accelerator treatment head is provided in a CAD file format. Direct import of these CAD files into GEANT4 may not be possible, and complex components such as individual leaves within a multi-leaf collimator may be difficult to define via other means. Solutions that allow for users to work around the limited support in the GEANT4 toolkit for loading predefined CAD geometries has been presented by others, however these solutions require intermediate file format conversion using commercial software. Here within we describe a technique that allows for CAD models to be directly loaded as geometry without the need for commercial software and intermediate file format conversion. Robustness of the interface was tested using a set of CAD models of various complexity; for the mod...

  5. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  6. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  7. APPLICATION RESEARCH OF COMBINATION PRINCIPLE IN CAD FEATURE RECOGNIZATION

    Institute of Scientific and Technical Information of China (English)

    Li Guangrong; Gong Guangrong; Ding Wuxue

    2005-01-01

    The method of extracting the basic features of part from the file of STEP AP214 of 3-D model is proposed. All faces in the file are the minimal elements. The combination is done for the faces with geometry restrictions and some attributes by the theory of the best alphabetic tree which is constructed by HU--TUCKER algorithm in combination principle. So the basic features could be attained. This provides the research basis to the more share and integration of CAD information in the virtual enterprises. Finally, a case is used to illustrate the validity of the approach.

  8. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  9. AutoCAD platform customization autolisp

    CERN Document Server

    Ambrosius, Lee

    2014-01-01

    Customize and personalize programs built on the AutoCAD platform AutoLISP is the key to unlocking the secrets of a more streamlined experience using industry leading software programs like AutoCAD, Civil 3D, Plant 3D, and more. AutoCAD Platform Customization: AutoLISP provides real-world examples that show you how to do everything from modifying graphical objects and reading and setting system variables to communicating with external programs. It also features a resources appendix and downloadable datasets and customization examples-tools that ensure swift and easy adoption. Find out how to r

  10. Materials for chairside CAD/CAM restorations.

    Science.gov (United States)

    Fasbinder, Dennis J

    2010-01-01

    Chairside computer-aided design/computer-aided manufacturing (CAD/CAM) systems have become considerably more accurate, efficient, and prevalent as the technology has evolved in the past 25 years. The initial restorative material option for chairside CAD/CAM restorations was limited to ceramic blocks. Restorative material options have multiplied and now include esthetic ceramics, high-strength ceramics, and composite materials for both definitive and temporary restoration applications. This article will review current materials available for chairside CAD/CAM restorations.

  11. Dataudveksling mellem CAD og CAE programmer

    DEFF Research Database (Denmark)

    Sørensen, Torben; Conrad, Finn

    2001-01-01

    Når mange forskelligartede programmer benyttes til beregninger og anden databehandling på samme modeller er det nødvendig at udveksle modellerne mellem disse forskellige programmer. Biler og skibe bliver f.eks. typisk designet i 3D CAD systemer, mens CAD modellerne herefter anvendes i andre...... dedikerede IT-systemer i forbindelse montageplanlægningen, svejseplanlægningen, robotprogrammeringen mm. der således her et behov for at udveksle CAD modellen mellem de forskellige programmer. Udveksling af information mellem forskellige programmer og systemer kræver såvel en fælles specifikation af det...

  12. Generalizacija linija i AutoCAD Map

    OpenAIRE

    Vučetić, Nada; Lapaine, Miljenko

    2001-01-01

    The paper offers the results of original research made on the application of AutoCAD Map in line generalisation. The differences and similarities have been found out between the Douglas-Peucker method and the method of line simplification that is incorporated in AutoCAD Map. There have been also the inaccuracies found out in AutoCAD Map manual relating to the issues of buffer width and tolerance, and the line width before and after simplification. The paper gives recommendations about pseudo ...

  13. Line Generalization and AutoCAD Map

    OpenAIRE

    Nada Vučetić; Miljenko Lapaine

    2001-01-01

    The paper offers the results of original research made on the application of AutoCAD Map in line generalisation. The differences and similarities have been found out between the Douglas-Peucker method and the method of line simplification that is incorporated in AutoCAD Map. There have been also the inaccuracies found out in AutoCAD Map manual relating to the issues of buffer width and tolerance, and the line width before and after simplification. The paper gives recommendations about pseudo ...

  14. A new data integration approach for AutoCAD and GIS

    Science.gov (United States)

    Ye, Hongmei; Li, Yuhong; Wang, Cheng; Li, Lijun

    2006-10-01

    GIS has its advantages both on spatial data analysis and management, particularly on the geometric and attributive information management, which has also attracted lots attentions among researchers around world. AutoCAD plays more and more important roles as one of the main data sources of GIS. Various work and achievements can be found in the related literature. However, the conventional data integration from AutoCAD to GIS is time-consuming, which also can cause the information loss both in the geometric aspects and the attributive aspects for a large system. It is necessary and urgent to sort out new approach and algorithm for the efficient high-quality data integration. In this paper, a novel data integration approach from AutoCAD to GIS will be introduced based on the spatial data mining technique through the data structure analysis both in the AutoCAD and GIS. A practicable algorithm for the data conversion from CAD to GIS will be given as well. By a designed evaluation scheme, the accuracy of the conversion both in the geometric and the attributive information will be demonstrated. Finally, the validity and feasibility of the new approach will be shown by an experimental analysis.

  15. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  16. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  17. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  18. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  19. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  20. Improving the radiologist-CAD interaction: designing for appropriate trust.

    Science.gov (United States)

    Jorritsma, W; Cnossen, F; van Ooijen, P M A

    2015-02-01

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the interaction between radiologists and the CAD system is not optimal. An important factor in the interaction between humans and automated aids (such as CAD) is trust. Suboptimal performance of the human-automation team is often caused by an inappropriate level of trust in the automation. In this review, we examine the role of trust in the radiologist-CAD interaction and suggest ways to improve the output of the CAD system so that it allows radiologists to calibrate their trust in the CAD system more effectively. Observer studies of the CAD systems show that radiologists often have an inappropriate level of trust in the CAD system. They sometimes under-trust CAD, thereby reducing its potential benefits, and sometimes over-trust it, leading to diagnostic errors they would not have made without CAD. Based on the literature on trust in human-automation interaction and the results of CAD observer studies, we have identified four ways to improve the output of CAD so that it allows radiologists to form a more appropriate level of trust in CAD. Designing CAD systems for appropriate trust is important and can improve the performance of the radiologist-CAD team. Future CAD research and development should acknowledge the importance of the radiologist-CAD interaction, and specifically the role of trust therein, in order to create the perfect artificial partner for the radiologist. This review focuses on the role of trust in the radiologist-CAD interaction. The aim of the review is to encourage CAD developers to design for appropriate trust and thereby improve the performance of the radiologist-CAD team. Copyright © 2014 The Royal College of Radiologists. Published by Elsevier Ltd

  1. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  2. CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation

    Directory of Open Access Journals (Sweden)

    Hussein CHIBLE,

    2013-10-01

    Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented

  3. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  4. Distortion of CAD-CAM-fabricated implant-fixed titanium and zirconia complete dental prosthesis frameworks.

    Science.gov (United States)

    Al-Meraikhi, Hadi; Yilmaz, Burak; McGlumphy, Edwin; Brantley, William A; Johnston, William M

    2017-05-03

    Computer-aided design and computer-aided manufacturing (CAD-CAM)-fabricated titanium and zirconia implant-supported fixed dental prostheses have become increasingly popular for restoring patients with complete edentulism. However, the distortion level of these frameworks is not well known. The purpose of this in vitro study was to compare the 3-dimensional (3D) distortion of CAD-CAM zirconia and titanium implant-fixed screw-retained complete dental prostheses. A master edentulous model with 4 implants at the positions of the maxillary first molars and canines was used. Multiunit abutments (Nobel Biocare) secured to the model were digitally scanned using scan bodies and a laboratory scanner (S600 ARTI; Zirkonzahn). Titanium (n=5) and zirconia (n=5) frameworks were milled using a CAD-CAM system (Zirkonzahn M1; Zirkonzahn). All frameworks were scanned using an industrial computed tomography (CT) scanner (Nikon/X-Tek XT H 225kV MCT Micro-Focus). The direct CT scans were reconstructed to generate standard tessellation language (STL) files. To calculate the 3D distortion of the frameworks, STL files of the CT scans were aligned to the CAD model using a sum of the least squares best-fit algorithm. Surface comparison points were placed on the CAD model on the midfacial aspect of all teeth. The 3D distortion of each direct scan to the CAD model was calculated. In addition, color maps of the scan-to-CAD comparison were constructed using a ±0.500 mm color scale range. Both materials exhibited distortion; however, no significant difference was found in the amount of distortion from the CAD model between the materials (P=.747). Absolute values of deviations from the CAD model were evident in the x and y plane and less so in the z direction. Zirconia and titanium frameworks showed similar 3D distortion compared with the CAD model for the tested CAD-CAM and implant systems. The distortion was more pronounced in the horizontal and sagittal plane than in the vertical plane

  5. AutoCAD 2008 and AutoCAD LT 2008 Bible

    CERN Document Server

    Finkelstein, Ellen

    2011-01-01

    "Whether you're new to AutoCAD or a veteran, you will undoubtedly find this book to be an excellent resource."-- Abhi Singh, AutoCAD Product Manager, Autodesk, Inc.Here's the book that makes AutoCAD approachableEven the people at Autodesk look to Ellen Finkelstein for AutoCAD training, so who better to teach you about AutoCAD 2008? This comprehensive guide brings veterans up to speed on AutoCAD updates and takes novices from the basics to programming in AutoLISP(r) and VBA. Every feature is covered in a logical order, and with the Quick Start chapter, you'll be creating drawings on your very f

  6. CADS:Cantera Aerosol Dynamics Simulator.

    Energy Technology Data Exchange (ETDEWEB)

    Moffat, Harry K.

    2007-07-01

    This manual describes a library for aerosol kinetics and transport, called CADS (Cantera Aerosol Dynamics Simulator), which employs a section-based approach for describing the particle size distributions. CADS is based upon Cantera, a set of C++ libraries and applications that handles gas phase species transport and reactions. The method uses a discontinuous Galerkin formulation to represent the particle distributions within each section and to solve for changes to the aerosol particle distributions due to condensation, coagulation, and nucleation processes. CADS conserves particles, elements, and total enthalpy up to numerical round-off error, in all of its formulations. Both 0-D time dependent and 1-D steady state applications (an opposing-flow flame application) have been developed with CADS, with the initial emphasis on developing fundamental mechanisms for soot formation within fires. This report also describes the 0-D application, TDcads, which models a time-dependent perfectly stirred reactor.

  7. AutoCAD 2013 and AutoCAD LT 2013 bible

    CERN Document Server

    Finkelstein, Ellen

    2012-01-01

    The bestselling guide to AutoCAD, fully updated for the 2013 version AutoCAD, the number one architectural drawing software, can be challenging to learn. This comprehensive guide has sold more than 160,000 copies in previous editions and is the go-to resource for architects, engineers, drafters, interior designers, and space planners who need to learn and use AutoCAD and AutoCAD LT. From the basics of creating drawings and using commands to 2D and 3D drawing techniques, using layers, rendering, and customizing the program, this book covers it all. A Quick Start guide allows eve

  8. Hardware acceleration of EDA algorithms custom ICS, FPGAs and GPUs

    CERN Document Server

    Khatri, Sunil P

    2010-01-01

    This text covers the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. In it, widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs.

  9. Field analysis and CAD millimeter wave VCO

    Science.gov (United States)

    Jiang, Xiao-Hong; Hong, Wei

    1992-12-01

    In this paper, the CAD of millimeter wave VCO is investigated based on a frequency-domain harmonic balance technique, where the external-circuit mutual impedances looking outside from two active devices are calculated in terms of a rigorous definition and a mixed technique of modes expansion, Galerkin method and collocation method. The CAD results are in agreement with the experimental results, which shows the raliability of the presented model and optimisation.

  10. AutoCAD-To-NASTRAN Translator Program

    Science.gov (United States)

    Jones, A.

    1989-01-01

    Program facilitates creation of finite-element mathematical models from geometric entities. AutoCAD to NASTRAN translator (ACTON) computer program developed to facilitate quick generation of small finite-element mathematical models for use with NASTRAN finite-element modeling program. Reads geometric data of drawing from Data Exchange File (DXF) used in AutoCAD and other PC-based drafting programs. Written in Microsoft Quick-Basic (Version 2.0).

  11. AutoCAD-To-NASTRAN Translator Program

    Science.gov (United States)

    Jones, A.

    1989-01-01

    Program facilitates creation of finite-element mathematical models from geometric entities. AutoCAD to NASTRAN translator (ACTON) computer program developed to facilitate quick generation of small finite-element mathematical models for use with NASTRAN finite-element modeling program. Reads geometric data of drawing from Data Exchange File (DXF) used in AutoCAD and other PC-based drafting programs. Written in Microsoft Quick-Basic (Version 2.0).

  12. VLSI technology for smaller, cheaper, faster return link systems

    Science.gov (United States)

    Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

    1994-01-01

    Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

  13. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  14. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  15. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  16. Modeling selective attention using a neuromorphic analog VLSI device.

    Science.gov (United States)

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  17. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  18. VLSI-based Video Event Triggering for Image Data Compression

    Science.gov (United States)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  19. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  20. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  1. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    Science.gov (United States)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  2. Replacing design rules in the VLSI design cycle

    Science.gov (United States)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  3. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  4. Accuracy Assessment for Cad Modeling of Freeform Surface Described by Equation

    Directory of Open Access Journals (Sweden)

    Golba Grzegorz

    2015-06-01

    Full Text Available This paper presents the results of comparative analysis of modeling accuracy the freeform surface constructed by using a variety of algorithms for surface modeling. Also determined the accuracy of mapping the theoretical freeform surface described by mathematical equation. To model surface objects used: SolidWorks 2012, CATIA v5 and Geomagic Studio 12. During the design process of CAD models were used: profile curves, fitting parametric surface and polygonal mesh. To assess the accuracy of the CAD models used Geomagic Qualify 12. On the basis of analyse defined the scope of application of each modeling techniques depending on the nature of the constructed object.

  5. CAD system for footwear design based on whole real 3D data of last surface

    Science.gov (United States)

    Song, Wanzhong; Su, Xianyu

    2000-10-01

    Two major parts of application of CAD in footwear design are studied: the development of last surface; computer-aided design of planar shoe-template. A new quasi-experiential development algorithm of last surface based on triangulation approximation is presented. This development algorithm consumes less time and does not need any interactive operation for precisely development compared with other development algorithm of last surface. Based on this algorithm, a software, SHOEMAKERTM, which contains computer aided automatic measurement, automatic development of last surface and computer aide design of shoe-template has been developed.

  6. Timing and Area Optimization for VLSI Circuit and Layout

    Science.gov (United States)

    1994-05-10

    eigenvalues and eigenvectors of the matrices derived from the graph. A graph can be represented by the adjacency matriz A(G).I aii, if (vi, vi) E E •j =. (4.2...Design, vol. CAD-10, pp. 356-365, Mar. 1991. 3 [65] T. Saaao, ed., Logic Synthesis and Optimization. Boston , Massachussetts: Kluwer, 1993. [661 Y.-C. Ju

  7. Web-based CAD and CAM for optomechatronics

    Science.gov (United States)

    Han, Min; Zhou, Hai-Guang

    2001-10-01

    CAD & CAM technologies are being used in design and manufacturing process, and are receiving increasing attention from industries and education. We have been researching to develop a new kind of software that is for web-course CAD & CAM. It can be used either in industries or in training, it is supported by IE. Firstly, we aim at CAD/CAM for optomechatronics. We have developed a kind of CAD/CAM, which is not only for mechanics but also for optics and electronic. That is a new kind of software in China. Secondly, we have developed a kind of software for web-course CAD & CAM, we introduce the basis of CAD, the commands of CAD, the programming, CAD/CAM for optomechatronics, the joint application of CAD & CAM. We introduce the functions of MasterCAM, show the whole processes of CAD/CAM/CNC by examples. Following the steps showed on the web, the trainer can not miss. CAD & CAM are widely used in many areas, development of web-course CAD & CAM is necessary for long- distance education and public education. In 1992, China raised: CAD technique, as an important part of electronic technology, is a new key technique to improve the national economic and the modernization of national defence. As so for, the education. Of CAD & CAM is mainly involved in manufacturing industry in China. But with the rapidly development of new technology, especially the development of optics and electronics, CAD & CAM will receive more attention from those areas.

  8. T-Algorithm-Based Logic Simulation on Distributed Systems

    OpenAIRE

    Sundaram, S; Patnaik, LM

    1992-01-01

    Increase in the complexity of VLSI digital circuit it sign demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulataon algorithms is by exploiting the inherent parallelism an the sequentaal versaon. In this paper, we explore the possibility of mapping a T-algoriihm based logac samulataon algorithm onto a cluster of workstation interconnected by an ethernet. The set of gates at a particular level as partitioned by the hias...

  9. Multi-Volume CAD Modeling for Heterogeneous Object Design and Fabrication

    Institute of Scientific and Technical Information of China (English)

    SUN Wei

    2000-01-01

    he current computer-aided technologies in design and product development, the evolution of CAD modeling, and a framework of multi-volume CAD modeling system for heterogeneous object design and fabrication are presented in this paper.The multi-volume CAD modeling system is presented based on nonmanifold topological elements. Material identifications are defined as design attributes introduced along with geometric and topological information at the design stage. Extended Euler operation and reasoning Boolean operations for merging and extraction are executed according to the associated material identifications in the developed multi-volume modeling system for heterogeneous object.An application example and a pseudo-processing algorithm for prototyping of heterogeneous structure through solid free-form fabrication are also described.1

  10. The design and integration of retinal CAD-SR to diabetes patient ePR system

    Science.gov (United States)

    Wu, Huiqun; Wei, Yufang; Liu, Brent J.; Shang, Yujuan; Shi, Lili; Jiang, Kui; Dong, Jiancheng

    2017-03-01

    Diabetic retinopathy (DR) is one of the serious complications of diabetes that could lead to blindness. Digital fundus camera is often used to detect retinal changes but the diagnosis relies too much on ophthalmologist's experience. Based on our previously developed algorithms for quantifying retinal vessels and lesions, we developed a computer aided detection-structured report (CAD-SR) template and implemented it into picture archiving and communication system (PACS). Furthermore, we mapped our CAD-SR into HL7 CDA to integrate CAD findings into diabetes patient electronic patient record (ePR) system. Such integration could provide more quantitative features from fundus image into ePR system, which is valuable for further data mining researches.

  11. AutoCAD 2012 and AutoCAD LT 2012 Bible

    CERN Document Server

    Finkelstein, Ellen

    2011-01-01

    The latest version of this perennial favorite, in-depth, reference-tutorial This top-selling book has been updated by AutoCAD guru and author Ellen Finkelstein to provide you with the very latest coverage of both AutoCAD 2012 and AutoCAD LT 2012. It begins with a Quick Start tutorial, so you start creating right away. From there, the book covers so much in-depth material on AutoCAD that it is said that even Autodesk employees keep this comprehensive book at their desks. A DVD is included that features before-and-after drawings of all the tutorials and plenty of great examples from AutoCAD prof

  12. Forecasting the Efficiency of Test Generation Algorithms for Combinational Circuits

    Institute of Scientific and Technical Information of China (English)

    徐拾义

    2000-01-01

    In this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit, choice of an algorithm from a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the Genetic Algorithm is used in order to construct an accurate model for some existing test generation algorithms that are being used everywhere in the world. Some objective quantitative measures are used as an effective tool in making such choice. Such measures are so important to the analysis of algorithms that they become one of the subjects of this work.

  13. A Contraction-based Ratio-cut Partitioning Algorithm

    Directory of Open Access Journals (Sweden)

    Youssef Saab

    2002-01-01

    Full Text Available Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, ratio-cut partitioning has received attention due to its tendency to partition circuits into their natural clusters. Node contraction has also been shown to enhance the performance of iterative partitioning algorithms. This paper describes a new simple ratio-cut partitioning algorithm using node contraction. This new algorithm combines iterative improvement with progressive cluster formation. Under suitably mild assumptions, the new algorithm runs in linear time. It is also shown that the new algorithm compares favorably with previous approaches.

  14. Ecodesigning with CAD Features: Analysis and Proposals

    Directory of Open Access Journals (Sweden)

    Raoudha Gaha

    2013-01-01

    Full Text Available The integration of environmental aspects in design frameworks has become a necessity for manufacturers to maintain their market position. This is especially true in the Computer Aided Design (CAD phase, which is the last phase in the design process. At this stage, more than 80% of choices have been made. However, the environmental impacts generated by the remaining choices are significant. Features Technology (FT, the core of the CAD phase, is used to integrate environmental aspects. This paper presents a literature review of different works based on FT to ecodesign products. First, we present an overview of features in CAD systems. Second, we present a critical review of works done on ecodesigning with features that we divide into two subsections: the first one concerns CAD-Life Cycle Assessment (LCA integration (methodologies, prototype tools, and commercial tools, and the second one, works using FT in CAD phase to reduce the environmental impact of one life cycle stage such as material selection or manufacturing. Finally, we propose an approach based on FT for ecodesigning products to promote simple new ecodesign tools which will help the inexperienced designer.

  15. 3D CAD Model Clustering and Retrieval Inspired by Fish Swarm%鱼群启发的三维 CAD 模型聚类与检索

    Institute of Scientific and Technical Information of China (English)

    皇甫中民; 张树生; 闫雒恒

    2016-01-01

    为了提高三维 CAD 模型检索中模型的局部细节区别能力以及检索效率,提出一种鱼群启发的三维 CAD 模型聚类及检索方法。依据 B-Rep 形式 CAD 模型的属性邻接图以及图谱理论,采用一种融合空间邻接关系的词袋模式作为模型的特征描述子,用于模型聚类与检索中的特征描述及相似性计算;针对模型聚类问题,受鱼群运动模式启发,提出基于全局公告信息引导及模糊 c 均值修正的人工鱼群聚类算法,将模型库空间聚类划分为若干子空间;模型检索采取两层检索机制:首先通过隶属度函数将索引模型定位至相应搜索子空间,然后在较小的子空间内进行相似性比较。实验结果表明,该方法的特征描述子能较好地区别模型局部细节特征,模型库聚类效果较好,检索质量和效率均有明显提高,可有效地支持 CAD 模型的重用。%In order to improve both the discriminative power for local regions of CAD model and the searching efficiency in 3D CAD model retrieval, a novel method for 3D CAD model clustering and retrieval is proposed inspired by fish swarm. According to the Attribute Adjacent Graph (AAG) of B-rep model and spectral graph the-ory, each CAD in library model is represented by a shape descriptor called as CAD Spatial Bag of Words (CMSBows), which is combined with the adjacent relations of the local regions of CAD model. An improved Ar-tificial Fish Swarm Algorithm (AFSA), based on the global bulletin board guiding and the fuzzy c means revising, is proposed to partition the global database into different model base. For model retrieval, a two-level searching mechanism is employed, i.e., the query model is classified into the corresponding sub model base using member-ship function, and then, the most similarity CAD model is retrieved in this limited scope. Experimental results show that the proposed feature descriptors improve the distinguishing

  16. Next Generation CAD/CAM/CAE Systems

    Science.gov (United States)

    Noor, Ahmed K. (Compiler); Malone, John B. (Compiler)

    1997-01-01

    This document contains presentations from the joint UVA/NASA Workshop on Next Generation CAD/CAM/CAE Systems held at NASA Langley Research Center in Hampton, Virginia on March 18-19, 1997. The presentations focused on current capabilities and future directions of CAD/CAM/CAE systems, aerospace industry projects, and university activities related to simulation-based design. Workshop attendees represented NASA, commercial software developers, the aerospace industry, government labs, and academia. The workshop objectives were to assess the potential of emerging CAD/CAM/CAE technology for use in intelligent simulation-based design and to provide guidelines for focused future research leading to effective use of CAE systems for simulating the entire life cycle of aerospace systems.

  17. Formal Management of CAD/CAM Processes

    Science.gov (United States)

    Kohlhase, Michael; Lemburg, Johannes; Schröder, Lutz; Schulz, Ewaryst

    Systematic engineering design processes have many aspects in common with software engineering, with CAD/CAM objects replacing program code as the implementation stage of the development. They are, however, currently considerably less formal. We propose to draw on the mentioned similarities and transfer methods from software engineering to engineering design in order to enhance in particular the reliability and reusability of engineering processes. We lay out a vision of a document-oriented design process that integrates CAD/CAM documents with requirement specifications; as a first step towards supporting such a process, we present a tool that interfaces a CAD system with program verification workflows, thus allowing for completely formalised development strands within a semi-formal methodology.

  18. Sharing the learning activity using intelligent CAD

    DEFF Research Database (Denmark)

    Duffy, S. M.; Duffy, Alex

    1996-01-01

    In this paper the need for Intelligent Computer Aided Design (Int.CAD) to jointly support design and learning assistance is introduced. The paper focuses on presenting and exploring the possibility of realizing ''learning'' assistance in Int.CAD by introducing a new concept called Shared Learning....... Shared Learning is proposed to empower CAD tools with more useful learning capabilities than that currently available and thereby provide a stronger interaction of learning between a designer and a computer. ''Controlled'' computational learning is proposed as a means whereby the Shared Learning concept...... can be realized. The viability of this new concept is explored by using a system called PERSPECT. PERSPECT is a preliminary numerical design tool aimed at supporting the effective utilization of numerical experiential knowledge in design. After a detailed discussion of PERSPECT's numerical design...

  19. AutoCAD platform customization user interface and beyond

    CERN Document Server

    Ambrosius, Lee

    2014-01-01

    Make AutoCAD your own with powerful personalization options Options for AutoCAD customization are typically the domain of administrators, but savvy users can perform their own customizations to personalize AutoCAD. Until recently, most users never thought to customize the AutoCAD platform to meet their specific needs, instead leaving it to administrators. If you are an AutoCAD user who wants to ramp up personalization options in your favorite software, AutoCAD Platform Customization: User Interface and Beyond is the perfect resource for you. Author Lee Ambrosius is recognized as a leader in Au

  20. Optical integration of CAD/CAM materials.

    Science.gov (United States)

    Güth, Jan-Frederik; Magne, Pascal

    The optical integration (OI) of monolithic CAD/CAM materials under 4 illuminations was evaluated using a standardized and clinically relevant method. Eighteen inlays were manufactured and placed (glycerin gel). Standardized photos were taken under 4 illuminations (neutral white light direct and indirect illumination, cross-polarized light, fluorescent light). Six evaluators defined the optical integration score (OIS) as the "visibility" of the restoration (0 = worst OI, 4 = optimal OI). The intact tooth served as control. The null hypothesis was that different illuminations did not influence the OI of CAD/CAM inlays. One-way ANOVA, followed by Scheffe's post hoc, was applied (P = 0.05). Neutral light direct illumination: OIS between 2.67 (IPS e.max CAD LT A1, ENAMIC A1) and 3.83 (IPS e.max CAD HT A1) with a mean of 3.28 (± 0.339). Indirect illumination: OIS from 1.00 (Paradigm MZ100 A1) to 2.41 (ENAMIC A1) with a mean of 1.88 (± 0.598). Fluorescent light: OIS between 0.75 and 3.25 with a mean of 1.67 (± 1.025). ENAMIC and VITA BLOCS Mark II showed the best optical integration in fluorescence. IPS e.max CAD, Paradigm MZ 100 demonstrated low fluorescence; Lava Ultimate high fluorescence. OI was influenced by different illumination. A simple method accessible to clinicians for additional evaluation of CAD/CAM materials in daily practice is presented. All materials showed excellent OI under direct illumination with neutral white light. The most pronounced differences in optical integration between tooth and evaluated materials were observed under fluorescent light.

  1. TinkerCell: modular CAD tool for synthetic biology

    Directory of Open Access Journals (Sweden)

    Bergmann Frank T

    2009-10-01

    Full Text Available Abstract Background Synthetic biology brings together concepts and techniques from engineering and biology. In this field, computer-aided design (CAD is necessary in order to bridge the gap between computational modeling and biological data. Using a CAD application, it would be possible to construct models using available biological "parts" and directly generate the DNA sequence that represents the model, thus increasing the efficiency of design and construction of synthetic networks. Results An application named TinkerCell has been developed in order to serve as a CAD tool for synthetic biology. TinkerCell is a visual modeling tool that supports a hierarchy of biological parts. Each part in this hierarchy consists of a set of attributes that define the part, such as sequence or rate constants. Models that are constructed using these parts can be analyzed using various third-party C and Python programs that are hosted by TinkerCell via an extensive C and Python application programming interface (API. TinkerCell supports the notion of a module, which are networks with interfaces. Such modules can be connected to each other, forming larger modular networks. TinkerCell is a free and open-source project under the Berkeley Software Distribution license. Downloads, documentation, and tutorials are available at http://www.tinkercell.com. Conclusion An ideal CAD application for engineering biological systems would provide features such as: building and simulating networks, analyzing robustness of networks, and searching databases for components that meet the design criteria. At the current state of synthetic biology, there are no established methods for measuring robustness or identifying components that fit a design. The same is true for databases of biological parts. TinkerCell's flexible modeling framework allows it to cope with changes in the field. Such changes may involve the way parts are characterized or the way synthetic networks are modeled

  2. AutoCAD 2012 and AutoCAD LT 2012 No Experience Required

    CERN Document Server

    Gladfelter, Donnie

    2011-01-01

    The perfect step-by-step introduction to Autodesk's powerful architectural design software With this essential guide, you'll learn how to plan, develop, document, and present a complete AutoCAD project by building a summer cabin from start to finish. You can follow each step sequentially or jump in at any point by downloading the drawing files from the book's companion web site. You'll also master all essential AutoCAD features, get a thorough grounding in the basics, learn the very latest industry standards and techniques, and quickly become productive with AutoCAD 2012.Features concise expla

  3. AutoCAD 2015 and AutoCAD LT 2015 essentials

    CERN Document Server

    Onstott, Scott

    2014-01-01

    Step-by-step instructions for the AutoCAD fundamentals AutoCAD 2015 Essentials contains 400 pages of full-color, comprehensive instruction on the world's top drafting and architecture software. This 2015 edition features architectural, manufacturing, and landscape architecture examples. And like previous editions, the detailed guide introduces core concepts using interactive tutorials and open-ended projects, which can be completed in any order, thanks to downloadable data sets (an especially useful feature for students and professionals studying for Autodesk AutoCAD certification). Unlike man

  4. Exploration on the Integration of CAD Course and National CAD Grade Certi-fication Training

    Institute of Scientific and Technical Information of China (English)

    ZHANG Ting-ting; SHI Feng-qin

    2013-01-01

    Based on the syllabus and standard of National CAD Grade Certification issued by the Ministry of Education and China Figure Association, this paper discusses the teaching model of combining classroom teaching with skill grade certification in voca-tional college. To achieve the unity of classroom teaching and skill training can save training costs and increase the significance of classroom teaching. Implementation of integrating mechanical CAD curriculum and national CAD grade certification training is the extension of teaching reform. It can make the vocational college students obtain the professional qualification certificates besides di-plomas.

  5. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  6. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  7. High-energy heavy ion testing of VLSI devices for single event upsets and latch up

    Indian Academy of Sciences (India)

    S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra

    2005-08-01

    Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.

  8. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  9. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    Science.gov (United States)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  10. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  11. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    Directory of Open Access Journals (Sweden)

    D.Yammenavar

    2011-08-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.

  12. Design and Analog VLSI Implementation of Artificial Neural Network

    Directory of Open Access Journals (Sweden)

    Prof. Bapuray.D.Yammenavar

    2011-07-01

    Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.

  13. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  14. CAD system for automatic analysis of CT perfusion maps

    Science.gov (United States)

    Hachaj, T.; Ogiela, M. R.

    2011-03-01

    In this article, authors present novel algorithms developed for the computer-assisted diagnosis (CAD) system for analysis of dynamic brain perfusion, computer tomography (CT) maps, cerebral blood flow (CBF), and cerebral blood volume (CBV). Those methods perform both quantitative analysis [detection and measurement and description with brain anatomy atlas (AA) of potential asymmetries/lesions] and qualitative analysis (semantic interpretation of visualized symptoms). The semantic interpretation (decision about type of lesion: ischemic/hemorrhagic, is the brain tissue at risk of infraction or not) of visualized symptoms is done by, so-called, cognitive inference processes allowing for reasoning on character of pathological regions based on specialist image knowledge. The whole system is implemented in.NET platform (C# programming language) and can be used on any standard PC computer with.NET framework installed.

  15. Pipe Drafting with CAD. Teacher Edition.

    Science.gov (United States)

    Smithson, Buddy

    This teacher's guide contains nine units of instruction for a course on computer-assisted pipe drafting. The course covers the following topics: introduction to pipe drafting with CAD (computer-assisted design); flow diagrams; pipe and pipe components; valves; piping plans and elevations; isometrics; equipment fabrication drawings; piping design…

  16. DeviceEditor visual biological CAD canvas

    Directory of Open Access Journals (Sweden)

    Chen Joanna

    2012-02-01

    Full Text Available Abstract Background Biological Computer Aided Design (bioCAD assists the de novo design and selection of existing genetic components to achieve a desired biological activity, as part of an integrated design-build-test cycle. To meet the emerging needs of Synthetic Biology, bioCAD tools must address the increasing prevalence of combinatorial library design, design rule specification, and scar-less multi-part DNA assembly. Results We report the development and deployment of web-based bioCAD software, DeviceEditor, which provides a graphical design environment that mimics the intuitive visual whiteboard design process practiced in biological laboratories. The key innovations of DeviceEditor include visual combinatorial library design, direct integration with scar-less multi-part DNA assembly design automation, and a graphical user interface for the creation and modification of design specification rules. We demonstrate how biological designs are rendered on the DeviceEditor canvas, and we present effective visualizations of genetic component ordering and combinatorial variations within complex designs. Conclusions DeviceEditor liberates researchers from DNA base-pair manipulation, and enables users to create successful prototypes using standardized, functional, and visual abstractions. Open and documented software interfaces support further integration of DeviceEditor with other bioCAD tools and software platforms. DeviceEditor saves researcher time and institutional resources through correct-by-construction design, the automation of tedious tasks, design reuse, and the minimization of DNA assembly costs.

  17. A Case Study in CAD Design Automation

    Science.gov (United States)

    Lowe, Andrew G.; Hartman, Nathan W.

    2011-01-01

    Computer-aided design (CAD) software and other product life-cycle management (PLM) tools have become ubiquitous in industry during the past 20 years. Over this time they have continuously evolved, becoming programs with enormous capabilities, but the companies that use them have not evolved their design practices at the same rate. Due to the…

  18. The BRL-CAD Package: An Overview

    Science.gov (United States)

    2013-04-01

    TERMS NURBS BSpline, raytracing , CSG, BRL-CAD 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT UU 18. NUMBER OF PAGES 14 19a...Definition and Raytracing of B-spline Objects in a Combinatorial Solid Geometric Modeling System," USENIX: Proceeding of the Fourth Computer Graphics

  19. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  20. Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.

    Science.gov (United States)

    Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak

    2007-07-23

    In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.

  1. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Energy Technology Data Exchange (ETDEWEB)

    Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))

    1993-08-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.

  2. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    CERN Document Server

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  3. A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level

    Institute of Scientific and Technical Information of China (English)

    胡谋

    1992-01-01

    A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.

  4. Using AutoCAD to improve the visibility of the organizational technological design

    Directory of Open Access Journals (Sweden)

    Lebedeva Irina Mikhailovna

    2014-01-01

    Full Text Available The article describes the issue of increasing the visibility of technological solutions in organizational-technological design. The ability to visualize the main stages of building process technology contributes to organic integration of all the requirements. A special role for the harmonious perception is played by correct display of the lighting facilities, shadowing. Realistic shadows help to analyze the rooms’ insolation of the designed facility and the surrounding areas. We give a justification for the use of AutoCAD in order to automate the process of visualizing the results of organizational-technological design. The author describes the methods of obtaining realistic natural lighting in AutoCAD without significantly increasing the complexity of the process. Engineering companies in 46 % of cases use the software AutoCAD in order to create construction plans. AutoCAD has a variety of possibilities and is constantly evolving. Continuation is one of the benefits of this program. AutoCAD is unique in terms of customization, because, apart from instruction languages, it has two built-in programming languages: AutoLISP and VisualBasic. Because of these specific features AutoCAD allows to create any applications related to graphics implementation. Constant monitoring of lightning changes allows finding the appropriate in terms of aesthetics, ergonomics and insolation decisions on planning and associating a building or structure to the environment. Solar lighting is simulated by a combination of several directional lightning point sources. The author offers a brief description of the program algorithm, which allows automatically managing lighting settings and creating a file with a realistic visualization of the design solutions.

  5. A CAD of fully automated colonic polyp detection for contrasted and non-contrasted CT scans.

    Science.gov (United States)

    Tulum, Gökalp; Bolat, Bülent; Osman, Onur

    2017-04-01

    Computer-aided detection (CAD) systems are developed to help radiologists detect colonic polyps over CT scans. It is possible to reduce the detection time and increase the detection accuracy rates by using CAD systems. In this paper, we aimed to develop a fully integrated CAD system for automated detection of polyps that yields a high polyp detection rate with a reasonable number of false positives. The proposed CAD system is a multistage implementation whose main components are: automatic colon segmentation, candidate detection, feature extraction and classification. The first element of the algorithm includes a discrete segmentation for both air and fluid regions. Colon-air regions were determined based on adaptive thresholding, and the volume/length measure was used to detect air regions. To extract the colon-fluid regions, a rule-based connectivity test was used to detect the regions belong to the colon. Potential polyp candidates were detected based on the 3D Laplacian of Gaussian filter. The geometrical features were used to reduce false-positive detections. A 2D projection image was generated to extract discriminative features as the inputs of an artificial neural network classifier. Our CAD system performs at 100% sensitivity for polyps larger than 9 mm, 95.83% sensitivity for polyps 6-10 mm and 85.71% sensitivity for polyps smaller than 6 mm with 5.3 false positives per dataset. Also, clinically relevant polyps ([Formula: see text]6 mm) were identified with 96.67% sensitivity at 1.12 FP/dataset. To the best of our knowledge, the novel polyp candidate detection system which determines polyp candidates with LoG filters is one of the main contributions. We also propose a new 2D projection image calculation scheme to determine the distinctive features. We believe that our CAD system is highly effective for assisting radiologist interpreting CT.

  6. Developing a visual sensitive image features based CAD scheme to assist classification of mammographic masses

    Science.gov (United States)

    Wang, Yunzhi; Aghaei, Faranak; Tan, Maxine; Qiu, Yuchen; Liu, Hong; Zheng, Bin

    2017-03-01

    Computer-aided diagnosis (CAD) schemes of mammograms have been previously developed and tested. However, due to using "black-box" approaches with a large number of complicated features, radiologists have lower confidence to accept or consider CAD-cued results. In order to help solve this issue, this study aims to develop and evaluate a new CAD scheme that uses visual sensitive image features to classify between malignant and benign mammographic masses. A dataset of 301 masses detected on both craniocaudal (CC) and mediolateraloblique (MLO) view images was retrospectively assembled. Among them, 152 were malignant and 149 were benign. An iterative region-growing algorithm was applied to the special Gaussian-kernel filtered images to segment mass regions. Total 13 Image features were computed to mimic 5 categories of visually sensitive features that are commonly used by radiologists in classifying suspicious mammographic masses namely, mass size, shape factor, contrast, homogeneity and spiculation. We then selected one optimal feature in each of 5 feature categories by using a student t-test, and applied two logistic regression classifiers using either CC or MLO view images to distinguish between malignant and benign masses. Last, a fusion method of combining two classification scores was applied and tested. By applying a 10-fold cross-validation method, the area under receiver operating characteristic curves was 0.806+/-0.025. This study demonstrated a new approach to develop CAD scheme based on 5 visually sensitive image features. Combining with a "visual-aid" interface, CAD results are much more easily explainable to the observers and may increase their confidence to consider CAD-cued results.

  7. CAD/CAM. High-Technology Training Module.

    Science.gov (United States)

    Zuleger, Robert

    This high technology training module is an advanced course on computer-assisted design/computer-assisted manufacturing (CAD/CAM) for grades 11 and 12. This unit, to be used with students in advanced drafting courses, introduces the concept of CAD/CAM. The content outline includes the following seven sections: (1) CAD/CAM software; (2) computer…

  8. Education and Training Packages for CAD/CAM.

    Science.gov (United States)

    Wright, I. C.

    1986-01-01

    Discusses educational efforts in the fields of Computer Assisted Design and Manufacturing (CAD/CAM). Describes two educational training initiatives underway in the United Kingdom, one of which is a resource materials package for teachers of CAD/CAM at the undergraduate level, and the other a training course for managers of CAD/CAM systems. (TW)

  9. Current techniques in CAD/CAM denture fabrication.

    Science.gov (United States)

    Baba, Nadim Z; AlRumaih, Hamad S; Goodacre, Brian J; Goodacre, Charles J

    2016-01-01

    Recently, the use of computer-aided design/computer-aided manufacturing (CAD/CAM) to produce complete dentures has seen exponential growth in the dental market, and the number of commercially available CAD/CAM denture systems grows every year. The purpose of this article is to describe the clinical and laboratory procedures of 5 CAD/CAM denture systems.

  10. Improving the radiologist-CAD interaction : designing for appropriate trust

    NARCIS (Netherlands)

    Jorritsma, W.; Cnossen, F.; van Ooijen, P. M. A.

    2015-01-01

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the

  11. Improving the radiologist-CAD interaction: designing for appropriate trust

    NARCIS (Netherlands)

    Jorritsma, W; Cnossen, F; van Ooijen, P M A

    2015-01-01

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the

  12. Fra form-Z til AutoCad

    DEFF Research Database (Denmark)

    Jensen, Henrik

    2003-01-01

    Dette kursus er lavet for at forberede de studerende til deres tegnestuepraktik, og dets indhold er planlagt i samarbejde med tegnestuerne. I 2003 var form-Z Arkitektskolens grundlæggende CAD-program; men på tegnestuerne arbejde man med AutoCad. Kurset er opbygget over CAD Clasic skabelonen (se min...

  13. Improving the radiologist-CAD interaction : designing for appropriate trust

    NARCIS (Netherlands)

    Jorritsma, W.; Cnossen, F.; van Ooijen, P. M. A.

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the

  14. A CAD (Classroom Assessment Design) of a Computer Programming Course

    Science.gov (United States)

    Hawi, Nazir S.

    2012-01-01

    This paper presents a CAD (classroom assessment design) of an entry-level undergraduate computer programming course "Computer Programming I". CAD has been the product of a long experience in teaching computer programming courses including teaching "Computer Programming I" 22 times. Each semester, CAD is evaluated and modified…

  15. Improving the radiologist-CAD interaction : designing for appropriate trust

    NARCIS (Netherlands)

    Jorritsma, W.; Cnossen, F.; van Ooijen, P. M. A.

    2015-01-01

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the

  16. Improving the radiologist-CAD interaction: designing for appropriate trust

    NARCIS (Netherlands)

    Jorritsma, W; Cnossen, F; van Ooijen, P M A

    2015-01-01

    Computer-aided diagnosis (CAD) has great potential to improve radiologists' diagnostic performance. However, the reported performance of the radiologist-CAD team is lower than what might be expected based on the performance of the radiologist and the CAD system in isolation. This indicates that the

  17. Computer-aided diagnosis (CAD) of subsolid nodules: Evaluation of a commercial CAD system.

    Science.gov (United States)

    Benzakoun, Joseph; Bommart, Sébastien; Coste, Joël; Chassagnon, Guillaume; Lederlin, Mathieu; Boussouar, Samia; Revel, Marie-Pierre

    2016-10-01

    To evaluate the performance of a commercially available CAD system for automated detection and measurement of subsolid nodules. The CAD system was tested on 50 pure ground-glass and 50 part-solid nodules (median diameter: 17mm) previously found on standard-dose CT scans in 100 different patients. True nodule detection and the total number of CAD marks were evaluated at different sensitivity settings. The influence of nodule and CT acquisition characteristics was analyzed with logistic regression. Software and manually measured diameters were compared with Spearman and Bland-Altman methods. With sensitivity adjusted for 3-mm nodule detection, 50/100 (50%) subsolid nodules were detected, at the average cost of 17 CAD marks per CT. These figures were respectively 26/100 (26%) and 2 at the 5-mm setting. At the highest sensitivity setting (2-mm nodule detection), the average number of CAD marks per CT was 41 but the nodule detection rate only increased to 54%. Part-solid nodules were better detected than pure ground glass nodules: 36/50 (72%) versus 14/50 (28%) at the 3-mm setting (pCAD system was insufficient, but high-quality segmentation was obtained in 79% of cases, allowing automated measurement of size and attenuation. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

  18. Machinability of CAD-CAM materials.

    Science.gov (United States)

    Chavali, Ramakiran; Nejat, Amir H; Lawson, Nathaniel C

    2017-08-01

    Although new materials are available for computer-aided design and computer-aided manufacturing (CAD-CAM) fabrication, limited information is available regarding their machinability. The depth of penetration of a milling tool into a material during a timed milling cycle may indicate its machinability. The purpose of this in vitro study was to compare the tool penetration rate for 2 polymer-containing CAD-CAM materials (Lava Ultimate and Enamic) and 2 ceramic-based CAD-CAM materials (e.max CAD and Celtra Duo). The materials were sectioned into 4-mm-thick specimens (n=5/material) and polished with 320-grit SiC paper. Each specimen was loaded into a custom milling apparatus. The apparatus pushed the specimens against a milling tool (E4D Tapered 2016000) rotating at 40 000 RPM with a constant force of 0.98 N. After a 6-minute timed milling cycle, the length of each milling cut was measured with image analysis software under a digital light microscope. Representative specimens and milling tools were examined with scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy. The penetration rate of Lava Ultimate (3.21 ±0.46 mm/min) and Enamic (2.53 ±0.57 mm/min) was significantly greater than that of e.max CAD (1.12 ±0.32 mm/min) or Celtra Duo (0.80 ±0.21 mm/min) materials. SEM observations showed little tool damage, regardless of material type. Residual material was found on the tools used with polymer-containing materials, and wear of the embedding medium was seen on the tools used with the ceramic-based materials. Edge chipping was noted on cuts made in the ceramic-based materials. Lava Ultimate and Enamic have greater machinability and less edge chipping than e.max CAD and Celtra Duo. Copyright © 2016 Editorial Council for the Journal of Prosthetic Dentistry. Published by Elsevier Inc. All rights reserved.

  19. AutoCAD 2014 review for certification official certification preparation

    CERN Document Server

    ASCENT center for technical knowledge

    2014-01-01

    The AutoCAD® 2014 Review for Certification book is intended for users of AutoCAD® preparing to complete the AutoCAD 2014 Certified Professional exam. This book contains a collection of relevant instructional topics, practice exercises, and review questions from the Autodesk Official Training Guides (AOTG) from ASCENT - Center for Technical Knowledge pertaining specifically to the Certified Professional exam topics and objectives. This book is intended for experienced users of AutoCAD in preparation for certification. New users of AutoCAD should refer to the AOTG training guides from ASCENT, such as AutoCAD/AutoCAD LT 2014 Fundamentals, for more comprehensive instruction.

  20. A fast lightstripe rangefinding system with smart VLSI sensor

    Science.gov (United States)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  1. A new computationally efficient CAD system for pulmonary nodule detection in CT imagery.

    Science.gov (United States)

    Messay, Temesguen; Hardie, Russell C; Rogers, Steven K

    2010-06-01

    Early detection of lung nodules is extremely important for the diagnosis and clinical management of lung cancer. In this paper, a novel computer aided detection (CAD) system for the detection of pulmonary nodules in thoracic computed tomography (CT) imagery is presented. The paper describes the architecture of the CAD system and assesses its performance on a publicly available database to serve as a benchmark for future research efforts. Training and tuning of all modules in our CAD system is done using a separate and independent dataset provided courtesy of the University of Texas Medical Branch (UTMB). The publicly available testing dataset is that created by the Lung Image Database Consortium (LIDC). The LIDC data used here is comprised of 84 CT scans containing 143 nodules ranging from 3 to 30mm in effective size that are manually segmented at least by one of the four radiologists. The CAD system uses a fully automated lung segmentation algorithm to define the boundaries of the lung regions. It combines intensity thresholding with morphological processing to detect and segment nodule candidates simultaneously. A set of 245 features is computed for each segmented nodule candidate. A sequential forward selection process is used to determine the optimum subset of features for two distinct classifiers, a Fisher Linear Discriminant (FLD) classifier and a quadratic classifier. A performance comparison between the two classifiers is presented, and based on this, the FLD classifier is selected for the CAD system. With an average of 517.5 nodule candidates per case/scan (517.5+/-72.9), the proposed front-end detector/segmentor is able to detect 92.8% of all the nodules in the LIDC/testing dataset (based on merged ground truth). The mean overlap between the nodule regions delineated by three or more radiologists and the ones segmented by the proposed segmentation algorithm is approximately 63%. Overall, with a specificity of 3 false positives (FPs) per case/patient on

  2. Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

    Science.gov (United States)

    Offord, Bruce W.

    1992-01-01

    In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

  3. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  4. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    CERN Document Server

    Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A

    1999-01-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  5. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    Science.gov (United States)

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  6. A VLSI analog pipeline read-out for electrode segmented ionization chambers

    Science.gov (United States)

    Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.

    1999-05-01

    We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.

  7. AutoCAD-To-GIFTS Translator Program

    Science.gov (United States)

    Jones, Andrew

    1989-01-01

    AutoCAD-to-GIFTS translator program, ACTOG, developed to facilitate quick generation of small finite-element models using CASA/GIFTS finite-element modeling program. Reads geometric data of drawing from Data Exchange File (DXF) used in AutoCAD and other PC-based drafting programs. Geometric entities recognized by ACTOG include points, lines, arcs, solids, three-dimensional lines, and three-dimensional faces. From this information, ACTOG creates GIFTS SRC file, which then reads into GIFTS preprocessor BULKM or modified and reads into EDITM to create finite-element model. SRC file used as is or edited for any number of uses. Written in Microsoft Quick-Basic (Version 2.0).

  8. AutoCAD-To-GIFTS Translator Program

    Science.gov (United States)

    Jones, Andrew

    1989-01-01

    AutoCAD-to-GIFTS translator program, ACTOG, developed to facilitate quick generation of small finite-element models using CASA/GIFTS finite-element modeling program. Reads geometric data of drawing from Data Exchange File (DXF) used in AutoCAD and other PC-based drafting programs. Geometric entities recognized by ACTOG include points, lines, arcs, solids, three-dimensional lines, and three-dimensional faces. From this information, ACTOG creates GIFTS SRC file, which then reads into GIFTS preprocessor BULKM or modified and reads into EDITM to create finite-element model. SRC file used as is or edited for any number of uses. Written in Microsoft Quick-Basic (Version 2.0).

  9. CAD Integration : new optical design possibilities

    Science.gov (United States)

    Haumonte, Jean-Baptiste; Venturino, Jean-Claude

    2005-09-01

    The development of optical design and analysis tools in a CAD software can help to optimise the design, size and performance of tomorrow's consumer products. While optics was still held back by software limitations, CAD programs were moving forward in leaps and bounds, improving manufacturing technologies and making it possible to design and produce highly innovative and sophisticated products. The problem was that in the past, 'traditional' optical design programs were only able to simulate spherical and aspherical lenses, meaning that the optical designers were limited to designing systems which were a series of imperfect lenses, each one correcting the last. That is why OPTIS has created the first optical design program to be fully integrated into a CAD program. The technology is available from OPTIS in an integrated SOLIDWORKS or CATIA V5 version. Users of this software can reduce the number of lenses needed in a system. Designers will now have access to complex surfaces such as NURBS meaning they will now be able to define free shape progressive lenses and even improve on optical performances using fewer lenses. This revolutionary technology will allow mechanical designers to work on optical systems and to share information with optical designers for the first time. Previously not possible in a CAD program you may now determine all the optical performances of any optical system, providing first order and third order performances, sequential and non-sequential ray-tracing, wavefront surfaces, point spread function, MTF, spot-diagram, using real optical surfaces and guaranteeing the mechanical precision necessary for an optical system.

  10. KiCad challenges the big ones

    CERN Multimedia

    Antonella Del Rosso

    2015-01-01

    Printed Circuit Boards (PCB) are the heart of any electronic device, including your toaster and your smartphone. Designing PCBs is the job of electronic engineers who, so far, have often had no option but to use proprietary tools to design complex circuits. Thanks to the efforts that CERN experts have put in to improve the free KiCad software, that situation is about to change.   KiCad's development started in 1992 as a way to design PCBs, the units that control how an electronic device works. Since 2013, experts in the Beams department have made important contributions to KiCad as part of the Open Hardware Initiative (OHI), which provides a framework to facilitate knowledge exchange across the electronic design community. “Our vision is to allow the hardware developers to share as easily as their software colleagues,” says Javier Serrano, head of the BE-CO-HT section and OHI initiator. “Software sources are easily shared online because they are text ...

  11. TEACHING CAD PROGRAMMING TO ARCHITECTURE STUDENTS

    Directory of Open Access Journals (Sweden)

    Maria Gabriela Caffarena CELANI

    2008-11-01

    Full Text Available The objective of this paper is to discuss the relevance of including the discipline of computer programming in the architectural curriculum. To do so I start by explaining how computer programming has been applied in other educational contexts with pedagogical success, describing Seymour Papert's principles. After that, I summarize the historical development of CAD and provide three historical examples of educational applications of computer programming in architecture, followed by a contemporary case that I find of particular relevance. Next, I propose a methodology for teaching programming for architects that aims at improving the quality of designs by making their concepts more explicit. This methodology is based on my own experience teaching computer programming for architecture students at undergraduate and graduate levels at the State University of Campinas, Brazil. The paper ends with a discussion about the role of programming nowadays, when most CAD software are user-friendly and do not require any knowledge of programming for improving performance. I conclude that the introduction of programming in the CAD curriculum within a proper conceptual framework may transform the concept of architectural education. Key-words: Computer programming; computer-aided design; architectural education.

  12. Dataudveksling mellem CAD og CAE programmer

    DEFF Research Database (Denmark)

    Sørensen, Torben; Conrad, Finn

    2001-01-01

    Når mange forskelligartede programmer benyttes til beregninger og anden databehandling på samme modeller er det nødvendig at udveksle modellerne mellem disse forskellige programmer. Biler og skibe bliver f.eks. typisk designet i 3D CAD systemer, mens CAD modellerne herefter anvendes i andre...... dedikerede IT-systemer i forbindelse montageplanlægningen, svejseplanlægningen, robotprogrammeringen mm. der således her et behov for at udveksle CAD modellen mellem de forskellige programmer. Udveksling af information mellem forskellige programmer og systemer kræver såvel en fælles specifikation af det...... modellen knyttede data vokser når denne benyttes i flere forskellige systemer. Ideelt set må sådanne digitale modeldata derfor indeholde nok information til at dække hele modellens "livs cyklus", afhængig af anvendelsen kan dette omfatte alle data fra design til analyse, evt. produktion, kvalitetskontrol...

  13. Multifunctional facades - design optimisation with CAD; Multifunktionale Fassaden - Effektive Auslegung durch CAD-Einsatz

    Energy Technology Data Exchange (ETDEWEB)

    Viotto, M. [Institut fuer Solare Energieversorgungstechnik (ISET), Kassel (Germany). Abt. fuer Anlagen- und Messtechnik

    1998-02-01

    The energetically optimal design of PV facades requires the consideration of many technical conditions (different elevations/orientations of modules; shading possibility; high and different module temperatures). It also requires the interface with architecture, civil and electrical engineering. To support this planning process, the software program PV-CAD was developed which rapidly calculates energy yield under conditions of inhomogeneous irradiance, shading, thermal behaviour of modules and electrical layout. PV-CAD is compatible with other civil and electrical engineering CAD programs and incorporates extensive databases (weather data; modules and inverter types). (orig.) [Deutsch] Fuer optimalen Energieertrag sind zahlreiche technische Randbedingungen bei der Auslegung einer Photovoltaik (PV)-Fassade zu beruecksichtigen (unterschiedliche Ausrichtungen/Neigungen der Module; moegliche Teilabschattung; hoehere und unterschiedliche Betriebstemperaturen). Installation und Betrieb einer PV-Fassade erfordern die Abstimmung zwischen Architektur, Bauwesen und Elektrotechnik. Zur Unterstuetzung der Planer wurde das Programm PV-CAD entwickelt, das den Energieertrag unter Beruecksichtigung von inhomogener Einstrahlung und Abschattung, Temperaturverhalten der Fassadenmodule sowie unterschiedlichen elektrischen Anlagenkonzepten schnell ermittelt; es fuegt sich nahtlos in CAD-Arbeitsumgebungen ein. (orig.)

  14. Pre-defined wire length support in TopoR CAD

    Directory of Open Access Journals (Sweden)

    Lysenko A. A.

    2009-08-01

    Full Text Available This article introduces mathematical models and algorithm for calculation of wire shapes of specified length, which are inscribed in an arbitrary trapezium. This helps to save workspace, which is especially important for any-angle routing. The presented algorithm allows to maintain the defined wire length with a maximum tolerance of 50 nm. For compatibility with CAD formats that do not support arc-shaped wires, TopoR creates approximated snake-like connections made up of straight lines only.

  15. A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

    Science.gov (United States)

    Richstein, James K.

    1993-12-01

    Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.

  16. Accurate and Precise Computation Using Analog VLSI, with Applications to Computer Graphics and Neural Networks.

    Science.gov (United States)

    Kirk, David Blair

    This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for

  17. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Science.gov (United States)

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  18. FaSa: A Fast and Stable Quadratic Placement Algorithm

    Institute of Scientific and Technical Information of China (English)

    HOU WenTing(侯文婷); HONG XianLong(洪先龙); WU WeiMin(吴为民); CAI YiCi(蔡懿慈)

    2003-01-01

    Placement is a critical step in VLSI design because it dominates overall speed andquality of design flow. In this paper, a new fast and stable placement algorithm called FaSa is pro-posed. It uses quadratic programming model and Lagrange multiplier method to solve placementproblems. And an incremental LU factorization method is used to solve equations for speeding up.The experimental results show that FaSa is very stable, much faster than previous algorithms andits total wire length is comparable with other algorithms.

  19. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  20. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  1. VLSI Architecture Of A Binary Up/Down Counter

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie; Reed, I. S.

    1988-01-01

    Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.

  2. 箱体类零件的特征识别和CAD/CAPP集成%Feature recognition for box-type parts and CAD/CAPP integration

    Institute of Scientific and Technical Information of China (English)

    曾顺; 张璐; 周雄辉

    2013-01-01

    为充分利用已有的设计信息,实现设计信息到制造信息的快速转换,针对箱体类零件的几何特点,提出以面为中心的,基于痕迹与规则的混合特征识别算法.实例证明,该文的识别算法能够有效识别箱体类零件中的常用加工特征,并在开发的CAD/CAPP集成系统中利用遗传算法实现了对所获取的特征信息的充分利用,制定出合理的工艺路线.CAD/CAPP集成技术能够有效地缩短产品开发周期,提高工艺人员的工作效率,降低成本.%In order to fully utilize the existing design information and realize the transition from design information to manufacturing information,according to geometric characteristics of box-type parts,this paper focuses on surface and proposes a rule and hint based hybrid recognition method,which,as proved,effectively realizes the common machining feature recognition,and the developed CAD/CAPP integrated system achieves full use of the acquired feature information using genetic algorithm and can effectively develop a reasonable process.The CAD/CAPP integration technology can effectively shorten the product development cycle,while improving the efficiency of the process engineer to reduce costs.

  3. Object-oriented CAD data-base support for software reusability in computer-aided software engineering environments

    Energy Technology Data Exchange (ETDEWEB)

    Poulin, J.S.

    1989-01-01

    There is currently a large research effort underway to develop new techniques and methods for the efficient development of software. However, much of this effort ignores the vast sum of knowledge that has been acquired through the experiences in the field of engineering CAD, especially in the area of VLSI design. Much of what has been learned in this area centers on database support for the design process, and in particular, efficient object-oriented modeling techniques for software design data. It is believed that the data model for software is a central issue surrounding the development of CASE systems. Recognizing that great gains in software productivity will be realized only when software developed for one application is reused in subsequent applications, it is necessary to consider ways to support reuse through the data model used in these CASE environments. Awareness of these reusability issues has led to the development of a new object-oriented semantic data model for use in CASE environments. The proposed semantic data model for software is based on the molecular object model used in CAD, but has been enhanced to capture and support more of the software development cycle. The model differs from the molecular object model in that where the molecular model defines an object as being composed of only an interface and an implementation, this model distinguishes between the interface used for defining an object and an interface that is used to call an object. The comprehensive model structure incorporates a classification and retrieval mechanism designed to help map conceptual requirements to existing components in the software archive.

  4. Fit of CAD/CAM implant frameworks: a comprehensive review.

    Science.gov (United States)

    Abduo, Jaafar

    2014-12-01

    Computer-aided design and computer-aided manufacturing (CAD/CAM) is a strongly emerging prosthesis fabrication method for implant dentistry. Currently, CAD/CAM allows the construction of implant frameworks from different materials. This review evaluates the literature pertaining to the precision fit of fixed implant frameworks fabricated by CAD/CAM. Following a comprehensive electronic search through PubMed (MEDLINE), 14 relevant articles were identified. The results indicate that the precision fit of CAD/CAM frameworks exceeded the fit of the 1-piece cast frameworks and laser-welded frameworks. A similar fit was observed for CAD/CAM frameworks and bonding of the framework body to prefabricated cylinders. The influence of CAD/CAM materials on the fit of a framework is minimal.

  5. Automatic Modelling of Photograhed Parts in CATIA CAD Environment

    Directory of Open Access Journals (Sweden)

    Yunus Kayır

    2014-04-01

    Full Text Available In this study, a system was developed that can model parts in CATIA CAD program automatically by using photographic images obtained from the parts. The system, called ImageCAD, can use very kind of photography that was taken for prismatic and cylindrical parts. It can recognize geometric entities, such as lines, circles, arc and free curve, in the image by according to the selection of the user. ImageCAD can save generated knowledge of the entities in a suitable format for the CATIA program. ImageCAD, is controlled by using menus that were done in the CATIA interface, turn whatever you want photographs into 3B CAD models. The obtained CAD models have suitable structure that can be used for all CATIA application. Visual Basic programing language was preferred to design the system.

  6. Barriers and Coping Strategies of Garment CAD Application and Popularization

    Directory of Open Access Journals (Sweden)

    Zhe Li

    2013-07-01

    Full Text Available The aim of study is to make the garment CAD get faster development and popularization in China. Garment CAD enhances enterprise's economic and social benefits, but it actually receives the hindrance in the domestic application and popularization. The domestic popularity rate is obviously lower than that in European and American developed countries. The main barriers which existing in the application and popularization process of garment CAD in China are analyzed and corresponding countermeasures are proposed.

  7. CAD-driven microassembly and visual servoing

    Energy Technology Data Exchange (ETDEWEB)

    Feddema, J.T.; Simon, R.W.

    1998-03-10

    This paper describes current research and development on a robotic visual servoing system for assembly of LIGA (Lithography Galvonoforming Abforming) parts. The workcell consists of an AMTI robot, precision stage, long working distance microscope, and LIGA fabricated tweezers for picking up the parts. Fourier optics methods are used to generate synthetic microscope images from CAD drawings. These synthetic images are used off-line to test image processing routines under varying magnifications and depths of field, They also provide reference image features which are used to visually servo the part to the desired position.

  8. Haemostatic function in coronary artery disease (CAD).

    Science.gov (United States)

    Gupta, A; Sikka, M; Madan, N; Dwidedi, S; Rusia, U; Sharma, S

    1997-04-01

    Tests to evaluate haemostatic function bleeding time (BT), prothrombin time (PT) partial thromboplastin time with kaolin (PTTK), thrombin time (TT), platelet count, platelet function tests (platelet adhesiveness and microthrombus index) and plasma fibrinogen levels were performed in 30 patients of coronary artery disease (14 myocardial infarction, 16 angina pectoris) and 20 age and sex matched controls. There was no statistically significant difference in platelet adhesiveness and mean microthrombus index in patients and controls. The BT, PT, PTTK and TT were normal in all patients and controls. Stepwise logistic regression analysis showed that plasma fibrinogen was an independent risk factor in the production of CAD.

  9. DESIGNING AN EFFECTIVE INTERSECTION USING CAD ENVIRONMENT

    Directory of Open Access Journals (Sweden)

    CRISAN George-Horea

    2017-05-01

    Full Text Available Ensuring the safety and streamline in road traffic are very important aims, with regard to the nowadays people mobility level. Road infrastructure is an essential element that can meet these requirements. Thus, it is proposed to develop an effective model of intersection by using CAD software tools. This type of intersection can be successfully used on almost any category of roads, increasing road traffic safety, reducing passing times through the intersection and in the same time, reducing conflict points and increase the intersection capacity.

  10. Improvement of MS (multiple sclerosis) CAD (computer aided diagnosis) performance using C/C++ and computing engine in the graphical processing unit (GPU)

    Science.gov (United States)

    Suh, Joohyung; Ma, Kevin; Le, Anh

    2011-03-01

    Multiple Sclerosis (MS) is a disease which is caused by damaged myelin around axons of the brain and spinal cord. Currently, MR Imaging is used for diagnosis, but it is very highly variable and time-consuming since the lesion detection and estimation of lesion volume are performed manually. For this reason, we developed a CAD (Computer Aided Diagnosis) system which would assist segmentation of MS to facilitate physician's diagnosis. The MS CAD system utilizes K-NN (k-nearest neighbor) algorithm to detect and segment the lesion volume in an area based on the voxel. The prototype MS CAD system was developed under the MATLAB environment. Currently, the MS CAD system consumes a huge amount of time to process data. In this paper we will present the development of a second version of MS CAD system which has been converted into C/C++ in order to take advantage of the GPU (Graphical Processing Unit) which will provide parallel computation. With the realization of C/C++ and utilizing the GPU, we expect to cut running time drastically. The paper investigates the conversion from MATLAB to C/C++ and the utilization of a high-end GPU for parallel computing of data to improve algorithm performance of MS CAD.

  11. A panorama of dental CAD/CAM restorative systems.

    Science.gov (United States)

    Liu, Perng-Ru

    2005-07-01

    In the last 2 decades, exciting new developments in dental materials and computer technology have led to the success of contemporary dental computer-aided design/computer-aided manufacturing (CAD/CAM) technology. Several highly sophisticated chairside and laboratory CAD/CAM systems have been introduced or are under development. This article provides an overview of the development of various CAD/CAM systems. Operational components, methodologies, and restorative materials used with common CAD/CAM systems are discussed. Research data and clinical studies are presented to substantiate the clinical performance of these systems.

  12. Panorama of dental CAD/CAM restorative systems.

    Science.gov (United States)

    Liu, Perng-Ru; Essig, Milton E

    2008-10-01

    In the past two decades, exciting new developments in dental materials and computer technology have led to the success of contemporary dental computer-aided design/computer-aided manufacture (CAD/CAM) technology. Several highly sophisticated in-office and laboratory CAD/CAM systems have been introduced or are under development. This article provides an overview of the development of various CAD/CAM systems. Operational components, methodologies, and restorative materials used with common CAD/CAM systems are discussed. Research data and clinical studies are presented to substantiate the clinical performance of these systems.

  13. CATO: a CAD tool for intelligent design of optical networks and interconnects

    Science.gov (United States)

    Chlamtac, Imrich; Ciesielski, Maciej; Fumagalli, Andrea F.; Ruszczyk, Chester; Wedzinga, Gosse

    1997-10-01

    Increasing communication speed requirements have created a great interest in very high speed optical and all-optical networks and interconnects. The design of these optical systems is a highly complex task, requiring the simultaneous optimization of various parts of the system, ranging from optical components' characteristics to access protocol techniques. Currently there are no computer aided design (CAD) tools on the market to support the interrelated design of all parts of optical communication systems, thus the designer has to rely on costly and time consuming testbed evaluations. The objective of the CATO (CAD tool for optical networks and interconnects) project is to develop a prototype of an intelligent CAD tool for the specification, design, simulation and optimization of optical communication networks. CATO allows the user to build an abstract, possible incomplete, model of the system, and determine its expected performance. Based on design constraints provided by the user, CATO will automatically complete an optimum design, using mathematical programming techniques, intelligent search methods and artificial intelligence (AI). Initial design and testing of a CATO prototype (CATO-1) has been completed recently. The objective was to prove the feasibility of combining AI techniques, simulation techniques, an optical device library and a graphical user interface into a flexible CAD tool for obtaining optimal communication network designs in terms of system cost and performance. CATO-1 is an experimental tool for designing packet-switching wavelength division multiplexing all-optical communication systems using a LAN/MAN ring topology as the underlying network. The two specific AI algorithms incorporated are simulated annealing and a genetic algorithm. CATO-1 finds the optimal number of transceivers for each network node, using an objective function that includes the cost of the devices and the overall system performance.

  14. A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1989-01-01

    In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or di...... above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 °C)....

  15. Automatic Generation of CFD-Ready Surface Triangulations from CAD Geometry

    Science.gov (United States)

    Aftosmis, M. J.; Delanaye, M.; Haimes, R.; Nixon, David (Technical Monitor)

    1998-01-01

    This paper presents an approach for the generation of closed manifold surface triangulations from CAD geometry. CAD parts and assemblies are used in their native format, without translation, and a part's native geometry engine is accessed through a modeler-independent application programming interface (API). In seeking a robust and fully automated procedure, the algorithm is based on a new physical space manifold triangulation technique which was developed to avoid robustness issues associated with poorly conditioned mappings. In addition, this approach avoids the usual ambiguities associated with floating-point predicate evaluation on constructed coordinate geometry in a mapped space, The technique is incremental, so that each new site improves the triangulation by some well defined quality measure. Sites are inserted using a variety of priority queues to ensure that new insertions will address the worst triangles first, As a result of this strategy, the algorithm will return its 'best' mesh for a given (prespecified) number of sites. Alternatively, the algorithm may be allowed to terminate naturally after achieving a prespecified measure of mesh quality. The resulting triangulations are 'CFD-ready' in that: (1) Edges match the underlying part model to within a specified tolerance. (2) Triangles on disjoint surfaces in close proximity have matching length-scales. (3) The algorithm produces a triangulation such that no angle is less than a given angle bound, alpha, or greater than Pi - 2alpha This result also sets bounds on the maximum vertex degree, triangle aspect-ratio and maximum stretching rate for the triangulation. In addition to tile output triangulations for a variety of CAD parts, tile discussion presents related theoretical results which assert the existence of such all angle bound, and demonstrate that maximum bounds of between 25 deg and 30 deg may be achieved in practice.

  16. Cascaded VLSI neural network architecture for on-line learning

    Science.gov (United States)

    Duong, Tuan A. (Inventor); Daud, Taher (Inventor); Thakoor, Anilkumar P. (Inventor)

    1995-01-01

    High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

  17. A Comparison of the Marginal and Internal Fit of Cobalt- Chromium Copings Fabricated by Two Different CAD/CAM Systems (CAD/ Milling, CAD/ Ceramill Sintron).

    Science.gov (United States)

    Vojdani, Mahroo; Torabi, Kianoosh; Atashkar, Berivan; Heidari, Hossein; Torabi Ardakani, Mahshid

    2016-12-01

    Marginal fitness is the most important criteria for evaluation of the clinical acceptability of a cast restoration. Marginal gap which is due to cement solubility and plaque retention is potentially detrimental to both tooth and periodontal tissues. This in vitro study aimed to evaluate the marginal and internal fit of cobalt- chromium (Co-Cr) copings fabricated by two different CAD/CAM systems: (CAD/ milling and CAD/ Ceramill Sintron). We prepared one machined standard stainless steel master model with following dimensions: 7 mm height, 5mm diameter, 90˚ shoulder marginal finish line with 1 mm width, 10˚ convergence angle and anti-rotational surface on the buccal aspect of the die. There were 10 copings produced from hard presintered Co-Cr blocks according to CAD/ Milling technique and ten copings from soft non- presintered Co-Cr blocks according to CAD/ Ceramill Sintron technique. Marginal and internal accuracies of copings were documented by the replica technique. Replicas were examined at ten reference points under a digital microscope (230X). The Student's t-test was used for statistical analysis. pCAD/milling group (hard copings) had a mean marginal discrepancy (MD) of 104 µm, axial discrepancy (AD) of 23 µm and occlusal discrepancy of 130 µm. For CAD/ Ceramill Sintron group, these values were 195 µm (MD), 46 µm (AD), and 232 µm (OD). Internal total discrepancy (ITD) for the CAD/milling group was 77 µm, whereas for the CAD/Ceramill Sintron group was 143 µm. Hard presintered Co-Cr copings had significantly higher marginal and internal accuracies compared to the soft non-presintered copings.

  18. Motion estimation for video coding efficient algorithms and architectures

    CERN Document Server

    Chakrabarti, Indrajit; Chatterjee, Sumit Kumar

    2015-01-01

    The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones.

  19. An analog VLSI implementation of a visual interneuron: enhanced sensory processing through biophysical modeling.

    Science.gov (United States)

    Harrison, R R; Koch, C

    1999-10-01

    Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.

  20. A cost-effective methodology for the design of massively-parallel VLSI functional units

    Science.gov (United States)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  1. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-07

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  2. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  3. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  4. Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications

    Directory of Open Access Journals (Sweden)

    P. Mohan Krishna

    2014-04-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.

  5. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...

  6. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  7. Current-mode subthreshold MOS circuits for analog VLSI neural systems

    Science.gov (United States)

    Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.

    1991-03-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  8. Current-mode subthreshold MOS circuits for analog VLSI neural systems.

    Science.gov (United States)

    Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K

    1991-01-01

    An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

  9. A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

    OpenAIRE

    Tiri, Kris; Verbauwhede, Ingrid

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...

  10. The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter

    Science.gov (United States)

    2001-09-01

    December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60

  11. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  12. VLSI implementation of a nonlinear neuronal model: a "neural prosthesis" to restore hippocampal trisynaptic dynamics.

    Science.gov (United States)

    Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W

    2006-01-01

    We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.

  13. CAD Method to Design Complex Dobby Weaves with Large Repeats

    Institute of Scientific and Technical Information of China (English)

    祝成炎

    2001-01-01

    The principle of a CAD method of converting the pre-designed figures in image form into complex dobby weaves with the appearances similar to the original figures is mainly introduced in this paper. A few designed weaves by the created CAD system are also given as examples of the practical application in the area of complex dobby weave designing.

  14. CAD/CAM: Practical and Persuasive in Canadian Schools

    Science.gov (United States)

    Willms, Ed

    2007-01-01

    Chances are that many high school students would not know how to use drafting instruments, but some might want to gain competence in computer-assisted design (CAD) and possibly computer-assisted manufacturing (CAM). These students are often attracted to tech courses by the availability of CAD/CAM instructions, and many go on to impress employers…

  15. A systematic review of CAD/CAM fit restoration evaluations.

    Science.gov (United States)

    Boitelle, P; Mawussi, B; Tapie, L; Fromentin, O

    2014-11-01

    The evolution and development of CAD/CAM systems have led to the production of prosthetic reconstructions by going beyond the use of traditional techniques. Precision adjustment of prosthetic elements is considered essential to ensure sustainable restoration and dental preparation. The purpose of this article was to summarise the current literature on the fitting quality of fixed prostheses obtained by CAD/CAM technology.

  16. A Generation Method of Mechanical Assembly Drawing in CAD

    Institute of Scientific and Technical Information of China (English)

    2000-01-01

    This paper supplies a generation method of mechanical assembly drawing in CAD. By means of the programs of Auto Lisp, the method which based on AutoCAD may complete profiling the parts, forming parts graphic base, calculation of removing hidden line, and establishing assembly drawing.

  17. An Instructional Method for the AutoCAD Modeling Environment.

    Science.gov (United States)

    Mohler, James L.

    1997-01-01

    Presents a command organizer for AutoCAD to aid new uses in operating within the 3-D modeling environment. Addresses analyzing the problem, visualization skills, nonlinear tools, a static view of a dynamic model, the AutoCAD organizer, environment attributes, and control of the environment. Contains 11 references. (JRH)

  18. STL-standaard slaat brug tussen CAD en CAM

    NARCIS (Netherlands)

    Gunnink, J.W.

    1999-01-01

    De STL-standaard, gemeengoed bij rapid prototyping technieken, kan ook een rol spelen in het traject van 3D CAD-ontwerp naar (laser)frezen. Met één druk op de knop de freesmachine aansturen vanuit het CAD-ontwerp komt binnen handbereik. TNO Industrie in Delft hoort op dat gebied wereldwijd tot de

  19. Teach CAD and Measuring Skills through Reverse Engineering

    Science.gov (United States)

    Board, Keith

    2012-01-01

    This article describes a reverse engineering activity that gives students hands-on, minds-on experience with measuring tools, machine parts, and CAD. The author developed this activity to give students an abundance of practical experience with measuring tools. Equally important, it provides a good interface between the virtual world of CAD 3D…

  20. An Instructional Method for the AutoCAD Modeling Environment.

    Science.gov (United States)

    Mohler, James L.

    1997-01-01

    Presents a command organizer for AutoCAD to aid new uses in operating within the 3-D modeling environment. Addresses analyzing the problem, visualization skills, nonlinear tools, a static view of a dynamic model, the AutoCAD organizer, environment attributes, and control of the environment. Contains 11 references. (JRH)

  1. Teach CAD and Measuring Skills through Reverse Engineering

    Science.gov (United States)

    Board, Keith

    2012-01-01

    This article describes a reverse engineering activity that gives students hands-on, minds-on experience with measuring tools, machine parts, and CAD. The author developed this activity to give students an abundance of practical experience with measuring tools. Equally important, it provides a good interface between the virtual world of CAD 3D…

  2. The CAD System Development for Power Plants Pipe-Prefabrication

    Institute of Scientific and Technical Information of China (English)

    RUI Xiaoming; MA Zhiyong

    2006-01-01

    An intelligent design software system for the power station pipe-prefabrication (PPDS) has been developed in the paper, which is taking pipe material database as core and developed on the platform of AutoCAD and Borland C++.Whereas design and construction of power plants in China belong to different departments, the input and recognition problem of pipeline system disposition chart must be solved firstly for the prefabrication design. Based on AI technology, the model fast building subsystem (MFBS) was established for entering the 3-D pipeline graph data, so that the problems of reconstruction of pipeline digital model and computer identification of original 2-D design data can be solved. The optimization design scheme in the pipe-prefabrication process has been studied and also the corresponding algorithm put forward. The technique and system mentioned can effectively raise the pipe- prefabrication design quality and efficiency in the construction of large scale power plants, reduce the period of design and the waste of raw material. PPCADS has still offered the functions such as the construction design for pipeline prefabricated process, the detailing drawing for manufacturing pipe section and automatic generating the technical files for the completed project.

  3. 3D CAD for concept design - a case study

    Directory of Open Access Journals (Sweden)

    S.K. Mandal

    2013-07-01

    Full Text Available Generally for any new design initially a concept layout in 2D CAD is generated. But sometimes if the geometry of product becomes complicated, then 3D CAD model is preferred. Because 3D CAD model can give us a complete all side view at a time like a real product, but in a virtual world. The present case study will show the utilization of 3D CAD at the concept design stage of a complicated shaped product for a new system. This will also give an idea about cost and time comparison. Thus this paper will describe about the importance of 3D CAD tools for product development. 

  4. Efficient Interconnection Schemes for VLSI and Parallel Computation

    Science.gov (United States)

    1989-08-01

    MTTl/LjCS/TR-456 NOOO14-87-K-0825 and NOOO14-86-K-0593 6a. NAME OF "ERFORMING ORGANIZATION I6b. OFFICE SYMBOL 7a. NAME OF MONITORING ORGANIZATION HIIT ...generally abstracted away, and the simulation results are expressed in terms of the running time for the chosen message routing algorithm. Chapter 4...messages on fat-trees. The running times of these algorithms are expressed as a function of the load factor of a set of messages to be routed, the load

  5. Grid infrastructures for developing mammography CAD systems.

    Science.gov (United States)

    Ramos-Pollan, Raul; Franco, Jose M; Sevilla, Jorge; Guevara-Lopez, Miguel A; de Posada, Naimy Gonzalez; Loureiro, Joanna; Ramos, Isabel

    2010-01-01

    This paper presents a set of technologies developed to exploit Grid infrastructures for breast cancer CAD, that include (1) federated repositories of mammography images and clinical data over Grid storage, (2) a workstation for mammography image analysis and diagnosis and (3) a framework for data analysis and training machine learning classifiers over Grid computing power specially tuned for medical image based data. An experimental mammography digital repository of approximately 300 mammograms from the MIAS database was created and classifiers were built achieving a 0.85 average area under the ROC curve in a dataset of 100 selected mammograms with representative pathological lesions and normal cases. Similar results were achieved with classifiers built for the UCI Breast Cancer Wisconsin dataset (699 features vectors). Now these technologies are being validated in a real medical environment at the Faculty of Medicine in Porto University after a process of integrating the tools within the clinicians workflows and IT systems.

  6. Design of a superconducting magnet for CADS

    Institute of Scientific and Technical Information of China (English)

    YANG Xiao-Liang; MA Li-Zhen; WU Vei; ZHENG Shi-Jun; DU Jun-Jie; HAN Shao-Fei; GUAN Ming-Zhi; HE Yuan

    2012-01-01

    This paper describes a superconducting magnet system for the China Accelerator Driven System (CADS).The magnetic field is provided hy one main,two bucking and four racetrack coils.The main coil produces a central field of up to 7 T and the effective length is more than 140 mm,the two bucking coils can shield most of the fringe field,and the four racetrack superconducting coils produce the steering magnetic field.Its leakage field in the cavity zone is about 5 × 10-5 T when the shielding material Niobium and cryogenic permalloy are used as the Meissner shielding and passive shielding respectively.The quench calculations and protection system are also discussed.

  7. Immediate CAD/ CAM Custom Fabricated Dental Implants

    Directory of Open Access Journals (Sweden)

    Jafar Kolahi

    2010-11-01

    Full Text Available Introduction: There will almost always be gaps between cylin-drical or screw shaped prefabricated implant surface and funnel-shaped tooth socket when an implant is placed immediately after tooth extraction. Hence expensive and difficult bone grafting is re-quired. A custom fabricated implant will be a pragmatic solution for this limitation.The hypothesis: First step following extraction of a tooth is data capture or scanning via a 3D scan method e.g. coordinate measuring machine or non-contact laser scanners such as triangulation range finder. Second step is reconstruction or modeling via editable CAD (computer-aided design model, allowing us to add retentive holes and correction of implant angle. Third step is fabrication via CAM (computer aided manufacturing followed by plasma cleaning process. Fourth step is insertion of the CAD/CAM custom fabricated one-stage implant in the fresh tooth socket. Optimal time for this step is 24-48 hours after extraction. The custom fabricated implant should not load 3-4 months. Usage of chlorhexidine mouth-rinse or chewing gum twice daily for 2 weeks and, in some cases oral antibiotic is recommended. Evaluation of the hypothesis: Contemporary dental implant system faced with several clinical and anatomical limitations such is low sinuses or nerve bundles. Complex and expensive surgical procedures such as nerve repositioning and sinus lift are frequently required. With custom fabricated implant we can overcome several of these limitations because insertion of custom fabricated implant will perform before alveolar bone recession.

  8. A VLSI design for a trace-back Viterbi decoder

    Science.gov (United States)

    Truong, T. K.; Shih, Ming-Tang; Reed, Irving S.; Satorius, E. H.

    1992-01-01

    A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.

  9. Boolean Expressions of Rectilinear Polygons with VLSI Applications.

    Science.gov (United States)

    1982-11-01

    Ottmann [6] in optimal time and space. Thus, we will use their technique to determine and report the intersection endpoints. The detection and report... Ottmann , "Algorithms for reporting and counting geometric intersections," IEEE Trans. Comput., vol. C-28, pp. 643-647, Sept. 1979. 7. W. J. Paul, R. E

  10. CAD of control systems: Application of nonlinear programming to a linear quadratic formulation

    Science.gov (United States)

    Fleming, P.

    1983-01-01

    The familiar suboptimal regulator design approach is recast as a constrained optimization problem and incorporated in a Computer Aided Design (CAD) package where both design objective and constraints are quadratic cost functions. This formulation permits the separate consideration of, for example, model following errors, sensitivity measures and control energy as objectives to be minimized or limits to be observed. Efficient techniques for computing the interrelated cost functions and their gradients are utilized in conjunction with a nonlinear programming algorithm. The effectiveness of the approach and the degree of insight into the problem which it affords is illustrated in a helicopter regulation design example.

  11. Automated CD-SEM recipe creation technology for mass production using CAD data

    Science.gov (United States)

    Kawahara, Toshikazu; Yoshida, Masamichi; Tanaka, Masashi; Ido, Sanyu; Nakano, Hiroyuki; Adachi, Naokaka; Abe, Yuichi; Nagatomo, Wataru

    2011-03-01

    Critical Dimension Scanning Electron Microscope (CD-SEM) recipe creation needs sample preparation necessary for matching pattern registration, and recipe creation on CD-SEM using the sample, which hinders the reduction in test production cost and time in semiconductor manufacturing factories. From the perspective of cost reduction and improvement of the test production efficiency, automated CD-SEM recipe creation without the sample preparation and the manual operation has been important in the production lines. For the automated CD-SEM recipe creation, we have introduced RecipeDirector (RD) that enables the recipe creation by using Computer-Aided Design (CAD) data and text data that includes measurement information. We have developed a system that automatically creates the CAD data and the text data necessary for the recipe creation on RD; and, for the elimination of the manual operation, we have enhanced RD so that all measurement information can be specified in the text data. As a result, we have established an automated CD-SEM recipe creation system without the sample preparation and the manual operation. For the introduction of the CD-SEM recipe creation system using RD to the production lines, the accuracy of the pattern matching was an issue. The shape of design templates for the matching created from the CAD data was different from that of SEM images in vision. Thus, a development of robust pattern matching algorithm that considers the shape difference was needed. The addition of image processing of the templates for the matching and shape processing of the CAD patterns in the lower layer has enabled the robust pattern matching. This paper describes the automated CD-SEM recipe creation technology for the production lines without the sample preparation and the manual operation using RD applied in Sony Semiconductor Kyusyu Corporation Kumamoto Technology Center (SCK Corporation Kumamoto TEC).

  12. CAD Integrated Multipoint Adjoint-Based Optimization of a Turbocharger Radial Turbine

    Directory of Open Access Journals (Sweden)

    Lasse Mueller

    2017-09-01

    Full Text Available The adjoint method is considered as the most efficient approach to compute gradients with respect to an arbitrary number of design parameters. However, one major challenge of adjoint-based shape optimization methods is the integration into a computer-aided design (CAD workflow for practical industrial cases. This paper presents an adjoint-based framework that uses a tailored shape parameterization to satisfy geometric constraints due to mechanical and manufacturing requirements while maintaining the shape in a CAD representation. The system employs a sequential quadratic programming (SQP algorithm and in-house developed libraries for the CAD and grid generation as well as a 3D Navier–Stokes flow and adjoint solver. The developed method is applied to a multipoint optimization of a turbocharger radial turbine aiming at maximizing the total-to-static efficiency at multiple operating points while constraining the output power and the choking mass flow of the machine. The optimization converged in a few design cycles in which the total-to-static efficiency could be significantly improved over a wide operating range. Additionally, the imposed aerodynamic constraints with strict convergence tolerances are satisfied and several geometric constraints are inherently respected due to the parameterization of the turbine. In particular, radial fibered blades are used to avoid bending stresses in the turbine blades due to centrifugal forces. The methodology is a step forward towards robustness and consistency of gradient-based optimization for practical industrial cases, as it maintains the optimal shape in CAD representation. As shown in this paper, this avoids shape approximations and allows manufacturing constraints to be included.

  13. Phylogeny and expression profiling of CAD and CAD-like genes in hybrid Populus (P. deltoides × P. nigra: evidence from herbivore damage for subfunctionalization and functional divergence

    Directory of Open Access Journals (Sweden)

    Frost Christopher J

    2010-05-01

    Full Text Available Abstract Background Cinnamyl Alcohol Dehydrogenase (CAD proteins function in lignin biosynthesis and play a critical role in wood development and plant defense against stresses. Previous phylogenetic studies did not include genes from seedless plants and did not reflect the deep evolutionary history of this gene family. We reanalyzed the phylogeny of CAD and CAD-like genes using a representative dataset including lycophyte and bryophyte sequences. Many CAD/CAD-like genes do not seem to be associated with wood development under normal growth conditions. To gain insight into the functional evolution of CAD/CAD-like genes, we analyzed their expression in Populus plant tissues in response to feeding damage by gypsy moth larvae (Lymantria dispar L.. Expression of CAD/CAD-like genes in Populus tissues (xylem, leaves, and barks was analyzed in herbivore-treated and non-treated plants by real time quantitative RT-PCR. Results CAD family genes were distributed in three classes based on sequence conservation. All the three classes are represented by seedless as well as seed plants, including the class of bona fide lignin pathway genes. The expression of some CAD/CAD-like genes that are not associated with xylem development were induced following herbivore damage in leaves, while other genes were induced in only bark or xylem tissues. Five of the CAD/CAD-like genes, however, showed a shift in expression from one tissue to another between non-treated and herbivore-treated plants. Systemic expression of the CAD/CAD-like genes was generally suppressed. Conclusions Our results indicated a correlation between the evolution of the CAD gene family and lignin and that the three classes of genes may have evolved in the ancestor of land plants. Our results also suggest that the CAD/CAD-like genes have evolved a diversity of expression profiles and potentially different functions, but that they are nonetheless co-regulated under stress conditions.

  14. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods.

  15. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  16. CAD-centric Computation Management System for a Virtual TBM

    Energy Technology Data Exchange (ETDEWEB)

    Ramakanth Munipalli; K.Y. Szema; P.Y. Huang; C.M. Rowell; A.Ying; M. Abdou

    2011-05-03

    HyPerComp Inc. in research collaboration with TEXCEL has set out to build a Virtual Test Blanket Module (VTBM) computational system to address the need in contemporary fusion research for simulating the integrated behavior of the blanket, divertor and plasma facing components in a fusion environment. Physical phenomena to be considered in a VTBM will include fluid flow, heat transfer, mass transfer, neutronics, structural mechanics and electromagnetics. We seek to integrate well established (third-party) simulation software in various disciplines mentioned above. The integrated modeling process will enable user groups to interoperate using a common modeling platform at various stages of the analysis. Since CAD is at the core of the simulation (as opposed to computational meshes which are different for each problem,) VTBM will have a well developed CAD interface, governing CAD model editing, cleanup, parameter extraction, model deformation (based on simulation,) CAD-based data interpolation. In Phase-I, we built the CAD-hub of the proposed VTBM and demonstrated its use in modeling a liquid breeder blanket module with coupled MHD and structural mechanics using HIMAG and ANSYS. A complete graphical user interface of the VTBM was created, which will form the foundation of any future development. Conservative data interpolation via CAD (as opposed to mesh-based transfer), the regeneration of CAD models based upon computed deflections, are among the other highlights of phase-I activity.

  17. Investigation of IGES for CAD/CAE data transfer

    Science.gov (United States)

    Zobrist, George W.

    1989-01-01

    In a CAD/CAE facility there is always the possibility that one may want to transfer the design graphics database from the native system to a non-native system. This may occur because of dissimilar systems within an organization or a new CAD/CAE system is to be purchased. The Initial Graphics Exchange Specification (IGES) was developed in an attempt to solve this scenario. IGES is a neutral database format into which the CAD/CAE native database format can be translated to and from. Translating the native design database format to IGES requires a pre-processor and transling from IGES to the native database format requires a post-processor. IGES is an artifice to represent CAD/CAE product data in a neutral environment to allow interfacing applications, archive the database, interchange of product data between dissimilar CAD/CAE systems, and other applications. The intent here is to present test data on translating design product data from a CAD/CAE system to itself and to translate data initially prepared in IGES format to various native design formats. This information can be utilized in planning potential procurement and developing a design discipline within the CAD/CAE community.

  18. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  19. A new CAD approach for improving efficacy of cancer screening

    Science.gov (United States)

    Zheng, Bin; Qian, Wei; Li, Lihua; Pu, Jiantao; Kang, Yan; Lure, Fleming; Tan, Maxine; Qiu, Yuchen

    2015-03-01

    Since performance and clinical utility of current computer-aided detection (CAD) schemes of detecting and classifying soft tissue lesions (e.g., breast masses and lung nodules) is not satisfactory, many researchers in CAD field call for new CAD research ideas and approaches. The purpose of presenting this opinion paper is to share our vision and stimulate more discussions of how to overcome or compensate the limitation of current lesion-detection based CAD schemes in the CAD research community. Since based on our observation that analyzing global image information plays an important role in radiologists' decision making, we hypothesized that using the targeted quantitative image features computed from global images could also provide highly discriminatory power, which are supplementary to the lesion-based information. To test our hypothesis, we recently performed a number of independent studies. Based on our published preliminary study results, we demonstrated that global mammographic image features and background parenchymal enhancement of breast MR images carried useful information to (1) predict near-term breast cancer risk based on negative screening mammograms, (2) distinguish between true- and false-positive recalls in mammography screening examinations, and (3) classify between malignant and benign breast MR examinations. The global case-based CAD scheme only warns a risk level of the cases without cueing a large number of false-positive lesions. It can also be applied to guide lesion-based CAD cueing to reduce false-positives but enhance clinically relevant true-positive cueing. However, before such a new CAD approach is clinically acceptable, more work is needed to optimize not only the scheme performance but also how to integrate with lesion-based CAD schemes in the clinical practice.

  20. Turnkey CAD/CAM systems' integration with IPAD systems

    Science.gov (United States)

    Blauth, R. E.

    1980-01-01

    Today's commercially available turnkey CAD/CAM systems provide a highly interactive environment, and support many specialized application functions for the design/drafting/manufacturing process. This paper presents an overview of several aerospace companies which have successfully integrated turnkey CAD/CAM systems with their own company wide engineering and manufacturing systems. It also includes a vendor's view of the benefits as well as the disadvantages of such integration efforts. Specific emphasis is placed upon the selection of standards for representing geometric engineering data and for communicating such information between different CAD/CAM systems.

  1. Single unit CAD/CAM restorations: a literature review.

    Science.gov (United States)

    Freedman, Michael; Quinn, Frank; O'Sullivan, Michael

    2007-01-01

    Computer-aided design/computer-aided manufacture (CAD/CAM) has been used in dentistry since 1987. Since then, many CAD/CAM systems have been described, which enable the production of chair-side single unit dental restorations. These restorations are of comparable quality to those made by conventional techniques and have some specific advantages, including rapid production, improved wear properties, decreased laboratory fee and improved cross infection control. This literature review investigates the evidence base for the use of single unit CAD/CAM restorations. Materials, marginal gap, aesthetics, post-operative sensitivity, cementation, cost-effectiveness and longevity are discussed.

  2. Engineering drawing from first principles using AutoCAD

    CERN Document Server

    Maguire, Dennis E

    1998-01-01

    Engineering Drawing From First Principles is a guide to good draughting for students of engineering who need to learn how to produce technically accurate and detailed designs to British and International Standards. Written by Dennis Maguire, an experienced author and City and Guilds chief examiner, this text is designed for use on Further Education and University courses where a basic understanding of draughtsmanship and CAD is necessary. Although not written as an AutoCAD tutor, the book will be a useful introduction to good CAD practice.Part of the Revision and Self-Assessmen

  3. Study on CAD/CAE System of Engine Connecting Rod

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    The intensive competition of automotive market requ ir es shortening the product development circle and improving the product quality. Many of auto manufacturers in china have introduced some CAD/CAE/CAM systems in product development process, and have got some success. But the special and effi cient CAD system aimed at particular product is absent. This paper provides a CA D/CAE system that can realize the integration of CAD and CAE process for engine connecting rod development. The paper discusses som...

  4. Complete PCB design using OrCAD capture and layout

    CERN Document Server

    Mitzner, Kraig

    2011-01-01

    This book provides instruction on how to use the OrCAD design suite to design and manufacture printed circuit boards. The book is written for both students and practicing engineers who need a quick tutorial on how to use the software and who need in-depth knowledge of the capabilities and limitations of the software package. There are two goals the book aims to reach:The primary goal is to show the reader how to design a PCB using OrCAD Capture and OrCAD Layout. Capture is used to build the schematic diagram of the circuit, and Layout is used to design the circuit board so that

  5. Study on Isomerous CAD Model Exchange Based on Feature

    Institute of Scientific and Technical Information of China (English)

    SHAO Xiaodong; CHEN Feng; XU Chenguang

    2006-01-01

    A model-exchange method based on feature between isomerous CAD systems is put forward in this paper. In this method, CAD model information is accessed at both feature and geometry levels and converted according to standard feature operation. The feature information including feature tree, dimensions and constraints, which will be lost in traditional data conversion, as well as geometry are converted completely from source CAD system to destination one. So the transferred model can be edited through feature operation, which cannot be implemented by general model-exchange interface.

  6. Release and Dynamic Management of CAD Network Graphics Library

    Institute of Scientific and Technical Information of China (English)

    XU Mao-feng; ZHANG Yi; LIU Fang; LI Ai-jun

    2003-01-01

    We aimed at the release and dynamic management of CAD network graphics library (NGL). The characteristics of realization on network of CAD graphics are analysed, while the existing problems of the presenting share methods of graphics file are also discussed. Release and dynamic management are accomplished with the B/S combined with C/S as well as the file organization based on attribute information, which have essential practical sense to the establishment of CAD NGL, share and cooperation in tech-design as well as the distance education of engineering graphics.

  7. A Motion Adaptive De-interlacing Technique and VLSI Architecture%一种运动自适应去隔行技术及其VLSI结构

    Institute of Scientific and Technical Information of China (English)

    普玉伟; 叶兵; 曾德瑞; 蒋特林

    2011-01-01

    An efficient motion adaptive de-interlacing is proposed in this paper. The mixing pixels is classified to fast motion, slow motion or static region according to the motion detection of the same parity field, the corresponding interpolation method is used in different motion region. The edge detection uses the improved ELA algorithm which overcomes the traditional ELA algorithm's deficiency at processing horizontal edge, and the edge is preserved effectively. Compared with motion compensated algorithm, our proposed algorithm required lower computational complexity, and it is easier to implement by VLSI .The experiment shows that the proposed algorithm gains better de-interlacing and high peak signal-to-noise ratio.%提出一种有效的运动自适应去隔行算法.该算法通过对同极性的相邻场进行运动检测,把插值点所处的区域分为快速运动区域、慢速运动区域和静止区域,对不同的区域采用不同的插值算法.在边缘检测方面,采用改进型ELA算法克服了传统的ELA算法处理水平边缘方面的不足,使边缘得到有效保护.与运动补偿算法相比,该算法计算复杂度较低,易于VLSI实现.实验结果显示,该算法取得了良好的去隔行效果和较高的峰值信噪比.

  8. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  9. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  10. How to build VLSI-efficient neural chips

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-02-01

    This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

  11. CAD/CAM approach to improving industry productivity gathers momentum

    Science.gov (United States)

    Fulton, R. E.

    1982-01-01

    Recent results and planning for the NASA/industry Integrated Programs for Aerospace-Vehicle Design (IPAD) program for improving productivity with CAD/CAM methods are outlined. The industrial group work is being mainly done by Boeing, and progress has been made in defining the designer work environment, developing requirements and a preliminary design for a future CAD/CAM system, and developing CAD/CAM technology. The work environment was defined by conducting a detailed study of a reference design process, and key software elements for a CAD/CAM system have been defined, specifically for interactive design or experiment control processes. Further work is proceeding on executive, data management, geometry and graphics, and general utility software, and dynamic aspects of the programs being developed are outlined

  12. Solid modeling and applications rapid prototyping, CAD and CAE theory

    CERN Document Server

    Um, Dugan

    2016-01-01

    The lessons in this fundamental text equip students with the theory of Computer Assisted Design (CAD), Computer Assisted Engineering (CAE), the essentials of Rapid Prototyping, as well as practical skills needed to apply this understanding in real world design and manufacturing settings. The book includes three main areas: CAD, CAE, and Rapid Prototyping, each enriched with numerous examples and exercises. In the CAD section, Professor Um outlines the basic concept of geometric modeling, Hermite and Bezier Spline curves theory, and 3-dimensional surface theories as well as rendering theory. The CAE section explores mesh generation theory, matrix notion for FEM, the stiffness method, and truss Equations. And in Rapid Prototyping, the author illustrates stereo lithographic theory and introduces popular modern RP technologies. Solid Modeling and Applications: Rapid Prototyping, CAD and CAE Theory is ideal for university students in various engineering disciplines as well as design engineers involved in product...

  13. An Inspection Information Integration System of CAD and CMM

    Institute of Scientific and Technical Information of China (English)

    WANG Junying; WANG Jianmei

    2006-01-01

    Manual definition of inspection feature in Coordinate Measuring Machines (CMM) is time-consuming and error-potential. Since CAD model contains all design data, an integration system of CAD/CMM is constructed to automate above process. First, tolerance feature and its attributes, including tolerance type, value and tag of related geometry, are extracted from CAD model and written to QDAS file, based on feature technology. The tags are then added as attribute to related geometry in CAD model. Thereby they can be automatically remarked in the parameter list of their corresponding geometric item when exporting STEP file. At last, both STEP and QDAS file are imported to CMM system. Based on the mapping between geometric and tolerance feature in neutral files, inspection features can be recognized by CMM without manual interruption. The system has been implemented on Unigraphics platform, and proved to applicable for all types of tolerance and geometry.

  14. Geometric data transfer between CAD systems: solid models

    DEFF Research Database (Denmark)

    Kroszynski, Uri; Palstroem, Bjarne; Trostmann, Erik

    1989-01-01

    The first phase of the ESPRIT project CAD*I resulted in a specification for the exchange of solid models as well as in some pilot implementations of processors based on this specification. The authors summarize the CAD*I approach, addressing the structure of neutral files for solids, entities......, and attributes supporting three kinds of representations: facilities for the transfer of parametric designs; referencing library components; and other general mechanisms. They also describe the current state of the specification and processor implementations and include an example of a CAD*I neutral file....... Results from cycle and intersystem solid model transfer tests are presented, showing the practicality of the CAD*I proposal. B-rep model transfer results are discussed in some detail. The relationship of this work to standardization efforts is outlined...

  15. Resin-composite blocks for dental CAD/CAM applications.

    Science.gov (United States)

    Ruse, N D; Sadoun, M J

    2014-12-01

    Advances in digital impression technology and manufacturing processes have led to a dramatic paradigm shift in dentistry and to the widespread use of computer-aided design/computer-aided manufacturing (CAD/CAM) in the fabrication of indirect dental restorations. Research and development in materials suitable for CAD/CAM applications are currently the most active field in dental materials. Two classes of materials are used in the production of CAD/CAM restorations: glass-ceramics/ceramics and resin composites. While glass-ceramics/ceramics have overall superior mechanical and esthetic properties, resin-composite materials may offer significant advantages related to their machinability and intra-oral reparability. This review summarizes recent developments in resin-composite materials for CAD/CAM applications, focusing on both commercial and experimental materials.

  16. CAD mutations and uridine-responsive epileptic encephalopathy

    NARCIS (Netherlands)

    Koch, J.; Mayr, J.A.; Alhaddad, B.; Rauscher, C.; Bierau, J.; Kovacs-Nagy, R.; Coene, K.L.M.; Bader, I.; Holzhacker, M.; Prokisch, H.; Venselaar, H.; Wevers, R.A.; Distelmaier, F.; Polster, T.; Leiz, S.; Betzler, C.; Strom, T.M.; Sperl, W.; Meitinger, T.; Wortmann, S.B.; Haack, T.B.

    2017-01-01

    Unexplained global developmental delay and epilepsy in childhood pose a major socioeconomic burden. Progress in defining the molecular bases does not often translate into effective treatment. Notable exceptions include certain inborn errors of metabolism amenable to dietary intervention. CAD encodes

  17. CAD-CAE in Electrical Machines and Drives Teaching.

    Science.gov (United States)

    Belmans, R.; Geysen, W.

    1988-01-01

    Describes the use of computer-aided design (CAD) techniques in teaching the design of electrical motors. Approaches described include three technical viewpoints, such as electromagnetics, thermal, and mechanical aspects. Provides three diagrams, a table, and conclusions. (YP)

  18. Application of AutoCAD Electrical%AutoCAD Electrical的应用

    Institute of Scientific and Technical Information of China (English)

    范文军; 潘庆杰

    2011-01-01

    当前,AutoCAD Electrical技术以简单、快捷、存储方便等优点已在电气控制设计中承担着不可替代的重要作用.该技术的应用使工程设计人员如虎添翼,在更加广阔的天地里施展才华.本文中提出的五种方法,对利用该技术有效地提高绘制复杂图形的速度大有裨益.

  19. Reserch on Technology of Wooden Furniture CAD System

    Institute of Scientific and Technical Information of China (English)

    YangJiping; HeYulin; 等

    2002-01-01

    This paper introduces the current situation of domestic furniture production as well as world furniture CAD products,puts forward the necessity of developing a dedicated CAD system_WFCAD and its main functions,It analyzes in detail the applied technology and key techniques,including geometric modeling,assembly,joint design,database linking and management.The application of WFCAD in furniture manufacturing enterprises and its further improvement are outlined.

  20. 浅谈工程软件AutoCAD

    Institute of Scientific and Technical Information of China (English)

    庄文强

    2015-01-01

    熟悉 AutoCAD 制图软件的基本操作,了解工程制图绘制的格式和基本要求,加强应用 AutoCAD 绘制二维工程图纸的能力,运用AutoCAD到实际工程项目中,让AutoCAD惠及更多的人。

  1. Chairside CAD/CAM materials. Part 2: Flexural strength testing.

    Science.gov (United States)

    Wendler, Michael; Belli, Renan; Petschelt, Anselm; Mevec, Daniel; Harrer, Walter; Lube, Tanja; Danzer, Robert; Lohbauer, Ulrich

    2017-01-01

    Strength is one of the preferred parameters used in dentistry for determining clinical indication of dental restoratives. However, small dimensions of CAD/CAM blocks limit reliable measurements with standardized uniaxial bending tests. The objective of this study was to introduce the ball-on-three-ball (B3B) biaxial strength test for dental for small CAD/CAM block in the context of the size effect on strength predicted by the Weibull theory. Eight representative chairside CAD/CAM materials ranging from polycrystalline zirconia (e.max ZirCAD, Ivoclar-Vivadent), reinforced glasses (Vitablocs Mark II, VITA; Empress CAD, Ivoclar-Vivadent) and glass-ceramics (e.max CAD, Ivoclar-Vivadent; Suprinity, VITA; Celtra Duo, Dentsply) to hybrid materials (Enamic, VITA; Lava Ultimate, 3M ESPE) have been selected. Specimens were prepared with highly polished surfaces in rectangular plate (12×12×1.2mm(3)) or round disc (Ø=12mm, thickness=1.2mm) geometries. Specimens were tested using the B3B assembly and the biaxial strength was determined using calculations derived from finite element analyses of the respective stress fields. Size effects on strength were determined based on results from 4-point-bending specimens. A good agreement was found between the biaxial strength results for the different geometries (plates vs. discs) using the B3B test. Strength values ranged from 110.9MPa (Vitablocs Mark II) to 1303.21MPa (e.max ZirCAD). The strength dependency on specimen size was demonstrated through the calculated effective volume/surface. The B3B test has shown to be a reliable and simple method for determining the biaxial strength restorative materials supplied as small CAD/CAM blocks. A flexible solution was made available for the B3B test in the rectangular plate geometry. Copyright © 2016 The Academy of Dental Materials. Published by Elsevier Ltd. All rights reserved.

  2. Structured reporting platform improves CAD-RADS assessment.

    Science.gov (United States)

    Szilveszter, Bálint; Kolossváry, Márton; Karády, Júlia; Jermendy, Ádám L; Károlyi, Mihály; Panajotu, Alexisz; Bagyura, Zsolt; Vecsey-Nagy, Milán; Cury, Ricardo C; Leipsic, Jonathon A; Merkely, Béla; Maurovich-Horvat, Pál

    2017-09-18

    Structured reporting in cardiac imaging is strongly encouraged to improve quality through consistency. The Coronary Artery Disease - Reporting and Data System (CAD-RADS) was recently introduced to facilitate interdisciplinary communication of coronary CT angiography (CTA) results. We aimed to assess the agreement between manual and automated CAD-RADS classification using a structured reporting platform. Five readers prospectively interpreted 500 coronary CT angiographies using a structured reporting platform that automatically calculates the CAD-RADS score based on stenosis and plaque parameters manually entered by the reader. In addition, all readers manually assessed CAD-RADS blinded to the automatically derived results, which was used as the reference standard. We evaluated factors influencing reader performance including CAD-RADS training, clinical load, time of the day and level of expertise. Total agreement between manual and automated classification was 80.2%. Agreement in stenosis categories was 86.7%, whereas the agreement in modifiers was 95.8% for "N", 96.8% for "S", 95.6% for "V" and 99.4% for "G". Agreement for V improved after CAD-RADS training (p = 0.047). Time of the day and clinical load did not influence reader performance (p > 0.05 both). Less experienced readers had a higher total agreement as compared to more experienced readers (87.0% vs 78.0%, respectively; p = 0.011). Even though automated CAD-RADS classification uses data filled in by the readers, it outperforms manual classification by preventing human errors. Structured reporting platforms with automated calculation of the CAD-RADS score might improve data quality and support standardization of clinical decision making. Copyright © 2017. Published by Elsevier Inc.

  3. Integration of CAPP with CAD Based on Solid Edge

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    CAD technique and its software products have been d ev eloped independently of CAPP, but the market's requirements on reducing lead-t ime of a new product and promoting automation of design and manufacture processe s need integration of CAPP with CAD. The base of CAXs' integration in product d esign and manufacture is information integration. There are several information integration approaches, for example, by data format transition through special d ata interface, or by standard format file for data ex...

  4. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    Science.gov (United States)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  5. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  6. Spike-based VLSI modeling of the ILD system in the echolocating bat.

    Science.gov (United States)

    Horiuchi, T; Hynna, K

    2001-01-01

    The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.

  7. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  8. VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.

    Science.gov (United States)

    1985-08-01

    purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be

  9. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  10. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  11. Control of autonomous mobile robots using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S.

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.

  12. The cinnamyl alcohol dehydrogenase (CAD gene family in flax (Linum usitatissimum L.: Insight from expression profiling of cads induced by elicitors in cultured flax cells

    Directory of Open Access Journals (Sweden)

    Eom Hee Seung

    2016-01-01

    Full Text Available Cinnamyl alcohol dehydrogenase (CAD is a key enzyme in the biosynthesis of lignin and lignans as it catalyzes the final step of monolignol biosynthesis, using NADPH as a cofactor. In higher plants, CAD is encoded by a multigene family consisting of three major classes. Based on the recently released flax (Linum usitatissimum L. whole-genome sequences, in this study we identified six CAD family genes that contain an ADH_N domain and an ADH_zinc_N domain, which suggests that the putative flax CADs (LuCADs are zinc-dependent alcohol dehydrogenases and members of the plant CAD family. In addition, expression analysis using quantitative real-time PCR revealed spatial variations in the expression of LuCADs in different organs. Comparative analysis between LuCAD enzymatic activity and LuCAD transcripts indicates that the variation of LuCAD enzymatic activities by elicitors is reflected by transcription of LuCADs in flax suspension-cultured cells. Taken together, our genome-wide analysis of CAD genes and the expression profiling of these genes provide valuable information for understanding the function of CADs, and will assist future studies on the physiological role of monolignols associated with plant defense.

  13. A New Method for Compensation and Rematch of Cavity Failure in C-ADS Linac

    CERN Document Server

    Xue, Zhou; Meng, Cai

    2015-01-01

    For proton linear accelerators used in applications such as C-ADS, due to the nature of the operation, it is essential to have beam failures at the rate several orders of magnitude lower than usual performance of similar accelerators. A fault-tolerant mechanism should be mandatorily imposed in order to maintain short recovery time, high uptime and extremely low frequency of beam loss. This paper proposes an innovative and challenging way to use fast electronic devices and Field Programmable Gate Array (FPGA) instead of embedded computers to complete the computation of beam dynamics. The method of building an equivalent model and optimizing using genetic algorithm is shown. Eventually, the results based on the model and algorithm are compared with TRACEWIN simulation to show the precision and correctness of the mechanism.

  14. CAD-DIRECTED INSPECTION PLANNING FOR FREEFORM SURFACE USING CONTACT PROBES

    Institute of Scientific and Technical Information of China (English)

    Chen Manyi; Li Bin; Duan Zhengcheng

    2005-01-01

    A methodology for CAD-directed measurement of freeform surface using a coordinate measuring machine equipped with a touch-trigger probe is presented, mainly including adaptive sampling of measurement points and registration of freeform surface. The proposed sampling method follows four steps:Freeform surface is fitted by bi-cubic B-spline; Curvedness measure of the surface is computed; Given a number of sampling points, an iterative algorithm is constructed for selecting a set of measurement points by employing the curvedness information; The measurement points is regularized for tradeoffbetween maximizing the measurement accuracy and minimizing the sampling time and cost. The aforesaid algorithm is demonstrated in term of a marine propeller blade. An offset surface registration method is presented to improve alignment accuracy of freeform objects, and Monte Carlo simulation is conducted to verify the effectiveness of the method.

  15. VLSI for High-Speed Digital Signal Processing

    Science.gov (United States)

    1994-09-30

    GND K8 X[5] B4 GND F9 VDD K9 X[21 B5 Y[9] FlO out_clk K1O VDD B6 Y[6] FI1 phil-in K11 X[1] B7 Yf4] GI proc[1] LI GND B8 Y[21 G2 proc[O] L2 data[4] B9...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

  16. Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

    Directory of Open Access Journals (Sweden)

    Deepa Yagain

    2014-01-01

    Full Text Available Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

  17. An Algorithm for Classification of 3-D Spherical Spatial Points

    Institute of Scientific and Technical Information of China (English)

    ZHU Qing-xin; Mudur SP; LIU Chang; PENG Bo; WU Jia

    2003-01-01

    This paper presents a highly efficient algorithm for classification of 3D points sampled from lots of spheres, using neighboring relations of spatial points to construct a neighbor graph from points cloud. This algorithm can be used in object recognition, computer vision, and CAD model building, etc.

  18. 简述AutoCAD 2004二次开发工具%The Discussion about the Tools in the Secondary Development of AutoCAD2004

    Institute of Scientific and Technical Information of China (English)

    吴成军

    2009-01-01

    文章对AutoCAD 2004的二次开发工具进行了较为详细的介绍,并对AutoCAD 2004各种二次开发工具的特点进行了分析和比较.为AutoCAD 2004软件使用者进行基于AutoCAD 2004进行二次开发提供了有益的参考.

  19. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation

    Science.gov (United States)

    Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene

    2004-05-01

    We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.

  20. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    Science.gov (United States)

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  1. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    Science.gov (United States)

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.

  2. New VLSI smart sensor for collision avoidance inspired by insect vision

    Science.gov (United States)

    Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran

    1995-01-01

    An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

  3. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  4. The digi-neocognitron: a digital neocognitron neural network model for VLSI.

    Science.gov (United States)

    White, B A; Elmasry, M I

    1992-01-01

    One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.

  5. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  6. Intelligent CAD System for Automatic Detection of Mitotic Cells from Breast Cancer Histology Slide Images Based on Teaching-Learning-Based Optimization

    Directory of Open Access Journals (Sweden)

    Ramin Nateghi

    2014-01-01

    Full Text Available This paper introduces a computer-assisted diagnosis (CAD system for automatic mitosis detection from breast cancer histopathology slide images. In this system, a new approach for reducing the number of false positives is proposed based on Teaching-Learning-Based optimization (TLBO. The proposed CAD system is implemented on the histopathology slide images acquired by Aperio XT scanner (scanner A. In TLBO algorithm, the number of false positives (falsely detected nonmitosis candidates as mitosis ones is defined as a cost function and, by minimizing it, many of nonmitosis candidates will be removed. Then some color and texture (textural features such as those derived from cooccurrence and run-length matrices are extracted from the remaining candidates and finally mitotic cells are classified using a specific support vector machine (SVM classifier. The simulation results have proven the claims about the high performance and efficiency of the proposed CAD system.

  7. Sistema CAD integrado para la edificación

    Directory of Open Access Journals (Sweden)

    Recuero, Alfonso

    1988-12-01

    Full Text Available The development of CAD systems for building construction must not be excessively ambitious to begin with, as this could mean economic problems and a lack of enthusiasm when over —ambitious initial object— ives are not achieved. Building construction covers a very wide range of activities and professionals. In fact, there exists a number of applications which cover the main areas involved in a satisfactory and independent manner: e.g. topography, geometry, structure, installations and management. The Instituto Eduardo Torroja, together with other Research Centres and Tehcnical Project Offices, is working on a research project, the guidelines of which are as follows: The integration of the different exiting applications will be made gradually with a detailed study of their corresponding data bases and their connection to one or more general data bases. Special attention will be paid to the user computer interfaces. The 3-D graphic systems to be used should be more specialised, taking into graphic systems to be used should be more specialised, taking into account the differences that exist between mechanical and building applications. Research is also needed to improved the performance of some graphic algorithms; the structural analysis models to be used must be efficient and adequately complex. Some specific problems, also, such as column slab connections, etc. must be satisfactorily solved. The introduction of artificial intelligence techniques for making decisions on some specific points is also of interest.

    El desarrollo de sistemas CAD para la construcción no debiera ser muy ambicioso en principio, ya que esto podría engendrar problemas económicos y una falta de entusiasmo en el caso de que los objetivos iniciales no puedan ser alcanzados. La construcción de edificios cubre un amplio rango de actividades y de ramas profesionales. De hecho existe un cierto número de aplicaciones que cubren los principales sectores implicados

  8. Optimization of circuits using a constructive learning algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1997-05-01

    The paper presents an application of a constructive learning algorithm to optimization of circuits. For a given Boolean function f. a fresh constructive learning algorithm builds circuits belonging to the smallest F{sub n,m} class of functions (n inputs and having m groups of ones in their truth table). The constructive proofs, which show how arbitrary Boolean functions can be implemented by this algorithm, are shortly enumerated An interesting aspect is that the algorithm can be used for generating both classical Boolean circuits and threshold gate circuits (i.e. analogue inputs and digital outputs), or a mixture of them, thus taking advantage of mixed analogue/digital technologies. One illustrative example is detailed The size and the area of the different circuits are compared (special cost functions can be used to closer estimate the area and the delay of VLSI implementations). Conclusions and further directions of research are ending the paper.

  9. The Enzyme Activity and Substrate Specificity of Two Major Cinnamyl Alcohol Dehydrogenases in Sorghum (Sorghum bicolor), SbCAD2 and SbCAD4.

    Science.gov (United States)

    Jun, Se-Young; Walker, Alexander M; Kim, Hoon; Ralph, John; Vermerris, Wilfred; Sattler, Scott E; Kang, ChulHee

    2017-08-01

    Cinnamyl alcohol dehydrogenase (CAD) catalyzes the final step in monolignol biosynthesis, reducing sinapaldehyde, coniferaldehyde, and p-coumaraldehyde to their corresponding alcohols in an NADPH-dependent manner. Because of its terminal location in monolignol biosynthesis, the variation in substrate specificity and activity of CAD can result in significant changes in overall composition and amount of lignin. Our in-depth characterization of two major CAD isoforms, SbCAD2 (Brown midrib 6 [bmr6]) and SbCAD4, in lignifying tissues of sorghum (Sorghum bicolor), a strategic plant for generating renewable chemicals and fuels, indicates their similarity in both structure and activity to Arabidopsis (Arabidopsis thaliana) CAD5 and Populus tremuloides sinapyl alcohol dehydrogenase, respectively. This first crystal structure of a monocot CAD combined with enzyme kinetic data and a catalytic model supported by site-directed mutagenesis allows full comparison with dicot CADs and elucidates the potential signature sequence for their substrate specificity and activity. The L119W/G301F-SbCAD4 double mutant displayed its substrate preference in the order coniferaldehyde > p-coumaraldehyde > sinapaldehyde, with higher catalytic efficiency than that of both wild-type SbCAD4 and SbCAD2. As SbCAD4 is the only major CAD isoform in bmr6 mutants, replacing SbCAD4 with L119W/G301F-SbCAD4 in bmr6 plants could produce a phenotype that is more amenable to biomass processing. © 2017 American Society of Plant Biologists. All Rights Reserved.

  10. PRODUCT DATA MANAGEMENT DALAM KAITAN DENGAN CAD/CAM

    Directory of Open Access Journals (Sweden)

    Bernardo Nugroho Yahya

    2004-01-01

    Full Text Available The future industry is the one who can manage the information system. Today, communication technology and distributed system computerization already have the ability to implement system that able to exchange and share information between different users. Product Data Management (PDM is an up-to-date and excellent method on managing the exchange and share of information. PDM is able to integrate and manage data analyzing process and documentation of the related product component physically. By adjusting the CAD/CAM on certain condition, the PDM will function maximally by using the information based on STEP (Standard for the Exchange of Product Data model. This article will explain the relationship between PDM system and CAD/CAM on industry. Abstract in Bahasa Indonesia : Sistem informasi merupakan ujung tombak sebuah perusahaan yang unggul di masa depan. Komputerisasi dengan sistem yang terdistribusi dan teknologi komunikasi saat ini memiliki kemampuan untuk mengimplementasikan sistem yang dapat menukar dan men-share informasi antar user yang berbeda. Teknologi yang mendapat cukup perhatian luas dalam hal pertukaran dan sharing informasi ini adalah Product Data Management (PDM. PDM dapat mengintegrasikan dan mengatur proses pengolahan data dan dokumen teknik yang berhubungan dengan komponen fisik produk yang bersangkutan. PDM akan berfungsi maksimal apabila kesesuaian dengan CAD/CAM diatur sedemikian rupa, dihubungkan dengan informasi berbasiskan STEP (Standard for the Exchange of Product Data model. Artikel ini akan menjelaskan hubungan antara sistem PDM dengan CAD/CAM dalam industri. Kata kunci: PDM, Manajemen Data, CAD/CAM, STEP.

  11. Performance and value of CAD-deficient pine- Final Report

    Energy Technology Data Exchange (ETDEWEB)

    Bailian Li; Houmin Chang; Hasan Jameel

    2007-02-28

    The southern US produces 58% of the nation's timber, much of it grown in intensively managed plantations of genetically improved loblolly pine. One of the fastest-growing loblolly pine selections made by the NCSU-Industry Cooperative Tree Improvement Program, whose progeny are widely planted, is also the only known natural carrier of a rare gene, cadn1. This allele codes for deficiency in an enzyme, cinnamyl alcohol dehydrogenase, which catalyzes the last step in the biosynthesis of lignin precursors. This study is to characterize this candidate gene for marker-assisted selection and deployment in the breeding program. This research will enhance the sustainability of forest production in the South, where land-use pressures will limit the total area available in the future for intensively managed plantations. Furthermore, this research will provide information to establish higher-value plantation forests with more desirable wood/fiber quality traits. A rare mutant allele (cad-n1) of the cad gene in loblolly pine (Pinus taeda L.) causes a deficiency in the production of cinnamyl alcohol dehydrogenase (CAD). The effects of this allele were examined by comparing wood density and growth traits of cad-n1 heterozygous trees with those of wild-type trees in a 10-year-old open-pollinated family trial growing under two levels of fertilization in Scotland County, North Carolina. In all, 200 trees were sampled with 100 trees for each treatment. Wood density measurements were collected from wood cores at breast height using x-ray densitometry. We found that the substitution of cad-n1 for a wild-type allele (Cad) was associated with a significant effect on wood density. The cad-n1 heterozygotes had a significantly higher wood density (+2.6%) compared to wild-type trees. The higher density was apparently due to the higher percentage of latewood in the heterozygotes. The fertilization effect was highly significant for both growth and wood density traits. While no cad genotype

  12. Role of radiologists in CAD life-cycle

    Energy Technology Data Exchange (ETDEWEB)

    Pietka, Ewa, E-mail: ewa.pietka@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Kawa, Jacek, E-mail: jacek.kawa@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Spinczyk, Dominik, E-mail: dominik.spinczyk@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Badura, Pawel, E-mail: pawel.badura@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Wieclawek, Wojciech, E-mail: wojciech.wieclawek@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Czajkowska, Joanna, E-mail: joanna.czajkowska@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland); Rudzki, Marcin, E-mail: marcin.rudzki@polsl.pl [Silesian University of Technology, Faculty of Automatic Control, Electronics and Computer Science, ul. Akademicka 16, 44-100 Gliwice (Poland)

    2011-05-15

    A modern CAD (computer-aided diagnosis) system development involves a multidisciplinary team whose members are experts in medical and technical fields. This study indicates the activities of medical experts at various stages of the CAD design, testing, and implementation. Those stages include a medical analysis of the diagnostic problem, data collection, image analysis, evaluation, and clinical verification. At each stage the physicians knowledge and experience are indispensable. The final implementation involves integration with the existing Picture Archiving and Communication System. The term CAD life-cycle describes an overall process of the design, testing, and implementation of a system that in its final form assists the radiologists in their daily clinical routine. Four CAD systems (applied to the bone age assessment, Multiple Sclerosis detection, lung nodule detection, and pneumothorax measurement) developed in our laboratory are given as examples of how consecutive stages are developed by the multidisciplinary team. Specific advantages of the CAD implementation that include the daily clinical routine as well as research and education activities are discussed.

  13. Development and application of a segmentation routine in a mammographic mass CAD system

    Science.gov (United States)

    Catarious, David M., Jr.; Baydush, Alan H.; Floyd, Carey E., Jr.

    2004-05-01

    The purpose of this paper is to present a new segmentation routine developed for mammographic masses. We previously developed a computer-aided detection (CAD) system for mammographic masses that employed a simple but imprecise segmentation procedure. To improve the systems performance, an iterative, linear segmentation routine was developed. The routine begins by employing a linear discriminant function to determine the optimal threshold between estimates of an objects interior and exterior pixels. After applying the threshold and identifying the objects outline, two constraints are applied to minimize the influence of extraneous background structures. Each iteration further refines the outline until the stopping criterion is reached. The segmentation algorithm was tested on a database of 181 mammographic images that contained forty-nine malignant and fifty benign masses. A set of suspicious regions of interest (ROIs) was found using the previous CAD system. Twenty features were measured from the regions before and after applying the new segmentation routine. The difference in the features discriminatory ability was examined via receiver operating characteristic (ROC) analysis. A significant performance difference was observed in many features, particularly those describing the object border. Free-response ROC (FROC) curves were utilized to examine how the overall CAD system performance changed with the inclusion of the segmentation routine. The FROC performance appeared to be improved, especially for malignant masses. When detecting 90% of the malignant masses, the previous system achieved 4.4 false positives per image (FPpI) compared to the post-segmentation systems 3.7 FPpI. At 85%, the respective FPpI are 4.1 and 2.1.

  14. Comparative Analysis of Stein’s and Euclid’s Algorithm with BIST for GCD Computations

    Directory of Open Access Journals (Sweden)

    Sachin D.Kohale

    2013-02-01

    Full Text Available The Very Large Scale Integration(VLSI has a dramatic impacton the growth of digital technology. VLSI has not only reducedthe size and cost, but also increased the complexity of thecircuits. Due to increase in complexity, it is difficult to testcircuits. To reduce this problem of testing, it is advantageous toadd another IC along with it which will test and correct errorsby itself. This IC is known as Built in Self Test(BIST.In thispaper , we are particularly concentrating upon finding thecomparative parameters of Euclid’s and Stein’s Algorithm ,which is used to find greatest common divisor(GCD of two nonnegative integers. Thus, the best parameters to be found can beused effectively for finding gcd , This indirectly reduces time forcalculating greatest common divisor , which is being used veryfrequently in communication applications.

  15. Design strategy of intelligent CAD for welding positioner scheme design

    Institute of Scientific and Technical Information of China (English)

    林三宝; 杨春利; 吴林; 黎明

    2002-01-01

    Traditional CAD technique does not support the design processes such as function definition, conceptual design and preliminary design, which are most creative and play significant roles on the design quality. Because scheme design has close relationship with product structure, performance and technology cost, it is important for applying the intelligent CAD of scheme design to improve the quality and competitive level of the product. The definition and function of welding positioner are discussed in this paper. The new definition of welding positioner extends the research scope of welding positioner to welding fixture and welding positioning motion mechanism. The design process of welding fixture and positioning motion system is described, and the cased-based and knowledge-based design strategy of welding positioner scheme design intelligent CAD is then put forward, which lays foundation for developing proto-type system of welding positioner scheme design.

  16. Collaborative Design in PDM/3D CAD Integrated Environment

    Institute of Scientific and Technical Information of China (English)

    CHEN Zhuoning; ZHANG Fen; YAN Xiaoguang; BIN Hongzan

    2006-01-01

    Some key issues in supporting collaborative design in product data management (PDM) system and 3D computer aided design(CAD) system integrated environment are analyzed. The general architecture of the integrated environment is divided into five tiers and employs the transparently integrated mode, with the mode, function calling and information exchanging among independent PDM and CAD processes are carried out via message translation /parse approach.Product layout feature(PLF ) model definition is presented,PLF model is used to represent design intention at the preliminary design phase. The collaborative design methodology employing the PLF model in PDM/3D CAD integrated environment is analyzed. The design methodology can speed up the design process, reduce the investment and improve the product quality.

  17. Interoperability of CAD Standards and Robotics in CIME

    DEFF Research Database (Denmark)

    Sørensen, Torben

    The research presented in this dissertation concerns the identification of problems and provision of solutions for increasing the degree of interoperability between CAD, CACSD (Computer Aided Control Systems Design) and CAR (Computer Aided Robotics) in Computer Integrated Manufacturing and Engine......The research presented in this dissertation concerns the identification of problems and provision of solutions for increasing the degree of interoperability between CAD, CACSD (Computer Aided Control Systems Design) and CAR (Computer Aided Robotics) in Computer Integrated Manufacturing......· The development of a STEP based interface for general control system data and functions, especially related to robot motion control for interoperability of CAD, CACSD, and CAR systems for the extension of the inter-system communication capabilities beyond the stage achieved up to now.This interface development...

  18. AutoCAD electrical 2013 for electrical control designers

    CERN Document Server

    Tickoo, Sham; CADCIM Technologies

    2013-01-01

    The AutoCAD Electrical 2013 for Electrical Control Designers textbook has been written to assist the engineering students and the practicing designers learn the application of various AutoCAD Electrical tools and options for creating electrical control designs. After reading this textbook, the users will be able to create professional electrical-control drawings easily and effectively. Moreover, the users will be able to automate various control engineering tasks such as building circuits, numbering wires, creating bills of materials, and many more. The textbook takes the users across a wide spectrum of electrical control drawings through progressive examples and numerous illustrations and exercises, thereby making it an ideal guide for both the novice and the advanced users. Salient Features of the Textbook Consists of 14 chapters that are organized in a pedagogical sequence covering various tools and features of AutoCAD Electrical such as schematic drawings, parametric and non-parametric PLC modules, Circu...

  19. CAD-model-based vision for space applications

    Science.gov (United States)

    Shapiro, Linda G.

    1988-01-01

    A pose acquisition system operating in space must be able to perform well in a variety of different applications including automated guidance and inspections tasks with many different, but known objects. Since the space station is being designed with automation in mind, there will be CAD models of all the objects, including the station itself. The construction of vision models and procedures directly from the CAD models is the goal of this project. The system that is being designed and implementing must convert CAD models to vision models, predict visible features from a given view point from the vision models, construct view classes representing views of the objects, and use the view class model thus derived to rapidly determine the pose of the object from single images and/or stereo pairs.

  20. AutoCAD platform customization user interface, AutoLISP, VBA, and beyond

    CERN Document Server

    Ambrosius, Lee

    2015-01-01

    Take control of AutoCAD to boost the speed, quality, and precision of your work Senior drafters and savvy users are increasingly taking AutoCAD customization out of the hands of system administrators, and taking control of their own workflow. In AutoCAD Platform Customization, Autodesk customization guru Lee Ambrosius walks you through a multitude of customization options using detailed tutorials and real-world examples applicable to AutoCAD, AutoCAD LT, Civil 3D, Plant 3D, and other programs built on the AutoCAD platform. By unleashing the full power of the software, you'll simplify and str