Self arbitrated VLSI asynchronous sequential circuits
Whitaker, S.; Maki, G.
1990-01-01
A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.
Asynchronous sequential machine design and analysis
Tinder, Richard
2009-01-01
Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous state machine design and analysis presented in two parts: Part I on the background fundamentals related to asynchronous sequential logic circuits generally, and Part II on self-timed systems, high-performance asynchronous programmable sequencers, and arbiters.Part I provides a detailed review of the background fundamentals for the design and analysis of asynchronous finite state machines (FSMs). Included are the basic models, use of fully documented state diagrams, and the design and charac
Devi, T Kalavathi; Palaniappan, Sakthivel
2015-01-01
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.
Implementation of Optimized Reversible Sequential and Combinational Circuits for VLSI Applications
Directory of Open Access Journals (Sweden)
P. Mohan Krishna
2014-04-01
Full Text Available Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In this project we present sequential and combinational circuit with reversible logic gates which are simulated in Xilinx ISE and by writing the code in VHDL . we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on CMOS with pass transistor gates . Here the total reversible Adder is designed using EDA tools. We will analyze the VLSI limitations like power consumption and area of designed circuits.
Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.
Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo
2011-01-01
We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.
Schedule-based sequential localization in asynchronous wireless networks
Zachariah, Dave; De Angelis, Alessio; Dwivedi, Satyam; Händel, Peter
2014-12-01
In this paper, we consider the schedule-based network localization concept, which does not require synchronization among nodes and does not involve communication overhead. The concept makes use of a common transmission sequence, which enables each node to perform self-localization and to localize the entire network, based on noisy propagation-time measurements. We formulate the schedule-based localization problem as an estimation problem in a Bayesian framework. This provides robustness with respect to uncertainty in such system parameters as anchor locations and timing devices. Moreover, we derive a sequential approximate maximum a posteriori (AMAP) estimator. The estimator is fully decentralized and copes with varying noise levels. By studying the fundamental constraints given by the considered measurement model, we provide a system design methodology which enables a scalable solution. Finally, we evaluate the performance of the proposed AMAP estimator by numerical simulations emulating an impulse-radio ultra-wideband (IR-UWB) wireless network.
Indian Academy of Sciences (India)
S Jayanthy; M C Bhuvaneswari
2015-02-01
In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.
Einspruch, Norman G
1986-01-01
VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special
Basu, D K
2014-01-01
Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...
Kemeny, Sabrina E.
1994-01-01
Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional
An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic
Foster, D. L.
2012-01-01
For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…
An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic
Foster, D. L.
2012-01-01
For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…
Chandrasetty, Vikram Arkalgud
2011-01-01
This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic
Einspruch, Norman G; Gildenblat, Gennady Sh
1987-01-01
VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec
VLSI electronics microstructure science
1982-01-01
VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t
VLSI electronics microstructure science
1981-01-01
VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi
Einspruch, Norman G
1989-01-01
VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The
Energy Technology Data Exchange (ETDEWEB)
Hojat, S.
1986-01-01
The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.
DEFF Research Database (Denmark)
Rasmussen, Ole Steen
This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....
VLSI Universal Noiseless Coder
Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi
1989-01-01
Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.
Einspruch, Norman G
1984-01-01
VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section
Verweij, Jan F.
1993-01-01
Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was
Einspruch, Norman G
1987-01-01
VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.
Chen, Wai-Kai
2009-01-01
Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.
VLSI implementation of a fairness ATM buffer system
DEFF Research Database (Denmark)
Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard
1996-01-01
This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...
Very Large Scale Integration (VLSI).
Yeaman, Andrew R. J.
Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…
Designing asynchronous circuits using NULL convention logic (NCL)
Smith, Scott
2009-01-01
Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design
McKenzie, Neil
1989-12-01
We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.
Chen, Wai-Kai
2007-01-01
Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.
VLSI signal processing technology
Swartzlander, Earl
1994-01-01
This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in...
VLSI Architectures for Computing DFT's
Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.
1986-01-01
Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.
Synaptic dynamics in analog VLSI.
Bartolozzi, Chiara; Indiveri, Giacomo
2007-10-01
Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.
VLSI implementations for image communications
Pirsch, P
1993-01-01
The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits
Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney
2006-01-01
We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.
VLSI mixed signal processing system
Alvarez, A.; Premkumar, A. B.
1993-01-01
An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.
Fundamentals of Microelectronics Processing (VLSI).
Takoudis, Christos G.
1987-01-01
Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)
Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques
Directory of Open Access Journals (Sweden)
Nikos Sklavos
2002-01-01
Full Text Available An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently in Wireless Encryption Protocols and high speed networks.
The Fifth NASA Symposium on VLSI Design
1993-01-01
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.
A Design Methodology for Optoelectronic VLSI
2007-01-01
it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a
Compositional asynchronous membrane systems
Institute of Scientific and Technical Information of China (English)
Cosmin Bonchis; Cornel Izbasa; Gabriel Ciobanu
2007-01-01
This paper presents an algorithmic way of building complex membrane systems by coupling elementary membranes. Its application seems particularly valuable in the case of asynchronous membrane systems, since the resulting membrane system remains asynchronous. The composition method is based on a handshake mechanism implemented by using antiport rules and promoters.
VLSI Watermark Implementations and Applications
Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly
2008-01-01
This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Implementation of Plasmonics in VLSI
Directory of Open Access Journals (Sweden)
Shreya Bhattacharya
2012-12-01
Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.
Low latency asynchronous interface circuits
Energy Technology Data Exchange (ETDEWEB)
Sadowski, Greg
2017-06-20
In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.
VLSI Processor For Vector Quantization
Tawel, Raoul
1995-01-01
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
Existence test for asynchronous interval iterations
DEFF Research Database (Denmark)
Madsen, Kaj; Caprani, O.; Stauning, Ole
1997-01-01
In the search for regions that contain fixed points ofa real function of several variables, tests based on interval calculationscan be used to establish existence ornon-existence of fixed points in regions that are examined in the course ofthe search. The search can e.g. be performed...... as a synchronous (sequential) interval iteration:In each iteration step all components of the iterate are calculatedbased on the previous iterate. In this case it is straight forward to base simple interval existence and non-existencetests on the calculations done in each step of the iteration. The search can also...... be performed as an asynchronous (parallel) iteration: Only a few components are changed in each stepand this calculation is in general based on components from differentprevious iterates. For the asynchronous iteration it turns out thatsimple tests of existence and non-existence can be based...
Surface and interface effects in VLSI
Einspruch, Norman G
1985-01-01
VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import
Implementing neural architectures using analog VLSI circuits
Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.
1989-05-01
Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.
VLSI implementation of neural networks.
Wilamowski, B M; Binfet, J; Kaynak, M O
2000-06-01
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.
VOLTAGE REGULATORS ASYNCHRONOUS GENERATORS
Directory of Open Access Journals (Sweden)
Grigorash O. V.
2015-06-01
Full Text Available A promising is currently the use of asynchronous generators with capacitive excitation as a source of electricity in stand-alone power systems. Drive asynchronous generators may exercise as a thermal engine and wind wheel wind power plant or turbines of small hydropower plants. The article discusses the structural and schematics of voltage stabilizers and frequency of asynchronous generators with improved operational and technical specifications. Technical novelty of design solutions of the magnetic system and stabilizers asynchronous generator of electricity parameters confirmed by the patents for the invention of the Russian Federation. The proposed technical solution voltage stabilizer asynchronous generators, can reduce the weight of the block capacitors excitation and reactive power compensation, as well as to simplify the control system power circuit which has less power electronic devices. For wind power plants it is an important issue not only to stabilize the voltage of the generator, but also the frequency of the current. Recommend functionality stabilizer schemes parameters of electric power made for direct frequency converters with artificial and natural switching power electronic devices. It is also proposed as part of stabilization systems use single-phase voltage, three-phase transformers with rotating magnetic field, reduce the level of electromagnetic interference generated by power electronic devices for switching, enhance the efficiency and reliability of the stabilizer.
Asynchronized synchronous machines
Botvinnik, M M
1964-01-01
Asynchronized Synchronous Machines focuses on the theoretical research on asynchronized synchronous (AS) machines, which are "hybrids of synchronous and induction machines that can operate with slip. Topics covered in this book include the initial equations; vector diagram of an AS machine; regulation in cases of deviation from the law of full compensation; parameters of the excitation system; and schematic diagram of an excitation regulator. The possible applications of AS machines and its calculations in certain cases are also discussed. This publication is beneficial for students and indiv
Asynchronous Multiparty Computation
DEFF Research Database (Denmark)
Damgård, Ivan Bjerre; Geisler, Martin; Krøigaard, Mikkel
2009-01-01
We propose an asynchronous protocol for general multiparty computation. The protocol has perfect security and communication complexity where n is the number of parties, |C| is the size of the arithmetic circuit being computed, and k is the size of elements in the underlying field. The protocol g...
Multiparty Asynchronous Session Types
DEFF Research Database (Denmark)
Honda, Kohei; Yoshida, Nobuko; Carbone, Marco
2016-01-01
peers are directly abstracted as a global scenario. Global types retain the friendly type syntax of binary session types while specifying dependencies and capturing complex causal chains of multiparty asynchronous interactions. A global type plays the role of a shared agreement among communication peers...
DEFF Research Database (Denmark)
Panicker, Rajesh; Puthusserypady, Sadasivan; Sun, Ying
2010-01-01
An asynchronous hybrid brain-computer interface (BCI) system combining the P300 and steady-state visually evoked potentials (SSVEP) paradigms is introduced. A P300 base system is used for information transfer, and is augmented to include SSVEP for control state detection. The proposed system has...
Redundant Asynchronous Microprocessor System
Meyer, G.; Johnston, J. O.; Dunn, W. R.
1985-01-01
Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.
Asynchronous updating of threshold-coupled chaotic neurons
Indian Academy of Sciences (India)
Manish Dev Shirmali; Sudeshna Sinha; Kazuyuki Aihara
2008-06-01
We study a network of chaotic model neurons incorporating threshold activated coupling. We obtain a wide range of spatiotemporal patterns under varying degrees of asynchronicity in the evolution of the neuronal components. For instance, we find that sequential updating of threshold-coupled chaotic neurons can yield dynamical switching of the individual neurons between two states. So varying the asynchronicity in the updating scheme can serve as a control mechanism to extract different responses, and this can have possible applications in computation and information processing.
Text Mining: (Asynchronous Sequences
Directory of Open Access Journals (Sweden)
Sheema Khan
2014-12-01
Full Text Available In this paper we tried to correlate text sequences those provides common topics for semantic clues. We propose a two step method for asynchronous text mining. Step one check for the common topics in the sequences and isolates these with their timestamps. Step two takes the topic and tries to give the timestamp of the text document. After multiple repetitions of step two, we could give optimum result.
Østvand, Jon
2007-01-01
In this thesis multipliers with and without completion detection has been implemented using a 90 nm library to compare their properties reguarding completion time, area and power consumption. The structures tested were array and shiftand-add multipliers. The results were that when having larger bit-lengths, an asynchronous shift-and-add multiplier with completion detection can yield good completion times compared to a regular shift-and-add multiplier. Due to the large cost in area and power c...
Behavioral synthesis of asynchronous circuits
DEFF Research Database (Denmark)
Nielsen, Sune Fallgaard
2005-01-01
This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...
A coherent VLSI design environment
Penfield, Paul, Jr.
1988-05-01
The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.
Associative Pattern Recognition In Analog VLSI Circuits
Tawel, Raoul
1995-01-01
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Compact MOSFET models for VLSI design
Bhattacharyya, A B
2009-01-01
Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations
Directory of Open Access Journals (Sweden)
Ausif Mahmood
1996-01-01
a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.
Labeled Postings for Asynchronous Interaction
ChanLin, Lih-Juan; Chen, Yong-Ting; Chan, Kung-Chi
2009-01-01
The Internet promotes computer-mediated communications, and so asynchronous learning network systems permit more flexibility in time, space, and interaction than synchronous mode of learning. The key point of asynchronous learning is the materials for web-aided teaching and the flow of knowledge. This research focuses on improving online…
Alexander, George
1984-01-01
Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…
Pro asynchronous programming with .NET
Blewett, Richard; Ltd, Rock Solid Knowledge
2014-01-01
Pro Asynchronous Programming with .NET teaches the essential skill of asynchronous programming in .NET. It answers critical questions in .NET application development, such as: how do I keep my program responding at all times to keep my users happy how do I make the most of the available hardware how can I improve performanceIn the modern world, users expect more and more from their applications and devices, and multi-core hardware has the potential to provide it. But it takes carefully crafted code to turn that potential into responsive, scalable applications.With Pro Asynchronous Programming
VLSI 'smart' I/O module development
Kirk, Dan
The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.
Harnessing VLSI System Design with EDA Tools
Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj
2012-01-01
This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...
VLSI Microsystem for Rapid Bioinformatic Pattern Recognition
Fang, Wai-Chi; Lue, Jaw-Chyng
2009-01-01
A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).
Leak detection utilizing analog binaural (VLSI) techniques
Hartley, Frank T. (Inventor)
1995-01-01
A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Modular VLSI Reed-Solomon Decoder
Hsu, In-Shek; Truong, Trieu-Kie
1991-01-01
Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.
Generating Weighted Test Patterns for VLSI Chips
Siavoshi, Fardad
1990-01-01
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
Optimization of reversible sequential circuits
Sayem, Abu Sadat Md
2010-01-01
In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.
High performance genetic algorithm for VLSI circuit partitioning
Dinu, Simona
2016-12-01
Partitioning is one of the biggest challenges in computer-aided design for VLSI circuits (very large-scale integrated circuits). This work address the min-cut balanced circuit partitioning problem- dividing the graph that models the circuit into almost equal sized k sub-graphs while minimizing the number of edges cut i.e. minimizing the number of edges connecting the sub-graphs. The problem may be formulated as a combinatorial optimization problem. Experimental studies in the literature have shown the problem to be NP-hard and thus it is important to design an efficient heuristic algorithm to solve it. The approach proposed in this study is a parallel implementation of a genetic algorithm, namely an island model. The information exchange between the evolving subpopulations is modeled using a fuzzy controller, which determines an optimal balance between exploration and exploitation of the solution space. The results of simulations show that the proposed algorithm outperforms the standard sequential genetic algorithm both in terms of solution quality and convergence speed. As a direction for future study, this research can be further extended to incorporate local search operators which should include problem-specific knowledge. In addition, the adaptive configuration of mutation and crossover rates is another guidance for future research.
Jiang, P C; Chen, H
2006-01-01
VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.
Analogue VLSI for probabilistic networks and spike-time computation.
Murray, A
2001-02-01
The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.
Parallel optimization algorithms and their implementation in VLSI design
Lee, G.; Feeley, J. J.
1991-01-01
Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.
Trends and challenges in VLSI technology scaling towards 100 nm
Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram
Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj
1993-01-01
Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.
Design of Asynchronous Sequential Circuits using Reversible Logic Gates
Directory of Open Access Journals (Sweden)
Bahram Dehghan
2012-09-01
Full Text Available In recent literature, Reversible logic has become one of the promising arena in low power dissipating circuit design in the past few years and has found its applications in low power CMOS circuits ,optical information processing and nanotechnology. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents asynchronoussequential circuits and circuits without hazard effect using reversible logic gates. I illustrate that we can produce AND, OR, NAND, NOR, EXOR and EXNOR outputs in one design using reversible logic gates. Also, I will evaluate the proposed circuits. The results show that reversible logic can be used to design these circuits. In this paper, the number of gates and garbage outputs is considered.
A High-Speed Asynchronous Communication Technique for MOS (Metal-Oxide-Semiconductor) VLSI Systems.
1985-12-01
by a well controlled amount; rather than use an active delay line the passive delay inherent in the pc board traces could be used. The transmission...in a synchronous system without a detailed analysis of the actual delays involved. The technique provides phase jitter inmunity of close to 1/4 of .~k
State assignment approach to asynchronous CMOS circuit design
Kantabutra, Vitit; Andreou, Andreas G.
1994-04-01
We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.
C. Grelck; H. Wiesinger
2014-01-01
Asynchronous adaptive specialization of rank- and shape-generic code for processing immutable (purely functional) multi-dimensional arrays has proven to be an effective technique to reconcile the desire for abstract specifications with the need to achieve reasonably high performance in sequential as
Yang, Dazhi; Richardson, Jennifer C.; French, Brian F.; Lehman, James D.
2011-01-01
The purpose of this study was to develop and validate a content analysis model for assessing students' cognitive learning in asynchronous online discussions. It adopted a fully mixed methods design, in which qualitative and quantitative methods were employed sequentially for data analysis and interpretation. Specifically, the design was a…
Yang, Dazhi; Richardson, Jennifer C.; French, Brian F.; Lehman, James D.
2011-01-01
The purpose of this study was to develop and validate a content analysis model for assessing students' cognitive learning in asynchronous online discussions. It adopted a fully mixed methods design, in which qualitative and quantitative methods were employed sequentially for data analysis and interpretation. Specifically, the design was a…
Asynchronous Bounded Expected Delay Networks
Bakhshi, Rena; Fokkink, Wan; Pang, Jun
2010-01-01
The commonly used asynchronous bounded delay (ABD) network models assume a fixed bound on message delay. We propose a probabilistic network model, called asynchronous bounded expected delay (ABE) model. Instead of a strict bound, the ABE model requires only a bound on the expected message delay. While the conditions of ABD networks restrict the set of possible executions, in ABE networks all asynchronous executions are possible, but executions with extremely long delays are less probable. In contrast to ABD networks, ABE networks cannot be synchronised efficiently. At the example of an election algorithm, we show that the minimal assumptions of ABE networks are sufficient for the development of efficient algorithms. For anonymous, unidirectional ABE rings of known size N we devise a probabilistic leader election algorithm having average message and time complexity O(N).
An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs
Directory of Open Access Journals (Sweden)
Ching-Hsing Luo
2011-07-01
Full Text Available In this work, an asynchronous multi-sensor micro control unit (MCU core is proposed for wireless body sensor networks (WBSNs. It consists of asynchronous interfaces, a power management unit, a multi-sensor controller, a data encoder (DE, and an error correct coder (ECC. To improve the system performance and expansion abilities, the asynchronous interface is created for handshaking different clock domains between ADC and RF with MCU. To increase the use time of the WBSN system, a power management technique is developed for reducing power consumption. In addition, the multi-sensor controller is designed for detecting various biomedical signals. To prevent loss error from wireless transmission, use of an error correct coding technique is important in biomedical applications. The data encoder is added for lossless compression of various biomedical signals with a compression ratio of almost three. This design is successfully tested on a FPGA board. The VLSI architecture of this work contains 2.68-K gate counts and consumes power 496-μW at 133-MHz processing rate by using TSMC 0.13-μm CMOS process. Compared with the previous techniques, this work offers higher performance, more functions, and lower hardware cost than other micro controller designs.
VLSI Circuits for High Speed Data Conversion
1994-05-16
Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp
Single Spin Logic Implementation of VLSI Adders
Shukla, Soumitra
2011-01-01
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.
An Analog VLSI Saccadic Eye Movement System
1994-01-01
In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...
Communication Protocols Augmentation in VLSI Design Applications
Directory of Open Access Journals (Sweden)
Kanhu Charan Padhy
2015-05-01
Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
VLSI binary multiplier using residue number systems
Energy Technology Data Exchange (ETDEWEB)
Barsi, F.; Di Cola, A.
1982-01-01
The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.
Positive semidefinite integrated covariance estimation, factorizations and asynchronicity
DEFF Research Database (Denmark)
Sauri, Orimar; Lunde, Asger; Laurent, Sébastien;
2017-01-01
An estimator of the ex-post covariation of log-prices under asynchronicity and microstructure noise is proposed. It uses the Cholesky factorization of the covariance matrix in order to exploit the heterogeneity in trading intensities to estimate the different parameters sequentially with as many...... observations as possible. The estimator is positive semidefinite by construction. We derive asymptotic results and confirm their good finite sample properties by means of a Monte Carlo simulation. In the application we forecast portfolio Value-at-Risk and sector risk exposures for a portfolio of 52 stocks. We...
A Verification System for Distributed Objects with Asynchronous Method Calls
Ahrendt, Wolfgang; Dylla, Maximilian
We present a verification system for Creol, an object-oriented modeling language for concurrent distributed applications. The system is an instance of KeY, a framework for object-oriented software verification, which has so far been applied foremost to sequential Java. Building on KeY characteristic concepts, like dynamic logic, sequent calculus, explicit substitutions, and the taclet rule language, the system presented in this paper addresses functional correctness of Creol models featuring local cooperative thread parallelism and global communication via asynchronous method calls. The calculus heavily operates on communication histories which describe the interfaces of Creol units. Two example scenarios demonstrate the usage of the system.
Wavelength-encoded OCDMA system using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal
2007-07-01
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
Technology computer aided design simulation for VLSI MOSFET
Sarkar, Chandan Kumar
2013-01-01
Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and
The VLSI-PLM Board: Design, Construction, and Testing
1989-03-01
Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The
Bilinear Interpolation Image Scaling Processor for VLSI
Directory of Open Access Journals (Sweden)
Ms. Pawar Ashwini Dilip
2014-05-01
Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process
VLSI circuits for high speed data conversion
Wooley, Bruce A.
1994-05-01
The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.
Acquiring Knowledge from Asynchronous Discussion
Teo, Yiong Hwee; Webster, Len
2008-01-01
This article discusses a study which was designed to explore how online scaffolding can be incorporated to support knowledge acquisition in asynchronous discussion. A group of Singapore preservice teachers engaged in collaborative critiquing of videos before they embarked on their video projects to illustrate what constitutes good and bad video…
Asymptotic behavior of asynchronous stochasticapproximation
Institute of Scientific and Technical Information of China (English)
方海涛; 陈翰馥
2001-01-01
The pathwise convergence of a distributed, asynchronous stochastic approximation (SA) scheme is analyzed. The conditions imposed on the step size and noise are the weakest in comparison with the existing ones. The step sizes in different processors are allowed to be different, and the time_delays between processors are also allowed to be different and even time_varying.
The 1992 4th NASA SERC Symposium on VLSI Design
Whitaker, Sterling R.
1992-01-01
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.
Interaction of algorithm and implementation for analog VLSI stereo vision
Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.
1991-07-01
Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.
Duong, T. A.
2004-01-01
In this paper, we present a new, simple, and optimized hardware architecture sequential learning technique for adaptive Principle Component Analysis (PCA) which will help optimize the hardware implementation in VLSI and to overcome the difficulties of the traditional gradient descent in learning convergence and hardware implementation.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...
NASA Space Engineering Research Center for VLSI System Design
1993-01-01
This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.
Design and Verification of High-Speed VLSI Physical Design
Institute of Scientific and Technical Information of China (English)
Dian Zhou; Rui-Ming Li
2005-01-01
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.
Memory Based Machine Intelligence Techniques in VLSI hardware
James, Alex Pappachen
2012-01-01
We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.
VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network
Directory of Open Access Journals (Sweden)
Mohd Asyraf Mansor
2016-09-01
Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.
Wald, Abraham
2013-01-01
In 1943, while in charge of Columbia University's Statistical Research Group, Abraham Wald devised Sequential Design, an innovative statistical inference system. Because the decision to terminate an experiment is not predetermined, sequential analysis can arrive at a decision much sooner and with substantially fewer observations than equally reliable test procedures based on a predetermined number of observations. The system's immense value was immediately recognized, and its use was restricted to wartime research and procedures. In 1945, it was released to the public and has since revolutio
VLSI Design of a Turbo Decoder
Fang, Wai-Chi
2007-01-01
A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.
Analog VLSI neural network integrated circuits
Kub, F. J.; Moon, K. K.; Just, E. A.
1991-01-01
Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.
Relaxation Based Electrical Simulation for VLSI Circuits
Directory of Open Access Journals (Sweden)
S. Rajkumar
2012-06-01
Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.
Multi-net optimization of VLSI interconnect
Moiseev, Konstantin; Wimer, Shmuel
2015-01-01
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...
PLA realizations for VLSI state machines
Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.
1990-01-01
A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.
Asynchronous control for networked systems
Rubio, Francisco; Bencomo, Sebastián
2015-01-01
This book sheds light on networked control systems; it describes different techniques for asynchronous control, moving away from the periodic actions of classical control, replacing them with state-based decisions and reducing the frequency with which communication between subsystems is required. The text focuses specially on event-based control. Split into two parts, Asynchronous Control for Networked Systems begins by addressing the problems of single-loop networked control systems, laying out various solutions which include two alternative model-based control schemes (anticipatory and predictive) and the use of H2/H∞ robust control to deal with network delays and packet losses. Results on self-triggering and send-on-delta sampling are presented to reduce the need for feedback in the loop. In Part II, the authors present solutions for distributed estimation and control. They deal first with reliable networks and then extend their results to scenarios in which delays and packet losses may occur. The novel ...
Queue-Dispatch Asynchronous Systems
Geeraerts, Gilles; Raskin, Jean-François
2012-01-01
To make the development of efficient multi-core applications easier, libraries, such as Grand Central Dispatch, have been proposed. When using such a library, the programmer writes so-called blocks, which are chunks of codes, and dispatches them, using synchronous or asynchronous calls, to several types of waiting queues. A scheduler is then responsible for dispatching those blocks on the available cores. Blocks can synchronize via a global memory. In this paper, we propose Queue-Dispatch Asynchronous Systems as a mathematical model that faithfully formalizes the synchronization mechanisms and the behavior of the scheduler in those systems. We study in detail their relationships to classical formalisms such as pushdown systems, Petri nets, fifo systems, and counter systems. Our main technical contributions are precise worst-case complexity results for the Parikh coverability problem for several subclasses of our model.
Behavioral synthesis of asynchronous circuits
DEFF Research Database (Denmark)
Nielsen, Sune Fallgaard
2005-01-01
domain by introducing a computation model, which resembles the synchronous datapath and control architecture, but which is completely asynchronous. The model contains the possibility for isolating some or all of the functional units by locking their respective inputs and outputs while the functional unit....... The datapath and control architecture is then expressed in the Balsa-language, and using syntax directed compilation a corresponding handshake circuit implementation (and eventually a layout) is produced....
GAMIFICATION IN ASYNCHRONOUS EDUCATION PROCESS
Directory of Open Access Journals (Sweden)
B. P. Dyakonov
2016-01-01
Full Text Available The author of the paper discourses on the prospects of education in the context of the global tendency towards informatization and virtualization of the modern world, influence of these processes on personalized senses of education and educational values and related problems of methodological and technological education in relation to the personalized meanings and educational values. Educational individualization is defined by the author as the most expected way of educational evolution. Distance learning is studied as the main example of the modern transformative educational model. Asynchronous education is explored and characterized as one of the distance learning examples. While defining what asynchronous distance learning is, the author explores its role in the specifics of forming a subject to subject educational approach, while forecasting difficulties in creating holistic asynchronous educational environment. Gamification techniques in the educational process are studied with their respective opportunities and threats, examples in grad and post grad professional studies are provided, including but not limited to foreign language studies. Addictiveness as the goal and means of a build in gamification process is explored as the way to bridge the gap between students and the educators. The author studies gamification in the context of minimizing negative connotations from the educational process, while controversies between pain and game approaches of getting knowledge are brought into light.
A massively asynchronous, parallel brain
Zeki, Semir
2015-01-01
Whether the visual brain uses a parallel or a serial, hierarchical, strategy to process visual signals, the end result appears to be that different attributes of the visual scene are perceived asynchronously—with colour leading form (orientation) by 40 ms and direction of motion by about 80 ms. Whatever the neural root of this asynchrony, it creates a problem that has not been properly addressed, namely how visual attributes that are perceived asynchronously over brief time windows after stimulus onset are bound together in the longer term to give us a unified experience of the visual world, in which all attributes are apparently seen in perfect registration. In this review, I suggest that there is no central neural clock in the (visual) brain that synchronizes the activity of different processing systems. More likely, activity in each of the parallel processing-perceptual systems of the visual brain is reset independently, making of the brain a massively asynchronous organ, just like the new generation of more efficient computers promise to be. Given the asynchronous operations of the brain, it is likely that the results of activities in the different processing-perceptual systems are not bound by physiological interactions between cells in the specialized visual areas, but post-perceptually, outside the visual brain. PMID:25823871
Institute of Scientific and Technical Information of China (English)
Zhong-zhi Bai
2002-01-01
We study the numerical behaviours of the relaxed asynchronous multisplitting methods for the linear complementarity problems by solving some typical problems from practical applications on a real multiprocessor system. Numerical results show that the parallel multisplitting relaxation methods always perform much better than the corresponding sequential alternatives, and that the asynchronous multisplitting relaxation methods often outperform their corresponding synchronous counterparts. Moreover, the two-sweep relaxed multisplitting methods have better convergence properties than their corresponding one-sweep relaxed ones in the sense that they have larger convergence domains and faster convergence speeds. Hence, the asynchronous multisplitting unsymmetric relaxation iterations should be the methods of choice for solving the large sparse linear complementarity problems in the parallel computing environments.
Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.
Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta
2012-01-01
Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.
Dante, V; Del Giudice, P; Mattia, M
2001-01-01
We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.
Emergent auditory feature tuning in a real-time neuromorphic VLSI system
Directory of Open Access Journals (Sweden)
Sadique eSheik
2012-02-01
Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.
时序逻辑电路设计的Petri网方法%Design of Sequential Logic Circuit Based on Petri Net
Institute of Scientific and Technical Information of China (English)
张继军; 吴哲辉
2002-01-01
A new method for designing sequential logic circuits is put forward in this paper. The method is that driv-ing condition for flip-flops is obtained by means of the transition firing condition of petri net and that designing asyn-chronous sequential circuits and synchronous sequential circuits can be unified.
Asynchronous Learning Forums for Business Acculturation
Pence, Christine Cope; Wulf, Catharina
2009-01-01
The use of IT as a facilitator for student collaboration in higher business education has grown rapidly since 2000. Asynchronous discussion forums are used abundantly for collaborative training purposes and for teaching students business-relevant tools for their future careers. This article presents an analysis of the asynchronous discussion forum…
Asynchronous Parallelization of a CFD Solver
Directory of Open Access Journals (Sweden)
Daniel S. Abdi
2015-01-01
Full Text Available A Navier-Stokes equations solver is parallelized to run on a cluster of computers using the domain decomposition method. Two approaches of communication and computation are investigated, namely, synchronous and asynchronous methods. Asynchronous communication between subdomains is not commonly used in CFD codes; however, it has a potential to alleviate scaling bottlenecks incurred due to processors having to wait for each other at designated synchronization points. A common way to avoid this idle time is to overlap asynchronous communication with computation. For this to work, however, there must be something useful and independent a processor can do while waiting for messages to arrive. We investigate an alternative approach of computation, namely, conducting asynchronous iterations to improve local subdomain solution while communication is in progress. An in-house CFD code is parallelized using message passing interface (MPI, and scalability tests are conducted that suggest asynchronous iterations are a viable way of parallelizing CFD code.
VLSI digital demodulator co-processor
Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.
A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.
CMOS VLSI Active-Pixel Sensor for Tracking
Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie
2004-01-01
An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The
VLSI micro- and nanophotonics science, technology, and applications
Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati
2011-01-01
Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe
A radial basis function neurocomputer implemented with analog VLSI circuits
Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul
1992-01-01
An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.
NASA Space Engineering Research Center for VLSI systems design
1991-01-01
This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.
Handbook of VLSI chip design and expert systems
Schwarz, A F
1993-01-01
Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.
AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT
Directory of Open Access Journals (Sweden)
Y. Y. Lankevich
2015-01-01
Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.
Asynchronous Capacity per Unit Cost
Chandar, Venkat; Tse, David
2010-01-01
The capacity per unit cost, or equivalently minimum cost to transmit one bit, is a well-studied quantity. It has been studied under the assumption of full synchrony between the transmitter and the receiver. In many applications, such as sensor networks, transmissions are very bursty, with small amounts of bits arriving infrequently at random times. In such scenarios, the cost of acquiring synchronization is significant and one is interested in the fundamental limits on communication without assuming a priori synchronization. In this paper, we show that the minimum cost to transmit B bits of information asynchronously is (B + \\bar{H})k_sync, where k_sync is the synchronous minimum cost per bit and \\bar{H} is a measure of timing uncertainty equal to the entropy for most reasonable arrival time distributions.
Burst-Mode Asynchronous Controllers on FPGA
Directory of Open Access Journals (Sweden)
Duarte L. Oliveira
2008-01-01
Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.
CMOS VLSI Layout and Verification of a SIMD Computer
Zheng, Jianqing
1996-01-01
A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.
An efficient interpolation filter VLSI architecture for HEVC standard
Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang
2015-12-01
The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.
A special purpose silicon compiler for designing supercomputing VLSI systems
Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.
1991-01-01
Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
刘彦佩
2001-01-01
This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.
Artificial immune system algorithm in VLSI circuit configuration
Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd
2017-08-01
In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.
Hybrid VLSI/QCA Architecture for Computing FFTs
Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew
2003-01-01
A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.
Tungsten and other refractory metals for VLSI applications II
Energy Technology Data Exchange (ETDEWEB)
Broadbent, E.K.
1987-01-01
This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.
An Interactive Multimedia Learning Environment for VLSI Built with COSMOS
Angelides, Marios C.; Agius, Harry W.
2002-01-01
This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…
Asynchronous stochastic approximation with differential inclusions
Directory of Open Access Journals (Sweden)
David S. Leslie
2012-01-01
Full Text Available The asymptotic pseudo-trajectory approach to stochastic approximation of Benaïm, Hofbauer and Sorin is extended for asynchronous stochastic approximations with a set-valued mean field. The asynchronicity of the process is incorporated into the mean field to produce convergence results which remain similar to those of an equivalent synchronous process. In addition, this allows many of the restrictive assumptions previously associated with asynchronous stochastic approximation to be removed. The framework is extended for a coupled asynchronous stochastic approximation process with set-valued mean fields. Two-timescales arguments are used here in a similar manner to the original work in this area by Borkar. The applicability of this approach is demonstrated through learning in a Markov decision process.
Asynchronous networks and event driven dynamics
Bick, Christian; Field, Michael
2017-02-01
Real-world networks in technology, engineering and biology often exhibit dynamics that cannot be adequately reproduced using network models given by smooth dynamical systems and a fixed network topology. Asynchronous networks give a theoretical and conceptual framework for the study of network dynamics where nodes can evolve independently of one another, be constrained, stop, and later restart, and where the interaction between different components of the network may depend on time, state, and stochastic effects. This framework is sufficiently general to encompass a wide range of applications ranging from engineering to neuroscience. Typically, dynamics is piecewise smooth and there are relationships with Filippov systems. In this paper, we give examples of asynchronous networks, and describe the basic formalism and structure. In the following companion paper, we make the notion of a functional asynchronous network rigorous, discuss the phenomenon of dynamical locks, and present a foundational result on the spatiotemporal factorization of the dynamics for a large class of functional asynchronous networks.
Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.
Matsubara, Takashi; Torikai, Hiroyuki
2013-05-01
A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.
GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
Institute of Scientific and Technical Information of China (English)
Lu Junming; Lin Zhenghui
2002-01-01
In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.
GA—BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
Institute of Scientific and Technical Information of China (English)
LuJunming; LinZhenghui
2002-01-01
In this paper,the glitching activity and process variations in the maximum power dissipation estimation of CMOS circulits are introduced.Given a circuit and the gate library,a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view.The simulation on ISCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02.Compared with the traditional Monte Carlo-based technique,the new approach presented in this paper is more effective.
Advanced symbolic analysis for VLSI systems methods and applications
Shi, Guoyong; Tlelo Cuautle, Esteban
2014-01-01
This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Directory of Open Access Journals (Sweden)
Chávez-Bracamontes Ramón
2015-07-01
Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding
VLSI physical design analyzer: A profiling and data mining tool
Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi
2015-03-01
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Embedded Processor Based Automatic Temperature Control of VLSI Chips
Directory of Open Access Journals (Sweden)
Narasimha Murthy Yayavaram
2009-01-01
Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.
A novel 3D algorithm for VLSI floorplanning
Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira
2013-01-01
3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.
VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION
Directory of Open Access Journals (Sweden)
John Moses C
2014-05-01
Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.
VLSI design for fault-dictionary based testability
Miller, Charles D.
The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.
Opto-VLSI-based tunable single-mode fiber laser.
Xiao, Feng; Alameh, Kamal; Lee, Tongtak
2009-10-12
A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.
VLSI neural system architecture for finite ring recursive reduction.
Zhang, D; Jullien, G A
1996-12-01
The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.
Trace-based post-silicon validation for VLSI circuits
Liu, Xiao
2014-01-01
This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...
A systematic method for configuring VLSI networks of spiking neurons.
Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney
2011-10-01
An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.
Opto-VLSI-based N × M wavelength selective switch.
Xiao, Feng; Alameh, Kamal
2013-07-29
In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.
Digital VLSI algorithms and architectures for support vector machines.
Anguita, D; Boni, A; Ridella, S
2000-06-01
In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.
VLSI circuits for bidirectional interface to peripheral and visceral nerves.
Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V
2015-08-01
This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.
VLSI Design with Alliance Free CAD Tools: an Implementation Example
Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel
2015-01-01
This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
2011-01-01
Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...
Design of a VLSI Decoder for Partially Structured LDPC Codes
Directory of Open Access Journals (Sweden)
Fabrizio Vacca
2008-01-01
of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.
Diseño digital : una perspectiva VLSI-CMOS
Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel
1996-01-01
Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.
Discriminative methods for classification of asynchronous imaginary motor tasks from EEG data.
Delgado Saa, Jaime F; Çetin, Müjdat
2013-09-01
In this work, two methods based on statistical models that take into account the temporal changes in the electroencephalographic (EEG) signal are proposed for asynchronous brain-computer interfaces (BCI) based on imaginary motor tasks. Unlike the current approaches to asynchronous BCI systems that make use of windowed versions of the EEG data combined with static classifiers, the methods proposed here are based on discriminative models that allow sequential labeling of data. In particular, the two methods we propose for asynchronous BCI are based on conditional random fields (CRFs) and latent dynamic CRFs (LDCRFs), respectively. We describe how the asynchronous BCI problem can be posed as a classification problem based on CRFs or LDCRFs, by defining appropriate random variables and their relationships. CRF allows modeling the extrinsic dynamics of data, making it possible to model the transitions between classes, which in this context correspond to distinct tasks in an asynchronous BCI system. On the other hand, LDCRF goes beyond this approach by incorporating latent variables that permit modeling the intrinsic structure for each class and at the same time allows modeling extrinsic dynamics. We apply our proposed methods on the publicly available BCI competition III dataset V as well as a data set recorded in our laboratory. Results obtained are compared to the top algorithm in the BCI competition as well as to methods based on hierarchical hidden Markov models (HHMMs), hierarchical hidden CRF (HHCRF), neural networks based on particle swarm optimization (IPSONN) and to a recently proposed approach based on neural networks and fuzzy theory, the S-dFasArt. Our experimental analysis demonstrates the improvements provided by our proposed methods in terms of classification accuracy.
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM
Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn
2014-01-01
This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…
A neuromorphic VLSI device for implementing 2-D selective attention systems.
Indiveri, G
2001-01-01
Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.
Synchronization of Asynchronous Switched Boolean Network.
Zhang, Hao; Wang, Xingyuan; Lin, Xiaohui
2015-01-01
In this paper, the complete synchronizations for asynchronous switched Boolean network with free Boolean sequence controllers and close-loop controllers are studied. First, the basic asynchronous switched Boolean network model is provided. With the method of semi-tensor product, the Boolean dynamics is translated into linear representation. Second, necessary and sufficient conditions for ASBN synchronization with free Boolean sequence control and close-loop control are derived, respectively. Third, some illustrative examples are provided to show the efficiency of the proposed methods.
A simple asynchronous replica-exchange implementation
Bussi, Giovanni
2008-01-01
We discuss the possibility of implementing asynchronous replica-exchange (or parallel tempering) molecular dynamics. In our scheme, the exchange attempts are driven by asynchronous messages sent by one of the computing nodes, so that different replicas are allowed to perform a different number of time-steps between subsequent attempts. The implementation is simple and based on the message-passing interface (MPI). We illustrate the advantages of our scheme with respect to the standard synchronous algorithm and we benchmark it for a model Lennard-Jones liquid on an IBM-LS21 blade center cluster.
Handbook of asynchronous machines with variable speed
Razik, Hubert
2013-01-01
This handbook deals with the asynchronous machine in its close environment. It was born from a reflection on this electromagnetic converter whose integration in industrial environments takes a wide part. Previously this type of motor operated at fixed speed, from now on it has been integrated more and more in processes at variable speed. For this reason it seemed useful, or necessary, to write a handbook on the various aspects from the motor in itself, via the control and while finishing by the diagnosis aspect. Indeed, an asynchronous motor is used nowadays in industry where variation speed a
A Provably Secure Asynchronous Proactive RSA Scheme
Institute of Scientific and Technical Information of China (English)
ZHANG Rui-shan; LI Qiang; CHEN Ke-fei
2005-01-01
The drawback of the first asynchronous proactive RSA scheme presented by Zhou in 2001, is that the se curity definition and security proof do not follow the approach of provable security. This paper presented a provably secure asynchronous proactive RSA scheme, which includes three protocols: initial key distribution protocol,signature generation protocol and share refreshing protocol. Taken these protocols together, a complete provably secure proactive RSA scheme was obtained. And the efficiency of the scheme is approximate to that of the scheme of Zhou.
Processor arrays with asynchronous TDM optical buses
Li, Y.; Zheng, S. Q.
1997-04-01
We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardwared priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performances of our proposed buses are significantly better than the performances of known pipelined synchronous time division multiplexing optical buses. We also propose a class of processor arrays connected by pipelined asynchronous time division multiplexing optical buses. We claim that our proposed processor array not only have better performance, but also have better scalabilities than the existing processor arrays connected by pipelined synchronous time division multiplexing optical buses.
VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.
1983-10-01
34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being
Asynchronous asymmetric form of heterogeneous osteopetrosis: initial case expanded and a new case
Energy Technology Data Exchange (ETDEWEB)
Young, L.W. [Loma Linda University Medical Center and Children' s Hospital, CA (United States); Lachman, R.S. [International Skeletal Dysplasia Registry, Cedars-Sinai Medical Center, Los Angeles, CA (United States)
2001-01-01
We have discovered additional serial radiographs and clinical information on the initial case of ''regional osteopetrosis tarda'' that has been included in several editions of Caffey's Pediatric X-Ray Diagnosis. A definite second case was found after a search of radiology teaching files of other selected medical centers and the International Skeletal Dysplasia Registry. Analysis of the sequential unusual radiographic findings of the initial case and the equivalent compelling findings of the second case justifies renewed attention to an asynchronous asymmetric form of heterogeneous osteopetrosis. (orig.)
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
Russinoff, David M.
1995-01-01
We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.
Convergence of some asynchronous nonlinear multisplitting methods
Szyld, Daniel B.; Xu, Jian-Jun
2000-09-01
Frommer's nonlinear multisplitting methods for solving nonlinear systems of equations are extended to the asynchronous setting. Block methods are extended to include overlap as well. Several specific cases are discussed. Sufficient conditions to guarantee their local convergence are given. A numerical example is presented illustrating the performance of the new approach.
Asynchronous ASCII Event Count Status Code
2012-03-01
IRIG STANDARD 215-12 TELECOMMUNICATIONS AND TIMING GROUP ASYNCHRONOUS ASCII EVENT COUNT STATUS CODES...Inter-range Instrumentation Group ( IRIG ) Standard for American Standard Code for Information Interchange (ASCII)-formatted EC status transfer which can be...circuits and Ethernet networks. Provides systems engineers and equipment vendors with an Inter-range Instrumentation Group ( IRIG ) Standard for American
Increasing Student Engagement Using Asynchronous Learning
Northey, Gavin; Bucic, Tania; Chylinski, Mathew; Govind, Rahul
2015-01-01
Student engagement is an ongoing concern for educators because of its positive association with deep learning and educational outcomes. This article tests the use of a social networking site (Facebook) as a tool to facilitate asynchronous learning opportunities that complement face-to-face interactions and thereby enable a stronger learning…
Asynchronous Rumor Spreading on Random Graphs
Panagiotou, Konstantinos
2016-01-01
We perform a thorough study of various characteristics of the asynchronous push-pull protocol for spreading a rumor on Erd\\H{o}s-R\\'enyi random graphs $G_{n,p}$, for any $p>c\\ln(n)/n$ with $c>1$. In particular, we provide a simple strategy for analyzing the asynchronous push-pull protocol on arbitrary graph topologies and apply this strategy to $G_{n,p}$. We prove tight bounds of logarithmic order for the total time that is needed until the information has spread to all nodes. Surprisingly, the time required by the asynchronous push-pull protocol is asymptotically almost unaffected by the average degree of the graph. Similarly tight bounds for Erd\\H{o}s-R\\'enyi random graphs have previously only been obtained for the synchronous push protocol, where it has been observed that the total running time increases significantly for sparse random graphs. Finally, we quantify the robustness of the protocol with respect to transmission and node failures. Our analysis suggests that the asynchronous protocols are particu...
Maintaining High Assurance in Asynchronous Messaging
2015-10-24
be inconvenient and not consistent with normal dialog communication. II. PRIOR WORK A proliferation of standards for asynchronous messaging has...Software Technology Conference, “A Persona -Based Framework for Flexible Delegation and Least Privilege,” Las Vegas, Nevada, May 2008. [25] William
Increasing Student Engagement Using Asynchronous Learning
Northey, Gavin; Bucic, Tania; Chylinski, Mathew; Govind, Rahul
2015-01-01
Student engagement is an ongoing concern for educators because of its positive association with deep learning and educational outcomes. This article tests the use of a social networking site (Facebook) as a tool to facilitate asynchronous learning opportunities that complement face-to-face interactions and thereby enable a stronger learning…
FIFO Buffer for Asynchronous Data Streams
Bascle, K. P.
1985-01-01
Variable-rate, asynchronous data signals from up to four measuring instruments or other sources combined in first-in/first-out (FIFO) buffer for transmission on single channel. Constructed in complementary metal-oxide-semiconductor (CMOS) logic, buffer consumes low power (only 125 mW at 5V) and conforms to aerospace standards of reliability and maintainability.
Asynchronous stream processing with S-Net
Grelck, C.; Scholz, S.-B.; Shafarenko, A.
2010-01-01
We present the rationale and design of S-Net, a coordination language for asynchronous stream processing. The language achieves a near-complete separation between the application code, written in any conventional programming language, and the coordination/communication code written in S-Net. Our app
2005-07-01
a constant factor of K + 2. (To see this, note sequential stacking requires training K+2 classifiers: the classifiers f1, . . . , fK used in cross...on the non- sequential learners (ME and VP) but improves per- formance of the sequential learners (CRFs and VPH - MMs) less consistently. This pattern
Cooperative Sequential Spectrum Sensing Based on Level-triggered Sampling
Yilmaz, Yasin; Wang, Xiaodong
2011-01-01
We propose a new framework for cooperative spectrum sensing in cognitive radio networks, that is based on a novel class of non-uniform samplers, called the event-triggered samplers, and sequential detection. In the proposed scheme, each secondary user computes its local sensing decision statistic based on its own channel output; and whenever such decision statistic crosses certain predefined threshold values, the secondary user will send one (or several) bit of information to the fusion center. The fusion center asynchronously receives the bits from different secondary users and updates the global sensing decision statistic to perform a sequential probability ratio test (SPRT), to reach a sensing decision. We provide an asymptotic analysis for the above scheme, and under different conditions, we compare it against the cooperative sensing scheme that is based on traditional uniform sampling and sequential detection. Simulation results show that the proposed scheme, using even 1 bit, can outperform its uniform ...
Imaging with polycrystalline mercuric iodide detectors using VLSI readout
Energy Technology Data Exchange (ETDEWEB)
Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J
1999-06-01
Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.
VLSI implementations of threshold logic-a comprehensive survey.
Beiu, V; Quintana, J M; Avedillo, M J
2003-01-01
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.
Crystal growth and evaluation of silicon for VLSI and ULSI
Eranna, Golla
2014-01-01
PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri
A VLSI architecture for simplified arithmetic Fourier transform algorithm
Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.
1992-01-01
The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.
VLSI architectures for modern error-correcting codes
Zhang, Xinmiao
2015-01-01
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI
VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER
Directory of Open Access Journals (Sweden)
Joseph Gladwin Sekar
2013-01-01
Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.
Formal verification an essential toolkit for modern VLSI design
Seligman, Erik; Kumar, M V Achutha Kiran
2015-01-01
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific
Low-power Analog VLSI Implementation of Wavelet Transform
Institute of Scientific and Technical Information of China (English)
ZHANG Jiang-hong
2009-01-01
For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.
An adaptive, lossless data compression algorithm and VLSI implementations
Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu
1993-01-01
This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.
A VLSI Algorithm for Calculating the Treee to Tree Distance
Institute of Scientific and Technical Information of China (English)
徐美瑞; 刘小林
1993-01-01
Given two ordered,labeled trees βand α，to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.
Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.
Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David
2005-11-01
A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.
Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips
Institute of Scientific and Technical Information of China (English)
WANGJun
2004-01-01
Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.
Inhibition Controls Asynchronous States of Neuronal Networks
Treviño, Mario
2016-01-01
Computations in cortical circuits require action potentials from excitatory and inhibitory neurons. In this mini-review, I first provide a quick overview of findings that indicate that GABAergic neurons play a fundamental role in coordinating spikes and generating synchronized network activity. Next, I argue that these observations helped popularize the notion that network oscillations require a high degree of spike correlations among interneurons which, in turn, produce synchronous inhibition of the local microcircuit. The aim of this text is to discuss some recent experimental and computational findings that support a complementary view: one in which interneurons participate actively in producing asynchronous states in cortical networks. This requires a proper mixture of shared excitation and inhibition leading to asynchronous activity between neighboring cells. Such contribution from interneurons would be extremely important because it would tend to reduce the spike correlation between neighboring pyramidal cells, a drop in redundancy that could enhance the information-processing capacity of neural networks. PMID:27274721
Computing by Temporal Order: Asynchronous Cellular Automata
Directory of Open Access Journals (Sweden)
Michael Vielhaber
2012-08-01
Full Text Available Our concern is the behaviour of the elementary cellular automata with state set 0,1 over the cell set Z/nZ (one-dimensional finite wrap-around case, under all possible update rules (asynchronicity. Over the torus Z/nZ (n<= 11,we will see that the ECA with Wolfram rule 57 maps any v in F_2^n to any w in F_2^n, varying the update rule. We furthermore show that all even (element of the alternating group bijective functions on the set F_2^n = 0,...,2^n-1, can be computed by ECA57, by iterating it a sufficient number of times with varying update rules, at least for n <= 10. We characterize the non-bijective functions computable by asynchronous rules.
Low Latency High Throughout Circular Asynchronous FIFO
Institute of Scientific and Technical Information of China (English)
XIAO Yong; ZHOU Runde
2008-01-01
This paper describes a circular first in first out (FIFO) and its protocols which have a very low la-tency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micro-pipelines, this FIFO's cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 Ijm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.
Inhibition Controls Asynchronous States of Neuronal Networks.
Treviño, Mario
2016-01-01
Computations in cortical circuits require action potentials from excitatory and inhibitory neurons. In this mini-review, I first provide a quick overview of findings that indicate that GABAergic neurons play a fundamental role in coordinating spikes and generating synchronized network activity. Next, I argue that these observations helped popularize the notion that network oscillations require a high degree of spike correlations among interneurons which, in turn, produce synchronous inhibition of the local microcircuit. The aim of this text is to discuss some recent experimental and computational findings that support a complementary view: one in which interneurons participate actively in producing asynchronous states in cortical networks. This requires a proper mixture of shared excitation and inhibition leading to asynchronous activity between neighboring cells. Such contribution from interneurons would be extremely important because it would tend to reduce the spike correlation between neighboring pyramidal cells, a drop in redundancy that could enhance the information-processing capacity of neural networks.
Testing interconnected VLSI circuits in the Big Viterbi Decoder
Onyszchuk, I. M.
1991-01-01
The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.
New VLSI complexity results for threshold gate comparison
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1996-12-31
The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.
A VLSI design concept for parallel iterative algorithms
Directory of Open Access Journals (Sweden)
C. C. Sun
2009-05-01
Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.
A fast neural-network algorithm for VLSI cell placement.
Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail
1998-12-01
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
Fast Asynchronous Data Communication Via Fiber Optics
Bergman, Larry A.; Tell, Robert G.
1989-01-01
Transmitter and receiver devised for asynchronous digital communication via optical fiber at rates above 100 Mb/s. Transmitter converts parallel data to serial for high-speed transmission; receiver recovers clock signal and converts data back to parallel. No phase-lock loops used. New receiver design avoids over-sampling altogether. Local sampling oscillator operating nominally at clock frequency generates N clock signals of equally spaced phase, used to clock incoming data into N separate shift registers.
Asynchronous exponential growth of a bacterial population
Directory of Open Access Journals (Sweden)
Mohamed Boulanouar
2014-01-01
Full Text Available In this work, we complete a study started earlier in [1,2] wherein a model of growing bacterial population has been the matter of a mathematical analysis. We show that the full model is governed by a strongly continuous semigroup. Beside the positivity and the irreducibility of the generated semigroup, we describe its asymptotic behavior in the uniform topology which leads to the asynchronous exponential growth of the bacterial population.
Asynchronous event-based binocular stereo matching.
Rogister, Paul; Benosman, Ryad; Ieng, Sio-Hoi; Lichtsteiner, Patrick; Delbruck, Tobi
2012-02-01
We present a novel event-based stereo matching algorithm that exploits the asynchronous visual events from a pair of silicon retinas. Unlike conventional frame-based cameras, recent artificial retinas transmit their outputs as a continuous stream of asynchronous temporal events, in a manner similar to the output cells of the biological retina. Our algorithm uses the timing information carried by this representation in addressing the stereo-matching problem on moving objects. Using the high temporal resolution of the acquired data stream for the dynamic vision sensor, we show that matching on the timing of the visual events provides a new solution to the real-time computation of 3-D objects when combined with geometric constraints using the distance to the epipolar lines. The proposed algorithm is able to filter out incorrect matches and to accurately reconstruct the depth of moving objects despite the low spatial resolution of the sensor. This brief sets up the principles for further event-based vision processing and demonstrates the importance of dynamic information and spike timing in processing asynchronous streams of visual events.
Blending Online Asynchronous and Synchronous Learning
Directory of Open Access Journals (Sweden)
Lisa C. Yamagata-Lynch
2014-04-01
Full Text Available In this article I will share a qualitative self-study about a 15-week blended 100% online graduate level course facilitated through synchronous meetings on Blackboard Collaborate and asynchronous discussions on Blackboard. I taught the course at the University of Tennessee (UT during the spring 2012 semester and the course topic was online learning environments. The primary research question of this study was: How can the designer/instructor optimize learning experiences for students who are studying about online learning environments in a blended online course relying on both synchronous and asynchronous technologies? I relied on student reflections of course activities during the beginning, middle, and the end of the semester as the primary data source to obtain their insights regarding course experiences. Through the experiences involved in designing and teaching the course and engaging in this study I found that there is room in the instructional technology research community to address strategies for facilitating online synchronous learning that complement asynchronous learning. Synchronous online whole class meetings and well-structured small group meetings can help students feel a stronger sense of connection to their peers and instructor and stay engaged with course activities. In order to provide meaningful learning spaces in synchronous learning environments, the instructor/designer needs to balance the tension between embracing the flexibility that the online space affords to users and designing deliberate structures that will help them take advantage of the flexible space.
FPGA Architecture for Multi-Style Asynchronous Logic
Huot, N; Fesquet, L; Renaudin, M
2011-01-01
This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.
Mathematical Model of Asynchronous Motor with Embedded Combined Braking Device
Directory of Open Access Journals (Sweden)
V. Solencov
2013-01-01
Full Text Available The paper presents a conclusion of a mathematical model pertaining to asynchronous motor with embedded combined braking device on the basis of electromechanical brake and electromagnetic slip coupling. The mathematical model has been obtained in an orthogonal coordinate system a, b, which is fixed with respect to the asymmetric part of the asynchronous motor with embedded combined braking device. The model makes it possible to investigate transient processes in various asynchronous motors with embedded braking devices.
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Directory of Open Access Journals (Sweden)
Cavallaro Joseph R
2006-01-01
Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.
Opto-VLSI-based reconfigurable free-space optical interconnects architecture
DEFF Research Database (Denmark)
Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;
2007-01-01
is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....
Real-time simulation of biologically realistic stochastic neurons in VLSI.
Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie
2010-09-01
Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.
Pop, Paul; Madsen, Jan
2016-01-01
This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...
Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo; Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits
Institute of Scientific and Technical Information of China (English)
Yasuo Kokubun
2003-01-01
In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.
Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems
2015-01-01
This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...
EPOS for Coordination of Asynchronous Sensor Webs Project
National Aeronautics and Space Administration — Develop, integrate, and deploy software-based tools to coordinate asynchronous, distributed missions and optimize observation planning spanning simultaneous...
Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.
Mustafa, Haithem; Xiao, Feng; Alameh, Kamal
2011-10-24
A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.
CMOS VLSI Hyperbolic Tangent Function & its Derivative Circuits for Neuron Implementation
Directory of Open Access Journals (Sweden)
Hussein CHIBLE,
2013-10-01
Full Text Available The hyperbolic tangent function and its derivative are key essential element in analog signal processing and especially in analog VLSI implementation of neuron of artificial neural networks. The main conditions of these types of circuits are the small silicon area, and the low power consumption. The objective of this paper is to study and design CMOS VLSI hyperbolic tangent function and its derivative circuit for neural network implementation. A circuit is designed and the results are presented
POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS
Directory of Open Access Journals (Sweden)
D. I. Cheremisinov
2013-01-01
Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.
Cascaded VLSI neural network architecture for on-line learning
Duong, Tuan A. (Inventor); Daud, Taher (Inventor); Thakoor, Anilkumar P. (Inventor)
1995-01-01
High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.
Sequentializing Parameterized Programs
Directory of Open Access Journals (Sweden)
Salvatore La Torre
2012-07-01
Full Text Available We exhibit assertion-preserving (reachability preserving transformations from parameterized concurrent shared-memory programs, under a k-round scheduling of processes, to sequential programs. The salient feature of the sequential program is that it tracks the local variables of only one thread at any point, and uses only O(k copies of shared variables (it does not use extra counters, not even one counter to keep track of the number of threads. Sequentialization is achieved using the concept of a linear interface that captures the effect an unbounded block of processes have on the shared state in a k-round schedule. Our transformation utilizes linear interfaces to sequentialize the program, and to ensure the sequential program explores only reachable states and preserves local invariants.
VLSI technology for smaller, cheaper, faster return link systems
Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John
1994-01-01
Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.
Cascaded VLSI Chips Help Neural Network To Learn
Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.
1993-01-01
Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.
Efficient VLSI architecture for training radial basis function networks.
Fan, Zhe-Cheng; Hwang, Wen-Jyi
2013-03-19
This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.
Abdelhalim, K; Smolyakov, V; Genov, R
2011-10-01
A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.
Event-driven neural integration and synchronicity in analog VLSI.
Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert
2012-01-01
Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.
Modeling selective attention using a neuromorphic analog VLSI device.
Indiveri, G
2000-12-01
Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.
Analog VLSI implementation of resonate-and-fire neuron.
Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo
2006-12-01
We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.
VLSI-based Video Event Triggering for Image Data Compression
Williams, Glenn L.
1994-01-01
Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
1992-01-01
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
VLSI design techniques for floating-point computation
Energy Technology Data Exchange (ETDEWEB)
Bose, B. K.
1988-01-01
The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.
Efficient VLSI Architecture for Training Radial Basis Function Networks
Directory of Open Access Journals (Sweden)
Wen-Jyi Hwang
2013-03-01
Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.
Carbon nanotube based VLSI interconnects analysis and design
Kaushik, Brajesh Kumar
2015-01-01
The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.
Realistic model of compact VLSI FitzHugh-Nagumo oscillators
Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel
2014-02-01
In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.
Power Efficient Sub-Array in Reconfigurable VLSI Meshes
Institute of Scientific and Technical Information of China (English)
Ji-Gang Wu; Thambipillai Srikanthan
2005-01-01
Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.
Replacing design rules in the VLSI design cycle
Hurley, Paul; Kryszczuk, Krzysztof
2012-03-01
We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.
Parallel optical interconnects utilizing VLSI/FLC spatial light modulators
Genco, Sheryl M.
1991-12-01
Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.
A VLSI implementation of DCT using pass transistor technology
Kamath, S.; Lynn, Douglas; Whitaker, Sterling
A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.
Parallel Distribution of Asynchronous Optical Signals
White, R J; Bradbury, S M; Marshall, P
2007-01-01
An eleven channel digital asynchronous transceiver (DAT) employing parallel optical link technology has been developed for trigger signal distribution across the Very Energetic Radiation Imaging Telescope Array System (VERITAS). Combinatorial logic functions are implemented in Xilinx Spartan 3 FPGAs, providing a versatile solution adaptable for use in future atmospheric Cerenkov detectors and other high-energy astroparticle experiments. The device is dead-time free and introduces a minimal skew of 1.6 ns between channels. The jitter on each DAT channel is less than 0.8 ns 95% of the time, allowing communication between telescopes and a central trigger system separated by hundreds of meters, without limiting array performance.
Globally coupled maps with asynchronous updating
Abramson, G; Abramson, Guillermo; Zanette, Damian H.
1998-01-01
We analyze a system of globally coupled logistic maps with asynchronous updating. We show that its dynamics differs considerably from that of the synchronous case. For growing values of the coupling intensity, an inverse bifurcation cascade replaces the structure of clusters and ordering in the phase diagram. We present numerical simulations and an analytical description based on an effective single-element dynamics affected by internal fluctuations. Both of them show how global coupling is able to suppress the complexity of the single-element evolution. We find that, in contrast to systems with synchronous update, internal fluctuations satisfy the law of large numbers.
Asynchronous Event-Driven Particle Algorithms
Energy Technology Data Exchange (ETDEWEB)
Donev, A
2007-02-28
We present in a unifying way the main components of three examples of asynchronous event-driven algorithms for simulating physical systems of interacting particles. The first example, hard-particle molecular dynamics (MD), is well-known. We also present a recently-developed diffusion kinetic Monte Carlo (DKMC) algorithm, as well as a novel event-driven algorithm for Direct Simulation Monte Carlo (DSMC). Finally, we describe how to combine MD with DSMC in an event-driven framework, and discuss some promises and challenges for event-driven simulation of realistic physical systems.
Asynchronous Event-Driven Particle Algorithms
Energy Technology Data Exchange (ETDEWEB)
Donev, A
2007-08-30
We present, in a unifying way, the main components of three asynchronous event-driven algorithms for simulating physical systems of interacting particles. The first example, hard-particle molecular dynamics (MD), is well-known. We also present a recently-developed diffusion kinetic Monte Carlo (DKMC) algorithm, as well as a novel stochastic molecular-dynamics algorithm that builds on the Direct Simulation Monte Carlo (DSMC). We explain how to effectively combine event-driven and classical time-driven handling, and discuss some promises and challenges for event-driven simulation of realistic physical systems.
Two Studies Examining Argumentation in Asynchronous Computer Mediated Communication
Joiner, Richard; Jones, Sarah; Doherty, John
2008-01-01
Asynchronous computer mediated communication (CMC) would seem to be an ideal medium for supporting development in student argumentation. This paper investigates this assumption through two studies. The first study compared asynchronous CMC with face-to-face discussions. The transactional and strategic level of the argumentation (i.e. measures of…
Designing Asynchronous Circuits for Low Power: An IFIR Filter
DEFF Research Database (Denmark)
Nielsen, Lars Skovby; Sparsø, Jens
1999-01-01
by numerically small samples). Apart from the improved RAM design, these measures are only viable in an asynchronous design. The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous low-power digital signal-processing circuits in a broader...
ASYNCHRONOUS BYZANTINE AGREEMENT PROTOCOL BASED ON VERIFIABLE SIGNATURE SHARING
Institute of Scientific and Technical Information of China (English)
Ji Dongyao; Feng Dengguo
2006-01-01
An ([n / 3]- 1 )-resilient Asynchronous Byzantine Agreement Protocol (ABAP) that combines verifiable signature sharing and random secret sharing is proposed. The protocol works in the asynchronous network environment and produces Byzantine agreement within a fixed expected number of computational rounds. The correctness of the protocol is proved in theory.
Asynchronous Learning Sources in a High-Tech Organization
Bouhnik, Dan; Giat, Yahel; Sanderovitch, Yafit
2009-01-01
Purpose: The purpose of this study is to characterize learning from asynchronous sources among research and development (R&D) personnel. It aims to examine four aspects of asynchronous source learning: employee preferences regarding self-learning; extent of source usage; employee satisfaction with these sources and the effect of the sources on the…
Localized radio frequency communication using asynchronous transfer mode protocol
Witzke, Edward L.; Robertson, Perry J.; Pierson, Lyndon G.
2007-08-14
A localized wireless communication system for communication between a plurality of circuit boards, and between electronic components on the circuit boards. Transceivers are located on each circuit board and electronic component. The transceivers communicate with one another over spread spectrum radio frequencies. An asynchronous transfer mode protocol controls communication flow with asynchronous transfer mode switches located on the circuit boards.
Institute of Scientific and Technical Information of China (English)
王晖; 刘大有; 等
1994-01-01
In this paper we consider the problem of sequential processing and present a sequential model based on the back-propagation algorithm.This model is intended to deal with intrinsically sequential problems,such as word recognition,speech recognition,natural language understanding.This model can be used to train a network to learn the sequence of input patterns,in a fixed order or a random order.Besides,this model is open- and partial-associative,characterized as “resognizing while accumulating”, which, as we argue, is mental cognition process oriented.
Asynchronous vascular consultation via electronic methods: A feasibility pilot.
Chittle, Melissa D; Rao, Sandhya K; Jaff, Michael R; Patel, Virendra I; Gallen, Kathleen M; Avadhani, Radhika; Ferris, Timothy G; Wasfy, Jason H
2015-12-01
Management of chronic disease often requires multidisciplinary clinical efforts and specialist care. With the emergence of Accountable Care Organizations (ACOs), health care systems are incentivized to evaluate methods of information exchange between generalists and specialists in order to provide value while preserving quality. Our objective was to evaluate patient and referring provider satisfaction and outcomes of asynchronous electronic consultations in vascular care in a large tertiary academic medical center. Referring providers were offered a vascular 'e-consult' option through an electronic referral management system. We conducted chart review to understand the downstream effects and surveyed patients and referring providers to assess satisfaction. From 24 March 2014 to 1 March 2015, 54 e-consults were completed. Additional testing and recommendations were made in 49/54 (90.7%) e-consults, including lower-extremity venous duplex ultrasonography with reflux testing, duplex ultrasonography of the carotid artery, computed tomography, magnetic resonance imaging, non-invasive physiology arterial studies, laboratory tests, medications, compression stockings, and sequential lymphedema compression therapy. Referring providers were compliant with recommendations in 40/49 (81.6%) of e-consults. A total of 17/54 (31.5%) patients were surveyed with a median patient satisfaction score of 13.7/15 (91.3%) (SD ± 6.4). The program was associated with high referring provider satisfaction, with 87.0% finding the e-consult very helpful and 80.0% stating it averted the need for a traditional visit. Our experience suggests that e-consults are an effective way to provide vascular care in some patients and are associated with high patient and provider satisfaction. E-consults may therefore be an efficient method of care delivery for vascular patients within an ACO.
Resynchronization of the Asynchronous Polar CD Ind
Myers, Gordon; Patterson, Joseph; de Miguel, Enrique; Hambsch, Franz-Josef; Monard, Berto; Bolt, Greg; McCormick, Jennie; Rea, Robert; Allen, William
2017-04-01
CD Ind is one of only four confirmed asynchronous polars (APs). APs are strongly magnetic cataclysmic variables of the AM Herculis subclass with the characteristic that their white dwarfs rotate a few percent out of synchronism with their binary orbit. Theory suggests that nova eruptions disrupt previously synchronized states. Following the eruption, the system is expected to rapidly resynchronize over a timescale of centuries. The other three asynchronous polars—V1432 Aql, BY Cam, and V1500 Cyg—have resynchronization time estimates ranging from 100 to more than 3500 years, with all but one being less than 1200 years. We report on the analysis of over 46,000 observations of CD Ind taken between 2007 and 2016, combined with previous observations from 1996, and estimate a CD Ind resynchronization time of 6400 ± 800 years. We also estimate an orbital period of 110.820(1) minutes and a current (2016.4) white dwarf spin period of 109.6564(1) minutes.
Controllability of asynchronous Boolean multiplex control networks.
Luo, Chao; Wang, Xingyuan; Liu, Hong
2014-09-01
In this article, the controllability of asynchronous Boolean multiplex control networks (ABMCNs) is studied. First, the model of Boolean multiplex control networks under Harvey' asynchronous update is presented. By means of semi-tensor product approach, the logical dynamics is converted into linear representation, and a generalized formula of control-depending network transition matrices is achieved. Second, a necessary and sufficient condition is proposed to verify that only control-depending fixed points of ABMCNs can be controlled with probability one. Third, using two types of controls, the controllability of system is studied and formulae are given to show: (a) when an initial state is given, the reachable set at time s under a group of specified controls; (b) the reachable set at time s under arbitrary controls; (c) the specific probability values from a given initial state to destination states. Based on the above formulae, an algorithm to calculate overall reachable states from a specified initial state is presented. Moreover, we also discuss an approach to find the particular control sequence which steers the system between two states with maximum probability. Examples are shown to illustrate the feasibility of the proposed scheme.
Selective particle capture by asynchronously beating cilia
Ding, Yang; Kanso, Eva
2015-12-01
Selective particle filtration is fundamental in many engineering and biological systems. For example, many aquatic microorganisms use filter feeding to capture food particles from the surrounding fluid, using motile cilia. One of the capture strategies is to use the same cilia to generate feeding currents and to intercept particles when the particles are on the downstream side of the cilia. Here, we develop a 3D computational model of ciliary bands interacting with flow suspended particles and calculate particle trajectories for a range of particle sizes. Consistent with experimental observations, we find optimal particle sizes that maximize capture rate. The optimal size depends nonlinearly on cilia spacing and cilia coordination, synchronous vs. asynchronous. These parameters affect the cilia-generated flow field, which in turn affects particle trajectories. The low capture rate of smaller particles is due to the particles' inability to cross the flow streamlines of neighboring cilia. Meanwhile, large particles have difficulty entering the sub-ciliary region once advected downstream, also resulting in low capture rates. The optimal range of particle sizes is enhanced when cilia beat asynchronously. These findings have potentially important implications on the design and use of biomimetic cilia in processes such as particle sorting in microfluidic devices.
Asynchronicity of facial blood perfusion in migraine.
Directory of Open Access Journals (Sweden)
Nina Zaproudina
Full Text Available Asymmetrical changes in blood perfusion and asynchronous blood supply to head tissues likely contribute to migraine pathophysiology. Imaging was widely used in order to understand hemodynamic variations in migraine. However, mapping of blood pulsations in the face of migraineurs has not been performed so far. We used the Blood Pulsation Imaging (BPI technique, which was recently developed in our group, to establish whether 2D-imaging of blood pulsations parameters can reveal new biomarkers of migraine. BPI characteristics were measured in migraineurs during the attack-free interval and compared to healthy subjects with and without a family history of migraine. We found a novel phenomenon of transverse waves of facial blood perfusion in migraineurs in contrast to healthy subjects who showed synchronous blood delivery to both sides of the face. Moreover, the amplitude of blood pulsations was symmetrically distributed over the face of healthy subjects, but asymmetrically in migraineurs and subjects with a family history of migraine. In the migraine patients we found a remarkable correlation between the side of unilateral headache and the direction of the blood perfusion wave. Our data suggest that migraine is associated with lateralization of blood perfusion and asynchronous blood pulsations in the facial area, which could be due to essential dysfunction of the autonomic vascular control in the face. These findings may further enhance our understanding of migraine pathophysiology and suggest new easily available biomarkers of this pathology.
Asynchronicity of facial blood perfusion in migraine.
Zaproudina, Nina; Teplov, Victor; Nippolainen, Ervin; Lipponen, Jukka A; Kamshilin, Alexei A; Närhi, Matti; Karjalainen, Pasi A; Giniatullin, Rashid
2013-01-01
Asymmetrical changes in blood perfusion and asynchronous blood supply to head tissues likely contribute to migraine pathophysiology. Imaging was widely used in order to understand hemodynamic variations in migraine. However, mapping of blood pulsations in the face of migraineurs has not been performed so far. We used the Blood Pulsation Imaging (BPI) technique, which was recently developed in our group, to establish whether 2D-imaging of blood pulsations parameters can reveal new biomarkers of migraine. BPI characteristics were measured in migraineurs during the attack-free interval and compared to healthy subjects with and without a family history of migraine. We found a novel phenomenon of transverse waves of facial blood perfusion in migraineurs in contrast to healthy subjects who showed synchronous blood delivery to both sides of the face. Moreover, the amplitude of blood pulsations was symmetrically distributed over the face of healthy subjects, but asymmetrically in migraineurs and subjects with a family history of migraine. In the migraine patients we found a remarkable correlation between the side of unilateral headache and the direction of the blood perfusion wave. Our data suggest that migraine is associated with lateralization of blood perfusion and asynchronous blood pulsations in the facial area, which could be due to essential dysfunction of the autonomic vascular control in the face. These findings may further enhance our understanding of migraine pathophysiology and suggest new easily available biomarkers of this pathology.
Controllability of asynchronous Boolean multiplex control networks
Luo, Chao; Wang, Xingyuan; Liu, Hong
2014-09-01
In this article, the controllability of asynchronous Boolean multiplex control networks (ABMCNs) is studied. First, the model of Boolean multiplex control networks under Harvey' asynchronous update is presented. By means of semi-tensor product approach, the logical dynamics is converted into linear representation, and a generalized formula of control-depending network transition matrices is achieved. Second, a necessary and sufficient condition is proposed to verify that only control-depending fixed points of ABMCNs can be controlled with probability one. Third, using two types of controls, the controllability of system is studied and formulae are given to show: (a) when an initial state is given, the reachable set at time s under a group of specified controls; (b) the reachable set at time s under arbitrary controls; (c) the specific probability values from a given initial state to destination states. Based on the above formulae, an algorithm to calculate overall reachable states from a specified initial state is presented. Moreover, we also discuss an approach to find the particular control sequence which steers the system between two states with maximum probability. Examples are shown to illustrate the feasibility of the proposed scheme.
THE RESEARCH OF GRADATION FUSION ALGORITHM BASED ON MULTISENSOR ASYNCHRONOUS SAMPLING SYSTEM
Institute of Scientific and Technical Information of China (English)
无
2005-01-01
This letter explores the distributed multisensor dynamic system, which has uniform sampling velocity and asynchronous sampling data for different sensors, and puts forward a new gradation fusion algorithm of multisensor dynamic system. As the total forecasted increment value between the two adjacent moments is the forecasted estimate value of the corresponding state increment in the fusion center, the new algorithm models the state and the forecasted estimate value of every moment. Kalman filter and all measurements arriving sequentially in the fusion period are employed to update the evaluation of target state step by step, on the condition that the system has obtained the target state evaluation that is based on the overall information in the previous fusion period. Accordingly, in the present period, the fusion evaluation of the target state at each sampling point on the basis of the overall information can be obtained. This letter elaborates the form of this new algorithm. Computer simulation demonstrates that this new algorithm owns greater precision in estimating target state than the present asynchronous fusion algorithm calibrated in time does.
Boolean approaches to graph embeddings related to VLSI
Institute of Scientific and Technical Information of China (English)
LIU; Yanpei(
2001-01-01
［1］Hu, T. C., Kuh, S. E., Theory and concepts of circuit layout, in VLSI Circuit Layout: Theory and Design, New York:IEEE Press, 1985, 3-18.［2］Liu Yanpei, Embeddability in Graphs, Boston-Beijing: Kluwer Science, 1995.［3］Liu Yanpei, Some combinatorial optimization problems arising from VLSI circuit design, Applied Math. -JCU, 1993, 38:218-235.［4］Liu Yanpei, Marchioro, P. , Petreschi, R., At most single bend embeddings of cubic graphs, Applied Math. -CJU, 1994,39: 127-142.［5］Liu Yanpei, Marchioro, P. , Petreschi, R. et al. , Theoretical results on at most 1-bend embeddability of graphs, Acta Math.Appl. Sinica, 1992, 8: 188-192.［6］Liu Yanpei, Morgana, A., Simeone, B., General theoretical results on rectilinear embeddability of graphs, Acta Math. Ap- pl. Simca, 1991, 7: 187-192.［7］Calamoneri, T., Petreschi, R., Liu Yanpei, Optimally Extending Bistandard Graphs on the Orthogonal Grid, ASCM2000 Symposium, Tailand, Dec.17-21, 2000.［8］Liu Yanpei, Morgana, A., Simeone, B., A graph partition problem, Acta Math. Appl. Sinica, 1996, 12: 393-400.［9］Liu Yanpei, Morgana, A. , Simeone, B. , A linear algorithm for 2-bend embeddings of planar graphs in the two dimensional grid, Discrete Appl. Math., 1998, 81: 69-91.［10］Liu Yanpei, Boolean approach to planar embeddings of a graph, Acta Math. Sinica, New Series, 1989, 5: 64-79.［11］Hammer, P. L., Liu Yanpei, Simeone, B., Boolean approaches to combinatorial optimization, J. Math. Res. Expos.,1990, 10: 300-312, 455-468, 619-628.［12］Liu Yanpei, Boolean planarity characterization of graphs, Acta Math. Sinica, New Series, 1988, 4: 316-329.［13］Liu Yanpei, Boolean characterizations of planarity and planar embeddings of graphs, Ann. O. R., 1990, 24: 165-174.
A Block-Asynchronous Relaxation Method for Graphics Processing Units
Energy Technology Data Exchange (ETDEWEB)
Antz, Hartwig [Karlsruhe Inst. of Technology (KIT) (Germany); Tomov, Stanimire [Univ. of Tennessee, Knoxville, TN (United States); Dongarra, Jack [Univ. of Tennessee, Knoxville, TN (United States); Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Univ. of Manchester (United Kingdom); Heuveline, Vincent [Karlsruhe Inst. of Technology (KIT) (Germany)
2011-11-30
In this paper, we analyze the potential of asynchronous relaxation methods on Graphics Processing Units (GPUs). For this purpose, we developed a set of asynchronous iteration algorithms in CUDA and compared them with a parallel implementation of synchronous relaxation methods on CPU-based systems. For a set of test matrices taken from the University of Florida Matrix Collection we monitor the convergence behavior, the average iteration time and the total time-to-solution time. Analyzing the results, we observe that even for our most basic asynchronous relaxation scheme, despite its lower convergence rate compared to the Gauss-Seidel relaxation (that we expected), the asynchronous iteration running on GPUs is still able to provide solution approximations of certain accuracy in considerably shorter time then Gauss- Seidel running on CPUs. Hence, it overcompensates for the slower convergence by exploiting the scalability and the good fit of the asynchronous schemes for the highly parallel GPU architectures. Further, enhancing the most basic asynchronous approach with hybrid schemes – using multiple iterations within the ”subdomain” handled by a GPU thread block and Jacobi-like asynchronous updates across the ”boundaries”, subject to tuning various parameters – we manage to not only recover the loss of global convergence but often accelerate convergence of up to two times (compared to the effective but difficult to parallelize Gauss-Seidel type of schemes), while keeping the execution time of a global iteration practically the same. This shows the high potential of the asynchronous methods not only as a stand alone numerical solver for linear systems of equations fulfilling certain convergence conditions but more importantly as a smoother in multigrid methods. Due to the explosion of parallelism in todays architecture designs, the significance and the need for asynchronous methods, as the ones described in this work, is expected to grow.
Asynchronous parallel pattern search for nonlinear optimization
Energy Technology Data Exchange (ETDEWEB)
P. D. Hough; T. G. Kolda; V. J. Torczon
2000-01-01
Parallel pattern search (PPS) can be quite useful for engineering optimization problems characterized by a small number of variables (say 10--50) and by expensive objective function evaluations such as complex simulations that take from minutes to hours to run. However, PPS, which was originally designed for execution on homogeneous and tightly-coupled parallel machine, is not well suited to the more heterogeneous, loosely-coupled, and even fault-prone parallel systems available today. Specifically, PPS is hindered by synchronization penalties and cannot recover in the event of a failure. The authors introduce a new asynchronous and fault tolerant parallel pattern search (AAPS) method and demonstrate its effectiveness on both simple test problems as well as some engineering optimization problems
Commande adaptive d'une machine asynchrone
I. Slama-Belkhodja; De Fornel, B.
1996-01-01
Cat article décrit une stratégie de commande adaptive indirecte à Placement de Pôles (PP), appliquée à la commande en vitesse d'une machine asynchrone alimentée par un ensemble hacheur-filtre-onduleur de tension. L'algorithme des Moindres Carrés Récursifs (MCR) est utilisé pour l'identification des modèles de comportement type entrées/sorties. Un intérêt particulier est porté à la mise en oeuvre de cet algorithme et à la discussion de ses résultats, tenant compte des erreurs de modélisation e...
Asynchronous discrete event schemes for PDEs
Stone, D.; Geiger, S.; Lord, G. J.
2017-08-01
A new class of asynchronous discrete-event simulation schemes for advection-diffusion-reaction equations is introduced, based on the principle of allowing quanta of mass to pass through faces of a (regular, structured) Cartesian finite volume grid. The timescales of these events are linked to the flux on the face. The resulting schemes are self-adaptive, and local in both time and space. Experiments are performed on realistic physical systems related to porous media flow applications, including a large 3D advection diffusion equation and advection diffusion reaction systems. The results are compared to highly accurate reference solutions where the temporal evolution is computed with exponential integrator schemes using the same finite volume discretisation. This allows a reliable estimation of the solution error. Our results indicate a first order convergence of the error as a control parameter is decreased, and we outline a framework for analysis.
Implementation of Universal Asynchronous Receiver and Transmitter
Directory of Open Access Journals (Sweden)
Payata Srikanth Yadav
2015-03-01
Full Text Available Universal Asynchronous Receiver Transmitter (UART is the serial communication protocol that is used for data exchange between computer & peripherals. UART is a low velocity, short-distance, low-cost protocol. UART includes three modules which are received, the baud rate generator and transmitter. The UART design with Very High Description Language can be integrated into the Field Programmable Gate Array to achieve stable data transmission and to make system reliable and compact. In the result and simulation part, this project will focus on check the receive data with error free & baud rate generation at different frequencies. Before synthesizing of UART a baud rate generator is incorporated into the system. We use the frequency divider which sets itself to required frequency for the functionality at lower frequency. All modules are designed using VERILOG and implemented on Xilinx Suite development board.
Asynchronous Parallel Evolutionary Algorithms for Constrained Optimizations
Institute of Scientific and Technical Information of China (English)
无
2000-01-01
Recently Guo Tao proposed a stochastic search algorithm in his PhD thesis for solving function op-timization problems. He combined the subspace search method (a general multi-parent recombination strategy) with the population hill-climbing method. The former keeps a global search for overall situation,and the latter keeps the convergence of the algorithm. Guo's algorithm has many advantages ,such as the sim-plicity of its structure ,the higher accuracy of its results, the wide range of its applications ,and the robustness of its use. In this paper a preliminary theoretical analysis of the algorithm is given and some numerical experiments has been done by using Guo's algorithm for demonstrating the theoretical results. Three asynchronous paral-lel evolutionary algorithms with different granularities for MIMD machines are designed by parallelizing Guo's Algorithm.
An Intuitionistic Epistemic Logic for Sequential Consistency on Shared Memory
Hirai, Yoichi
In the celebrated Gödel Prize winning papers, Herlihy, Shavit, Saks and Zaharoglou gave topological characterization of waitfree computation. In this paper, we characterize waitfree communication logically. First, we give an intuitionistic epistemic logic k∨ for asynchronous communication. The semantics for the logic k∨ is an abstraction of Herlihy and Shavit's topological model. In the same way Kripke model for intuitionistic logic informally describes an agent increasing its knowledge over time, the semantics of k∨ describes multiple agents passing proofs around and developing their knowledge together. On top of the logic k∨, we give an axiom type that characterizes sequential consistency on shared memory. The advantage of intuitionistic logic over classical logic then becomes apparent as the axioms for sequential consistency are meaningless for classical logic because they are classical tautologies. The axioms are similar to the axiom type for prelinearity (ϕ ⊃ ψ) ∨ (ψ ⊃ ϕ). This similarity reflects the analogy between sequential consistency for shared memory scheduling and linearity for Kripke frames: both require total order on schedules or models. Finally, under sequential consistency, we give soundness and completeness between a set of logical formulas called waitfree assertions and a set of models called waitfree schedule models.
Scalable asynchronous execution of cellular automata
Folino, Gianluigi; Giordano, Andrea; Mastroianni, Carlo
2016-10-01
The performance and scalability of cellular automata, when executed on parallel/distributed machines, are limited by the necessity of synchronizing all the nodes at each time step, i.e., a node can execute only after the execution of the previous step at all the other nodes. However, these synchronization requirements can be relaxed: a node can execute one step after synchronizing only with the adjacent nodes. In this fashion, different nodes can execute different time steps. This can be a notable advantageous in many novel and increasingly popular applications of cellular automata, such as smart city applications, simulation of natural phenomena, etc., in which the execution times can be different and variable, due to the heterogeneity of machines and/or data and/or executed functions. Indeed, a longer execution time at a node does not slow down the execution at all the other nodes but only at the neighboring nodes. This is particularly advantageous when the nodes that act as bottlenecks vary during the application execution. The goal of the paper is to analyze the benefits that can be achieved with the described asynchronous implementation of cellular automata, when compared to the classical all-to-all synchronization pattern. The performance and scalability have been evaluated through a Petri net model, as this model is very useful to represent the synchronization barrier among nodes. We examined the usual case in which the territory is partitioned into a number of regions, and the computation associated with a region is assigned to a computing node. We considered both the cases of mono-dimensional and two-dimensional partitioning. The results show that the advantage obtained through the asynchronous execution, when compared to the all-to-all synchronous approach is notable, and it can be as large as 90% in terms of speedup.
Evaluating the Efficiency of Asynchronous Systems with FASE
Buti, Federico; Corradini, Flavio; Di Berardini, Maria Rita; Vogler, Walter
2011-01-01
In this paper, we present FASE (Faster Asynchronous Systems Evaluation), a tool for evaluating the worst-case efficiency of asynchronous systems. The tool is based on some well-established results in the setting of a timed process algebra (PAFAS: a Process Algebra for Faster Asynchronous Systems). To show the applicability of FASE to concrete meaningful examples, we consider three implementations of a bounded buffer and use FASE to automatically evaluate their worst-case efficiency. We finally contrast our results with previous ones where the efficiency of the same implementations has already been considered.
Constant fan-in digital neural networks are VLSI-optimal
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1995-12-31
The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
High-energy heavy ion testing of VLSI devices for single event upsets and latch up
Indian Academy of Sciences (India)
S B Umesh; S R Kulkarni; R Sandhya; G R Joshi; R Damle; M Ravindra
2005-08-01
Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) and single event latch up (SEL). The experimental set up employed to produce low flux of heavy ions viz. silicon (Si), and silver (Ag), for studying single event effects (SEE) is briefly described. The heavy ion testing of a few VLSI devices is performed in the general purpose scattering chamber of the Pelletron facility, available at Nuclear Science Centre, New Delhi. The test results with respect to SEU and SEL are discussed.
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
Deyong, Mark R.; Findley, Randall L.; Fields, Chris
1992-01-01
A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.
Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts
Scheibler, Robin; Chebira, Amina
2011-01-01
We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.
Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects
Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan
2016-03-01
In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.
Adaptive WTA with an analog VLSI neuromorphic learning chip.
Häfliger, Philipp
2007-03-01
In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.
VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement
Directory of Open Access Journals (Sweden)
Jigar Shah
2012-07-01
Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.
DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK
Directory of Open Access Journals (Sweden)
D.Yammenavar
2011-08-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption andlearning using analog computations. Furthermore nature has evolved techniques to deal with impreciseanalog computations by using redundancy and massive connectivity. In this paper we are making use ofArtificial Neural Network to demonstrate the way in which the biological system processes in analogdomain.We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmeticoperations and for implementing Neural Network. The arithmetic circuits presented here are based onMOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier,adder and neuron activation function.The functionality of designed neural network is verified for analog operations like signal amplificationand frequency multiplication. The network designed can be adopted for digital operations like AND, ORand NOT. The network realizes its functionality for the trained targets which is verified using simulationresults. The schematic, Layout design and verification of proposed Neural Network is carried out usingCadence Virtuoso tool.
Design and Analog VLSI Implementation of Artificial Neural Network
Directory of Open Access Journals (Sweden)
Prof. Bapuray.D.Yammenavar
2011-07-01
Full Text Available Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which performs arithmetic operations and for implementing Neural Network. The arithmetic circuits presented here are based on MOS transistors operating in subthreshold region. The basic blocks of artificial neuron are multiplier, adder and neuron activation function. The functionality of designed neural network is verified for analog operations like signal amplification and frequency multiplication. The network designed can be adopted for digital operations like AND, OR and NOT. The network realizes its functionality for the trained targets which is verified using simulation results. The schematic, Layout design and verification of proposed Neural Network is carried out using Cadence Virtuoso tool.
Efficient VLSI architecture of CAVLC decoder with power optimized
Institute of Scientific and Technical Information of China (English)
CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min
2009-01-01
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
A bioinspired collision detection algorithm for VLSI implementation
Cuadri, J.; Linan, G.; Stafford, R.; Keil, M. S.; Roca, E.
2005-06-01
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.
Parallel VLSI design for the fast -D DWT core algorithm
Institute of Scientific and Technical Information of China (English)
WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong
2007-01-01
By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.
Sequential stochastic optimization
Cairoli, Renzo
1996-01-01
Sequential Stochastic Optimization provides mathematicians and applied researchers with a well-developed framework in which stochastic optimization problems can be formulated and solved. Offering much material that is either new or has never before appeared in book form, it lucidly presents a unified theory of optimal stopping and optimal sequential control of stochastic processes. This book has been carefully organized so that little prior knowledge of the subject is assumed; its only prerequisites are a standard graduate course in probability theory and some familiarity with discrete-paramet
Directory of Open Access Journals (Sweden)
Sidorenko V. P.
2012-08-01
Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.
Experimental demonstration of a tunable laser using an SOA and an Opto-VLSI Processor.
Aljada, Muhsen; Zheng, Rong; Alameh, Kamal; Lee, Yong-Tak
2007-07-23
In this paper we propose and experimentally demonstrate a tunable laser structure cascading a semiconductor optical amplifier (SOA) that generates broadband amplified spontaneous emission and a reflective Opto-VLSI processor that dynamically reflects arbitrarily wavelengths and injects them back into the SOA, thus synthesizing an output signal of variable wavelength. The wavelength tunablility is performed using digital phase holograms uploaded on the Opto-VLSI processor. Experimental results demonstrate a tuning range from 1524nm to 1534nm, and show that the proposed tunable laser structure has a stable performance.
The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits
Energy Technology Data Exchange (ETDEWEB)
Amendolia, S.R. (Univ. of Sassari and INFN, Pisa (Italy)); Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L. (Univ. and Scuola Normale Superiore, Pisa (Italy). INFN); Sciacca, G. (Univ. and LNS, Catania (Italy)); Turini, N. (Univ. and INFN, Bologna (Italy))
1993-08-01
An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used.
Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)
Institute of Scientific and Technical Information of China (English)
周涛; 吴行军; 白国强; 陈弘毅
2003-01-01
Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors
Directory of Open Access Journals (Sweden)
S. K. Nandy
1994-01-01
Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.
Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute
Williams, John
2008-01-01
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the
A Multiple—Valued Algebra for Modeling MOS VLSI Circuits at Switch—Level
Institute of Scientific and Technical Information of China (English)
胡谋
1992-01-01
A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.
Optimum Multiuser Detector for Multipath Slow Fading Asynchronous CDMA Channels
Institute of Scientific and Technical Information of China (English)
WangZhaocheng; YangZhixing; 等
1995-01-01
A structure of optimum multiuser detector for asynchronous CDMA in multipath slow fading channels is derived and the significant performance gain over the conventional RAKE receiv-er is shown by simulation.
Stand-Alone and Hybrid Positioning Using Asynchronous Pseudolites
Directory of Open Access Journals (Sweden)
Ciro Gioia
2014-12-01
Full Text Available global navigation satellite system (GNSS receivers are usually unable to achieve satisfactory performance in difficult environments, such as open-pit mines, urban canyons and indoors. Pseudolites have the potential to extend GNSS usage and significantly improve receiver performance in such environments by providing additional navigation signals. This also applies to asynchronous pseudolite systems, where different pseudolites operate in an independent way. Asynchronous pseudolite systems require, however, dedicated strategies in order to properly integrate GNSS and pseudolite measurements. In this paper, several asynchronous pseudolite/GNSS integration strategies are considered: loosely- and tightly-coupled approaches are developed and combined with pseudolite proximity and receiver signal strength (RSS-based positioning. The performance of the approaches proposed has been tested in different scenarios, including static and kinematic conditions. The tests performed demonstrate that the methods developed are effective techniques for integrating heterogeneous measurements from different sources, such as asynchronous pseudolites and GNSS.
A proof system for asynchronously communicating deterministic processes
de Boer, F.S.|info:eu-repo/dai/nl/072666641; van Hulst, M.
1994-01-01
We introduce in this paper new communication and synchronization constructs which allow deterministic processes, communicating asynchronously via unbounded FIFO buffers, to cope with an indeterminate environment. We develop for the resulting parallel programming language, which subsumes deterministi
A proof system for asynchronously communicating deterministic processes
de Boer, F.S.; van Hulst, M.
1994-01-01
We introduce in this paper new communication and synchronization constructs which allow deterministic processes, communicating asynchronously via unbounded FIFO buffers, to cope with an indeterminate environment. We develop for the resulting parallel programming language, which subsumes deterministi
Current Trends in High-Level Synthesis of Asynchronous Circuits
DEFF Research Database (Denmark)
Sparsø, Jens
2009-01-01
This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.......g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add highlevel synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes...... a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly...
Asynchronous Multi-Party Computation with Quadratic Communication
DEFF Research Database (Denmark)
Hirt, Martin; Nielsen, Jesper Buus; Przydatek, Bartosz
2008-01-01
We present an efficient protocol for secure multi-party computation in the asynchronous model with optimal resilience. For n parties, up to t computed with communication complexity O(cn^2k) bits, which...
Asynchronous Mid-Value Select in Hybrid SAL
National Aeronautics and Space Administration — The following SAL model is an abstraction of a module that implements a fault-tolerant mid-value select on asynchronously produced inputs. This is part of a larger...
TCDQ-TCT retraction and losses during asynchronous beam dump
Bracco, Chiara; Quaranta, Elena; CERN. Geneva. ATS Department
2016-01-01
The protection provided by the TCDQs in case of asynchronous beam dump depends strongly on their correct setup. They have to respect the strict hierarchy of the full collimation system and shield the tertiary collimators in the experimental regions. This MD aimed at performing asynchronous beam dump tests with different configurations, in order to assess the minimum allowed retraction between TCTs and TCDQs and, as a consequence, on the The protection provided by the TCDQs in case of asynchronous beam dump depends strongly on their correct setup. They have to respect the strict hierarchy of the full collimation system and shield the tertiary collimators in the experimental regions. This MD aimed at performing asynchronous beam dump tests with different configurations, in order to assess the minimum allowed retraction between TCTs and TCDQs and, as a consequence, on the β* reach.
Experimental 3D Asynchronous Field Programmable Gate Array (FPGA)
2015-03-01
EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) CORNELL UNIVERSITY MARCH 2015 FINAL TECHNICAL REPORT APPROVED FOR PUBLIC...From - To) OCT 2011 – OCT 2014 4. TITLE AND SUBTITLE EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) 5a. CONTRACT NUMBER...in collaboration with Albany’s College of Nanoscale Science and Engineering. 15. SUBJECT TERMS 3D Technology, vertical interconnects, AFPGA, FPGA
Novel Asynchronous Wrapper and Its Application to GALS Systems
Institute of Scientific and Technical Information of China (English)
Zhuang Shengxian; Peng Anjin; Lars Wanhammar
2006-01-01
An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Müller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.
Forced Sequence Sequential Decoding
DEFF Research Database (Denmark)
Jensen, Ole Riis; Paaske, Erik
1998-01-01
the iteration process provides the sequential decoders with side information that allows a smaller average load and minimizes the probability of computational overflow. Analytical results for the probability that the first RS word is decoded after C computations are presented. These results are supported...
Sequential memory: Binding dynamics
Afraimovich, Valentin; Gong, Xue; Rabinovich, Mikhail
2015-10-01
Temporal order memories are critical for everyday animal and human functioning. Experiments and our own experience show that the binding or association of various features of an event together and the maintaining of multimodality events in sequential order are the key components of any sequential memories—episodic, semantic, working, etc. We study a robustness of binding sequential dynamics based on our previously introduced model in the form of generalized Lotka-Volterra equations. In the phase space of the model, there exists a multi-dimensional binding heteroclinic network consisting of saddle equilibrium points and heteroclinic trajectories joining them. We prove here the robustness of the binding sequential dynamics, i.e., the feasibility phenomenon for coupled heteroclinic networks: for each collection of successive heteroclinic trajectories inside the unified networks, there is an open set of initial points such that the trajectory going through each of them follows the prescribed collection staying in a small neighborhood of it. We show also that the symbolic complexity function of the system restricted to this neighborhood is a polynomial of degree L - 1, where L is the number of modalities.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER DESIGN
Directory of Open Access Journals (Sweden)
Basel Halak
2016-02-01
Full Text Available The use of asynchronous design approaches to construct digital signal processing (DSP systems is a rapidly growing research area driven by a wide range of emerging energy constrained applications such as wireless sensor network, portable medical devices and brain implants. The asynchronous design techniques allow the construction of systems which are samples driven, which means they only dissipate dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous design over conventional synchronous circuits allows them to be energy efficient. However the implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard synchronous design tools and modelling languages. This paper devises a novel asynchronous design for a finite impulse response (FIR filter, an essential building block of DSP systems, which is synthesizable and suitable for implementation using conventional synchronous systems design flow and tools. The proposed design is based on a modified version of the micropipline architecture and it is constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been developed on an FPGA, and systematically verified. The results prove correct functionality of the novel design and a superior performance compared to a synchronous FIR implementation. The findings of this work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and performance benefits.
VLSI circuits implementing computational models of neocortical circuits.
Wijekoon, Jayawan H B; Dudek, Piotr
2012-09-15
This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.
Commande adaptive d'une machine asynchrone
Slama-Belkhodja, I.; de Fornel, B.
1996-06-01
The paper deals with an indirect self-tuning speed control for an induction motor supplied by a chopper-filter-inverter system. Input/Output models are identified with the recursive least squares algorithm and the controller adaptation is based on a pole assignement strategy. Emphasis is put on the evaluation of the parameter identification in order to avoid instabilities because of disturbances or insufficient excitations. This is especially of importance when the adaptive control is carried out in closed loop systems and without additional test signals. Simulation results show the improvement of the dynamic responses and the robustness against load variations or parameters variations (rotor resistance, inertia). Cat article décrit une stratégie de commande adaptive indirecte à Placement de Pôles (PP), appliquée à la commande en vitesse d'une machine asynchrone alimentée par un ensemble hacheur-filtre-onduleur de tension. L'algorithme des Moindres Carrés Récursifs (MCR) est utilisé pour l'identification des modèles de comportement type entrées/sorties. Un intérêt particulier est porté à la mise en oeuvre de cet algorithme et à la discussion de ses résultats, tenant compte des erreurs de modélisation et de la nature peu riche en excitations des entrées du processus. Différents régimes transitoires ont été simulés pour apprécier l'apport de cette association (MCR-PP) : démarrages et inversion des sens de rotation, à vide et en charges, applications d'échelons de couple résistant, variations paramétriques. Les résultats permettent d'illustrer, tant au niveau des performances que de la robustesse, l'apport d'une telle commande adaptive pour des entraînements électriques avec une machine asynchrone.
A fast lightstripe rangefinding system with smart VLSI sensor
Gruss, Andrew; Carley, L. Richard; Kanade, Takeo
1989-01-01
The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.
Asynchronous Rate Chaos in Spiking Neuronal Circuits
Harish, Omri; Hansel, David
2015-01-01
The brain exhibits temporally complex patterns of activity with features similar to those of chaotic systems. Theoretical studies over the last twenty years have described various computational advantages for such regimes in neuronal systems. Nevertheless, it still remains unclear whether chaos requires specific cellular properties or network architectures, or whether it is a generic property of neuronal circuits. We investigate the dynamics of networks of excitatory-inhibitory (EI) spiking neurons with random sparse connectivity operating in the regime of balance of excitation and inhibition. Combining Dynamical Mean-Field Theory with numerical simulations, we show that chaotic, asynchronous firing rate fluctuations emerge generically for sufficiently strong synapses. Two different mechanisms can lead to these chaotic fluctuations. One mechanism relies on slow I-I inhibition which gives rise to slow subthreshold voltage and rate fluctuations. The decorrelation time of these fluctuations is proportional to the time constant of the inhibition. The second mechanism relies on the recurrent E-I-E feedback loop. It requires slow excitation but the inhibition can be fast. In the corresponding dynamical regime all neurons exhibit rate fluctuations on the time scale of the excitation. Another feature of this regime is that the population-averaged firing rate is substantially smaller in the excitatory population than in the inhibitory population. This is not necessarily the case in the I-I mechanism. Finally, we discuss the neurophysiological and computational significance of our results. PMID:26230679
Managing Asynchronous Data in ATLAS's Concurrent Framework
Leggett, Charles; The ATLAS collaboration
2016-01-01
In order to be able to make effective use of emerging hardware, where the amount of memory available to any CPU is rapidly decreasing as the core count continues to rise, ATLAS has begun a migration to a concurrent, multi-threaded software framework, known as AthenaMT. Significant progress has been made in implementing AthenaMT - we can currently run realistic Geant4 simulations on massively concurrent machines. the migration of realistic prototypes of reconstruction workflows is more difficult, given the large amounts of legacy code and the complexity and challenges of reconstruction software. These types of workflows, however, are the types that will most benefit from the memory reduction features of a multi-threaded framework. One of the challenges that we will report on in this paper is the re-design and implementation of several key asynchronous technologies whose behaviour is radically different in a concurrent environment than in a serial one, namely the management of Conditions data and the Detector D...
Rapid, generalized adaptation to asynchronous audiovisual speech.
Van der Burg, Erik; Goodbourn, Patrick T
2015-04-01
The brain is adaptive. The speed of propagation through air, and of low-level sensory processing, differs markedly between auditory and visual stimuli; yet the brain can adapt to compensate for the resulting cross-modal delays. Studies investigating temporal recalibration to audiovisual speech have used prolonged adaptation procedures, suggesting that adaptation is sluggish. Here, we show that adaptation to asynchronous audiovisual speech occurs rapidly. Participants viewed a brief clip of an actor pronouncing a single syllable. The voice was either advanced or delayed relative to the corresponding lip movements, and participants were asked to make a synchrony judgement. Although we did not use an explicit adaptation procedure, we demonstrate rapid recalibration based on a single audiovisual event. We find that the point of subjective simultaneity on each trial is highly contingent upon the modality order of the preceding trial. We find compelling evidence that rapid recalibration generalizes across different stimuli, and different actors. Finally, we demonstrate that rapid recalibration occurs even when auditory and visual events clearly belong to different actors. These results suggest that rapid temporal recalibration to audiovisual speech is primarily mediated by basic temporal factors, rather than higher-order factors such as perceived simultaneity and source identity.
Managing Asynchronous Data in ATLAS's Concurrent Framework
Baines, John; The ATLAS collaboration
2016-01-01
In order to be able to make effective use of emerging hardware, where the amount of memory available to any CPU is rapidly decreasing as the core count continues to rise, ATLAS has begun a migration to a concurrent, multi-threaded software framework, known as AthenaMT. Significant progress has been made in implementing AthenaMT - we can currently run realistic Geant4 simulations on massively concurrent machines. the migration of realistic prototypes of reconstruction workflows is more difficult, given the large amounts of legacy code and the complexity and challenges of reconstruction software. These types of workflows, however, are the types that will most benefit from the memory reduction features of a multi-threaded framework. One of the challenges that we will report on in this paper is the re-design and implementation of several key asynchronous technologies whose behaviour is radically different in a concurrent environment than in a serial one, namely the management of Conditions data and the Detector D...
A VLSI Processor Design of Real-Time Data Compression for High-Resolution Imaging Radar
Fang, W.
1994-01-01
For the high-resolution imaging radar systems, real-time data compression of raw imaging data is required to accomplish the science requirements and satisfy the given communication and storage constraints. The Block Adaptive Quantizer (BAQ) algorithm and its associated VLSI processor design have been developed to provide a real-time data compressor for high-resolution imaging radar systems.
Fully-depleted silicon-on-sapphire and its application to advanced VLSI design
Offord, Bruce W.
1992-01-01
In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.
VLSI chip-set for data compression using the Rice algorithm
Venbrux, J.; Liu, N.
1990-01-01
A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
Synthesis of on-chip control circuits for mVLSI biochips
DEFF Research Database (Denmark)
Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin
2017-01-01
them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G C; Cirio, R; Donetti, M; Figus, M; Marchetto, F; Peroni, C; Pernigotti, E; Thénard, J M; Zampieri, A
1999-01-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
Bayoumi, Magdy
As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…
A VLSI analog pipeline read-out for electrode segmented ionization chambers
Bonazzola, G. C.; Bouvier, S.; Cirio, R.; Donetti, M.; Figus, M.; Marchetto, F.; Peroni, C.; Pernigotti, E.; Thenard, J. M.; Zampieri, A.
1999-05-01
We report on the design and test of a 32-channel VLSI chip based on the analog pipeline memory concept. The charge from a strip of a ionization chamber, is stored as a function of time in a switched capacitor array. The cell reading can be done in parallel with the writing.
Sequential measurements of conjugate observables
Energy Technology Data Exchange (ETDEWEB)
Carmeli, Claudio [Dipartimento di Fisica, Universita di Genova, Via Dodecaneso 33, 16146 Genova (Italy); Heinosaari, Teiko [Department of Physics and Astronomy, Turku Centre for Quantum Physics, University of Turku, 20014 Turku (Finland); Toigo, Alessandro, E-mail: claudio.carmeli@gmail.com, E-mail: teiko.heinosaari@utu.fi, E-mail: alessandro.toigo@polimi.it [Dipartimento di Matematica ' Francesco Brioschi' , Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133 Milano (Italy)
2011-07-15
We present a unified treatment of sequential measurements of two conjugate observables. Our approach is to derive a mathematical structure theorem for all the relevant covariant instruments. As a consequence of this result, we show that every Weyl-Heisenberg covariant observable can be implemented as a sequential measurement of two conjugate observables. This method is applicable both in finite- and infinite-dimensional Hilbert spaces, therefore covering sequential spin component measurements as well as position-momentum sequential measurements.
ASCERTAINMENT OF THE EQUIVALENT CIRCUIT PARAMETERS OF THE ASYNCHRONOUS MACHINE
Directory of Open Access Journals (Sweden)
V. S. Safaryan
2015-01-01
Full Text Available The article considers experimental and analytical determination of the asynchronous machine equivalent-circuit parameters with application of the reference data. Transient processes investigation of the asynchronous machines necessitates the equivalent circuit parameters (resistance impedance, inductances and coefficient of the stator-rotor contours mutual inductance that help form the transitory-process mathematical simulation model. The reference books do not provide those parameters; they instead give the rated ones (active power, voltage, slide, coefficient of performance and capacity coefficient as well as the ratio of starting and nominal currents and torques. The noted studies on the asynchronous machine equivalent-circuits parametrization fail to solve the problems ad finem or solve them with admissions. The paper presents experimental and analytical determinations of the asynchronous machine equivalent-circuit parameters: the experimental one based on the results of two measurements and the analytical one where the problem boils down to solving a system of nonlineal algebraic equations. The authors investigate the equivalent asynchronous machine input-resistance properties and adduce the dependence curvatures of the input-resistances on the slide. They present a symbolic model for analytical parameterization of the asynchronous machine equivalent-circuit that represents a system of nonlineal equations and requires one of the rotor-parameters arbitrary assignment. The article demonstrates that for the asynchronous machine equivalent-circuit experimental parameterization the measures are to be conducted of the stator-circuit voltage, current and active power with two different slides and arbitrary assignment of one of the rotor parameters. The paper substantiates the fact that additional measurement does not discard the rotor-parameter choice arbitrariness. The authors establish that in motoring mode there is a critical slide by which the
Modelling sequentially scored item responses
Akkermans, W.
2000-01-01
The sequential model can be used to describe the variable resulting from a sequential scoring process. In this paper two more item response models are investigated with respect to their suitability for sequential scoring: the partial credit model and the graded response model. The investigation is c
Scalable Symmetric Key Cryptography Using Asynchronous Data Exchange in Enterprise Grid
Directory of Open Access Journals (Sweden)
Medhat Awadallah
2011-11-01
Full Text Available Symmetric key cryptography is one of the most critical computing problems that need high performance computing power resources. The use of large key sizes and complex encryption/decryption algorithms to achieve unbreakable state has led to an increased time computational complexity. Traditionally, this problem is solved in the grid environment by partitioning data streams into several blocks of a predefined size. This is done while sequentially reading the data from the raw data file. The grid manager node then takes the responsibility of passing these blocks to the executer nodes where different blocks are processed separately and simultaneously. Although this technique allows parallel processing to speed up the encryption/decryption process, creating blocks by sequentially reading the data file and distributing these blocks on executers synchronously by the central manager node is a poor technique and a source of delay. In this paper, we present a novel approach that tackles this problem by allowing executers to access data file at random and asynchronously exchange the blocks among them, thereby, delay is significantly reduced and data size can be scaled up. In order to show the merit of our approach experiments have been conducted through a system-level middleware for grid computing called Alchemi. The results show a remarkable performance enhancement in our approach over traditional approaches in terms of speed.
Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits
Directory of Open Access Journals (Sweden)
Anindya Jana
2012-05-01
Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.
Sequential cloning of chromosomes
Energy Technology Data Exchange (ETDEWEB)
Lacks, S.A.
1991-12-31
A method for sequential cloning of chromosomal DNA and chromosomal DNA cloned by this method are disclosed. The method includes the selection of a target organism having a segment of chromosomal DNA to be sequentially cloned. A first DNA segment, having a first restriction enzyme site on either side. homologous to the chromosomal DNA to be sequentially cloned is isolated. A first vector product is formed by ligating the homologous segment into a suitably designed vector. The first vector product is circularly integrated into the target organism`s chromosomal DNA. The resulting integrated chromosomal DNA segment includes the homologous DNA segment at either end of the integrated vector segment. The integrated chromosomal DNA is cleaved with a second restriction enzyme and ligated to form a vector-containing plasmid, which is replicated in a host organism. The replicated plasmid is then cleaved with the first restriction enzyme. Next, a DNA segment containing the vector and a segment of DNA homologous to a distal portion of the previously isolated DNA segment is isolated. This segment is then ligated to form a plasmid which is replicated within a suitable host. This plasmid is then circularly integrated into the target chromosomal DNA. The chromosomal DNA containing the circularly integrated vector is treated with a third, retrorestriction enzyme. The cleaved DNA is ligated to give a plasmid that is used to transform a host permissive for replication of its vector. The sequential cloning process continues by repeated cycles of circular integration and excision. The excision is carried out alternately with the second and third enzymes.
Sequential cloning of chromosomes
Lacks, S.A.
1995-07-18
A method for sequential cloning of chromosomal DNA of a target organism is disclosed. A first DNA segment homologous to the chromosomal DNA to be sequentially cloned is isolated. The first segment has a first restriction enzyme site on either side. A first vector product is formed by ligating the homologous segment into a suitably designed vector. The first vector product is circularly integrated into the target organism`s chromosomal DNA. The resulting integrated chromosomal DNA segment includes the homologous DNA segment at either end of the integrated vector segment. The integrated chromosomal DNA is cleaved with a second restriction enzyme and ligated to form a vector-containing plasmid, which is replicated in a host organism. The replicated plasmid is then cleaved with the first restriction enzyme. Next, a DNA segment containing the vector and a segment of DNA homologous to a distal portion of the previously isolated DNA segment is isolated. This segment is then ligated to form a plasmid which is replicated within a suitable host. This plasmid is then circularly integrated into the target chromosomal DNA. The chromosomal DNA containing the circularly integrated vector is treated with a third, retrorestriction (class IIS) enzyme. The cleaved DNA is ligated to give a plasmid that is used to transform a host permissive for replication of its vector. The sequential cloning process continues by repeated cycles of circular integration and excision. The excision is carried out alternately with the second and third enzymes. 9 figs.
A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
Richstein, James K.
1993-12-01
Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straightforward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator was designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi-opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two-dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display were combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns. The alternate design using VLSI logic gates will provide one-shot pulse widths of approximately 3 ns.
Kirk, David Blair
This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a gradient descent optimization technique. The parameter-setting and optimization tools allow us to automatically choose values for compensating our circuit building blocks, based on our goals for the circuit performance. We can also use the techniques to optimize parameters for larger systems, applying the goal-based techniques hierarchically. We also describe a set of thought experiments involving circuit techniques for increasing the precision of analog computation. Our engineering design methodology is a step toward easier use of analog VLSI to solve problems in computer graphics and neural networks. We provide data measured from compensated multipliers built using these design techniques. To demonstrate the feasibility of using analog VLSI for more quantitative computation, we develop small applications using the goal-based design approach and compensated components. Finally, we conclude by discussing the expected significance of this work for the wider use of analog VLSI for
IHadoop: Asynchronous iterations for MapReduce
Elnikety, Eslam Mohamed Ibrahim
2011-11-01
MapReduce is a distributed programming frame-work designed to ease the development of scalable data-intensive applications for large clusters of commodity machines. Most machine learning and data mining applications involve iterative computations over large datasets, such as the Web hyperlink structures and social network graphs. Yet, the MapReduce model does not efficiently support this important class of applications. The architecture of MapReduce, most critically its dataflow techniques and task scheduling, is completely unaware of the nature of iterative applications; tasks are scheduled according to a policy that optimizes the execution for a single iteration which wastes bandwidth, I/O, and CPU cycles when compared with an optimal execution for a consecutive set of iterations. This work presents iHadoop, a modified MapReduce model, and an associated implementation, optimized for iterative computations. The iHadoop model schedules iterations asynchronously. It connects the output of one iteration to the next, allowing both to process their data concurrently. iHadoop\\'s task scheduler exploits inter-iteration data locality by scheduling tasks that exhibit a producer/consumer relation on the same physical machine allowing a fast local data transfer. For those iterative applications that require satisfying certain criteria before termination, iHadoop runs the check concurrently during the execution of the subsequent iteration to further reduce the application\\'s latency. This paper also describes our implementation of the iHadoop model, and evaluates its performance against Hadoop, the widely used open source implementation of MapReduce. Experiments using different data analysis applications over real-world and synthetic datasets show that iHadoop performs better than Hadoop for iterative algorithms, reducing execution time of iterative applications by 25% on average. Furthermore, integrating iHadoop with HaLoop, a variant Hadoop implementation that caches
Gigabit Ethernet Asynchronous Clock Compensation FIFO
Duhachek, Jeff
2012-01-01
Clock compensation for Gigabit Ethernet is necessary because the clock recovered from the 1.25 Gb/s serial data stream has the potential to be 200 ppm slower or faster than the system clock. The serial data is converted to 10-bit parallel data at a 125 MHz rate on a clock recovered from the serial data stream. This recovered data needs to be processed by a system clock that is also running at a nominal rate of 125 MHz, but not synchronous to the recovered clock. To cross clock domains, an asynchronous FIFO (first-in-first-out) is used, with the write pointer (wprt) in the recovered clock domain and the read pointer (rptr) in the system clock domain. Because the clocks are generated from separate sources, there is potential for FIFO overflow or underflow. Clock compensation in Gigabit Ethernet is possible by taking advantage of the protocol data stream features. There are two distinct data streams that occur in Gigabit Ethernet where identical data is transmitted for a period of time. The first is configuration, which happens during auto-negotiation. The second is idle, which occurs at the end of auto-negotiation and between every packet. The identical data in the FIFO can be repeated by decrementing the read pointer, thus compensating for a FIFO that is draining too fast. The identical data in the FIFO can also be skipped by incrementing the read pointer, which compensates for a FIFO draining too slowly. The unique and novel features of this FIFO are that it works in both the idle stream and the configuration streams. The increment or decrement of the read pointer is different in the idle and compensation streams to preserve disparity. Another unique feature is that the read pointer to write pointer difference range changes between compensation and idle to minimize FIFO latency during packet transmission.
Asynchronous reference frame agreement in a quantum network
Islam, Tanvirul; Wehner, Stephanie
2016-03-01
An efficient implementation of many multiparty protocols for quantum networks requires that all the nodes in the network share a common reference frame. Establishing such a reference frame from scratch is especially challenging in an asynchronous network where network links might have arbitrary delays and the nodes do not share synchronised clocks. In this work, we study the problem of establishing a common reference frame in an asynchronous network of n nodes of which at most t are affected by arbitrary unknown error, and the identities of the faulty nodes are not known. We present a protocol that allows all the correctly functioning nodes to agree on a common reference frame as long as the network graph is complete and not more than t\\lt n/4 nodes are faulty. As the protocol is asynchronous, it can be used with some assumptions to synchronise clocks over a network. Also, the protocol has the appealing property that it allows any existing two-node asynchronous protocol for reference frame agreement to be lifted to a robust protocol for an asynchronous quantum network.
DYNAMIC REGIMES OF ASYNCHRONOUS MOTORS WITH CONCATENATED CAPACITORS
Directory of Open Access Journals (Sweden)
V. S. Malyar
2015-04-01
Full Text Available Purpose. Development of mathematical model for calculation of starting modes of asynchronous motor connected in series with capacitors. Method. Mathematical modeling of dynamic modes of asynchronous motors with lateral capacitor compensation of reactive power. Results. The calculation algorithm and results of mathematic modeling of processes during starting modes of asynchronous motor feeding from the network through capacitors connected in series are presented. It is shown that for some values of capacitance the self-excitation processes and subharmonic oscillations can appear. Scientific novelty. Mathematic modeling and research of processes in asynchronous motor under its feeding through capacitors is carried out for the first time. The calculation algorithm is based on the mathematical model of asynchronous motor with high level of adequacy, which takes into account the magnetic core saturation and the current displacement in limbs of the rotor. Practical implication. Developed mathematical model makes it possible to investigate the possibility of self-excitation modes appearing in condition of their feeding from line with lateral compensation of reactance in order to avoid the negative effects typical for them.
Advanced plasma etching processes for dielectric materials in VLSI technology
Wang, Juan Juan
Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the
Asynchronous Communication: Capacity Bounds and Suboptimality of Training
Tchamkerten, Aslan; Wornell, Gregory
2011-01-01
Basic limits of asynchronous point-to-point communication over discrete memoryless channels are established. In the system model of interest, the codeword is transmitted over a channel starting at a random time within a prescribed window whose length corresponds to the level of asynchronism in the system. Communication rate is defined as the ratio between the message size and the elapsed time between when transmission commences and when the decoder makes a decision. Upper and lower bounds on the capacity of such systems are established, and are shown to coincide in some nontrivial cases. Additional properties of capacity as a function of the level of asynchronism are also developed. In practice, communication is typically structured according to a training-based architecture, whereby synchronization and communication are implemented separately. We quantify the inherent constraints in this architecture, and analyze its corresponding performance limits. We show that, in general, schemes conforming to this archi...
Forced Sequence Sequential Decoding
DEFF Research Database (Denmark)
Jensen, Ole Riis
In this thesis we describe a new concatenated decoding scheme based on iterations between an inner sequentially decoded convolutional code of rate R=1/4 and memory M=23, and block interleaved outer Reed-Solomon codes with non-uniform profile. With this scheme decoding with good performance is pos...... of computational overflow. Analytical results for the probability that the first Reed-Solomon word is decoded after C computations are presented. This is supported by simulation results that are also extended to other parameters....
A Loosely Synchronizing Asynchronous Router for TDM-Scheduled NOCs
DEFF Research Database (Denmark)
Kotleas, Ioannis; Humphreys, Dean; Sørensen, Rasmus Bo
2014-01-01
This paper presents an asynchronous router design for use in time-division-multiplexed (TDM) networks-on-chip. Unlike existing synchronous, mesochronous and asynchronous router designs with similar functionality, the router is able to silently skip over cycles/TDM-slots where no traffic...... is scheduled and hence avoid all switching activity in the idle links and router ports. In this way switching activity is reduced to the minimum possible amount. The fact that this relaxed synchronization is sufficient to implement TDM scheduling represents a contribution at the conceptual level. The idea can...
On the theoretical gap between synchronous and asynchronous MPC protocols
DEFF Research Database (Denmark)
Beerliová-Trubíniová, Zuzana; Hirt, Martin; Nielsen, Jesper Buus
2010-01-01
that in the cryptographic setting (with setup), the sole reason for it is the distribution of inputs: given an oracle for input distribution, cryptographically-secure asynchronous MPC is possible with the very same condition as synchronous MPC, namely t ..., we show that such an input-distribution oracle can be reduced to an oracle that allows each party to synchronously broadcast one single message. This means that when one single round of synchronous broadcast is available, then asynchronous MPC is possible at the same condition as synchronous MPC...
Design issues in the semantics and scheduling of asynchronous tasks.
Energy Technology Data Exchange (ETDEWEB)
Olivier, Stephen L.
2013-07-01
The asynchronous task model serves as a useful vehicle for shared memory parallel programming, particularly on multicore and manycore processors. As adoption of model among programmers has increased, support has emerged for the integration of task parallel language constructs into mainstream programming languages, e.g., C and C++. This paper examines some of the design decisions in Cilk and OpenMP concerning semantics and scheduling of asynchronous tasks with the aim of informing the efforts of committees considering language integration, as well as developers of new task parallel languages and libraries.
Asynchronous Broadcast on the Intel SCC using Interrupts
Petrović, Darko; Shahmirzadi, Omid; Ropars, Thomas; Schiper, André
2012-01-01
International audience; This paper focuses on the design of an asynchronous broadcast primitive on the Intel SCC. Our solution is based on OC-Bcast, a state-of-the-art k-ary tree synchronous broadcast algorithm that leverages the parallelism provided by on-chip Remote Memory Accesses to Message Passing Buffers. In the paper, we study the use of parallel inter-core interrupts as a means to implement an efficient asynchronous group communication primitive, and present the userspace library we d...
Harrison, R R; Koch, C
1999-10-01
Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.
A cost-effective methodology for the design of massively-parallel VLSI functional units
Venkateswaran, N.; Sriram, G.; Desouza, J.
1993-01-01
In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.
Xiao, Feng; Alameh, Kamal; Lee, Yong Tak
2009-12-07
A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.
VLSI architectures for computing multiplications and inverses in GF(2-m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.
1983-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
VLSI architectures for computing multiplications and inverses in GF(2m)
Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.
1985-01-01
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam
2011-12-01
Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.
Energy Technology Data Exchange (ETDEWEB)
Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)
2014-01-31
The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.
Las Vegas is better than determinism in VLSI and distributed computing
DEFF Research Database (Denmark)
Mehlhorn, Kurt; Schmidt, Erik Meineche
1982-01-01
to (accepting) nondeterministic computations as well as to deterministic computations. Hence whenever a boolean function f is such that f and -&-fmarc; (the complement of f, -&-fmarc; -&-equil; 1 -&-minus; f) have efficient nondeterministic chips then the known techniques are of no help for proving lower bounds...... on the complexity of deterministic chips. In this paper we describe a lower bound technique (Thm 1) which only applies to deterministic computations......In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply...
Active Sequential Hypothesis Testing
Naghshvar, Mohammad
2012-01-01
Consider a decision maker who is responsible to dynamically collect observations so as to enhance his information in a speedy manner about an underlying phenomena of interest while accounting for the penalty of wrong declaration. The special cases of the problem are shown to be that of variable-length coding with feedback and noisy dynamic search. Due to the sequential nature of the problem, the decision maker relies on his current information state to adaptively select the most "informative" sensing action among the available ones. In this paper, using results in dynamic programming, a lower bound for the optimal total cost is established. Moreover, upper bounds are obtained via an analysis of heuristic policies for dynamic selection of actions. It is shown that the proposed heuristics achieve asymptotic optimality in many practically relevant problems including the problems of variable-length coding with feedback and noisy dynamic search; where asymptotic optimality implies that the relative difference betw...
Asynchronous Session Types – Exceptions and Multiparty Interactions
DEFF Research Database (Denmark)
Carbone, Marco; Yoshida, Nobuko; Honda, Kohei
2009-01-01
to capture many real scenarios, there are cases where they are not powerful enough for describing and validating interactions involving more complex scenarios. In this note, we shall explore two extensions of session types to interactional exceptions and multiparty session in presence of asynchronous...
Psychological Type and Asynchronous Written Dialogue in Adult Learning
Lin, Lin; Cranton, Patricia; Bridglall, Beatrice
2005-01-01
This study explores how adults learn from asynchronous written dialogue through the lens of psychological type preferences. We asked participants to discover their dominant and auxiliary psychological preferences using the Personal Empowerment through Type inventory. Participants then completed an open-ended survey in which they described their…
Reliable interface design for combining asynchronous and synchronous circuits
Josephson, Lueli; Brunvand, Erik L.; Gopalakrishan, Ganesh; Hurdle, John F.
1993-01-01
In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.
Students' Use of Asynchronous Discussions for Academic Discourse Socialization
Beckett, Gulbahar H.; Amaro-Jimenez, Carla; Beckett, Kelvin S.
2010-01-01
Our universities are becoming increasingly diverse at the same time as online asynchronous discussions (OADs) are emerging as the most important forum for computer mediated communication (CMC) in distance education. But there is shortage of studies that explore how graduate students from different ethnic, linguistic and cultural backgrounds use…
Asynchronous rotation scan for synthetic aperture interferometric radiometer
Institute of Scientific and Technical Information of China (English)
WU Ji; ZHANG Cheng; LIU Hao; SUN WeiYing
2009-01-01
Synthetic aperture interferometric technique has wide applications in optics, radio astronomy and mi-crowave remote sensing areas. With the increasing demands of high resolution imaging observation, a new time-sharing sampling scheme of asynchronous rotation scan is proposed to meet the technical challenge of achieving a large equivalent aperture and overcome the operating barriers of space borne application. This configuration is basically composed by two asynchronously and concentrically ro-tating antenna groups, whose revolving radii and speeds are different. The synthetic aperture system with asynchronous rotation scanning scheme can effectively solve the trade-off problem of system complexity, and greatly simplify the system hardware at the cost of sacrificing a certain time resolution. The basic rules and design methods of asynchronous rotation scan are investigated The Gridding method is introduced to inverse the spiral sampling data for image reconstruction. The potential ap-plications of geostationary orbit (GEO) earth observation and solar polar orbit (SPO) plasma cloud observation are explored with numerical simulations to validate the significance and feasibility of this new imaging configuration.
Asynchronous Assessment in a Large Lecture Marketing Course
Downey, W. Scott; Schetzsle, Stacey
2012-01-01
Asynchronous assessment, which includes quizzes or exams online or outside class, offers marketing educators an opportunity to make more efficient use of class time and to enhance students' learning experiences by giving them more flexibility and choice in their assessment environment. In this paper, we examine the performance difference between…
RELAXED ASYNCHRONOUS ITERATIONS FOR THE LINEAR COMPLEMENTARITY PROBLEM
Institute of Scientific and Technical Information of China (English)
Zhong-zhi Bai; Yu-guang Huang
2002-01-01
We present a class of relaxed asynchronous parallel multisplitting iterative methods forsolving the linear complementarity problem on multiprocessor systems, and set up theirconvergence theories when the system matrix of the linear complementarity problem is anH-matrix with positive diagonal elements.
Chaos begets order: asynchronous cell contractions drive epithelial morphogenesis.
Paluch, Ewa; Heisenberg, Carl-Philipp
2009-01-01
Apical cell contraction triggers tissue folding and invagination in epithelia. During Drosophila gastrulation, ventral furrow formation was thought to be driven by smooth, purse-string-like constriction of an acto-myosin belt underlying adherens junctions. Now Martin et al. report in Nature that ventral furrow formation is triggered by asynchronous pulsed contractions of the apical acto-myosin cortex in individual cells.
Abstracting Asynchronous Multi-Valued Networks: An Initial Investigation
Steggles, L Jason
2011-01-01
Multi-valued networks provide a simple yet expressive qualitative state based modelling approach for biological systems. In this paper we develop an abstraction theory for asynchronous multi-valued network models that allows the state space of a model to be reduced while preserving key properties of the model. The abstraction theory therefore provides a mechanism for coping with the state space explosion problem and supports the analysis and comparison of multi-valued networks. We take as our starting point the abstraction theory for synchronous multi-valued networks which is based on the finite set of traces that represent the behaviour of such a model. The problem with extending this approach to the asynchronous case is that we can now have an infinite set of traces associated with a model making a simple trace inclusion test infeasible. To address this we develop a decision procedure for checking asynchronous abstractions based on using the finite state graph of an asynchronous multi-valued network to reas...
Developing a Successful Asynchronous Online Extension Program for Forest Landowners
Zobrist, Kevin W.
2014-01-01
Asynchronous online Extension classes can reach a wide audience, is convenient for the learner, and minimizes ongoing demands on instructor time. However, producing such classes takes significant effort up front. Advance planning and good communication with contributors are essential to success. Considerations include delivery platforms, content…
Online Graduate Education: Developing Scholars through Asynchronous Discussion
Bowden, Randall
2012-01-01
Considerable effort has been placed on understanding and enhancing online interaction to increase student learning, examine teaching strategies, and build learning communities. This research explored another aspect of interaction: the emergence of scholarship by graduate students through asynchronous discussion. Qualitative analysis of archived…
Principles for Effective Asynchronous Online Instruction in Religious Studies
McGuire, Beverley
2017-01-01
Asynchronous online instruction has become increasingly popular in the field of religious studies. However, despite voluminous research on online learning in general and numerous articles on online theological instruction, there has been little discussion of how to effectively design and deliver online undergraduate courses in religious studies.…
Designing Asynchronous Circuits for Low Power: An IFIR Filter
DEFF Research Database (Denmark)
Nielsen, Lars Skovby; Sparsø, Jens
1999-01-01
in the same 0.7 /spl mu/m CMOS technology. When processing typical data (less than 50 dB sound pressure), the asynchronous control and data-path logic, an improved RAM design, and by a mechanism that adapts the number range to the actual need (exploiting the fact that typical audio signals are characterized...
Cyber Asynchronous versus Blended Cyber Approach in Distance English Learning
Ge, Zi-Gang
2012-01-01
This study aims to compare the single cyber asynchronous learning approach with the blended cyber learning approach in distance English education. Two classes of 70 students participated in this study, which lasted one semester of about four months, with one class using the blended approach for their English study and the other only using the…
Reconceptualising Moderation in Asynchronous Online Discussions Using Grounded Theory
Vlachopoulos, Panos; Cowan, John
2010-01-01
This article reports a grounded theory study of the moderation of asynchronous online discussions, to explore the processes by which tutors in higher education decide when and how to moderate. It aims to construct a theory of e-moderation based on some key factors which appear to influence e-moderation. It discusses previous research on the…
Miscellany of Students' Satisfaction in an Asynchronous Learning Environment
Larbi-Siaw, Otu; Owusu-Agyeman, Yaw
2017-01-01
This study investigates the determinants of students' satisfaction in an asynchronous learning environment using seven key considerations: the e-learning environment, student-content interaction, student and student interaction, student-teacher interaction, group cohesion and timely participation, knowledge of Internet usage, and satisfaction. The…
Asynchronous rotation scan for synthetic aperture interferometric radiometer
Institute of Scientific and Technical Information of China (English)
无
2009-01-01
Synthetic aperture interferometric technique has wide applications in optics,radio astronomy and mi-crowave remote sensing areas.With the increasing demands of high resolution imaging observation,a new time-sharing sampling scheme of asynchronous rotation scan is proposed to meet the technical challenge of achieving a large equivalent aperture and overcome the operating barriers of space borne application.This configuration is basically composed by two asynchronously and concentrically ro-tating antenna groups,whose revolving radii and speeds are different.The synthetic aperture system with asynchronous rotation scanning scheme can effectively solve the trade-off problem of system complexity,and greatly simplify the system hardware at the cost of sacrificing a certain time resolution.The basic rules and design methods of asynchronous rotation scan are investigated The Gridding method is introduced to inverse the spiral sampling data for image reconstruction.The potential ap-plications of geostationary orbit(GEO)earth observation and solar polar orbit(SPO)plasma cloud observation are explored with numerical simulations to validate the significance and feasibility of this new imaging configuration.
Teachers of the Gifted: Experiences with Asynchronous Development
Rosenberg, Jennifer
2012-01-01
Gifted students' development is asynchronous in the social, emotional, physical and cognitive domains. Because of this, unique interventions must be used by teachers of the gifted in order to best serve their developmental and educational needs. This qualitative study used transcendental phenomenology to examine and describe the experiences…
Asynchronous Group Review of EFL Writing: Interactions and Text Revisions
Saeed, Murad Abdu; Ghazali, Kamila
2017-01-01
The current paper reports an empirical study of asynchronous online group review of argumentative essays among nine English as foreign language (EFL) Arab university learners joining English in their first, second, and third years at the institution. In investigating online interactions, commenting patterns, and how the students facilitate text…
International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking
Shirur, Yasha; Prasad, Rekha
2013-01-01
This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.
Current-mode subthreshold MOS circuits for analog VLSI neural systems
Andreou, Andreas G.; Boahen, Kwabena A.; Pouliquen, Philippe O.; Pavasovic, Aleksandra; Jenkins, Robert E.
1991-03-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
Current-mode subthreshold MOS circuits for analog VLSI neural systems.
Andreou, A G; Boahen, K A; Pouliquen, P O; Pavasovic, A; Jenkins, R E; Strohbehn, K
1991-01-01
An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Tiri, Kris; Verbauwhede, Ingrid
2007-01-01
Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regul...
The Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter
2001-09-01
December 2000. Michael, S., Analog VLSI: Class Notes, Naval Postgraduate School, Monterey, CA, 1999. Sedra , A.S., Smith , K.C., Microelectronic...loop gain for an opamp is defined by the following equation ( Sedra , 1998) The ideal opamp has an infinite open loop gain, which can be seen from...Response (from Lee, 2000). The slew rate is defined by the following equation ( Sedra , 1998) 0 103102 10 104 105 106 107 f (Hz) 20 40 60
An Asynchronous Electric Drive with the Indirect Control of the Output Variables
Directory of Open Access Journals (Sweden)
Glazachev Alexander V.
2017-01-01
Full Text Available The article gives a mathematical description of an asynchronous motor with a device of indirect control of the electromagnetic torque and the angular velocity of the asynchronous motor in the electric drive that allows to prove on its basis the method of monitoring the output variables of the asynchronous electric motor. The simulation model of an asynchronous motor with a device of indirect control of the output variables of the asynchronous motor and the main results of the study have been given.
Matsubara, Takashi; Torikai, Hiroyuki
2016-04-01
Modeling and implementation approaches for the reproduction of input-output relationships in biological nervous tissues contribute to the development of engineering and clinical applications. However, because of high nonlinearity, the traditional modeling and implementation approaches encounter difficulties in terms of generalization ability (i.e., performance when reproducing an unknown data set) and computational resources (i.e., computation time and circuit elements). To overcome these difficulties, asynchronous cellular automaton-based neuron (ACAN) models, which are described as special kinds of cellular automata that can be implemented as small asynchronous sequential logic circuits have been proposed. This paper presents a novel type of such ACAN and a theoretical analysis of its excitability. This paper also presents a novel network of such neurons, which can mimic input-output relationships of biological and nonlinear ordinary differential equation model neural networks. Numerical analyses confirm that the presented network has a higher generalization ability than other major modeling and implementation approaches. In addition, Field-Programmable Gate Array-implementations confirm that the presented network requires lower computational resources.
Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.
Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz
2010-01-01
Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.
VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.
Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram
2010-01-01
In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.
Hsiao, Min-Chi; Chan, Chiu-Hsien; Srinivasan, Vijay; Ahuja, Ashish; Erinjippurath, Gopal; Zanos, Theodoros P; Gholmieh, Ghassan; Song, Dong; Wills, Jack D; LaCoss, Jeff; Courellis, Spiros; Tanguay, Armand R; Granacki, John J; Marmarelis, Vasilis Z; Berger, Theodore W
2006-01-01
We are developing a biomimetic electronic neural prosthesis to replace regions of the hippocampal brain area that have been damaged by disease or insult. We have used the hippocampal slice preparation as the first step in developing such a prosthesis. The major intrinsic circuitry of the hippocampus consists of an excitatory cascade involving the dentate gyrus (DG), CA3, and CA1 subregions; this trisynaptic circuit can be maintained in a transverse slice preparation. Our demonstration of a neural prosthesis for the hippocampal slice involves: (i) surgically removing CA3 function from the trisynaptic circuit by transecting CA3 axons, (ii) replacing biological CA3 function with a hardware VLSI (very large scale integration) model of the nonlinear dynamics of CA3, and (iii) through a specially designed multi-site electrode array, transmitting DG output to the hardware device, and routing the hardware device output to the synaptic inputs of the CA1 subregion, thus by-passing the damaged CA3. Field EPSPs were recorded from the CA1 dendritic zone in intact slices and "hybrid" DG-VLSI-CA1 slices. Results show excellent agreement between data from intact slices and transected slices with the hardware-substituted CA3: propagation of temporal patterns of activity from DG-->VLSI-->CA1 reproduces that observed experimentally in the biological DG-->CA3-->CA1 circuit.
Directory of Open Access Journals (Sweden)
Rachmad Vidya Wicaksana Putra
2016-06-01
Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
Multi-Attribute Sequential Search
Bearden, J. Neil; Connolly, Terry
2007-01-01
This article describes empirical and theoretical results from two multi-attribute sequential search tasks. In both tasks, the DM sequentially encounters options described by two attributes and must pay to learn the values of the attributes. In the "continuous" version of the task the DM learns the precise numerical value of an attribute when she…
A sequential tree approach for incremental sequential pattern mining
Indian Academy of Sciences (India)
RAJESH KUMAR BOGHEY; SHAILENDRA SINGH
2016-12-01
‘‘Sequential pattern mining’’ is a prominent and significant method to explore the knowledge and innovation from the large database. Common sequential pattern mining algorithms handle static databases.Pragmatically, looking into the functional and actual execution, the database grows exponentially thereby leading to the necessity and requirement of such innovation, research, and development culminating into the designing of mining algorithm. Once the database is updated, the previous mining result will be incorrect, and we need to restart and trigger the entire mining process for the new updated sequential database. To overcome and avoid the process of rescanning of the entire database, this unique system of incremental mining of sequential pattern is available. The previous approaches, system, and techniques are a priori-based frameworks but mine patterns is an advanced and sophisticated technique giving the desired solution. We propose and incorporate an algorithm called STISPM for incremental mining of sequential patterns using the sequence treespace structure. STISPM uses the depth-first approach along with backward tracking and the dynamic lookahead pruning strategy that removes infrequent and irregular patterns. The process and approach from the root node to any leaf node depict a sequential pattern in the database. The structural characteristic of the sequence tree makes it convenient and appropriate for incremental sequential pattern mining. The sequence tree also stores all the sequential patterns with its count and statistics, so whenever the support system is withdrawn or changed, our algorithm using frequent sequence tree as the storage structure can find and detect all the sequential patternswithout mining the database once again.
Sequential Design of Experiments
Energy Technology Data Exchange (ETDEWEB)
Anderson-Cook, Christine Michaela [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
2017-06-30
A sequential design of experiments strategy is being developed and implemented that allows for adaptive learning based on incoming results as the experiment is being run. The plan is to incorporate these strategies for the NCCC and TCM experimental campaigns to be run in the coming months. This strategy for experimentation has the advantages of allowing new data collected during the experiment to inform future experimental runs based on their projected utility for a particular goal. For example, the current effort for the MEA capture system at NCCC plans to focus on maximally improving the quality of prediction of CO_{2} capture efficiency as measured by the width of the confidence interval for the underlying response surface that is modeled as a function of 1) Flue Gas Flowrate [1000-3000] kg/hr; 2) CO_{2} weight fraction [0.125-0.175]; 3) Lean solvent loading [0.1-0.3], and; 4) Lean solvent flowrate [3000-12000] kg/hr.
Asynchronous telehealth: a scoping review of analytic studies.
Deshpande, Amol; Khoja, Shariq; Lorca, Julio; McKibbon, Ann; Rizo, Carlos; Husereau, Donald; Jadad, Alejandro R
2009-06-02
Asynchronous telehealth captures clinically important digital samples (e.g., still images, video, audio, text files) and relevant data in one location and subsequently transmits these files for interpretation at a remote site by health professionals without requiring the simultaneous presence of the patient involved and his or her health care provider. Its utility in the health care system, however, still remains poorly defined. We conducted this scoping review to determine the impact of asynchronous telehealth on health outcomes, process of care, access to health services, and health resources. A search was performed up to December 2006 of MEDLINE, CINAHL, HealthSTAR, the Database of Abstracts of Reviews of Effectiveness, and The Cochrane Library. Studies were included if they contained original data on the use of asynchronous telehealth and were published in English in a peer-reviewed journal. Two independent reviewers screened all articles and extracted data, reaching consensus on the articles and data identified. Data were extracted on general study characteristics, clinical domain, technology, setting, category of outcome, and results. Study quality (internal validity) was assessed using the Jadad scale for randomized controlled trials and the Downs and Black index for non-randomized studies. Summary data were categorized by medical specialty and presented qualitatively. The scoping review included 52 original studies from 238 citations identified; of these 52, almost half focused on the use of telehealth in dermatology. Included studies were characterized by diverse designs, interventions, and outcomes. Only 16 studies were judged to be of high quality. Most studies showed beneficial effects in terms of diagnostic accuracy, wait times, referral management, and satisfaction with services. Evidence on the impact of asynchronous telehealth on resource use in dermatology suggests a reduction in the number of, or avoidance of, in-person visits. Reports from other
Sequential biases in accumulating evidence
Huggins, Richard; Dogo, Samson Henry
2015-01-01
Whilst it is common in clinical trials to use the results of tests at one phase to decide whether to continue to the next phase and to subsequently design the next phase, we show that this can lead to biased results in evidence synthesis. Two new kinds of bias associated with accumulating evidence, termed ‘sequential decision bias’ and ‘sequential design bias’, are identified. Both kinds of bias are the result of making decisions on the usefulness of a new study, or its design, based on the previous studies. Sequential decision bias is determined by the correlation between the value of the current estimated effect and the probability of conducting an additional study. Sequential design bias arises from using the estimated value instead of the clinically relevant value of an effect in sample size calculations. We considered both the fixed‐effect and the random‐effects models of meta‐analysis and demonstrated analytically and by simulations that in both settings the problems due to sequential biases are apparent. According to our simulations, the sequential biases increase with increased heterogeneity. Minimisation of sequential biases arises as a new and important research area necessary for successful evidence‐based approaches to the development of science. © 2015 The Authors. Research Synthesis Methods Published by John Wiley & Sons Ltd. PMID:26626562
Sequential Testing: Basics and Benefits
1978-03-01
103-109 44. A. Wald , Sequential Analysis, John Wiley and Sons, 1947 45. A Wald and J. Wolfowitz , "Optimum Character of The Sequential Probability Ratio...work done by A. Wald [44].. Wald’s work on sequential analysis can be used virtually’without modification in a situation where decisions are made... Wald can be used. The decision to accept, reject, or continue the test depends on: 8 < (8 0/el)r exp [-(1/01 - 1/0 0 )V(t)] < A (1) where 0 and A are
The effects of sequential attention shifts within visual working memory
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Qi eLi
2014-09-01
Full Text Available Previous studies have shown conflicting data as to whether it is possible to sequentially shift spatial attention among visual working memory (VWM representations. The present study investigated this issue by asynchronously presenting attentional cues during the retention interval of a change detection task. In particular, we focused on two types of sequential attention shifts: 1 orienting attention to one location, and then withdrawing attention from it, and 2 switching the focus of attention from one location to another. In Experiment 1, a withdrawal cue was presented after a spatial retro-cue to measure the effect of withdrawing attention. The withdrawal cue significantly reduced the cost of invalid spatial cues, but surprisingly, did not attenuate the benefit of valid spatial cues. This indicates that the withdrawal cue only triggered the activation of facilitative components but not inhibitory components of attention. In Experiment 2, two spatial retro-cues were presented successively to examine the effect of switching the focus of attention. We observed benefits of both the first and second cues in sequential cueing, indicating that participants were able to reorient attention from one location to another within VWM, and the reallocation of attention did not attenuate memory at the first cued location. In Experiment 3, we found that reducing the validity of the preceding spatial cue did lead to a significant reduction in its benefit. However, performance at the first-cued location was still better than the neutral baseline or performance at the uncued locations, indicating that the first cue benefit might have been preserved both partially under automatic control and partially under voluntary control. Our findings revealed new properties of dynamic attentional control in VWM maintenance.
Inference of asynchronous Boolean network from biological pathways.
Das, Haimabati; Layek, Ritwik Kumar
2015-01-01
Gene regulation is a complex process with multiple levels of interactions. In order to describe this complex dynamical system with tractable parameterization, the choice of the dynamical system model is of paramount importance. The right abstraction of the modeling scheme can reduce the complexity in the inference and intervention design, both computationally and experimentally. This article proposes an asynchronous Boolean network framework to capture the transcriptional regulation as well as the protein-protein interactions in a genetic regulatory system. The inference of asynchronous Boolean network from biological pathways information and experimental evidence are explained using an algorithm. The suitability of this paradigm for the variability of several reaction rates is also discussed. This methodology and model selection open up new research challenges in understanding gene-protein interactive system in a coherent way and can be beneficial for designing effective therapeutic intervention strategy.
Channel Estimation And Multiuser Detection In Asynchronous Satellite Communications
Chaouech, Helmi; 10.5121/ijwmn.2010.2411
2010-01-01
In this paper, we propose a new method of channel estimation for asynchronous additive white Gaussian noise channels in satellite communications. This method is based on signals correlation and multiuser interference cancellation which adopts a successive structure. Propagation delays and signals amplitudes are jointly estimated in order to be used for data detection at the receiver. As, a multiuser detector, a single stage successive interference cancellation (SIC) architecture is analyzed and integrated to the channel estimation technique and the whole system is evaluated. The satellite access method adopted is the direct sequence code division multiple access (DS CDMA) one. To evaluate the channel estimation and the detection technique, we have simulated a satellite uplink with an asynchronous multiuser access.
Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
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Soundous Chairat
2017-05-01
Full Text Available This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI technology at 0.6 V and a 1.1 ns/bit latency per stage.
Diversity Multiplexing Tradeoff of Asynchronous Cooperative Relay Networks
Krishnakumar, R N; Kumar, P Vijay
2008-01-01
The assumption of nodes in a cooperative communication relay network operating in synchronous fashion is often unrealistic. In the present paper, we consider two different models of asynchronous operation in cooperative-diversity networks experiencing slow fading and examine the corresponding diversity-multiplexing tradeoffs (DMT). For both models, we propose protocols and distributed space-time codes that asymptotically achieve the transmit diversity bound for all multiplexing gains and for any number of relays.
Asynchronous Transfer Mode (ATM) Switch Technology and Vendor Survey
Berry, Noemi
1995-01-01
Asynchronous Transfer Mode (ATM) switch and software features are described and compared in order to make switch comparisons meaningful. An ATM switch's performance cannot be measured solely based on its claimed switching capacity; traffic management and congestion control are emerging as the determining factors in an ATM network's ultimate throughput. Non-switch ATM products and experiences with actual installations of ATM networks are described. A compilation of select vendor offerings as of October 1994 is provided in chart form.
IDENTIFICATION AND CONTROL OF AN ASYNCHRONOUS MACHINE USING NEURAL NETWORKS
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A ZERGAOUI
2000-06-01
Full Text Available In this work, we present the application of artificial neural networks to the identification and control of the asynchronous motor, which is a complex nonlinear system with variable internal dynamics. We show that neural networks can be applied to control the stator currents of the induction motor. The results of the different simulations are presented to evaluate the performance of the neural controller proposed.
Synthèse automatique de circuits asynchrones QDI
DINH DUC, Anh Vu
2003-01-01
ISBN 2-84813-010-5; Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). Since many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the current lack of design methods and associated tools prevents them from being widely spread. This dissertation deals with a new design methodology for quasi-dela...
PersisDroid: Android Performance Diagnosis via Anatomizing Asynchronous Executions
Kang, Yu; Zhou, Yangfan; Xu, Hui; Lyu, Michael R.
2015-01-01
Android applications (apps) grow dramatically in recent years. Apps are user interface (UI) centric typically. Rapid UI responsiveness is key consideration to app developers. However, we still lack a handy tool for profiling app performance so as to diagnose performance problems. This paper presents PersisDroid, a tool specifically designed for this task. The key notion of PersisDroid is that the UI-triggered asynchronous executions also contribute to the UI performance, and hence its perform...
Marine Forces Reserve: Accelerating Knowledge Flow through Asynchronous Learning Technologies
2014-12-19
pedagogic techniques that are infeasible in the classroom , and they suggest that in some respects technologically intermediated learning can be even better...frameworks and technologies to examine I-I knowledge flows, and from the practitioner perspective, we bring to bear deep inside knowledge of the focal...ASYNCHRONOUS LEARNING TECHNOLOGIES by Mark Nissen, Robert McGuiness and Anthony Davis December 2014 Further distribution of all or part of this
Pipelined asynchronous time-division multiplexing optical bus
Zheng, S. Q.; Li, Yueming
1997-12-01
We propose a pipelined asynchronous time-division multiplexing optical bus. Such a bus can use one of two hardwared priority schemes: the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performance of the proposed bus is significantly better than the performances of known pipelined synchronous time-division multiplexing optical buses. The possibilities of using our buses to construct multichannel switches and multidimensional processor arrays are also discussed.
Financial Data Modeling by Using Asynchronous Parallel Evolutionary Algorithms
Institute of Scientific and Technical Information of China (English)
Wang Chun; Li Qiao-yun
2003-01-01
In this paper, the high-level knowledge of financial data modeled by ordinary differential equations (ODEs) is discovered in dynamic data by using an asynchronous parallel evolutionary modeling algorithm (APHEMA). A numerical example of Nasdaq index analysis is used to demonstrate the potential of APHEMA. The results show that the dynamic models automatically discovered in dynamic data by computer can be used to predict the financial trends.
Sequential operators in computability logic
Japaridze, Giorgi
2007-01-01
Computability logic (CL) (see http://www.cis.upenn.edu/~giorgi/cl.html) is a semantical platform and research program for redeveloping logic as a formal theory of computability, as opposed to the formal theory of truth which it has more traditionally been. Formulas in CL stand for (interactive) computational problems, understood as games between a machine and its environment; logical operators represent operations on such entities; and "truth" is understood as existence of an effective solution, i.e., of an algorithmic winning strategy. The formalism of CL is open-ended, and may undergo series of extensions as the study of the subject advances. The main groups of operators on which CL has been focused so far are the parallel, choice, branching, and blind operators. The present paper introduces a new important group of operators, called sequential. The latter come in the form of sequential conjunction and disjunction, sequential quantifiers, and sequential recurrences. As the name may suggest, the algorithmic ...
Data Collection for Mobile Group Consumption: An Asynchronous Distributed Approach.
Zhu, Weiping; Chen, Weiran; Hu, Zhejie; Li, Zuoyou; Liang, Yue; Chen, Jiaojiao
2016-04-06
Mobile group consumption refers to consumption by a group of people, such as a couple, a family, colleagues and friends, based on mobile communications. It differs from consumption only involving individuals, because of the complex relations among group members. Existing data collection systems for mobile group consumption are centralized, which has the disadvantages of being a performance bottleneck, having single-point failure and increasing business and security risks. Moreover, these data collection systems are based on a synchronized clock, which is often unrealistic because of hardware constraints, privacy concerns or synchronization cost. In this paper, we propose the first asynchronous distributed approach to collecting data generated by mobile group consumption. We formally built a system model thereof based on asynchronous distributed communication. We then designed a simulation system for the model for which we propose a three-layer solution framework. After that, we describe how to detect the causality relation of two/three gathering events that happened in the system based on the collected data. Various definitions of causality relations based on asynchronous distributed communication are supported. Extensive simulation results show that the proposed approach is effective for data collection relating to mobile group consumption.
Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition.
Marisa, T; Niederhauser, T; Haeberlin, A; Wildhaber, R A; Vogel, R; Goette, J; Jacomet, M
2017-02-07
A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm(2) and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.
Asynchronous signal-dependent non-uniform sampler
Can-Cimino, Azime; Chaparro, Luis F.; Sejdić, Ervin
2014-05-01
Analog sparse signals resulting from biomedical and sensing network applications are typically non-stationary with frequency-varying spectra. By ignoring that the maximum frequency of their spectra is changing, uniform sampling of sparse signals collects unnecessary samples in quiescent segments of the signal. A more appropriate sampling approach would be signal-dependent. Moreover, in many of these applications power consumption and analog processing are issues of great importance that need to be considered. In this paper we present a signal dependent non-uniform sampler that uses a Modified Asynchronous Sigma Delta Modulator which consumes low-power and can be processed using analog procedures. Using Prolate Spheroidal Wave Functions (PSWF) interpolation of the original signal is performed, thus giving an asynchronous analog to digital and digital to analog conversion. Stable solutions are obtained by using modulated PSWFs functions. The advantage of the adapted asynchronous sampler is that range of frequencies of the sparse signal is taken into account avoiding aliasing. Moreover, it requires saving only the zero-crossing times of the non-uniform samples, or their differences, and the reconstruction can be done using their quantized values and a PSWF-based interpolation. The range of frequencies analyzed can be changed and the sampler can be implemented as a bank of filters for unknown range of frequencies. The performance of the proposed algorithm is illustrated with an electroencephalogram (EEG) signal.
Asynchronous Stoichiometric Response in Lithium Iron Phosphate Batteries
Energy Technology Data Exchange (ETDEWEB)
Paxton, William A. [State Univ. of New Jersey, Piscataway, NJ (United States); Akdogan, E. Koray [State Univ. of New Jersey, Piscataway, NJ (United States); Savkliyidiz, Ilyas [State Univ. of New Jersey, Piscataway, NJ (United States); Choksi, Ankur U. [State Univ. of New Jersey, Piscataway, NJ (United States); Silver, Scott X. [State Univ. of New Jersey, Piscataway, NJ (United States); Tsakalokos, Thomas [State Univ. of New Jersey, Piscataway, NJ (United States); Zhong, Zhong [Brookhaven National Lab. (BNL), Upton, NY (United States)
2014-11-11
The operando energy-dispersive x-ray diffraction (EDXRD) was carried out on a newly formed 8 Ah lithium iron phosphate (LiFePO4) battery with the goal of elucidating the origin of asynchronous phase transformation commonly seen with in situ x-ray diffraction studies. The high-energy photons at the NSLS X17B1 beamline allow for penetration into a fully assembled battery and therefore negate any need for a specially designed in situ cell which often uses modified current collectors to minimize x-ray attenuation. Spatially-and-temporally resolved phase-mapping was conducted with a semiquantitative reference intensity ratio (RIR) analysis to estimate the relative abundance of the delithiated phase. The data show an asynchronous response in the stoichiometry versus the electrochemical profile and suggest limited diffusion in the electrode toward the end of discharge. These results confirm that the asynchronous electrode response is not just limited to specially designed cells but occurs in fully assembled cells alike. We attribute this behavior to be a consequence of performing a local measurement over a wide-area heterogeneous reaction.
A novel asynchronous access method with binary interfaces
Directory of Open Access Journals (Sweden)
Torres-Solis Jorge
2008-10-01
Full Text Available Abstract Background Traditionally synchronous access strategies require users to comply with one or more time constraints in order to communicate intent with a binary human-machine interface (e.g., mechanical, gestural or neural switches. Asynchronous access methods are preferable, but have not been used with binary interfaces in the control of devices that require more than two commands to be successfully operated. Methods We present the mathematical development and evaluation of a novel asynchronous access method that may be used to translate sporadic activations of binary interfaces into distinct outcomes for the control of devices requiring an arbitrary number of commands to be controlled. With this method, users are required to activate their interfaces only when the device under control behaves erroneously. Then, a recursive algorithm, incorporating contextual assumptions relevant to all possible outcomes, is used to obtain an informed estimate of user intention. We evaluate this method by simulating a control task requiring a series of target commands to be tracked by a model user. Results When compared to a random selection, the proposed asynchronous access method offers a significant reduction in the number of interface activations required from the user. Conclusion This novel access method offers a variety of advantages over traditionally synchronous access strategies and may be adapted to a wide variety of contexts, with primary relevance to applications involving direct object manipulation.
A Synchronous-Asynchronous Particle Swarm Optimisation Algorithm
Directory of Open Access Journals (Sweden)
Nor Azlina Ab Aziz
2014-01-01
Full Text Available In the original particle swarm optimisation (PSO algorithm, the particles’ velocities and positions are updated after the whole swarm performance is evaluated. This algorithm is also known as synchronous PSO (S-PSO. The strength of this update method is in the exploitation of the information. Asynchronous update PSO (A-PSO has been proposed as an alternative to S-PSO. A particle in A-PSO updates its velocity and position as soon as its own performance has been evaluated. Hence, particles are updated using partial information, leading to stronger exploration. In this paper, we attempt to improve PSO by merging both update methods to utilise the strengths of both methods. The proposed synchronous-asynchronous PSO (SA-PSO algorithm divides the particles into smaller groups. The best member of a group and the swarm’s best are chosen to lead the search. Members within a group are updated synchronously, while the groups themselves are asynchronously updated. Five well-known unimodal functions, four multimodal functions, and a real world optimisation problem are used to study the performance of SA-PSO, which is compared with the performances of S-PSO and A-PSO. The results are statistically analysed and show that the proposed SA-PSO has performed consistently well.
Cooperative Distributed Sequential Spectrum Sensing
S, Jithin K; Gopalarathnam, Raghav
2010-01-01
We consider cooperative spectrum sensing for cognitive radios. We develop an energy efficient detector with low detection delay using sequential hypothesis testing. Sequential Probability Ratio Test (SPRT) is used at both the local nodes and the fusion center. We also analyse the performance of this algorithm and compare with the simulations. Modelling uncertainties in the distribution parameters are considered. Slow fading with and without perfect channel state information at the cognitive radios is taken into account.
Complementary sequential measurements generate entanglement
Coles, Patrick J.; Piani, Marco
2013-01-01
We present a new paradigm for capturing the complementarity of two observables. It is based on the entanglement created by the interaction between the system observed and the two measurement devices used to measure the observables sequentially. Our main result is a lower bound on this entanglement and resembles well-known entropic uncertainty relations. Besides its fundamental interest, this result directly bounds the effectiveness of sequential bipartite operations---corresponding to the mea...
Sequentially pulsed traveling wave accelerator
Caporaso, George J.; Nelson, Scott D.; Poole, Brian R.
2009-08-18
A sequentially pulsed traveling wave compact accelerator having two or more pulse forming lines each with a switch for producing a short acceleration pulse along a short length of a beam tube, and a trigger mechanism for sequentially triggering the switches so that a traveling axial electric field is produced along the beam tube in synchronism with an axially traversing pulsed beam of charged particles to serially impart energy to the particle beam.
View Dependent Sequential Point Trees
Institute of Scientific and Technical Information of China (English)
Wen-Cheng Wang; Feng Wei; En-Hua Wu
2006-01-01
Sequential point trees provide the state-of-the-art technique for rendering point models, by re-arranging hierarchical points sequentially according to geometric errors running on GPU for fast rendering. This paper presents a view dependent method to augment sequential point trees by embedding the hierarchical tree structures in the sequential list of hierarchical points. By the method, two kinds of indices are constructed to facilitate the points rendering in an order mostly from near to far and from coarse to fine. As a result, invisible points can be culled view-dependently in high efficiency for hardware acceleration, and at the same time, the advantage of sequential point trees could be still fully taken. Therefore, the new method can run much faster than the conventional sequential point trees, and the acceleration can be highly promoted particularly when the objects possess complex occlusion relationship and viewed closely because invisible points would be in a high percentage of the points at finer levels.
Juswardy, Budi; Xiao, Feng; Alameh, Kamal
2009-03-16
This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.
Directory of Open Access Journals (Sweden)
Md Mobarok Hossain Rubel
2016-07-01
Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.
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Miss. Rachana R. Patil
2015-01-01
Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology
Buxton, Eric C
2014-02-12
To evaluate and compare pharmacists' satisfaction with the content and learning environment of a continuing education program series offered as either synchronous or asynchronous webinars. An 8-lecture series of online presentations on the topic of new drug therapies was offered to pharmacists in synchronous and asynchronous webinar formats. Participants completed a 50-question online survey at the end of the program series to evaluate their perceptions of the distance learning experience. Eighty-two participants completed the survey instrument (41 participants from the live webinar series and 41 participants from the asynchronous webinar series.) Responses indicated that while both groups were satisfied with the program content, the asynchronous group showed greater satisfaction with many aspects of the learning environment. The synchronous and asynchronous webinar participants responded positively regarding the quality of the programming and the method of delivery, but asynchronous participants rated their experience more positively overall.
2014-01-01
Objective. To evaluate and compare pharmacists’ satisfaction with the content and learning environment of a continuing education program series offered as either synchronous or asynchronous webinars. Methods. An 8-lecture series of online presentations on the topic of new drug therapies was offered to pharmacists in synchronous and asynchronous webinar formats. Participants completed a 50-question online survey at the end of the program series to evaluate their perceptions of the distance learning experience. Results. Eighty-two participants completed the survey instrument (41 participants from the live webinar series and 41 participants from the asynchronous webinar series.) Responses indicated that while both groups were satisfied with the program content, the asynchronous group showed greater satisfaction with many aspects of the learning environment. Conclusion. The synchronous and asynchronous webinar participants responded positively regarding the quality of the programming and the method of delivery, but asynchronous participants rated their experience more positively overall. PMID:24558276
ON THE ISSUE OF VECTOR CONTROL OF THE ASYNCHRONOUS MOTORS
Directory of Open Access Journals (Sweden)
B. I. Firago
2015-01-01
Full Text Available The paper considers the issue of one of the widespread types of vector control realization for the asynchronous motors with a short-circuited rotor. Of all more than 20 vector control types known presently, the following are applied most frequently: direct vector control with velocity pickup (VP, direct vector control without VP, indirect vector control with VP and indirect vector control without VP. Despite the fact that the asynchronous-motor indirect vector control without VP is the easiest and most spread, the absence of VP does not allow controlling the motor electromagnetic torque at zero velocity. This is the reason why for electric motor drives of such requirements they utilize the vector control with a velocity transducer. The systems of widest dissemination became the direct and indirect vector control systems with X-axis alignment of the synchronously rotating x–y-coordinate frame along the rotor flux-linkage vector inasmuch as this provides the simplest correlations for controlling variables. Although these two types of vector control are well presented in literature, a number of issues concerning their realization and practical application require further elaboration. These include: the block schemes adequate representation as consisted with the modern realization of vector control and clarification of the analytical expressions for evaluating the regulator parameters.The authors present a technique for evaluating the dynamics of an asynchronous electric motor drive with direct vector control and x-axis alignment along the vector of rotor flux linkage. The article offers a generalized structure of this vector control type with detailed description of its principal blocks: controlling system, frequency converter, and the asynchronous motor.The paper presents a direct vector control simulating model developed in the MatLab environment on the grounds of this structure. The authors illustrate the described technique with the results
Institute of Scientific and Technical Information of China (English)
XIONG ChengYi; TIAN JinWen; LIU Jian
2008-01-01
This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding (BPC) in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and par-allel & pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture (PA) was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture (HA) was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an N×N code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and ex-perimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alter-natives for low power applications.
VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network
Hsieh, Hung-Yi; Tang, Kea-Tiong
2011-11-01
This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.
Fey, D; Kasche, B; Burkert, C; Tschäche, O
1998-01-10
A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.
VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders
Directory of Open Access Journals (Sweden)
Georgios Passas
2012-01-01
Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.
New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Directory of Open Access Journals (Sweden)
M. V. Atre
1995-07-01
Full Text Available A new algorithm for test-vector-generation (TVG for combinational circuits has been presented for testing VLSI chips. This is done by defining a suitable metric or distance, in the space of all input vectors, between a vector and a set of vectors. The test vectors are generated by suitably maximising the above distance. Two different methods of maximising the distance are suggested. Performances of the two methods for different circuits are presented and compared with the random method of TVG. It was observed that method B is superior to the other two methods. Also, method A is slightly better than method R.
Spike-based VLSI modeling of the ILD system in the echolocating bat.
Horiuchi, T; Hynna, K
2001-01-01
The azimuthal localization of objects by echolocating bats is based on the difference of echo intensity received at the two ears, known as the interaural level difference (ILD). Mimicking the neural circuitry in the bat associated with the computation of ILD, we have constructed a spike-based VLSI model that can produce responses similar to those seen in the lateral superior olive (LSO) and some parts of the inferior colliculus (IC). We further explore some of the interesting computational consequences of the dynamics of both synapses and cellular mechanisms.
Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.
Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert
2004-01-01
Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.
VLSI (Very Large Scale Integration) Design Tools, Reference Manual, Release 3.0.
1985-08-01
purpose of the Consortium is to advance the state of the art in VLSI technology and to transfer this technology between industry and the university...it is passed to Lyra with the -r switch to indicate a specific ruleset. Otherwise, the current technology is used as the ruleset. sacro < character...symbols art aligned so that the symbolic point n1 on the top of si is adjacent to the symbolic point n2 on the bottom of s2. Both points are taken to be
Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.
1984-10-01
analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI
VLSI Structure for an All Digital Receiver for CDMA PABX Handset
Institute of Scientific and Technical Information of China (English)
ZhouShidong; BiGuangguo
1995-01-01
In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.
Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
Directory of Open Access Journals (Sweden)
Ankush S. Patharkar
2014-07-01
Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.
Energy Technology Data Exchange (ETDEWEB)
Pin, F.G.; Pattay, R.S.
1991-01-01
Two types of computer boards including custom-designed VLSI chips have been developed to provide a qualitative reasoning capability for the real-time control of autonomous mobile robots. The design and operation of these boards are described and an example of application of qualitative reasoning for the autonomous navigation of a mobile robot in a-priori unknown environments is presented. Results concerning consistency and modularity in the development of qualitative reasoning schemes as well as the general applicability of these techniques to robotic control domains are also discussed. 17 refs., 4 figs.
Vlsi implementation of flexible architecture for decision tree classification in data mining
Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak
2017-07-01
The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.
编码系统研究及VLSI实现%A Study of JPEG2000 Encoding System and Its VLSI Implementation
Institute of Scientific and Technical Information of China (English)
马涛; 汶德胜
2009-01-01
A system architecture and its VLSI implementation for JPEG2000 were presented. Parallel coding architecture based on wavelet sub-band was introduced in the system. Simplified logic and parallel processing were adopted to optimize arithmetic for JPEG2000 standard, such as 2-line-parallelling 9/7 lifting discrete wavelet transform, strip-paralleling bit plane coding, compacted interval update and parallel renormalization for binary arithmetic coding, etc. All modules are pipelined manner. Especially, asynchronous pipelining implementation was adopted in the BPC and BAC to distribute execution time dynamically. The speed ratio was tested close to pipeline segment 3. Original image is imported by the image data generating board, and the compressed data is send into PC to be truncated and decoded by software. The average difference of PSNR between LuraWave and the proposed system is below 0.8dB, which shows the validity of the improved arithmetic. The input pixel clock can reach to 20MHz.%提出了一种JPEG2000编码系统结构和VLSI方案.该方案以小波子带为单位,多套并行处理.对JPEG2000标准中各个模块的算法进行了逻辑化简、并行编码等优化.如采用双行并行9/7提升小波分解,条带并行的比特平面编码,简化区间更新和并行归一化算术编码等.各模块均以流水线方式工作,其中的比特平面编码和算术编码采用异步流水线方式动态分配执行时间,加速比均接近于流水段数3.以图像信号产生板送入原始图像,编码后送入PC机进行码流截断和解压缩.该系统在各个压缩率下的信噪比与LuraWave商用压缩软件的差距均在0.8 dB之内,可见改进后的算法可行且有效,像元时钟可达20 MHz.
The Progression of Sequential Reactions
Directory of Open Access Journals (Sweden)
Jack McGeachy
2010-01-01
Full Text Available Sequential reactions consist of linked reactions in which the product of the first reaction becomes the substrate of a second reaction. Sequential reactions occur in industrially important processes, such as the chlorination of methane. A generalized series of three sequential reactions was analyzed in order to determine the times at which each chemical species reaches its maximum. To determine the concentration of each species as a function of time, the differential rate laws for each species were solved. The solution of each gave the concentration curve of the chemical species. The concentration curves of species A1 and A2 possessed discreet maxima, which were determined through slope-analysis. The concentration curve of the final product, A3, did not possess a discreet maximum, but rather approached a finite limit.
Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2011-03-01
Full Text Available This paper present area efficient layout designs for 3.3GigaHertz (GHz Phase Locked loop (PLL withfour multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output,using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designedusing 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulatingan integrated circuit at physical description level. The main novelties related to the 45 nm technology arethe high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate lengthrequired for 45 nm technology is 25nm. Low Power (0.211miliwatt phase locked loop with four multipleoutputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHzrespectively is obtained using 45 nm VLSI technology.
Schreiter, Juerg; Ramacher, Ulrich; Heittmann, Arne; Matolin, Daniel; Schuffny, Rene
2004-05-01
We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.
Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.
Yu, Theodore; Cauwenberghs, Gert
2010-06-01
We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.
On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
Lin, Meng-Chun; Dung, Lan-Rong
2008-02-01
This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.
Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.
Mitra, S; Fusi, S; Indiveri, G
2009-02-01
Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated.
Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing
Khachab, Nabil Ibrahim
1990-01-01
The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.
New VLSI smart sensor for collision avoidance inspired by insect vision
Abbott, Derek; Moini, Alireza; Yakovleff, Andre; Nguyen, X. Thong; Blanksby, Andrew; Kim, Gyudong; Bouzerdoum, Abdesselam; Bogner, Robert E.; Eshraghian, Kamran
1995-01-01
An analog VLSI implementation of a smart microsensor that mimics the early visual processing stage in insects is described with an emphasis on the overall concept and the front- end detection. The system employs the `smart sensor' paradigm in that the detectors and processing circuitry are integrated on the one chip. The integrated circuit is composed of sixty channels of photodetectors and parallel processing elements. The photodetection circuitry includes p-well junction diodes on a 2 micrometers CMOS process and a logarithmic compression to increase the dynamic range of the system. The future possibility of gallium arsenide implementation is discussed. The processing elements behind each photodetector contain a low frequency differentiator where subthreshold design methods have been used. The completed IC is ideal for motion detection, particularly collision avoidance tasks, as it essentially detects distance, speed & bearing of an object. The Horridge Template Model for insect vision has been directly mapped into VLSI and therefore the IC truly exploits the beauty of nature in that the insect eye is so compact with parallel processing, enabling compact motion detection without the computational overhead of intensive imaging, full image extraction and interpretation. This world-first has exciting applications in the areas of automobile anti- collision, IVHS, autonomous robot guidance, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.
VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces
Wooley, Bruce A.
1991-04-01
The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.
A multi coding technique to reduce transition activity in VLSI circuits
Vithyalakshmi, N.; Rajaram, M.
2014-02-01
Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.
The digi-neocognitron: a digital neocognitron neural network model for VLSI.
White, B A; Elmasry, M I
1992-01-01
One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.
Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology
Directory of Open Access Journals (Sweden)
Ms. Ujwala A. Belorkar
2010-06-01
Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design
VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems
Energy Technology Data Exchange (ETDEWEB)
Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)
2009-07-15
The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.
Transistor switching and sequential circuits
Sparkes, John J
1969-01-01
Transistor Switching and Sequential Circuits presents the basic ideas involved in the construction of computers, instrumentation, pulse communication systems, and automation. This book discusses the design procedure for sequential circuits. Organized into two parts encompassing eight chapters, this book begins with an overview of the ways on how to generate the types of waveforms needed in digital circuits, principally ramps, square waves, and delays. This text then considers the behavior of some simple circuits, including the inverter, the emitter follower, and the long-tailed pair. Other cha
Complementary sequential measurements generate entanglement
Coles, Patrick J.; Piani, Marco
2014-01-01
We present a paradigm for capturing the complementarity of two observables. It is based on the entanglement created by the interaction between the system observed and the two measurement devices used to measure the observables sequentially. Our main result is a lower bound on this entanglement and resembles well-known entropic uncertainty relations. Besides its fundamental interest, this result directly bounds the effectiveness of sequential bipartite operations—corresponding to the measurement interactions—for entanglement generation. We further discuss the intimate connection of our result with two primitives of information processing, namely, decoupling and coherent teleportation.
Sequential Divestiture and Firm Asymmetry
Directory of Open Access Journals (Sweden)
Wen Zhou
2013-01-01
Full Text Available Simple Cournot models of divestiture tend to generate incentives to divest which are too strong, predicting that firms will break up into an infinite number of divisions resulting in perfect competition. This paper shows that if the order of divestitures is endogenized, firms will always choose sequential, and hence very limited, divestitures. Divestitures favor the larger firm and the follower in a sequential game. Divestitures in which the larger firm is the follower generate greater industry profit and social welfare, but a smaller consumer surplus.
Asynchronous parallel generating set search for linearly-constrained optimization.
Energy Technology Data Exchange (ETDEWEB)
Kolda, Tamara G.; Griffin, Joshua; Lewis, Robert Michael
2007-04-01
We describe an asynchronous parallel derivative-free algorithm for linearly-constrained optimization. Generating set search (GSS) is the basis of ourmethod. At each iteration, a GSS algorithm computes a set of search directionsand corresponding trial points and then evaluates the objective function valueat each trial point. Asynchronous versions of the algorithm have been developedin the unconstrained and bound-constrained cases which allow the iterations tocontinue (and new trial points to be generated and evaluated) as soon as anyother trial point completes. This enables better utilization of parallel resourcesand a reduction in overall runtime, especially for problems where the objec-tive function takes minutes or hours to compute. For linearly-constrained GSS,the convergence theory requires that the set of search directions conform to the3 nearby boundary. The complexity of developing the asynchronous algorithm forthe linearly-constrained case has to do with maintaining a suitable set of searchdirections as the search progresses and is the focus of this research. We describeour implementation in detail, including how to avoid function evaluations bycaching function values and using approximate look-ups. We test our imple-mentation on every CUTEr test problem with general linear constraints and upto 1000 variables. Without tuning to individual problems, our implementationwas able to solve 95% of the test problems with 10 or fewer variables, 75%of the problems with 11-100 variables, and nearly half of the problems with100-1000 variables. To the best of our knowledge, these are the best resultsthat have ever been achieved with a derivative-free method. Our asynchronousparallel implementation is freely available as part of the APPSPACK software.4
Creating video-annotated discussions: An asynchronous alternative
Directory of Open Access Journals (Sweden)
Craig D. Howard
2010-01-01
Full Text Available In this article the authors illustrate the design and development of a pedagogical intervention using video annotations in a pre-service teacher education courrse. An annotation platform was selected and video was shot to create a video backdrop on which asynchronous discussions would take place. The article addresses design considerations in the selection of video, the editing process, and the development of a tutorial to lead learners through their first experience with this form of discussion. Learner participation samples were collected, and an analysis of the design process concludes the article.
Wind Generator Stabilization with Doubly-Fed Asynchronous Machine
Institute of Scientific and Technical Information of China (English)
WU Li; WANG Zhi-xin
2007-01-01
This paper investigates the function of doubly-fed asynchronous machine(DASM) with emphasis placed on its ability to the stabilization of the power system including wind generators. P(active power) and Q(reactive power) compensation from DASM can be regulated independently through secondary-excitation controlling. Simulation results by power system computer aided design(PSCAD) show that DASM can restore the wind-generator system to a normal operating condition rapidly even following severe transmission-line failures. Comparison studies have also been performed between wind turbine pitch control and proposed method.
Faculty development and mentorship using selected online asynchronous teaching strategies.
Vitale, Anne T
2010-12-01
The use of distance learning continues to improve accessibility to nursing education programs, yet online teaching remains an intimidating experience for novice educators. An emerging role in professional faculty development is the online educator, who serves as a mentor for novice faculty. This article presents the necessary elements to plan, organize, and manage asynchronous online courses, especially for novice educators and online faculty mentors. Course engagement and faculty-student online communication strategies are explored using examples. Threaded discussion strategies for engaging students in active, collaborative learning are discussed using specific examples. A threaded discussion grading rubric is included. Strategies to sustain interactive learning and evaluate student learning using examples are offered.
Negative circuits and sustained oscillations in asynchronous automata networks
Richard, Adrien
2009-01-01
The biologist Ren\\'e Thomas conjectured, twenty years ago, that the presence of a negative feedback circuit in the interaction graph of a dynamical system is a necessary condition for this system to produce sustained oscillations. In this paper, we state and prove this conjecture for asynchronous automata networks, a class of discrete dynamical systems extensively used to model the behaviors of gene networks. As a corollary, we obtain the following fixed point theorem: given a product $X$ of $n$ finite intervals of integers, and a map $F$ from $X$ to itself, if the interaction graph associated with $F$ has no negative circuit, then $F$ has at least one fixed point.
A wavelet approach to binary blackholes with asynchronous multitasking
Lim, Hyun; Hirschmann, Eric; Neilsen, David; Anderson, Matthew; Debuhr, Jackson; Zhang, Bo
2016-03-01
Highly accurate simulations of binary black holes and neutron stars are needed to address a variety of interesting problems in relativistic astrophysics. We present a new method for the solving the Einstein equations (BSSN formulation) using iterated interpolating wavelets. Wavelet coefficients provide a direct measure of the local approximation error for the solution and place collocation points that naturally adapt to features of the solution. Further, they exhibit exponential convergence on unevenly spaced collection points. The parallel implementation of the wavelet simulation framework presented here deviates from conventional practice in combining multi-threading with a form of message-driven computation sometimes referred to as asynchronous multitasking.
Directory of Open Access Journals (Sweden)
I.A. Tsodik
2014-04-01
Full Text Available A methodology of an asynchronous motor mathematical model synthesis is described. Experiments are suggested to be conducted in the following sequence. Geometrical models are first built in AutoCAD, then imported to Comsol Multiphysics, and further processed in Matlab with computation of coefficients and dependences applied in the asynchronous motor mathematical model.
The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core
DEFF Research Database (Denmark)
Christensen, Kåre Tais; Jensen, P.; Korger, P.
1998-01-01
This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...
The Key Implementation Technology of Client/Server's Asynchronous Communication Programs
Institute of Scientific and Technical Information of China (English)
无
2002-01-01
This paper introduces the implementation method,key technology and flowchart of Client/Server's asynchronous communication programs on Linux or Unix,and further explains a few problems to which should pay attention for improving CPU's efficiency in implementing asynchronous communication programs.
Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend
DEFF Research Database (Denmark)
Nielsen, Sune Fallgaard; Sparsø, Jens; Madsen, Jan
2009-01-01
of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. The paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware...
Using Television Sitcoms to Facilitate Asynchronous Discussions in the Online Communication Course
Tolman, Elizabeth; Asbury, Bryan
2012-01-01
Asynchronous discussions are a useful instructional resource in the online communication course. In discussion groups students have the opportunity to actively participate and interact with students and the instructor. Asynchronous communication allows for flexibility because "participants can interact with significant amounts of time between…
Optimization design of a full asynchronous pipeline circuit based on null convention logic
Energy Technology Data Exchange (ETDEWEB)
Guan Xuguang; Zhou Duan; Yang Yintang, E-mail: guanxuguang_5@126.co [Institute of Microelectronics, Xidian University, Xi' an 710071 (China)
2009-07-15
This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline. Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode. The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules. Performance penalty brought by null cycle is reduced while the data processing capacity is increased. The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-{mu}m CMOS technology. Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption. This indicates the new design proposal is preferable for high-speed asynchronous designs due to its high throughput and delay-insensitivity.
Exploring the Effect of Scripted Roles on Cognitive Presence in Asynchronous Online Discussions
Olesova, Larisa; Slavin, Margaret; Lim, Jieun
2016-01-01
The purpose of this study was to identify the effect of scripted roles on students' level of cognitive presence in asynchronous online threaded discussions. A quantitative content analysis was used to investigate: (1) what level of cognitive presence is achieved by students' assigned roles in asynchronous online discussions; (2) differences…
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
DEFF Research Database (Denmark)
Bjerregaard, Tobias; Sparsø, Jens
2005-01-01
Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in asynchronous Network-on-Chip. We present a novel scheduling discipline called Asynchronous Latency Guarantee (ALG...
Sequential triangulation of orbital photography
Rajan, M.; Junkins, J. L.; Turner, J. D.
1979-01-01
The feasibility of structuring the satellite photogrammetric triangulation as an iterative Extended Kalman estimation algorithm is demonstrated. Comparative numerical results of the sequential against batch estimation algorithm are presented. Difficulty of accurately modeling of the attitude motion is overcome by utilizing the on-board angular rate measurements. Solutions of the differential equations and the evaluation of state transition matrix are carried out numerically.
Attack Trees with Sequential Conjunction
Jhawar, Ravi; Kordy, Barbara; Mauw, Sjouke; Radomirović, Sasa; Trujillo-Rasua, Rolando
2015-01-01
We provide the first formal foundation of SAND attack trees which are a popular extension of the well-known attack trees. The SAND at- tack tree formalism increases the expressivity of attack trees by intro- ducing the sequential conjunctive operator SAND. This operator enables the modeling of
Sequential triangulation of orbital photography
Rajan, M.; Junkins, J. L.; Turner, J. D.
1979-01-01
The feasibility of structuring the satellite photogrammetric triangulation as an iterative Extended Kalman estimation algorithm is demonstrated. Comparative numerical results of the sequential against batch estimation algorithm are presented. Difficulty of accurately modeling of the attitude motion is overcome by utilizing the on-board angular rate measurements. Solutions of the differential equations and the evaluation of state transition matrix are carried out numerically.
Dynamic stability of sequential stimulus representations in adapting neuronal networks
Directory of Open Access Journals (Sweden)
Renato Carlos Farinha Duarte
2014-10-01
Full Text Available The ability to acquire and maintain appropriate representations of time-varying, sequentialstimulus events is a fundamental feature of neocortical circuits and a necessary first step towardsmore specialized information processing. The dynamical properties of such representationsdepend on the current state of the circuit, which is determined primarily by the ongoing, internallygenerated activity, setting the ground state from which input-specific transformations emerge.Here, we begin by demonstrating that timing-dependent synaptic plasticity mechanisms havean important role to play in the active maintenance of an ongoing dynamics characterized byasynchronous and irregular firing, closely resembling cortical activity in vivo. Incoming stimuli,acting as perturbations of the local balance of excitation and inhibition, require fast adaptiveresponses to prevent the development of unstable activity regimes, such as those characterizedby a high degree of population-wide synchrony. We establish a link between such pathologicalnetwork activity, which is circumvented by the action of plasticity, and a reduced computationalcapacity. Additionally, we demonstrate that the action of plasticity shapes and stabilizes thetransient network states exhibited in the presence of sequentially presented stimulus events,allowing the development of adequate and discernible stimulus representations. The mainfeature responsible for the increased discriminability of stimulus-driven population responsesin plastic networks is shown to be the decorrelating action of inhibitory plasticity and theconsequent maintenance of the asynchronous irregular dynamic regime both for ongoing activityand stimulus-driven responses, whereas excitatory plasticity is shown to play only a marginalrole.
Continuous EEG signal analysis for asynchronous BCI application.
Hsu, Wei-Yen
2011-08-01
In this study, we propose a two-stage recognition system for continuous analysis of electroencephalogram (EEG) signals. An independent component analysis (ICA) and correlation coefficient are used to automatically eliminate the electrooculography (EOG) artifacts. Based on the continuous wavelet transform (CWT) and Student's two-sample t-statistics, active segment selection then detects the location of active segment in the time-frequency domain. Next, multiresolution fractal feature vectors (MFFVs) are extracted with the proposed modified fractal dimension from wavelet data. Finally, the support vector machine (SVM) is adopted for the robust classification of MFFVs. The EEG signals are continuously analyzed in 1-s segments, and every 0.5 second moves forward to simulate asynchronous BCI works in the two-stage recognition architecture. The segment is first recognized as lifted or not in the first stage, and then is classified as left or right finger lifting at stage two if the segment is recognized as lifting in the first stage. Several statistical analyses are used to evaluate the performance of the proposed system. The results indicate that it is a promising system in the applications of asynchronous BCI work.
Algebraic Number Precoded OFDM Transmission for Asynchronous Cooperative Multirelay Networks
Directory of Open Access Journals (Sweden)
Hua Jiang
2014-01-01
Full Text Available This paper proposes a space-time block coding (STBC transmission scheme for asynchronous cooperative systems. By combination of rotated complex constellations and Hadamard transform, these constructed codes are capable of achieving full cooperative diversity with the analysis of the pairwise error probability (PEP. Due to the asynchronous characteristic of cooperative systems, orthogonal frequency division multiplexing (OFDM technique with cyclic prefix (CP is adopted for combating timing delays from relay nodes. The total transmit power across the entire network is fixed and appropriate power allocation can be implemented to optimize the network performance. The relay nodes do not require decoding and demodulation operation, resulting in a low complexity. Besides, there is no delay for forwarding the OFDM symbols to the destination node. At the destination node the received signals have the corresponding STBC structure on each subcarrier. In order to reduce the decoding complexity, the sphere decoder is implemented for fast data decoding. Bit error rate (BER performance demonstrates the effectiveness of the proposed scheme.
Asynchronously sampled blind source separation for coherent optical links
Detwiler, Thomas F.; Searcy, Steven M.; Stark, Andrew J.; Ralph, Stephen E.; Basch, Bert E.
2011-01-01
Polarization multiplexing is an integral technique for generating spectrally efficient 100 Gb/s and higher optical links. Post coherent detection DSP-based polarization demultiplexing of QPSK links is commonly performed after timing recovery. We propose and demonstrate a method of asynchronous blind source separation using the constant modulus algorithm (CMA) on the asynchronously sampled signal to initially separate energy from arbitrarily aligned polarization states. This method lends well to implementation as it allows for an open-loop sampling frequency for analog-to-digital conversion at less than twice the symbol rate. We show that the performance of subsequent receiver functions is enhanced by the initial pol demux operation. CMA singularity behavior is avoided through tap settling constraints. The method is applicable to QPSK transmissions and many other modulation formats as well, including general QAM signals, offset-QPSK, and CPM, or a combination thereof. We present the architecture and its performance under several different formats and link conditions. Comparisons of complexity and performance are drawn between the proposed architecture and conventional receivers.
Asynchronous replica exchange software for grid and heterogeneous computing
Gallicchio, Emilio; Xia, Junchao; Flynn, William F.; Zhang, Baofeng; Samlalsingh, Sade; Mentes, Ahmet; Levy, Ronald M.
2015-11-01
Parallel replica exchange sampling is an extended ensemble technique often used to accelerate the exploration of the conformational ensemble of atomistic molecular simulations of chemical systems. Inter-process communication and coordination requirements have historically discouraged the deployment of replica exchange on distributed and heterogeneous resources. Here we describe the architecture of a software (named ASyncRE) for performing asynchronous replica exchange molecular simulations on volunteered computing grids and heterogeneous high performance clusters. The asynchronous replica exchange algorithm on which the software is based avoids centralized synchronization steps and the need for direct communication between remote processes. It allows molecular dynamics threads to progress at different rates and enables parameter exchanges among arbitrary sets of replicas independently from other replicas. ASyncRE is written in Python following a modular design conducive to extensions to various replica exchange schemes and molecular dynamics engines. Applications of the software for the modeling of association equilibria of supramolecular and macromolecular complexes on BOINC campus computational grids and on the CPU/MIC heterogeneous hardware of the XSEDE Stampede supercomputer are illustrated. They show the ability of ASyncRE to utilize large grids of desktop computers running the Windows, MacOS, and/or Linux operating systems as well as collections of high performance heterogeneous hardware devices.
An Asynchronous IEEE Floating-Point Arithmetic Unit
Directory of Open Access Journals (Sweden)
Joel R. Noche
2007-12-01
Full Text Available An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor and DCVS (differentialcascode voltage switch logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath.
Asynchronous Replica Exchange Software for Grid and Heterogeneous Computing
Gallicchio, Emilio; Xia, Junchao; Flynn, William F.; Zhang, Baofeng; Samlalsingh, Sade; Mentes, Ahmet; Levy, Ronald M.
2015-01-01
Parallel replica exchange sampling is an extended ensemble technique often used to accelerate the exploration of the conformational ensemble of atomistic molecular simulations of chemical systems. Inter-process communication and coordination requirements have historically discouraged the deployment of replica exchange on distributed and heterogeneous resources. Here we describe the architecture of a software (named ASyncRE) for performing asynchronous replica exchange molecular simulations on volunteered computing grids and heterogeneous high performance clusters. The asynchronous replica exchange algorithm on which the software is based avoids centralized synchronization steps and the need for direct communication between remote processes. It allows molecular dynamics threads to progress at different rates and enables parameter exchanges among arbitrary sets of replicas independently from other replicas. ASyncRE is written in Python following a modular design conducive to extensions to various replica exchange schemes and molecular dynamics engines. Applications of the software for the modeling of association equilibria of supramolecular and macromolecular complexes on BOINC campus computational grids and on the CPU/MIC heterogeneous hardware of the XSEDE Stampede supercomputer are illustrated. They show the ability of ASyncRE to utilize large grids of desktop computers running the Windows, MacOS, and/or Linux operating systems as well as collections of high performance heterogeneous hardware devices. PMID:27103749
Fast asynchronous updating algorithms for k-shell indices
Lee, Yan-Li; Zhou, Tao
2017-09-01
Identifying influential nodes in networks is a significant and challenging task. Among many centrality indices, the k-shell index performs very well in finding out influential spreaders. However, the traditional method for calculating the k-shell indices of nodes needs the global topological information, which limits its applications in large-scale dynamically growing networks. Recently, Lü et al. [Nature Commun. 7 (2016) 10168] proposed a novel asynchronous algorithm to calculate the k-shell indices, which is suitable to deal with large-scale growing networks. In this paper, we propose two algorithms to select nodes and update their intermediate values towards the k-shell indices, which can help in accelerating the convergence of the calculation of k-shell indices. The former algorithm takes into account the degrees of nodes while the latter algorithm prefers to choose the node whose neighbors' values have been changed recently. We test these two methods on four real networks and four artificial networks. The results suggest that the two algorithms can respectively reduce the convergence time up to 75.4% and 92.9% in average, compared with the original asynchronous updating algorithm.
Formation of the wide asynchronous binary asteroid population
Energy Technology Data Exchange (ETDEWEB)
Jacobson, Seth A. [Department of Astrophysical and Planetary Science, UCB 391, University of Colorado, Boulder, CO 80309 (United States); Scheeres, Daniel J.; McMahon, Jay [Department of Aerospace Engineering Sciences, UCB 429, University of Colorado, Boulder, CO 80309 (United States)
2014-01-01
We propose and analyze a new mechanism for the formation of the wide asynchronous binary population. These binary asteroids have wide semimajor axes relative to most near-Earth and main belt asteroid systems. Confirmed members have rapidly rotating primaries and satellites that are not tidally locked. Previously suggested formation mechanisms from impact ejecta, from planetary flybys, and directly from rotational fission events cannot satisfy all of the observations. The newly hypothesized mechanism works as follows: (1) these systems are formed from rotational fission, (2) their satellites are tidally locked, (3) their orbits are expanded by the binary Yarkovsky-O'Keefe-Radzievskii-Paddack (BYORP) effect, (4) their satellites desynchronize as a result of the adiabatic invariance between the libration of the secondary and the mutual orbit, and (5) the secondary avoids resynchronization because of the YORP effect. This seemingly complex chain of events is a natural pathway for binaries with satellites that have particular shapes, which define the BYORP effect torque that acts on the system. After detailing the theory, we analyze each of the wide asynchronous binary members and candidates to assess their most likely formation mechanism. Finally, we suggest possible future observations to check and constrain our hypothesis.
Designing Parallel Bus Using Universal Asynchronous Receiver Transmitter
Directory of Open Access Journals (Sweden)
Satyandra Sharad
2013-04-01
Full Text Available This paper entitled “DESIGNING PARALLEL BUSUSING UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER” is designed to the core of a UART interface module, which includes both receive and transmit modules, and the command parser. This paper will be a viable solution to design parallel buses with the help of UART. In the test bench , there is a RFM(register file model to which we write/read back data from just to check our design .The txt file issues serial inputs to the core and the core outputs parallel data and address in the form of bus. This bus is connected to our RFM (register file model instantiated in the test bench along with the design. This makes easy to retrieve parallel data from serial input. The base of the paper is to use microcontroller along with other components to interface with the physical world. In contrast, most serial communication must first be converted back into parallel form by a universal asynchronous receiver/transmitter (UART before they may be directly connected to a data bus. Both Transmissions (Parallel and Serial are used to connect peripheral devices and enable us to communicate with these devices. The UART core described here is designed using VHDL and implemented on Xilinx Vertex FPGA.
Asynchronous Code-Division Random Access Using Convex Optimization
Applebaum, Lorne; Duarte, Marco F; Calderbank, Robert
2011-01-01
Many applications in cellular systems and sensor networks involve a random subset of a large number of users asynchronously reporting activity to a base station. This paper examines the problem of multiuser detection (MUD) in random access channels for such applications. Traditional orthogonal signaling ignores the random nature of user activity in this problem and limits the total number of users to be on the order of the number of signal space dimensions. Contention-based schemes, on the other hand, suffer from delays caused by colliding transmissions and the hidden node problem. In contrast, this paper presents a novel asynchronous (non-orthogonal) code-division random access scheme along with a convex optimization-based MUD algorithm that overcomes the issues associated with orthogonal signaling and contention-based methods. Two key distinguishing features of the proposed algorithm are that it does not require knowledge of the delay or channel state information of every user and it has polynomial-time com...
Asynchronous glaciation at Nanga Parbat, northwestern Himalaya Mountains, Pakistan
Phillips, William M.; Sloan, Valerie F.; Shroder, John F., Jr.; Sharma, Pankaj; Clarke, Michèle L.; Rendell, Helen M.
2000-05-01
We present a new glacial chronology demonstrating asynchroneity between advances of Himalayan glaciers and Northern Hemisphere ice-sheet volumes. Glaciers at Nanga Parbat expanded during the early to middle Holocene ca. 9.0 5.5 ka. No major advances at Nanga Parbat during the last global glacial stage of marine oxygen isotope stage 2 (MIS-2) between 24 and 11 ka were identified. Preliminary evidence also indicates advances between ca. 60 and 30 ka. These periods of high ice volume coincide with warm, wet regional climates dominated by a strong southwest Asian summer monsoon. The general lack of deposits dating from MIS-2 suggests that Nanga Parbat was too arid to support expanded ice during this period of low monsoon intensity. Advances during warm, wet periods are possible for the high-altitude summer accumulation glaciers typical of the Himalayas, and explain asynchronous behavior. However, the Holocene advances at Nanga Parbat appear to have been forced by an abrupt drop in temperature ca. 8.4 8.0 ka and an increase in winter precipitation ca. 7 5.5 ka. These results highlight the overall sensitivity of Himalayan glaciation to orbital forcing of monsoon intensity, and on millennial or shorter time scales, to changes in North Atlantic circulation.
Spatiotemporal Features for Asynchronous Event-based Data
Directory of Open Access Journals (Sweden)
Xavier eLagorce
2015-02-01
Full Text Available Bio-inspired asynchronous event-based vision sensors are currently introducing a paradigm shift in visual information processing. These new sensors rely on a stimulus-driven principle of light acquisition similar to biological retinas. They are event-driven and fully asynchronous, thereby reducing redundancy and encoding exact times of input signal changes, leading to a very precise temporal resolution. Approaches for higher-level computer vision often rely on the realiable detection of features in visual frames, but similar definitions of features for the novel dynamic and event-based visual input representation of silicon retinas have so far been lacking. This article addresses the problem of learning and recognizing features for event-based vision sensors, which capture properties of truly spatiotemporal volumes of sparse visual event information. A novel computational architecture for learning and encoding spatiotemporal features is introduced based on a set of predictive recurrent reservoir networks, competing via winner-take-all selection. Features are learned in an unsupervised manner from real-world input recorded with event-based vision sensors. It is shown that the networks in the architecture learn distinct and task-specific dynamic visual features, and can predict their trajectories over time.
Asynchronous Task-Based Polar Decomposition on Manycore Architectures
Sukkari, Dalal
2016-10-25
This paper introduces the first asynchronous, task-based implementation of the polar decomposition on manycore architectures. Based on a new formulation of the iterative QR dynamically-weighted Halley algorithm (QDWH) for the calculation of the polar decomposition, the proposed implementation replaces the original and hostile LU factorization for the condition number estimator by the more adequate QR factorization to enable software portability across various architectures. Relying on fine-grained computations, the novel task-based implementation is also capable of taking advantage of the identity structure of the matrix involved during the QDWH iterations, which decreases the overall algorithmic complexity. Furthermore, the artifactual synchronization points have been severely weakened compared to previous implementations, unveiling look-ahead opportunities for better hardware occupancy. The overall QDWH-based polar decomposition can then be represented as a directed acyclic graph (DAG), where nodes represent computational tasks and edges define the inter-task data dependencies. The StarPU dynamic runtime system is employed to traverse the DAG, to track the various data dependencies and to asynchronously schedule the computational tasks on the underlying hardware resources, resulting in an out-of-order task scheduling. Benchmarking experiments show significant improvements against existing state-of-the-art high performance implementations (i.e., Intel MKL and Elemental) for the polar decomposition on latest shared-memory vendors\\' systems (i.e., Intel Haswell/Broadwell/Knights Landing, NVIDIA K80/P100 GPUs and IBM Power8), while maintaining high numerical accuracy.
Asynchronous API Pattern and its Application%异步接口模式及其应用
Institute of Scientific and Technical Information of China (English)
何华海; 丁柯
2002-01-01
In distributed systems,high efficiency can be achieved using asynchronous API between client and server.This paper provides an architectural pattern that implements asynchronous API generally. Asynchronous methods donot execute operations directly,however,they delegate the sending and receiving process to individual threads via aqueue ,the client deals with results by means of callback ,wait or check. Synchronous API is implemented on the baseof asynchronous API. Presently the asynchronous API pattern has been employed in the implementation of messagequeue middleware ISMQ.
A Parallel-based Lifting Algorithm and VLSI Architecture for DWT
Institute of Scientific and Technical Information of China (English)
无
2006-01-01
A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
Yang, Yuning; Kamboh, Awais M; Mason, Andrew J
2014-04-30
This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces.
Hoang, Linh; Yang, Zhi; Liu, Wentai
2009-01-01
An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.
A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI.
Mill, R; Sheik, S; Indiveri, G; Denham, S L
2011-10-01
Stimulus-specific adaptation (SSA) is a phenomenon observed in neural systems which occurs when the spike count elicited in a single neuron decreases with repetitions of the same stimulus, and recovers when a different stimulus is presented. SSA therefore effectively highlights rare events in stimulus sequences, and suppresses responses to repetitive ones. In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI). The hardware system is evaluated using biologically realistic spike trains with parameters chosen to reflect those of the stimuli used in physiological experiments. We examine the effect of input parameters and stimulus history upon SSA and show that the trends apparent in the results obtained in silico compare favorably with those observed in biological neurons.
VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.
Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V
2007-03-01
A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.
Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En
2015-08-13
A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.
Knowledge-based synthesis of custom VLSI physical design tools: First steps
Setliff, Dorothy E.; Rutenbar, Rob A.
A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
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V.Sri Sai Harsha
2015-09-01
Full Text Available There is an increasing demand for portable devices powered up by battery, this led the manufacturers of semiconductor technology to scale down the feature size which results in reduction in threshold voltage and enables the complex functionality on a single chip. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be able to choose required and apt leakage reduction technique.
Cirio, R.; Bourhaleb, F.; Degiorgis, P. G.; Donetti, M.; Marchetto, F.; Marletti, M.; Mazza, G.; Peroni, C.; Rizzi, E.; SanzFreire, C.
2002-04-01
A VLSI chip based on a recycling integrator has been designed and built to be used as front-end readout of detectors for dosimetry and beam monitoring. The chip is suitable for measurements with both conventional radiotherapy accelerators (photon or electron beams) and with hadron accelerators (proton or light ion beams). As the chips might be located at few centimeters from the irradiation area and they are meant to be used in routine hospital practice, it is mandatory to assert their damage to both electromagnetic and neutron irradiation. We have tested a few chips on a X-ray beam and on thermal and fast neutron beams. Results of the tests are reported and an estimate of the expected lifetime of the chip for routine use is given.
An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm
Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit
2016-09-01
The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.
VLSI design of 3D display processing chip for binocular stereo displays
Institute of Scientific and Technical Information of China (English)
Ge Chenyang; Zheng Nanning
2010-01-01
In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.
Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
Directory of Open Access Journals (Sweden)
HOO, C.-S.
2013-02-01
Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
P.A.HarshaVardhini
2012-04-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips
Directory of Open Access Journals (Sweden)
M.Madhavi Latha
2012-05-01
Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation
Massengill, Lloyd W.
1991-03-01
A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.
Real-time motion detection using an analog VLSI zero-crossing chip
Bair, Wyeth; Koch, Christof
1991-07-01
The authors have designed and tested a one-dimensional 64 pixel, analog CMOS VLSI chip which localizes intensity edges in real-time. This device exploits on-chip photoreceptors and the natural filtering properties of resistive networks to implement a scheme similar to and motivated by the Difference of Gaussians (DOG) operator proposed by Marr and Hildreth (1980). The chip computes the zero-crossings associated with the difference of two exponential weighting functions and reports only those zero-crossings at which the derivative is above an adjustable threshold. A real-time motion detection system based on the zero- crossing chip and a conventional microprocessor provides linear velocity output over two orders of magnitude of light intensity and target velocity.
VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Li, Kang; Yu, Juebang; Li, Jian
In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.
A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT
Liu, Kai; Li, YunSong; Belyaev, Eugeniy
2010-08-01
The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA
Directory of Open Access Journals (Sweden)
Nishi Pandey
2015-10-01
Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family
Analyzing VLSI component test results of a GenRad GR125 tester
Zulaica, D.; Lee, C.-H.
1995-06-01
The GenRad GR125 VLSI chip tester provides tools for testing the functionality of entire chips. Test operation results, such as timing sensitivity or propagation delay, can be compared to published values of other manufacturers' chips. The tool options allow for many input vector situations to be tested, leaving the possibility that a certain test result has no meaning. Thus, the test operations are also analyzed for intent. Automating the analysis of test results can speed up the testing process and prepare results for processing by other tools. The procedure used GR125 test results of a 7404 Hex Inverter in a sample VHDL performance modeler on a Unix workstation. The VHDL code is simulated using the Mentor Graphics Corporation's Idea Station software, but should be portable to any VHDL simulator.
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard
Institute of Scientific and Technical Information of China (English)
Li Zhang; Don Xie; Di Wu
2006-01-01
The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.